intel_display.c 293.3 KB
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/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

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#include <linux/dmi.h>
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#include <linux/module.h>
#include <linux/input.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/vgaarb.h>
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#include <drm/drm_edid.h>
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include <drm/drm_dp_helper.h>
#include <drm/drm_crtc_helper.h>
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#include <linux/dma_remapping.h>
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bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
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static void intel_increase_pllclock(struct drm_crtc *crtc);
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static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
				struct intel_crtc_config *pipe_config);
static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
				    struct intel_crtc_config *pipe_config);

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static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
			  int x, int y, struct drm_framebuffer *old_fb);


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typedef struct {
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	int	min, max;
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} intel_range_t;

typedef struct {
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	int	dot_limit;
	int	p2_slow, p2_fast;
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} intel_p2_t;

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typedef struct intel_limit intel_limit_t;
struct intel_limit {
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	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
	intel_p2_t	    p2;
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};
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/* FDI */
#define IRONLAKE_FDI_FREQ		2700000 /* in kHz for mode->clock */

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int
intel_pch_rawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	WARN_ON(!HAS_PCH_SPLIT(dev));

	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
}

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static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev)
{
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	if (IS_GEN5(dev)) {
		struct drm_i915_private *dev_priv = dev->dev_private;
		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
	} else
		return 27;
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}

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static const intel_limit_t intel_limits_i8xx_dac = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 2, .max = 33 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 4, .p2_fast = 2 },
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};

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static const intel_limit_t intel_limits_i8xx_dvo = {
	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 2, .max = 33 },
	.p2 = { .dot_limit = 165000,
		.p2_slow = 4, .p2_fast = 4 },
};

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static const intel_limit_t intel_limits_i8xx_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 1, .max = 6 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 14, .p2_fast = 7 },
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};
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static const intel_limit_t intel_limits_i9xx_sdvo = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
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	.m1 = { .min = 8, .max = 18 },
	.m2 = { .min = 3, .max = 7 },
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	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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};

static const intel_limit_t intel_limits_i9xx_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
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	.m1 = { .min = 8, .max = 18 },
	.m2 = { .min = 3, .max = 7 },
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	.p = { .min = 7, .max = 98 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 7 },
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};

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static const intel_limit_t intel_limits_g4x_sdvo = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 1, .max = 3},
	.p2 = { .dot_limit = 270000,
		.p2_slow = 10,
		.p2_fast = 10
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	},
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};

static const intel_limit_t intel_limits_g4x_hdmi = {
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	.dot = { .min = 22000, .max = 400000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 16, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8},
	.p2 = { .dot_limit = 165000,
		.p2_slow = 10, .p2_fast = 5 },
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};

static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
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	.dot = { .min = 20000, .max = 115000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 14, .p2_fast = 14
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	},
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};

static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
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	.dot = { .min = 80000, .max = 224000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 14, .max = 42 },
	.p1 = { .min = 2, .max = 6 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 7, .p2_fast = 7
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	},
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};

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static const intel_limit_t intel_limits_pineview_sdvo = {
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	.dot = { .min = 20000, .max = 400000},
	.vco = { .min = 1700000, .max = 3500000 },
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	/* Pineview's Ncounter is a ring counter */
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	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
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	/* Pineview only has one combined m divider, which we treat as m2. */
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	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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};

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static const intel_limit_t intel_limits_pineview_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1700000, .max = 3500000 },
	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 7, .max = 112 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 14 },
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};

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/* Ironlake / Sandybridge
 *
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
 * the range value for them is (actual_value - 2).
 */
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static const intel_limit_t intel_limits_ironlake_dac = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 5 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 10, .p2_fast = 5 },
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};

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static const intel_limit_t intel_limits_ironlake_single_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 118 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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};

static const intel_limit_t intel_limits_ironlake_dual_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 56 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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};

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/* LVDS 100mhz refclk limits. */
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static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 2 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
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	.p1 = { .min = 2, .max = 8 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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};

static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 42 },
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	.p1 = { .min = 2, .max = 6 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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};

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static const intel_limit_t intel_limits_vlv_dac = {
	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 4000000, .max = 6000000 },
	.n = { .min = 1, .max = 7 },
	.m = { .min = 22, .max = 450 }, /* guess */
	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
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	.p1 = { .min = 1, .max = 3 },
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	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
};

static const intel_limit_t intel_limits_vlv_hdmi = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 4000000, .max = 6000000 },
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	.n = { .min = 1, .max = 7 },
	.m = { .min = 60, .max = 300 }, /* guess */
	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 2, .max = 3 },
	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
};

static const intel_limit_t intel_limits_vlv_dp = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 4000000, .max = 6000000 },
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	.n = { .min = 1, .max = 7 },
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	.m = { .min = 22, .max = 450 },
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	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
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	.p1 = { .min = 1, .max = 3 },
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	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
};

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static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
						int refclk)
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{
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	struct drm_device *dev = crtc->dev;
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	const intel_limit_t *limit;
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	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		if (intel_is_dual_link_lvds(dev)) {
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			if (refclk == 100000)
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				limit = &intel_limits_ironlake_dual_lvds_100m;
			else
				limit = &intel_limits_ironlake_dual_lvds;
		} else {
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			if (refclk == 100000)
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				limit = &intel_limits_ironlake_single_lvds_100m;
			else
				limit = &intel_limits_ironlake_single_lvds;
		}
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	} else
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		limit = &intel_limits_ironlake_dac;
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	return limit;
}

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static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	const intel_limit_t *limit;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		if (intel_is_dual_link_lvds(dev))
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			limit = &intel_limits_g4x_dual_channel_lvds;
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		else
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			limit = &intel_limits_g4x_single_channel_lvds;
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	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
		   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
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		limit = &intel_limits_g4x_hdmi;
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	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
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		limit = &intel_limits_g4x_sdvo;
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	} else /* The option is for other outputs */
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		limit = &intel_limits_i9xx_sdvo;
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	return limit;
}

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static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
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{
	struct drm_device *dev = crtc->dev;
	const intel_limit_t *limit;

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	if (HAS_PCH_SPLIT(dev))
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		limit = intel_ironlake_limit(crtc, refclk);
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	else if (IS_G4X(dev)) {
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		limit = intel_g4x_limit(crtc);
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	} else if (IS_PINEVIEW(dev)) {
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		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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			limit = &intel_limits_pineview_lvds;
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		else
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			limit = &intel_limits_pineview_sdvo;
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	} else if (IS_VALLEYVIEW(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
			limit = &intel_limits_vlv_dac;
		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
			limit = &intel_limits_vlv_hdmi;
		else
			limit = &intel_limits_vlv_dp;
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	} else if (!IS_GEN2(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
			limit = &intel_limits_i9xx_lvds;
		else
			limit = &intel_limits_i9xx_sdvo;
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	} else {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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			limit = &intel_limits_i8xx_lvds;
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		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
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			limit = &intel_limits_i8xx_dvo;
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		else
			limit = &intel_limits_i8xx_dac;
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	}
	return limit;
}

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/* m1 is reserved as 0 in Pineview, n is a ring counter */
static void pineview_clock(int refclk, intel_clock_t *clock)
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{
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	clock->m = clock->m2 + 2;
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / clock->n;
	clock->dot = clock->vco / clock->p;
}

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static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
{
	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
}

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static void i9xx_clock(int refclk, intel_clock_t *clock)
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{
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	clock->m = i9xx_dpll_compute_m(clock);
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	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / (clock->n + 2);
	clock->dot = clock->vco / clock->p;
}

/**
 * Returns whether any output on the specified pipe is of the specified type
 */
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bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
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{
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	struct drm_device *dev = crtc->dev;
	struct intel_encoder *encoder;

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	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->type == type)
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			return true;

	return false;
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}

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#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
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/**
 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */

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static bool intel_PLL_is_valid(struct drm_device *dev,
			       const intel_limit_t *limit,
			       const intel_clock_t *clock)
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{
	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
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		INTELPllInvalid("p1 out of range\n");
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	if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
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		INTELPllInvalid("p out of range\n");
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	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
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		INTELPllInvalid("m2 out of range\n");
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	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
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		INTELPllInvalid("m1 out of range\n");
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	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
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		INTELPllInvalid("m1 <= m2\n");
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	if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
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		INTELPllInvalid("m out of range\n");
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	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
497
		INTELPllInvalid("n out of range\n");
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	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
499
		INTELPllInvalid("vco out of range\n");
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	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
	 * connector, etc., rather than just a single range.
	 */
	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
504
		INTELPllInvalid("dot out of range\n");
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	return true;
}

509
static bool
510
i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
511 512
		    int target, int refclk, intel_clock_t *match_clock,
		    intel_clock_t *best_clock)
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{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;
	int err = target;

518
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		/*
520 521 522
		 * For LVDS just rely on its current settings for dual-channel.
		 * We haven't figured out how to reliably set up different
		 * single/dual channel state, if we even can.
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523
		 */
524
		if (intel_is_dual_link_lvds(dev))
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			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

535
	memset(best_clock, 0, sizeof(*best_clock));
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537 538 539 540
	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
	     clock.m1++) {
		for (clock.m2 = limit->m2.min;
		     clock.m2 <= limit->m2.max; clock.m2++) {
541
			if (clock.m2 >= clock.m1)
542 543 544 545 546
				break;
			for (clock.n = limit->n.min;
			     clock.n <= limit->n.max; clock.n++) {
				for (clock.p1 = limit->p1.min;
					clock.p1 <= limit->p1.max; clock.p1++) {
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					int this_err;

549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570
					i9xx_clock(refclk, &clock);
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
						continue;
					if (match_clock &&
					    clock.p != match_clock->p)
						continue;

					this_err = abs(clock.dot - target);
					if (this_err < err) {
						*best_clock = clock;
						err = this_err;
					}
				}
			}
		}
	}

	return (err != target);
}

static bool
571 572 573
pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
		   int target, int refclk, intel_clock_t *match_clock,
		   intel_clock_t *best_clock)
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{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;
	int err = target;

579
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		/*
581 582 583
		 * For LVDS just rely on its current settings for dual-channel.
		 * We haven't figured out how to reliably set up different
		 * single/dual channel state, if we even can.
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584
		 */
585
		if (intel_is_dual_link_lvds(dev))
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			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

596
	memset(best_clock, 0, sizeof(*best_clock));
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598 599 600 601 602 603 604 605
	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
	     clock.m1++) {
		for (clock.m2 = limit->m2.min;
		     clock.m2 <= limit->m2.max; clock.m2++) {
			for (clock.n = limit->n.min;
			     clock.n <= limit->n.max; clock.n++) {
				for (clock.p1 = limit->p1.min;
					clock.p1 <= limit->p1.max; clock.p1++) {
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					int this_err;

608
					pineview_clock(refclk, &clock);
609 610
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
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						continue;
612 613 614
					if (match_clock &&
					    clock.p != match_clock->p)
						continue;
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					this_err = abs(clock.dot - target);
					if (this_err < err) {
						*best_clock = clock;
						err = this_err;
					}
				}
			}
		}
	}

	return (err != target);
}

629
static bool
630 631 632
g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
		   int target, int refclk, intel_clock_t *match_clock,
		   intel_clock_t *best_clock)
633 634 635 636 637
{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;
	int max_n;
	bool found;
638 639
	/* approximately equals target * 0.00585 */
	int err_most = (target >> 8) + (target >> 9);
640 641 642
	found = false;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643
		if (intel_is_dual_link_lvds(dev))
644 645 646 647 648 649 650 651 652 653 654 655
			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

	memset(best_clock, 0, sizeof(*best_clock));
	max_n = limit->n.max;
656
	/* based on hardware requirement, prefer smaller n to precision */
657
	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
658
		/* based on hardware requirement, prefere larger m1,m2 */
659 660 661 662 663 664 665 666
		for (clock.m1 = limit->m1.max;
		     clock.m1 >= limit->m1.min; clock.m1--) {
			for (clock.m2 = limit->m2.max;
			     clock.m2 >= limit->m2.min; clock.m2--) {
				for (clock.p1 = limit->p1.max;
				     clock.p1 >= limit->p1.min; clock.p1--) {
					int this_err;

667
					i9xx_clock(refclk, &clock);
668 669
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
670
						continue;
671 672

					this_err = abs(clock.dot - target);
673 674 675 676 677 678 679 680 681 682
					if (this_err < err_most) {
						*best_clock = clock;
						err_most = this_err;
						max_n = clock.n;
						found = true;
					}
				}
			}
		}
	}
683 684 685
	return found;
}

686
static bool
687 688 689
vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
		   int target, int refclk, intel_clock_t *match_clock,
		   intel_clock_t *best_clock)
690 691 692
{
	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
	u32 m, n, fastclk;
693
	u32 updrate, minupdate, p;
694 695 696
	unsigned long bestppm, ppm, absppm;
	int dotclk, flag;

697
	flag = 0;
698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752
	dotclk = target * 1000;
	bestppm = 1000000;
	ppm = absppm = 0;
	fastclk = dotclk / (2*100);
	updrate = 0;
	minupdate = 19200;
	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
	bestm1 = bestm2 = bestp1 = bestp2 = 0;

	/* based on hardware requirement, prefer smaller n to precision */
	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
		updrate = refclk / n;
		for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
			for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
				if (p2 > 10)
					p2 = p2 - 1;
				p = p1 * p2;
				/* based on hardware requirement, prefer bigger m1,m2 values */
				for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
					m2 = (((2*(fastclk * p * n / m1 )) +
					       refclk) / (2*refclk));
					m = m1 * m2;
					vco = updrate * m;
					if (vco >= limit->vco.min && vco < limit->vco.max) {
						ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
						absppm = (ppm > 0) ? ppm : (-ppm);
						if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
							bestppm = 0;
							flag = 1;
						}
						if (absppm < bestppm - 10) {
							bestppm = absppm;
							flag = 1;
						}
						if (flag) {
							bestn = n;
							bestm1 = m1;
							bestm2 = m2;
							bestp1 = p1;
							bestp2 = p2;
							flag = 0;
						}
					}
				}
			}
		}
	}
	best_clock->n = bestn;
	best_clock->m1 = bestm1;
	best_clock->m2 = bestm2;
	best_clock->p1 = bestp1;
	best_clock->p2 = bestp2;

	return true;
}
753

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enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
					     enum pipe pipe)
{
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

760
	return intel_crtc->config.cpu_transcoder;
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}

763 764 765 766 767 768 769 770 771 772 773
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 frame, frame_reg = PIPEFRAME(pipe);

	frame = I915_READ(frame_reg);

	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		DRM_DEBUG_KMS("vblank wait timed out\n");
}

774 775 776 777 778 779 780 781 782
/**
 * intel_wait_for_vblank - wait for vblank on a given pipe
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * Wait for vblank to occur on a given pipe.  Needed for various bits of
 * mode setting code.
 */
void intel_wait_for_vblank(struct drm_device *dev, int pipe)
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{
784
	struct drm_i915_private *dev_priv = dev->dev_private;
785
	int pipestat_reg = PIPESTAT(pipe);
786

787 788 789 790 791
	if (INTEL_INFO(dev)->gen >= 5) {
		ironlake_wait_for_vblank(dev, pipe);
		return;
	}

792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807
	/* Clear existing vblank status. Note this will clear any other
	 * sticky status fields as well.
	 *
	 * This races with i915_driver_irq_handler() with the result
	 * that either function could miss a vblank event.  Here it is not
	 * fatal, as we will either wait upon the next vblank interrupt or
	 * timeout.  Generally speaking intel_wait_for_vblank() is only
	 * called during modeset at which time the GPU should be idle and
	 * should *not* be performing page flips and thus not waiting on
	 * vblanks...
	 * Currently, the result of us stealing a vblank from the irq
	 * handler is that a single frame will be skipped during swapbuffers.
	 */
	I915_WRITE(pipestat_reg,
		   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

808
	/* Wait for vblank interrupt bit to set */
809 810 811
	if (wait_for(I915_READ(pipestat_reg) &
		     PIPE_VBLANK_INTERRUPT_STATUS,
		     50))
812 813 814
		DRM_DEBUG_KMS("vblank wait timed out\n");
}

815 816
/*
 * intel_wait_for_pipe_off - wait for pipe to turn off
817 818 819 820 821 822 823
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * After disabling a pipe, we can't wait for vblank in the usual way,
 * spinning on the vblank interrupt status bit, since we won't actually
 * see an interrupt when the pipe is disabled.
 *
824 825 826 827 828 829
 * On Gen4 and above:
 *   wait for the pipe register state bit to turn off
 *
 * Otherwise:
 *   wait for the display line value to settle (it usually
 *   ends up stopping at the start of the next frame).
830
 *
831
 */
832
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
833 834
{
	struct drm_i915_private *dev_priv = dev->dev_private;
835 836
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
837 838

	if (INTEL_INFO(dev)->gen >= 4) {
839
		int reg = PIPECONF(cpu_transcoder);
840 841

		/* Wait for the Pipe State to go off */
842 843
		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
			     100))
844
			WARN(1, "pipe_off wait timed out\n");
845
	} else {
846
		u32 last_line, line_mask;
847
		int reg = PIPEDSL(pipe);
848 849
		unsigned long timeout = jiffies + msecs_to_jiffies(100);

850 851 852 853 854
		if (IS_GEN2(dev))
			line_mask = DSL_LINEMASK_GEN2;
		else
			line_mask = DSL_LINEMASK_GEN3;

855 856
		/* Wait for the display line to settle */
		do {
857
			last_line = I915_READ(reg) & line_mask;
858
			mdelay(5);
859
		} while (((I915_READ(reg) & line_mask) != last_line) &&
860 861
			 time_after(timeout, jiffies));
		if (time_after(jiffies, timeout))
862
			WARN(1, "pipe_off wait timed out\n");
863
	}
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}

866 867 868 869 870 871 872 873 874 875 876 877
/*
 * ibx_digital_port_connected - is the specified port connected?
 * @dev_priv: i915 private structure
 * @port: the port to test
 *
 * Returns true if @port is connected, false otherwise.
 */
bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
				struct intel_digital_port *port)
{
	u32 bit;

878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905
	if (HAS_PCH_IBX(dev_priv->dev)) {
		switch(port->port) {
		case PORT_B:
			bit = SDE_PORTB_HOTPLUG;
			break;
		case PORT_C:
			bit = SDE_PORTC_HOTPLUG;
			break;
		case PORT_D:
			bit = SDE_PORTD_HOTPLUG;
			break;
		default:
			return true;
		}
	} else {
		switch(port->port) {
		case PORT_B:
			bit = SDE_PORTB_HOTPLUG_CPT;
			break;
		case PORT_C:
			bit = SDE_PORTC_HOTPLUG_CPT;
			break;
		case PORT_D:
			bit = SDE_PORTD_HOTPLUG_CPT;
			break;
		default:
			return true;
		}
906 907 908 909 910
	}

	return I915_READ(SDEISR) & bit;
}

911 912 913 914 915 916
static const char *state_string(bool enabled)
{
	return enabled ? "on" : "off";
}

/* Only for pre-ILK configs */
917 918
void assert_pll(struct drm_i915_private *dev_priv,
		enum pipe pipe, bool state)
919 920 921 922 923 924 925 926 927 928 929 930 931
{
	int reg;
	u32 val;
	bool cur_state;

	reg = DPLL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & DPLL_VCO_ENABLE);
	WARN(cur_state != state,
	     "PLL state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}

932
struct intel_shared_dpll *
933 934 935 936
intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;

937
	if (crtc->config.shared_dpll < 0)
938 939
		return NULL;

940
	return &dev_priv->shared_dplls[crtc->config.shared_dpll];
941 942
}

943
/* For ILK+ */
944 945 946
void assert_shared_dpll(struct drm_i915_private *dev_priv,
			struct intel_shared_dpll *pll,
			bool state)
947 948
{
	bool cur_state;
949
	struct intel_dpll_hw_state hw_state;
950

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	if (HAS_PCH_LPT(dev_priv->dev)) {
		DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		return;
	}

956
	if (WARN (!pll,
957
		  "asserting DPLL %s with no DPLL\n", state_string(state)))
958 959
		return;

960
	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
961
	WARN(cur_state != state,
962 963
	     "%s assertion failure (expected %s, current %s)\n",
	     pll->name, state_string(state), state_string(cur_state));
964 965 966 967 968 969 970 971
}

static void assert_fdi_tx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;
972 973
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
974

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	if (HAS_DDI(dev_priv->dev)) {
		/* DDI does not have a specific FDI_TX register */
977
		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
978
		val = I915_READ(reg);
979
		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
980 981 982 983 984
	} else {
		reg = FDI_TX_CTL(pipe);
		val = I915_READ(reg);
		cur_state = !!(val & FDI_TX_ENABLE);
	}
985 986 987 988 989 990 991 992 993 994 995 996 997 998
	WARN(cur_state != state,
	     "FDI TX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)

static void assert_fdi_rx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

999 1000 1001
	reg = FDI_RX_CTL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & FDI_RX_ENABLE);
1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018
	WARN(cur_state != state,
	     "FDI RX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)

static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

	/* ILK FDI PLL is always enabled */
	if (dev_priv->info->gen == 5)
		return;

1019
	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
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	if (HAS_DDI(dev_priv->dev))
1021 1022
		return;

1023 1024 1025 1026 1027
	reg = FDI_TX_CTL(pipe);
	val = I915_READ(reg);
	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
}

1028 1029
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
		       enum pipe pipe, bool state)
1030 1031 1032
{
	int reg;
	u32 val;
1033
	bool cur_state;
1034 1035 1036

	reg = FDI_RX_CTL(pipe);
	val = I915_READ(reg);
1037 1038 1039 1040
	cur_state = !!(val & FDI_RX_PLL_ENABLE);
	WARN(cur_state != state,
	     "FDI RX PLL assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
1041 1042
}

1043 1044 1045 1046 1047 1048
static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
				  enum pipe pipe)
{
	int pp_reg, lvds_reg;
	u32 val;
	enum pipe panel_pipe = PIPE_A;
1049
	bool locked = true;
1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068

	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		pp_reg = PCH_PP_CONTROL;
		lvds_reg = PCH_LVDS;
	} else {
		pp_reg = PP_CONTROL;
		lvds_reg = LVDS;
	}

	val = I915_READ(pp_reg);
	if (!(val & PANEL_POWER_ON) ||
	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		locked = false;

	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		panel_pipe = PIPE_B;

	WARN(panel_pipe == pipe && locked,
	     "panel assertion failure, pipe %c regs locked\n",
1069
	     pipe_name(pipe));
1070 1071
}

1072 1073
void assert_pipe(struct drm_i915_private *dev_priv,
		 enum pipe pipe, bool state)
1074 1075 1076
{
	int reg;
	u32 val;
1077
	bool cur_state;
1078 1079
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
1080

1081 1082 1083 1084
	/* if we need the pipe A quirk it must be always on */
	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		state = true;

1085 1086
	if (!intel_display_power_enabled(dev_priv->dev,
				POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1087 1088 1089 1090 1091 1092 1093
		cur_state = false;
	} else {
		reg = PIPECONF(cpu_transcoder);
		val = I915_READ(reg);
		cur_state = !!(val & PIPECONF_ENABLE);
	}

1094 1095
	WARN(cur_state != state,
	     "pipe %c assertion failure (expected %s, current %s)\n",
1096
	     pipe_name(pipe), state_string(state), state_string(cur_state));
1097 1098
}

1099 1100
static void assert_plane(struct drm_i915_private *dev_priv,
			 enum plane plane, bool state)
1101 1102 1103
{
	int reg;
	u32 val;
1104
	bool cur_state;
1105 1106 1107

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1108 1109 1110 1111
	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
	WARN(cur_state != state,
	     "plane %c assertion failure (expected %s, current %s)\n",
	     plane_name(plane), state_string(state), state_string(cur_state));
1112 1113
}

1114 1115 1116
#define assert_plane_enabled(d, p) assert_plane(d, p, true)
#define assert_plane_disabled(d, p) assert_plane(d, p, false)

1117 1118 1119
static void assert_planes_disabled(struct drm_i915_private *dev_priv,
				   enum pipe pipe)
{
1120
	struct drm_device *dev = dev_priv->dev;
1121 1122 1123 1124
	int reg, i;
	u32 val;
	int cur_pipe;

1125 1126
	/* Primary planes are fixed to pipes on gen4+ */
	if (INTEL_INFO(dev)->gen >= 4) {
1127 1128 1129 1130 1131
		reg = DSPCNTR(pipe);
		val = I915_READ(reg);
		WARN((val & DISPLAY_PLANE_ENABLE),
		     "plane %c assertion failure, should be disabled but not\n",
		     plane_name(pipe));
1132
		return;
1133
	}
1134

1135
	/* Need to check both planes against the pipe */
1136
	for_each_pipe(i) {
1137 1138 1139 1140 1141
		reg = DSPCNTR(i);
		val = I915_READ(reg);
		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
			DISPPLANE_SEL_PIPE_SHIFT;
		WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1142 1143
		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
		     plane_name(i), pipe_name(pipe));
1144 1145 1146
	}
}

1147 1148 1149
static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
				    enum pipe pipe)
{
1150
	struct drm_device *dev = dev_priv->dev;
1151 1152 1153
	int reg, i;
	u32 val;

1154 1155 1156 1157 1158 1159 1160 1161 1162 1163
	if (IS_VALLEYVIEW(dev)) {
		for (i = 0; i < dev_priv->num_plane; i++) {
			reg = SPCNTR(pipe, i);
			val = I915_READ(reg);
			WARN((val & SP_ENABLE),
			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
			     sprite_name(pipe, i), pipe_name(pipe));
		}
	} else if (INTEL_INFO(dev)->gen >= 7) {
		reg = SPRCTL(pipe);
1164
		val = I915_READ(reg);
1165
		WARN((val & SPRITE_ENABLE),
1166
		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1167 1168 1169
		     plane_name(pipe), pipe_name(pipe));
	} else if (INTEL_INFO(dev)->gen >= 5) {
		reg = DVSCNTR(pipe);
1170
		val = I915_READ(reg);
1171
		WARN((val & DVS_ENABLE),
1172
		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1173
		     plane_name(pipe), pipe_name(pipe));
1174 1175 1176
	}
}

1177 1178 1179 1180 1181
static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
{
	u32 val;
	bool enabled;

E
Eugeni Dodonov 已提交
1182 1183 1184 1185 1186
	if (HAS_PCH_LPT(dev_priv->dev)) {
		DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		return;
	}

1187 1188 1189 1190 1191 1192
	val = I915_READ(PCH_DREF_CONTROL);
	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
			    DREF_SUPERSPREAD_SOURCE_MASK));
	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
}

1193 1194
static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
					   enum pipe pipe)
1195 1196 1197 1198 1199
{
	int reg;
	u32 val;
	bool enabled;

1200
	reg = PCH_TRANSCONF(pipe);
1201 1202
	val = I915_READ(reg);
	enabled = !!(val & TRANS_ENABLE);
1203 1204 1205
	WARN(enabled,
	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
	     pipe_name(pipe));
1206 1207
}

1208 1209
static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
			    enum pipe pipe, u32 port_sel, u32 val)
1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225
{
	if ((val & DP_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
			return false;
	} else {
		if ((val & DP_PIPE_MASK) != (pipe << 30))
			return false;
	}
	return true;
}

1226 1227 1228
static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
1229
	if ((val & SDVO_ENABLE) == 0)
1230 1231 1232
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
1233
		if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1234 1235
			return false;
	} else {
1236
		if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272
			return false;
	}
	return true;
}

static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & LVDS_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
			return false;
	}
	return true;
}

static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & ADPA_DAC_ENABLE) == 0)
		return false;
	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
			return false;
	}
	return true;
}

1273
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1274
				   enum pipe pipe, int reg, u32 port_sel)
1275
{
1276
	u32 val = I915_READ(reg);
1277
	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1278
	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1279
	     reg, pipe_name(pipe));
1280

1281 1282
	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
	     && (val & DP_PIPEB_SELECT),
1283
	     "IBX PCH dp port still using transcoder B\n");
1284 1285 1286 1287 1288
}

static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
				     enum pipe pipe, int reg)
{
1289
	u32 val = I915_READ(reg);
1290
	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1291
	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1292
	     reg, pipe_name(pipe));
1293

1294
	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1295
	     && (val & SDVO_PIPE_B_SELECT),
1296
	     "IBX PCH hdmi port still using transcoder B\n");
1297 1298 1299 1300 1301 1302 1303 1304
}

static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

1305 1306 1307
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1308 1309 1310

	reg = PCH_ADPA;
	val = I915_READ(reg);
1311
	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1312
	     "PCH VGA enabled on transcoder %c, should be disabled\n",
1313
	     pipe_name(pipe));
1314 1315 1316

	reg = PCH_LVDS;
	val = I915_READ(reg);
1317
	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1318
	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
1319
	     pipe_name(pipe));
1320

1321 1322 1323
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1324 1325
}

1326
static void vlv_enable_pll(struct intel_crtc *crtc)
1327
{
1328 1329 1330 1331
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int reg = DPLL(crtc->pipe);
	u32 dpll = crtc->config.dpll_hw_state.dpll;
1332

1333
	assert_pipe_disabled(dev_priv, crtc->pipe);
1334 1335 1336 1337 1338 1339

	/* No really, not for ILK+ */
	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));

	/* PLL is protected by panel, make sure we can write it */
	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1340
		assert_panel_unlocked(dev_priv, crtc->pipe);
1341

1342 1343 1344 1345 1346 1347 1348 1349 1350
	I915_WRITE(reg, dpll);
	POSTING_READ(reg);
	udelay(150);

	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);

	I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
	POSTING_READ(DPLL_MD(crtc->pipe));
1351 1352

	/* We do this three times for luck */
1353
	I915_WRITE(reg, dpll);
1354 1355
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
1356
	I915_WRITE(reg, dpll);
1357 1358
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
1359
	I915_WRITE(reg, dpll);
1360 1361 1362 1363
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
}

1364
static void i9xx_enable_pll(struct intel_crtc *crtc)
1365
{
1366 1367 1368 1369
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int reg = DPLL(crtc->pipe);
	u32 dpll = crtc->config.dpll_hw_state.dpll;
1370

1371
	assert_pipe_disabled(dev_priv, crtc->pipe);
1372

1373
	/* No really, not for ILK+ */
1374
	BUG_ON(dev_priv->info->gen >= 5);
1375 1376

	/* PLL is protected by panel, make sure we can write it */
1377 1378
	if (IS_MOBILE(dev) && !IS_I830(dev))
		assert_panel_unlocked(dev_priv, crtc->pipe);
1379

1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396
	I915_WRITE(reg, dpll);

	/* Wait for the clocks to stabilize. */
	POSTING_READ(reg);
	udelay(150);

	if (INTEL_INFO(dev)->gen >= 4) {
		I915_WRITE(DPLL_MD(crtc->pipe),
			   crtc->config.dpll_hw_state.dpll_md);
	} else {
		/* The pixel multiplier can only be updated once the
		 * DPLL is enabled and the clocks are stable.
		 *
		 * So write it again.
		 */
		I915_WRITE(reg, dpll);
	}
1397 1398

	/* We do this three times for luck */
1399
	I915_WRITE(reg, dpll);
1400 1401
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
1402
	I915_WRITE(reg, dpll);
1403 1404
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
1405
	I915_WRITE(reg, dpll);
1406 1407 1408 1409 1410
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
}

/**
1411
 * i9xx_disable_pll - disable a PLL
1412 1413 1414 1415 1416 1417 1418
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to disable
 *
 * Disable the PLL for @pipe, making sure the pipe is off first.
 *
 * Note!  This is for pre-ILK only.
 */
1419
static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1420 1421 1422 1423 1424 1425 1426 1427
{
	/* Don't disable pipe A or pipe A PLLs if needed */
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		return;

	/* Make sure the pipe isn't still relying on us */
	assert_pipe_disabled(dev_priv, pipe);

1428 1429
	I915_WRITE(DPLL(pipe), 0);
	POSTING_READ(DPLL(pipe));
1430 1431
}

1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445
void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
{
	u32 port_mask;

	if (!port)
		port_mask = DPLL_PORTB_READY_MASK;
	else
		port_mask = DPLL_PORTC_READY_MASK;

	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
		WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
		     'B' + port, I915_READ(DPLL(0)));
}

1446
/**
D
Daniel Vetter 已提交
1447
 * ironlake_enable_shared_dpll - enable PCH PLL
1448 1449 1450 1451 1452 1453
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * The PCH PLL needs to be enabled before the PCH transcoder, since it
 * drives the transcoder clock.
 */
1454
static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1455
{
1456 1457
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1458

1459
	/* PCH PLLs only available on ILK, SNB and IVB */
1460
	BUG_ON(dev_priv->info->gen < 5);
1461
	if (WARN_ON(pll == NULL))
1462 1463 1464 1465
		return;

	if (WARN_ON(pll->refcount == 0))
		return;
1466

1467 1468
	DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
		      pll->name, pll->active, pll->on,
1469
		      crtc->base.base.id);
1470

1471 1472
	if (pll->active++) {
		WARN_ON(!pll->on);
1473
		assert_shared_dpll_enabled(dev_priv, pll);
1474 1475
		return;
	}
1476
	WARN_ON(pll->on);
1477

1478
	DRM_DEBUG_KMS("enabling %s\n", pll->name);
1479
	pll->enable(dev_priv, pll);
1480
	pll->on = true;
1481 1482
}

1483
static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1484
{
1485 1486
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1487

1488 1489
	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);
1490
	if (WARN_ON(pll == NULL))
1491
	       return;
1492

1493 1494
	if (WARN_ON(pll->refcount == 0))
		return;
1495

1496 1497
	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
		      pll->name, pll->active, pll->on,
1498
		      crtc->base.base.id);
1499

1500
	if (WARN_ON(pll->active == 0)) {
1501
		assert_shared_dpll_disabled(dev_priv, pll);
1502 1503 1504
		return;
	}

1505
	assert_shared_dpll_enabled(dev_priv, pll);
1506
	WARN_ON(!pll->on);
1507
	if (--pll->active)
1508
		return;
1509

1510
	DRM_DEBUG_KMS("disabling %s\n", pll->name);
1511
	pll->disable(dev_priv, pll);
1512
	pll->on = false;
1513 1514
}

1515 1516
static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
					   enum pipe pipe)
1517
{
1518
	struct drm_device *dev = dev_priv->dev;
1519
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1520
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1521
	uint32_t reg, val, pipeconf_val;
1522 1523 1524 1525 1526

	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);

	/* Make sure PCH DPLL is enabled */
D
Daniel Vetter 已提交
1527
	assert_shared_dpll_enabled(dev_priv,
1528
				   intel_crtc_to_shared_dpll(intel_crtc));
1529 1530 1531 1532 1533

	/* FDI must be feeding us bits for PCH ports */
	assert_fdi_tx_enabled(dev_priv, pipe);
	assert_fdi_rx_enabled(dev_priv, pipe);

1534 1535 1536 1537 1538 1539 1540
	if (HAS_PCH_CPT(dev)) {
		/* Workaround: Set the timing override bit before enabling the
		 * pch transcoder. */
		reg = TRANS_CHICKEN2(pipe);
		val = I915_READ(reg);
		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
		I915_WRITE(reg, val);
1541
	}
1542

1543
	reg = PCH_TRANSCONF(pipe);
1544
	val = I915_READ(reg);
1545
	pipeconf_val = I915_READ(PIPECONF(pipe));
1546 1547 1548 1549 1550 1551

	if (HAS_PCH_IBX(dev_priv->dev)) {
		/*
		 * make the BPC in transcoder be consistent with
		 * that in pipeconf reg.
		 */
1552 1553
		val &= ~PIPECONF_BPC_MASK;
		val |= pipeconf_val & PIPECONF_BPC_MASK;
1554
	}
1555 1556 1557

	val &= ~TRANS_INTERLACE_MASK;
	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1558 1559 1560 1561 1562
		if (HAS_PCH_IBX(dev_priv->dev) &&
		    intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
			val |= TRANS_LEGACY_INTERLACED_ILK;
		else
			val |= TRANS_INTERLACED;
1563 1564 1565
	else
		val |= TRANS_PROGRESSIVE;

1566 1567
	I915_WRITE(reg, val | TRANS_ENABLE);
	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1568
		DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1569 1570
}

1571
static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1572
				      enum transcoder cpu_transcoder)
1573
{
1574 1575 1576 1577 1578 1579
	u32 val, pipeconf_val;

	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);

	/* FDI must be feeding us bits for PCH ports */
D
Daniel Vetter 已提交
1580
	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1581
	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1582

1583 1584
	/* Workaround: set timing override bit. */
	val = I915_READ(_TRANSA_CHICKEN2);
1585
	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1586 1587
	I915_WRITE(_TRANSA_CHICKEN2, val);

1588
	val = TRANS_ENABLE;
1589
	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1590

1591 1592
	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
	    PIPECONF_INTERLACED_ILK)
1593
		val |= TRANS_INTERLACED;
1594 1595 1596
	else
		val |= TRANS_PROGRESSIVE;

1597 1598
	I915_WRITE(LPT_TRANSCONF, val);
	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1599
		DRM_ERROR("Failed to enable PCH transcoder\n");
1600 1601
}

1602 1603
static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
					    enum pipe pipe)
1604
{
1605 1606
	struct drm_device *dev = dev_priv->dev;
	uint32_t reg, val;
1607 1608 1609 1610 1611

	/* FDI relies on the transcoder */
	assert_fdi_tx_disabled(dev_priv, pipe);
	assert_fdi_rx_disabled(dev_priv, pipe);

1612 1613 1614
	/* Ports must be off as well */
	assert_pch_ports_disabled(dev_priv, pipe);

1615
	reg = PCH_TRANSCONF(pipe);
1616 1617 1618 1619 1620
	val = I915_READ(reg);
	val &= ~TRANS_ENABLE;
	I915_WRITE(reg, val);
	/* wait for PCH transcoder off, transcoder state */
	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1621
		DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1622 1623 1624 1625 1626 1627 1628 1629

	if (!HAS_PCH_IBX(dev)) {
		/* Workaround: Clear the timing override chicken bit again. */
		reg = TRANS_CHICKEN2(pipe);
		val = I915_READ(reg);
		val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		I915_WRITE(reg, val);
	}
1630 1631
}

1632
static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1633 1634 1635
{
	u32 val;

1636
	val = I915_READ(LPT_TRANSCONF);
1637
	val &= ~TRANS_ENABLE;
1638
	I915_WRITE(LPT_TRANSCONF, val);
1639
	/* wait for PCH transcoder off, transcoder state */
1640
	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1641
		DRM_ERROR("Failed to disable PCH transcoder\n");
1642 1643 1644

	/* Workaround: clear timing override bit. */
	val = I915_READ(_TRANSA_CHICKEN2);
1645
	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1646
	I915_WRITE(_TRANSA_CHICKEN2, val);
1647 1648
}

1649
/**
1650
 * intel_enable_pipe - enable a pipe, asserting requirements
1651 1652
 * @dev_priv: i915 private structure
 * @pipe: pipe to enable
1653
 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1654 1655 1656 1657 1658 1659 1660 1661 1662
 *
 * Enable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe is actually running (i.e. first vblank) before
 * returning.
 */
1663 1664
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
			      bool pch_port)
1665
{
1666 1667
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
D
Daniel Vetter 已提交
1668
	enum pipe pch_transcoder;
1669 1670 1671
	int reg;
	u32 val;

1672 1673 1674
	assert_planes_disabled(dev_priv, pipe);
	assert_sprites_disabled(dev_priv, pipe);

1675
	if (HAS_PCH_LPT(dev_priv->dev))
1676 1677 1678 1679
		pch_transcoder = TRANSCODER_A;
	else
		pch_transcoder = pipe;

1680 1681 1682 1683 1684 1685 1686
	/*
	 * A pipe without a PLL won't actually be able to drive bits from
	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
	 * need the check.
	 */
	if (!HAS_PCH_SPLIT(dev_priv->dev))
		assert_pll_enabled(dev_priv, pipe);
1687 1688 1689
	else {
		if (pch_port) {
			/* if driving the PCH, we need FDI enabled */
1690
			assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
D
Daniel Vetter 已提交
1691 1692
			assert_fdi_tx_pll_enabled(dev_priv,
						  (enum pipe) cpu_transcoder);
1693 1694 1695
		}
		/* FIXME: assert CPU port conditions for SNB+ */
	}
1696

1697
	reg = PIPECONF(cpu_transcoder);
1698
	val = I915_READ(reg);
1699 1700 1701 1702
	if (val & PIPECONF_ENABLE)
		return;

	I915_WRITE(reg, val | PIPECONF_ENABLE);
1703 1704 1705 1706
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
1707
 * intel_disable_pipe - disable a pipe, asserting requirements
1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720
 * @dev_priv: i915 private structure
 * @pipe: pipe to disable
 *
 * Disable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe has shut down before returning.
 */
static void intel_disable_pipe(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
1721 1722
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
1723 1724 1725 1726 1727 1728 1729 1730
	int reg;
	u32 val;

	/*
	 * Make sure planes won't keep trying to pump pixels to us,
	 * or we might hang the display.
	 */
	assert_planes_disabled(dev_priv, pipe);
1731
	assert_sprites_disabled(dev_priv, pipe);
1732 1733 1734 1735 1736

	/* Don't disable pipe A or pipe A PLLs if needed */
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		return;

1737
	reg = PIPECONF(cpu_transcoder);
1738
	val = I915_READ(reg);
1739 1740 1741 1742
	if ((val & PIPECONF_ENABLE) == 0)
		return;

	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1743 1744 1745
	intel_wait_for_pipe_off(dev_priv->dev, pipe);
}

1746 1747 1748 1749
/*
 * Plane regs are double buffered, going from enabled->disabled needs a
 * trigger in order to latch.  The display address reg provides this.
 */
1750
void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1751 1752
				      enum plane plane)
{
1753 1754 1755 1756
	if (dev_priv->info->gen >= 4)
		I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
	else
		I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1757 1758
}

1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777
/**
 * intel_enable_plane - enable a display plane on a given pipe
 * @dev_priv: i915 private structure
 * @plane: plane to enable
 * @pipe: pipe being fed
 *
 * Enable @plane on @pipe, making sure that @pipe is running first.
 */
static void intel_enable_plane(struct drm_i915_private *dev_priv,
			       enum plane plane, enum pipe pipe)
{
	int reg;
	u32 val;

	/* If the pipe isn't enabled, we can't pump pixels and may hang */
	assert_pipe_enabled(dev_priv, pipe);

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1778 1779 1780 1781
	if (val & DISPLAY_PLANE_ENABLE)
		return;

	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1782
	intel_flush_display_plane(dev_priv, plane);
1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
 * intel_disable_plane - disable a display plane
 * @dev_priv: i915 private structure
 * @plane: plane to disable
 * @pipe: pipe consuming the data
 *
 * Disable @plane; should be an independent operation.
 */
static void intel_disable_plane(struct drm_i915_private *dev_priv,
				enum plane plane, enum pipe pipe)
{
	int reg;
	u32 val;

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1802 1803 1804 1805
	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		return;

	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1806 1807 1808 1809
	intel_flush_display_plane(dev_priv, plane);
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

1810 1811 1812 1813 1814 1815 1816 1817 1818
static bool need_vtd_wa(struct drm_device *dev)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

1819
int
1820
intel_pin_and_fence_fb_obj(struct drm_device *dev,
1821
			   struct drm_i915_gem_object *obj,
1822
			   struct intel_ring_buffer *pipelined)
1823
{
1824
	struct drm_i915_private *dev_priv = dev->dev_private;
1825 1826 1827
	u32 alignment;
	int ret;

1828
	switch (obj->tiling_mode) {
1829
	case I915_TILING_NONE:
1830 1831
		if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
			alignment = 128 * 1024;
1832
		else if (INTEL_INFO(dev)->gen >= 4)
1833 1834 1835
			alignment = 4 * 1024;
		else
			alignment = 64 * 1024;
1836 1837 1838 1839 1840 1841
		break;
	case I915_TILING_X:
		/* pin() will align the object as required by fence */
		alignment = 0;
		break;
	case I915_TILING_Y:
1842 1843 1844 1845
		/* Despite that we check this in framebuffer_init userspace can
		 * screw us over and change the tiling after the fact. Only
		 * pinned buffers can't change their tiling. */
		DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1846 1847 1848 1849 1850
		return -EINVAL;
	default:
		BUG();
	}

1851 1852 1853 1854 1855 1856 1857 1858
	/* Note that the w/a also requires 64 PTE of padding following the
	 * bo. We currently fill all unused PTE with the shadow page and so
	 * we should always have valid PTE following the scanout preventing
	 * the VT-d warning.
	 */
	if (need_vtd_wa(dev) && alignment < 256 * 1024)
		alignment = 256 * 1024;

1859
	dev_priv->mm.interruptible = false;
1860
	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1861
	if (ret)
1862
		goto err_interruptible;
1863 1864 1865 1866 1867 1868

	/* Install a fence for tiled scan-out. Pre-i965 always needs a
	 * fence, whereas 965+ only requires a fence if using
	 * framebuffer compression.  For simplicity, we always install
	 * a fence as the cost is not that onerous.
	 */
1869
	ret = i915_gem_object_get_fence(obj);
1870 1871
	if (ret)
		goto err_unpin;
1872

1873
	i915_gem_object_pin_fence(obj);
1874

1875
	dev_priv->mm.interruptible = true;
1876
	return 0;
1877 1878

err_unpin:
1879
	i915_gem_object_unpin_from_display_plane(obj);
1880 1881
err_interruptible:
	dev_priv->mm.interruptible = true;
1882
	return ret;
1883 1884
}

1885 1886 1887
void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_fence(obj);
1888
	i915_gem_object_unpin_from_display_plane(obj);
1889 1890
}

1891 1892
/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
 * is assumed to be a power-of-two. */
1893 1894 1895 1896
unsigned long intel_gen4_compute_page_offset(int *x, int *y,
					     unsigned int tiling_mode,
					     unsigned int cpp,
					     unsigned int pitch)
1897
{
1898 1899
	if (tiling_mode != I915_TILING_NONE) {
		unsigned int tile_rows, tiles;
1900

1901 1902
		tile_rows = *y / 8;
		*y %= 8;
1903

1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915
		tiles = *x / (512/cpp);
		*x %= 512/cpp;

		return tile_rows * pitch * 8 + tiles * 4096;
	} else {
		unsigned int offset;

		offset = *y * pitch + *x * cpp;
		*y = 0;
		*x = (offset & 4095) / cpp;
		return offset & -4096;
	}
1916 1917
}

1918 1919
static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			     int x, int y)
J
Jesse Barnes 已提交
1920 1921 1922 1923 1924
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_framebuffer *intel_fb;
1925
	struct drm_i915_gem_object *obj;
J
Jesse Barnes 已提交
1926
	int plane = intel_crtc->plane;
1927
	unsigned long linear_offset;
J
Jesse Barnes 已提交
1928
	u32 dspcntr;
1929
	u32 reg;
J
Jesse Barnes 已提交
1930 1931 1932 1933 1934 1935

	switch (plane) {
	case 0:
	case 1:
		break;
	default:
1936
		DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
J
Jesse Barnes 已提交
1937 1938 1939 1940 1941 1942
		return -EINVAL;
	}

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

1943 1944
	reg = DSPCNTR(plane);
	dspcntr = I915_READ(reg);
J
Jesse Barnes 已提交
1945 1946
	/* Mask out pixel format bits in case we change it */
	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1947 1948
	switch (fb->pixel_format) {
	case DRM_FORMAT_C8:
J
Jesse Barnes 已提交
1949 1950
		dspcntr |= DISPPLANE_8BPP;
		break;
1951 1952 1953
	case DRM_FORMAT_XRGB1555:
	case DRM_FORMAT_ARGB1555:
		dspcntr |= DISPPLANE_BGRX555;
J
Jesse Barnes 已提交
1954
		break;
1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972
	case DRM_FORMAT_RGB565:
		dspcntr |= DISPPLANE_BGRX565;
		break;
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
		dspcntr |= DISPPLANE_BGRX888;
		break;
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
		dspcntr |= DISPPLANE_RGBX888;
		break;
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
		dspcntr |= DISPPLANE_BGRX101010;
		break;
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
		dspcntr |= DISPPLANE_RGBX101010;
J
Jesse Barnes 已提交
1973 1974
		break;
	default:
1975
		BUG();
J
Jesse Barnes 已提交
1976
	}
1977

1978
	if (INTEL_INFO(dev)->gen >= 4) {
1979
		if (obj->tiling_mode != I915_TILING_NONE)
J
Jesse Barnes 已提交
1980 1981 1982 1983 1984
			dspcntr |= DISPPLANE_TILED;
		else
			dspcntr &= ~DISPPLANE_TILED;
	}

1985 1986 1987
	if (IS_G4X(dev))
		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

1988
	I915_WRITE(reg, dspcntr);
J
Jesse Barnes 已提交
1989

1990
	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
J
Jesse Barnes 已提交
1991

1992 1993
	if (INTEL_INFO(dev)->gen >= 4) {
		intel_crtc->dspaddr_offset =
1994 1995 1996
			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
						       fb->bits_per_pixel / 8,
						       fb->pitches[0]);
1997 1998
		linear_offset -= intel_crtc->dspaddr_offset;
	} else {
1999
		intel_crtc->dspaddr_offset = linear_offset;
2000
	}
2001

2002 2003 2004
	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		      fb->pitches[0]);
2005
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2006
	if (INTEL_INFO(dev)->gen >= 4) {
2007
		I915_MODIFY_DISPBASE(DSPSURF(plane),
2008
				     i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2009
		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2010
		I915_WRITE(DSPLINOFF(plane), linear_offset);
2011
	} else
2012
		I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2013
	POSTING_READ(reg);
J
Jesse Barnes 已提交
2014

2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026
	return 0;
}

static int ironlake_update_plane(struct drm_crtc *crtc,
				 struct drm_framebuffer *fb, int x, int y)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_framebuffer *intel_fb;
	struct drm_i915_gem_object *obj;
	int plane = intel_crtc->plane;
2027
	unsigned long linear_offset;
2028 2029 2030 2031 2032 2033
	u32 dspcntr;
	u32 reg;

	switch (plane) {
	case 0:
	case 1:
J
Jesse Barnes 已提交
2034
	case 2:
2035 2036
		break;
	default:
2037
		DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2038 2039 2040 2041 2042 2043 2044 2045 2046 2047
		return -EINVAL;
	}

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

	reg = DSPCNTR(plane);
	dspcntr = I915_READ(reg);
	/* Mask out pixel format bits in case we change it */
	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048 2049
	switch (fb->pixel_format) {
	case DRM_FORMAT_C8:
2050 2051
		dspcntr |= DISPPLANE_8BPP;
		break;
2052 2053
	case DRM_FORMAT_RGB565:
		dspcntr |= DISPPLANE_BGRX565;
2054
		break;
2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
		dspcntr |= DISPPLANE_BGRX888;
		break;
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
		dspcntr |= DISPPLANE_RGBX888;
		break;
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
		dspcntr |= DISPPLANE_BGRX101010;
		break;
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
		dspcntr |= DISPPLANE_RGBX101010;
2070 2071
		break;
	default:
2072
		BUG();
2073 2074 2075 2076 2077 2078 2079
	}

	if (obj->tiling_mode != I915_TILING_NONE)
		dspcntr |= DISPPLANE_TILED;
	else
		dspcntr &= ~DISPPLANE_TILED;

2080 2081 2082 2083
	if (IS_HASWELL(dev))
		dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
	else
		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2084 2085 2086

	I915_WRITE(reg, dspcntr);

2087
	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2088
	intel_crtc->dspaddr_offset =
2089 2090 2091
		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
					       fb->bits_per_pixel / 8,
					       fb->pitches[0]);
2092
	linear_offset -= intel_crtc->dspaddr_offset;
2093

2094 2095 2096
	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
		      fb->pitches[0]);
2097
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2098
	I915_MODIFY_DISPBASE(DSPSURF(plane),
2099
			     i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2100 2101 2102 2103 2104 2105
	if (IS_HASWELL(dev)) {
		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
	} else {
		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
		I915_WRITE(DSPLINOFF(plane), linear_offset);
	}
2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118
	POSTING_READ(reg);

	return 0;
}

/* Assume fb object is pinned & idle & fenced and just update base pointers */
static int
intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			   int x, int y, enum mode_set_atomic state)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

2119 2120
	if (dev_priv->display.disable_fbc)
		dev_priv->display.disable_fbc(dev);
2121
	intel_increase_pllclock(crtc);
J
Jesse Barnes 已提交
2122

2123
	return dev_priv->display.update_plane(crtc, fb, x, y);
J
Jesse Barnes 已提交
2124 2125
}

2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163
void intel_display_handle_reset(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;

	/*
	 * Flips in the rings have been nuked by the reset,
	 * so complete all pending flips so that user space
	 * will get its events and not get stuck.
	 *
	 * Also update the base address of all primary
	 * planes to the the last fb to make sure we're
	 * showing the correct fb after a reset.
	 *
	 * Need to make two loops over the crtcs so that we
	 * don't try to grab a crtc mutex before the
	 * pending_flip_queue really got woken up.
	 */

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		enum plane plane = intel_crtc->plane;

		intel_prepare_page_flip(dev, plane);
		intel_finish_page_flip_plane(dev, plane);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

		mutex_lock(&crtc->mutex);
		if (intel_crtc->active)
			dev_priv->display.update_plane(crtc, crtc->fb,
						       crtc->x, crtc->y);
		mutex_unlock(&crtc->mutex);
	}
}

2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186
static int
intel_finish_fb(struct drm_framebuffer *old_fb)
{
	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	bool was_interruptible = dev_priv->mm.interruptible;
	int ret;

	/* Big Hammer, we also need to ensure that any pending
	 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
	 * current scanout is retired before unpinning the old
	 * framebuffer.
	 *
	 * This should only fail upon a hung GPU, in which case we
	 * can safely continue.
	 */
	dev_priv->mm.interruptible = false;
	ret = i915_gem_object_finish_gpu(obj);
	dev_priv->mm.interruptible = was_interruptible;

	return ret;
}

2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213
static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!dev->primary->master)
		return;

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
		return;

	switch (intel_crtc->pipe) {
	case 0:
		master_priv->sarea_priv->pipeA_x = x;
		master_priv->sarea_priv->pipeA_y = y;
		break;
	case 1:
		master_priv->sarea_priv->pipeB_x = x;
		master_priv->sarea_priv->pipeB_y = y;
		break;
	default:
		break;
	}
}

2214
static int
2215
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2216
		    struct drm_framebuffer *fb)
J
Jesse Barnes 已提交
2217 2218
{
	struct drm_device *dev = crtc->dev;
2219
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2220
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2221
	struct drm_framebuffer *old_fb;
2222
	int ret;
J
Jesse Barnes 已提交
2223 2224

	/* no fb bound */
2225
	if (!fb) {
2226
		DRM_ERROR("No FB bound\n");
2227 2228 2229
		return 0;
	}

2230
	if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2231 2232 2233
		DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
			  plane_name(intel_crtc->plane),
			  INTEL_INFO(dev)->num_pipes);
2234
		return -EINVAL;
J
Jesse Barnes 已提交
2235 2236
	}

2237
	mutex_lock(&dev->struct_mutex);
2238
	ret = intel_pin_and_fence_fb_obj(dev,
2239
					 to_intel_framebuffer(fb)->obj,
2240
					 NULL);
2241 2242
	if (ret != 0) {
		mutex_unlock(&dev->struct_mutex);
2243
		DRM_ERROR("pin & fence failed\n");
2244 2245
		return ret;
	}
J
Jesse Barnes 已提交
2246

2247 2248 2249 2250 2251
	/* Update pipe size and adjust fitter if needed */
	if (i915_fastboot) {
		I915_WRITE(PIPESRC(intel_crtc->pipe),
			   ((crtc->mode.hdisplay - 1) << 16) |
			   (crtc->mode.vdisplay - 1));
2252
		if (!intel_crtc->config.pch_pfit.enabled &&
2253 2254 2255 2256 2257 2258 2259 2260
		    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
		     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
			I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
			I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
			I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
		}
	}

2261
	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2262
	if (ret) {
2263
		intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2264
		mutex_unlock(&dev->struct_mutex);
2265
		DRM_ERROR("failed to update base address\n");
2266
		return ret;
J
Jesse Barnes 已提交
2267
	}
2268

2269 2270
	old_fb = crtc->fb;
	crtc->fb = fb;
2271 2272
	crtc->x = x;
	crtc->y = y;
2273

2274
	if (old_fb) {
2275 2276
		if (intel_crtc->active && old_fb != fb)
			intel_wait_for_vblank(dev, intel_crtc->pipe);
2277
		intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2278
	}
2279

2280
	intel_update_fbc(dev);
R
Rodrigo Vivi 已提交
2281
	intel_edp_psr_update(dev);
2282
	mutex_unlock(&dev->struct_mutex);
J
Jesse Barnes 已提交
2283

2284
	intel_crtc_update_sarea_pos(crtc, x, y);
2285 2286

	return 0;
J
Jesse Barnes 已提交
2287 2288
}

2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299
static void intel_fdi_normal_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* enable normal train */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2300
	if (IS_IVYBRIDGE(dev)) {
2301 2302
		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2303 2304 2305
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2306
	}
2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_NORMAL_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_NONE;
	}
	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

	/* wait one idle pattern time */
	POSTING_READ(reg);
	udelay(1000);
2323 2324 2325 2326 2327

	/* IVB wants error correction enabled */
	if (IS_IVYBRIDGE(dev))
		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
			   FDI_FE_ERRC_ENABLE);
2328 2329
}

2330 2331 2332 2333 2334
static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
{
	return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
}

2335 2336 2337 2338 2339 2340 2341 2342 2343
static void ivb_modeset_global_resources(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *pipe_B_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
	struct intel_crtc *pipe_C_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
	uint32_t temp;

2344 2345 2346 2347 2348 2349 2350
	/*
	 * When everything is off disable fdi C so that we could enable fdi B
	 * with all lanes. Note that we don't care about enabled pipes without
	 * an enabled pch encoder.
	 */
	if (!pipe_has_enabled_pch(pipe_B_crtc) &&
	    !pipe_has_enabled_pch(pipe_C_crtc)) {
2351 2352 2353 2354 2355 2356 2357 2358 2359 2360
		WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);

		temp = I915_READ(SOUTH_CHICKEN1);
		temp &= ~FDI_BC_BIFURCATION_SELECT;
		DRM_DEBUG_KMS("disabling fdi C rx\n");
		I915_WRITE(SOUTH_CHICKEN1, temp);
	}
}

2361 2362 2363 2364 2365 2366 2367
/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2368
	int plane = intel_crtc->plane;
2369
	u32 reg, temp, tries;
2370

2371 2372 2373 2374
	/* FDI needs bits from pipe & plane first */
	assert_pipe_enabled(dev_priv, pipe);
	assert_plane_enabled(dev_priv, plane);

2375 2376
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
2377 2378
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
2379 2380
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
2381 2382
	I915_WRITE(reg, temp);
	I915_READ(reg);
2383 2384
	udelay(150);

2385
	/* enable CPU FDI TX and PCH FDI RX */
2386 2387
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2388 2389
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2390 2391
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
2392
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2393

2394 2395
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2396 2397
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
2398 2399 2400
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
2401 2402
	udelay(150);

2403
	/* Ironlake workaround, enable clock pointer after FDI enable*/
2404 2405 2406
	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
		   FDI_RX_PHASE_SYNC_POINTER_EN);
2407

2408
	reg = FDI_RX_IIR(pipe);
2409
	for (tries = 0; tries < 5; tries++) {
2410
		temp = I915_READ(reg);
2411 2412 2413 2414
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if ((temp & FDI_RX_BIT_LOCK)) {
			DRM_DEBUG_KMS("FDI train 1 done.\n");
2415
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2416 2417 2418
			break;
		}
	}
2419
	if (tries == 5)
2420
		DRM_ERROR("FDI train 1 fail!\n");
2421 2422

	/* Train 2 */
2423 2424
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2425 2426
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
2427
	I915_WRITE(reg, temp);
2428

2429 2430
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2431 2432
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
2433
	I915_WRITE(reg, temp);
2434

2435 2436
	POSTING_READ(reg);
	udelay(150);
2437

2438
	reg = FDI_RX_IIR(pipe);
2439
	for (tries = 0; tries < 5; tries++) {
2440
		temp = I915_READ(reg);
2441 2442 2443
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
2444
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2445 2446 2447 2448
			DRM_DEBUG_KMS("FDI train 2 done.\n");
			break;
		}
	}
2449
	if (tries == 5)
2450
		DRM_ERROR("FDI train 2 fail!\n");
2451 2452

	DRM_DEBUG_KMS("FDI train done\n");
2453

2454 2455
}

2456
static const int snb_b_fdi_train_param[] = {
2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469
	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
};

/* The FDI link training functions for SNB/Cougarpoint. */
static void gen6_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2470
	u32 reg, temp, i, retry;
2471

2472 2473
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
2474 2475
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
2476 2477
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
2478 2479 2480
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
2481 2482
	udelay(150);

2483
	/* enable CPU FDI TX and PCH FDI RX */
2484 2485
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2486 2487
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2488 2489 2490 2491 2492
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	/* SNB-B */
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2493
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2494

2495 2496 2497
	I915_WRITE(FDI_RX_MISC(pipe),
		   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

2498 2499
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2500 2501 2502 2503 2504 2505 2506
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
2507 2508 2509
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
2510 2511
	udelay(150);

2512
	for (i = 0; i < 4; i++) {
2513 2514
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2515 2516
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
2517 2518 2519
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
2520 2521
		udelay(500);

2522 2523 2524 2525 2526 2527 2528 2529 2530 2531
		for (retry = 0; retry < 5; retry++) {
			reg = FDI_RX_IIR(pipe);
			temp = I915_READ(reg);
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
			if (temp & FDI_RX_BIT_LOCK) {
				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
				DRM_DEBUG_KMS("FDI train 1 done.\n");
				break;
			}
			udelay(50);
2532
		}
2533 2534
		if (retry < 5)
			break;
2535 2536
	}
	if (i == 4)
2537
		DRM_ERROR("FDI train 1 fail!\n");
2538 2539

	/* Train 2 */
2540 2541
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2542 2543 2544 2545 2546 2547 2548
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
	if (IS_GEN6(dev)) {
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		/* SNB-B */
		temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
	}
2549
	I915_WRITE(reg, temp);
2550

2551 2552
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2553 2554 2555 2556 2557 2558 2559
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_2;
	}
2560 2561 2562
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
2563 2564
	udelay(150);

2565
	for (i = 0; i < 4; i++) {
2566 2567
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2568 2569
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
2570 2571 2572
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
2573 2574
		udelay(500);

2575 2576 2577 2578 2579 2580 2581 2582 2583 2584
		for (retry = 0; retry < 5; retry++) {
			reg = FDI_RX_IIR(pipe);
			temp = I915_READ(reg);
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
			if (temp & FDI_RX_SYMBOL_LOCK) {
				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
				DRM_DEBUG_KMS("FDI train 2 done.\n");
				break;
			}
			udelay(50);
2585
		}
2586 2587
		if (retry < 5)
			break;
2588 2589
	}
	if (i == 4)
2590
		DRM_ERROR("FDI train 2 fail!\n");
2591 2592 2593 2594

	DRM_DEBUG_KMS("FDI train done.\n");
}

2595 2596 2597 2598 2599 2600 2601
/* Manual link training for Ivy Bridge A0 parts */
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2602
	u32 reg, temp, i, j;
2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614

	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

2615 2616 2617
	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
		      I915_READ(FDI_RX_IIR(pipe)));

2618 2619 2620 2621 2622 2623 2624 2625
	/* Try each vswing and preemphasis setting twice before moving on */
	for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
		/* disable first in case we need to retry */
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
		temp &= ~FDI_TX_ENABLE;
		I915_WRITE(reg, temp);
2626

2627 2628 2629 2630 2631 2632
		reg = FDI_RX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_AUTO;
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp &= ~FDI_RX_ENABLE;
		I915_WRITE(reg, temp);
2633

2634
		/* enable CPU FDI TX and PCH FDI RX */
2635 2636
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2637 2638 2639
		temp &= ~FDI_DP_PORT_WIDTH_MASK;
		temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
		temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2640
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641 2642 2643
		temp |= snb_b_fdi_train_param[j/2];
		temp |= FDI_COMPOSITE_SYNC;
		I915_WRITE(reg, temp | FDI_TX_ENABLE);
2644

2645 2646
		I915_WRITE(FDI_RX_MISC(pipe),
			   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2647

2648
		reg = FDI_RX_CTL(pipe);
2649
		temp = I915_READ(reg);
2650 2651 2652
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
		temp |= FDI_COMPOSITE_SYNC;
		I915_WRITE(reg, temp | FDI_RX_ENABLE);
2653

2654 2655
		POSTING_READ(reg);
		udelay(1); /* should be 0.5us */
2656

2657 2658 2659 2660
		for (i = 0; i < 4; i++) {
			reg = FDI_RX_IIR(pipe);
			temp = I915_READ(reg);
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2661

2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674
			if (temp & FDI_RX_BIT_LOCK ||
			    (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
				DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
					      i);
				break;
			}
			udelay(1); /* should be 0.5us */
		}
		if (i == 4) {
			DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
			continue;
		}
2675

2676
		/* Train 2 */
2677 2678
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2679 2680 2681 2682 2683 2684 2685 2686
		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
		I915_WRITE(reg, temp);

		reg = FDI_RX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2687 2688 2689
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
2690
		udelay(2); /* should be 1.5us */
2691

2692 2693 2694 2695
		for (i = 0; i < 4; i++) {
			reg = FDI_RX_IIR(pipe);
			temp = I915_READ(reg);
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2696

2697 2698 2699 2700 2701 2702 2703 2704
			if (temp & FDI_RX_SYMBOL_LOCK ||
			    (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
				DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
					      i);
				goto train_done;
			}
			udelay(2); /* should be 1.5us */
2705
		}
2706 2707
		if (i == 4)
			DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2708 2709
	}

2710
train_done:
2711 2712 2713
	DRM_DEBUG_KMS("FDI train done.\n");
}

2714
static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2715
{
2716
	struct drm_device *dev = intel_crtc->base.dev;
2717 2718
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = intel_crtc->pipe;
2719
	u32 reg, temp;
J
Jesse Barnes 已提交
2720

2721

2722
	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2723 2724
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2725 2726
	temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2727
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2728 2729 2730
	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

	POSTING_READ(reg);
2731 2732 2733
	udelay(200);

	/* Switch from Rawclk to PCDclk */
2734 2735 2736 2737
	temp = I915_READ(reg);
	I915_WRITE(reg, temp | FDI_PCDCLK);

	POSTING_READ(reg);
2738 2739
	udelay(200);

2740 2741 2742 2743 2744
	/* Enable CPU FDI TX PLL, always on for Ironlake */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2745

2746 2747
		POSTING_READ(reg);
		udelay(100);
2748
	}
2749 2750
}

2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779
static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* Switch from PCDclk to Rawclk */
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_PCDCLK);

	/* Disable CPU FDI TX PLL */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);

	POSTING_READ(reg);
	udelay(100);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);

	/* Wait for the clocks to turn off. */
	POSTING_READ(reg);
	udelay(100);
}

2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796
static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* disable CPU FDI tx and PCH FDI rx */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
	POSTING_READ(reg);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~(0x7 << 16);
2797
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2798 2799 2800 2801 2802 2803
	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(100);

	/* Ironlake workaround, disable clock pointer after downing FDI */
2804 2805 2806
	if (HAS_PCH_IBX(dev)) {
		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
	}
2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825

	/* still set train pattern 1 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
	/* BPC in FDI rx is consistent with that in PIPECONF */
	temp &= ~(0x07 << 16);
2826
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2827 2828 2829 2830 2831 2832
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(100);
}

2833 2834 2835 2836
static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2837
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2838 2839 2840
	unsigned long flags;
	bool pending;

2841 2842
	if (i915_reset_in_progress(&dev_priv->gpu_error) ||
	    intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2843 2844 2845 2846 2847 2848 2849 2850 2851
		return false;

	spin_lock_irqsave(&dev->event_lock, flags);
	pending = to_intel_crtc(crtc)->unpin_work != NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	return pending;
}

2852 2853
static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
{
2854
	struct drm_device *dev = crtc->dev;
2855
	struct drm_i915_private *dev_priv = dev->dev_private;
2856 2857 2858 2859

	if (crtc->fb == NULL)
		return;

2860 2861
	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));

2862 2863 2864
	wait_event(dev_priv->pending_flip_queue,
		   !intel_crtc_has_pending_flip(crtc));

2865 2866 2867
	mutex_lock(&dev->struct_mutex);
	intel_finish_fb(crtc->fb);
	mutex_unlock(&dev->struct_mutex);
2868 2869
}

2870 2871 2872 2873 2874 2875 2876 2877
/* Program iCLKIP clock to the desired frequency */
static void lpt_program_iclkip(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 divsel, phaseinc, auxdiv, phasedir = 0;
	u32 temp;

2878 2879
	mutex_lock(&dev_priv->dpio_lock);

2880 2881 2882 2883 2884 2885 2886
	/* It is necessary to ungate the pixclk gate prior to programming
	 * the divisors, and gate it back when it is done.
	 */
	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);

	/* Disable SSCCTL */
	intel_sbi_write(dev_priv, SBI_SSCCTL6,
2887 2888 2889
			intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
				SBI_SSCCTL_DISABLE,
			SBI_ICLK);
2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929

	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
	if (crtc->mode.clock == 20000) {
		auxdiv = 1;
		divsel = 0x41;
		phaseinc = 0x20;
	} else {
		/* The iCLK virtual clock root frequency is in MHz,
		 * but the crtc->mode.clock in in KHz. To get the divisors,
		 * it is necessary to divide one by another, so we
		 * convert the virtual clock precision to KHz here for higher
		 * precision.
		 */
		u32 iclk_virtual_root_freq = 172800 * 1000;
		u32 iclk_pi_range = 64;
		u32 desired_divisor, msb_divisor_value, pi_value;

		desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
		msb_divisor_value = desired_divisor / iclk_pi_range;
		pi_value = desired_divisor % iclk_pi_range;

		auxdiv = 0;
		divsel = msb_divisor_value - 2;
		phaseinc = pi_value;
	}

	/* This should not happen with any sane values */
	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		~SBI_SSCDIVINTPHASE_INCVAL_MASK);

	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
			crtc->mode.clock,
			auxdiv,
			divsel,
			phasedir,
			phaseinc);

	/* Program SSCDIVINTPHASE6 */
2930
	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2931 2932 2933 2934 2935 2936
	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2937
	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2938 2939

	/* Program SSCAUXDIV */
2940
	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2941 2942
	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2943
	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2944 2945

	/* Enable modulator and associated divider */
2946
	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2947
	temp &= ~SBI_SSCCTL_DISABLE;
2948
	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2949 2950 2951 2952 2953

	/* Wait for initialization time */
	udelay(24);

	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2954 2955

	mutex_unlock(&dev_priv->dpio_lock);
2956 2957
}

2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981
static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
						enum pipe pch_transcoder)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;

	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
		   I915_READ(HTOTAL(cpu_transcoder)));
	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
		   I915_READ(HBLANK(cpu_transcoder)));
	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
		   I915_READ(HSYNC(cpu_transcoder)));

	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
		   I915_READ(VTOTAL(cpu_transcoder)));
	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
		   I915_READ(VBLANK(cpu_transcoder)));
	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
		   I915_READ(VSYNC(cpu_transcoder)));
	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
		   I915_READ(VSYNCSHIFT(cpu_transcoder)));
}

2982 2983 2984 2985 2986 2987 2988 2989 2990
/*
 * Enable PCH resources required for PCH ports:
 *   - PCH PLLs
 *   - FDI training & RX/TX
 *   - update transcoder timings
 *   - DP transcoding bits
 *   - transcoder
 */
static void ironlake_pch_enable(struct drm_crtc *crtc)
2991 2992 2993 2994 2995
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2996
	u32 reg, temp;
2997

2998
	assert_pch_transcoder_disabled(dev_priv, pipe);
2999

3000 3001 3002 3003 3004
	/* Write the TU size bits before fdi link training, so that error
	 * detection works. */
	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);

3005
	/* For PCH output, training FDI link */
3006
	dev_priv->display.fdi_link_train(crtc);
3007

3008 3009
	/* We need to program the right clock selection before writing the pixel
	 * mutliplier into the DPLL. */
3010
	if (HAS_PCH_CPT(dev)) {
3011
		u32 sel;
3012

3013
		temp = I915_READ(PCH_DPLL_SEL);
3014 3015
		temp |= TRANS_DPLL_ENABLE(pipe);
		sel = TRANS_DPLLB_SEL(pipe);
3016
		if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3017 3018 3019
			temp |= sel;
		else
			temp &= ~sel;
3020 3021
		I915_WRITE(PCH_DPLL_SEL, temp);
	}
3022

3023 3024 3025 3026 3027 3028 3029 3030 3031
	/* XXX: pch pll's can be enabled any time before we enable the PCH
	 * transcoder, and we actually should do this to not upset any PCH
	 * transcoder that already use the clock when we share it.
	 *
	 * Note that enable_shared_dpll tries to do the right thing, but
	 * get_shared_dpll unconditionally resets the pll - we need that to have
	 * the right LVDS enable sequence. */
	ironlake_enable_shared_dpll(intel_crtc);

3032 3033
	/* set transcoder timing, panel must allow it */
	assert_panel_unlocked(dev_priv, pipe);
3034
	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3035

3036
	intel_fdi_normal_train(crtc);
3037

3038 3039
	/* For PCH DP, enable TRANS_DP_CTL */
	if (HAS_PCH_CPT(dev) &&
3040 3041
	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3042
		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3043 3044 3045
		reg = TRANS_DP_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(TRANS_DP_PORT_SEL_MASK |
3046 3047
			  TRANS_DP_SYNC_MASK |
			  TRANS_DP_BPC_MASK);
3048 3049
		temp |= (TRANS_DP_OUTPUT_ENABLE |
			 TRANS_DP_ENH_FRAMING);
3050
		temp |= bpc << 9; /* same format but at 11:9 */
3051 3052

		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3053
			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3054
		if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3055
			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3056 3057 3058

		switch (intel_trans_dp_port_sel(crtc)) {
		case PCH_DP_B:
3059
			temp |= TRANS_DP_PORT_SEL_B;
3060 3061
			break;
		case PCH_DP_C:
3062
			temp |= TRANS_DP_PORT_SEL_C;
3063 3064
			break;
		case PCH_DP_D:
3065
			temp |= TRANS_DP_PORT_SEL_D;
3066 3067
			break;
		default:
3068
			BUG();
3069
		}
3070

3071
		I915_WRITE(reg, temp);
3072
	}
3073

3074
	ironlake_enable_pch_transcoder(dev_priv, pipe);
3075 3076
}

P
Paulo Zanoni 已提交
3077 3078 3079 3080 3081
static void lpt_pch_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3082
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
P
Paulo Zanoni 已提交
3083

3084
	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
P
Paulo Zanoni 已提交
3085

3086
	lpt_program_iclkip(crtc);
P
Paulo Zanoni 已提交
3087

3088
	/* Set transcoder timing. */
3089
	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
P
Paulo Zanoni 已提交
3090

3091
	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3092 3093
}

3094
static void intel_put_shared_dpll(struct intel_crtc *crtc)
3095
{
3096
	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3097 3098 3099 3100 3101

	if (pll == NULL)
		return;

	if (pll->refcount == 0) {
3102
		WARN(1, "bad %s refcount\n", pll->name);
3103 3104 3105
		return;
	}

3106 3107 3108 3109 3110
	if (--pll->refcount == 0) {
		WARN_ON(pll->on);
		WARN_ON(pll->active);
	}

3111
	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3112 3113
}

3114
static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3115
{
3116 3117 3118
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
	enum intel_dpll_id i;
3119 3120

	if (pll) {
3121 3122
		DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
			      crtc->base.base.id, pll->name);
3123
		intel_put_shared_dpll(crtc);
3124 3125
	}

3126 3127
	if (HAS_PCH_IBX(dev_priv->dev)) {
		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3128
		i = (enum intel_dpll_id) crtc->pipe;
D
Daniel Vetter 已提交
3129
		pll = &dev_priv->shared_dplls[i];
3130

3131 3132
		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
			      crtc->base.base.id, pll->name);
3133 3134 3135 3136

		goto found;
	}

D
Daniel Vetter 已提交
3137 3138
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		pll = &dev_priv->shared_dplls[i];
3139 3140 3141 3142 3143

		/* Only want to check enabled timings first */
		if (pll->refcount == 0)
			continue;

3144 3145
		if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
			   sizeof(pll->hw_state)) == 0) {
3146
			DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3147
				      crtc->base.base.id,
3148
				      pll->name, pll->refcount, pll->active);
3149 3150 3151 3152 3153 3154

			goto found;
		}
	}

	/* Ok no matching timings, maybe there's a free one? */
D
Daniel Vetter 已提交
3155 3156
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		pll = &dev_priv->shared_dplls[i];
3157
		if (pll->refcount == 0) {
3158 3159
			DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
				      crtc->base.base.id, pll->name);
3160 3161 3162 3163 3164 3165 3166
			goto found;
		}
	}

	return NULL;

found:
3167
	crtc->config.shared_dpll = i;
3168 3169
	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
			 pipe_name(crtc->pipe));
3170

3171
	if (pll->active == 0) {
3172 3173 3174
		memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
		       sizeof(pll->hw_state));

3175
		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3176
		WARN_ON(pll->on);
3177
		assert_shared_dpll_disabled(dev_priv, pll);
3178

3179
		pll->mode_set(dev_priv, pll);
3180 3181
	}
	pll->refcount++;
3182

3183 3184 3185
	return pll;
}

3186
static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3187 3188
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3189
	int dslreg = PIPEDSL(pipe);
3190 3191 3192 3193 3194 3195
	u32 temp;

	temp = I915_READ(dslreg);
	udelay(500);
	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		if (wait_for(I915_READ(dslreg) != temp, 5))
3196
			DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3197 3198 3199
	}
}

3200 3201 3202 3203 3204 3205
static void ironlake_pfit_enable(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = crtc->pipe;

3206
	if (crtc->config.pch_pfit.enabled) {
3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217
		/* Force use of hard-coded filter coefficients
		 * as some pre-programmed values are broken,
		 * e.g. x201.
		 */
		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
						 PF_PIPE_SEL_IVB(pipe));
		else
			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
		I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
		I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3218 3219 3220
	}
}

3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242
static void intel_enable_planes(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	enum pipe pipe = to_intel_crtc(crtc)->pipe;
	struct intel_plane *intel_plane;

	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
		if (intel_plane->pipe == pipe)
			intel_plane_restore(&intel_plane->base);
}

static void intel_disable_planes(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	enum pipe pipe = to_intel_crtc(crtc)->pipe;
	struct intel_plane *intel_plane;

	list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
		if (intel_plane->pipe == pipe)
			intel_plane_disable(&intel_plane->base);
}

3243 3244 3245 3246 3247
static void ironlake_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3248
	struct intel_encoder *encoder;
3249 3250 3251
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;

3252 3253
	WARN_ON(!crtc->enabled);

3254 3255 3256 3257
	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
3258 3259 3260 3261

	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);

3262 3263
	intel_update_watermarks(dev);

3264
	for_each_encoder_on_crtc(dev, crtc, encoder)
3265 3266
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);
3267

3268
	if (intel_crtc->config.has_pch_encoder) {
3269 3270 3271
		/* Note: FDI PLL enabling _must_ be done before we enable the
		 * cpu pipes, hence this is separate from all the other fdi/pch
		 * enabling. */
3272
		ironlake_fdi_pll_enable(intel_crtc);
3273 3274 3275 3276
	} else {
		assert_fdi_tx_disabled(dev_priv, pipe);
		assert_fdi_rx_disabled(dev_priv, pipe);
	}
3277

3278
	ironlake_pfit_enable(intel_crtc);
3279

3280 3281 3282 3283 3284 3285
	/*
	 * On ILK+ LUT must be loaded before the pipe is running but with
	 * clocks enabled
	 */
	intel_crtc_load_lut(crtc);

3286 3287
	intel_enable_pipe(dev_priv, pipe,
			  intel_crtc->config.has_pch_encoder);
3288
	intel_enable_plane(dev_priv, plane, pipe);
3289
	intel_enable_planes(crtc);
3290
	intel_crtc_update_cursor(crtc, true);
3291

3292
	if (intel_crtc->config.has_pch_encoder)
3293
		ironlake_pch_enable(crtc);
3294

3295
	mutex_lock(&dev->struct_mutex);
C
Chris Wilson 已提交
3296
	intel_update_fbc(dev);
3297 3298
	mutex_unlock(&dev->struct_mutex);

3299 3300
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);
3301 3302

	if (HAS_PCH_CPT(dev))
3303
		cpt_verify_modeset(dev, intel_crtc->pipe);
3304 3305 3306 3307 3308 3309 3310 3311 3312 3313

	/*
	 * There seems to be a race in PCH platform hw (at least on some
	 * outputs) where an enabled pipe still completes any pageflip right
	 * away (as if the pipe is off) instead of waiting for vblank. As soon
	 * as the first vblank happend, everything works as expected. Hence just
	 * wait for one vblank before returning to avoid strange things
	 * happening.
	 */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
3314 3315
}

P
Paulo Zanoni 已提交
3316 3317 3318
/* IPS only exists on ULT machines and is tied to pipe A. */
static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
{
3319
	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
P
Paulo Zanoni 已提交
3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351
}

static void hsw_enable_ips(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;

	if (!crtc->config.ips_enabled)
		return;

	/* We can only enable IPS after we enable a plane and wait for a vblank.
	 * We guarantee that the plane is enabled by calling intel_enable_ips
	 * only after intel_enable_plane. And intel_enable_plane already waits
	 * for a vblank, so all we need to do here is to enable the IPS bit. */
	assert_plane_enabled(dev_priv, crtc->plane);
	I915_WRITE(IPS_CTL, IPS_ENABLE);
}

static void hsw_disable_ips(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!crtc->config.ips_enabled)
		return;

	assert_plane_enabled(dev_priv, crtc->plane);
	I915_WRITE(IPS_CTL, 0);

	/* We need to wait for a vblank before we can disable the plane. */
	intel_wait_for_vblank(dev, crtc->pipe);
}

3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366
static void haswell_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_encoder *encoder;
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;

	WARN_ON(!crtc->enabled);

	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
3367 3368 3369 3370 3371

	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
	if (intel_crtc->config.has_pch_encoder)
		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);

3372 3373
	intel_update_watermarks(dev);

3374
	if (intel_crtc->config.has_pch_encoder)
3375
		dev_priv->display.fdi_link_train(crtc);
3376 3377 3378 3379 3380

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);

3381
	intel_ddi_enable_pipe_clock(intel_crtc);
3382

3383
	ironlake_pfit_enable(intel_crtc);
3384 3385 3386 3387 3388 3389 3390

	/*
	 * On ILK+ LUT must be loaded before the pipe is running but with
	 * clocks enabled
	 */
	intel_crtc_load_lut(crtc);

3391
	intel_ddi_set_pipe_settings(crtc);
3392
	intel_ddi_enable_transcoder_func(crtc);
3393

3394 3395
	intel_enable_pipe(dev_priv, pipe,
			  intel_crtc->config.has_pch_encoder);
3396
	intel_enable_plane(dev_priv, plane, pipe);
3397
	intel_enable_planes(crtc);
3398
	intel_crtc_update_cursor(crtc, true);
3399

P
Paulo Zanoni 已提交
3400 3401
	hsw_enable_ips(intel_crtc);

3402
	if (intel_crtc->config.has_pch_encoder)
P
Paulo Zanoni 已提交
3403
		lpt_pch_enable(crtc);
3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422

	mutex_lock(&dev->struct_mutex);
	intel_update_fbc(dev);
	mutex_unlock(&dev->struct_mutex);

	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);

	/*
	 * There seems to be a race in PCH platform hw (at least on some
	 * outputs) where an enabled pipe still completes any pageflip right
	 * away (as if the pipe is off) instead of waiting for vblank. As soon
	 * as the first vblank happend, everything works as expected. Hence just
	 * wait for one vblank before returning to avoid strange things
	 * happening.
	 */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
}

3423 3424 3425 3426 3427 3428 3429 3430
static void ironlake_pfit_disable(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = crtc->pipe;

	/* To avoid upsetting the power well on haswell only disable the pfit if
	 * it's in use. The hw state code will make sure we get this right. */
3431
	if (crtc->config.pch_pfit.enabled) {
3432 3433 3434 3435 3436 3437
		I915_WRITE(PF_CTL(pipe), 0);
		I915_WRITE(PF_WIN_POS(pipe), 0);
		I915_WRITE(PF_WIN_SZ(pipe), 0);
	}
}

3438 3439 3440 3441 3442
static void ironlake_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3443
	struct intel_encoder *encoder;
3444 3445
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3446
	u32 reg, temp;
3447

3448

3449 3450 3451
	if (!intel_crtc->active)
		return;

3452 3453 3454
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->disable(encoder);

3455
	intel_crtc_wait_for_pending_flips(crtc);
3456
	drm_vblank_off(dev, pipe);
3457

3458
	if (dev_priv->fbc.plane == plane)
3459
		intel_disable_fbc(dev);
3460

3461
	intel_crtc_update_cursor(crtc, false);
3462
	intel_disable_planes(crtc);
3463 3464
	intel_disable_plane(dev_priv, plane, pipe);

3465 3466 3467
	if (intel_crtc->config.has_pch_encoder)
		intel_set_pch_fifo_underrun_reporting(dev, pipe, false);

3468
	intel_disable_pipe(dev_priv, pipe);
3469

3470
	ironlake_pfit_disable(intel_crtc);
3471

3472 3473 3474
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->post_disable)
			encoder->post_disable(encoder);
3475

3476 3477
	if (intel_crtc->config.has_pch_encoder) {
		ironlake_fdi_disable(crtc);
3478

3479 3480
		ironlake_disable_pch_transcoder(dev_priv, pipe);
		intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3481

3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492
		if (HAS_PCH_CPT(dev)) {
			/* disable TRANS_DP_CTL */
			reg = TRANS_DP_CTL(pipe);
			temp = I915_READ(reg);
			temp &= ~(TRANS_DP_OUTPUT_ENABLE |
				  TRANS_DP_PORT_SEL_MASK);
			temp |= TRANS_DP_PORT_SEL_NONE;
			I915_WRITE(reg, temp);

			/* disable DPLL_SEL */
			temp = I915_READ(PCH_DPLL_SEL);
3493
			temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3494
			I915_WRITE(PCH_DPLL_SEL, temp);
3495
		}
3496

3497
		/* disable PCH DPLL */
D
Daniel Vetter 已提交
3498
		intel_disable_shared_dpll(intel_crtc);
3499

3500 3501
		ironlake_fdi_pll_disable(intel_crtc);
	}
3502

3503
	intel_crtc->active = false;
3504
	intel_update_watermarks(dev);
3505 3506

	mutex_lock(&dev->struct_mutex);
3507
	intel_update_fbc(dev);
3508
	mutex_unlock(&dev->struct_mutex);
3509
}
3510

3511
static void haswell_crtc_disable(struct drm_crtc *crtc)
3512
{
3513 3514
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
3515
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516 3517 3518
	struct intel_encoder *encoder;
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3519
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3520

3521 3522 3523 3524 3525 3526 3527 3528 3529
	if (!intel_crtc->active)
		return;

	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->disable(encoder);

	intel_crtc_wait_for_pending_flips(crtc);
	drm_vblank_off(dev, pipe);

R
Rodrigo Vivi 已提交
3530
	/* FBC must be disabled before disabling the plane on HSW. */
3531
	if (dev_priv->fbc.plane == plane)
3532 3533
		intel_disable_fbc(dev);

P
Paulo Zanoni 已提交
3534 3535
	hsw_disable_ips(intel_crtc);

3536
	intel_crtc_update_cursor(crtc, false);
3537
	intel_disable_planes(crtc);
R
Rodrigo Vivi 已提交
3538 3539
	intel_disable_plane(dev_priv, plane, pipe);

3540 3541
	if (intel_crtc->config.has_pch_encoder)
		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3542 3543
	intel_disable_pipe(dev_priv, pipe);

3544
	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3545

3546
	ironlake_pfit_disable(intel_crtc);
3547

3548
	intel_ddi_disable_pipe_clock(intel_crtc);
3549 3550 3551 3552 3553

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->post_disable)
			encoder->post_disable(encoder);

3554
	if (intel_crtc->config.has_pch_encoder) {
3555
		lpt_disable_pch_transcoder(dev_priv);
3556
		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3557
		intel_ddi_fdi_disable(crtc);
3558
	}
3559 3560 3561 3562 3563 3564 3565 3566 3567

	intel_crtc->active = false;
	intel_update_watermarks(dev);

	mutex_lock(&dev->struct_mutex);
	intel_update_fbc(dev);
	mutex_unlock(&dev->struct_mutex);
}

3568 3569 3570
static void ironlake_crtc_off(struct drm_crtc *crtc)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
D
Daniel Vetter 已提交
3571
	intel_put_shared_dpll(intel_crtc);
3572 3573
}

3574 3575 3576 3577 3578
static void haswell_crtc_off(struct drm_crtc *crtc)
{
	intel_ddi_put_crtc_pll(crtc);
}

3579 3580 3581
static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
{
	if (!enable && intel_crtc->overlay) {
3582
		struct drm_device *dev = intel_crtc->base.dev;
3583
		struct drm_i915_private *dev_priv = dev->dev_private;
3584

3585
		mutex_lock(&dev->struct_mutex);
3586 3587 3588
		dev_priv->mm.interruptible = false;
		(void) intel_overlay_switch_off(intel_crtc->overlay);
		dev_priv->mm.interruptible = true;
3589
		mutex_unlock(&dev->struct_mutex);
3590 3591
	}

3592 3593 3594
	/* Let userspace switch the overlay on again. In most cases userspace
	 * has to recompute where to put it anyway.
	 */
3595 3596
}

3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620
/**
 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
 * cursor plane briefly if not already running after enabling the display
 * plane.
 * This workaround avoids occasional blank screens when self refresh is
 * enabled.
 */
static void
g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
{
	u32 cntl = I915_READ(CURCNTR(pipe));

	if ((cntl & CURSOR_MODE) == 0) {
		u32 fw_bcl_self = I915_READ(FW_BLC_SELF);

		I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
		I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
		intel_wait_for_vblank(dev_priv->dev, pipe);
		I915_WRITE(CURCNTR(pipe), cntl);
		I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
		I915_WRITE(FW_BLC_SELF, fw_bcl_self);
	}
}

3621 3622 3623 3624 3625 3626
static void i9xx_pfit_enable(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc_config *pipe_config = &crtc->config;

3627
	if (!crtc->config.gmch_pfit.control)
3628 3629 3630
		return;

	/*
3631 3632
	 * The panel fitter should only be adjusted whilst the pipe is disabled,
	 * according to register description and PRM.
3633
	 */
3634 3635
	WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
	assert_pipe_disabled(dev_priv, crtc->pipe);
3636

3637 3638
	I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
	I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3639 3640 3641 3642

	/* Border color in case we don't scale up to the full screen. Black by
	 * default, change to something else for debugging. */
	I915_WRITE(BCLRPAT(crtc->pipe), 0);
3643 3644
}

3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665
static void valleyview_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_encoder *encoder;
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;

	WARN_ON(!crtc->enabled);

	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
	intel_update_watermarks(dev);

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_pll_enable)
			encoder->pre_pll_enable(encoder);

3666
	vlv_enable_pll(intel_crtc);
3667 3668 3669 3670 3671

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);

3672 3673
	i9xx_pfit_enable(intel_crtc);

3674 3675
	intel_crtc_load_lut(crtc);

3676 3677
	intel_enable_pipe(dev_priv, pipe, false);
	intel_enable_plane(dev_priv, plane, pipe);
3678
	intel_enable_planes(crtc);
3679
	intel_crtc_update_cursor(crtc, true);
3680 3681

	intel_update_fbc(dev);
3682 3683 3684

	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);
3685 3686
}

3687
static void i9xx_crtc_enable(struct drm_crtc *crtc)
J
Jesse Barnes 已提交
3688 3689 3690 3691
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3692
	struct intel_encoder *encoder;
J
Jesse Barnes 已提交
3693
	int pipe = intel_crtc->pipe;
3694
	int plane = intel_crtc->plane;
J
Jesse Barnes 已提交
3695

3696 3697
	WARN_ON(!crtc->enabled);

3698 3699 3700 3701
	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
3702 3703
	intel_update_watermarks(dev);

3704 3705 3706 3707
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);

3708 3709
	i9xx_enable_pll(intel_crtc);

3710 3711
	i9xx_pfit_enable(intel_crtc);

3712 3713
	intel_crtc_load_lut(crtc);

3714
	intel_enable_pipe(dev_priv, pipe, false);
3715
	intel_enable_plane(dev_priv, plane, pipe);
3716
	intel_enable_planes(crtc);
3717
	/* The fixup needs to happen before cursor is enabled */
3718 3719
	if (IS_G4X(dev))
		g4x_fixup_plane(dev_priv, pipe);
3720
	intel_crtc_update_cursor(crtc, true);
J
Jesse Barnes 已提交
3721

3722 3723
	/* Give the overlay scaler a chance to enable if it's on this pipe */
	intel_crtc_dpms_overlay(intel_crtc, true);
3724

3725
	intel_update_fbc(dev);
3726

3727 3728
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);
3729
}
J
Jesse Barnes 已提交
3730

3731 3732 3733 3734 3735
static void i9xx_pfit_disable(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

3736 3737
	if (!crtc->config.gmch_pfit.control)
		return;
3738

3739
	assert_pipe_disabled(dev_priv, crtc->pipe);
3740

3741 3742 3743
	DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
			 I915_READ(PFIT_CONTROL));
	I915_WRITE(PFIT_CONTROL, 0);
3744 3745
}

3746 3747 3748 3749 3750
static void i9xx_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3751
	struct intel_encoder *encoder;
3752 3753
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3754

3755 3756 3757
	if (!intel_crtc->active)
		return;

3758 3759 3760
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->disable(encoder);

3761
	/* Give the overlay scaler a chance to disable if it's on this pipe */
3762 3763
	intel_crtc_wait_for_pending_flips(crtc);
	drm_vblank_off(dev, pipe);
3764

3765
	if (dev_priv->fbc.plane == plane)
3766
		intel_disable_fbc(dev);
J
Jesse Barnes 已提交
3767

3768 3769
	intel_crtc_dpms_overlay(intel_crtc, false);
	intel_crtc_update_cursor(crtc, false);
3770
	intel_disable_planes(crtc);
3771
	intel_disable_plane(dev_priv, plane, pipe);
3772

3773
	intel_disable_pipe(dev_priv, pipe);
3774

3775
	i9xx_pfit_disable(intel_crtc);
3776

3777 3778 3779 3780
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->post_disable)
			encoder->post_disable(encoder);

3781
	i9xx_disable_pll(dev_priv, pipe);
3782

3783
	intel_crtc->active = false;
3784 3785
	intel_update_fbc(dev);
	intel_update_watermarks(dev);
3786 3787
}

3788 3789 3790 3791
static void i9xx_crtc_off(struct drm_crtc *crtc)
{
}

3792 3793
static void intel_crtc_update_sarea(struct drm_crtc *crtc,
				    bool enabled)
3794 3795 3796 3797 3798
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
J
Jesse Barnes 已提交
3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816

	if (!dev->primary->master)
		return;

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
		return;

	switch (pipe) {
	case 0:
		master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	case 1:
		master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	default:
3817
		DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
J
Jesse Barnes 已提交
3818 3819 3820 3821
		break;
	}
}

3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842
/**
 * Sets the power management mode of the pipe and plane.
 */
void intel_crtc_update_dpms(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	bool enable = false;

	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		enable |= intel_encoder->connectors_active;

	if (enable)
		dev_priv->display.crtc_enable(crtc);
	else
		dev_priv->display.crtc_disable(crtc);

	intel_crtc_update_sarea(crtc, enable);
}

3843 3844 3845
static void intel_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
3846
	struct drm_connector *connector;
3847
	struct drm_i915_private *dev_priv = dev->dev_private;
3848
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849

3850 3851 3852 3853
	/* crtc should still be enabled when we disable it. */
	WARN_ON(!crtc->enabled);

	dev_priv->display.crtc_disable(crtc);
3854
	intel_crtc->eld_vld = false;
3855
	intel_crtc_update_sarea(crtc, false);
3856 3857
	dev_priv->display.off(crtc);

3858 3859
	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3860 3861 3862

	if (crtc->fb) {
		mutex_lock(&dev->struct_mutex);
3863
		intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3864
		mutex_unlock(&dev->struct_mutex);
3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877
		crtc->fb = NULL;
	}

	/* Update computed state. */
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		if (!connector->encoder || !connector->encoder->crtc)
			continue;

		if (connector->encoder->crtc != crtc)
			continue;

		connector->dpms = DRM_MODE_DPMS_OFF;
		to_intel_encoder(connector->encoder)->connectors_active = false;
3878 3879 3880
	}
}

C
Chris Wilson 已提交
3881
void intel_encoder_destroy(struct drm_encoder *encoder)
3882
{
3883
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
C
Chris Wilson 已提交
3884 3885 3886

	drm_encoder_cleanup(encoder);
	kfree(intel_encoder);
3887 3888
}

3889
/* Simple dpms helper for encoders with just one connector, no cloning and only
3890 3891
 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
 * state of the entire output pipe. */
3892
static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3893
{
3894 3895 3896
	if (mode == DRM_MODE_DPMS_ON) {
		encoder->connectors_active = true;

3897
		intel_crtc_update_dpms(encoder->base.crtc);
3898 3899 3900
	} else {
		encoder->connectors_active = false;

3901
		intel_crtc_update_dpms(encoder->base.crtc);
3902
	}
J
Jesse Barnes 已提交
3903 3904
}

3905 3906
/* Cross check the actual hw state with our own modeset state tracking (and it's
 * internal consistency). */
3907
static void intel_connector_check_state(struct intel_connector *connector)
J
Jesse Barnes 已提交
3908
{
3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937
	if (connector->get_hw_state(connector)) {
		struct intel_encoder *encoder = connector->encoder;
		struct drm_crtc *crtc;
		bool encoder_enabled;
		enum pipe pipe;

		DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
			      connector->base.base.id,
			      drm_get_connector_name(&connector->base));

		WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		     "wrong connector dpms state\n");
		WARN(connector->base.encoder != &encoder->base,
		     "active connector not linked to encoder\n");
		WARN(!encoder->connectors_active,
		     "encoder->connectors_active not set\n");

		encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		WARN(!encoder_enabled, "encoder not enabled\n");
		if (WARN_ON(!encoder->base.crtc))
			return;

		crtc = encoder->base.crtc;

		WARN(!crtc->enabled, "crtc not enabled\n");
		WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		WARN(pipe != to_intel_crtc(crtc)->pipe,
		     "encoder active on the wrong pipe\n");
	}
J
Jesse Barnes 已提交
3938 3939
}

3940 3941 3942
/* Even simpler default implementation, if there's really no special case to
 * consider. */
void intel_connector_dpms(struct drm_connector *connector, int mode)
J
Jesse Barnes 已提交
3943
{
3944
	struct intel_encoder *encoder = intel_attached_encoder(connector);
3945

3946 3947 3948
	/* All the simple cases only support two dpms states. */
	if (mode != DRM_MODE_DPMS_ON)
		mode = DRM_MODE_DPMS_OFF;
3949

3950 3951 3952 3953 3954 3955 3956 3957 3958
	if (mode == connector->dpms)
		return;

	connector->dpms = mode;

	/* Only need to change hw state when actually enabled */
	if (encoder->base.crtc)
		intel_encoder_dpms(encoder, mode);
	else
3959
		WARN_ON(encoder->connectors_active != false);
3960

3961
	intel_modeset_check_state(connector->dev);
J
Jesse Barnes 已提交
3962 3963
}

3964 3965 3966 3967
/* Simple connector->get_hw_state implementation for encoders that support only
 * one connector and no cloning and hence the encoder state determines the state
 * of the connector. */
bool intel_connector_get_hw_state(struct intel_connector *connector)
C
Chris Wilson 已提交
3968
{
3969
	enum pipe pipe = 0;
3970
	struct intel_encoder *encoder = connector->encoder;
C
Chris Wilson 已提交
3971

3972
	return encoder->get_hw_state(encoder, &pipe);
C
Chris Wilson 已提交
3973 3974
}

3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015
static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
				     struct intel_crtc_config *pipe_config)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *pipe_B_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);

	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
		      pipe_name(pipe), pipe_config->fdi_lanes);
	if (pipe_config->fdi_lanes > 4) {
		DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
			      pipe_name(pipe), pipe_config->fdi_lanes);
		return false;
	}

	if (IS_HASWELL(dev)) {
		if (pipe_config->fdi_lanes > 2) {
			DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
				      pipe_config->fdi_lanes);
			return false;
		} else {
			return true;
		}
	}

	if (INTEL_INFO(dev)->num_pipes == 2)
		return true;

	/* Ivybridge 3 pipe is really complicated */
	switch (pipe) {
	case PIPE_A:
		return true;
	case PIPE_B:
		if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
		    pipe_config->fdi_lanes > 2) {
			DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
				      pipe_name(pipe), pipe_config->fdi_lanes);
			return false;
		}
		return true;
	case PIPE_C:
4016
		if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032
		    pipe_B_crtc->config.fdi_lanes <= 2) {
			if (pipe_config->fdi_lanes > 2) {
				DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
					      pipe_name(pipe), pipe_config->fdi_lanes);
				return false;
			}
		} else {
			DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
			return false;
		}
		return true;
	default:
		BUG();
	}
}

4033 4034 4035
#define RETRY 1
static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
				       struct intel_crtc_config *pipe_config)
4036
{
4037
	struct drm_device *dev = intel_crtc->base.dev;
4038
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4039
	int lane, link_bw, fdi_dotclock;
4040
	bool setup_ok, needs_recompute = false;
4041

4042
retry:
4043 4044 4045 4046 4047 4048 4049 4050 4051
	/* FDI is a binary signal running at ~2.7GHz, encoding
	 * each output octet as 10 bits. The actual frequency
	 * is stored as a divider into a 100MHz clock, and the
	 * mode pixel clock is stored in units of 1KHz.
	 * Hence the bw of each lane in terms of the mode signal
	 * is:
	 */
	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;

4052
	fdi_dotclock = adjusted_mode->clock;
4053
	fdi_dotclock /= pipe_config->pixel_multiplier;
4054

4055
	lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4056 4057 4058 4059
					   pipe_config->pipe_bpp);

	pipe_config->fdi_lanes = lane;

4060
	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4061
			       link_bw, &pipe_config->fdi_m_n);
4062

4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078
	setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
					    intel_crtc->pipe, pipe_config);
	if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
		pipe_config->pipe_bpp -= 2*3;
		DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
			      pipe_config->pipe_bpp);
		needs_recompute = true;
		pipe_config->bw_constrained = true;

		goto retry;
	}

	if (needs_recompute)
		return RETRY;

	return setup_ok ? 0 : -EINVAL;
4079 4080
}

P
Paulo Zanoni 已提交
4081 4082 4083
static void hsw_compute_ips_config(struct intel_crtc *crtc,
				   struct intel_crtc_config *pipe_config)
{
4084 4085
	pipe_config->ips_enabled = i915_enable_ips &&
				   hsw_crtc_supports_ips(crtc) &&
4086
				   pipe_config->pipe_bpp <= 24;
P
Paulo Zanoni 已提交
4087 4088
}

4089
static int intel_crtc_compute_config(struct intel_crtc *crtc,
4090
				     struct intel_crtc_config *pipe_config)
J
Jesse Barnes 已提交
4091
{
4092
	struct drm_device *dev = crtc->base.dev;
4093
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4094

4095
	if (HAS_PCH_SPLIT(dev)) {
4096
		/* FDI link clock is fixed at 2.7G */
4097 4098
		if (pipe_config->requested_mode.clock * 3
		    > IRONLAKE_FDI_FREQ * 4)
4099
			return -EINVAL;
4100
	}
4101

4102 4103
	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4104 4105 4106
	 */
	if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
		adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4107
		return -EINVAL;
4108

4109
	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4110
		pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4111
	} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4112 4113 4114 4115 4116
		/* only a 8bpc pipe, with 6bpc dither through the panel fitter
		 * for lvds. */
		pipe_config->pipe_bpp = 8*3;
	}

4117
	if (HAS_IPS(dev))
4118 4119 4120 4121 4122 4123
		hsw_compute_ips_config(crtc, pipe_config);

	/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
	 * clock survives for now. */
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
		pipe_config->shared_dpll = crtc->config.shared_dpll;
P
Paulo Zanoni 已提交
4124

4125
	if (pipe_config->has_pch_encoder)
4126
		return ironlake_fdi_compute_config(crtc, pipe_config);
4127

4128
	return 0;
J
Jesse Barnes 已提交
4129 4130
}

J
Jesse Barnes 已提交
4131 4132 4133 4134 4135
static int valleyview_get_display_clock_speed(struct drm_device *dev)
{
	return 400000; /* FIXME */
}

4136 4137 4138 4139
static int i945_get_display_clock_speed(struct drm_device *dev)
{
	return 400000;
}
J
Jesse Barnes 已提交
4140

4141
static int i915_get_display_clock_speed(struct drm_device *dev)
J
Jesse Barnes 已提交
4142
{
4143 4144
	return 333000;
}
J
Jesse Barnes 已提交
4145

4146 4147 4148 4149
static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
{
	return 200000;
}
J
Jesse Barnes 已提交
4150

4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174
static int pnv_get_display_clock_speed(struct drm_device *dev)
{
	u16 gcfgc = 0;

	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);

	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
		return 267000;
	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
		return 333000;
	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
		return 444000;
	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
		return 200000;
	default:
		DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
		return 133000;
	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
		return 167000;
	}
}

4175 4176 4177
static int i915gm_get_display_clock_speed(struct drm_device *dev)
{
	u16 gcfgc = 0;
J
Jesse Barnes 已提交
4178

4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);

	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		return 133000;
	else {
		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		case GC_DISPLAY_CLOCK_333_MHZ:
			return 333000;
		default:
		case GC_DISPLAY_CLOCK_190_200_MHZ:
			return 190000;
J
Jesse Barnes 已提交
4190
		}
4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211
	}
}

static int i865_get_display_clock_speed(struct drm_device *dev)
{
	return 266000;
}

static int i855_get_display_clock_speed(struct drm_device *dev)
{
	u16 hpllcc = 0;
	/* Assume that the hardware is in the high speed state.  This
	 * should be the default.
	 */
	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
	case GC_CLOCK_133_200:
	case GC_CLOCK_100_200:
		return 200000;
	case GC_CLOCK_166_250:
		return 250000;
	case GC_CLOCK_100_133:
J
Jesse Barnes 已提交
4212
		return 133000;
4213
	}
J
Jesse Barnes 已提交
4214

4215 4216 4217
	/* Shouldn't happen */
	return 0;
}
J
Jesse Barnes 已提交
4218

4219 4220 4221
static int i830_get_display_clock_speed(struct drm_device *dev)
{
	return 133000;
J
Jesse Barnes 已提交
4222 4223
}

4224
static void
4225
intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4226
{
4227 4228
	while (*num > DATA_LINK_M_N_MASK ||
	       *den > DATA_LINK_M_N_MASK) {
4229 4230 4231 4232 4233
		*num >>= 1;
		*den >>= 1;
	}
}

4234 4235 4236 4237 4238 4239 4240 4241
static void compute_m_n(unsigned int m, unsigned int n,
			uint32_t *ret_m, uint32_t *ret_n)
{
	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
	*ret_m = div_u64((uint64_t) m * *ret_n, n);
	intel_reduce_m_n_ratio(ret_m, ret_n);
}

4242 4243 4244 4245
void
intel_link_compute_m_n(int bits_per_pixel, int nlanes,
		       int pixel_clock, int link_clock,
		       struct intel_link_m_n *m_n)
4246
{
4247
	m_n->tu = 64;
4248 4249 4250 4251 4252 4253 4254

	compute_m_n(bits_per_pixel * pixel_clock,
		    link_clock * nlanes * 8,
		    &m_n->gmch_m, &m_n->gmch_n);

	compute_m_n(pixel_clock, link_clock,
		    &m_n->link_m, &m_n->link_n);
4255 4256
}

4257 4258
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
{
4259 4260
	if (i915_panel_use_ssc >= 0)
		return i915_panel_use_ssc != 0;
4261
	return dev_priv->vbt.lvds_use_ssc
4262
		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4263 4264
}

4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286
static int vlv_get_refclk(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int refclk = 27000; /* for DP & HDMI */

	return 100000; /* only one validated so far */

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		refclk = 96000;
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		if (intel_panel_use_ssc(dev_priv))
			refclk = 100000;
		else
			refclk = 96000;
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		refclk = 100000;
	}

	return refclk;
}

4287 4288 4289 4290 4291 4292
static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int refclk;

4293 4294 4295
	if (IS_VALLEYVIEW(dev)) {
		refclk = vlv_get_refclk(crtc);
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4296
	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4297
		refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
			      refclk / 1000);
	} else if (!IS_GEN2(dev)) {
		refclk = 96000;
	} else {
		refclk = 48000;
	}

	return refclk;
}

4309
static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4310
{
4311
	return (1 << dpll->n) << 16 | dpll->m2;
4312
}
4313

4314 4315 4316
static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
{
	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4317 4318
}

4319
static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4320 4321
				     intel_clock_t *reduced_clock)
{
4322
	struct drm_device *dev = crtc->base.dev;
4323
	struct drm_i915_private *dev_priv = dev->dev_private;
4324
	int pipe = crtc->pipe;
4325 4326 4327
	u32 fp, fp2 = 0;

	if (IS_PINEVIEW(dev)) {
4328
		fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4329
		if (reduced_clock)
4330
			fp2 = pnv_dpll_compute_fp(reduced_clock);
4331
	} else {
4332
		fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4333
		if (reduced_clock)
4334
			fp2 = i9xx_dpll_compute_fp(reduced_clock);
4335 4336 4337
	}

	I915_WRITE(FP0(pipe), fp);
4338
	crtc->config.dpll_hw_state.fp0 = fp;
4339

4340 4341
	crtc->lowfreq_avail = false;
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4342 4343
	    reduced_clock && i915_powersave) {
		I915_WRITE(FP1(pipe), fp2);
4344
		crtc->config.dpll_hw_state.fp1 = fp2;
4345
		crtc->lowfreq_avail = true;
4346 4347
	} else {
		I915_WRITE(FP1(pipe), fp);
4348
		crtc->config.dpll_hw_state.fp1 = fp;
4349 4350 4351
	}
}

4352 4353 4354 4355 4356 4357 4358 4359
static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
{
	u32 reg_val;

	/*
	 * PLLB opamp always calibrates to max value of 0x3f, force enable it
	 * and set it to a reasonable value instead.
	 */
4360
	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4361 4362
	reg_val &= 0xffffff00;
	reg_val |= 0x00000030;
4363
	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4364

4365
	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4366 4367
	reg_val &= 0x8cffffff;
	reg_val = 0x8c000000;
4368
	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4369

4370
	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4371
	reg_val &= 0xffffff00;
4372
	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4373

4374
	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4375 4376
	reg_val &= 0x00ffffff;
	reg_val |= 0xb0000000;
4377
	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4378 4379
}

4380 4381 4382 4383 4384 4385 4386
static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
					 struct intel_link_m_n *m_n)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = crtc->pipe;

4387 4388 4389 4390
	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406
}

static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
					 struct intel_link_m_n *m_n)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = crtc->pipe;
	enum transcoder transcoder = crtc->config.cpu_transcoder;

	if (INTEL_INFO(dev)->gen >= 5) {
		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
	} else {
4407 4408 4409 4410
		I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
		I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
		I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
		I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4411 4412 4413
	}
}

4414 4415 4416 4417 4418 4419 4420 4421
static void intel_dp_set_m_n(struct intel_crtc *crtc)
{
	if (crtc->config.has_pch_encoder)
		intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
	else
		intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
}

4422
static void vlv_update_pll(struct intel_crtc *crtc)
4423
{
4424
	struct drm_device *dev = crtc->base.dev;
4425
	struct drm_i915_private *dev_priv = dev->dev_private;
4426
	int pipe = crtc->pipe;
4427
	u32 dpll, mdiv;
4428
	u32 bestn, bestm1, bestm2, bestp1, bestp2;
4429
	u32 coreclk, reg_val, dpll_md;
4430

4431 4432
	mutex_lock(&dev_priv->dpio_lock);

4433 4434 4435 4436 4437
	bestn = crtc->config.dpll.n;
	bestm1 = crtc->config.dpll.m1;
	bestm2 = crtc->config.dpll.m2;
	bestp1 = crtc->config.dpll.p1;
	bestp2 = crtc->config.dpll.p2;
4438

4439 4440 4441 4442 4443 4444 4445
	/* See eDP HDMI DPIO driver vbios notes doc */

	/* PLL B needs special handling */
	if (pipe)
		vlv_pllb_recal_opamp(dev_priv);

	/* Set up Tx target for periodic Rcomp update */
4446
	vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4447 4448

	/* Disable target IRef on PLL */
4449
	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4450
	reg_val &= 0x00ffffff;
4451
	vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4452 4453

	/* Disable fast lock */
4454
	vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4455 4456

	/* Set idtafcrecal before PLL is enabled */
4457 4458 4459 4460
	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
	mdiv |= ((bestn << DPIO_N_SHIFT));
	mdiv |= (1 << DPIO_K_SHIFT);
4461 4462 4463 4464 4465 4466 4467

	/*
	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
	 * but we don't support that).
	 * Note: don't use the DAC post divider as it seems unstable.
	 */
	mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4468
	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4469 4470

	mdiv |= DPIO_ENABLE_CALIBRATION;
4471
	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4472

4473
	/* Set HBR and RBR LPF coefficients */
4474
	if (crtc->config.port_clock == 162000 ||
4475
	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4476
	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4477
		vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4478
				 0x009f0003);
4479
	else
4480
		vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4481 4482 4483 4484 4485 4486
				 0x00d0000f);

	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
		/* Use SSC source */
		if (!pipe)
4487
			vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4488 4489
					 0x0df40000);
		else
4490
			vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4491 4492 4493 4494
					 0x0df70000);
	} else { /* HDMI or VGA */
		/* Use bend source */
		if (!pipe)
4495
			vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4496 4497
					 0x0df70000);
		else
4498
			vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4499 4500
					 0x0df40000);
	}
4501

4502
	coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4503 4504 4505 4506
	coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
		coreclk |= 0x01000000;
4507
	vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4508

4509
	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4510

4511 4512 4513 4514 4515
	/* Enable DPIO clock input */
	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
	if (pipe)
		dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4516 4517

	dpll |= DPLL_VCO_ENABLE;
4518 4519
	crtc->config.dpll_hw_state.dpll = dpll;

4520 4521
	dpll_md = (crtc->config.pixel_multiplier - 1)
		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
4522 4523
	crtc->config.dpll_hw_state.dpll_md = dpll_md;

4524 4525
	if (crtc->config.has_dp_encoder)
		intel_dp_set_m_n(crtc);
4526 4527

	mutex_unlock(&dev_priv->dpio_lock);
4528 4529
}

4530 4531
static void i9xx_update_pll(struct intel_crtc *crtc,
			    intel_clock_t *reduced_clock,
4532 4533
			    int num_connectors)
{
4534
	struct drm_device *dev = crtc->base.dev;
4535 4536 4537
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpll;
	bool is_sdvo;
4538
	struct dpll *clock = &crtc->config.dpll;
4539

4540
	i9xx_update_pll_dividers(crtc, reduced_clock);
4541

4542 4543
	is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
		intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4544 4545 4546

	dpll = DPLL_VGA_MODE_DIS;

4547
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4548 4549 4550
		dpll |= DPLLB_MODE_LVDS;
	else
		dpll |= DPLLB_MODE_DAC_SERIAL;
4551

4552
	if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4553 4554
		dpll |= (crtc->config.pixel_multiplier - 1)
			<< SDVO_MULTIPLIER_SHIFT_HIRES;
4555
	}
4556 4557

	if (is_sdvo)
4558
		dpll |= DPLL_SDVO_HIGH_SPEED;
4559

4560
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4561
		dpll |= DPLL_SDVO_HIGH_SPEED;
4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587

	/* compute bitmask from p1 value */
	if (IS_PINEVIEW(dev))
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
	else {
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		if (IS_G4X(dev) && reduced_clock)
			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
	}
	switch (clock->p2) {
	case 5:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		break;
	case 7:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
		break;
	case 10:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		break;
	case 14:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
		break;
	}
	if (INTEL_INFO(dev)->gen >= 4)
		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);

4588
	if (crtc->config.sdvo_tv_clock)
4589
		dpll |= PLL_REF_INPUT_TVCLKINBC;
4590
	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4591 4592 4593 4594 4595 4596
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

	dpll |= DPLL_VCO_ENABLE;
4597 4598
	crtc->config.dpll_hw_state.dpll = dpll;

4599
	if (INTEL_INFO(dev)->gen >= 4) {
4600 4601
		u32 dpll_md = (crtc->config.pixel_multiplier - 1)
			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
4602
		crtc->config.dpll_hw_state.dpll_md = dpll_md;
4603
	}
4604 4605 4606

	if (crtc->config.has_dp_encoder)
		intel_dp_set_m_n(crtc);
4607 4608
}

4609 4610
static void i8xx_update_pll(struct intel_crtc *crtc,
			    intel_clock_t *reduced_clock,
4611 4612
			    int num_connectors)
{
4613
	struct drm_device *dev = crtc->base.dev;
4614 4615
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpll;
4616
	struct dpll *clock = &crtc->config.dpll;
4617

4618
	i9xx_update_pll_dividers(crtc, reduced_clock);
4619

4620 4621
	dpll = DPLL_VGA_MODE_DIS;

4622
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4623 4624 4625 4626 4627 4628 4629 4630 4631 4632
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
	} else {
		if (clock->p1 == 2)
			dpll |= PLL_P1_DIVIDE_BY_TWO;
		else
			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		if (clock->p2 == 4)
			dpll |= PLL_P2_DIVIDE_BY_4;
	}

4633 4634 4635
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
		dpll |= DPLL_DVO_2X_MODE;

4636
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4637 4638 4639 4640 4641 4642
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

	dpll |= DPLL_VCO_ENABLE;
4643
	crtc->config.dpll_hw_state.dpll = dpll;
4644 4645
}

4646
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4647 4648 4649 4650
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe = intel_crtc->pipe;
4651
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4652 4653 4654
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;
	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4655 4656 4657 4658 4659 4660
	uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;

	/* We need to be careful not to changed the adjusted mode, for otherwise
	 * the hw state checker will get angry at the mismatch. */
	crtc_vtotal = adjusted_mode->crtc_vtotal;
	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4661 4662 4663

	if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		/* the chip adds 2 halflines automatically */
4664 4665
		crtc_vtotal -= 1;
		crtc_vblank_end -= 1;
4666 4667 4668 4669 4670 4671 4672
		vsyncshift = adjusted_mode->crtc_hsync_start
			     - adjusted_mode->crtc_htotal / 2;
	} else {
		vsyncshift = 0;
	}

	if (INTEL_INFO(dev)->gen > 3)
4673
		I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4674

4675
	I915_WRITE(HTOTAL(cpu_transcoder),
4676 4677
		   (adjusted_mode->crtc_hdisplay - 1) |
		   ((adjusted_mode->crtc_htotal - 1) << 16));
4678
	I915_WRITE(HBLANK(cpu_transcoder),
4679 4680
		   (adjusted_mode->crtc_hblank_start - 1) |
		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
4681
	I915_WRITE(HSYNC(cpu_transcoder),
4682 4683 4684
		   (adjusted_mode->crtc_hsync_start - 1) |
		   ((adjusted_mode->crtc_hsync_end - 1) << 16));

4685
	I915_WRITE(VTOTAL(cpu_transcoder),
4686
		   (adjusted_mode->crtc_vdisplay - 1) |
4687
		   ((crtc_vtotal - 1) << 16));
4688
	I915_WRITE(VBLANK(cpu_transcoder),
4689
		   (adjusted_mode->crtc_vblank_start - 1) |
4690
		   ((crtc_vblank_end - 1) << 16));
4691
	I915_WRITE(VSYNC(cpu_transcoder),
4692 4693 4694
		   (adjusted_mode->crtc_vsync_start - 1) |
		   ((adjusted_mode->crtc_vsync_end - 1) << 16));

4695 4696 4697 4698 4699 4700 4701 4702
	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
	 * bits. */
	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
	    (pipe == PIPE_B || pipe == PIPE_C))
		I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));

4703 4704 4705 4706 4707 4708 4709
	/* pipesrc controls the size that is scaled from, which should
	 * always be the user's requested size.
	 */
	I915_WRITE(PIPESRC(pipe),
		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
}

4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748
static void intel_get_pipe_timings(struct intel_crtc *crtc,
				   struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
	uint32_t tmp;

	tmp = I915_READ(HTOTAL(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
	tmp = I915_READ(HBLANK(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
	tmp = I915_READ(HSYNC(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;

	tmp = I915_READ(VTOTAL(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
	tmp = I915_READ(VBLANK(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
	tmp = I915_READ(VSYNC(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;

	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
		pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
		pipe_config->adjusted_mode.crtc_vtotal += 1;
		pipe_config->adjusted_mode.crtc_vblank_end += 1;
	}

	tmp = I915_READ(PIPESRC(crtc->pipe));
	pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
	pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
}

4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769
static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
					     struct intel_crtc_config *pipe_config)
{
	struct drm_crtc *crtc = &intel_crtc->base;

	crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
	crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
	crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
	crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;

	crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
	crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
	crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
	crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;

	crtc->mode.flags = pipe_config->adjusted_mode.flags;

	crtc->mode.clock = pipe_config->adjusted_mode.clock;
	crtc->mode.flags |= pipe_config->adjusted_mode.flags;
}

4770 4771 4772 4773 4774 4775
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t pipeconf;

4776
	pipeconf = 0;
4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789

	if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		/* Enable pixel doubling when the dot clock is > 90% of the (display)
		 * core speed.
		 *
		 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		 * pipe == 0 check?
		 */
		if (intel_crtc->config.requested_mode.clock >
		    dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
			pipeconf |= PIPECONF_DOUBLE_WIDE;
	}

4790 4791 4792 4793 4794
	/* only g4x and later have fancy bpc/dither controls */
	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
		/* Bspec claims that we can't use dithering for 30bpp pipes. */
		if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
			pipeconf |= PIPECONF_DITHER_EN |
4795 4796
				    PIPECONF_DITHER_TYPE_SP;

4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809
		switch (intel_crtc->config.pipe_bpp) {
		case 18:
			pipeconf |= PIPECONF_6BPC;
			break;
		case 24:
			pipeconf |= PIPECONF_8BPC;
			break;
		case 30:
			pipeconf |= PIPECONF_10BPC;
			break;
		default:
			/* Case prevented by intel_choose_pipe_bpp_dither. */
			BUG();
4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827
		}
	}

	if (HAS_PIPE_CXSR(dev)) {
		if (intel_crtc->lowfreq_avail) {
			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
		} else {
			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
		}
	}

	if (!IS_GEN2(dev) &&
	    intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
	else
		pipeconf |= PIPECONF_PROGRESSIVE;

4828 4829
	if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
		pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4830

4831 4832 4833 4834
	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
	POSTING_READ(PIPECONF(intel_crtc->pipe));
}

4835 4836
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
			      int x, int y,
4837
			      struct drm_framebuffer *fb)
J
Jesse Barnes 已提交
4838 4839 4840 4841
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4842
	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
J
Jesse Barnes 已提交
4843
	int pipe = intel_crtc->pipe;
4844
	int plane = intel_crtc->plane;
4845
	int refclk, num_connectors = 0;
4846
	intel_clock_t clock, reduced_clock;
4847
	u32 dspcntr;
4848 4849
	bool ok, has_reduced_clock = false;
	bool is_lvds = false;
4850
	struct intel_encoder *encoder;
4851
	const intel_limit_t *limit;
4852
	int ret;
J
Jesse Barnes 已提交
4853

4854
	for_each_encoder_on_crtc(dev, crtc, encoder) {
4855
		switch (encoder->type) {
J
Jesse Barnes 已提交
4856 4857 4858 4859
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		}
4860

4861
		num_connectors++;
J
Jesse Barnes 已提交
4862 4863
	}

4864
	refclk = i9xx_get_refclk(crtc, num_connectors);
J
Jesse Barnes 已提交
4865

4866 4867 4868 4869 4870
	/*
	 * Returns a set of divisors for the desired target clock with the given
	 * refclk, or FALSE.  The returned values represent the clock equation:
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
	 */
4871
	limit = intel_limit(crtc, refclk);
4872 4873
	ok = dev_priv->display.find_dpll(limit, crtc,
					 intel_crtc->config.port_clock,
4874 4875
					 refclk, NULL, &clock);
	if (!ok && !intel_crtc->config.clock_set) {
J
Jesse Barnes 已提交
4876
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
4877
		return -EINVAL;
J
Jesse Barnes 已提交
4878 4879
	}

4880
	if (is_lvds && dev_priv->lvds_downclock_avail) {
4881 4882 4883 4884 4885 4886
		/*
		 * Ensure we match the reduced clock's P to the target clock.
		 * If the clocks don't match, we can't switch the display clock
		 * by using the FP0/FP1. In such case we will disable the LVDS
		 * downclock feature.
		*/
4887 4888
		has_reduced_clock =
			dev_priv->display.find_dpll(limit, crtc,
4889
						    dev_priv->lvds_downclock,
4890
						    refclk, &clock,
4891
						    &reduced_clock);
Z
Zhenyu Wang 已提交
4892
	}
4893 4894 4895 4896 4897 4898 4899 4900
	/* Compat-code for transition, will disappear. */
	if (!intel_crtc->config.clock_set) {
		intel_crtc->config.dpll.n = clock.n;
		intel_crtc->config.dpll.m1 = clock.m1;
		intel_crtc->config.dpll.m2 = clock.m2;
		intel_crtc->config.dpll.p1 = clock.p1;
		intel_crtc->config.dpll.p2 = clock.p2;
	}
Z
Zhenyu Wang 已提交
4901

4902
	if (IS_GEN2(dev))
4903
		i8xx_update_pll(intel_crtc,
4904 4905
				has_reduced_clock ? &reduced_clock : NULL,
				num_connectors);
4906
	else if (IS_VALLEYVIEW(dev))
4907
		vlv_update_pll(intel_crtc);
J
Jesse Barnes 已提交
4908
	else
4909
		i9xx_update_pll(intel_crtc,
4910
				has_reduced_clock ? &reduced_clock : NULL,
4911
                                num_connectors);
J
Jesse Barnes 已提交
4912 4913 4914 4915

	/* Set up the display plane register */
	dspcntr = DISPPLANE_GAMMA_ENABLE;

4916 4917 4918 4919 4920 4921
	if (!IS_VALLEYVIEW(dev)) {
		if (pipe == 0)
			dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		else
			dspcntr |= DISPPLANE_SEL_PIPE_B;
	}
J
Jesse Barnes 已提交
4922

4923
	intel_set_pipe_timings(intel_crtc);
4924 4925 4926

	/* pipesrc and dspsize control the size that is scaled from,
	 * which should always be the user's requested size.
J
Jesse Barnes 已提交
4927
	 */
4928 4929 4930 4931
	I915_WRITE(DSPSIZE(plane),
		   ((mode->vdisplay - 1) << 16) |
		   (mode->hdisplay - 1));
	I915_WRITE(DSPPOS(plane), 0);
4932

4933 4934
	i9xx_set_pipeconf(intel_crtc);

4935 4936 4937
	I915_WRITE(DSPCNTR(plane), dspcntr);
	POSTING_READ(DSPCNTR(plane));

4938
	ret = intel_pipe_set_base(crtc, x, y, fb);
4939 4940 4941 4942 4943 4944

	intel_update_watermarks(dev);

	return ret;
}

4945 4946 4947 4948 4949 4950 4951 4952
static void i9xx_get_pfit_config(struct intel_crtc *crtc,
				 struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

	tmp = I915_READ(PFIT_CONTROL);
4953 4954
	if (!(tmp & PFIT_ENABLE))
		return;
4955

4956
	/* Check whether the pfit is attached to our pipe. */
4957 4958 4959 4960 4961 4962 4963 4964
	if (INTEL_INFO(dev)->gen < 4) {
		if (crtc->pipe != PIPE_B)
			return;
	} else {
		if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
			return;
	}

4965
	pipe_config->gmch_pfit.control = tmp;
4966 4967 4968 4969 4970 4971
	pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
	if (INTEL_INFO(dev)->gen < 5)
		pipe_config->gmch_pfit.lvds_border_bits =
			I915_READ(LVDS) & LVDS_BORDER_ENABLE;
}

4972 4973 4974 4975 4976 4977 4978
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
				 struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

4979
	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4980
	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4981

4982 4983 4984 4985
	tmp = I915_READ(PIPECONF(crtc->pipe));
	if (!(tmp & PIPECONF_ENABLE))
		return false;

4986 4987
	intel_get_pipe_timings(crtc, pipe_config);

4988 4989
	i9xx_get_pfit_config(crtc, pipe_config);

4990 4991 4992 4993 4994
	if (INTEL_INFO(dev)->gen >= 4) {
		tmp = I915_READ(DPLL_MD(crtc->pipe));
		pipe_config->pixel_multiplier =
			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4995
		pipe_config->dpll_hw_state.dpll_md = tmp;
4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006
	} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
		tmp = I915_READ(DPLL(crtc->pipe));
		pipe_config->pixel_multiplier =
			((tmp & SDVO_MULTIPLIER_MASK)
			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
	} else {
		/* Note that on i915G/GM the pixel multiplier is in the sdvo
		 * port and will be fixed up in the encoder->get_config
		 * function. */
		pipe_config->pixel_multiplier = 1;
	}
5007 5008 5009 5010
	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
	if (!IS_VALLEYVIEW(dev)) {
		pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
		pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5011 5012 5013 5014 5015
	} else {
		/* Mask out read-only status bits. */
		pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
						     DPLL_PORTC_READY_MASK |
						     DPLL_PORTB_READY_MASK);
5016
	}
5017

5018 5019 5020
	return true;
}

P
Paulo Zanoni 已提交
5021
static void ironlake_init_pch_refclk(struct drm_device *dev)
5022 5023 5024 5025
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
5026
	u32 val, final;
5027
	bool has_lvds = false;
5028 5029
	bool has_cpu_edp = false;
	bool has_panel = false;
5030 5031
	bool has_ck505 = false;
	bool can_ssc = false;
5032 5033

	/* We need to take the global config into account */
5034 5035 5036 5037 5038 5039 5040 5041 5042
	list_for_each_entry(encoder, &mode_config->encoder_list,
			    base.head) {
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			has_panel = true;
			has_lvds = true;
			break;
		case INTEL_OUTPUT_EDP:
			has_panel = true;
5043
			if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5044 5045
				has_cpu_edp = true;
			break;
5046 5047 5048
		}
	}

5049
	if (HAS_PCH_IBX(dev)) {
5050
		has_ck505 = dev_priv->vbt.display_clock_mode;
5051 5052 5053 5054 5055 5056
		can_ssc = has_ck505;
	} else {
		has_ck505 = false;
		can_ssc = true;
	}

5057 5058
	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
		      has_panel, has_lvds, has_ck505);
5059 5060 5061 5062 5063 5064

	/* Ironlake: try to setup display ref clock before DPLL
	 * enabling. This is only under driver's control after
	 * PCH B stepping, previous chipset stepping should be
	 * ignoring this setting.
	 */
5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102
	val = I915_READ(PCH_DREF_CONTROL);

	/* As we must carefully and slowly disable/enable each source in turn,
	 * compute the final state we want first and check if we need to
	 * make any changes at all.
	 */
	final = val;
	final &= ~DREF_NONSPREAD_SOURCE_MASK;
	if (has_ck505)
		final |= DREF_NONSPREAD_CK505_ENABLE;
	else
		final |= DREF_NONSPREAD_SOURCE_ENABLE;

	final &= ~DREF_SSC_SOURCE_MASK;
	final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
	final &= ~DREF_SSC1_ENABLE;

	if (has_panel) {
		final |= DREF_SSC_SOURCE_ENABLE;

		if (intel_panel_use_ssc(dev_priv) && can_ssc)
			final |= DREF_SSC1_ENABLE;

		if (has_cpu_edp) {
			if (intel_panel_use_ssc(dev_priv) && can_ssc)
				final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
			else
				final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		} else
			final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
	} else {
		final |= DREF_SSC_SOURCE_DISABLE;
		final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
	}

	if (final == val)
		return;

5103
	/* Always enable nonspread source */
5104
	val &= ~DREF_NONSPREAD_SOURCE_MASK;
5105

5106
	if (has_ck505)
5107
		val |= DREF_NONSPREAD_CK505_ENABLE;
5108
	else
5109
		val |= DREF_NONSPREAD_SOURCE_ENABLE;
5110

5111
	if (has_panel) {
5112 5113
		val &= ~DREF_SSC_SOURCE_MASK;
		val |= DREF_SSC_SOURCE_ENABLE;
5114

5115
		/* SSC must be turned on before enabling the CPU output  */
5116
		if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5117
			DRM_DEBUG_KMS("Using SSC on panel\n");
5118
			val |= DREF_SSC1_ENABLE;
5119
		} else
5120
			val &= ~DREF_SSC1_ENABLE;
5121 5122

		/* Get SSC going before enabling the outputs */
5123
		I915_WRITE(PCH_DREF_CONTROL, val);
5124 5125 5126
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);

5127
		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5128 5129

		/* Enable CPU source on CPU attached eDP */
5130
		if (has_cpu_edp) {
5131
			if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5132
				DRM_DEBUG_KMS("Using SSC on eDP\n");
5133
				val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5134
			}
5135
			else
5136
				val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5137
		} else
5138
			val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5139

5140
		I915_WRITE(PCH_DREF_CONTROL, val);
5141 5142 5143 5144 5145
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);
	} else {
		DRM_DEBUG_KMS("Disabling SSC entirely\n");

5146
		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5147 5148

		/* Turn off CPU output */
5149
		val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5150

5151
		I915_WRITE(PCH_DREF_CONTROL, val);
5152 5153 5154 5155
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);

		/* Turn off the SSC source */
5156 5157
		val &= ~DREF_SSC_SOURCE_MASK;
		val |= DREF_SSC_SOURCE_DISABLE;
5158 5159

		/* Turn off SSC1 */
5160
		val &= ~DREF_SSC1_ENABLE;
5161

5162
		I915_WRITE(PCH_DREF_CONTROL, val);
5163 5164 5165
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);
	}
5166 5167

	BUG_ON(val != final);
5168 5169
}

5170
static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
P
Paulo Zanoni 已提交
5171
{
5172
	uint32_t tmp;
P
Paulo Zanoni 已提交
5173

5174 5175 5176
	tmp = I915_READ(SOUTH_CHICKEN2);
	tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
	I915_WRITE(SOUTH_CHICKEN2, tmp);
P
Paulo Zanoni 已提交
5177

5178 5179 5180
	if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
			       FDI_MPHY_IOSFSB_RESET_STATUS, 100))
		DRM_ERROR("FDI mPHY reset assert timeout\n");
P
Paulo Zanoni 已提交
5181

5182 5183 5184
	tmp = I915_READ(SOUTH_CHICKEN2);
	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
	I915_WRITE(SOUTH_CHICKEN2, tmp);
P
Paulo Zanoni 已提交
5185

5186 5187 5188
	if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
				FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
		DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5189 5190 5191 5192 5193 5194
}

/* WaMPhyProgramming:hsw */
static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
{
	uint32_t tmp;
P
Paulo Zanoni 已提交
5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216

	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
	tmp &= ~(0xFF << 24);
	tmp |= (0x12 << 24);
	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
	tmp |= (1 << 11);
	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
	tmp |= (1 << 11);
	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
	tmp |= (1 << 24) | (1 << 21) | (1 << 18);
	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
	tmp |= (1 << 24) | (1 << 21) | (1 << 18);
	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);

5217 5218 5219 5220
	tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
	tmp &= ~(7 << 13);
	tmp |= (5 << 13);
	intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
P
Paulo Zanoni 已提交
5221

5222 5223 5224 5225
	tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
	tmp &= ~(7 << 13);
	tmp |= (5 << 13);
	intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
P
Paulo Zanoni 已提交
5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238 5239 5240 5241 5242 5243 5244 5245 5246

	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
	tmp &= ~0xFF;
	tmp |= 0x1C;
	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
	tmp &= ~0xFF;
	tmp |= 0x1C;
	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
	tmp &= ~(0xFF << 16);
	tmp |= (0x1C << 16);
	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
	tmp &= ~(0xFF << 16);
	tmp |= (0x1C << 16);
	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);

5247 5248 5249
	tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
	tmp |= (1 << 27);
	intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
P
Paulo Zanoni 已提交
5250

5251 5252 5253
	tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
	tmp |= (1 << 27);
	intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
P
Paulo Zanoni 已提交
5254

5255 5256 5257 5258
	tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
	tmp &= ~(0xF << 28);
	tmp |= (4 << 28);
	intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
P
Paulo Zanoni 已提交
5259

5260 5261 5262 5263
	tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
	tmp &= ~(0xF << 28);
	tmp |= (4 << 28);
	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5264 5265
}

5266 5267 5268 5269 5270 5271 5272 5273
/* Implements 3 different sequences from BSpec chapter "Display iCLK
 * Programming" based on the parameters passed:
 * - Sequence to enable CLKOUT_DP
 * - Sequence to enable CLKOUT_DP without spread
 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
 */
static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
				 bool with_fdi)
5274 5275
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5276 5277 5278 5279 5280 5281 5282
	uint32_t reg, tmp;

	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
		with_spread = true;
	if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
		 with_fdi, "LP PCH doesn't have FDI\n"))
		with_fdi = false;
5283 5284 5285 5286 5287 5288 5289 5290 5291 5292

	mutex_lock(&dev_priv->dpio_lock);

	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
	tmp &= ~SBI_SSCCTL_DISABLE;
	tmp |= SBI_SSCCTL_PATHALT;
	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);

	udelay(24);

5293 5294 5295 5296
	if (with_spread) {
		tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
		tmp &= ~SBI_SSCCTL_PATHALT;
		intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5297

5298 5299 5300 5301 5302
		if (with_fdi) {
			lpt_reset_fdi_mphy(dev_priv);
			lpt_program_fdi_mphy(dev_priv);
		}
	}
P
Paulo Zanoni 已提交
5303

5304 5305 5306 5307 5308
	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
	       SBI_GEN0 : SBI_DBUFF0;
	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
	tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5309 5310

	mutex_unlock(&dev_priv->dpio_lock);
P
Paulo Zanoni 已提交
5311 5312
}

5313 5314 5315 5316 5317 5318 5319 5320 5321 5322 5323 5324 5325 5326 5327 5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340
/* Sequence to disable CLKOUT_DP */
static void lpt_disable_clkout_dp(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t reg, tmp;

	mutex_lock(&dev_priv->dpio_lock);

	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
	       SBI_GEN0 : SBI_DBUFF0;
	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
	tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);

	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
	if (!(tmp & SBI_SSCCTL_DISABLE)) {
		if (!(tmp & SBI_SSCCTL_PATHALT)) {
			tmp |= SBI_SSCCTL_PATHALT;
			intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
			udelay(32);
		}
		tmp |= SBI_SSCCTL_DISABLE;
		intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
	}

	mutex_unlock(&dev_priv->dpio_lock);
}

5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354
static void lpt_init_pch_refclk(struct drm_device *dev)
{
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
	bool has_vga = false;

	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		switch (encoder->type) {
		case INTEL_OUTPUT_ANALOG:
			has_vga = true;
			break;
		}
	}

5355 5356 5357 5358
	if (has_vga)
		lpt_enable_clkout_dp(dev, true, true);
	else
		lpt_disable_clkout_dp(dev);
5359 5360
}

P
Paulo Zanoni 已提交
5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371
/*
 * Initialize reference clocks when the driver loads
 */
void intel_init_pch_refclk(struct drm_device *dev)
{
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
		ironlake_init_pch_refclk(dev);
	else if (HAS_PCH_LPT(dev))
		lpt_init_pch_refclk(dev);
}

5372 5373 5374 5375 5376 5377 5378 5379
static int ironlake_get_refclk(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
	int num_connectors = 0;
	bool is_lvds = false;

5380
	for_each_encoder_on_crtc(dev, crtc, encoder) {
5381 5382 5383 5384 5385 5386 5387 5388 5389 5390
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		}
		num_connectors++;
	}

	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5391 5392
			      dev_priv->vbt.lvds_ssc_freq);
		return dev_priv->vbt.lvds_ssc_freq * 1000;
5393 5394 5395 5396 5397
	}

	return 120000;
}

5398
static void ironlake_set_pipeconf(struct drm_crtc *crtc)
J
Jesse Barnes 已提交
5399
{
5400
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
J
Jesse Barnes 已提交
5401 5402
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
5403 5404
	uint32_t val;

5405
	val = 0;
5406

5407
	switch (intel_crtc->config.pipe_bpp) {
5408
	case 18:
5409
		val |= PIPECONF_6BPC;
5410 5411
		break;
	case 24:
5412
		val |= PIPECONF_8BPC;
5413 5414
		break;
	case 30:
5415
		val |= PIPECONF_10BPC;
5416 5417
		break;
	case 36:
5418
		val |= PIPECONF_12BPC;
5419 5420
		break;
	default:
5421 5422
		/* Case prevented by intel_choose_pipe_bpp_dither. */
		BUG();
5423 5424
	}

5425
	if (intel_crtc->config.dither)
5426 5427
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);

5428
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5429 5430 5431 5432
		val |= PIPECONF_INTERLACED_ILK;
	else
		val |= PIPECONF_PROGRESSIVE;

5433
	if (intel_crtc->config.limited_color_range)
5434 5435
		val |= PIPECONF_COLOR_RANGE_SELECT;

5436 5437 5438 5439
	I915_WRITE(PIPECONF(pipe), val);
	POSTING_READ(PIPECONF(pipe));
}

5440 5441 5442 5443 5444 5445 5446
/*
 * Set up the pipe CSC unit.
 *
 * Currently only full range RGB to limited range RGB conversion
 * is supported, but eventually this should handle various
 * RGB<->YCbCr scenarios as well.
 */
5447
static void intel_set_pipe_csc(struct drm_crtc *crtc)
5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	uint16_t coeff = 0x7800; /* 1.0 */

	/*
	 * TODO: Check what kind of values actually come out of the pipe
	 * with these coeff/postoff values and adjust to get the best
	 * accuracy. Perhaps we even need to take the bpc value into
	 * consideration.
	 */

5462
	if (intel_crtc->config.limited_color_range)
5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485
		coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */

	/*
	 * GY/GU and RY/RU should be the other way around according
	 * to BSpec, but reality doesn't agree. Just set them up in
	 * a way that results in the correct picture.
	 */
	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);

	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);

	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);

	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);

	if (INTEL_INFO(dev)->gen > 6) {
		uint16_t postoff = 0;

5486
		if (intel_crtc->config.limited_color_range)
5487 5488 5489 5490 5491 5492 5493 5494 5495 5496
			postoff = (16 * (1 << 13) / 255) & 0x1fff;

		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);

		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
	} else {
		uint32_t mode = CSC_MODE_YUV_TO_RGB;

5497
		if (intel_crtc->config.limited_color_range)
5498 5499 5500 5501 5502 5503
			mode |= CSC_BLACK_SCREEN_OFFSET;

		I915_WRITE(PIPE_CSC_MODE(pipe), mode);
	}
}

5504
static void haswell_set_pipeconf(struct drm_crtc *crtc)
P
Paulo Zanoni 已提交
5505 5506 5507
{
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5508
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
P
Paulo Zanoni 已提交
5509 5510
	uint32_t val;

5511
	val = 0;
P
Paulo Zanoni 已提交
5512

5513
	if (intel_crtc->config.dither)
P
Paulo Zanoni 已提交
5514 5515
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);

5516
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
P
Paulo Zanoni 已提交
5517 5518 5519 5520
		val |= PIPECONF_INTERLACED_ILK;
	else
		val |= PIPECONF_PROGRESSIVE;

5521 5522
	I915_WRITE(PIPECONF(cpu_transcoder), val);
	POSTING_READ(PIPECONF(cpu_transcoder));
5523 5524 5525

	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
P
Paulo Zanoni 已提交
5526 5527
}

5528 5529 5530 5531 5532 5533 5534 5535 5536
static bool ironlake_compute_clocks(struct drm_crtc *crtc,
				    intel_clock_t *clock,
				    bool *has_reduced_clock,
				    intel_clock_t *reduced_clock)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	int refclk;
5537
	const intel_limit_t *limit;
5538
	bool ret, is_lvds = false;
J
Jesse Barnes 已提交
5539

5540 5541
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		switch (intel_encoder->type) {
J
Jesse Barnes 已提交
5542 5543 5544 5545 5546 5547
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		}
	}

5548
	refclk = ironlake_get_refclk(crtc);
J
Jesse Barnes 已提交
5549

5550 5551 5552 5553 5554
	/*
	 * Returns a set of divisors for the desired target clock with the given
	 * refclk, or FALSE.  The returned values represent the clock equation:
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
	 */
5555
	limit = intel_limit(crtc, refclk);
5556 5557
	ret = dev_priv->display.find_dpll(limit, crtc,
					  to_intel_crtc(crtc)->config.port_clock,
5558
					  refclk, NULL, clock);
5559 5560
	if (!ret)
		return false;
5561

5562
	if (is_lvds && dev_priv->lvds_downclock_avail) {
5563 5564 5565 5566 5567 5568
		/*
		 * Ensure we match the reduced clock's P to the target clock.
		 * If the clocks don't match, we can't switch the display clock
		 * by using the FP0/FP1. In such case we will disable the LVDS
		 * downclock feature.
		*/
5569 5570 5571 5572 5573
		*has_reduced_clock =
			dev_priv->display.find_dpll(limit, crtc,
						    dev_priv->lvds_downclock,
						    refclk, clock,
						    reduced_clock);
5574
	}
5575

5576 5577 5578
	return true;
}

5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592 5593 5594 5595 5596
static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t temp;

	temp = I915_READ(SOUTH_CHICKEN1);
	if (temp & FDI_BC_BIFURCATION_SELECT)
		return;

	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);

	temp |= FDI_BC_BIFURCATION_SELECT;
	DRM_DEBUG_KMS("enabling fdi C rx\n");
	I915_WRITE(SOUTH_CHICKEN1, temp);
	POSTING_READ(SOUTH_CHICKEN1);
}

5597
static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5598 5599 5600 5601 5602 5603
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	switch (intel_crtc->pipe) {
	case PIPE_A:
5604
		break;
5605
	case PIPE_B:
5606
		if (intel_crtc->config.fdi_lanes > 2)
5607 5608 5609 5610
			WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
		else
			cpt_enable_fdi_bc_bifurcation(dev);

5611
		break;
5612 5613 5614
	case PIPE_C:
		cpt_enable_fdi_bc_bifurcation(dev);

5615
		break;
5616 5617 5618 5619 5620
	default:
		BUG();
	}
}

5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
{
	/*
	 * Account for spread spectrum to avoid
	 * oversubscribing the link. Max center spread
	 * is 2.5%; use 5% for safety's sake.
	 */
	u32 bps = target_clock * bpp * 21 / 20;
	return bps / (link_bw * 8) + 1;
}

5632
static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5633
{
5634
	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5635 5636
}

5637
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5638
				      u32 *fp,
5639
				      intel_clock_t *reduced_clock, u32 *fp2)
J
Jesse Barnes 已提交
5640
{
5641
	struct drm_crtc *crtc = &intel_crtc->base;
J
Jesse Barnes 已提交
5642 5643
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
5644 5645
	struct intel_encoder *intel_encoder;
	uint32_t dpll;
5646
	int factor, num_connectors = 0;
5647
	bool is_lvds = false, is_sdvo = false;
J
Jesse Barnes 已提交
5648

5649 5650
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		switch (intel_encoder->type) {
J
Jesse Barnes 已提交
5651 5652 5653 5654
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_SDVO:
5655
		case INTEL_OUTPUT_HDMI:
J
Jesse Barnes 已提交
5656 5657 5658
			is_sdvo = true;
			break;
		}
5659

5660
		num_connectors++;
J
Jesse Barnes 已提交
5661 5662
	}

5663
	/* Enable autotuning of the PLL clock (if permissible) */
5664 5665 5666
	factor = 21;
	if (is_lvds) {
		if ((intel_panel_use_ssc(dev_priv) &&
5667
		     dev_priv->vbt.lvds_ssc_freq == 100) ||
5668
		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5669
			factor = 25;
5670
	} else if (intel_crtc->config.sdvo_tv_clock)
5671
		factor = 20;
5672

5673
	if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5674
		*fp |= FP_CB_TUNE;
5675

5676 5677 5678
	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
		*fp2 |= FP_CB_TUNE;

5679
	dpll = 0;
5680

5681 5682 5683 5684
	if (is_lvds)
		dpll |= DPLLB_MODE_LVDS;
	else
		dpll |= DPLLB_MODE_DAC_SERIAL;
5685

5686 5687
	dpll |= (intel_crtc->config.pixel_multiplier - 1)
		<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5688 5689

	if (is_sdvo)
5690
		dpll |= DPLL_SDVO_HIGH_SPEED;
5691
	if (intel_crtc->config.has_dp_encoder)
5692
		dpll |= DPLL_SDVO_HIGH_SPEED;
J
Jesse Barnes 已提交
5693

5694
	/* compute bitmask from p1 value */
5695
	dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5696
	/* also FPA1 */
5697
	dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5698

5699
	switch (intel_crtc->config.dpll.p2) {
5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711
	case 5:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		break;
	case 7:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
		break;
	case 10:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		break;
	case 14:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
		break;
J
Jesse Barnes 已提交
5712 5713
	}

5714
	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5715
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
J
Jesse Barnes 已提交
5716 5717 5718
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

5719
	return dpll | DPLL_VCO_ENABLE;
5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732
}

static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
				  int x, int y,
				  struct drm_framebuffer *fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	int num_connectors = 0;
	intel_clock_t clock, reduced_clock;
5733
	u32 dpll = 0, fp = 0, fp2 = 0;
5734
	bool ok, has_reduced_clock = false;
5735
	bool is_lvds = false;
5736
	struct intel_encoder *encoder;
5737
	struct intel_shared_dpll *pll;
5738 5739 5740 5741 5742 5743 5744 5745 5746 5747
	int ret;

	for_each_encoder_on_crtc(dev, crtc, encoder) {
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		}

		num_connectors++;
5748
	}
J
Jesse Barnes 已提交
5749

5750 5751
	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5752

5753
	ok = ironlake_compute_clocks(crtc, &clock,
5754
				     &has_reduced_clock, &reduced_clock);
5755
	if (!ok && !intel_crtc->config.clock_set) {
5756 5757
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
		return -EINVAL;
J
Jesse Barnes 已提交
5758
	}
5759 5760 5761 5762 5763 5764 5765 5766
	/* Compat-code for transition, will disappear. */
	if (!intel_crtc->config.clock_set) {
		intel_crtc->config.dpll.n = clock.n;
		intel_crtc->config.dpll.m1 = clock.m1;
		intel_crtc->config.dpll.m2 = clock.m2;
		intel_crtc->config.dpll.p1 = clock.p1;
		intel_crtc->config.dpll.p2 = clock.p2;
	}
J
Jesse Barnes 已提交
5767

5768
	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5769
	if (intel_crtc->config.has_pch_encoder) {
5770
		fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5771
		if (has_reduced_clock)
5772
			fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5773

5774
		dpll = ironlake_compute_dpll(intel_crtc,
5775 5776 5777
					     &fp, &reduced_clock,
					     has_reduced_clock ? &fp2 : NULL);

5778
		intel_crtc->config.dpll_hw_state.dpll = dpll;
5779 5780 5781 5782 5783 5784
		intel_crtc->config.dpll_hw_state.fp0 = fp;
		if (has_reduced_clock)
			intel_crtc->config.dpll_hw_state.fp1 = fp2;
		else
			intel_crtc->config.dpll_hw_state.fp1 = fp;

5785
		pll = intel_get_shared_dpll(intel_crtc);
5786
		if (pll == NULL) {
5787 5788
			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
					 pipe_name(pipe));
5789 5790
			return -EINVAL;
		}
5791
	} else
D
Daniel Vetter 已提交
5792
		intel_put_shared_dpll(intel_crtc);
J
Jesse Barnes 已提交
5793

5794 5795
	if (intel_crtc->config.has_dp_encoder)
		intel_dp_set_m_n(intel_crtc);
J
Jesse Barnes 已提交
5796

5797 5798 5799 5800
	if (is_lvds && has_reduced_clock && i915_powersave)
		intel_crtc->lowfreq_avail = true;
	else
		intel_crtc->lowfreq_avail = false;
5801 5802 5803 5804

	if (intel_crtc->config.has_pch_encoder) {
		pll = intel_crtc_to_shared_dpll(intel_crtc);

5805 5806
	}

5807
	intel_set_pipe_timings(intel_crtc);
5808

5809 5810 5811 5812
	if (intel_crtc->config.has_pch_encoder) {
		intel_cpu_transcoder_set_m_n(intel_crtc,
					     &intel_crtc->config.fdi_m_n);
	}
5813

5814 5815
	if (IS_IVYBRIDGE(dev))
		ivybridge_update_fdi_bc_bifurcation(intel_crtc);
J
Jesse Barnes 已提交
5816

5817
	ironlake_set_pipeconf(crtc);
J
Jesse Barnes 已提交
5818

5819 5820
	/* Set up the display plane register */
	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5821
	POSTING_READ(DSPCNTR(plane));
J
Jesse Barnes 已提交
5822

5823
	ret = intel_pipe_set_base(crtc, x, y, fb);
5824 5825 5826

	intel_update_watermarks(dev);

5827
	return ret;
J
Jesse Barnes 已提交
5828 5829
}

5830 5831 5832 5833 5834 5835 5836 5837 5838 5839 5840 5841 5842 5843 5844 5845
static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
					struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum transcoder transcoder = pipe_config->cpu_transcoder;

	pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
	pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
	pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
					& ~TU_SIZE_MASK;
	pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
	pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
				   & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
}

5846 5847 5848 5849 5850 5851 5852 5853 5854 5855
static void ironlake_get_pfit_config(struct intel_crtc *crtc,
				     struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

	tmp = I915_READ(PF_CTL(crtc->pipe));

	if (tmp & PF_ENABLE) {
5856
		pipe_config->pch_pfit.enabled = true;
5857 5858
		pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
		pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5859 5860 5861 5862 5863 5864 5865 5866

		/* We currently do not free assignements of panel fitters on
		 * ivb/hsw (since we don't use the higher upscaling modes which
		 * differentiates them) so just WARN about this case for now. */
		if (IS_GEN7(dev)) {
			WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
				PF_PIPE_SEL_IVB(crtc->pipe));
		}
5867
	}
J
Jesse Barnes 已提交
5868 5869
}

5870 5871 5872 5873 5874 5875 5876
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
				     struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

5877
	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5878
	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5879

5880 5881 5882 5883
	tmp = I915_READ(PIPECONF(crtc->pipe));
	if (!(tmp & PIPECONF_ENABLE))
		return false;

5884
	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5885 5886
		struct intel_shared_dpll *pll;

5887 5888
		pipe_config->has_pch_encoder = true;

5889 5890 5891
		tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
5892 5893

		ironlake_get_fdi_m_n_config(crtc, pipe_config);
5894

5895
		if (HAS_PCH_IBX(dev_priv->dev)) {
5896 5897
			pipe_config->shared_dpll =
				(enum intel_dpll_id) crtc->pipe;
5898 5899 5900 5901 5902 5903 5904
		} else {
			tmp = I915_READ(PCH_DPLL_SEL);
			if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
			else
				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
		}
5905 5906 5907 5908 5909

		pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];

		WARN_ON(!pll->get_hw_state(dev_priv, pll,
					   &pipe_config->dpll_hw_state));
5910 5911 5912 5913 5914

		tmp = pipe_config->dpll_hw_state.dpll;
		pipe_config->pixel_multiplier =
			((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
			 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5915 5916
	} else {
		pipe_config->pixel_multiplier = 1;
5917 5918
	}

5919 5920
	intel_get_pipe_timings(crtc, pipe_config);

5921 5922
	ironlake_get_pfit_config(crtc, pipe_config);

5923 5924 5925
	return true;
}

5926 5927 5928 5929 5930 5931
static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
	struct intel_crtc *crtc;
	unsigned long irqflags;
5932
	uint32_t val;
5933 5934 5935 5936 5937 5938 5939 5940 5941 5942 5943 5944 5945 5946 5947 5948 5949 5950 5951 5952 5953 5954 5955 5956 5957

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
		WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
		     pipe_name(crtc->pipe));

	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
	WARN(plls->spll_refcount, "SPLL enabled\n");
	WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
	WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
	WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
	WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
	     "CPU PWM1 enabled\n");
	WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
	     "CPU PWM2 enabled\n");
	WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
	     "PCH PWM1 enabled\n");
	WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
	     "Utility pin enabled\n");
	WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	val = I915_READ(DEIMR);
	WARN((val & ~DE_PCH_EVENT_IVB) != val,
	     "Unexpected DEIMR bits enabled: 0x%x\n", val);
	val = I915_READ(SDEIMR);
5958
	WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
5959 5960 5961 5962 5963 5964 5965 5966 5967 5968 5969 5970 5971 5972 5973 5974 5975 5976 5977 5978 5979 5980 5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994 5995 5996 5997 5998 5999 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009 6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028
	     "Unexpected SDEIMR bits enabled: 0x%x\n", val);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

/*
 * This function implements pieces of two sequences from BSpec:
 * - Sequence for display software to disable LCPLL
 * - Sequence for display software to allow package C8+
 * The steps implemented here are just the steps that actually touch the LCPLL
 * register. Callers should take care of disabling all the display engine
 * functions, doing the mode unset, fixing interrupts, etc.
 */
void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
		       bool switch_to_fclk, bool allow_power_down)
{
	uint32_t val;

	assert_can_disable_lcpll(dev_priv);

	val = I915_READ(LCPLL_CTL);

	if (switch_to_fclk) {
		val |= LCPLL_CD_SOURCE_FCLK;
		I915_WRITE(LCPLL_CTL, val);

		if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
				       LCPLL_CD_SOURCE_FCLK_DONE, 1))
			DRM_ERROR("Switching to FCLK failed\n");

		val = I915_READ(LCPLL_CTL);
	}

	val |= LCPLL_PLL_DISABLE;
	I915_WRITE(LCPLL_CTL, val);
	POSTING_READ(LCPLL_CTL);

	if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
		DRM_ERROR("LCPLL still locked\n");

	val = I915_READ(D_COMP);
	val |= D_COMP_COMP_DISABLE;
	I915_WRITE(D_COMP, val);
	POSTING_READ(D_COMP);
	ndelay(100);

	if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
		DRM_ERROR("D_COMP RCOMP still in progress\n");

	if (allow_power_down) {
		val = I915_READ(LCPLL_CTL);
		val |= LCPLL_POWER_DOWN_ALLOW;
		I915_WRITE(LCPLL_CTL, val);
		POSTING_READ(LCPLL_CTL);
	}
}

/*
 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
 * source.
 */
void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
{
	uint32_t val;

	val = I915_READ(LCPLL_CTL);

	if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
		    LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
		return;

6029 6030 6031 6032
	/* Make sure we're not on PC8 state before disabling PC8, otherwise
	 * we'll hang the machine! */
	dev_priv->uncore.funcs.force_wake_get(dev_priv);

6033 6034 6035
	if (val & LCPLL_POWER_DOWN_ALLOW) {
		val &= ~LCPLL_POWER_DOWN_ALLOW;
		I915_WRITE(LCPLL_CTL, val);
6036
		POSTING_READ(LCPLL_CTL);
6037 6038 6039 6040 6041 6042
	}

	val = I915_READ(D_COMP);
	val |= D_COMP_COMP_FORCE;
	val &= ~D_COMP_COMP_DISABLE;
	I915_WRITE(D_COMP, val);
6043
	POSTING_READ(D_COMP);
6044 6045 6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056 6057 6058 6059 6060

	val = I915_READ(LCPLL_CTL);
	val &= ~LCPLL_PLL_DISABLE;
	I915_WRITE(LCPLL_CTL, val);

	if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
		DRM_ERROR("LCPLL not locked yet\n");

	if (val & LCPLL_CD_SOURCE_FCLK) {
		val = I915_READ(LCPLL_CTL);
		val &= ~LCPLL_CD_SOURCE_FCLK;
		I915_WRITE(LCPLL_CTL, val);

		if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
					LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
			DRM_ERROR("Switching back to LCPLL failed\n");
	}
6061 6062

	dev_priv->uncore.funcs.force_wake_put(dev_priv);
6063 6064
}

6065 6066 6067 6068 6069 6070 6071 6072 6073 6074 6075 6076 6077 6078 6079 6080 6081 6082 6083 6084 6085 6086 6087 6088 6089 6090 6091 6092 6093 6094 6095 6096 6097 6098 6099 6100 6101
void hsw_enable_pc8_work(struct work_struct *__work)
{
	struct drm_i915_private *dev_priv =
		container_of(to_delayed_work(__work), struct drm_i915_private,
			     pc8.enable_work);
	struct drm_device *dev = dev_priv->dev;
	uint32_t val;

	if (dev_priv->pc8.enabled)
		return;

	DRM_DEBUG_KMS("Enabling package C8+\n");

	dev_priv->pc8.enabled = true;

	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		val = I915_READ(SOUTH_DSPCLK_GATE_D);
		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
	}

	lpt_disable_clkout_dp(dev);
	hsw_pc8_disable_interrupts(dev);
	hsw_disable_lcpll(dev_priv, true, true);
}

static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
{
	WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
	WARN(dev_priv->pc8.disable_count < 1,
	     "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);

	dev_priv->pc8.disable_count--;
	if (dev_priv->pc8.disable_count != 0)
		return;

	schedule_delayed_work(&dev_priv->pc8.enable_work,
6102
			      msecs_to_jiffies(i915_pc8_timeout));
6103 6104 6105 6106 6107 6108 6109 6110 6111 6112 6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145 6146 6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161 6162 6163 6164 6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175 6176 6177 6178 6179 6180 6181 6182 6183 6184 6185 6186 6187 6188 6189 6190 6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206 6207 6208 6209 6210 6211 6212 6213 6214 6215 6216 6217 6218 6219 6220 6221 6222
}

static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	uint32_t val;

	WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
	WARN(dev_priv->pc8.disable_count < 0,
	     "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);

	dev_priv->pc8.disable_count++;
	if (dev_priv->pc8.disable_count != 1)
		return;

	cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
	if (!dev_priv->pc8.enabled)
		return;

	DRM_DEBUG_KMS("Disabling package C8+\n");

	hsw_restore_lcpll(dev_priv);
	hsw_pc8_restore_interrupts(dev);
	lpt_init_pch_refclk(dev);

	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		val = I915_READ(SOUTH_DSPCLK_GATE_D);
		val |= PCH_LP_PARTITION_LEVEL_DISABLE;
		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
	}

	intel_prepare_ddi(dev);
	i915_gem_init_swizzling(dev);
	mutex_lock(&dev_priv->rps.hw_lock);
	gen6_update_ring_freq(dev);
	mutex_unlock(&dev_priv->rps.hw_lock);
	dev_priv->pc8.enabled = false;
}

void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
{
	mutex_lock(&dev_priv->pc8.lock);
	__hsw_enable_package_c8(dev_priv);
	mutex_unlock(&dev_priv->pc8.lock);
}

void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
{
	mutex_lock(&dev_priv->pc8.lock);
	__hsw_disable_package_c8(dev_priv);
	mutex_unlock(&dev_priv->pc8.lock);
}

static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_crtc *crtc;
	uint32_t val;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
		if (crtc->base.enabled)
			return false;

	/* This case is still possible since we have the i915.disable_power_well
	 * parameter and also the KVMr or something else might be requesting the
	 * power well. */
	val = I915_READ(HSW_PWR_WELL_DRIVER);
	if (val != 0) {
		DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
		return false;
	}

	return true;
}

/* Since we're called from modeset_global_resources there's no way to
 * symmetrically increase and decrease the refcount, so we use
 * dev_priv->pc8.requirements_met to track whether we already have the refcount
 * or not.
 */
static void hsw_update_package_c8(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool allow;

	if (!i915_enable_pc8)
		return;

	mutex_lock(&dev_priv->pc8.lock);

	allow = hsw_can_enable_package_c8(dev_priv);

	if (allow == dev_priv->pc8.requirements_met)
		goto done;

	dev_priv->pc8.requirements_met = allow;

	if (allow)
		__hsw_enable_package_c8(dev_priv);
	else
		__hsw_disable_package_c8(dev_priv);

done:
	mutex_unlock(&dev_priv->pc8.lock);
}

static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
{
	if (!dev_priv->pc8.gpu_idle) {
		dev_priv->pc8.gpu_idle = true;
		hsw_enable_package_c8(dev_priv);
	}
}

static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
{
	if (dev_priv->pc8.gpu_idle) {
		dev_priv->pc8.gpu_idle = false;
		hsw_disable_package_c8(dev_priv);
	}
6223 6224
}

6225 6226 6227 6228 6229 6230
static void haswell_modeset_global_resources(struct drm_device *dev)
{
	bool enable = false;
	struct intel_crtc *crtc;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6231 6232
		if (!crtc->base.enabled)
			continue;
6233

6234
		if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6235
		    crtc->config.cpu_transcoder != TRANSCODER_EDP)
6236 6237 6238 6239
			enable = true;
	}

	intel_set_power_well(dev, enable);
6240 6241

	hsw_update_package_c8(dev);
6242 6243
}

P
Paulo Zanoni 已提交
6244 6245 6246 6247 6248 6249 6250 6251 6252 6253
static int haswell_crtc_mode_set(struct drm_crtc *crtc,
				 int x, int y,
				 struct drm_framebuffer *fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int plane = intel_crtc->plane;
	int ret;

6254
	if (!intel_ddi_pll_mode_set(crtc))
6255 6256
		return -EINVAL;

6257 6258
	if (intel_crtc->config.has_dp_encoder)
		intel_dp_set_m_n(intel_crtc);
P
Paulo Zanoni 已提交
6259 6260 6261

	intel_crtc->lowfreq_avail = false;

6262
	intel_set_pipe_timings(intel_crtc);
P
Paulo Zanoni 已提交
6263

6264 6265 6266 6267
	if (intel_crtc->config.has_pch_encoder) {
		intel_cpu_transcoder_set_m_n(intel_crtc,
					     &intel_crtc->config.fdi_m_n);
	}
P
Paulo Zanoni 已提交
6268

6269
	haswell_set_pipeconf(crtc);
P
Paulo Zanoni 已提交
6270

6271
	intel_set_pipe_csc(crtc);
6272

P
Paulo Zanoni 已提交
6273
	/* Set up the display plane register */
6274
	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
P
Paulo Zanoni 已提交
6275 6276 6277 6278 6279 6280
	POSTING_READ(DSPCNTR(plane));

	ret = intel_pipe_set_base(crtc, x, y, fb);

	intel_update_watermarks(dev);

6281
	return ret;
J
Jesse Barnes 已提交
6282 6283
}

6284 6285 6286 6287 6288
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
				    struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
6289
	enum intel_display_power_domain pfit_domain;
6290 6291
	uint32_t tmp;

6292
	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6293 6294
	pipe_config->shared_dpll = DPLL_ID_PRIVATE;

6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309 6310 6311 6312 6313 6314 6315 6316
	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
	if (tmp & TRANS_DDI_FUNC_ENABLE) {
		enum pipe trans_edp_pipe;
		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		default:
			WARN(1, "unknown pipe linked to edp transcoder\n");
		case TRANS_DDI_EDP_INPUT_A_ONOFF:
		case TRANS_DDI_EDP_INPUT_A_ON:
			trans_edp_pipe = PIPE_A;
			break;
		case TRANS_DDI_EDP_INPUT_B_ONOFF:
			trans_edp_pipe = PIPE_B;
			break;
		case TRANS_DDI_EDP_INPUT_C_ONOFF:
			trans_edp_pipe = PIPE_C;
			break;
		}

		if (trans_edp_pipe == crtc->pipe)
			pipe_config->cpu_transcoder = TRANSCODER_EDP;
	}

6317
	if (!intel_display_power_enabled(dev,
6318
			POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6319 6320
		return false;

6321
	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6322 6323 6324
	if (!(tmp & PIPECONF_ENABLE))
		return false;

6325
	/*
6326
	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6327 6328 6329
	 * DDI E. So just check whether this pipe is wired to DDI E and whether
	 * the PCH transcoder is on.
	 */
6330
	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6331
	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6332
	    I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6333 6334
		pipe_config->has_pch_encoder = true;

6335 6336 6337
		tmp = I915_READ(FDI_RX_CTL(PIPE_A));
		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
6338 6339

		ironlake_get_fdi_m_n_config(crtc, pipe_config);
6340 6341
	}

6342 6343
	intel_get_pipe_timings(crtc, pipe_config);

6344 6345 6346
	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
	if (intel_display_power_enabled(dev, pfit_domain))
		ironlake_get_pfit_config(crtc, pipe_config);
6347

P
Paulo Zanoni 已提交
6348 6349 6350
	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
				   (I915_READ(IPS_CTL) & IPS_ENABLE);

6351 6352
	pipe_config->pixel_multiplier = 1;

6353 6354 6355
	return true;
}

6356 6357
static int intel_crtc_mode_set(struct drm_crtc *crtc,
			       int x, int y,
6358
			       struct drm_framebuffer *fb)
6359 6360 6361
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
6362
	struct intel_encoder *encoder;
6363
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6364
	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6365
	int pipe = intel_crtc->pipe;
6366 6367
	int ret;

6368
	drm_vblank_pre_modeset(dev, pipe);
6369

6370 6371
	ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);

J
Jesse Barnes 已提交
6372
	drm_vblank_post_modeset(dev, pipe);
6373

6374 6375 6376 6377 6378 6379 6380 6381
	if (ret != 0)
		return ret;

	for_each_encoder_on_crtc(dev, crtc, encoder) {
		DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
			encoder->base.base.id,
			drm_get_encoder_name(&encoder->base),
			mode->base.id, mode->name);
6382
		encoder->mode_set(encoder);
6383 6384 6385
	}

	return 0;
J
Jesse Barnes 已提交
6386 6387
}

6388 6389 6390 6391 6392 6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414 6415 6416
static bool intel_eld_uptodate(struct drm_connector *connector,
			       int reg_eldv, uint32_t bits_eldv,
			       int reg_elda, uint32_t bits_elda,
			       int reg_edid)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t i;

	i = I915_READ(reg_eldv);
	i &= bits_eldv;

	if (!eld[0])
		return !i;

	if (!i)
		return false;

	i = I915_READ(reg_elda);
	i &= ~bits_elda;
	I915_WRITE(reg_elda, i);

	for (i = 0; i < eld[2]; i++)
		if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
			return false;

	return true;
}

6417 6418 6419 6420 6421 6422 6423 6424 6425 6426 6427 6428 6429 6430 6431 6432
static void g4x_write_eld(struct drm_connector *connector,
			  struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t len;
	uint32_t i;

	i = I915_READ(G4X_AUD_VID_DID);

	if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

6433 6434 6435 6436 6437 6438
	if (intel_eld_uptodate(connector,
			       G4X_AUD_CNTL_ST, eldv,
			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
			       G4X_HDMIW_HDMIEDID))
		return;

6439 6440 6441 6442 6443 6444 6445 6446 6447 6448 6449 6450 6451 6452 6453 6454 6455 6456
	i = I915_READ(G4X_AUD_CNTL_ST);
	i &= ~(eldv | G4X_ELD_ADDR);
	len = (i >> 9) & 0x1f;		/* ELD buffer size */
	I915_WRITE(G4X_AUD_CNTL_ST, i);

	if (!eld[0])
		return;

	len = min_t(uint8_t, eld[2], len);
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));

	i = I915_READ(G4X_AUD_CNTL_ST);
	i |= eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, i);
}

6457 6458 6459 6460 6461 6462
static void haswell_write_eld(struct drm_connector *connector,
				     struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	struct drm_device *dev = crtc->dev;
6463
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6464 6465 6466 6467 6468 6469 6470 6471 6472 6473 6474 6475 6476 6477 6478 6479 6480 6481 6482 6483 6484 6485 6486 6487 6488
	uint32_t eldv;
	uint32_t i;
	int len;
	int pipe = to_intel_crtc(crtc)->pipe;
	int tmp;

	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
	int aud_config = HSW_AUD_CFG(pipe);
	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;


	DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");

	/* Audio output enable */
	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
	tmp = I915_READ(aud_cntrl_st2);
	tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
	I915_WRITE(aud_cntrl_st2, tmp);

	/* Wait for 1 vertical blank */
	intel_wait_for_vblank(dev, pipe);

	/* Set ELD valid state */
	tmp = I915_READ(aud_cntrl_st2);
6489
	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6490 6491 6492
	tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
	I915_WRITE(aud_cntrl_st2, tmp);
	tmp = I915_READ(aud_cntrl_st2);
6493
	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6494 6495 6496

	/* Enable HDMI mode */
	tmp = I915_READ(aud_config);
6497
	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6498 6499 6500 6501 6502 6503 6504
	/* clear N_programing_enable and N_value_index */
	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
	I915_WRITE(aud_config, tmp);

	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));

	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6505
	intel_crtc->eld_vld = true;
6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523 6524 6525 6526 6527 6528 6529 6530 6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */
		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
	} else
		I915_WRITE(aud_config, 0);

	if (intel_eld_uptodate(connector,
			       aud_cntrl_st2, eldv,
			       aud_cntl_st, IBX_ELD_ADDRESS,
			       hdmiw_hdmiedid))
		return;

	i = I915_READ(aud_cntrl_st2);
	i &= ~eldv;
	I915_WRITE(aud_cntrl_st2, i);

	if (!eld[0])
		return;

	i = I915_READ(aud_cntl_st);
	i &= ~IBX_ELD_ADDRESS;
	I915_WRITE(aud_cntl_st, i);
	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */
	DRM_DEBUG_DRIVER("port num:%d\n", i);

	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	i = I915_READ(aud_cntrl_st2);
	i |= eldv;
	I915_WRITE(aud_cntrl_st2, i);

}

6544 6545 6546 6547 6548 6549 6550 6551 6552
static void ironlake_write_eld(struct drm_connector *connector,
				     struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t i;
	int len;
	int hdmiw_hdmiedid;
6553
	int aud_config;
6554 6555
	int aud_cntl_st;
	int aud_cntrl_st2;
6556
	int pipe = to_intel_crtc(crtc)->pipe;
6557

6558
	if (HAS_PCH_IBX(connector->dev)) {
6559 6560 6561
		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6562
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6563
	} else {
6564 6565 6566
		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6567
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6568 6569
	}

6570
	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6571 6572

	i = I915_READ(aud_cntl_st);
6573
	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */
6574 6575 6576
	if (!i) {
		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		/* operate blindly on all ports */
6577 6578 6579
		eldv = IBX_ELD_VALIDB;
		eldv |= IBX_ELD_VALIDB << 4;
		eldv |= IBX_ELD_VALIDB << 8;
6580
	} else {
6581
		DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6582
		eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6583 6584
	}

6585 6586 6587
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */
6588 6589 6590
		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
	} else
		I915_WRITE(aud_config, 0);
6591

6592 6593 6594 6595 6596 6597
	if (intel_eld_uptodate(connector,
			       aud_cntrl_st2, eldv,
			       aud_cntl_st, IBX_ELD_ADDRESS,
			       hdmiw_hdmiedid))
		return;

6598 6599 6600 6601 6602 6603 6604 6605
	i = I915_READ(aud_cntrl_st2);
	i &= ~eldv;
	I915_WRITE(aud_cntrl_st2, i);

	if (!eld[0])
		return;

	i = I915_READ(aud_cntl_st);
6606
	i &= ~IBX_ELD_ADDRESS;
6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620 6621 6622 6623 6624 6625 6626 6627 6628 6629 6630 6631 6632 6633 6634 6635 6636 6637 6638 6639 6640 6641 6642
	I915_WRITE(aud_cntl_st, i);

	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	i = I915_READ(aud_cntrl_st2);
	i |= eldv;
	I915_WRITE(aud_cntrl_st2, i);
}

void intel_write_eld(struct drm_encoder *encoder,
		     struct drm_display_mode *mode)
{
	struct drm_crtc *crtc = encoder->crtc;
	struct drm_connector *connector;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	connector = drm_select_eld(encoder, mode);
	if (!connector)
		return;

	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
			 connector->base.id,
			 drm_get_connector_name(connector),
			 connector->encoder->base.id,
			 drm_get_encoder_name(connector->encoder));

	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;

	if (dev_priv->display.write_eld)
		dev_priv->display.write_eld(connector, crtc);
}

J
Jesse Barnes 已提交
6643 6644 6645 6646 6647 6648
/** Loads the palette/gamma unit for the CRTC with the prepared values */
void intel_crtc_load_lut(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
P
Paulo Zanoni 已提交
6649 6650
	enum pipe pipe = intel_crtc->pipe;
	int palreg = PALETTE(pipe);
J
Jesse Barnes 已提交
6651
	int i;
P
Paulo Zanoni 已提交
6652
	bool reenable_ips = false;
J
Jesse Barnes 已提交
6653 6654

	/* The clocks have to be on to load the palette. */
6655
	if (!crtc->enabled || !intel_crtc->active)
J
Jesse Barnes 已提交
6656 6657
		return;

6658 6659 6660
	if (!HAS_PCH_SPLIT(dev_priv->dev))
		assert_pll_enabled(dev_priv, pipe);

6661
	/* use legacy palette for Ironlake */
6662
	if (HAS_PCH_SPLIT(dev))
P
Paulo Zanoni 已提交
6663 6664 6665 6666 6667 6668 6669 6670 6671 6672 6673
		palreg = LGC_PALETTE(pipe);

	/* Workaround : Do not read or write the pipe palette/gamma data while
	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
	 */
	if (intel_crtc->config.ips_enabled &&
	    ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
	     GAMMA_MODE_MODE_SPLIT)) {
		hsw_disable_ips(intel_crtc);
		reenable_ips = true;
	}
6674

J
Jesse Barnes 已提交
6675 6676 6677 6678 6679 6680
	for (i = 0; i < 256; i++) {
		I915_WRITE(palreg + 4 * i,
			   (intel_crtc->lut_r[i] << 16) |
			   (intel_crtc->lut_g[i] << 8) |
			   intel_crtc->lut_b[i]);
	}
P
Paulo Zanoni 已提交
6681 6682 6683

	if (reenable_ips)
		hsw_enable_ips(intel_crtc);
J
Jesse Barnes 已提交
6684 6685
}

6686 6687 6688 6689 6690 6691 6692 6693 6694 6695 6696
static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	bool visible = base != 0;
	u32 cntl;

	if (intel_crtc->cursor_visible == visible)
		return;

6697
	cntl = I915_READ(_CURACNTR);
6698 6699 6700 6701
	if (visible) {
		/* On these chipsets we can only modify the base whilst
		 * the cursor is disabled.
		 */
6702
		I915_WRITE(_CURABASE, base);
6703 6704 6705 6706 6707 6708 6709 6710

		cntl &= ~(CURSOR_FORMAT_MASK);
		/* XXX width must be 64, stride 256 => 0x00 << 28 */
		cntl |= CURSOR_ENABLE |
			CURSOR_GAMMA_ENABLE |
			CURSOR_FORMAT_ARGB;
	} else
		cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6711
	I915_WRITE(_CURACNTR, cntl);
6712 6713 6714 6715 6716 6717 6718 6719 6720 6721 6722 6723 6724

	intel_crtc->cursor_visible = visible;
}

static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool visible = base != 0;

	if (intel_crtc->cursor_visible != visible) {
6725
		uint32_t cntl = I915_READ(CURCNTR(pipe));
6726 6727 6728 6729 6730 6731 6732 6733
		if (base) {
			cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
			cntl |= pipe << 28; /* Connect to correct pipe */
		} else {
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
			cntl |= CURSOR_MODE_DISABLE;
		}
6734
		I915_WRITE(CURCNTR(pipe), cntl);
6735 6736 6737 6738

		intel_crtc->cursor_visible = visible;
	}
	/* and commit changes on next vblank */
6739
	I915_WRITE(CURBASE(pipe), base);
6740 6741
}

J
Jesse Barnes 已提交
6742 6743 6744 6745 6746 6747 6748 6749 6750 6751 6752 6753 6754 6755 6756 6757 6758
static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool visible = base != 0;

	if (intel_crtc->cursor_visible != visible) {
		uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		if (base) {
			cntl &= ~CURSOR_MODE;
			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
		} else {
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
			cntl |= CURSOR_MODE_DISABLE;
		}
6759
		if (IS_HASWELL(dev)) {
6760
			cntl |= CURSOR_PIPE_CSC_ENABLE;
6761 6762
			cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
		}
J
Jesse Barnes 已提交
6763 6764 6765 6766 6767 6768 6769 6770
		I915_WRITE(CURCNTR_IVB(pipe), cntl);

		intel_crtc->cursor_visible = visible;
	}
	/* and commit changes on next vblank */
	I915_WRITE(CURBASE_IVB(pipe), base);
}

6771
/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6772 6773
static void intel_crtc_update_cursor(struct drm_crtc *crtc,
				     bool on)
6774 6775 6776 6777 6778 6779 6780
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int x = intel_crtc->cursor_x;
	int y = intel_crtc->cursor_y;
6781
	u32 base, pos;
6782 6783 6784 6785
	bool visible;

	pos = 0;

6786
	if (on && crtc->enabled && crtc->fb) {
6787 6788 6789 6790 6791 6792 6793 6794 6795 6796 6797 6798 6799 6800 6801 6802 6803 6804 6805 6806 6807 6808 6809 6810 6811 6812 6813 6814
		base = intel_crtc->cursor_addr;
		if (x > (int) crtc->fb->width)
			base = 0;

		if (y > (int) crtc->fb->height)
			base = 0;
	} else
		base = 0;

	if (x < 0) {
		if (x + intel_crtc->cursor_width < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		x = -x;
	}
	pos |= x << CURSOR_X_SHIFT;

	if (y < 0) {
		if (y + intel_crtc->cursor_height < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		y = -y;
	}
	pos |= y << CURSOR_Y_SHIFT;

	visible = base != 0;
6815
	if (!visible && !intel_crtc->cursor_visible)
6816 6817
		return;

6818
	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
J
Jesse Barnes 已提交
6819 6820 6821 6822 6823 6824 6825 6826 6827
		I915_WRITE(CURPOS_IVB(pipe), pos);
		ivb_update_cursor(crtc, base);
	} else {
		I915_WRITE(CURPOS(pipe), pos);
		if (IS_845G(dev) || IS_I865G(dev))
			i845_update_cursor(crtc, base);
		else
			i9xx_update_cursor(crtc, base);
	}
6828 6829
}

J
Jesse Barnes 已提交
6830
static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6831
				 struct drm_file *file,
J
Jesse Barnes 已提交
6832 6833 6834 6835 6836 6837
				 uint32_t handle,
				 uint32_t width, uint32_t height)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6838
	struct drm_i915_gem_object *obj;
6839
	uint32_t addr;
6840
	int ret;
J
Jesse Barnes 已提交
6841 6842 6843

	/* if we want to turn off the cursor ignore width and height */
	if (!handle) {
6844
		DRM_DEBUG_KMS("cursor off\n");
6845
		addr = 0;
6846
		obj = NULL;
6847
		mutex_lock(&dev->struct_mutex);
6848
		goto finish;
J
Jesse Barnes 已提交
6849 6850 6851 6852 6853 6854 6855 6856
	}

	/* Currently we only support 64x64 cursors */
	if (width != 64 || height != 64) {
		DRM_ERROR("we currently only support 64x64 cursors\n");
		return -EINVAL;
	}

6857
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6858
	if (&obj->base == NULL)
J
Jesse Barnes 已提交
6859 6860
		return -ENOENT;

6861
	if (obj->base.size < width * height * 4) {
J
Jesse Barnes 已提交
6862
		DRM_ERROR("buffer is to small\n");
6863 6864
		ret = -ENOMEM;
		goto fail;
J
Jesse Barnes 已提交
6865 6866
	}

6867
	/* we only need to pin inside GTT if cursor is non-phy */
6868
	mutex_lock(&dev->struct_mutex);
6869
	if (!dev_priv->info->cursor_needs_physical) {
6870 6871
		unsigned alignment;

6872 6873 6874 6875 6876 6877
		if (obj->tiling_mode) {
			DRM_ERROR("cursor cannot be tiled\n");
			ret = -EINVAL;
			goto fail_locked;
		}

6878 6879 6880 6881 6882 6883 6884 6885 6886 6887
		/* Note that the w/a also requires 2 PTE of padding following
		 * the bo. We currently fill all unused PTE with the shadow
		 * page and so we should always have valid PTE following the
		 * cursor preventing the VT-d warning.
		 */
		alignment = 0;
		if (need_vtd_wa(dev))
			alignment = 64*1024;

		ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6888 6889
		if (ret) {
			DRM_ERROR("failed to move cursor bo into the GTT\n");
6890
			goto fail_locked;
6891 6892
		}

6893 6894
		ret = i915_gem_object_put_fence(obj);
		if (ret) {
6895
			DRM_ERROR("failed to release fence for cursor");
6896 6897 6898
			goto fail_unpin;
		}

6899
		addr = i915_gem_obj_ggtt_offset(obj);
6900
	} else {
6901
		int align = IS_I830(dev) ? 16 * 1024 : 256;
6902
		ret = i915_gem_attach_phys_object(dev, obj,
6903 6904
						  (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
						  align);
6905 6906
		if (ret) {
			DRM_ERROR("failed to attach phys object\n");
6907
			goto fail_locked;
6908
		}
6909
		addr = obj->phys_obj->handle->busaddr;
6910 6911
	}

6912
	if (IS_GEN2(dev))
J
Jesse Barnes 已提交
6913 6914
		I915_WRITE(CURSIZE, (height << 12) | width);

6915 6916
 finish:
	if (intel_crtc->cursor_bo) {
6917
		if (dev_priv->info->cursor_needs_physical) {
6918
			if (intel_crtc->cursor_bo != obj)
6919 6920
				i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		} else
6921
			i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
6922
		drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6923
	}
6924

6925
	mutex_unlock(&dev->struct_mutex);
6926 6927

	intel_crtc->cursor_addr = addr;
6928
	intel_crtc->cursor_bo = obj;
6929 6930 6931
	intel_crtc->cursor_width = width;
	intel_crtc->cursor_height = height;

6932
	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6933

J
Jesse Barnes 已提交
6934
	return 0;
6935
fail_unpin:
6936
	i915_gem_object_unpin_from_display_plane(obj);
6937
fail_locked:
6938
	mutex_unlock(&dev->struct_mutex);
6939
fail:
6940
	drm_gem_object_unreference_unlocked(&obj->base);
6941
	return ret;
J
Jesse Barnes 已提交
6942 6943 6944 6945 6946 6947
}

static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6948 6949
	intel_crtc->cursor_x = x;
	intel_crtc->cursor_y = y;
6950

6951
	intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
J
Jesse Barnes 已提交
6952 6953 6954 6955 6956 6957 6958 6959 6960 6961 6962 6963 6964 6965 6966

	return 0;
}

/** Sets the color ramps on behalf of RandR */
void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				 u16 blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	intel_crtc->lut_r[regno] = red >> 8;
	intel_crtc->lut_g[regno] = green >> 8;
	intel_crtc->lut_b[regno] = blue >> 8;
}

6967 6968 6969 6970 6971 6972 6973 6974 6975 6976
void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
			     u16 *blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	*red = intel_crtc->lut_r[regno] << 8;
	*green = intel_crtc->lut_g[regno] << 8;
	*blue = intel_crtc->lut_b[regno] << 8;
}

J
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6977
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
J
James Simmons 已提交
6978
				 u16 *blue, uint32_t start, uint32_t size)
J
Jesse Barnes 已提交
6979
{
J
James Simmons 已提交
6980
	int end = (start + size > 256) ? 256 : start + size, i;
J
Jesse Barnes 已提交
6981 6982
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

J
James Simmons 已提交
6983
	for (i = start; i < end; i++) {
J
Jesse Barnes 已提交
6984 6985 6986 6987 6988 6989 6990 6991 6992 6993 6994 6995 6996 6997
		intel_crtc->lut_r[i] = red[i] >> 8;
		intel_crtc->lut_g[i] = green[i] >> 8;
		intel_crtc->lut_b[i] = blue[i] >> 8;
	}

	intel_crtc_load_lut(crtc);
}

/* VESA 640x480x72Hz mode to set on the pipe */
static struct drm_display_mode load_detect_mode = {
	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
};

6998 6999
static struct drm_framebuffer *
intel_framebuffer_create(struct drm_device *dev,
7000
			 struct drm_mode_fb_cmd2 *mode_cmd,
7001 7002 7003 7004 7005 7006 7007 7008 7009 7010 7011 7012 7013 7014 7015 7016 7017 7018 7019 7020 7021 7022 7023 7024 7025 7026 7027 7028 7029 7030 7031 7032 7033 7034 7035 7036 7037 7038 7039 7040 7041
			 struct drm_i915_gem_object *obj)
{
	struct intel_framebuffer *intel_fb;
	int ret;

	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
	if (!intel_fb) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return ERR_PTR(-ENOMEM);
	}

	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
	if (ret) {
		drm_gem_object_unreference_unlocked(&obj->base);
		kfree(intel_fb);
		return ERR_PTR(ret);
	}

	return &intel_fb->base;
}

static u32
intel_framebuffer_pitch_for_width(int width, int bpp)
{
	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
	return ALIGN(pitch, 64);
}

static u32
intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
{
	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
}

static struct drm_framebuffer *
intel_framebuffer_create_for_mode(struct drm_device *dev,
				  struct drm_display_mode *mode,
				  int depth, int bpp)
{
	struct drm_i915_gem_object *obj;
7042
	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7043 7044 7045 7046 7047 7048 7049 7050

	obj = i915_gem_alloc_object(dev,
				    intel_framebuffer_size_for_mode(mode, bpp));
	if (obj == NULL)
		return ERR_PTR(-ENOMEM);

	mode_cmd.width = mode->hdisplay;
	mode_cmd.height = mode->vdisplay;
7051 7052
	mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
								bpp);
7053
	mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7054 7055 7056 7057 7058 7059 7060 7061 7062 7063 7064 7065 7066 7067 7068 7069 7070 7071 7072 7073

	return intel_framebuffer_create(dev, &mode_cmd, obj);
}

static struct drm_framebuffer *
mode_fits_in_fbdev(struct drm_device *dev,
		   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	struct drm_framebuffer *fb;

	if (dev_priv->fbdev == NULL)
		return NULL;

	obj = dev_priv->fbdev->ifb.obj;
	if (obj == NULL)
		return NULL;

	fb = &dev_priv->fbdev->ifb.base;
7074 7075
	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
							       fb->bits_per_pixel))
7076 7077
		return NULL;

7078
	if (obj->base.size < mode->vdisplay * fb->pitches[0])
7079 7080 7081 7082 7083
		return NULL;

	return fb;
}

7084
bool intel_get_load_detect_pipe(struct drm_connector *connector,
7085
				struct drm_display_mode *mode,
7086
				struct intel_load_detect_pipe *old)
J
Jesse Barnes 已提交
7087 7088
{
	struct intel_crtc *intel_crtc;
7089 7090
	struct intel_encoder *intel_encoder =
		intel_attached_encoder(connector);
J
Jesse Barnes 已提交
7091
	struct drm_crtc *possible_crtc;
7092
	struct drm_encoder *encoder = &intel_encoder->base;
J
Jesse Barnes 已提交
7093 7094
	struct drm_crtc *crtc = NULL;
	struct drm_device *dev = encoder->dev;
7095
	struct drm_framebuffer *fb;
J
Jesse Barnes 已提交
7096 7097
	int i = -1;

7098 7099 7100 7101
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector),
		      encoder->base.id, drm_get_encoder_name(encoder));

J
Jesse Barnes 已提交
7102 7103
	/*
	 * Algorithm gets a little messy:
7104
	 *
J
Jesse Barnes 已提交
7105 7106
	 *   - if the connector already has an assigned crtc, use it (but make
	 *     sure it's on first)
7107
	 *
J
Jesse Barnes 已提交
7108 7109 7110 7111 7112 7113 7114
	 *   - try to find the first unused crtc that can drive this connector,
	 *     and use that if we find one
	 */

	/* See if we already have a CRTC for this connector */
	if (encoder->crtc) {
		crtc = encoder->crtc;
7115

7116 7117
		mutex_lock(&crtc->mutex);

7118
		old->dpms_mode = connector->dpms;
7119 7120 7121
		old->load_detect_temp = false;

		/* Make sure the crtc and connector are running */
7122 7123
		if (connector->dpms != DRM_MODE_DPMS_ON)
			connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7124

7125
		return true;
J
Jesse Barnes 已提交
7126 7127 7128 7129 7130 7131 7132 7133 7134 7135 7136 7137 7138 7139 7140 7141 7142
	}

	/* Find an unused one (if possible) */
	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		i++;
		if (!(encoder->possible_crtcs & (1 << i)))
			continue;
		if (!possible_crtc->enabled) {
			crtc = possible_crtc;
			break;
		}
	}

	/*
	 * If we didn't find an unused CRTC, don't use any.
	 */
	if (!crtc) {
7143 7144
		DRM_DEBUG_KMS("no pipe available for load-detect\n");
		return false;
J
Jesse Barnes 已提交
7145 7146
	}

7147
	mutex_lock(&crtc->mutex);
7148 7149
	intel_encoder->new_crtc = to_intel_crtc(crtc);
	to_intel_connector(connector)->new_encoder = intel_encoder;
J
Jesse Barnes 已提交
7150 7151

	intel_crtc = to_intel_crtc(crtc);
7152
	old->dpms_mode = connector->dpms;
7153
	old->load_detect_temp = true;
7154
	old->release_fb = NULL;
J
Jesse Barnes 已提交
7155

7156 7157
	if (!mode)
		mode = &load_detect_mode;
J
Jesse Barnes 已提交
7158

7159 7160 7161 7162 7163 7164 7165
	/* We need a framebuffer large enough to accommodate all accesses
	 * that the plane may generate whilst we perform load detection.
	 * We can not rely on the fbcon either being present (we get called
	 * during its initialisation to detect all boot displays, or it may
	 * not even exist) or that it is large enough to satisfy the
	 * requested mode.
	 */
7166 7167
	fb = mode_fits_in_fbdev(dev, mode);
	if (fb == NULL) {
7168
		DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7169 7170
		fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		old->release_fb = fb;
7171 7172
	} else
		DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7173
	if (IS_ERR(fb)) {
7174
		DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7175
		mutex_unlock(&crtc->mutex);
7176
		return false;
J
Jesse Barnes 已提交
7177 7178
	}

7179
	if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7180
		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7181 7182
		if (old->release_fb)
			old->release_fb->funcs->destroy(old->release_fb);
7183
		mutex_unlock(&crtc->mutex);
7184
		return false;
J
Jesse Barnes 已提交
7185
	}
7186

J
Jesse Barnes 已提交
7187
	/* let the connector get through one full cycle before testing */
7188
	intel_wait_for_vblank(dev, intel_crtc->pipe);
7189
	return true;
J
Jesse Barnes 已提交
7190 7191
}

7192
void intel_release_load_detect_pipe(struct drm_connector *connector,
7193
				    struct intel_load_detect_pipe *old)
J
Jesse Barnes 已提交
7194
{
7195 7196
	struct intel_encoder *intel_encoder =
		intel_attached_encoder(connector);
7197
	struct drm_encoder *encoder = &intel_encoder->base;
7198
	struct drm_crtc *crtc = encoder->crtc;
J
Jesse Barnes 已提交
7199

7200 7201 7202 7203
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector),
		      encoder->base.id, drm_get_encoder_name(encoder));

7204
	if (old->load_detect_temp) {
7205 7206 7207
		to_intel_connector(connector)->new_encoder = NULL;
		intel_encoder->new_crtc = NULL;
		intel_set_mode(crtc, NULL, 0, 0, NULL);
7208

7209 7210 7211 7212
		if (old->release_fb) {
			drm_framebuffer_unregister_private(old->release_fb);
			drm_framebuffer_unreference(old->release_fb);
		}
7213

7214
		mutex_unlock(&crtc->mutex);
7215
		return;
J
Jesse Barnes 已提交
7216 7217
	}

7218
	/* Switch crtc and encoder back off if necessary */
7219 7220
	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		connector->funcs->dpms(connector, old->dpms_mode);
7221 7222

	mutex_unlock(&crtc->mutex);
J
Jesse Barnes 已提交
7223 7224 7225
}

/* Returns the clock of the currently programmed mode of the given pipe. */
7226 7227
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
				struct intel_crtc_config *pipe_config)
J
Jesse Barnes 已提交
7228
{
7229
	struct drm_device *dev = crtc->base.dev;
J
Jesse Barnes 已提交
7230
	struct drm_i915_private *dev_priv = dev->dev_private;
7231
	int pipe = pipe_config->cpu_transcoder;
7232
	u32 dpll = I915_READ(DPLL(pipe));
J
Jesse Barnes 已提交
7233 7234 7235 7236
	u32 fp;
	intel_clock_t clock;

	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7237
		fp = I915_READ(FP0(pipe));
J
Jesse Barnes 已提交
7238
	else
7239
		fp = I915_READ(FP1(pipe));
J
Jesse Barnes 已提交
7240 7241

	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7242 7243 7244
	if (IS_PINEVIEW(dev)) {
		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7245 7246 7247 7248 7249
	} else {
		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
	}

7250
	if (!IS_GEN2(dev)) {
7251 7252 7253
		if (IS_PINEVIEW(dev))
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7254 7255
		else
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
J
Jesse Barnes 已提交
7256 7257 7258 7259 7260 7261 7262 7263 7264 7265 7266 7267
			       DPLL_FPA01_P1_POST_DIV_SHIFT);

		switch (dpll & DPLL_MODE_MASK) {
		case DPLLB_MODE_DAC_SERIAL:
			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
				5 : 10;
			break;
		case DPLLB_MODE_LVDS:
			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
				7 : 14;
			break;
		default:
7268
			DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
J
Jesse Barnes 已提交
7269
				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
7270 7271
			pipe_config->adjusted_mode.clock = 0;
			return;
J
Jesse Barnes 已提交
7272 7273
		}

7274 7275 7276 7277
		if (IS_PINEVIEW(dev))
			pineview_clock(96000, &clock);
		else
			i9xx_clock(96000, &clock);
J
Jesse Barnes 已提交
7278 7279 7280 7281 7282 7283 7284 7285 7286 7287 7288
	} else {
		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);

		if (is_lvds) {
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
				       DPLL_FPA01_P1_POST_DIV_SHIFT);
			clock.p2 = 14;

			if ((dpll & PLL_REF_INPUT_MASK) ==
			    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
				/* XXX: might not be 66MHz */
7289
				i9xx_clock(66000, &clock);
J
Jesse Barnes 已提交
7290
			} else
7291
				i9xx_clock(48000, &clock);
J
Jesse Barnes 已提交
7292 7293 7294 7295 7296 7297 7298 7299 7300 7301 7302 7303
		} else {
			if (dpll & PLL_P1_DIVIDE_BY_TWO)
				clock.p1 = 2;
			else {
				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
			}
			if (dpll & PLL_P2_DIVIDE_BY_4)
				clock.p2 = 4;
			else
				clock.p2 = 2;

7304
			i9xx_clock(48000, &clock);
J
Jesse Barnes 已提交
7305 7306 7307
		}
	}

7308
	pipe_config->adjusted_mode.clock = clock.dot;
7309 7310 7311 7312 7313 7314 7315 7316 7317 7318 7319 7320 7321 7322 7323 7324 7325 7326 7327 7328 7329 7330 7331 7332 7333 7334 7335 7336 7337 7338 7339
}

static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
				    struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
	int link_freq, repeat;
	u64 clock;
	u32 link_m, link_n;

	repeat = pipe_config->pixel_multiplier;

	/*
	 * The calculation for the data clock is:
	 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
	 * But we want to avoid losing precison if possible, so:
	 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
	 *
	 * and the link clock is simpler:
	 * link_clock = (m * link_clock * repeat) / n
	 */

	/*
	 * We need to get the FDI or DP link clock here to derive
	 * the M/N dividers.
	 *
	 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
	 * For DP, it's either 1.62GHz or 2.7GHz.
	 * We do our calculations in 10*MHz since we don't need much precison.
J
Jesse Barnes 已提交
7340
	 */
7341 7342 7343 7344 7345 7346 7347 7348 7349 7350
	if (pipe_config->has_pch_encoder)
		link_freq = intel_fdi_link_freq(dev) * 10000;
	else
		link_freq = pipe_config->port_clock;

	link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
	link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));

	if (!link_m || !link_n)
		return;
J
Jesse Barnes 已提交
7351

7352 7353 7354 7355
	clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
	do_div(clock, link_n);

	pipe_config->adjusted_mode.clock = clock;
J
Jesse Barnes 已提交
7356 7357 7358 7359 7360 7361
}

/** Returns the currently programmed mode of the given pipe. */
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
					     struct drm_crtc *crtc)
{
7362
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
7363
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7364
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
J
Jesse Barnes 已提交
7365
	struct drm_display_mode *mode;
7366
	struct intel_crtc_config pipe_config;
7367 7368 7369 7370
	int htot = I915_READ(HTOTAL(cpu_transcoder));
	int hsync = I915_READ(HSYNC(cpu_transcoder));
	int vtot = I915_READ(VTOTAL(cpu_transcoder));
	int vsync = I915_READ(VSYNC(cpu_transcoder));
J
Jesse Barnes 已提交
7371 7372 7373 7374 7375

	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
	if (!mode)
		return NULL;

7376 7377 7378 7379 7380 7381 7382
	/*
	 * Construct a pipe_config sufficient for getting the clock info
	 * back out of crtc_clock_get.
	 *
	 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
	 * to use a real value here instead.
	 */
7383
	pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7384 7385 7386 7387
	pipe_config.pixel_multiplier = 1;
	i9xx_crtc_clock_get(intel_crtc, &pipe_config);

	mode->clock = pipe_config.adjusted_mode.clock;
J
Jesse Barnes 已提交
7388 7389 7390 7391 7392 7393 7394 7395 7396 7397 7398 7399 7400 7401
	mode->hdisplay = (htot & 0xffff) + 1;
	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
	mode->hsync_start = (hsync & 0xffff) + 1;
	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
	mode->vdisplay = (vtot & 0xffff) + 1;
	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
	mode->vsync_start = (vsync & 0xffff) + 1;
	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;

	drm_mode_set_name(mode);

	return mode;
}

7402
static void intel_increase_pllclock(struct drm_crtc *crtc)
7403 7404 7405 7406 7407
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
7408 7409
	int dpll_reg = DPLL(pipe);
	int dpll;
7410

7411
	if (HAS_PCH_SPLIT(dev))
7412 7413 7414 7415 7416
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

7417
	dpll = I915_READ(dpll_reg);
7418
	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7419
		DRM_DEBUG_DRIVER("upclocking LVDS\n");
7420

7421
		assert_panel_unlocked(dev_priv, pipe);
7422 7423 7424

		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
7425
		intel_wait_for_vblank(dev, pipe);
7426

7427 7428
		dpll = I915_READ(dpll_reg);
		if (dpll & DISPLAY_RATE_SELECT_FPA1)
7429
			DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7430 7431 7432 7433 7434 7435 7436 7437 7438
	}
}

static void intel_decrease_pllclock(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7439
	if (HAS_PCH_SPLIT(dev))
7440 7441 7442 7443 7444 7445 7446 7447 7448 7449
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

	/*
	 * Since this is called by a timer, we should never get here in
	 * the manual case.
	 */
	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7450 7451 7452
		int pipe = intel_crtc->pipe;
		int dpll_reg = DPLL(pipe);
		int dpll;
7453

7454
		DRM_DEBUG_DRIVER("downclocking LVDS\n");
7455

7456
		assert_panel_unlocked(dev_priv, pipe);
7457

7458
		dpll = I915_READ(dpll_reg);
7459 7460
		dpll |= DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
7461
		intel_wait_for_vblank(dev, pipe);
7462 7463
		dpll = I915_READ(dpll_reg);
		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7464
			DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7465 7466 7467 7468
	}

}

7469 7470
void intel_mark_busy(struct drm_device *dev)
{
7471 7472 7473 7474
	struct drm_i915_private *dev_priv = dev->dev_private;

	hsw_package_c8_gpu_busy(dev_priv);
	i915_update_gfx_val(dev_priv);
7475 7476 7477
}

void intel_mark_idle(struct drm_device *dev)
7478
{
7479
	struct drm_i915_private *dev_priv = dev->dev_private;
7480 7481
	struct drm_crtc *crtc;

7482 7483
	hsw_package_c8_gpu_idle(dev_priv);

7484 7485 7486 7487 7488 7489 7490
	if (!i915_powersave)
		return;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (!crtc->fb)
			continue;

7491
		intel_decrease_pllclock(crtc);
7492 7493 7494
	}
}

7495 7496
void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
			struct intel_ring_buffer *ring)
7497
{
7498 7499
	struct drm_device *dev = obj->base.dev;
	struct drm_crtc *crtc;
7500

7501
	if (!i915_powersave)
7502 7503
		return;

7504 7505 7506 7507
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (!crtc->fb)
			continue;

7508 7509 7510 7511 7512 7513
		if (to_intel_framebuffer(crtc->fb)->obj != obj)
			continue;

		intel_increase_pllclock(crtc);
		if (ring && intel_fbc_enabled(dev))
			ring->fbc_dirty = true;
7514 7515 7516
	}
}

J
Jesse Barnes 已提交
7517 7518 7519
static void intel_crtc_destroy(struct drm_crtc *crtc)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7520 7521 7522 7523 7524 7525 7526 7527 7528 7529 7530 7531 7532
	struct drm_device *dev = crtc->dev;
	struct intel_unpin_work *work;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (work) {
		cancel_work_sync(&work->work);
		kfree(work);
	}
J
Jesse Barnes 已提交
7533

7534 7535
	intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);

J
Jesse Barnes 已提交
7536
	drm_crtc_cleanup(crtc);
7537

J
Jesse Barnes 已提交
7538 7539 7540
	kfree(intel_crtc);
}

7541 7542 7543 7544
static void intel_unpin_work_fn(struct work_struct *__work)
{
	struct intel_unpin_work *work =
		container_of(__work, struct intel_unpin_work, work);
7545
	struct drm_device *dev = work->crtc->dev;
7546

7547
	mutex_lock(&dev->struct_mutex);
7548
	intel_unpin_fb_obj(work->old_fb_obj);
7549 7550
	drm_gem_object_unreference(&work->pending_flip_obj->base);
	drm_gem_object_unreference(&work->old_fb_obj->base);
7551

7552 7553 7554 7555 7556 7557
	intel_update_fbc(dev);
	mutex_unlock(&dev->struct_mutex);

	BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
	atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);

7558 7559 7560
	kfree(work);
}

7561
static void do_intel_finish_page_flip(struct drm_device *dev,
7562
				      struct drm_crtc *crtc)
7563 7564 7565 7566 7567 7568 7569 7570 7571 7572 7573 7574
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
	unsigned long flags;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
7575 7576 7577 7578 7579

	/* Ensure we don't miss a work->pending update ... */
	smp_rmb();

	if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7580 7581 7582 7583
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

7584 7585 7586
	/* and that the unpin work is consistent wrt ->pending. */
	smp_rmb();

7587 7588
	intel_crtc->unpin_work = NULL;

7589 7590
	if (work->event)
		drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7591

7592 7593
	drm_vblank_put(dev, intel_crtc->pipe);

7594 7595
	spin_unlock_irqrestore(&dev->event_lock, flags);

7596
	wake_up_all(&dev_priv->pending_flip_queue);
7597 7598

	queue_work(dev_priv->wq, &work->work);
7599 7600

	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7601 7602
}

7603 7604 7605 7606 7607
void intel_finish_page_flip(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];

7608
	do_intel_finish_page_flip(dev, crtc);
7609 7610 7611 7612 7613 7614 7615
}

void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];

7616
	do_intel_finish_page_flip(dev, crtc);
7617 7618
}

7619 7620 7621 7622 7623 7624 7625
void intel_prepare_page_flip(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
	unsigned long flags;

7626 7627 7628 7629
	/* NB: An MMIO update of the plane base pointer will also
	 * generate a page-flip completion irq, i.e. every modeset
	 * is also accompanied by a spurious intel_prepare_page_flip().
	 */
7630
	spin_lock_irqsave(&dev->event_lock, flags);
7631 7632
	if (intel_crtc->unpin_work)
		atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7633 7634 7635
	spin_unlock_irqrestore(&dev->event_lock, flags);
}

7636 7637 7638 7639 7640 7641 7642 7643 7644
inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
{
	/* Ensure that the work item is consistent when activating it ... */
	smp_wmb();
	atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
	/* and that it is marked active as soon as the irq could fire. */
	smp_wmb();
}

7645 7646 7647
static int intel_gen2_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
7648 7649
				 struct drm_i915_gem_object *obj,
				 uint32_t flags)
7650 7651 7652 7653
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	u32 flip_mask;
7654
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7655 7656
	int ret;

7657
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7658
	if (ret)
7659
		goto err;
7660

7661
	ret = intel_ring_begin(ring, 6);
7662
	if (ret)
7663
		goto err_unpin;
7664 7665 7666 7667 7668 7669 7670 7671

	/* Can't queue multiple flips, so wait for the previous
	 * one to finish before executing the next.
	 */
	if (intel_crtc->plane)
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
	else
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7672 7673 7674 7675 7676
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
7677
	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7678
	intel_ring_emit(ring, 0); /* aux display base address, unused */
7679 7680

	intel_mark_page_flip_active(intel_crtc);
7681
	intel_ring_advance(ring);
7682 7683 7684 7685 7686
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7687 7688 7689 7690 7691 7692
	return ret;
}

static int intel_gen3_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
7693 7694
				 struct drm_i915_gem_object *obj,
				 uint32_t flags)
7695 7696 7697 7698
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	u32 flip_mask;
7699
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7700 7701
	int ret;

7702
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7703
	if (ret)
7704
		goto err;
7705

7706
	ret = intel_ring_begin(ring, 6);
7707
	if (ret)
7708
		goto err_unpin;
7709 7710 7711 7712 7713

	if (intel_crtc->plane)
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
	else
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7714 7715 7716 7717 7718
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
7719
	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7720 7721
	intel_ring_emit(ring, MI_NOOP);

7722
	intel_mark_page_flip_active(intel_crtc);
7723
	intel_ring_advance(ring);
7724 7725 7726 7727 7728
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7729 7730 7731 7732 7733 7734
	return ret;
}

static int intel_gen4_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
7735 7736
				 struct drm_i915_gem_object *obj,
				 uint32_t flags)
7737 7738 7739 7740
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	uint32_t pf, pipesrc;
7741
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7742 7743
	int ret;

7744
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7745
	if (ret)
7746
		goto err;
7747

7748
	ret = intel_ring_begin(ring, 4);
7749
	if (ret)
7750
		goto err_unpin;
7751 7752 7753 7754 7755

	/* i965+ uses the linear or tiled offsets from the
	 * Display Registers (which do not change across a page-flip)
	 * so we need only reprogram the base address.
	 */
7756 7757 7758
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
7759
	intel_ring_emit(ring,
7760
			(i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7761
			obj->tiling_mode);
7762 7763 7764 7765 7766 7767 7768

	/* XXX Enabling the panel-fitter across page-flip is so far
	 * untested on non-native modes, so ignore it for now.
	 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
	 */
	pf = 0;
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7769
	intel_ring_emit(ring, pf | pipesrc);
7770 7771

	intel_mark_page_flip_active(intel_crtc);
7772
	intel_ring_advance(ring);
7773 7774 7775 7776 7777
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7778 7779 7780 7781 7782 7783
	return ret;
}

static int intel_gen6_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
7784 7785
				 struct drm_i915_gem_object *obj,
				 uint32_t flags)
7786 7787 7788
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7789
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7790 7791 7792
	uint32_t pf, pipesrc;
	int ret;

7793
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7794
	if (ret)
7795
		goto err;
7796

7797
	ret = intel_ring_begin(ring, 4);
7798
	if (ret)
7799
		goto err_unpin;
7800

7801 7802 7803
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7804
	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7805

7806 7807 7808 7809 7810 7811 7812
	/* Contrary to the suggestions in the documentation,
	 * "Enable Panel Fitter" does not seem to be required when page
	 * flipping with a non-native mode, and worse causes a normal
	 * modeset to fail.
	 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
	 */
	pf = 0;
7813
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7814
	intel_ring_emit(ring, pf | pipesrc);
7815 7816

	intel_mark_page_flip_active(intel_crtc);
7817
	intel_ring_advance(ring);
7818 7819 7820 7821 7822
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7823 7824 7825
	return ret;
}

7826 7827 7828
static int intel_gen7_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
7829 7830
				 struct drm_i915_gem_object *obj,
				 uint32_t flags)
7831 7832 7833
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7834
	struct intel_ring_buffer *ring;
7835
	uint32_t plane_bit = 0;
7836 7837 7838
	int len, ret;

	ring = obj->ring;
7839
	if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
7840
		ring = &dev_priv->ring[BCS];
7841 7842 7843

	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
	if (ret)
7844
		goto err;
7845

7846 7847 7848 7849 7850 7851 7852 7853 7854 7855 7856 7857 7858
	switch(intel_crtc->plane) {
	case PLANE_A:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		break;
	case PLANE_B:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		break;
	case PLANE_C:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		break;
	default:
		WARN_ONCE(1, "unknown plane in flip command\n");
		ret = -ENODEV;
7859
		goto err_unpin;
7860 7861
	}

7862 7863 7864 7865 7866
	len = 4;
	if (ring->id == RCS)
		len += 6;

	ret = intel_ring_begin(ring, len);
7867
	if (ret)
7868
		goto err_unpin;
7869

7870 7871 7872 7873 7874 7875 7876 7877 7878 7879 7880 7881 7882 7883 7884 7885 7886 7887 7888 7889
	/* Unmask the flip-done completion message. Note that the bspec says that
	 * we should do this for both the BCS and RCS, and that we must not unmask
	 * more than one flip event at any time (or ensure that one flip message
	 * can be sent by waiting for flip-done prior to queueing new flips).
	 * Experimentation says that BCS works despite DERRMR masking all
	 * flip-done completion events and that unmasking all planes at once
	 * for the RCS also doesn't appear to drop events. Setting the DERRMR
	 * to zero does lead to lockups within MI_DISPLAY_FLIP.
	 */
	if (ring->id == RCS) {
		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
		intel_ring_emit(ring, DERRMR);
		intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
					DERRMR_PIPEB_PRI_FLIP_DONE |
					DERRMR_PIPEC_PRI_FLIP_DONE));
		intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
		intel_ring_emit(ring, DERRMR);
		intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
	}

7890
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7891
	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7892
	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7893
	intel_ring_emit(ring, (MI_NOOP));
7894 7895

	intel_mark_page_flip_active(intel_crtc);
7896
	intel_ring_advance(ring);
7897 7898 7899 7900 7901
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7902 7903 7904
	return ret;
}

7905 7906 7907
static int intel_default_queue_flip(struct drm_device *dev,
				    struct drm_crtc *crtc,
				    struct drm_framebuffer *fb,
7908 7909
				    struct drm_i915_gem_object *obj,
				    uint32_t flags)
7910 7911 7912 7913
{
	return -ENODEV;
}

7914 7915
static int intel_crtc_page_flip(struct drm_crtc *crtc,
				struct drm_framebuffer *fb,
7916 7917
				struct drm_pending_vblank_event *event,
				uint32_t page_flip_flags)
7918 7919 7920
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
7921 7922
	struct drm_framebuffer *old_fb = crtc->fb;
	struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7923 7924
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
7925
	unsigned long flags;
7926
	int ret;
7927

7928 7929 7930 7931 7932 7933 7934 7935 7936 7937 7938 7939 7940
	/* Can't change pixel format via MI display flips. */
	if (fb->pixel_format != crtc->fb->pixel_format)
		return -EINVAL;

	/*
	 * TILEOFF/LINOFF registers can't be changed via MI display flips.
	 * Note that pitch changes could also affect these register.
	 */
	if (INTEL_INFO(dev)->gen > 3 &&
	    (fb->offsets[0] != crtc->fb->offsets[0] ||
	     fb->pitches[0] != crtc->fb->pitches[0]))
		return -EINVAL;

7941 7942 7943 7944 7945
	work = kzalloc(sizeof *work, GFP_KERNEL);
	if (work == NULL)
		return -ENOMEM;

	work->event = event;
7946
	work->crtc = crtc;
7947
	work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7948 7949
	INIT_WORK(&work->work, intel_unpin_work_fn);

7950 7951 7952 7953
	ret = drm_vblank_get(dev, intel_crtc->pipe);
	if (ret)
		goto free_work;

7954 7955 7956 7957 7958
	/* We borrow the event spin lock for protecting unpin_work */
	spin_lock_irqsave(&dev->event_lock, flags);
	if (intel_crtc->unpin_work) {
		spin_unlock_irqrestore(&dev->event_lock, flags);
		kfree(work);
7959
		drm_vblank_put(dev, intel_crtc->pipe);
7960 7961

		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7962 7963 7964 7965 7966
		return -EBUSY;
	}
	intel_crtc->unpin_work = work;
	spin_unlock_irqrestore(&dev->event_lock, flags);

7967 7968 7969
	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
		flush_workqueue(dev_priv->wq);

7970 7971 7972
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		goto cleanup;
7973

7974
	/* Reference the objects for the scheduled work. */
7975 7976
	drm_gem_object_reference(&work->old_fb_obj->base);
	drm_gem_object_reference(&obj->base);
7977 7978

	crtc->fb = fb;
7979

7980 7981
	work->pending_flip_obj = obj;

7982 7983
	work->enable_stall_check = true;

7984
	atomic_inc(&intel_crtc->unpin_work_count);
7985
	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7986

7987
	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
7988 7989
	if (ret)
		goto cleanup_pending;
7990

7991
	intel_disable_fbc(dev);
7992
	intel_mark_fb_busy(obj, NULL);
7993 7994
	mutex_unlock(&dev->struct_mutex);

7995 7996
	trace_i915_flip_request(intel_crtc->plane, obj);

7997
	return 0;
7998

7999
cleanup_pending:
8000
	atomic_dec(&intel_crtc->unpin_work_count);
8001
	crtc->fb = old_fb;
8002 8003
	drm_gem_object_unreference(&work->old_fb_obj->base);
	drm_gem_object_unreference(&obj->base);
8004 8005
	mutex_unlock(&dev->struct_mutex);

8006
cleanup:
8007 8008 8009 8010
	spin_lock_irqsave(&dev->event_lock, flags);
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

8011 8012
	drm_vblank_put(dev, intel_crtc->pipe);
free_work:
8013 8014 8015
	kfree(work);

	return ret;
8016 8017
}

8018 8019 8020 8021 8022
static struct drm_crtc_helper_funcs intel_helper_funcs = {
	.mode_set_base_atomic = intel_pipe_set_base_atomic,
	.load_lut = intel_crtc_load_lut,
};

8023 8024 8025 8026 8027 8028
static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
				  struct drm_crtc *crtc)
{
	struct drm_device *dev;
	struct drm_crtc *tmp;
	int crtc_mask = 1;
8029

8030
	WARN(!crtc, "checking null crtc?\n");
8031

8032
	dev = crtc->dev;
8033

8034 8035 8036 8037 8038
	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
		if (tmp == crtc)
			break;
		crtc_mask <<= 1;
	}
8039

8040 8041 8042
	if (encoder->possible_crtcs & crtc_mask)
		return true;
	return false;
8043
}
J
Jesse Barnes 已提交
8044

8045 8046 8047 8048 8049 8050 8051
/**
 * intel_modeset_update_staged_output_state
 *
 * Updates the staged output configuration state, e.g. after we've read out the
 * current hw state.
 */
static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8052
{
8053 8054
	struct intel_encoder *encoder;
	struct intel_connector *connector;
8055

8056 8057 8058 8059 8060
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		connector->new_encoder =
			to_intel_encoder(connector->base.encoder);
	}
8061

8062 8063 8064 8065 8066
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		encoder->new_crtc =
			to_intel_crtc(encoder->base.crtc);
	}
8067 8068
}

8069 8070 8071 8072 8073 8074 8075 8076 8077
/**
 * intel_modeset_commit_output_state
 *
 * This function copies the stage display pipe configuration to the real one.
 */
static void intel_modeset_commit_output_state(struct drm_device *dev)
{
	struct intel_encoder *encoder;
	struct intel_connector *connector;
8078

8079 8080 8081 8082
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		connector->base.encoder = &connector->new_encoder->base;
	}
8083

8084 8085 8086 8087 8088 8089
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		encoder->base.crtc = &encoder->new_crtc->base;
	}
}

8090 8091 8092 8093 8094 8095 8096 8097 8098 8099 8100 8101 8102 8103 8104 8105 8106 8107 8108 8109 8110 8111 8112 8113 8114 8115
static void
connected_sink_compute_bpp(struct intel_connector * connector,
			   struct intel_crtc_config *pipe_config)
{
	int bpp = pipe_config->pipe_bpp;

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
		connector->base.base.id,
		drm_get_connector_name(&connector->base));

	/* Don't use an invalid EDID bpc value */
	if (connector->base.display_info.bpc &&
	    connector->base.display_info.bpc * 3 < bpp) {
		DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
			      bpp, connector->base.display_info.bpc*3);
		pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
	}

	/* Clamp bpp to 8 on screens without EDID 1.4 */
	if (connector->base.display_info.bpc == 0 && bpp > 24) {
		DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
			      bpp);
		pipe_config->pipe_bpp = 24;
	}
}

8116
static int
8117 8118 8119
compute_baseline_pipe_bpp(struct intel_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct intel_crtc_config *pipe_config)
8120
{
8121 8122
	struct drm_device *dev = crtc->base.dev;
	struct intel_connector *connector;
8123 8124
	int bpp;

8125 8126
	switch (fb->pixel_format) {
	case DRM_FORMAT_C8:
8127 8128
		bpp = 8*3; /* since we go through a colormap */
		break;
8129 8130 8131 8132 8133 8134
	case DRM_FORMAT_XRGB1555:
	case DRM_FORMAT_ARGB1555:
		/* checked in intel_framebuffer_init already */
		if (WARN_ON(INTEL_INFO(dev)->gen > 3))
			return -EINVAL;
	case DRM_FORMAT_RGB565:
8135 8136
		bpp = 6*3; /* min is 18bpp */
		break;
8137 8138 8139 8140 8141 8142 8143
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
		/* checked in intel_framebuffer_init already */
		if (WARN_ON(INTEL_INFO(dev)->gen < 4))
			return -EINVAL;
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
8144 8145
		bpp = 8*3;
		break;
8146 8147 8148 8149 8150 8151
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
		/* checked in intel_framebuffer_init already */
		if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8152
			return -EINVAL;
8153 8154
		bpp = 10*3;
		break;
8155
	/* TODO: gen4+ supports 16 bpc floating point, too. */
8156 8157 8158 8159 8160 8161 8162 8163 8164
	default:
		DRM_DEBUG_KMS("unsupported depth\n");
		return -EINVAL;
	}

	pipe_config->pipe_bpp = bpp;

	/* Clamp display bpp to EDID value */
	list_for_each_entry(connector, &dev->mode_config.connector_list,
8165
			    base.head) {
8166 8167
		if (!connector->new_encoder ||
		    connector->new_encoder->new_crtc != crtc)
8168 8169
			continue;

8170
		connected_sink_compute_bpp(connector, pipe_config);
8171 8172 8173 8174 8175
	}

	return bpp;
}

8176 8177 8178 8179 8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199
static void intel_dump_pipe_config(struct intel_crtc *crtc,
				   struct intel_crtc_config *pipe_config,
				   const char *context)
{
	DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
		      context, pipe_name(crtc->pipe));

	DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
	DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
		      pipe_config->pipe_bpp, pipe_config->dither);
	DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
		      pipe_config->has_pch_encoder,
		      pipe_config->fdi_lanes,
		      pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
		      pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
		      pipe_config->fdi_m_n.tu);
	DRM_DEBUG_KMS("requested mode:\n");
	drm_mode_debug_printmodeline(&pipe_config->requested_mode);
	DRM_DEBUG_KMS("adjusted mode:\n");
	drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
	DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
		      pipe_config->gmch_pfit.control,
		      pipe_config->gmch_pfit.pgm_ratios,
		      pipe_config->gmch_pfit.lvds_border_bits);
8200
	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8201
		      pipe_config->pch_pfit.pos,
8202 8203
		      pipe_config->pch_pfit.size,
		      pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
P
Paulo Zanoni 已提交
8204
	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8205 8206
}

8207 8208 8209 8210 8211 8212 8213 8214 8215 8216 8217 8218 8219 8220 8221 8222 8223 8224 8225
static bool check_encoder_cloning(struct drm_crtc *crtc)
{
	int num_encoders = 0;
	bool uncloneable_encoders = false;
	struct intel_encoder *encoder;

	list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
			    base.head) {
		if (&encoder->new_crtc->base != crtc)
			continue;

		num_encoders++;
		if (!encoder->cloneable)
			uncloneable_encoders = true;
	}

	return !(num_encoders > 1 && uncloneable_encoders);
}

8226 8227
static struct intel_crtc_config *
intel_modeset_pipe_config(struct drm_crtc *crtc,
8228
			  struct drm_framebuffer *fb,
8229
			  struct drm_display_mode *mode)
8230
{
8231 8232
	struct drm_device *dev = crtc->dev;
	struct intel_encoder *encoder;
8233
	struct intel_crtc_config *pipe_config;
8234 8235
	int plane_bpp, ret = -EINVAL;
	bool retry = true;
8236

8237 8238 8239 8240 8241
	if (!check_encoder_cloning(crtc)) {
		DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
		return ERR_PTR(-EINVAL);
	}

8242 8243
	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
	if (!pipe_config)
8244 8245
		return ERR_PTR(-ENOMEM);

8246 8247
	drm_mode_copy(&pipe_config->adjusted_mode, mode);
	drm_mode_copy(&pipe_config->requested_mode, mode);
8248 8249
	pipe_config->cpu_transcoder =
		(enum transcoder) to_intel_crtc(crtc)->pipe;
8250
	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8251

8252 8253 8254 8255 8256 8257 8258 8259 8260 8261 8262 8263 8264
	/*
	 * Sanitize sync polarity flags based on requested ones. If neither
	 * positive or negative polarity is requested, treat this as meaning
	 * negative polarity.
	 */
	if (!(pipe_config->adjusted_mode.flags &
	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
		pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;

	if (!(pipe_config->adjusted_mode.flags &
	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
		pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;

8265 8266 8267 8268 8269 8270
	/* Compute a starting value for pipe_config->pipe_bpp taking the source
	 * plane pixel format and any sink constraints into account. Returns the
	 * source plane bpp so that dithering can be selected on mismatches
	 * after encoders and crtc also have had their say. */
	plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
					      fb, pipe_config);
8271 8272 8273
	if (plane_bpp < 0)
		goto fail;

8274
encoder_retry:
8275
	/* Ensure the port clock defaults are reset when retrying. */
8276
	pipe_config->port_clock = 0;
8277
	pipe_config->pixel_multiplier = 1;
8278

8279 8280 8281
	/* Fill in default crtc timings, allow encoders to overwrite them. */
	drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);

8282 8283 8284
	/* Pass our mode to the connectors and the CRTC to give them a chance to
	 * adjust it according to limitations or connector properties, and also
	 * a chance to reject the mode entirely.
8285
	 */
8286 8287
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
8288

8289 8290
		if (&encoder->new_crtc->base != crtc)
			continue;
8291

8292 8293
		if (!(encoder->compute_config(encoder, pipe_config))) {
			DRM_DEBUG_KMS("Encoder config failure\n");
8294 8295
			goto fail;
		}
8296
	}
8297

8298 8299 8300 8301 8302
	/* Set default port clock if not overwritten by the encoder. Needs to be
	 * done afterwards in case the encoder adjusts the mode. */
	if (!pipe_config->port_clock)
		pipe_config->port_clock = pipe_config->adjusted_mode.clock;

8303
	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8304
	if (ret < 0) {
8305 8306
		DRM_DEBUG_KMS("CRTC fixup failed\n");
		goto fail;
8307
	}
8308 8309 8310 8311 8312 8313 8314 8315 8316 8317 8318 8319

	if (ret == RETRY) {
		if (WARN(!retry, "loop in pipe configuration computation\n")) {
			ret = -EINVAL;
			goto fail;
		}

		DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
		retry = false;
		goto encoder_retry;
	}

8320 8321 8322 8323
	pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
	DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
		      plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);

8324
	return pipe_config;
8325
fail:
8326
	kfree(pipe_config);
8327
	return ERR_PTR(ret);
8328
}
8329

8330 8331 8332 8333 8334
/* Computes which crtcs are affected and sets the relevant bits in the mask. For
 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
static void
intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
			     unsigned *prepare_pipes, unsigned *disable_pipes)
J
Jesse Barnes 已提交
8335 8336
{
	struct intel_crtc *intel_crtc;
8337 8338 8339 8340
	struct drm_device *dev = crtc->dev;
	struct intel_encoder *encoder;
	struct intel_connector *connector;
	struct drm_crtc *tmp_crtc;
J
Jesse Barnes 已提交
8341

8342
	*disable_pipes = *modeset_pipes = *prepare_pipes = 0;
J
Jesse Barnes 已提交
8343

8344 8345 8346 8347 8348 8349 8350 8351
	/* Check which crtcs have changed outputs connected to them, these need
	 * to be part of the prepare_pipes mask. We don't (yet) support global
	 * modeset across multiple crtcs, so modeset_pipes will only have one
	 * bit set at most. */
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (connector->base.encoder == &connector->new_encoder->base)
			continue;
J
Jesse Barnes 已提交
8352

8353 8354 8355 8356 8357 8358 8359 8360 8361
		if (connector->base.encoder) {
			tmp_crtc = connector->base.encoder->crtc;

			*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
		}

		if (connector->new_encoder)
			*prepare_pipes |=
				1 << connector->new_encoder->new_crtc->pipe;
J
Jesse Barnes 已提交
8362 8363
	}

8364 8365 8366 8367 8368 8369 8370 8371 8372 8373 8374 8375 8376
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		if (encoder->base.crtc == &encoder->new_crtc->base)
			continue;

		if (encoder->base.crtc) {
			tmp_crtc = encoder->base.crtc;

			*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
		}

		if (encoder->new_crtc)
			*prepare_pipes |= 1 << encoder->new_crtc->pipe;
8377 8378
	}

8379 8380 8381 8382
	/* Check for any pipes that will be fully disabled ... */
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
			    base.head) {
		bool used = false;
J
Jesse Barnes 已提交
8383

8384 8385 8386
		/* Don't try to disable disabled crtcs. */
		if (!intel_crtc->base.enabled)
			continue;
8387

8388 8389 8390 8391 8392 8393 8394 8395
		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
				    base.head) {
			if (encoder->new_crtc == intel_crtc)
				used = true;
		}

		if (!used)
			*disable_pipes |= 1 << intel_crtc->pipe;
8396 8397
	}

8398 8399 8400 8401 8402 8403

	/* set_mode is also used to update properties on life display pipes. */
	intel_crtc = to_intel_crtc(crtc);
	if (crtc->enabled)
		*prepare_pipes |= 1 << intel_crtc->pipe;

8404 8405 8406 8407 8408
	/*
	 * For simplicity do a full modeset on any pipe where the output routing
	 * changed. We could be more clever, but that would require us to be
	 * more careful with calling the relevant encoder->mode_set functions.
	 */
8409 8410 8411 8412 8413 8414
	if (*prepare_pipes)
		*modeset_pipes = *prepare_pipes;

	/* ... and mask these out. */
	*modeset_pipes &= ~(*disable_pipes);
	*prepare_pipes &= ~(*disable_pipes);
8415 8416 8417 8418 8419 8420 8421 8422

	/*
	 * HACK: We don't (yet) fully support global modesets. intel_set_config
	 * obies this rule, but the modeset restore mode of
	 * intel_modeset_setup_hw_state does not.
	 */
	*modeset_pipes &= 1 << intel_crtc->pipe;
	*prepare_pipes &= 1 << intel_crtc->pipe;
8423 8424 8425

	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		      *modeset_pipes, *prepare_pipes, *disable_pipes);
8426
}
J
Jesse Barnes 已提交
8427

8428
static bool intel_crtc_in_use(struct drm_crtc *crtc)
8429
{
8430
	struct drm_encoder *encoder;
8431 8432
	struct drm_device *dev = crtc->dev;

8433 8434 8435 8436 8437 8438 8439 8440 8441 8442 8443 8444 8445 8446 8447 8448 8449 8450 8451 8452 8453 8454 8455 8456 8457 8458 8459 8460 8461 8462 8463 8464 8465 8466 8467 8468 8469 8470 8471 8472
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		if (encoder->crtc == crtc)
			return true;

	return false;
}

static void
intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
{
	struct intel_encoder *intel_encoder;
	struct intel_crtc *intel_crtc;
	struct drm_connector *connector;

	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
			    base.head) {
		if (!intel_encoder->base.crtc)
			continue;

		intel_crtc = to_intel_crtc(intel_encoder->base.crtc);

		if (prepare_pipes & (1 << intel_crtc->pipe))
			intel_encoder->connectors_active = false;
	}

	intel_modeset_commit_output_state(dev);

	/* Update computed state. */
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
			    base.head) {
		intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
	}

	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		if (!connector->encoder || !connector->encoder->crtc)
			continue;

		intel_crtc = to_intel_crtc(connector->encoder->crtc);

		if (prepare_pipes & (1 << intel_crtc->pipe)) {
8473 8474 8475
			struct drm_property *dpms_property =
				dev->mode_config.dpms_property;

8476
			connector->dpms = DRM_MODE_DPMS_ON;
8477
			drm_object_property_set_value(&connector->base,
8478 8479
							 dpms_property,
							 DRM_MODE_DPMS_ON);
8480 8481 8482 8483 8484 8485 8486 8487

			intel_encoder = to_intel_encoder(connector->encoder);
			intel_encoder->connectors_active = true;
		}
	}

}

8488 8489 8490 8491 8492 8493 8494 8495 8496 8497 8498 8499 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509
static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
				    struct intel_crtc_config *new)
{
	int clock1, clock2, diff;

	clock1 = cur->adjusted_mode.clock;
	clock2 = new->adjusted_mode.clock;

	if (clock1 == clock2)
		return true;

	if (!clock1 || !clock2)
		return false;

	diff = abs(clock1 - clock2);

	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
		return true;

	return false;
}

8510 8511 8512 8513
#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
	list_for_each_entry((intel_crtc), \
			    &(dev)->mode_config.crtc_list, \
			    base.head) \
8514
		if (mask & (1 <<(intel_crtc)->pipe))
8515

8516
static bool
8517 8518
intel_pipe_config_compare(struct drm_device *dev,
			  struct intel_crtc_config *current_config,
8519 8520
			  struct intel_crtc_config *pipe_config)
{
8521 8522 8523 8524 8525 8526 8527 8528 8529
#define PIPE_CONF_CHECK_X(name)	\
	if (current_config->name != pipe_config->name) { \
		DRM_ERROR("mismatch in " #name " " \
			  "(expected 0x%08x, found 0x%08x)\n", \
			  current_config->name, \
			  pipe_config->name); \
		return false; \
	}

8530 8531 8532 8533 8534 8535 8536
#define PIPE_CONF_CHECK_I(name)	\
	if (current_config->name != pipe_config->name) { \
		DRM_ERROR("mismatch in " #name " " \
			  "(expected %i, found %i)\n", \
			  current_config->name, \
			  pipe_config->name); \
		return false; \
8537 8538
	}

8539 8540
#define PIPE_CONF_CHECK_FLAGS(name, mask)	\
	if ((current_config->name ^ pipe_config->name) & (mask)) { \
8541
		DRM_ERROR("mismatch in " #name "(" #mask ") "	   \
8542 8543 8544 8545 8546 8547
			  "(expected %i, found %i)\n", \
			  current_config->name & (mask), \
			  pipe_config->name & (mask)); \
		return false; \
	}

8548 8549 8550
#define PIPE_CONF_QUIRK(quirk)	\
	((current_config->quirks | pipe_config->quirks) & (quirk))

8551 8552
	PIPE_CONF_CHECK_I(cpu_transcoder);

8553 8554
	PIPE_CONF_CHECK_I(has_pch_encoder);
	PIPE_CONF_CHECK_I(fdi_lanes);
8555 8556 8557 8558 8559
	PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
	PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
	PIPE_CONF_CHECK_I(fdi_m_n.link_m);
	PIPE_CONF_CHECK_I(fdi_m_n.link_n);
	PIPE_CONF_CHECK_I(fdi_m_n.tu);
8560

8561 8562 8563 8564 8565 8566 8567 8568 8569 8570 8571 8572 8573 8574
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);

8575
	PIPE_CONF_CHECK_I(pixel_multiplier);
8576

8577 8578 8579
	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
			      DRM_MODE_FLAG_INTERLACE);

8580 8581 8582 8583 8584 8585 8586 8587 8588 8589
	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
		PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
				      DRM_MODE_FLAG_PHSYNC);
		PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
				      DRM_MODE_FLAG_NHSYNC);
		PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
				      DRM_MODE_FLAG_PVSYNC);
		PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
				      DRM_MODE_FLAG_NVSYNC);
	}
8590

8591 8592 8593
	PIPE_CONF_CHECK_I(requested_mode.hdisplay);
	PIPE_CONF_CHECK_I(requested_mode.vdisplay);

8594 8595 8596 8597 8598
	PIPE_CONF_CHECK_I(gmch_pfit.control);
	/* pfit ratios are autocomputed by the hw on gen4+ */
	if (INTEL_INFO(dev)->gen < 4)
		PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
	PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8599 8600 8601 8602 8603
	PIPE_CONF_CHECK_I(pch_pfit.enabled);
	if (current_config->pch_pfit.enabled) {
		PIPE_CONF_CHECK_I(pch_pfit.pos);
		PIPE_CONF_CHECK_I(pch_pfit.size);
	}
8604

P
Paulo Zanoni 已提交
8605 8606
	PIPE_CONF_CHECK_I(ips_enabled);

8607
	PIPE_CONF_CHECK_I(shared_dpll);
8608
	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8609
	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8610 8611
	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8612

8613
#undef PIPE_CONF_CHECK_X
8614
#undef PIPE_CONF_CHECK_I
8615
#undef PIPE_CONF_CHECK_FLAGS
8616
#undef PIPE_CONF_QUIRK
8617

8618 8619
	if (!IS_HASWELL(dev)) {
		if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8620
			DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8621 8622 8623 8624 8625 8626
				  current_config->adjusted_mode.clock,
				  pipe_config->adjusted_mode.clock);
			return false;
		}
	}

8627 8628 8629
	return true;
}

8630 8631
static void
check_connector_state(struct drm_device *dev)
8632 8633 8634 8635 8636 8637 8638 8639 8640 8641 8642 8643
{
	struct intel_connector *connector;

	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		/* This also checks the encoder/connector hw state with the
		 * ->get_hw_state callbacks. */
		intel_connector_check_state(connector);

		WARN(&connector->new_encoder->base != connector->base.encoder,
		     "connector's staged encoder doesn't match current encoder\n");
	}
8644 8645 8646 8647 8648 8649 8650
}

static void
check_encoder_state(struct drm_device *dev)
{
	struct intel_encoder *encoder;
	struct intel_connector *connector;
8651 8652 8653 8654 8655 8656 8657 8658 8659 8660 8661 8662 8663 8664 8665 8666 8667 8668 8669 8670 8671 8672 8673 8674 8675 8676 8677 8678 8679 8680 8681 8682 8683 8684 8685 8686 8687 8688 8689 8690 8691 8692 8693 8694 8695 8696 8697 8698 8699 8700 8701

	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		bool enabled = false;
		bool active = false;
		enum pipe pipe, tracked_pipe;

		DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base));

		WARN(&encoder->new_crtc->base != encoder->base.crtc,
		     "encoder's stage crtc doesn't match current crtc\n");
		WARN(encoder->connectors_active && !encoder->base.crtc,
		     "encoder's active_connectors set, but no crtc\n");

		list_for_each_entry(connector, &dev->mode_config.connector_list,
				    base.head) {
			if (connector->base.encoder != &encoder->base)
				continue;
			enabled = true;
			if (connector->base.dpms != DRM_MODE_DPMS_OFF)
				active = true;
		}
		WARN(!!encoder->base.crtc != enabled,
		     "encoder's enabled state mismatch "
		     "(expected %i, found %i)\n",
		     !!encoder->base.crtc, enabled);
		WARN(active && !encoder->base.crtc,
		     "active encoder with no crtc\n");

		WARN(encoder->connectors_active != active,
		     "encoder's computed active state doesn't match tracked active state "
		     "(expected %i, found %i)\n", active, encoder->connectors_active);

		active = encoder->get_hw_state(encoder, &pipe);
		WARN(active != encoder->connectors_active,
		     "encoder's hw state doesn't match sw tracking "
		     "(expected %i, found %i)\n",
		     encoder->connectors_active, active);

		if (!encoder->base.crtc)
			continue;

		tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		WARN(active && pipe != tracked_pipe,
		     "active encoder's pipe doesn't match"
		     "(expected %i, found %i)\n",
		     tracked_pipe, pipe);

	}
8702 8703 8704 8705 8706 8707 8708 8709 8710
}

static void
check_crtc_state(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *crtc;
	struct intel_encoder *encoder;
	struct intel_crtc_config pipe_config;
8711 8712 8713 8714 8715 8716

	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
			    base.head) {
		bool enabled = false;
		bool active = false;

8717 8718
		memset(&pipe_config, 0, sizeof(pipe_config));

8719 8720 8721 8722 8723 8724 8725 8726 8727 8728 8729 8730 8731 8732
		DRM_DEBUG_KMS("[CRTC:%d]\n",
			      crtc->base.base.id);

		WARN(crtc->active && !crtc->base.enabled,
		     "active crtc, but not enabled in sw tracking\n");

		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
				    base.head) {
			if (encoder->base.crtc != &crtc->base)
				continue;
			enabled = true;
			if (encoder->connectors_active)
				active = true;
		}
8733

8734 8735 8736 8737 8738 8739 8740
		WARN(active != crtc->active,
		     "crtc's computed active state doesn't match tracked active state "
		     "(expected %i, found %i)\n", active, crtc->active);
		WARN(enabled != crtc->base.enabled,
		     "crtc's computed enabled state doesn't match tracked enabled state "
		     "(expected %i, found %i)\n", enabled, crtc->base.enabled);

8741 8742
		active = dev_priv->display.get_pipe_config(crtc,
							   &pipe_config);
8743 8744 8745 8746 8747

		/* hw state is inconsistent with the pipe A quirk */
		if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
			active = crtc->active;

8748 8749
		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
				    base.head) {
8750
			enum pipe pipe;
8751 8752
			if (encoder->base.crtc != &crtc->base)
				continue;
8753 8754
			if (encoder->get_config &&
			    encoder->get_hw_state(encoder, &pipe))
8755 8756 8757
				encoder->get_config(encoder, &pipe_config);
		}

8758 8759 8760
		if (dev_priv->display.get_clock)
			dev_priv->display.get_clock(crtc, &pipe_config);

8761 8762 8763 8764
		WARN(crtc->active != active,
		     "crtc active state doesn't match with hw state "
		     "(expected %i, found %i)\n", crtc->active, active);

8765 8766 8767 8768 8769 8770 8771 8772
		if (active &&
		    !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
			WARN(1, "pipe state doesn't match!\n");
			intel_dump_pipe_config(crtc, &pipe_config,
					       "[hw state]");
			intel_dump_pipe_config(crtc, &crtc->config,
					       "[sw state]");
		}
8773 8774 8775
	}
}

8776 8777 8778 8779 8780 8781 8782
static void
check_shared_dpll_state(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *crtc;
	struct intel_dpll_hw_state dpll_hw_state;
	int i;
8783 8784 8785 8786 8787 8788 8789 8790 8791 8792 8793 8794 8795 8796 8797 8798 8799

	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
		int enabled_crtcs = 0, active_crtcs = 0;
		bool active;

		memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));

		DRM_DEBUG_KMS("%s\n", pll->name);

		active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);

		WARN(pll->active > pll->refcount,
		     "more active pll users than references: %i vs %i\n",
		     pll->active, pll->refcount);
		WARN(pll->active && !pll->on,
		     "pll in active use but not on in sw tracking\n");
8800 8801
		WARN(pll->on && !pll->active,
		     "pll in on but not on in use in sw tracking\n");
8802 8803 8804 8805 8806 8807 8808 8809 8810 8811 8812 8813 8814 8815 8816 8817 8818
		WARN(pll->on != active,
		     "pll on state mismatch (expected %i, found %i)\n",
		     pll->on, active);

		list_for_each_entry(crtc, &dev->mode_config.crtc_list,
				    base.head) {
			if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
				enabled_crtcs++;
			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
				active_crtcs++;
		}
		WARN(pll->active != active_crtcs,
		     "pll active crtcs mismatch (expected %i, found %i)\n",
		     pll->active, active_crtcs);
		WARN(pll->refcount != enabled_crtcs,
		     "pll enabled crtcs mismatch (expected %i, found %i)\n",
		     pll->refcount, enabled_crtcs);
8819 8820 8821 8822

		WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
				       sizeof(dpll_hw_state)),
		     "pll hw state mismatch\n");
8823
	}
8824 8825
}

8826 8827 8828 8829 8830 8831 8832 8833 8834
void
intel_modeset_check_state(struct drm_device *dev)
{
	check_connector_state(dev);
	check_encoder_state(dev);
	check_crtc_state(dev);
	check_shared_dpll_state(dev);
}

8835 8836 8837
static int __intel_set_mode(struct drm_crtc *crtc,
			    struct drm_display_mode *mode,
			    int x, int y, struct drm_framebuffer *fb)
8838 8839
{
	struct drm_device *dev = crtc->dev;
8840
	drm_i915_private_t *dev_priv = dev->dev_private;
8841 8842
	struct drm_display_mode *saved_mode, *saved_hwmode;
	struct intel_crtc_config *pipe_config = NULL;
8843 8844
	struct intel_crtc *intel_crtc;
	unsigned disable_pipes, prepare_pipes, modeset_pipes;
8845
	int ret = 0;
8846

8847
	saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8848 8849
	if (!saved_mode)
		return -ENOMEM;
8850
	saved_hwmode = saved_mode + 1;
8851

8852
	intel_modeset_affected_pipes(crtc, &modeset_pipes,
8853 8854
				     &prepare_pipes, &disable_pipes);

8855 8856
	*saved_hwmode = crtc->hwmode;
	*saved_mode = crtc->mode;
8857

8858 8859 8860 8861 8862 8863
	/* Hack: Because we don't (yet) support global modeset on multiple
	 * crtcs, we don't keep track of the new mode for more than one crtc.
	 * Hence simply check whether any bit is set in modeset_pipes in all the
	 * pieces of code that are not yet converted to deal with mutliple crtcs
	 * changing their mode at the same time. */
	if (modeset_pipes) {
8864
		pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8865 8866 8867 8868
		if (IS_ERR(pipe_config)) {
			ret = PTR_ERR(pipe_config);
			pipe_config = NULL;

8869
			goto out;
8870
		}
8871 8872
		intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
				       "[modeset]");
8873
	}
8874

8875 8876 8877
	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		intel_crtc_disable(&intel_crtc->base);

8878 8879 8880 8881
	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		if (intel_crtc->base.enabled)
			dev_priv->display.crtc_disable(&intel_crtc->base);
	}
8882

8883 8884
	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
	 * to set it here already despite that we pass it down the callchain.
8885
	 */
8886
	if (modeset_pipes) {
8887
		crtc->mode = *mode;
8888 8889 8890 8891
		/* mode_set/enable/disable functions rely on a correct pipe
		 * config. */
		to_intel_crtc(crtc)->config = *pipe_config;
	}
8892

8893 8894 8895
	/* Only after disabling all output pipelines that will be changed can we
	 * update the the output configuration. */
	intel_modeset_update_state(dev, prepare_pipes);
8896

8897 8898 8899
	if (dev_priv->display.modeset_global_resources)
		dev_priv->display.modeset_global_resources(dev);

8900 8901
	/* Set up the DPLL and any encoders state that needs to adjust or depend
	 * on the DPLL.
8902
	 */
8903
	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8904 8905 8906 8907
		ret = intel_crtc_mode_set(&intel_crtc->base,
					  x, y, fb);
		if (ret)
			goto done;
8908 8909 8910
	}

	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
8911 8912
	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
		dev_priv->display.crtc_enable(&intel_crtc->base);
8913

8914 8915
	if (modeset_pipes) {
		/* Store real post-adjustment hardware mode. */
8916
		crtc->hwmode = pipe_config->adjusted_mode;
8917

8918 8919 8920 8921 8922 8923
		/* Calculate and store various constants which
		 * are later needed by vblank and swap-completion
		 * timestamping. They are derived from true hwmode.
		 */
		drm_calc_timestamping_constants(crtc);
	}
8924 8925 8926

	/* FIXME: add subpixel order */
done:
8927
	if (ret && crtc->enabled) {
8928 8929
		crtc->hwmode = *saved_hwmode;
		crtc->mode = *saved_mode;
8930 8931
	}

8932
out:
8933
	kfree(pipe_config);
8934
	kfree(saved_mode);
8935
	return ret;
8936 8937
}

8938 8939 8940
static int intel_set_mode(struct drm_crtc *crtc,
			  struct drm_display_mode *mode,
			  int x, int y, struct drm_framebuffer *fb)
8941 8942 8943 8944 8945 8946 8947 8948 8949 8950 8951
{
	int ret;

	ret = __intel_set_mode(crtc, mode, x, y, fb);

	if (ret == 0)
		intel_modeset_check_state(crtc->dev);

	return ret;
}

8952 8953 8954 8955 8956
void intel_crtc_restore_mode(struct drm_crtc *crtc)
{
	intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
}

8957 8958
#undef for_each_intel_crtc_masked

8959 8960 8961 8962 8963
static void intel_set_config_free(struct intel_set_config *config)
{
	if (!config)
		return;

8964 8965
	kfree(config->save_connector_encoders);
	kfree(config->save_encoder_crtcs);
8966 8967 8968
	kfree(config);
}

8969 8970 8971 8972 8973 8974 8975
static int intel_set_config_save_state(struct drm_device *dev,
				       struct intel_set_config *config)
{
	struct drm_encoder *encoder;
	struct drm_connector *connector;
	int count;

8976 8977 8978 8979
	config->save_encoder_crtcs =
		kcalloc(dev->mode_config.num_encoder,
			sizeof(struct drm_crtc *), GFP_KERNEL);
	if (!config->save_encoder_crtcs)
8980 8981
		return -ENOMEM;

8982 8983 8984 8985
	config->save_connector_encoders =
		kcalloc(dev->mode_config.num_connector,
			sizeof(struct drm_encoder *), GFP_KERNEL);
	if (!config->save_connector_encoders)
8986 8987 8988 8989 8990 8991 8992 8993
		return -ENOMEM;

	/* Copy data. Note that driver private data is not affected.
	 * Should anything bad happen only the expected state is
	 * restored, not the drivers personal bookkeeping.
	 */
	count = 0;
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8994
		config->save_encoder_crtcs[count++] = encoder->crtc;
8995 8996 8997 8998
	}

	count = 0;
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8999
		config->save_connector_encoders[count++] = connector->encoder;
9000 9001 9002 9003 9004 9005 9006 9007
	}

	return 0;
}

static void intel_set_config_restore_state(struct drm_device *dev,
					   struct intel_set_config *config)
{
9008 9009
	struct intel_encoder *encoder;
	struct intel_connector *connector;
9010 9011 9012
	int count;

	count = 0;
9013 9014 9015
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		encoder->new_crtc =
			to_intel_crtc(config->save_encoder_crtcs[count++]);
9016 9017 9018
	}

	count = 0;
9019 9020 9021
	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		connector->new_encoder =
			to_intel_encoder(config->save_connector_encoders[count++]);
9022 9023 9024
	}
}

9025
static bool
9026
is_crtc_connector_off(struct drm_mode_set *set)
9027 9028 9029
{
	int i;

9030 9031 9032 9033 9034 9035 9036 9037 9038 9039
	if (set->num_connectors == 0)
		return false;

	if (WARN_ON(set->connectors == NULL))
		return false;

	for (i = 0; i < set->num_connectors; i++)
		if (set->connectors[i]->encoder &&
		    set->connectors[i]->encoder->crtc == set->crtc &&
		    set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9040 9041 9042 9043 9044
			return true;

	return false;
}

9045 9046 9047 9048 9049 9050 9051
static void
intel_set_config_compute_mode_changes(struct drm_mode_set *set,
				      struct intel_set_config *config)
{

	/* We should be able to check here if the fb has the same properties
	 * and then just flip_or_move it */
9052 9053
	if (is_crtc_connector_off(set)) {
		config->mode_changed = true;
9054
	} else if (set->crtc->fb != set->fb) {
9055 9056
		/* If we have no fb then treat it as a full mode set */
		if (set->crtc->fb == NULL) {
9057 9058 9059 9060 9061 9062 9063 9064 9065 9066
			struct intel_crtc *intel_crtc =
				to_intel_crtc(set->crtc);

			if (intel_crtc->active && i915_fastboot) {
				DRM_DEBUG_KMS("crtc has no fb, will flip\n");
				config->fb_changed = true;
			} else {
				DRM_DEBUG_KMS("inactive crtc, full mode set\n");
				config->mode_changed = true;
			}
9067 9068
		} else if (set->fb == NULL) {
			config->mode_changed = true;
9069 9070
		} else if (set->fb->pixel_format !=
			   set->crtc->fb->pixel_format) {
9071
			config->mode_changed = true;
9072
		} else {
9073
			config->fb_changed = true;
9074
		}
9075 9076
	}

9077
	if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9078 9079 9080 9081 9082 9083 9084 9085
		config->fb_changed = true;

	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		DRM_DEBUG_KMS("modes are different, full mode set\n");
		drm_mode_debug_printmodeline(&set->crtc->mode);
		drm_mode_debug_printmodeline(set->mode);
		config->mode_changed = true;
	}
9086 9087 9088

	DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
			set->crtc->base.id, config->mode_changed, config->fb_changed);
9089 9090
}

9091
static int
9092 9093 9094
intel_modeset_stage_output_state(struct drm_device *dev,
				 struct drm_mode_set *set,
				 struct intel_set_config *config)
9095
{
9096
	struct drm_crtc *new_crtc;
9097 9098
	struct intel_connector *connector;
	struct intel_encoder *encoder;
9099
	int ro;
9100

9101
	/* The upper layers ensure that we either disable a crtc or have a list
9102 9103 9104 9105 9106 9107 9108 9109
	 * of connectors. For paranoia, double-check this. */
	WARN_ON(!set->fb && (set->num_connectors != 0));
	WARN_ON(set->fb && (set->num_connectors == 0));

	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		/* Otherwise traverse passed in connector list and get encoders
		 * for them. */
9110
		for (ro = 0; ro < set->num_connectors; ro++) {
9111 9112
			if (set->connectors[ro] == &connector->base) {
				connector->new_encoder = connector->encoder;
9113 9114 9115 9116
				break;
			}
		}

9117 9118 9119 9120 9121 9122 9123 9124 9125 9126 9127 9128 9129 9130 9131
		/* If we disable the crtc, disable all its connectors. Also, if
		 * the connector is on the changing crtc but not on the new
		 * connector list, disable it. */
		if ((!set->fb || ro == set->num_connectors) &&
		    connector->base.encoder &&
		    connector->base.encoder->crtc == set->crtc) {
			connector->new_encoder = NULL;

			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
				connector->base.base.id,
				drm_get_connector_name(&connector->base));
		}


		if (&connector->new_encoder->base != connector->base.encoder) {
9132
			DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9133
			config->mode_changed = true;
9134 9135
		}
	}
9136
	/* connector->new_encoder is now updated for all connectors. */
9137

9138 9139 9140 9141
	/* Update crtc of enabled connectors. */
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (!connector->new_encoder)
9142 9143
			continue;

9144
		new_crtc = connector->new_encoder->base.crtc;
9145 9146

		for (ro = 0; ro < set->num_connectors; ro++) {
9147
			if (set->connectors[ro] == &connector->base)
9148 9149 9150 9151
				new_crtc = set->crtc;
		}

		/* Make sure the new CRTC will work with the encoder */
9152 9153
		if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
					   new_crtc)) {
9154
			return -EINVAL;
9155
		}
9156 9157 9158 9159 9160 9161 9162 9163 9164 9165 9166 9167 9168 9169 9170 9171 9172 9173 9174 9175 9176 9177 9178 9179 9180
		connector->encoder->new_crtc = to_intel_crtc(new_crtc);

		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
			connector->base.base.id,
			drm_get_connector_name(&connector->base),
			new_crtc->base.id);
	}

	/* Check for any encoders that needs to be disabled. */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		list_for_each_entry(connector,
				    &dev->mode_config.connector_list,
				    base.head) {
			if (connector->new_encoder == encoder) {
				WARN_ON(!connector->new_encoder->new_crtc);

				goto next_encoder;
			}
		}
		encoder->new_crtc = NULL;
next_encoder:
		/* Only now check for crtc changes so we don't miss encoders
		 * that will be disabled. */
		if (&encoder->new_crtc->base != encoder->base.crtc) {
9181
			DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9182
			config->mode_changed = true;
9183 9184
		}
	}
9185
	/* Now we've also updated encoder->new_crtc for all encoders. */
9186

9187 9188 9189 9190 9191 9192 9193 9194 9195 9196
	return 0;
}

static int intel_crtc_set_config(struct drm_mode_set *set)
{
	struct drm_device *dev;
	struct drm_mode_set save_set;
	struct intel_set_config *config;
	int ret;

9197 9198 9199
	BUG_ON(!set);
	BUG_ON(!set->crtc);
	BUG_ON(!set->crtc->helper_private);
9200

9201 9202 9203
	/* Enforce sane interface api - has been abused by the fb helper. */
	BUG_ON(!set->mode && set->fb);
	BUG_ON(set->fb && set->num_connectors == 0);
9204

9205 9206 9207 9208 9209 9210 9211 9212 9213 9214 9215 9216 9217 9218 9219 9220 9221 9222 9223 9224 9225 9226 9227 9228 9229 9230 9231 9232 9233 9234 9235
	if (set->fb) {
		DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
				set->crtc->base.id, set->fb->base.id,
				(int)set->num_connectors, set->x, set->y);
	} else {
		DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
	}

	dev = set->crtc->dev;

	ret = -ENOMEM;
	config = kzalloc(sizeof(*config), GFP_KERNEL);
	if (!config)
		goto out_config;

	ret = intel_set_config_save_state(dev, config);
	if (ret)
		goto out_config;

	save_set.crtc = set->crtc;
	save_set.mode = &set->crtc->mode;
	save_set.x = set->crtc->x;
	save_set.y = set->crtc->y;
	save_set.fb = set->crtc->fb;

	/* Compute whether we need a full modeset, only an fb base update or no
	 * change at all. In the future we might also check whether only the
	 * mode changed, e.g. for LVDS where we only change the panel fitter in
	 * such cases. */
	intel_set_config_compute_mode_changes(set, config);

9236
	ret = intel_modeset_stage_output_state(dev, set, config);
9237 9238 9239
	if (ret)
		goto fail;

9240
	if (config->mode_changed) {
9241 9242
		ret = intel_set_mode(set->crtc, set->mode,
				     set->x, set->y, set->fb);
9243
	} else if (config->fb_changed) {
9244 9245
		intel_crtc_wait_for_pending_flips(set->crtc);

D
Daniel Vetter 已提交
9246
		ret = intel_pipe_set_base(set->crtc,
9247
					  set->x, set->y, set->fb);
9248 9249
	}

9250
	if (ret) {
9251 9252
		DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
			      set->crtc->base.id, ret);
9253
fail:
9254
		intel_set_config_restore_state(dev, config);
9255

9256 9257 9258 9259 9260 9261
		/* Try to restore the config */
		if (config->mode_changed &&
		    intel_set_mode(save_set.crtc, save_set.mode,
				   save_set.x, save_set.y, save_set.fb))
			DRM_ERROR("failed to restore config after modeset failure\n");
	}
9262

9263 9264
out_config:
	intel_set_config_free(config);
9265 9266
	return ret;
}
9267 9268 9269 9270 9271

static const struct drm_crtc_funcs intel_crtc_funcs = {
	.cursor_set = intel_crtc_cursor_set,
	.cursor_move = intel_crtc_cursor_move,
	.gamma_set = intel_crtc_gamma_set,
9272
	.set_config = intel_crtc_set_config,
9273 9274 9275 9276
	.destroy = intel_crtc_destroy,
	.page_flip = intel_crtc_page_flip,
};

P
Paulo Zanoni 已提交
9277 9278
static void intel_cpu_pll_init(struct drm_device *dev)
{
P
Paulo Zanoni 已提交
9279
	if (HAS_DDI(dev))
P
Paulo Zanoni 已提交
9280 9281 9282
		intel_ddi_pll_init(dev);
}

9283 9284 9285
static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
				      struct intel_shared_dpll *pll,
				      struct intel_dpll_hw_state *hw_state)
9286
{
9287
	uint32_t val;
9288

9289
	val = I915_READ(PCH_DPLL(pll->id));
9290 9291 9292
	hw_state->dpll = val;
	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9293 9294 9295 9296

	return val & DPLL_VCO_ENABLE;
}

9297 9298 9299 9300 9301 9302 9303
static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
				  struct intel_shared_dpll *pll)
{
	I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
	I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
}

9304 9305 9306 9307 9308 9309
static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
				struct intel_shared_dpll *pll)
{
	/* PCH refclock must be enabled first */
	assert_pch_refclk_enabled(dev_priv);

9310 9311 9312 9313 9314 9315 9316 9317 9318 9319 9320 9321 9322
	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);

	/* Wait for the clocks to stabilize. */
	POSTING_READ(PCH_DPLL(pll->id));
	udelay(150);

	/* The pixel multiplier can only be updated once the
	 * DPLL is enabled and the clocks are stable.
	 *
	 * So write it again.
	 */
	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
	POSTING_READ(PCH_DPLL(pll->id));
9323 9324 9325 9326 9327 9328 9329 9330 9331 9332 9333 9334 9335
	udelay(200);
}

static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
				 struct intel_shared_dpll *pll)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_crtc *crtc;

	/* Make sure no transcoder isn't still depending on us. */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
		if (intel_crtc_to_shared_dpll(crtc) == pll)
			assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9336 9337
	}

9338 9339
	I915_WRITE(PCH_DPLL(pll->id), 0);
	POSTING_READ(PCH_DPLL(pll->id));
9340 9341 9342
	udelay(200);
}

9343 9344 9345 9346 9347
static char *ibx_pch_dpll_names[] = {
	"PCH DPLL A",
	"PCH DPLL B",
};

9348
static void ibx_pch_dpll_init(struct drm_device *dev)
9349
{
9350
	struct drm_i915_private *dev_priv = dev->dev_private;
9351 9352
	int i;

9353
	dev_priv->num_shared_dpll = 2;
9354

D
Daniel Vetter 已提交
9355
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9356 9357
		dev_priv->shared_dplls[i].id = i;
		dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9358
		dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9359 9360
		dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
		dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9361 9362
		dev_priv->shared_dplls[i].get_hw_state =
			ibx_pch_dpll_get_hw_state;
9363 9364 9365
	}
}

9366 9367
static void intel_shared_dpll_init(struct drm_device *dev)
{
9368
	struct drm_i915_private *dev_priv = dev->dev_private;
9369 9370 9371 9372 9373 9374 9375 9376 9377 9378 9379

	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
		ibx_pch_dpll_init(dev);
	else
		dev_priv->num_shared_dpll = 0;

	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
	DRM_DEBUG_KMS("%i shared PLLs initialized\n",
		      dev_priv->num_shared_dpll);
}

9380
static void intel_crtc_init(struct drm_device *dev, int pipe)
J
Jesse Barnes 已提交
9381
{
J
Jesse Barnes 已提交
9382
	drm_i915_private_t *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
9383 9384 9385 9386 9387 9388 9389 9390 9391 9392 9393 9394 9395 9396 9397 9398
	struct intel_crtc *intel_crtc;
	int i;

	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
	if (intel_crtc == NULL)
		return;

	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);

	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
	for (i = 0; i < 256; i++) {
		intel_crtc->lut_r[i] = i;
		intel_crtc->lut_g[i] = i;
		intel_crtc->lut_b[i] = i;
	}

9399 9400 9401
	/* Swap pipes & planes for FBC on pre-965 */
	intel_crtc->pipe = pipe;
	intel_crtc->plane = pipe;
9402
	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9403
		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9404
		intel_crtc->plane = !pipe;
9405 9406
	}

J
Jesse Barnes 已提交
9407 9408 9409 9410 9411
	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;

J
Jesse Barnes 已提交
9412 9413 9414
	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
}

9415
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9416
				struct drm_file *file)
9417 9418
{
	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9419 9420
	struct drm_mode_object *drmmode_obj;
	struct intel_crtc *crtc;
9421

9422 9423
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
9424

9425 9426
	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
			DRM_MODE_OBJECT_CRTC);
9427

9428
	if (!drmmode_obj) {
9429 9430 9431 9432
		DRM_ERROR("no such CRTC id\n");
		return -EINVAL;
	}

9433 9434
	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
	pipe_from_crtc_id->pipe = crtc->pipe;
9435

9436
	return 0;
9437 9438
}

9439
static int intel_encoder_clones(struct intel_encoder *encoder)
J
Jesse Barnes 已提交
9440
{
9441 9442
	struct drm_device *dev = encoder->base.dev;
	struct intel_encoder *source_encoder;
J
Jesse Barnes 已提交
9443 9444 9445
	int index_mask = 0;
	int entry = 0;

9446 9447 9448 9449
	list_for_each_entry(source_encoder,
			    &dev->mode_config.encoder_list, base.head) {

		if (encoder == source_encoder)
J
Jesse Barnes 已提交
9450
			index_mask |= (1 << entry);
9451 9452 9453 9454 9455

		/* Intel hw has only one MUX where enocoders could be cloned. */
		if (encoder->cloneable && source_encoder->cloneable)
			index_mask |= (1 << entry);

J
Jesse Barnes 已提交
9456 9457
		entry++;
	}
9458

J
Jesse Barnes 已提交
9459 9460 9461
	return index_mask;
}

9462 9463 9464 9465 9466 9467 9468 9469 9470 9471 9472 9473 9474 9475 9476 9477 9478
static bool has_edp_a(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!IS_MOBILE(dev))
		return false;

	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		return false;

	if (IS_GEN5(dev) &&
	    (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		return false;

	return true;
}

J
Jesse Barnes 已提交
9479 9480
static void intel_setup_outputs(struct drm_device *dev)
{
9481
	struct drm_i915_private *dev_priv = dev->dev_private;
9482
	struct intel_encoder *encoder;
9483
	bool dpd_is_edp = false;
J
Jesse Barnes 已提交
9484

9485
	intel_lvds_init(dev);
J
Jesse Barnes 已提交
9486

9487
	if (!IS_ULT(dev))
9488
		intel_crt_init(dev);
9489

P
Paulo Zanoni 已提交
9490
	if (HAS_DDI(dev)) {
9491 9492 9493 9494 9495 9496 9497 9498 9499 9500 9501 9502 9503 9504 9505 9506 9507 9508 9509
		int found;

		/* Haswell uses DDI functions to detect digital outputs */
		found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		/* DDI A only supports eDP */
		if (found)
			intel_ddi_init(dev, PORT_A);

		/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		 * register */
		found = I915_READ(SFUSE_STRAP);

		if (found & SFUSE_STRAP_DDIB_DETECTED)
			intel_ddi_init(dev, PORT_B);
		if (found & SFUSE_STRAP_DDIC_DETECTED)
			intel_ddi_init(dev, PORT_C);
		if (found & SFUSE_STRAP_DDID_DETECTED)
			intel_ddi_init(dev, PORT_D);
	} else if (HAS_PCH_SPLIT(dev)) {
9510
		int found;
9511 9512 9513 9514
		dpd_is_edp = intel_dpd_is_edp(dev);

		if (has_edp_a(dev))
			intel_dp_init(dev, DP_A, PORT_A);
9515

9516
		if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9517
			/* PCH SDVOB multiplex with HDMIB */
9518
			found = intel_sdvo_init(dev, PCH_SDVOB, true);
9519
			if (!found)
9520
				intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9521
			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9522
				intel_dp_init(dev, PCH_DP_B, PORT_B);
9523 9524
		}

9525
		if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9526
			intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9527

9528
		if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9529
			intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9530

9531
		if (I915_READ(PCH_DP_C) & DP_DETECTED)
9532
			intel_dp_init(dev, PCH_DP_C, PORT_C);
9533

9534
		if (I915_READ(PCH_DP_D) & DP_DETECTED)
9535
			intel_dp_init(dev, PCH_DP_D, PORT_D);
9536
	} else if (IS_VALLEYVIEW(dev)) {
9537
		/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9538 9539 9540 9541 9542 9543 9544
		if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
			intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
					PORT_C);
			if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
					      PORT_C);
		}
9545

9546
		if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9547 9548
			intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
					PORT_B);
9549 9550
			if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9551
		}
9552
	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9553
		bool found = false;
9554

9555
		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9556
			DRM_DEBUG_KMS("probing SDVOB\n");
9557
			found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9558 9559
			if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9560
				intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9561
			}
9562

9563
			if (!found && SUPPORTS_INTEGRATED_DP(dev))
9564
				intel_dp_init(dev, DP_B, PORT_B);
9565
		}
9566 9567 9568

		/* Before G4X SDVOC doesn't have its own detect register */

9569
		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9570
			DRM_DEBUG_KMS("probing SDVOC\n");
9571
			found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9572
		}
9573

9574
		if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9575

9576 9577
			if (SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9578
				intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9579
			}
9580
			if (SUPPORTS_INTEGRATED_DP(dev))
9581
				intel_dp_init(dev, DP_C, PORT_C);
9582
		}
9583

9584
		if (SUPPORTS_INTEGRATED_DP(dev) &&
9585
		    (I915_READ(DP_D) & DP_DETECTED))
9586
			intel_dp_init(dev, DP_D, PORT_D);
9587
	} else if (IS_GEN2(dev))
J
Jesse Barnes 已提交
9588 9589
		intel_dvo_init(dev);

9590
	if (SUPPORTS_TV(dev))
J
Jesse Barnes 已提交
9591 9592
		intel_tv_init(dev);

9593 9594 9595
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		encoder->base.possible_crtcs = encoder->crtc_mask;
		encoder->base.possible_clones =
9596
			intel_encoder_clones(encoder);
J
Jesse Barnes 已提交
9597
	}
9598

P
Paulo Zanoni 已提交
9599
	intel_init_pch_refclk(dev);
9600 9601

	drm_helper_move_panel_connectors_to_head(dev);
J
Jesse Barnes 已提交
9602 9603
}

9604 9605 9606 9607 9608 9609
void intel_framebuffer_fini(struct intel_framebuffer *fb)
{
	drm_framebuffer_cleanup(&fb->base);
	drm_gem_object_unreference_unlocked(&fb->obj->base);
}

J
Jesse Barnes 已提交
9610 9611 9612 9613
static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

9614
	intel_framebuffer_fini(intel_fb);
J
Jesse Barnes 已提交
9615 9616 9617 9618
	kfree(intel_fb);
}

static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9619
						struct drm_file *file,
J
Jesse Barnes 已提交
9620 9621 9622
						unsigned int *handle)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9623
	struct drm_i915_gem_object *obj = intel_fb->obj;
J
Jesse Barnes 已提交
9624

9625
	return drm_gem_handle_create(file, &obj->base, handle);
J
Jesse Barnes 已提交
9626 9627 9628 9629 9630 9631 9632
}

static const struct drm_framebuffer_funcs intel_fb_funcs = {
	.destroy = intel_user_framebuffer_destroy,
	.create_handle = intel_user_framebuffer_create_handle,
};

9633 9634
int intel_framebuffer_init(struct drm_device *dev,
			   struct intel_framebuffer *intel_fb,
9635
			   struct drm_mode_fb_cmd2 *mode_cmd,
9636
			   struct drm_i915_gem_object *obj)
J
Jesse Barnes 已提交
9637
{
9638
	int pitch_limit;
J
Jesse Barnes 已提交
9639 9640
	int ret;

9641 9642
	if (obj->tiling_mode == I915_TILING_Y) {
		DRM_DEBUG("hardware does not support tiling Y\n");
9643
		return -EINVAL;
9644
	}
9645

9646 9647 9648
	if (mode_cmd->pitches[0] & 63) {
		DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
			  mode_cmd->pitches[0]);
9649
		return -EINVAL;
9650
	}
9651

9652 9653 9654 9655 9656 9657 9658 9659 9660 9661 9662 9663 9664 9665 9666 9667 9668 9669 9670 9671
	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
		pitch_limit = 32*1024;
	} else if (INTEL_INFO(dev)->gen >= 4) {
		if (obj->tiling_mode)
			pitch_limit = 16*1024;
		else
			pitch_limit = 32*1024;
	} else if (INTEL_INFO(dev)->gen >= 3) {
		if (obj->tiling_mode)
			pitch_limit = 8*1024;
		else
			pitch_limit = 16*1024;
	} else
		/* XXX DSPC is limited to 4k tiled */
		pitch_limit = 8*1024;

	if (mode_cmd->pitches[0] > pitch_limit) {
		DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
			  obj->tiling_mode ? "tiled" : "linear",
			  mode_cmd->pitches[0], pitch_limit);
9672
		return -EINVAL;
9673
	}
9674 9675

	if (obj->tiling_mode != I915_TILING_NONE &&
9676 9677 9678
	    mode_cmd->pitches[0] != obj->stride) {
		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
			  mode_cmd->pitches[0], obj->stride);
9679
		return -EINVAL;
9680
	}
9681

9682
	/* Reject formats not supported by any plane early. */
9683
	switch (mode_cmd->pixel_format) {
9684
	case DRM_FORMAT_C8:
V
Ville Syrjälä 已提交
9685 9686 9687
	case DRM_FORMAT_RGB565:
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
9688 9689 9690
		break;
	case DRM_FORMAT_XRGB1555:
	case DRM_FORMAT_ARGB1555:
9691
		if (INTEL_INFO(dev)->gen > 3) {
9692 9693
			DRM_DEBUG("unsupported pixel format: %s\n",
				  drm_get_format_name(mode_cmd->pixel_format));
9694
			return -EINVAL;
9695
		}
9696 9697 9698
		break;
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
V
Ville Syrjälä 已提交
9699 9700
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
9701 9702
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
9703
		if (INTEL_INFO(dev)->gen < 4) {
9704 9705
			DRM_DEBUG("unsupported pixel format: %s\n",
				  drm_get_format_name(mode_cmd->pixel_format));
9706
			return -EINVAL;
9707
		}
9708
		break;
V
Ville Syrjälä 已提交
9709 9710 9711 9712
	case DRM_FORMAT_YUYV:
	case DRM_FORMAT_UYVY:
	case DRM_FORMAT_YVYU:
	case DRM_FORMAT_VYUY:
9713
		if (INTEL_INFO(dev)->gen < 5) {
9714 9715
			DRM_DEBUG("unsupported pixel format: %s\n",
				  drm_get_format_name(mode_cmd->pixel_format));
9716
			return -EINVAL;
9717
		}
9718 9719
		break;
	default:
9720 9721
		DRM_DEBUG("unsupported pixel format: %s\n",
			  drm_get_format_name(mode_cmd->pixel_format));
9722 9723 9724
		return -EINVAL;
	}

9725 9726 9727 9728
	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
	if (mode_cmd->offsets[0] != 0)
		return -EINVAL;

9729 9730 9731
	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
	intel_fb->obj = obj;

J
Jesse Barnes 已提交
9732 9733 9734 9735 9736 9737 9738 9739 9740 9741 9742 9743
	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
	if (ret) {
		DRM_ERROR("framebuffer init failed %d\n", ret);
		return ret;
	}

	return 0;
}

static struct drm_framebuffer *
intel_user_framebuffer_create(struct drm_device *dev,
			      struct drm_file *filp,
9744
			      struct drm_mode_fb_cmd2 *mode_cmd)
J
Jesse Barnes 已提交
9745
{
9746
	struct drm_i915_gem_object *obj;
J
Jesse Barnes 已提交
9747

9748 9749
	obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
						mode_cmd->handles[0]));
9750
	if (&obj->base == NULL)
9751
		return ERR_PTR(-ENOENT);
J
Jesse Barnes 已提交
9752

9753
	return intel_framebuffer_create(dev, mode_cmd, obj);
J
Jesse Barnes 已提交
9754 9755 9756 9757
}

static const struct drm_mode_config_funcs intel_mode_funcs = {
	.fb_create = intel_user_framebuffer_create,
9758
	.output_poll_changed = intel_fb_output_poll_changed,
J
Jesse Barnes 已提交
9759 9760
};

9761 9762 9763 9764 9765
/* Set up chip specific display functions */
static void intel_init_display(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

9766 9767 9768 9769 9770 9771 9772 9773 9774
	if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
		dev_priv->display.find_dpll = g4x_find_best_dpll;
	else if (IS_VALLEYVIEW(dev))
		dev_priv->display.find_dpll = vlv_find_best_dpll;
	else if (IS_PINEVIEW(dev))
		dev_priv->display.find_dpll = pnv_find_best_dpll;
	else
		dev_priv->display.find_dpll = i9xx_find_best_dpll;

P
Paulo Zanoni 已提交
9775
	if (HAS_DDI(dev)) {
9776
		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
P
Paulo Zanoni 已提交
9777
		dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9778 9779
		dev_priv->display.crtc_enable = haswell_crtc_enable;
		dev_priv->display.crtc_disable = haswell_crtc_disable;
9780
		dev_priv->display.off = haswell_crtc_off;
P
Paulo Zanoni 已提交
9781 9782
		dev_priv->display.update_plane = ironlake_update_plane;
	} else if (HAS_PCH_SPLIT(dev)) {
9783
		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9784
		dev_priv->display.get_clock = ironlake_crtc_clock_get;
9785
		dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9786 9787
		dev_priv->display.crtc_enable = ironlake_crtc_enable;
		dev_priv->display.crtc_disable = ironlake_crtc_disable;
9788
		dev_priv->display.off = ironlake_crtc_off;
9789
		dev_priv->display.update_plane = ironlake_update_plane;
9790 9791
	} else if (IS_VALLEYVIEW(dev)) {
		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9792
		dev_priv->display.get_clock = i9xx_crtc_clock_get;
9793 9794 9795 9796 9797
		dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		dev_priv->display.crtc_enable = valleyview_crtc_enable;
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
		dev_priv->display.off = i9xx_crtc_off;
		dev_priv->display.update_plane = i9xx_update_plane;
9798
	} else {
9799
		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9800
		dev_priv->display.get_clock = i9xx_crtc_clock_get;
9801
		dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9802 9803
		dev_priv->display.crtc_enable = i9xx_crtc_enable;
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
9804
		dev_priv->display.off = i9xx_crtc_off;
9805
		dev_priv->display.update_plane = i9xx_update_plane;
9806
	}
9807 9808

	/* Returns the core display clock speed */
J
Jesse Barnes 已提交
9809 9810 9811 9812
	if (IS_VALLEYVIEW(dev))
		dev_priv->display.get_display_clock_speed =
			valleyview_get_display_clock_speed;
	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9813 9814 9815 9816 9817
		dev_priv->display.get_display_clock_speed =
			i945_get_display_clock_speed;
	else if (IS_I915G(dev))
		dev_priv->display.get_display_clock_speed =
			i915_get_display_clock_speed;
9818
	else if (IS_I945GM(dev) || IS_845G(dev))
9819 9820
		dev_priv->display.get_display_clock_speed =
			i9xx_misc_get_display_clock_speed;
9821 9822 9823
	else if (IS_PINEVIEW(dev))
		dev_priv->display.get_display_clock_speed =
			pnv_get_display_clock_speed;
9824 9825 9826 9827 9828 9829
	else if (IS_I915GM(dev))
		dev_priv->display.get_display_clock_speed =
			i915gm_get_display_clock_speed;
	else if (IS_I865G(dev))
		dev_priv->display.get_display_clock_speed =
			i865_get_display_clock_speed;
9830
	else if (IS_I85X(dev))
9831 9832 9833 9834 9835 9836
		dev_priv->display.get_display_clock_speed =
			i855_get_display_clock_speed;
	else /* 852, 830 */
		dev_priv->display.get_display_clock_speed =
			i830_get_display_clock_speed;

9837
	if (HAS_PCH_SPLIT(dev)) {
9838
		if (IS_GEN5(dev)) {
9839
			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9840
			dev_priv->display.write_eld = ironlake_write_eld;
9841
		} else if (IS_GEN6(dev)) {
9842
			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9843
			dev_priv->display.write_eld = ironlake_write_eld;
9844 9845 9846
		} else if (IS_IVYBRIDGE(dev)) {
			/* FIXME: detect B0+ stepping and use auto training */
			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9847
			dev_priv->display.write_eld = ironlake_write_eld;
9848 9849
			dev_priv->display.modeset_global_resources =
				ivb_modeset_global_resources;
9850 9851
		} else if (IS_HASWELL(dev)) {
			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9852
			dev_priv->display.write_eld = haswell_write_eld;
9853 9854
			dev_priv->display.modeset_global_resources =
				haswell_modeset_global_resources;
9855
		}
9856
	} else if (IS_G4X(dev)) {
9857
		dev_priv->display.write_eld = g4x_write_eld;
9858
	}
9859 9860 9861 9862 9863 9864 9865 9866 9867 9868 9869 9870 9871 9872 9873 9874 9875 9876 9877 9878 9879

	/* Default just returns -ENODEV to indicate unsupported */
	dev_priv->display.queue_flip = intel_default_queue_flip;

	switch (INTEL_INFO(dev)->gen) {
	case 2:
		dev_priv->display.queue_flip = intel_gen2_queue_flip;
		break;

	case 3:
		dev_priv->display.queue_flip = intel_gen3_queue_flip;
		break;

	case 4:
	case 5:
		dev_priv->display.queue_flip = intel_gen4_queue_flip;
		break;

	case 6:
		dev_priv->display.queue_flip = intel_gen6_queue_flip;
		break;
9880 9881 9882
	case 7:
		dev_priv->display.queue_flip = intel_gen7_queue_flip;
		break;
9883
	}
9884 9885
}

9886 9887 9888 9889 9890
/*
 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
 * resume, or other times.  This quirk makes sure that's the case for
 * affected systems.
 */
9891
static void quirk_pipea_force(struct drm_device *dev)
9892 9893 9894 9895
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9896
	DRM_INFO("applying pipe a force quirk\n");
9897 9898
}

9899 9900 9901 9902 9903 9904 9905
/*
 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
 */
static void quirk_ssc_force_disable(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9906
	DRM_INFO("applying lvds SSC disable quirk\n");
9907 9908
}

9909
/*
9910 9911
 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
 * brightness value
9912 9913 9914 9915 9916
 */
static void quirk_invert_brightness(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9917
	DRM_INFO("applying inverted panel brightness quirk\n");
9918 9919
}

9920 9921 9922 9923 9924 9925 9926 9927 9928 9929 9930
/*
 * Some machines (Dell XPS13) suffer broken backlight controls if
 * BLM_PCH_PWM_ENABLE is set.
 */
static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
	DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
}

9931 9932 9933 9934 9935 9936 9937
struct intel_quirk {
	int device;
	int subsystem_vendor;
	int subsystem_device;
	void (*hook)(struct drm_device *dev);
};

9938 9939 9940 9941 9942 9943 9944 9945 9946 9947 9948 9949 9950 9951 9952 9953 9954 9955 9956 9957 9958 9959 9960 9961 9962 9963 9964 9965
/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
struct intel_dmi_quirk {
	void (*hook)(struct drm_device *dev);
	const struct dmi_system_id (*dmi_id_list)[];
};

static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
{
	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
	return 1;
}

static const struct intel_dmi_quirk intel_dmi_quirks[] = {
	{
		.dmi_id_list = &(const struct dmi_system_id[]) {
			{
				.callback = intel_dmi_reverse_brightness,
				.ident = "NCR Corporation",
				.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
					    DMI_MATCH(DMI_PRODUCT_NAME, ""),
				},
			},
			{ }  /* terminating entry */
		},
		.hook = quirk_invert_brightness,
	},
};

9966
static struct intel_quirk intel_quirks[] = {
9967
	/* HP Mini needs pipe A force quirk (LP: #322104) */
9968
	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9969 9970 9971 9972 9973 9974 9975

	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },

	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },

9976
	/* 830/845 need to leave pipe A & dpll A up */
9977
	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9978
	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9979 9980 9981

	/* Lenovo U160 cannot use SSC on LVDS */
	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9982 9983 9984

	/* Sony Vaio Y cannot use SSC on LVDS */
	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9985 9986 9987

	/* Acer Aspire 5734Z must invert backlight brightness */
	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9988 9989 9990

	/* Acer/eMachines G725 */
	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9991 9992 9993

	/* Acer/eMachines e725 */
	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9994 9995 9996

	/* Acer/Packard Bell NCL20 */
	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9997 9998 9999

	/* Acer Aspire 4736Z */
	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10000 10001 10002 10003 10004

	/* Dell XPS13 HD Sandy Bridge */
	{ 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
	/* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
	{ 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10005 10006 10007 10008 10009 10010 10011 10012 10013 10014 10015 10016 10017 10018 10019 10020 10021
};

static void intel_init_quirks(struct drm_device *dev)
{
	struct pci_dev *d = dev->pdev;
	int i;

	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		struct intel_quirk *q = &intel_quirks[i];

		if (d->device == q->device &&
		    (d->subsystem_vendor == q->subsystem_vendor ||
		     q->subsystem_vendor == PCI_ANY_ID) &&
		    (d->subsystem_device == q->subsystem_device ||
		     q->subsystem_device == PCI_ANY_ID))
			q->hook(dev);
	}
10022 10023 10024 10025
	for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
		if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
			intel_dmi_quirks[i].hook(dev);
	}
10026 10027
}

10028 10029 10030 10031 10032
/* Disable the VGA plane that we never use */
static void i915_disable_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u8 sr1;
10033
	u32 vga_reg = i915_vgacntrl_reg(dev);
10034 10035

	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10036
	outb(SR01, VGA_SR_INDEX);
10037 10038 10039 10040 10041 10042 10043 10044 10045
	sr1 = inb(VGA_SR_DATA);
	outb(sr1 | 1<<5, VGA_SR_DATA);
	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
	udelay(300);

	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
	POSTING_READ(vga_reg);
}

10046
static void i915_enable_vga_mem(struct drm_device *dev)
10047 10048 10049 10050 10051 10052 10053 10054 10055 10056 10057 10058 10059
{
	/* Enable VGA memory on Intel HD */
	if (HAS_PCH_SPLIT(dev)) {
		vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
		vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
						   VGA_RSRC_LEGACY_MEM |
						   VGA_RSRC_NORMAL_IO |
						   VGA_RSRC_NORMAL_MEM);
		vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
	}
}

10060 10061 10062 10063 10064 10065 10066 10067 10068 10069 10070 10071 10072
void i915_disable_vga_mem(struct drm_device *dev)
{
	/* Disable VGA memory on Intel HD */
	if (HAS_PCH_SPLIT(dev)) {
		vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
		outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
		vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
						   VGA_RSRC_NORMAL_IO |
						   VGA_RSRC_NORMAL_MEM);
		vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
	}
}

10073 10074
void intel_modeset_init_hw(struct drm_device *dev)
{
10075
	intel_init_power_well(dev);
10076

10077 10078
	intel_prepare_ddi(dev);

10079 10080
	intel_init_clock_gating(dev);

10081
	mutex_lock(&dev->struct_mutex);
10082
	intel_enable_gt_powersave(dev);
10083
	mutex_unlock(&dev->struct_mutex);
10084 10085
}

10086 10087 10088 10089 10090
void intel_modeset_suspend_hw(struct drm_device *dev)
{
	intel_suspend_hw(dev);
}

J
Jesse Barnes 已提交
10091 10092
void intel_modeset_init(struct drm_device *dev)
{
10093
	struct drm_i915_private *dev_priv = dev->dev_private;
10094
	int i, j, ret;
J
Jesse Barnes 已提交
10095 10096 10097 10098 10099 10100

	drm_mode_config_init(dev);

	dev->mode_config.min_width = 0;
	dev->mode_config.min_height = 0;

10101 10102 10103
	dev->mode_config.preferred_depth = 24;
	dev->mode_config.prefer_shadow = 1;

10104
	dev->mode_config.funcs = &intel_mode_funcs;
J
Jesse Barnes 已提交
10105

10106 10107
	intel_init_quirks(dev);

10108 10109
	intel_init_pm(dev);

B
Ben Widawsky 已提交
10110 10111 10112
	if (INTEL_INFO(dev)->num_pipes == 0)
		return;

10113 10114
	intel_init_display(dev);

10115 10116 10117 10118
	if (IS_GEN2(dev)) {
		dev->mode_config.max_width = 2048;
		dev->mode_config.max_height = 2048;
	} else if (IS_GEN3(dev)) {
10119 10120
		dev->mode_config.max_width = 4096;
		dev->mode_config.max_height = 4096;
J
Jesse Barnes 已提交
10121
	} else {
10122 10123
		dev->mode_config.max_width = 8192;
		dev->mode_config.max_height = 8192;
J
Jesse Barnes 已提交
10124
	}
B
Ben Widawsky 已提交
10125
	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
J
Jesse Barnes 已提交
10126

10127
	DRM_DEBUG_KMS("%d display pipe%s available.\n",
10128 10129
		      INTEL_INFO(dev)->num_pipes,
		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
J
Jesse Barnes 已提交
10130

10131
	for_each_pipe(i) {
J
Jesse Barnes 已提交
10132
		intel_crtc_init(dev, i);
10133 10134 10135
		for (j = 0; j < dev_priv->num_plane; j++) {
			ret = intel_plane_init(dev, i, j);
			if (ret)
10136 10137
				DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
					      pipe_name(i), sprite_name(i, j), ret);
10138
		}
J
Jesse Barnes 已提交
10139 10140
	}

P
Paulo Zanoni 已提交
10141
	intel_cpu_pll_init(dev);
D
Daniel Vetter 已提交
10142
	intel_shared_dpll_init(dev);
10143

10144 10145
	/* Just disable it once at startup */
	i915_disable_vga(dev);
J
Jesse Barnes 已提交
10146
	intel_setup_outputs(dev);
10147 10148 10149

	/* Just in case the BIOS is doing something questionable. */
	intel_disable_fbc(dev);
10150 10151
}

10152 10153 10154 10155 10156 10157 10158 10159 10160
static void
intel_connector_break_all_links(struct intel_connector *connector)
{
	connector->base.dpms = DRM_MODE_DPMS_OFF;
	connector->base.encoder = NULL;
	connector->encoder->connectors_active = false;
	connector->encoder->base.crtc = NULL;
}

10161 10162 10163 10164 10165 10166 10167 10168 10169 10170 10171 10172 10173 10174 10175 10176 10177 10178 10179 10180 10181 10182 10183 10184
static void intel_enable_pipe_a(struct drm_device *dev)
{
	struct intel_connector *connector;
	struct drm_connector *crt = NULL;
	struct intel_load_detect_pipe load_detect_temp;

	/* We can't just switch on the pipe A, we need to set things up with a
	 * proper mode and output configuration. As a gross hack, enable pipe A
	 * by enabling the load detect pipe once. */
	list_for_each_entry(connector,
			    &dev->mode_config.connector_list,
			    base.head) {
		if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
			crt = &connector->base;
			break;
		}
	}

	if (!crt)
		return;

	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
		intel_release_load_detect_pipe(crt, &load_detect_temp);

10185

10186 10187
}

10188 10189 10190
static bool
intel_check_plane_mapping(struct intel_crtc *crtc)
{
10191 10192
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
10193 10194
	u32 reg, val;

10195
	if (INTEL_INFO(dev)->num_pipes == 1)
10196 10197 10198 10199 10200 10201 10202 10203 10204 10205 10206 10207
		return true;

	reg = DSPCNTR(!crtc->plane);
	val = I915_READ(reg);

	if ((val & DISPLAY_PLANE_ENABLE) &&
	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		return false;

	return true;
}

10208 10209 10210 10211
static void intel_sanitize_crtc(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
10212
	u32 reg;
10213 10214

	/* Clear any frame start delays used for debugging left by the BIOS */
10215
	reg = PIPECONF(crtc->config.cpu_transcoder);
10216 10217 10218
	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);

	/* We need to sanitize the plane -> pipe mapping first because this will
10219 10220 10221
	 * disable the crtc (and hence change the state) if it is wrong. Note
	 * that gen4+ has a fixed plane -> pipe mapping.  */
	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10222 10223 10224 10225 10226 10227 10228 10229 10230 10231 10232 10233 10234 10235 10236 10237 10238 10239 10240 10241 10242 10243 10244 10245 10246 10247 10248
		struct intel_connector *connector;
		bool plane;

		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
			      crtc->base.base.id);

		/* Pipe has the wrong plane attached and the plane is active.
		 * Temporarily change the plane mapping and disable everything
		 * ...  */
		plane = crtc->plane;
		crtc->plane = !plane;
		dev_priv->display.crtc_disable(&crtc->base);
		crtc->plane = plane;

		/* ... and break all links. */
		list_for_each_entry(connector, &dev->mode_config.connector_list,
				    base.head) {
			if (connector->encoder->base.crtc != &crtc->base)
				continue;

			intel_connector_break_all_links(connector);
		}

		WARN_ON(crtc->active);
		crtc->base.enabled = false;
	}

10249 10250 10251 10252 10253 10254 10255 10256 10257
	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
	    crtc->pipe == PIPE_A && !crtc->active) {
		/* BIOS forgot to enable pipe A, this mostly happens after
		 * resume. Force-enable the pipe to fix this, the update_dpms
		 * call below we restore the pipe to the right state, but leave
		 * the required bits on. */
		intel_enable_pipe_a(dev);
	}

10258 10259 10260 10261 10262 10263 10264 10265 10266 10267 10268 10269 10270 10271 10272 10273 10274 10275 10276 10277 10278 10279 10280 10281 10282 10283 10284 10285 10286 10287 10288 10289 10290 10291 10292 10293 10294 10295 10296 10297 10298 10299 10300 10301 10302 10303 10304 10305 10306 10307 10308 10309 10310 10311 10312 10313 10314 10315 10316 10317 10318 10319 10320 10321 10322 10323 10324 10325 10326 10327 10328 10329 10330 10331
	/* Adjust the state of the output pipe according to whether we
	 * have active connectors/encoders. */
	intel_crtc_update_dpms(&crtc->base);

	if (crtc->active != crtc->base.enabled) {
		struct intel_encoder *encoder;

		/* This can happen either due to bugs in the get_hw_state
		 * functions or because the pipe is force-enabled due to the
		 * pipe A quirk. */
		DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
			      crtc->base.base.id,
			      crtc->base.enabled ? "enabled" : "disabled",
			      crtc->active ? "enabled" : "disabled");

		crtc->base.enabled = crtc->active;

		/* Because we only establish the connector -> encoder ->
		 * crtc links if something is active, this means the
		 * crtc is now deactivated. Break the links. connector
		 * -> encoder links are only establish when things are
		 *  actually up, hence no need to break them. */
		WARN_ON(crtc->active);

		for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
			WARN_ON(encoder->connectors_active);
			encoder->base.crtc = NULL;
		}
	}
}

static void intel_sanitize_encoder(struct intel_encoder *encoder)
{
	struct intel_connector *connector;
	struct drm_device *dev = encoder->base.dev;

	/* We need to check both for a crtc link (meaning that the
	 * encoder is active and trying to read from a pipe) and the
	 * pipe itself being active. */
	bool has_active_crtc = encoder->base.crtc &&
		to_intel_crtc(encoder->base.crtc)->active;

	if (encoder->connectors_active && !has_active_crtc) {
		DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base));

		/* Connector is active, but has no active pipe. This is
		 * fallout from our resume register restoring. Disable
		 * the encoder manually again. */
		if (encoder->base.crtc) {
			DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
				      encoder->base.base.id,
				      drm_get_encoder_name(&encoder->base));
			encoder->disable(encoder);
		}

		/* Inconsistent output/port/pipe state happens presumably due to
		 * a bug in one of the get_hw_state functions. Or someplace else
		 * in our code, like the register restore mess on resume. Clamp
		 * things to off as a safer default. */
		list_for_each_entry(connector,
				    &dev->mode_config.connector_list,
				    base.head) {
			if (connector->encoder != encoder)
				continue;

			intel_connector_break_all_links(connector);
		}
	}
	/* Enabled encoders without active connectors will be fixed in
	 * the crtc fixup. */
}

10332
void i915_redisable_vga(struct drm_device *dev)
10333 10334
{
	struct drm_i915_private *dev_priv = dev->dev_private;
10335
	u32 vga_reg = i915_vgacntrl_reg(dev);
10336

10337 10338 10339 10340 10341 10342 10343 10344
	/* This function can be called both from intel_modeset_setup_hw_state or
	 * at a very early point in our resume sequence, where the power well
	 * structures are not yet restored. Since this function is at a very
	 * paranoid "someone might have enabled VGA while we were not looking"
	 * level, just check if the power well is enabled instead of trying to
	 * follow the "don't touch the power well if we don't need it" policy
	 * the rest of the driver uses. */
	if (HAS_POWER_WELL(dev) &&
10345
	    (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10346 10347
		return;

10348 10349
	if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
		DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10350
		i915_disable_vga(dev);
10351
		i915_disable_vga_mem(dev);
10352 10353 10354
	}
}

10355
static void intel_modeset_readout_hw_state(struct drm_device *dev)
10356 10357 10358 10359 10360 10361
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe;
	struct intel_crtc *crtc;
	struct intel_encoder *encoder;
	struct intel_connector *connector;
10362
	int i;
10363

10364 10365
	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
			    base.head) {
10366
		memset(&crtc->config, 0, sizeof(crtc->config));
10367

10368 10369
		crtc->active = dev_priv->display.get_pipe_config(crtc,
								 &crtc->config);
10370 10371 10372 10373 10374 10375 10376 10377

		crtc->base.enabled = crtc->active;

		DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
			      crtc->base.base.id,
			      crtc->active ? "enabled" : "disabled");
	}

10378
	/* FIXME: Smash this into the new shared dpll infrastructure. */
P
Paulo Zanoni 已提交
10379
	if (HAS_DDI(dev))
10380 10381
		intel_ddi_setup_hw_pll_state(dev);

10382 10383 10384 10385 10386 10387 10388 10389 10390 10391 10392 10393
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];

		pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
		pll->active = 0;
		list_for_each_entry(crtc, &dev->mode_config.crtc_list,
				    base.head) {
			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
				pll->active++;
		}
		pll->refcount = pll->active;

10394 10395
		DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
			      pll->name, pll->refcount, pll->on);
10396 10397
	}

10398 10399 10400 10401 10402
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		pipe = 0;

		if (encoder->get_hw_state(encoder, &pipe)) {
10403 10404
			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
			encoder->base.crtc = &crtc->base;
10405
			if (encoder->get_config)
10406
				encoder->get_config(encoder, &crtc->config);
10407 10408 10409 10410 10411 10412 10413 10414 10415 10416 10417 10418
		} else {
			encoder->base.crtc = NULL;
		}

		encoder->connectors_active = false;
		DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base),
			      encoder->base.crtc ? "enabled" : "disabled",
			      pipe);
	}

10419 10420 10421 10422 10423 10424 10425 10426 10427
	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
			    base.head) {
		if (!crtc->active)
			continue;
		if (dev_priv->display.get_clock)
			dev_priv->display.get_clock(crtc,
						    &crtc->config);
	}

10428 10429 10430 10431 10432 10433 10434 10435 10436 10437 10438 10439 10440 10441 10442
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (connector->get_hw_state(connector)) {
			connector->base.dpms = DRM_MODE_DPMS_ON;
			connector->encoder->connectors_active = true;
			connector->base.encoder = &connector->encoder->base;
		} else {
			connector->base.dpms = DRM_MODE_DPMS_OFF;
			connector->base.encoder = NULL;
		}
		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
			      connector->base.base.id,
			      drm_get_connector_name(&connector->base),
			      connector->base.encoder ? "enabled" : "disabled");
	}
10443 10444 10445 10446 10447 10448 10449 10450 10451 10452 10453 10454
}

/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
 * and i915 state tracking structures. */
void intel_modeset_setup_hw_state(struct drm_device *dev,
				  bool force_restore)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe;
	struct drm_plane *plane;
	struct intel_crtc *crtc;
	struct intel_encoder *encoder;
10455
	int i;
10456 10457

	intel_modeset_readout_hw_state(dev);
10458

10459 10460 10461 10462 10463 10464 10465 10466 10467 10468 10469 10470 10471 10472 10473 10474
	/*
	 * Now that we have the config, copy it to each CRTC struct
	 * Note that this could go away if we move to using crtc_config
	 * checking everywhere.
	 */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
			    base.head) {
		if (crtc->active && i915_fastboot) {
			intel_crtc_mode_from_pipe_config(crtc, &crtc->config);

			DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
				      crtc->base.base.id);
			drm_mode_debug_printmodeline(&crtc->base.mode);
		}
	}

10475 10476 10477 10478 10479 10480 10481 10482 10483
	/* HW state is read out, now we need to sanitize this mess. */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		intel_sanitize_encoder(encoder);
	}

	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		intel_sanitize_crtc(crtc);
10484
		intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10485
	}
10486

10487 10488 10489 10490 10491 10492 10493 10494 10495 10496 10497 10498
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];

		if (!pll->on || pll->active)
			continue;

		DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);

		pll->disable(dev_priv, pll);
		pll->on = false;
	}

10499
	if (force_restore) {
10500 10501 10502 10503
		/*
		 * We need to use raw interfaces for restoring state to avoid
		 * checking (bogus) intermediate states.
		 */
10504
		for_each_pipe(pipe) {
10505 10506
			struct drm_crtc *crtc =
				dev_priv->pipe_to_crtc_mapping[pipe];
10507 10508 10509

			__intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
					 crtc->fb);
10510
		}
10511 10512
		list_for_each_entry(plane, &dev->mode_config.plane_list, head)
			intel_plane_restore(plane);
10513 10514

		i915_redisable_vga(dev);
10515 10516 10517
	} else {
		intel_modeset_update_staged_output_state(dev);
	}
10518 10519

	intel_modeset_check_state(dev);
10520 10521

	drm_mode_config_reset(dev);
10522 10523 10524 10525
}

void intel_modeset_gem_init(struct drm_device *dev)
{
10526
	intel_modeset_init_hw(dev);
10527 10528

	intel_setup_overlay(dev);
10529

10530
	intel_modeset_setup_hw_state(dev, false);
J
Jesse Barnes 已提交
10531 10532 10533 10534
}

void intel_modeset_cleanup(struct drm_device *dev)
{
10535 10536 10537
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;

10538 10539 10540 10541 10542 10543 10544 10545 10546 10547 10548
	/*
	 * Interrupts and polling as the first thing to avoid creating havoc.
	 * Too much stuff here (turning of rps, connectors, ...) would
	 * experience fancy races otherwise.
	 */
	drm_irq_uninstall(dev);
	cancel_work_sync(&dev_priv->hotplug_work);
	/*
	 * Due to the hpd irq storm handling the hotplug work can re-arm the
	 * poll handlers. Hence disable polling after hpd handling is shut down.
	 */
10549
	drm_kms_helper_poll_fini(dev);
10550

10551 10552
	mutex_lock(&dev->struct_mutex);

J
Jesse Barnes 已提交
10553 10554
	intel_unregister_dsm_handler();

10555 10556 10557 10558 10559
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		/* Skip inactive CRTCs */
		if (!crtc->fb)
			continue;

10560
		intel_increase_pllclock(crtc);
10561 10562
	}

10563
	intel_disable_fbc(dev);
10564

10565
	i915_enable_vga_mem(dev);
10566

10567
	intel_disable_gt_powersave(dev);
10568

10569 10570
	ironlake_teardown_rc6(dev);

10571 10572
	mutex_unlock(&dev->struct_mutex);

10573 10574 10575
	/* flush any delayed tasks or pending work */
	flush_scheduled_work();

10576 10577 10578
	/* destroy backlight, if any, before the connectors */
	intel_panel_destroy_backlight(dev);

J
Jesse Barnes 已提交
10579
	drm_mode_config_cleanup(dev);
10580 10581

	intel_cleanup_overlay(dev);
J
Jesse Barnes 已提交
10582 10583
}

10584 10585 10586
/*
 * Return which encoder is currently attached for connector.
 */
10587
struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
J
Jesse Barnes 已提交
10588
{
10589 10590
	return &intel_attached_encoder(connector)->base;
}
10591

10592 10593 10594 10595 10596 10597
void intel_connector_attach_encoder(struct intel_connector *connector,
				    struct intel_encoder *encoder)
{
	connector->encoder = encoder;
	drm_mode_connector_attach_encoder(&connector->base,
					  &encoder->base);
J
Jesse Barnes 已提交
10598
}
10599 10600 10601 10602 10603 10604 10605 10606 10607 10608 10609 10610 10611 10612 10613 10614 10615

/*
 * set vga decode state - true == enable VGA decode
 */
int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u16 gmch_ctrl;

	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
	if (state)
		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
	else
		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
	return 0;
}
10616 10617

struct intel_display_error_state {
10618 10619 10620

	u32 power_well_driver;

10621 10622
	int num_transcoders;

10623 10624 10625 10626 10627
	struct intel_cursor_error_state {
		u32 control;
		u32 position;
		u32 base;
		u32 size;
10628
	} cursor[I915_MAX_PIPES];
10629 10630 10631

	struct intel_pipe_error_state {
		u32 source;
10632
	} pipe[I915_MAX_PIPES];
10633 10634 10635 10636 10637 10638 10639 10640 10641

	struct intel_plane_error_state {
		u32 control;
		u32 stride;
		u32 size;
		u32 pos;
		u32 addr;
		u32 surface;
		u32 tile_offset;
10642
	} plane[I915_MAX_PIPES];
10643 10644 10645 10646 10647 10648 10649 10650 10651 10652 10653 10654 10655

	struct intel_transcoder_error_state {
		enum transcoder cpu_transcoder;

		u32 conf;

		u32 htotal;
		u32 hblank;
		u32 hsync;
		u32 vtotal;
		u32 vblank;
		u32 vsync;
	} transcoder[4];
10656 10657 10658 10659 10660
};

struct intel_display_error_state *
intel_display_capture_error_state(struct drm_device *dev)
{
10661
	drm_i915_private_t *dev_priv = dev->dev_private;
10662
	struct intel_display_error_state *error;
10663 10664 10665 10666 10667 10668
	int transcoders[] = {
		TRANSCODER_A,
		TRANSCODER_B,
		TRANSCODER_C,
		TRANSCODER_EDP,
	};
10669 10670
	int i;

10671 10672 10673
	if (INTEL_INFO(dev)->num_pipes == 0)
		return NULL;

10674 10675 10676 10677
	error = kmalloc(sizeof(*error), GFP_ATOMIC);
	if (error == NULL)
		return NULL;

10678 10679 10680
	if (HAS_POWER_WELL(dev))
		error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);

10681
	for_each_pipe(i) {
10682 10683 10684 10685 10686 10687 10688 10689 10690
		if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
			error->cursor[i].control = I915_READ(CURCNTR(i));
			error->cursor[i].position = I915_READ(CURPOS(i));
			error->cursor[i].base = I915_READ(CURBASE(i));
		} else {
			error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
			error->cursor[i].position = I915_READ(CURPOS_IVB(i));
			error->cursor[i].base = I915_READ(CURBASE_IVB(i));
		}
10691 10692 10693

		error->plane[i].control = I915_READ(DSPCNTR(i));
		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10694
		if (INTEL_INFO(dev)->gen <= 3) {
10695
			error->plane[i].size = I915_READ(DSPSIZE(i));
10696 10697
			error->plane[i].pos = I915_READ(DSPPOS(i));
		}
10698 10699
		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
			error->plane[i].addr = I915_READ(DSPADDR(i));
10700 10701 10702 10703 10704 10705
		if (INTEL_INFO(dev)->gen >= 4) {
			error->plane[i].surface = I915_READ(DSPSURF(i));
			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		}

		error->pipe[i].source = I915_READ(PIPESRC(i));
10706 10707 10708 10709 10710 10711 10712 10713 10714 10715 10716 10717 10718 10719 10720 10721 10722 10723
	}

	error->num_transcoders = INTEL_INFO(dev)->num_pipes;
	if (HAS_DDI(dev_priv->dev))
		error->num_transcoders++; /* Account for eDP. */

	for (i = 0; i < error->num_transcoders; i++) {
		enum transcoder cpu_transcoder = transcoders[i];

		error->transcoder[i].cpu_transcoder = cpu_transcoder;

		error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
		error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
		error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
		error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
		error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
		error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
		error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10724 10725
	}

10726 10727 10728 10729
	/* In the code above we read the registers without checking if the power
	 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
	 * prevent the next I915_WRITE from detecting it and printing an error
	 * message. */
10730
	intel_uncore_clear_errors(dev);
10731

10732 10733 10734
	return error;
}

10735 10736
#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)

10737
void
10738
intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10739 10740 10741 10742 10743
				struct drm_device *dev,
				struct intel_display_error_state *error)
{
	int i;

10744 10745 10746
	if (!error)
		return;

10747
	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10748
	if (HAS_POWER_WELL(dev))
10749
		err_printf(m, "PWR_WELL_CTL2: %08x\n",
10750
			   error->power_well_driver);
10751
	for_each_pipe(i) {
10752 10753 10754 10755 10756 10757
		err_printf(m, "Pipe [%d]:\n", i);
		err_printf(m, "  SRC: %08x\n", error->pipe[i].source);

		err_printf(m, "Plane [%d]:\n", i);
		err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
		err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10758
		if (INTEL_INFO(dev)->gen <= 3) {
10759 10760
			err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
			err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10761
		}
P
Paulo Zanoni 已提交
10762
		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10763
			err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10764
		if (INTEL_INFO(dev)->gen >= 4) {
10765 10766
			err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
			err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10767 10768
		}

10769 10770 10771 10772
		err_printf(m, "Cursor [%d]:\n", i);
		err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
		err_printf(m, "  POS: %08x\n", error->cursor[i].position);
		err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10773
	}
10774 10775 10776 10777 10778 10779 10780 10781 10782 10783 10784 10785

	for (i = 0; i < error->num_transcoders; i++) {
		err_printf(m, "  CPU transcoder: %c\n",
			   transcoder_name(error->transcoder[i].cpu_transcoder));
		err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
		err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
		err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
		err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
		err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
		err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
		err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
	}
10786
}