intel_display.c 252.0 KB
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/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

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#include <linux/cpufreq.h>
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#include <linux/module.h>
#include <linux/input.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/vgaarb.h>
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#include <drm/drm_edid.h>
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#include "drmP.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"
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#include "i915_trace.h"
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#include "drm_dp_helper.h"
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#include "drm_crtc_helper.h"
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#include <linux/dma_remapping.h>
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#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))

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bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
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static void intel_update_watermarks(struct drm_device *dev);
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static void intel_increase_pllclock(struct drm_crtc *crtc);
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static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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typedef struct {
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	/* given values */
	int n;
	int m1, m2;
	int p1, p2;
	/* derived values */
	int	dot;
	int	vco;
	int	m;
	int	p;
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} intel_clock_t;

typedef struct {
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	int	min, max;
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} intel_range_t;

typedef struct {
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	int	dot_limit;
	int	p2_slow, p2_fast;
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} intel_p2_t;

#define INTEL_P2_NUM		      2
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typedef struct intel_limit intel_limit_t;
struct intel_limit {
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	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
	intel_p2_t	    p2;
	bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
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			int, int, intel_clock_t *, intel_clock_t *);
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};
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/* FDI */
#define IRONLAKE_FDI_FREQ		2700000 /* in kHz for mode->clock */

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static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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		    int target, int refclk, intel_clock_t *match_clock,
		    intel_clock_t *best_clock);
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static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock);
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static bool
intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
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		      int target, int refclk, intel_clock_t *match_clock,
		      intel_clock_t *best_clock);
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static bool
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intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
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			   int target, int refclk, intel_clock_t *match_clock,
			   intel_clock_t *best_clock);
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static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev)
{
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	if (IS_GEN5(dev)) {
		struct drm_i915_private *dev_priv = dev->dev_private;
		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
	} else
		return 27;
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}

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static const intel_limit_t intel_limits_i8xx_dvo = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 2, .max = 33 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 4, .p2_fast = 2 },
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	.find_pll = intel_find_best_PLL,
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};

static const intel_limit_t intel_limits_i8xx_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 1, .max = 6 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 14, .p2_fast = 7 },
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	.find_pll = intel_find_best_PLL,
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};
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static const intel_limit_t intel_limits_i9xx_sdvo = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
	.m1 = { .min = 10, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_find_best_PLL,
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};

static const intel_limit_t intel_limits_i9xx_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
	.m1 = { .min = 10, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 7, .max = 98 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 7 },
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	.find_pll = intel_find_best_PLL,
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};

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static const intel_limit_t intel_limits_g4x_sdvo = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 1, .max = 3},
	.p2 = { .dot_limit = 270000,
		.p2_slow = 10,
		.p2_fast = 10
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_hdmi = {
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	.dot = { .min = 22000, .max = 400000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 16, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8},
	.p2 = { .dot_limit = 165000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
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	.dot = { .min = 20000, .max = 115000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 14, .p2_fast = 14
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
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	.dot = { .min = 80000, .max = 224000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 14, .max = 42 },
	.p1 = { .min = 2, .max = 6 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 7, .p2_fast = 7
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_display_port = {
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	.dot = { .min = 161670, .max = 227000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 2 },
	.m = { .min = 97, .max = 108 },
	.m1 = { .min = 0x10, .max = 0x12 },
	.m2 = { .min = 0x05, .max = 0x06 },
	.p = { .min = 10, .max = 20 },
	.p1 = { .min = 1, .max = 2},
	.p2 = { .dot_limit = 0,
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		.p2_slow = 10, .p2_fast = 10 },
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	.find_pll = intel_find_pll_g4x_dp,
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};

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static const intel_limit_t intel_limits_pineview_sdvo = {
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	.dot = { .min = 20000, .max = 400000},
	.vco = { .min = 1700000, .max = 3500000 },
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	/* Pineview's Ncounter is a ring counter */
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	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
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	/* Pineview only has one combined m divider, which we treat as m2. */
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	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_find_best_PLL,
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};

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static const intel_limit_t intel_limits_pineview_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1700000, .max = 3500000 },
	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 7, .max = 112 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_find_best_PLL,
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};

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/* Ironlake / Sandybridge
 *
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
 * the range value for them is (actual_value - 2).
 */
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static const intel_limit_t intel_limits_ironlake_dac = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 5 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_g4x_find_best_PLL,
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};

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static const intel_limit_t intel_limits_ironlake_single_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 118 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 56 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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	.find_pll = intel_g4x_find_best_PLL,
};

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/* LVDS 100mhz refclk limits. */
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static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 2 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
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	.p1 = { .min = 2, .max = 8 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 42 },
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	.p1 = { .min = 2, .max = 6 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_display_port = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000},
	.n = { .min = 1, .max = 2 },
	.m = { .min = 81, .max = 90 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 10, .max = 20 },
	.p1 = { .min = 1, .max = 2},
	.p2 = { .dot_limit = 0,
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		.p2_slow = 10, .p2_fast = 10 },
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	.find_pll = intel_find_pll_ironlake_dp,
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};

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static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
						int refclk)
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{
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	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	const intel_limit_t *limit;
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	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
		    LVDS_CLKB_POWER_UP) {
			/* LVDS dual channel */
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			if (refclk == 100000)
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				limit = &intel_limits_ironlake_dual_lvds_100m;
			else
				limit = &intel_limits_ironlake_dual_lvds;
		} else {
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			if (refclk == 100000)
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				limit = &intel_limits_ironlake_single_lvds_100m;
			else
				limit = &intel_limits_ironlake_single_lvds;
		}
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
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			HAS_eDP)
		limit = &intel_limits_ironlake_display_port;
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	else
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		limit = &intel_limits_ironlake_dac;
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	return limit;
}

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static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	const intel_limit_t *limit;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
		    LVDS_CLKB_POWER_UP)
			/* LVDS with dual channel */
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			limit = &intel_limits_g4x_dual_channel_lvds;
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		else
			/* LVDS with dual channel */
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			limit = &intel_limits_g4x_single_channel_lvds;
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	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
		   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
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		limit = &intel_limits_g4x_hdmi;
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	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
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		limit = &intel_limits_g4x_sdvo;
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	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
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		limit = &intel_limits_g4x_display_port;
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	} else /* The option is for other outputs */
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		limit = &intel_limits_i9xx_sdvo;
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	return limit;
}

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static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
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{
	struct drm_device *dev = crtc->dev;
	const intel_limit_t *limit;

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	if (HAS_PCH_SPLIT(dev))
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		limit = intel_ironlake_limit(crtc, refclk);
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	else if (IS_G4X(dev)) {
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		limit = intel_g4x_limit(crtc);
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	} else if (IS_PINEVIEW(dev)) {
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		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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			limit = &intel_limits_pineview_lvds;
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		else
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			limit = &intel_limits_pineview_sdvo;
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	} else if (!IS_GEN2(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
			limit = &intel_limits_i9xx_lvds;
		else
			limit = &intel_limits_i9xx_sdvo;
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	} else {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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			limit = &intel_limits_i8xx_lvds;
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		else
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			limit = &intel_limits_i8xx_dvo;
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	}
	return limit;
}

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/* m1 is reserved as 0 in Pineview, n is a ring counter */
static void pineview_clock(int refclk, intel_clock_t *clock)
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{
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	clock->m = clock->m2 + 2;
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / clock->n;
	clock->dot = clock->vco / clock->p;
}

static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
{
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	if (IS_PINEVIEW(dev)) {
		pineview_clock(refclk, clock);
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		return;
	}
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	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / (clock->n + 2);
	clock->dot = clock->vco / clock->p;
}

/**
 * Returns whether any output on the specified pipe is of the specified type
 */
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bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
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{
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	struct drm_device *dev = crtc->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;

	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
		if (encoder->base.crtc == crtc && encoder->type == type)
			return true;

	return false;
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}

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#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
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/**
 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */

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static bool intel_PLL_is_valid(struct drm_device *dev,
			       const intel_limit_t *limit,
			       const intel_clock_t *clock)
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{
	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
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		INTELPllInvalid("p1 out of range\n");
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	if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
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		INTELPllInvalid("p out of range\n");
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	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
500
		INTELPllInvalid("m2 out of range\n");
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	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
502
		INTELPllInvalid("m1 out of range\n");
503
	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
504
		INTELPllInvalid("m1 <= m2\n");
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	if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
506
		INTELPllInvalid("m out of range\n");
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	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
508
		INTELPllInvalid("n out of range\n");
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	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
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		INTELPllInvalid("vco out of range\n");
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	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
	 * connector, etc., rather than just a single range.
	 */
	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
515
		INTELPllInvalid("dot out of range\n");
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	return true;
}

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static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
522 523
		    int target, int refclk, intel_clock_t *match_clock,
		    intel_clock_t *best_clock)
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{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	intel_clock_t clock;
	int err = target;

531
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
532
	    (I915_READ(LVDS)) != 0) {
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		/*
		 * For LVDS, if the panel is on, just rely on its current
		 * settings for dual-channel.  We haven't figured out how to
		 * reliably set up different single/dual channel state, if we
		 * even can.
		 */
		if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
		    LVDS_CLKB_POWER_UP)
			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

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	memset(best_clock, 0, sizeof(*best_clock));
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	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
	     clock.m1++) {
		for (clock.m2 = limit->m2.min;
		     clock.m2 <= limit->m2.max; clock.m2++) {
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			/* m1 is always 0 in Pineview */
			if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
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				break;
			for (clock.n = limit->n.min;
			     clock.n <= limit->n.max; clock.n++) {
				for (clock.p1 = limit->p1.min;
					clock.p1 <= limit->p1.max; clock.p1++) {
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					int this_err;

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					intel_clock(dev, refclk, &clock);
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					if (!intel_PLL_is_valid(dev, limit,
								&clock))
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						continue;
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					if (match_clock &&
					    clock.p != match_clock->p)
						continue;
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					this_err = abs(clock.dot - target);
					if (this_err < err) {
						*best_clock = clock;
						err = this_err;
					}
				}
			}
		}
	}

	return (err != target);
}

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static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
589 590
			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock)
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{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	intel_clock_t clock;
	int max_n;
	bool found;
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	/* approximately equals target * 0.00585 */
	int err_most = (target >> 8) + (target >> 9);
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	found = false;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		int lvds_reg;

604
		if (HAS_PCH_SPLIT(dev))
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			lvds_reg = PCH_LVDS;
		else
			lvds_reg = LVDS;
		if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
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		    LVDS_CLKB_POWER_UP)
			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

	memset(best_clock, 0, sizeof(*best_clock));
	max_n = limit->n.max;
622
	/* based on hardware requirement, prefer smaller n to precision */
623
	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
624
		/* based on hardware requirement, prefere larger m1,m2 */
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		for (clock.m1 = limit->m1.max;
		     clock.m1 >= limit->m1.min; clock.m1--) {
			for (clock.m2 = limit->m2.max;
			     clock.m2 >= limit->m2.min; clock.m2--) {
				for (clock.p1 = limit->p1.max;
				     clock.p1 >= limit->p1.min; clock.p1--) {
					int this_err;

633
					intel_clock(dev, refclk, &clock);
634 635
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
636
						continue;
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					if (match_clock &&
					    clock.p != match_clock->p)
						continue;
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					this_err = abs(clock.dot - target);
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					if (this_err < err_most) {
						*best_clock = clock;
						err_most = this_err;
						max_n = clock.n;
						found = true;
					}
				}
			}
		}
	}
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	return found;
}

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static bool
656
intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
657 658
			   int target, int refclk, intel_clock_t *match_clock,
			   intel_clock_t *best_clock)
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{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;
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	if (target < 200000) {
		clock.n = 1;
		clock.p1 = 2;
		clock.p2 = 10;
		clock.m1 = 12;
		clock.m2 = 9;
	} else {
		clock.n = 2;
		clock.p1 = 1;
		clock.p2 = 10;
		clock.m1 = 14;
		clock.m2 = 8;
	}
	intel_clock(dev, refclk, &clock);
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
	return true;
}

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/* DisplayPort has only two frequencies, 162MHz and 270MHz */
static bool
intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
684 685
		      int target, int refclk, intel_clock_t *match_clock,
		      intel_clock_t *best_clock)
686
{
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	intel_clock_t clock;
	if (target < 200000) {
		clock.p1 = 2;
		clock.p2 = 10;
		clock.n = 2;
		clock.m1 = 23;
		clock.m2 = 8;
	} else {
		clock.p1 = 1;
		clock.p2 = 10;
		clock.n = 1;
		clock.m1 = 14;
		clock.m2 = 2;
	}
	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
	clock.p = (clock.p1 * clock.p2);
	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
	clock.vco = 0;
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
	return true;
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}

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/**
 * intel_wait_for_vblank - wait for vblank on a given pipe
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * Wait for vblank to occur on a given pipe.  Needed for various bits of
 * mode setting code.
 */
void intel_wait_for_vblank(struct drm_device *dev, int pipe)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	int pipestat_reg = PIPESTAT(pipe);
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	/* Clear existing vblank status. Note this will clear any other
	 * sticky status fields as well.
	 *
	 * This races with i915_driver_irq_handler() with the result
	 * that either function could miss a vblank event.  Here it is not
	 * fatal, as we will either wait upon the next vblank interrupt or
	 * timeout.  Generally speaking intel_wait_for_vblank() is only
	 * called during modeset at which time the GPU should be idle and
	 * should *not* be performing page flips and thus not waiting on
	 * vblanks...
	 * Currently, the result of us stealing a vblank from the irq
	 * handler is that a single frame will be skipped during swapbuffers.
	 */
	I915_WRITE(pipestat_reg,
		   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

738
	/* Wait for vblank interrupt bit to set */
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	if (wait_for(I915_READ(pipestat_reg) &
		     PIPE_VBLANK_INTERRUPT_STATUS,
		     50))
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		DRM_DEBUG_KMS("vblank wait timed out\n");
}

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/*
 * intel_wait_for_pipe_off - wait for pipe to turn off
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 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * After disabling a pipe, we can't wait for vblank in the usual way,
 * spinning on the vblank interrupt status bit, since we won't actually
 * see an interrupt when the pipe is disabled.
 *
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 * On Gen4 and above:
 *   wait for the pipe register state bit to turn off
 *
 * Otherwise:
 *   wait for the display line value to settle (it usually
 *   ends up stopping at the start of the next frame).
760
 *
761
 */
762
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
763 764
{
	struct drm_i915_private *dev_priv = dev->dev_private;
765 766

	if (INTEL_INFO(dev)->gen >= 4) {
767
		int reg = PIPECONF(pipe);
768 769

		/* Wait for the Pipe State to go off */
770 771
		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
			     100))
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			DRM_DEBUG_KMS("pipe_off wait timed out\n");
	} else {
		u32 last_line;
775
		int reg = PIPEDSL(pipe);
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		unsigned long timeout = jiffies + msecs_to_jiffies(100);

		/* Wait for the display line to settle */
		do {
780
			last_line = I915_READ(reg) & DSL_LINEMASK;
781
			mdelay(5);
782
		} while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
783 784 785 786
			 time_after(timeout, jiffies));
		if (time_after(jiffies, timeout))
			DRM_DEBUG_KMS("pipe_off wait timed out\n");
	}
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}

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static const char *state_string(bool enabled)
{
	return enabled ? "on" : "off";
}

/* Only for pre-ILK configs */
static void assert_pll(struct drm_i915_private *dev_priv,
		       enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

	reg = DPLL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & DPLL_VCO_ENABLE);
	WARN(cur_state != state,
	     "PLL state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
#define assert_pll_disabled(d, p) assert_pll(d, p, false)

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/* For ILK+ */
static void assert_pch_pll(struct drm_i915_private *dev_priv,
			   enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

820 821 822 823 824 825 826 827 828 829 830 831 832
	if (HAS_PCH_CPT(dev_priv->dev)) {
		u32 pch_dpll;

		pch_dpll = I915_READ(PCH_DPLL_SEL);

		/* Make sure the selected PLL is enabled to the transcoder */
		WARN(!((pch_dpll >> (4 * pipe)) & 8),
		     "transcoder %d PLL not enabled\n", pipe);

		/* Convert the transcoder pipe number to a pll pipe number */
		pipe = (pch_dpll >> (4 * pipe)) & 1;
	}

833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902
	reg = PCH_DPLL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & DPLL_VCO_ENABLE);
	WARN(cur_state != state,
	     "PCH PLL state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)

static void assert_fdi_tx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

	reg = FDI_TX_CTL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & FDI_TX_ENABLE);
	WARN(cur_state != state,
	     "FDI TX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)

static void assert_fdi_rx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

	reg = FDI_RX_CTL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & FDI_RX_ENABLE);
	WARN(cur_state != state,
	     "FDI RX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)

static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

	/* ILK FDI PLL is always enabled */
	if (dev_priv->info->gen == 5)
		return;

	reg = FDI_TX_CTL(pipe);
	val = I915_READ(reg);
	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
}

static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

	reg = FDI_RX_CTL(pipe);
	val = I915_READ(reg);
	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
}

903 904 905 906 907 908
static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
				  enum pipe pipe)
{
	int pp_reg, lvds_reg;
	u32 val;
	enum pipe panel_pipe = PIPE_A;
909
	bool locked = true;
910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928

	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		pp_reg = PCH_PP_CONTROL;
		lvds_reg = PCH_LVDS;
	} else {
		pp_reg = PP_CONTROL;
		lvds_reg = LVDS;
	}

	val = I915_READ(pp_reg);
	if (!(val & PANEL_POWER_ON) ||
	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		locked = false;

	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		panel_pipe = PIPE_B;

	WARN(panel_pipe == pipe && locked,
	     "panel assertion failure, pipe %c regs locked\n",
929
	     pipe_name(pipe));
930 931
}

932 933
void assert_pipe(struct drm_i915_private *dev_priv,
		 enum pipe pipe, bool state)
934 935 936
{
	int reg;
	u32 val;
937
	bool cur_state;
938

939 940 941 942
	/* if we need the pipe A quirk it must be always on */
	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		state = true;

943 944
	reg = PIPECONF(pipe);
	val = I915_READ(reg);
945 946 947
	cur_state = !!(val & PIPECONF_ENABLE);
	WARN(cur_state != state,
	     "pipe %c assertion failure (expected %s, current %s)\n",
948
	     pipe_name(pipe), state_string(state), state_string(cur_state));
949 950
}

951 952
static void assert_plane(struct drm_i915_private *dev_priv,
			 enum plane plane, bool state)
953 954 955
{
	int reg;
	u32 val;
956
	bool cur_state;
957 958 959

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
960 961 962 963
	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
	WARN(cur_state != state,
	     "plane %c assertion failure (expected %s, current %s)\n",
	     plane_name(plane), state_string(state), state_string(cur_state));
964 965
}

966 967 968
#define assert_plane_enabled(d, p) assert_plane(d, p, true)
#define assert_plane_disabled(d, p) assert_plane(d, p, false)

969 970 971 972 973 974 975
static void assert_planes_disabled(struct drm_i915_private *dev_priv,
				   enum pipe pipe)
{
	int reg, i;
	u32 val;
	int cur_pipe;

976
	/* Planes are fixed to pipes on ILK+ */
977 978 979 980 981 982
	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		reg = DSPCNTR(pipe);
		val = I915_READ(reg);
		WARN((val & DISPLAY_PLANE_ENABLE),
		     "plane %c assertion failure, should be disabled but not\n",
		     plane_name(pipe));
983
		return;
984
	}
985

986 987 988 989 990 991 992
	/* Need to check both planes against the pipe */
	for (i = 0; i < 2; i++) {
		reg = DSPCNTR(i);
		val = I915_READ(reg);
		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
			DISPPLANE_SEL_PIPE_SHIFT;
		WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
993 994
		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
		     plane_name(i), pipe_name(pipe));
995 996 997
	}
}

998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018
static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
{
	u32 val;
	bool enabled;

	val = I915_READ(PCH_DREF_CONTROL);
	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
			    DREF_SUPERSPREAD_SOURCE_MASK));
	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
}

static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
				       enum pipe pipe)
{
	int reg;
	u32 val;
	bool enabled;

	reg = TRANSCONF(pipe);
	val = I915_READ(reg);
	enabled = !!(val & TRANS_ENABLE);
1019 1020 1021
	WARN(enabled,
	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
	     pipe_name(pipe));
1022 1023
}

1024 1025
static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
			    enum pipe pipe, u32 port_sel, u32 val)
1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041
{
	if ((val & DP_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
			return false;
	} else {
		if ((val & DP_PIPE_MASK) != (pipe << 30))
			return false;
	}
	return true;
}

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static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & PORT_ENABLE) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
			return false;
	}
	return true;
}

static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & LVDS_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
			return false;
	}
	return true;
}

static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & ADPA_DAC_ENABLE) == 0)
		return false;
	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
			return false;
	}
	return true;
}

1089
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1090
				   enum pipe pipe, int reg, u32 port_sel)
1091
{
1092
	u32 val = I915_READ(reg);
1093
	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1094
	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1095
	     reg, pipe_name(pipe));
1096 1097 1098 1099 1100
}

static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
				     enum pipe pipe, int reg)
{
1101
	u32 val = I915_READ(reg);
1102
	WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1103
	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1104
	     reg, pipe_name(pipe));
1105 1106 1107 1108 1109 1110 1111 1112
}

static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

1113 1114 1115
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1116 1117 1118

	reg = PCH_ADPA;
	val = I915_READ(reg);
1119
	WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1120
	     "PCH VGA enabled on transcoder %c, should be disabled\n",
1121
	     pipe_name(pipe));
1122 1123 1124

	reg = PCH_LVDS;
	val = I915_READ(reg);
1125
	WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1126
	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
1127
	     pipe_name(pipe));
1128 1129 1130 1131 1132 1133

	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
	assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
}

1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200
/**
 * intel_enable_pll - enable a PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
 * make sure the PLL reg is writable first though, since the panel write
 * protect mechanism may be enabled.
 *
 * Note!  This is for pre-ILK only.
 */
static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
	int reg;
	u32 val;

	/* No really, not for ILK+ */
	BUG_ON(dev_priv->info->gen >= 5);

	/* PLL is protected by panel, make sure we can write it */
	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
		assert_panel_unlocked(dev_priv, pipe);

	reg = DPLL(pipe);
	val = I915_READ(reg);
	val |= DPLL_VCO_ENABLE;

	/* We do this three times for luck */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
}

/**
 * intel_disable_pll - disable a PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to disable
 *
 * Disable the PLL for @pipe, making sure the pipe is off first.
 *
 * Note!  This is for pre-ILK only.
 */
static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
	int reg;
	u32 val;

	/* Don't disable pipe A or pipe A PLLs if needed */
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		return;

	/* Make sure the pipe isn't still relying on us */
	assert_pipe_disabled(dev_priv, pipe);

	reg = DPLL(pipe);
	val = I915_READ(reg);
	val &= ~DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
}

1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214
/**
 * intel_enable_pch_pll - enable PCH PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * The PCH PLL needs to be enabled before the PCH transcoder, since it
 * drives the transcoder clock.
 */
static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
				 enum pipe pipe)
{
	int reg;
	u32 val;

1215 1216 1217
	if (pipe > 1)
		return;

1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235
	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);

	/* PCH refclock must be enabled first */
	assert_pch_refclk_enabled(dev_priv);

	reg = PCH_DPLL(pipe);
	val = I915_READ(reg);
	val |= DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(200);
}

static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
				  enum pipe pipe)
{
	int reg;
1236 1237
	u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
		pll_sel = TRANSC_DPLL_ENABLE;
1238

1239 1240 1241
	if (pipe > 1)
		return;

1242 1243 1244 1245 1246 1247
	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);

	/* Make sure transcoder isn't still depending on us */
	assert_transcoder_disabled(dev_priv, pipe);

1248 1249 1250 1251 1252 1253 1254 1255 1256
	if (pipe == 0)
		pll_sel |= TRANSC_DPLLA_SEL;
	else if (pipe == 1)
		pll_sel |= TRANSC_DPLLB_SEL;


	if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
		return;

1257 1258 1259 1260 1261 1262 1263 1264
	reg = PCH_DPLL(pipe);
	val = I915_READ(reg);
	val &= ~DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(200);
}

1265 1266 1267 1268
static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
				    enum pipe pipe)
{
	int reg;
1269
	u32 val, pipeconf_val;
1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282

	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);

	/* Make sure PCH DPLL is enabled */
	assert_pch_pll_enabled(dev_priv, pipe);

	/* FDI must be feeding us bits for PCH ports */
	assert_fdi_tx_enabled(dev_priv, pipe);
	assert_fdi_rx_enabled(dev_priv, pipe);

	reg = TRANSCONF(pipe);
	val = I915_READ(reg);
1283
	pipeconf_val = I915_READ(PIPECONF(pipe));
1284 1285 1286 1287 1288 1289 1290

	if (HAS_PCH_IBX(dev_priv->dev)) {
		/*
		 * make the BPC in transcoder be consistent with
		 * that in pipeconf reg.
		 */
		val &= ~PIPE_BPC_MASK;
1291
		val |= pipeconf_val & PIPE_BPC_MASK;
1292
	}
1293 1294 1295 1296 1297 1298 1299

	val &= ~TRANS_INTERLACE_MASK;
	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
		val |= TRANS_INTERLACED;
	else
		val |= TRANS_PROGRESSIVE;

1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314
	I915_WRITE(reg, val | TRANS_ENABLE);
	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
		DRM_ERROR("failed to enable transcoder %d\n", pipe);
}

static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
				     enum pipe pipe)
{
	int reg;
	u32 val;

	/* FDI relies on the transcoder */
	assert_fdi_tx_disabled(dev_priv, pipe);
	assert_fdi_rx_disabled(dev_priv, pipe);

1315 1316 1317
	/* Ports must be off as well */
	assert_pch_ports_disabled(dev_priv, pipe);

1318 1319 1320 1321 1322 1323
	reg = TRANSCONF(pipe);
	val = I915_READ(reg);
	val &= ~TRANS_ENABLE;
	I915_WRITE(reg, val);
	/* wait for PCH transcoder off, transcoder state */
	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1324
		DRM_ERROR("failed to disable transcoder %d\n", pipe);
1325 1326
}

1327
/**
1328
 * intel_enable_pipe - enable a pipe, asserting requirements
1329 1330
 * @dev_priv: i915 private structure
 * @pipe: pipe to enable
1331
 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1332 1333 1334 1335 1336 1337 1338 1339 1340
 *
 * Enable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe is actually running (i.e. first vblank) before
 * returning.
 */
1341 1342
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
			      bool pch_port)
1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353
{
	int reg;
	u32 val;

	/*
	 * A pipe without a PLL won't actually be able to drive bits from
	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
	 * need the check.
	 */
	if (!HAS_PCH_SPLIT(dev_priv->dev))
		assert_pll_enabled(dev_priv, pipe);
1354 1355 1356 1357 1358 1359 1360 1361
	else {
		if (pch_port) {
			/* if driving the PCH, we need FDI enabled */
			assert_fdi_rx_pll_enabled(dev_priv, pipe);
			assert_fdi_tx_pll_enabled(dev_priv, pipe);
		}
		/* FIXME: assert CPU port conditions for SNB+ */
	}
1362 1363 1364

	reg = PIPECONF(pipe);
	val = I915_READ(reg);
1365 1366 1367 1368
	if (val & PIPECONF_ENABLE)
		return;

	I915_WRITE(reg, val | PIPECONF_ENABLE);
1369 1370 1371 1372
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
1373
 * intel_disable_pipe - disable a pipe, asserting requirements
1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401
 * @dev_priv: i915 private structure
 * @pipe: pipe to disable
 *
 * Disable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe has shut down before returning.
 */
static void intel_disable_pipe(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
	int reg;
	u32 val;

	/*
	 * Make sure planes won't keep trying to pump pixels to us,
	 * or we might hang the display.
	 */
	assert_planes_disabled(dev_priv, pipe);

	/* Don't disable pipe A or pipe A PLLs if needed */
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		return;

	reg = PIPECONF(pipe);
	val = I915_READ(reg);
1402 1403 1404 1405
	if ((val & PIPECONF_ENABLE) == 0)
		return;

	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1406 1407 1408
	intel_wait_for_pipe_off(dev_priv->dev, pipe);
}

1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419
/*
 * Plane regs are double buffered, going from enabled->disabled needs a
 * trigger in order to latch.  The display address reg provides this.
 */
static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
				      enum plane plane)
{
	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
}

1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438
/**
 * intel_enable_plane - enable a display plane on a given pipe
 * @dev_priv: i915 private structure
 * @plane: plane to enable
 * @pipe: pipe being fed
 *
 * Enable @plane on @pipe, making sure that @pipe is running first.
 */
static void intel_enable_plane(struct drm_i915_private *dev_priv,
			       enum plane plane, enum pipe pipe)
{
	int reg;
	u32 val;

	/* If the pipe isn't enabled, we can't pump pixels and may hang */
	assert_pipe_enabled(dev_priv, pipe);

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1439 1440 1441 1442
	if (val & DISPLAY_PLANE_ENABLE)
		return;

	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1443
	intel_flush_display_plane(dev_priv, plane);
1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
 * intel_disable_plane - disable a display plane
 * @dev_priv: i915 private structure
 * @plane: plane to disable
 * @pipe: pipe consuming the data
 *
 * Disable @plane; should be an independent operation.
 */
static void intel_disable_plane(struct drm_i915_private *dev_priv,
				enum plane plane, enum pipe pipe)
{
	int reg;
	u32 val;

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1463 1464 1465 1466
	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		return;

	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1467 1468 1469 1470
	intel_flush_display_plane(dev_priv, plane);
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

1471
static void disable_pch_dp(struct drm_i915_private *dev_priv,
1472
			   enum pipe pipe, int reg, u32 port_sel)
1473 1474
{
	u32 val = I915_READ(reg);
1475
	if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1476
		DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1477
		I915_WRITE(reg, val & ~DP_PORT_EN);
1478
	}
1479 1480 1481 1482 1483 1484
}

static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
			     enum pipe pipe, int reg)
{
	u32 val = I915_READ(reg);
1485
	if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1486 1487
		DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
			      reg, pipe);
1488
		I915_WRITE(reg, val & ~PORT_ENABLE);
1489
	}
1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500
}

/* Disable any ports connected to this transcoder */
static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
				    enum pipe pipe)
{
	u32 reg, val;

	val = I915_READ(PCH_PP_CONTROL);
	I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);

1501 1502 1503
	disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
	disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
	disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1504 1505 1506

	reg = PCH_ADPA;
	val = I915_READ(reg);
1507
	if (adpa_pipe_enabled(dev_priv, val, pipe))
1508 1509 1510 1511
		I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);

	reg = PCH_LVDS;
	val = I915_READ(reg);
1512 1513
	if (lvds_pipe_enabled(dev_priv, val, pipe)) {
		DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1514 1515 1516 1517 1518 1519 1520 1521 1522 1523
		I915_WRITE(reg, val & ~LVDS_PORT_EN);
		POSTING_READ(reg);
		udelay(100);
	}

	disable_pch_hdmi(dev_priv, pipe, HDMIB);
	disable_pch_hdmi(dev_priv, pipe, HDMIC);
	disable_pch_hdmi(dev_priv, pipe, HDMID);
}

1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545
static void i8xx_disable_fbc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 fbc_ctl;

	/* Disable compression */
	fbc_ctl = I915_READ(FBC_CONTROL);
	if ((fbc_ctl & FBC_CTL_EN) == 0)
		return;

	fbc_ctl &= ~FBC_CTL_EN;
	I915_WRITE(FBC_CONTROL, fbc_ctl);

	/* Wait for compressing bit to clear */
	if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
		DRM_DEBUG_KMS("FBC idle timed out\n");
		return;
	}

	DRM_DEBUG_KMS("disabled FBC\n");
}

1546 1547 1548 1549 1550 1551
static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb = crtc->fb;
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1552
	struct drm_i915_gem_object *obj = intel_fb->obj;
1553
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1554
	int cfb_pitch;
1555 1556 1557
	int plane, i;
	u32 fbc_ctl, fbc_ctl2;

1558
	cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1559 1560
	if (fb->pitches[0] < cfb_pitch)
		cfb_pitch = fb->pitches[0];
1561 1562

	/* FBC_CTL wants 64B units */
1563 1564
	cfb_pitch = (cfb_pitch / 64) - 1;
	plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1565 1566 1567 1568 1569 1570

	/* Clear old tags */
	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
		I915_WRITE(FBC_TAG + (i * 4), 0);

	/* Set it up... */
1571 1572
	fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
	fbc_ctl2 |= plane;
1573 1574 1575 1576 1577
	I915_WRITE(FBC_CONTROL2, fbc_ctl2);
	I915_WRITE(FBC_FENCE_OFF, crtc->y);

	/* enable it... */
	fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1578
	if (IS_I945GM(dev))
1579
		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1580
	fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1581
	fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1582
	fbc_ctl |= obj->fence_reg;
1583 1584
	I915_WRITE(FBC_CONTROL, fbc_ctl);

1585 1586
	DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
		      cfb_pitch, crtc->y, intel_crtc->plane);
1587 1588
}

1589
static bool i8xx_fbc_enabled(struct drm_device *dev)
1590 1591 1592 1593 1594 1595
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
}

1596 1597 1598 1599 1600 1601
static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb = crtc->fb;
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1602
	struct drm_i915_gem_object *obj = intel_fb->obj;
1603
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1604
	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1605 1606 1607 1608
	unsigned long stall_watermark = 200;
	u32 dpfc_ctl;

	dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1609
	dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1610
	I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1611 1612 1613 1614 1615 1616 1617 1618 1619

	I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
		   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
		   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);

	/* enable it... */
	I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);

1620
	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1621 1622
}

1623
static void g4x_disable_fbc(struct drm_device *dev)
1624 1625 1626 1627 1628 1629
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpfc_ctl;

	/* Disable compression */
	dpfc_ctl = I915_READ(DPFC_CONTROL);
C
Chris Wilson 已提交
1630 1631 1632
	if (dpfc_ctl & DPFC_CTL_EN) {
		dpfc_ctl &= ~DPFC_CTL_EN;
		I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1633

C
Chris Wilson 已提交
1634 1635
		DRM_DEBUG_KMS("disabled FBC\n");
	}
1636 1637
}

1638
static bool g4x_fbc_enabled(struct drm_device *dev)
1639 1640 1641 1642 1643 1644
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
}

1645 1646 1647 1648 1649 1650
static void sandybridge_blit_fbc_update(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 blt_ecoskpd;

	/* Make sure blitter notifies FBC of writes */
1651
	gen6_gt_force_wake_get(dev_priv);
1652 1653 1654 1655 1656 1657 1658 1659 1660 1661
	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
		GEN6_BLITTER_LOCK_SHIFT;
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
	blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
			 GEN6_BLITTER_LOCK_SHIFT);
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
	POSTING_READ(GEN6_BLITTER_ECOSKPD);
1662
	gen6_gt_force_wake_put(dev_priv);
1663 1664
}

1665 1666 1667 1668 1669 1670
static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb = crtc->fb;
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1671
	struct drm_i915_gem_object *obj = intel_fb->obj;
1672
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1673
	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1674 1675 1676
	unsigned long stall_watermark = 200;
	u32 dpfc_ctl;

C
Chris Wilson 已提交
1677
	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1678 1679
	dpfc_ctl &= DPFC_RESERVED;
	dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1680 1681
	/* Set persistent mode for front-buffer rendering, ala X. */
	dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1682
	dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1683
	I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1684 1685 1686 1687 1688

	I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
		   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
		   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1689
	I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1690
	/* enable it... */
C
Chris Wilson 已提交
1691
	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1692

1693 1694
	if (IS_GEN6(dev)) {
		I915_WRITE(SNB_DPFC_CTL_SA,
1695
			   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1696
		I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1697
		sandybridge_blit_fbc_update(dev);
1698 1699
	}

1700 1701 1702
	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
}

1703
static void ironlake_disable_fbc(struct drm_device *dev)
1704 1705 1706 1707 1708 1709
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpfc_ctl;

	/* Disable compression */
	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
C
Chris Wilson 已提交
1710 1711 1712
	if (dpfc_ctl & DPFC_CTL_EN) {
		dpfc_ctl &= ~DPFC_CTL_EN;
		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1713

C
Chris Wilson 已提交
1714 1715
		DRM_DEBUG_KMS("disabled FBC\n");
	}
1716 1717 1718 1719 1720 1721 1722 1723 1724
}

static bool ironlake_fbc_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
}

1725 1726 1727 1728 1729 1730 1731 1732 1733 1734
bool intel_fbc_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv->display.fbc_enabled)
		return false;

	return dev_priv->display.fbc_enabled(dev);
}

1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747
static void intel_fbc_work_fn(struct work_struct *__work)
{
	struct intel_fbc_work *work =
		container_of(to_delayed_work(__work),
			     struct intel_fbc_work, work);
	struct drm_device *dev = work->crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	mutex_lock(&dev->struct_mutex);
	if (work == dev_priv->fbc_work) {
		/* Double check that we haven't switched fb without cancelling
		 * the prior work.
		 */
1748
		if (work->crtc->fb == work->fb) {
1749 1750 1751
			dev_priv->display.enable_fbc(work->crtc,
						     work->interval);

1752 1753 1754 1755 1756
			dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
			dev_priv->cfb_fb = work->crtc->fb->base.id;
			dev_priv->cfb_y = work->crtc->y;
		}

1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786
		dev_priv->fbc_work = NULL;
	}
	mutex_unlock(&dev->struct_mutex);

	kfree(work);
}

static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
{
	if (dev_priv->fbc_work == NULL)
		return;

	DRM_DEBUG_KMS("cancelling pending FBC enable\n");

	/* Synchronisation is provided by struct_mutex and checking of
	 * dev_priv->fbc_work, so we can perform the cancellation
	 * entirely asynchronously.
	 */
	if (cancel_delayed_work(&dev_priv->fbc_work->work))
		/* tasklet was killed before being run, clean up */
		kfree(dev_priv->fbc_work);

	/* Mark the work as no longer wanted so that if it does
	 * wake-up (because the work was already running and waiting
	 * for our mutex), it will discover that is no longer
	 * necessary to run.
	 */
	dev_priv->fbc_work = NULL;
}

1787
static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1788
{
1789 1790 1791
	struct intel_fbc_work *work;
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1792 1793 1794 1795

	if (!dev_priv->display.enable_fbc)
		return;

1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813
	intel_cancel_fbc_work(dev_priv);

	work = kzalloc(sizeof *work, GFP_KERNEL);
	if (work == NULL) {
		dev_priv->display.enable_fbc(crtc, interval);
		return;
	}

	work->crtc = crtc;
	work->fb = crtc->fb;
	work->interval = interval;
	INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);

	dev_priv->fbc_work = work;

	DRM_DEBUG_KMS("scheduling delayed FBC enable\n");

	/* Delay the actual enabling to let pageflipping cease and the
1814 1815 1816 1817
	 * display to settle before starting the compression. Note that
	 * this delay also serves a second purpose: it allows for a
	 * vblank to pass after disabling the FBC before we attempt
	 * to modify the control registers.
1818 1819 1820 1821 1822 1823 1824
	 *
	 * A more complicated solution would involve tracking vblanks
	 * following the termination of the page-flipping sequence
	 * and indeed performing the enable as a co-routine and not
	 * waiting synchronously upon the vblank.
	 */
	schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1825 1826 1827 1828 1829 1830
}

void intel_disable_fbc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1831 1832
	intel_cancel_fbc_work(dev_priv);

1833 1834 1835 1836
	if (!dev_priv->display.disable_fbc)
		return;

	dev_priv->display.disable_fbc(dev);
1837
	dev_priv->cfb_plane = -1;
1838 1839
}

1840 1841
/**
 * intel_update_fbc - enable/disable FBC as needed
C
Chris Wilson 已提交
1842
 * @dev: the drm_device
1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858
 *
 * Set up the framebuffer compression hardware at mode set time.  We
 * enable it if possible:
 *   - plane A only (on pre-965)
 *   - no pixel mulitply/line duplication
 *   - no alpha buffer discard
 *   - no dual wide
 *   - framebuffer <= 2048 in width, 1536 in height
 *
 * We can't assume that any compression will take place (worst case),
 * so the compressed buffer has to be the same size as the uncompressed
 * one.  It also must reside (along with the line length buffer) in
 * stolen memory.
 *
 * We need to enable/disable FBC on a global basis.
 */
C
Chris Wilson 已提交
1859
static void intel_update_fbc(struct drm_device *dev)
1860 1861
{
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
1862 1863 1864
	struct drm_crtc *crtc = NULL, *tmp_crtc;
	struct intel_crtc *intel_crtc;
	struct drm_framebuffer *fb;
1865
	struct intel_framebuffer *intel_fb;
1866
	struct drm_i915_gem_object *obj;
1867
	int enable_fbc;
1868 1869

	DRM_DEBUG_KMS("\n");
1870 1871 1872 1873

	if (!i915_powersave)
		return;

1874
	if (!I915_HAS_FBC(dev))
1875 1876
		return;

1877 1878 1879 1880
	/*
	 * If FBC is already on, we just have to verify that we can
	 * keep it that way...
	 * Need to disable if:
1881
	 *   - more than one pipe is active
1882 1883 1884 1885
	 *   - changing FBC params (stride, fence, mode)
	 *   - new fb is too large to fit in compressed buffer
	 *   - going to an unsupported config (interlace, pixel multiply, etc.)
	 */
1886
	list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1887
		if (tmp_crtc->enabled && tmp_crtc->fb) {
C
Chris Wilson 已提交
1888 1889 1890 1891 1892 1893 1894
			if (crtc) {
				DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
				dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
				goto out_disable;
			}
			crtc = tmp_crtc;
		}
1895
	}
C
Chris Wilson 已提交
1896 1897 1898 1899

	if (!crtc || crtc->fb == NULL) {
		DRM_DEBUG_KMS("no output, disabling\n");
		dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1900 1901
		goto out_disable;
	}
C
Chris Wilson 已提交
1902 1903 1904 1905

	intel_crtc = to_intel_crtc(crtc);
	fb = crtc->fb;
	intel_fb = to_intel_framebuffer(fb);
1906
	obj = intel_fb->obj;
C
Chris Wilson 已提交
1907

1908 1909 1910 1911
	enable_fbc = i915_enable_fbc;
	if (enable_fbc < 0) {
		DRM_DEBUG_KMS("fbc set to per-chip default\n");
		enable_fbc = 1;
1912
		if (INTEL_INFO(dev)->gen <= 6)
1913 1914 1915 1916
			enable_fbc = 0;
	}
	if (!enable_fbc) {
		DRM_DEBUG_KMS("fbc disabled per module param\n");
1917 1918 1919
		dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
		goto out_disable;
	}
1920
	if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1921
		DRM_DEBUG_KMS("framebuffer too large, disabling "
1922
			      "compression\n");
1923
		dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1924 1925
		goto out_disable;
	}
C
Chris Wilson 已提交
1926 1927
	if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
	    (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1928
		DRM_DEBUG_KMS("mode incompatible with compression, "
1929
			      "disabling\n");
1930
		dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1931 1932
		goto out_disable;
	}
C
Chris Wilson 已提交
1933 1934
	if ((crtc->mode.hdisplay > 2048) ||
	    (crtc->mode.vdisplay > 1536)) {
1935
		DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1936
		dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1937 1938
		goto out_disable;
	}
C
Chris Wilson 已提交
1939
	if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1940
		DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1941
		dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1942 1943
		goto out_disable;
	}
1944 1945 1946 1947 1948 1949 1950

	/* The use of a CPU fence is mandatory in order to detect writes
	 * by the CPU to the scanout and trigger updates to the FBC.
	 */
	if (obj->tiling_mode != I915_TILING_X ||
	    obj->fence_reg == I915_FENCE_REG_NONE) {
		DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1951
		dev_priv->no_fbc_reason = FBC_NOT_TILED;
1952 1953 1954
		goto out_disable;
	}

1955 1956 1957 1958
	/* If the kernel debugger is active, always disable compression */
	if (in_dbg_master())
		goto out_disable;

1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996
	/* If the scanout has not changed, don't modify the FBC settings.
	 * Note that we make the fundamental assumption that the fb->obj
	 * cannot be unpinned (and have its GTT offset and fence revoked)
	 * without first being decoupled from the scanout and FBC disabled.
	 */
	if (dev_priv->cfb_plane == intel_crtc->plane &&
	    dev_priv->cfb_fb == fb->base.id &&
	    dev_priv->cfb_y == crtc->y)
		return;

	if (intel_fbc_enabled(dev)) {
		/* We update FBC along two paths, after changing fb/crtc
		 * configuration (modeswitching) and after page-flipping
		 * finishes. For the latter, we know that not only did
		 * we disable the FBC at the start of the page-flip
		 * sequence, but also more than one vblank has passed.
		 *
		 * For the former case of modeswitching, it is possible
		 * to switch between two FBC valid configurations
		 * instantaneously so we do need to disable the FBC
		 * before we can modify its control registers. We also
		 * have to wait for the next vblank for that to take
		 * effect. However, since we delay enabling FBC we can
		 * assume that a vblank has passed since disabling and
		 * that we can safely alter the registers in the deferred
		 * callback.
		 *
		 * In the scenario that we go from a valid to invalid
		 * and then back to valid FBC configuration we have
		 * no strict enforcement that a vblank occurred since
		 * disabling the FBC. However, along all current pipe
		 * disabling paths we do need to wait for a vblank at
		 * some point. And we wait before enabling FBC anyway.
		 */
		DRM_DEBUG_KMS("disabling active FBC for update\n");
		intel_disable_fbc(dev);
	}

C
Chris Wilson 已提交
1997
	intel_enable_fbc(crtc, 500);
1998 1999 2000 2001
	return;

out_disable:
	/* Multiple disables should be harmless */
2002 2003
	if (intel_fbc_enabled(dev)) {
		DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2004
		intel_disable_fbc(dev);
2005
	}
2006 2007
}

2008
int
2009
intel_pin_and_fence_fb_obj(struct drm_device *dev,
2010
			   struct drm_i915_gem_object *obj,
2011
			   struct intel_ring_buffer *pipelined)
2012
{
2013
	struct drm_i915_private *dev_priv = dev->dev_private;
2014 2015 2016
	u32 alignment;
	int ret;

2017
	switch (obj->tiling_mode) {
2018
	case I915_TILING_NONE:
2019 2020
		if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
			alignment = 128 * 1024;
2021
		else if (INTEL_INFO(dev)->gen >= 4)
2022 2023 2024
			alignment = 4 * 1024;
		else
			alignment = 64 * 1024;
2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037
		break;
	case I915_TILING_X:
		/* pin() will align the object as required by fence */
		alignment = 0;
		break;
	case I915_TILING_Y:
		/* FIXME: Is this true? */
		DRM_ERROR("Y tiled not allowed for scan out buffers\n");
		return -EINVAL;
	default:
		BUG();
	}

2038
	dev_priv->mm.interruptible = false;
2039
	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2040
	if (ret)
2041
		goto err_interruptible;
2042 2043 2044 2045 2046 2047

	/* Install a fence for tiled scan-out. Pre-i965 always needs a
	 * fence, whereas 965+ only requires a fence if using
	 * framebuffer compression.  For simplicity, we always install
	 * a fence as the cost is not that onerous.
	 */
2048
	if (obj->tiling_mode != I915_TILING_NONE) {
2049
		ret = i915_gem_object_get_fence(obj, pipelined);
2050 2051
		if (ret)
			goto err_unpin;
2052 2053

		i915_gem_object_pin_fence(obj);
2054 2055
	}

2056
	dev_priv->mm.interruptible = true;
2057
	return 0;
2058 2059 2060

err_unpin:
	i915_gem_object_unpin(obj);
2061 2062
err_interruptible:
	dev_priv->mm.interruptible = true;
2063
	return ret;
2064 2065
}

2066 2067 2068 2069 2070 2071
void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_fence(obj);
	i915_gem_object_unpin(obj);
}

2072 2073
static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			     int x, int y)
J
Jesse Barnes 已提交
2074 2075 2076 2077 2078
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_framebuffer *intel_fb;
2079
	struct drm_i915_gem_object *obj;
J
Jesse Barnes 已提交
2080 2081 2082
	int plane = intel_crtc->plane;
	unsigned long Start, Offset;
	u32 dspcntr;
2083
	u32 reg;
J
Jesse Barnes 已提交
2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096

	switch (plane) {
	case 0:
	case 1:
		break;
	default:
		DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		return -EINVAL;
	}

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

2097 2098
	reg = DSPCNTR(plane);
	dspcntr = I915_READ(reg);
J
Jesse Barnes 已提交
2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115
	/* Mask out pixel format bits in case we change it */
	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
	switch (fb->bits_per_pixel) {
	case 8:
		dspcntr |= DISPPLANE_8BPP;
		break;
	case 16:
		if (fb->depth == 15)
			dspcntr |= DISPPLANE_15_16BPP;
		else
			dspcntr |= DISPPLANE_16BPP;
		break;
	case 24:
	case 32:
		dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
		break;
	default:
2116
		DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
J
Jesse Barnes 已提交
2117 2118
		return -EINVAL;
	}
2119
	if (INTEL_INFO(dev)->gen >= 4) {
2120
		if (obj->tiling_mode != I915_TILING_NONE)
J
Jesse Barnes 已提交
2121 2122 2123 2124 2125
			dspcntr |= DISPPLANE_TILED;
		else
			dspcntr &= ~DISPPLANE_TILED;
	}

2126
	I915_WRITE(reg, dspcntr);
J
Jesse Barnes 已提交
2127

2128
	Start = obj->gtt_offset;
2129
	Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
J
Jesse Barnes 已提交
2130

2131
	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2132 2133
		      Start, Offset, x, y, fb->pitches[0]);
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2134
	if (INTEL_INFO(dev)->gen >= 4) {
2135 2136 2137 2138 2139 2140
		I915_WRITE(DSPSURF(plane), Start);
		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
		I915_WRITE(DSPADDR(plane), Offset);
	} else
		I915_WRITE(DSPADDR(plane), Start + Offset);
	POSTING_READ(reg);
J
Jesse Barnes 已提交
2141

2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160
	return 0;
}

static int ironlake_update_plane(struct drm_crtc *crtc,
				 struct drm_framebuffer *fb, int x, int y)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_framebuffer *intel_fb;
	struct drm_i915_gem_object *obj;
	int plane = intel_crtc->plane;
	unsigned long Start, Offset;
	u32 dspcntr;
	u32 reg;

	switch (plane) {
	case 0:
	case 1:
J
Jesse Barnes 已提交
2161
	case 2:
2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209
		break;
	default:
		DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		return -EINVAL;
	}

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

	reg = DSPCNTR(plane);
	dspcntr = I915_READ(reg);
	/* Mask out pixel format bits in case we change it */
	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
	switch (fb->bits_per_pixel) {
	case 8:
		dspcntr |= DISPPLANE_8BPP;
		break;
	case 16:
		if (fb->depth != 16)
			return -EINVAL;

		dspcntr |= DISPPLANE_16BPP;
		break;
	case 24:
	case 32:
		if (fb->depth == 24)
			dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
		else if (fb->depth == 30)
			dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
		else
			return -EINVAL;
		break;
	default:
		DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
		return -EINVAL;
	}

	if (obj->tiling_mode != I915_TILING_NONE)
		dspcntr |= DISPPLANE_TILED;
	else
		dspcntr &= ~DISPPLANE_TILED;

	/* must disable */
	dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

	I915_WRITE(reg, dspcntr);

	Start = obj->gtt_offset;
2210
	Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2211 2212

	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2213 2214
		      Start, Offset, x, y, fb->pitches[0]);
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235
	I915_WRITE(DSPSURF(plane), Start);
	I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
	I915_WRITE(DSPADDR(plane), Offset);
	POSTING_READ(reg);

	return 0;
}

/* Assume fb object is pinned & idle & fenced and just update base pointers */
static int
intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			   int x, int y, enum mode_set_atomic state)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = dev_priv->display.update_plane(crtc, fb, x, y);
	if (ret)
		return ret;

C
Chris Wilson 已提交
2236
	intel_update_fbc(dev);
2237
	intel_increase_pllclock(crtc);
J
Jesse Barnes 已提交
2238 2239 2240 2241

	return 0;
}

2242
static int
2243 2244
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
		    struct drm_framebuffer *old_fb)
J
Jesse Barnes 已提交
2245 2246 2247 2248
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2249
	int ret;
J
Jesse Barnes 已提交
2250 2251 2252

	/* no fb bound */
	if (!crtc->fb) {
2253
		DRM_ERROR("No FB bound\n");
2254 2255 2256
		return 0;
	}

2257
	switch (intel_crtc->plane) {
2258 2259 2260
	case 0:
	case 1:
		break;
J
Jesse Barnes 已提交
2261 2262 2263 2264
	case 2:
		if (IS_IVYBRIDGE(dev))
			break;
		/* fall through otherwise */
2265
	default:
2266
		DRM_ERROR("no plane for crtc\n");
2267
		return -EINVAL;
J
Jesse Barnes 已提交
2268 2269
	}

2270
	mutex_lock(&dev->struct_mutex);
2271 2272
	ret = intel_pin_and_fence_fb_obj(dev,
					 to_intel_framebuffer(crtc->fb)->obj,
2273
					 NULL);
2274 2275
	if (ret != 0) {
		mutex_unlock(&dev->struct_mutex);
2276
		DRM_ERROR("pin & fence failed\n");
2277 2278
		return ret;
	}
J
Jesse Barnes 已提交
2279

2280
	if (old_fb) {
2281
		struct drm_i915_private *dev_priv = dev->dev_private;
2282
		struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2283

2284
		wait_event(dev_priv->pending_flip_queue,
2285
			   atomic_read(&dev_priv->mm.wedged) ||
2286
			   atomic_read(&obj->pending_flip) == 0);
2287 2288 2289 2290 2291

		/* Big Hammer, we also need to ensure that any pending
		 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
		 * current scanout is retired before unpinning the old
		 * framebuffer.
2292 2293 2294
		 *
		 * This should only fail upon a hung GPU, in which case we
		 * can safely continue.
2295
		 */
2296
		ret = i915_gem_object_finish_gpu(obj);
2297
		(void) ret;
2298 2299
	}

2300 2301
	ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
					 LEAVE_ATOMIC_MODE_SET);
2302
	if (ret) {
2303
		intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2304
		mutex_unlock(&dev->struct_mutex);
2305
		DRM_ERROR("failed to update base address\n");
2306
		return ret;
J
Jesse Barnes 已提交
2307
	}
2308

2309 2310
	if (old_fb) {
		intel_wait_for_vblank(dev, intel_crtc->pipe);
2311
		intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2312
	}
2313

2314
	mutex_unlock(&dev->struct_mutex);
J
Jesse Barnes 已提交
2315 2316

	if (!dev->primary->master)
2317
		return 0;
J
Jesse Barnes 已提交
2318 2319 2320

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
2321
		return 0;
J
Jesse Barnes 已提交
2322

2323
	if (intel_crtc->pipe) {
J
Jesse Barnes 已提交
2324 2325
		master_priv->sarea_priv->pipeB_x = x;
		master_priv->sarea_priv->pipeB_y = y;
2326 2327 2328
	} else {
		master_priv->sarea_priv->pipeA_x = x;
		master_priv->sarea_priv->pipeA_y = y;
J
Jesse Barnes 已提交
2329
	}
2330 2331

	return 0;
J
Jesse Barnes 已提交
2332 2333
}

2334
static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2335 2336 2337 2338 2339
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

2340
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

	if (clock < 200000) {
		u32 temp;
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
		/* workaround for 160Mhz:
		   1) program 0x4600c bits 15:0 = 0x8124
		   2) program 0x46010 bit 0 = 1
		   3) program 0x46034 bit 24 = 1
		   4) program 0x64000 bit 14 = 1
		   */
		temp = I915_READ(0x4600c);
		temp &= 0xffff0000;
		I915_WRITE(0x4600c, temp | 0x8124);

		temp = I915_READ(0x46010);
		I915_WRITE(0x46010, temp | 1);

		temp = I915_READ(0x46034);
		I915_WRITE(0x46034, temp | (1 << 24));
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
	}
	I915_WRITE(DP_A, dpa_ctl);

2367
	POSTING_READ(DP_A);
2368 2369 2370
	udelay(500);
}

2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381
static void intel_fdi_normal_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* enable normal train */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2382
	if (IS_IVYBRIDGE(dev)) {
2383 2384
		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2385 2386 2387
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2388
	}
2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_NORMAL_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_NONE;
	}
	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

	/* wait one idle pattern time */
	POSTING_READ(reg);
	udelay(1000);
2405 2406 2407 2408 2409

	/* IVB wants error correction enabled */
	if (IS_IVYBRIDGE(dev))
		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
			   FDI_FE_ERRC_ENABLE);
2410 2411
}

2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423
static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 flags = I915_READ(SOUTH_CHICKEN1);

	flags |= FDI_PHASE_SYNC_OVR(pipe);
	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
	flags |= FDI_PHASE_SYNC_EN(pipe);
	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
	POSTING_READ(SOUTH_CHICKEN1);
}

2424 2425 2426 2427 2428 2429 2430
/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2431
	int plane = intel_crtc->plane;
2432
	u32 reg, temp, tries;
2433

2434 2435 2436 2437
	/* FDI needs bits from pipe & plane first */
	assert_pipe_enabled(dev_priv, pipe);
	assert_plane_enabled(dev_priv, plane);

2438 2439
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
2440 2441
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
2442 2443
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
2444 2445
	I915_WRITE(reg, temp);
	I915_READ(reg);
2446 2447
	udelay(150);

2448
	/* enable CPU FDI TX and PCH FDI RX */
2449 2450
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2451 2452
	temp &= ~(7 << 19);
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2453 2454
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
2455
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2456

2457 2458
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2459 2460
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
2461 2462 2463
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
2464 2465
	udelay(150);

2466
	/* Ironlake workaround, enable clock pointer after FDI enable*/
2467 2468 2469 2470 2471
	if (HAS_PCH_IBX(dev)) {
		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
			   FDI_RX_PHASE_SYNC_POINTER_EN);
	}
2472

2473
	reg = FDI_RX_IIR(pipe);
2474
	for (tries = 0; tries < 5; tries++) {
2475
		temp = I915_READ(reg);
2476 2477 2478 2479
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if ((temp & FDI_RX_BIT_LOCK)) {
			DRM_DEBUG_KMS("FDI train 1 done.\n");
2480
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2481 2482 2483
			break;
		}
	}
2484
	if (tries == 5)
2485
		DRM_ERROR("FDI train 1 fail!\n");
2486 2487

	/* Train 2 */
2488 2489
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2490 2491
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
2492
	I915_WRITE(reg, temp);
2493

2494 2495
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2496 2497
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
2498
	I915_WRITE(reg, temp);
2499

2500 2501
	POSTING_READ(reg);
	udelay(150);
2502

2503
	reg = FDI_RX_IIR(pipe);
2504
	for (tries = 0; tries < 5; tries++) {
2505
		temp = I915_READ(reg);
2506 2507 2508
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
2509
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2510 2511 2512 2513
			DRM_DEBUG_KMS("FDI train 2 done.\n");
			break;
		}
	}
2514
	if (tries == 5)
2515
		DRM_ERROR("FDI train 2 fail!\n");
2516 2517

	DRM_DEBUG_KMS("FDI train done\n");
2518

2519 2520
}

2521
static const int snb_b_fdi_train_param[] = {
2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534
	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
};

/* The FDI link training functions for SNB/Cougarpoint. */
static void gen6_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2535
	u32 reg, temp, i;
2536

2537 2538
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
2539 2540
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
2541 2542
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
2543 2544 2545
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
2546 2547
	udelay(150);

2548
	/* enable CPU FDI TX and PCH FDI RX */
2549 2550
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2551 2552
	temp &= ~(7 << 19);
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2553 2554 2555 2556 2557
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	/* SNB-B */
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2558
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2559

2560 2561
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2562 2563 2564 2565 2566 2567 2568
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
2569 2570 2571
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
2572 2573
	udelay(150);

2574 2575 2576
	if (HAS_PCH_CPT(dev))
		cpt_phase_pointer_enable(dev, pipe);

2577
	for (i = 0; i < 4; i++) {
2578 2579
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2580 2581
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
2582 2583 2584
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
2585 2586
		udelay(500);

2587 2588
		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
2589 2590 2591
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_BIT_LOCK) {
2592
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2593 2594 2595 2596 2597
			DRM_DEBUG_KMS("FDI train 1 done.\n");
			break;
		}
	}
	if (i == 4)
2598
		DRM_ERROR("FDI train 1 fail!\n");
2599 2600

	/* Train 2 */
2601 2602
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2603 2604 2605 2606 2607 2608 2609
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
	if (IS_GEN6(dev)) {
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		/* SNB-B */
		temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
	}
2610
	I915_WRITE(reg, temp);
2611

2612 2613
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2614 2615 2616 2617 2618 2619 2620
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_2;
	}
2621 2622 2623
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
2624 2625
	udelay(150);

2626
	for (i = 0; i < 4; i++) {
2627 2628
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2629 2630
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
2631 2632 2633
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
2634 2635
		udelay(500);

2636 2637
		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
2638 2639 2640
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
2641
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2642 2643 2644 2645 2646
			DRM_DEBUG_KMS("FDI train 2 done.\n");
			break;
		}
	}
	if (i == 4)
2647
		DRM_ERROR("FDI train 2 fail!\n");
2648 2649 2650 2651

	DRM_DEBUG_KMS("FDI train done.\n");
}

2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680
/* Manual link training for Ivy Bridge A0 parts */
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp, i;

	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

	/* enable CPU FDI TX and PCH FDI RX */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~(7 << 19);
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
	temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
	temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2681
	temp |= FDI_COMPOSITE_SYNC;
2682 2683 2684 2685 2686 2687 2688
	I915_WRITE(reg, temp | FDI_TX_ENABLE);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_AUTO;
	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
	temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2689
	temp |= FDI_COMPOSITE_SYNC;
2690 2691 2692 2693 2694
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(150);

2695 2696 2697
	if (HAS_PCH_CPT(dev))
		cpt_phase_pointer_enable(dev, pipe);

2698
	for (i = 0; i < 4; i++) {
2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
		udelay(500);

		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_BIT_LOCK ||
		    (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
			DRM_DEBUG_KMS("FDI train 1 done.\n");
			break;
		}
	}
	if (i == 4)
		DRM_ERROR("FDI train 1 fail!\n");

	/* Train 2 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
	temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
	temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

2740
	for (i = 0; i < 4; i++) {
2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
		udelay(500);

		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
			DRM_DEBUG_KMS("FDI train 2 done.\n");
			break;
		}
	}
	if (i == 4)
		DRM_ERROR("FDI train 2 fail!\n");

	DRM_DEBUG_KMS("FDI train done.\n");
}

static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2767 2768 2769 2770 2771
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2772
	u32 reg, temp;
J
Jesse Barnes 已提交
2773

2774
	/* Write the TU size bits so error detection works */
2775 2776
	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2777

2778
	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2779 2780 2781
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~((0x7 << 19) | (0x7 << 16));
2782
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2783 2784 2785 2786
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

	POSTING_READ(reg);
2787 2788 2789
	udelay(200);

	/* Switch from Rawclk to PCDclk */
2790 2791 2792 2793
	temp = I915_READ(reg);
	I915_WRITE(reg, temp | FDI_PCDCLK);

	POSTING_READ(reg);
2794 2795 2796
	udelay(200);

	/* Enable CPU FDI TX PLL, always on for Ironlake */
2797 2798
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2799
	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2800 2801 2802
		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);

		POSTING_READ(reg);
2803
		udelay(100);
2804
	}
2805 2806
}

2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817
static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 flags = I915_READ(SOUTH_CHICKEN1);

	flags &= ~(FDI_PHASE_SYNC_EN(pipe));
	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
	flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
	POSTING_READ(SOUTH_CHICKEN1);
}
2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841
static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* disable CPU FDI tx and PCH FDI rx */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
	POSTING_READ(reg);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~(0x7 << 16);
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(100);

	/* Ironlake workaround, disable clock pointer after downing FDI */
2842 2843
	if (HAS_PCH_IBX(dev)) {
		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2844 2845
		I915_WRITE(FDI_RX_CHICKEN(pipe),
			   I915_READ(FDI_RX_CHICKEN(pipe) &
2846
				     ~FDI_RX_PHASE_SYNC_POINTER_EN));
2847 2848
	} else if (HAS_PCH_CPT(dev)) {
		cpt_phase_pointer_disable(dev, pipe);
2849
	}
2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875

	/* still set train pattern 1 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
	/* BPC in FDI rx is consistent with that in PIPECONF */
	temp &= ~(0x07 << 16);
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(100);
}

2876 2877 2878 2879 2880 2881 2882
/*
 * When we disable a pipe, we need to clear any pending scanline wait events
 * to avoid hanging the ring, which we assume we are waiting on.
 */
static void intel_clear_scanline_wait(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2883
	struct intel_ring_buffer *ring;
2884 2885 2886 2887 2888 2889
	u32 tmp;

	if (IS_GEN2(dev))
		/* Can't break the hang on i8xx */
		return;

2890
	ring = LP_RING(dev_priv);
2891 2892 2893
	tmp = I915_READ_CTL(ring);
	if (tmp & RING_WAIT)
		I915_WRITE_CTL(ring, tmp);
2894 2895
}

2896 2897
static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
{
2898
	struct drm_i915_gem_object *obj;
2899 2900 2901 2902 2903
	struct drm_i915_private *dev_priv;

	if (crtc->fb == NULL)
		return;

2904
	obj = to_intel_framebuffer(crtc->fb)->obj;
2905 2906
	dev_priv = crtc->dev->dev_private;
	wait_event(dev_priv->pending_flip_queue,
2907
		   atomic_read(&obj->pending_flip) == 0);
2908 2909
}

2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934
static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;

	/*
	 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
	 * must be driven by its own crtc; no sharing is possible.
	 */
	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		if (encoder->base.crtc != crtc)
			continue;

		switch (encoder->type) {
		case INTEL_OUTPUT_EDP:
			if (!intel_encoder_is_pch_edp(&encoder->base))
				return false;
			continue;
		}
	}

	return true;
}

2935 2936 2937 2938 2939 2940 2941 2942 2943
/*
 * Enable PCH resources required for PCH ports:
 *   - PCH PLLs
 *   - FDI training & RX/TX
 *   - update transcoder timings
 *   - DP transcoding bits
 *   - transcoder
 */
static void ironlake_pch_enable(struct drm_crtc *crtc)
2944 2945 2946 2947 2948
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2949
	u32 reg, temp, transc_sel;
2950

2951
	/* For PCH output, training FDI link */
2952
	dev_priv->display.fdi_link_train(crtc);
2953

2954
	intel_enable_pch_pll(dev_priv, pipe);
2955

2956
	if (HAS_PCH_CPT(dev)) {
2957 2958 2959
		transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
			TRANSC_DPLLB_SEL;

2960 2961
		/* Be sure PCH DPLL SEL is set */
		temp = I915_READ(PCH_DPLL_SEL);
2962 2963
		if (pipe == 0) {
			temp &= ~(TRANSA_DPLLB_SEL);
2964
			temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2965 2966
		} else if (pipe == 1) {
			temp &= ~(TRANSB_DPLLB_SEL);
2967
			temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2968 2969
		} else if (pipe == 2) {
			temp &= ~(TRANSC_DPLLB_SEL);
2970
			temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2971
		}
2972 2973
		I915_WRITE(PCH_DPLL_SEL, temp);
	}
2974

2975 2976
	/* set transcoder timing, panel must allow it */
	assert_panel_unlocked(dev_priv, pipe);
2977 2978 2979
	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
	I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2980

2981 2982 2983
	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2984
	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2985

2986 2987
	intel_fdi_normal_train(crtc);

2988 2989
	/* For PCH DP, enable TRANS_DP_CTL */
	if (HAS_PCH_CPT(dev) &&
2990 2991
	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2992
		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2993 2994 2995
		reg = TRANS_DP_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(TRANS_DP_PORT_SEL_MASK |
2996 2997
			  TRANS_DP_SYNC_MASK |
			  TRANS_DP_BPC_MASK);
2998 2999
		temp |= (TRANS_DP_OUTPUT_ENABLE |
			 TRANS_DP_ENH_FRAMING);
3000
		temp |= bpc << 9; /* same format but at 11:9 */
3001 3002

		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3003
			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3004
		if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3005
			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3006 3007 3008

		switch (intel_trans_dp_port_sel(crtc)) {
		case PCH_DP_B:
3009
			temp |= TRANS_DP_PORT_SEL_B;
3010 3011
			break;
		case PCH_DP_C:
3012
			temp |= TRANS_DP_PORT_SEL_C;
3013 3014
			break;
		case PCH_DP_D:
3015
			temp |= TRANS_DP_PORT_SEL_D;
3016 3017 3018
			break;
		default:
			DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3019
			temp |= TRANS_DP_PORT_SEL_B;
3020
			break;
3021
		}
3022

3023
		I915_WRITE(reg, temp);
3024
	}
3025

3026
	intel_enable_transcoder(dev_priv, pipe);
3027 3028
}

3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046
void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
	u32 temp;

	temp = I915_READ(dslreg);
	udelay(500);
	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		/* Without this, mode sets may fail silently on FDI */
		I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
		udelay(250);
		I915_WRITE(tc2reg, 0);
		if (wait_for(I915_READ(dslreg) != temp, 5))
			DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
	}
}

3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071
static void ironlake_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	u32 temp;
	bool is_pch_port;

	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
	intel_update_watermarks(dev);

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		temp = I915_READ(PCH_LVDS);
		if ((temp & LVDS_PORT_EN) == 0)
			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
	}

	is_pch_port = intel_crtc_driving_pch(crtc);

	if (is_pch_port)
3072
		ironlake_fdi_pll_enable(crtc);
3073 3074 3075 3076 3077 3078 3079 3080 3081 3082
	else
		ironlake_fdi_disable(crtc);

	/* Enable panel fitting for LVDS */
	if (dev_priv->pch_pf_size &&
	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
		/* Force use of hard-coded filter coefficients
		 * as some pre-programmed values are broken,
		 * e.g. x201.
		 */
3083 3084 3085
		I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
		I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3086 3087
	}

3088 3089 3090 3091 3092 3093
	/*
	 * On ILK+ LUT must be loaded before the pipe is running but with
	 * clocks enabled
	 */
	intel_crtc_load_lut(crtc);

3094 3095 3096 3097 3098
	intel_enable_pipe(dev_priv, pipe, is_pch_port);
	intel_enable_plane(dev_priv, plane, pipe);

	if (is_pch_port)
		ironlake_pch_enable(crtc);
3099

3100
	mutex_lock(&dev->struct_mutex);
C
Chris Wilson 已提交
3101
	intel_update_fbc(dev);
3102 3103
	mutex_unlock(&dev->struct_mutex);

3104
	intel_crtc_update_cursor(crtc, true);
3105 3106 3107 3108 3109 3110 3111 3112 3113
}

static void ironlake_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3114
	u32 reg, temp;
3115

3116 3117 3118
	if (!intel_crtc->active)
		return;

3119
	intel_crtc_wait_for_pending_flips(crtc);
3120
	drm_vblank_off(dev, pipe);
3121
	intel_crtc_update_cursor(crtc, false);
3122

3123
	intel_disable_plane(dev_priv, plane, pipe);
3124

3125 3126
	if (dev_priv->cfb_plane == plane)
		intel_disable_fbc(dev);
3127

3128
	intel_disable_pipe(dev_priv, pipe);
3129

3130
	/* Disable PF */
3131 3132
	I915_WRITE(PF_CTL(pipe), 0);
	I915_WRITE(PF_WIN_SZ(pipe), 0);
3133

3134
	ironlake_fdi_disable(crtc);
3135

3136 3137 3138 3139 3140 3141
	/* This is a horrible layering violation; we should be doing this in
	 * the connector/encoder ->prepare instead, but we don't always have
	 * enough information there about the config to know whether it will
	 * actually be necessary or just cause undesired flicker.
	 */
	intel_disable_pch_ports(dev_priv, pipe);
3142

3143
	intel_disable_transcoder(dev_priv, pipe);
3144

3145 3146
	if (HAS_PCH_CPT(dev)) {
		/* disable TRANS_DP_CTL */
3147 3148 3149
		reg = TRANS_DP_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3150
		temp |= TRANS_DP_PORT_SEL_NONE;
3151
		I915_WRITE(reg, temp);
3152 3153 3154

		/* disable DPLL_SEL */
		temp = I915_READ(PCH_DPLL_SEL);
3155 3156
		switch (pipe) {
		case 0:
3157
			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3158 3159
			break;
		case 1:
3160
			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3161 3162
			break;
		case 2:
3163
			/* C shares PLL A or B */
3164
			temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3165 3166 3167 3168
			break;
		default:
			BUG(); /* wtf */
		}
3169 3170
		I915_WRITE(PCH_DPLL_SEL, temp);
	}
3171

3172
	/* disable PCH DPLL */
3173 3174
	if (!intel_crtc->no_pll)
		intel_disable_pch_pll(dev_priv, pipe);
3175

3176
	/* Switch from PCDclk to Rawclk */
3177 3178 3179
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_PCDCLK);
3180

3181
	/* Disable CPU FDI TX PLL */
3182 3183 3184 3185 3186
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);

	POSTING_READ(reg);
3187
	udelay(100);
3188

3189 3190 3191
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3192

3193
	/* Wait for the clocks to turn off. */
3194
	POSTING_READ(reg);
3195
	udelay(100);
3196

3197
	intel_crtc->active = false;
3198
	intel_update_watermarks(dev);
3199 3200

	mutex_lock(&dev->struct_mutex);
3201 3202
	intel_update_fbc(dev);
	intel_clear_scanline_wait(dev);
3203
	mutex_unlock(&dev->struct_mutex);
3204
}
3205

3206 3207 3208 3209 3210
static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3211

3212 3213 3214 3215 3216 3217 3218 3219 3220 3221
	/* XXX: When our outputs are all unaware of DPMS modes other than off
	 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
	 */
	switch (mode) {
	case DRM_MODE_DPMS_ON:
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
		DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
		ironlake_crtc_enable(crtc);
		break;
3222

3223 3224 3225
	case DRM_MODE_DPMS_OFF:
		DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
		ironlake_crtc_disable(crtc);
3226 3227 3228 3229
		break;
	}
}

3230 3231 3232
static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
{
	if (!enable && intel_crtc->overlay) {
3233
		struct drm_device *dev = intel_crtc->base.dev;
3234
		struct drm_i915_private *dev_priv = dev->dev_private;
3235

3236
		mutex_lock(&dev->struct_mutex);
3237 3238 3239
		dev_priv->mm.interruptible = false;
		(void) intel_overlay_switch_off(intel_crtc->overlay);
		dev_priv->mm.interruptible = true;
3240
		mutex_unlock(&dev->struct_mutex);
3241 3242
	}

3243 3244 3245
	/* Let userspace switch the overlay on again. In most cases userspace
	 * has to recompute where to put it anyway.
	 */
3246 3247
}

3248
static void i9xx_crtc_enable(struct drm_crtc *crtc)
J
Jesse Barnes 已提交
3249 3250 3251 3252 3253
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
3254
	int plane = intel_crtc->plane;
J
Jesse Barnes 已提交
3255

3256 3257 3258 3259
	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
3260 3261
	intel_update_watermarks(dev);

3262
	intel_enable_pll(dev_priv, pipe);
3263
	intel_enable_pipe(dev_priv, pipe, false);
3264
	intel_enable_plane(dev_priv, plane, pipe);
J
Jesse Barnes 已提交
3265

3266
	intel_crtc_load_lut(crtc);
C
Chris Wilson 已提交
3267
	intel_update_fbc(dev);
J
Jesse Barnes 已提交
3268

3269 3270
	/* Give the overlay scaler a chance to enable if it's on this pipe */
	intel_crtc_dpms_overlay(intel_crtc, true);
3271
	intel_crtc_update_cursor(crtc, true);
3272
}
J
Jesse Barnes 已提交
3273

3274 3275 3276 3277 3278 3279 3280
static void i9xx_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3281

3282 3283 3284
	if (!intel_crtc->active)
		return;

3285
	/* Give the overlay scaler a chance to disable if it's on this pipe */
3286 3287
	intel_crtc_wait_for_pending_flips(crtc);
	drm_vblank_off(dev, pipe);
3288
	intel_crtc_dpms_overlay(intel_crtc, false);
3289
	intel_crtc_update_cursor(crtc, false);
3290

3291 3292
	if (dev_priv->cfb_plane == plane)
		intel_disable_fbc(dev);
J
Jesse Barnes 已提交
3293

3294 3295
	intel_disable_plane(dev_priv, plane, pipe);
	intel_disable_pipe(dev_priv, pipe);
3296
	intel_disable_pll(dev_priv, pipe);
3297

3298
	intel_crtc->active = false;
3299 3300 3301
	intel_update_fbc(dev);
	intel_update_watermarks(dev);
	intel_clear_scanline_wait(dev);
3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316
}

static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	/* XXX: When our outputs are all unaware of DPMS modes other than off
	 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
	 */
	switch (mode) {
	case DRM_MODE_DPMS_ON:
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
		i9xx_crtc_enable(crtc);
		break;
	case DRM_MODE_DPMS_OFF:
		i9xx_crtc_disable(crtc);
J
Jesse Barnes 已提交
3317 3318
		break;
	}
3319 3320 3321 3322 3323 3324 3325 3326
}

/**
 * Sets the power management mode of the pipe and plane.
 */
static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct drm_device *dev = crtc->dev;
3327
	struct drm_i915_private *dev_priv = dev->dev_private;
3328 3329 3330 3331 3332
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool enabled;

C
Chris Wilson 已提交
3333 3334 3335
	if (intel_crtc->dpms_mode == mode)
		return;

3336
	intel_crtc->dpms_mode = mode;
3337

3338
	dev_priv->display.dpms(crtc, mode);
J
Jesse Barnes 已提交
3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358

	if (!dev->primary->master)
		return;

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
		return;

	enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;

	switch (pipe) {
	case 0:
		master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	case 1:
		master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	default:
3359
		DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
J
Jesse Barnes 已提交
3360 3361 3362 3363
		break;
	}
}

3364 3365 3366 3367 3368 3369
static void intel_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
	struct drm_device *dev = crtc->dev;

	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3370 3371
	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3372 3373 3374

	if (crtc->fb) {
		mutex_lock(&dev->struct_mutex);
3375
		intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3376 3377 3378 3379
		mutex_unlock(&dev->struct_mutex);
	}
}

3380 3381 3382 3383 3384 3385 3386 3387 3388
/* Prepare for a mode set.
 *
 * Note we could be a lot smarter here.  We need to figure out which outputs
 * will be enabled, which disabled (in short, how the config will changes)
 * and perform the minimum necessary steps to accomplish that, e.g. updating
 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
 * panel fitting is in the proper state, etc.
 */
static void i9xx_crtc_prepare(struct drm_crtc *crtc)
J
Jesse Barnes 已提交
3389
{
3390
	i9xx_crtc_disable(crtc);
J
Jesse Barnes 已提交
3391 3392
}

3393
static void i9xx_crtc_commit(struct drm_crtc *crtc)
J
Jesse Barnes 已提交
3394
{
3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405
	i9xx_crtc_enable(crtc);
}

static void ironlake_crtc_prepare(struct drm_crtc *crtc)
{
	ironlake_crtc_disable(crtc);
}

static void ironlake_crtc_commit(struct drm_crtc *crtc)
{
	ironlake_crtc_enable(crtc);
J
Jesse Barnes 已提交
3406 3407
}

3408
void intel_encoder_prepare(struct drm_encoder *encoder)
J
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3409 3410 3411 3412 3413 3414
{
	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
	/* lvds has its own version of prepare see intel_lvds_prepare */
	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
}

3415
void intel_encoder_commit(struct drm_encoder *encoder)
J
Jesse Barnes 已提交
3416 3417
{
	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3418 3419 3420 3421
	struct drm_device *dev = encoder->dev;
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
	struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);

J
Jesse Barnes 已提交
3422 3423
	/* lvds has its own version of commit see intel_lvds_commit */
	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3424 3425 3426

	if (HAS_PCH_CPT(dev))
		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
J
Jesse Barnes 已提交
3427 3428
}

C
Chris Wilson 已提交
3429 3430
void intel_encoder_destroy(struct drm_encoder *encoder)
{
3431
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
C
Chris Wilson 已提交
3432 3433 3434 3435 3436

	drm_encoder_cleanup(encoder);
	kfree(intel_encoder);
}

J
Jesse Barnes 已提交
3437 3438 3439 3440
static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
				  struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
3441
	struct drm_device *dev = crtc->dev;
3442

3443
	if (HAS_PCH_SPLIT(dev)) {
3444
		/* FDI link clock is fixed at 2.7G */
J
Jesse Barnes 已提交
3445 3446
		if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
			return false;
3447
	}
3448

3449 3450
	/* All interlaced capable intel hw wants timings in frames. */
	drm_mode_set_crtcinfo(adjusted_mode, 0);
3451

J
Jesse Barnes 已提交
3452 3453 3454
	return true;
}

3455 3456 3457 3458
static int i945_get_display_clock_speed(struct drm_device *dev)
{
	return 400000;
}
J
Jesse Barnes 已提交
3459

3460
static int i915_get_display_clock_speed(struct drm_device *dev)
J
Jesse Barnes 已提交
3461
{
3462 3463
	return 333000;
}
J
Jesse Barnes 已提交
3464

3465 3466 3467 3468
static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
{
	return 200000;
}
J
Jesse Barnes 已提交
3469

3470 3471 3472
static int i915gm_get_display_clock_speed(struct drm_device *dev)
{
	u16 gcfgc = 0;
J
Jesse Barnes 已提交
3473

3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);

	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		return 133000;
	else {
		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		case GC_DISPLAY_CLOCK_333_MHZ:
			return 333000;
		default:
		case GC_DISPLAY_CLOCK_190_200_MHZ:
			return 190000;
J
Jesse Barnes 已提交
3485
		}
3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506
	}
}

static int i865_get_display_clock_speed(struct drm_device *dev)
{
	return 266000;
}

static int i855_get_display_clock_speed(struct drm_device *dev)
{
	u16 hpllcc = 0;
	/* Assume that the hardware is in the high speed state.  This
	 * should be the default.
	 */
	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
	case GC_CLOCK_133_200:
	case GC_CLOCK_100_200:
		return 200000;
	case GC_CLOCK_166_250:
		return 250000;
	case GC_CLOCK_100_133:
J
Jesse Barnes 已提交
3507
		return 133000;
3508
	}
J
Jesse Barnes 已提交
3509

3510 3511 3512
	/* Shouldn't happen */
	return 0;
}
J
Jesse Barnes 已提交
3513

3514 3515 3516
static int i830_get_display_clock_speed(struct drm_device *dev)
{
	return 133000;
J
Jesse Barnes 已提交
3517 3518
}

3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536
struct fdi_m_n {
	u32        tu;
	u32        gmch_m;
	u32        gmch_n;
	u32        link_m;
	u32        link_n;
};

static void
fdi_reduce_ratio(u32 *num, u32 *den)
{
	while (*num > 0xffffff || *den > 0xffffff) {
		*num >>= 1;
		*den >>= 1;
	}
}

static void
3537 3538
ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
		     int link_clock, struct fdi_m_n *m_n)
3539 3540 3541
{
	m_n->tu = 64; /* default size */

3542 3543 3544
	/* BUG_ON(pixel_clock > INT_MAX / 36); */
	m_n->gmch_m = bits_per_pixel * pixel_clock;
	m_n->gmch_n = link_clock * nlanes * 8;
3545 3546
	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);

3547 3548
	m_n->link_m = pixel_clock;
	m_n->link_n = link_clock;
3549 3550 3551 3552
	fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
}


3553 3554 3555 3556 3557 3558 3559 3560
struct intel_watermark_params {
	unsigned long fifo_size;
	unsigned long max_wm;
	unsigned long default_wm;
	unsigned long guard_size;
	unsigned long cacheline_size;
};

3561
/* Pineview has different values for various configs */
3562
static const struct intel_watermark_params pineview_display_wm = {
3563 3564 3565 3566 3567
	PINEVIEW_DISPLAY_FIFO,
	PINEVIEW_MAX_WM,
	PINEVIEW_DFT_WM,
	PINEVIEW_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE
3568
};
3569
static const struct intel_watermark_params pineview_display_hplloff_wm = {
3570 3571 3572 3573 3574
	PINEVIEW_DISPLAY_FIFO,
	PINEVIEW_MAX_WM,
	PINEVIEW_DFT_HPLLOFF_WM,
	PINEVIEW_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE
3575
};
3576
static const struct intel_watermark_params pineview_cursor_wm = {
3577 3578 3579 3580 3581
	PINEVIEW_CURSOR_FIFO,
	PINEVIEW_CURSOR_MAX_WM,
	PINEVIEW_CURSOR_DFT_WM,
	PINEVIEW_CURSOR_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE,
3582
};
3583
static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3584 3585 3586 3587 3588
	PINEVIEW_CURSOR_FIFO,
	PINEVIEW_CURSOR_MAX_WM,
	PINEVIEW_CURSOR_DFT_WM,
	PINEVIEW_CURSOR_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE
3589
};
3590
static const struct intel_watermark_params g4x_wm_info = {
3591 3592 3593 3594 3595 3596
	G4X_FIFO_SIZE,
	G4X_MAX_WM,
	G4X_MAX_WM,
	2,
	G4X_FIFO_LINE_SIZE,
};
3597
static const struct intel_watermark_params g4x_cursor_wm_info = {
3598 3599 3600 3601 3602 3603
	I965_CURSOR_FIFO,
	I965_CURSOR_MAX_WM,
	I965_CURSOR_DFT_WM,
	2,
	G4X_FIFO_LINE_SIZE,
};
3604
static const struct intel_watermark_params i965_cursor_wm_info = {
3605 3606 3607 3608 3609 3610
	I965_CURSOR_FIFO,
	I965_CURSOR_MAX_WM,
	I965_CURSOR_DFT_WM,
	2,
	I915_FIFO_LINE_SIZE,
};
3611
static const struct intel_watermark_params i945_wm_info = {
3612
	I945_FIFO_SIZE,
3613 3614
	I915_MAX_WM,
	1,
3615 3616
	2,
	I915_FIFO_LINE_SIZE
3617
};
3618
static const struct intel_watermark_params i915_wm_info = {
3619
	I915_FIFO_SIZE,
3620 3621
	I915_MAX_WM,
	1,
3622
	2,
3623 3624
	I915_FIFO_LINE_SIZE
};
3625
static const struct intel_watermark_params i855_wm_info = {
3626 3627 3628
	I855GM_FIFO_SIZE,
	I915_MAX_WM,
	1,
3629
	2,
3630 3631
	I830_FIFO_LINE_SIZE
};
3632
static const struct intel_watermark_params i830_wm_info = {
3633 3634 3635
	I830_FIFO_SIZE,
	I915_MAX_WM,
	1,
3636
	2,
3637 3638 3639
	I830_FIFO_LINE_SIZE
};

3640
static const struct intel_watermark_params ironlake_display_wm_info = {
3641 3642 3643 3644 3645 3646
	ILK_DISPLAY_FIFO,
	ILK_DISPLAY_MAXWM,
	ILK_DISPLAY_DFTWM,
	2,
	ILK_FIFO_LINE_SIZE
};
3647
static const struct intel_watermark_params ironlake_cursor_wm_info = {
3648 3649 3650 3651 3652 3653
	ILK_CURSOR_FIFO,
	ILK_CURSOR_MAXWM,
	ILK_CURSOR_DFTWM,
	2,
	ILK_FIFO_LINE_SIZE
};
3654
static const struct intel_watermark_params ironlake_display_srwm_info = {
3655 3656 3657 3658 3659 3660
	ILK_DISPLAY_SR_FIFO,
	ILK_DISPLAY_MAX_SRWM,
	ILK_DISPLAY_DFT_SRWM,
	2,
	ILK_FIFO_LINE_SIZE
};
3661
static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3662 3663 3664 3665 3666 3667 3668
	ILK_CURSOR_SR_FIFO,
	ILK_CURSOR_MAX_SRWM,
	ILK_CURSOR_DFT_SRWM,
	2,
	ILK_FIFO_LINE_SIZE
};

3669
static const struct intel_watermark_params sandybridge_display_wm_info = {
3670 3671 3672 3673 3674 3675
	SNB_DISPLAY_FIFO,
	SNB_DISPLAY_MAXWM,
	SNB_DISPLAY_DFTWM,
	2,
	SNB_FIFO_LINE_SIZE
};
3676
static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3677 3678 3679 3680 3681 3682
	SNB_CURSOR_FIFO,
	SNB_CURSOR_MAXWM,
	SNB_CURSOR_DFTWM,
	2,
	SNB_FIFO_LINE_SIZE
};
3683
static const struct intel_watermark_params sandybridge_display_srwm_info = {
3684 3685 3686 3687 3688 3689
	SNB_DISPLAY_SR_FIFO,
	SNB_DISPLAY_MAX_SRWM,
	SNB_DISPLAY_DFT_SRWM,
	2,
	SNB_FIFO_LINE_SIZE
};
3690
static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3691 3692 3693 3694 3695 3696 3697 3698
	SNB_CURSOR_SR_FIFO,
	SNB_CURSOR_MAX_SRWM,
	SNB_CURSOR_DFT_SRWM,
	2,
	SNB_FIFO_LINE_SIZE
};


3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716
/**
 * intel_calculate_wm - calculate watermark level
 * @clock_in_khz: pixel clock
 * @wm: chip FIFO params
 * @pixel_size: display pixel size
 * @latency_ns: memory latency for the platform
 *
 * Calculate the watermark level (the level at which the display plane will
 * start fetching from memory again).  Each chip has a different display
 * FIFO size and allocation, so the caller needs to figure that out and pass
 * in the correct intel_watermark_params structure.
 *
 * As the pixel clock runs, the FIFO will be drained at a rate that depends
 * on the pixel size.  When it reaches the watermark level, it'll start
 * fetching FIFO line sized based chunks from memory until the FIFO fills
 * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 * will occur, and a display engine hang could result.
 */
3717
static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3718 3719
					const struct intel_watermark_params *wm,
					int fifo_size,
3720 3721 3722
					int pixel_size,
					unsigned long latency_ns)
{
3723
	long entries_required, wm_size;
3724

3725 3726 3727 3728 3729 3730 3731 3732
	/*
	 * Note: we need to make sure we don't overflow for various clock &
	 * latency values.
	 * clocks go from a few thousand to several hundred thousand.
	 * latency is usually a few thousand
	 */
	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
		1000;
3733
	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3734

3735
	DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3736

3737
	wm_size = fifo_size - (entries_required + wm->guard_size);
3738

3739
	DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3740

3741 3742
	/* Don't promote wm_size to unsigned... */
	if (wm_size > (long)wm->max_wm)
3743
		wm_size = wm->max_wm;
3744
	if (wm_size <= 0)
3745 3746 3747 3748 3749 3750
		wm_size = wm->default_wm;
	return wm_size;
}

struct cxsr_latency {
	int is_desktop;
3751
	int is_ddr3;
3752 3753 3754 3755 3756 3757 3758 3759
	unsigned long fsb_freq;
	unsigned long mem_freq;
	unsigned long display_sr;
	unsigned long display_hpll_disable;
	unsigned long cursor_sr;
	unsigned long cursor_hpll_disable;
};

3760
static const struct cxsr_latency cxsr_latency_table[] = {
3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795
	{1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
	{1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
	{1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
	{1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
	{1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */

	{1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
	{1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
	{1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
	{1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
	{1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */

	{1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
	{1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
	{1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
	{1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
	{1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */

	{0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
	{0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
	{0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
	{0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
	{0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */

	{0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
	{0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
	{0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
	{0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
	{0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */

	{0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
	{0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
	{0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
	{0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
	{0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3796 3797
};

3798 3799 3800 3801
static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
							 int is_ddr3,
							 int fsb,
							 int mem)
3802
{
3803
	const struct cxsr_latency *latency;
3804 3805 3806 3807 3808 3809 3810 3811
	int i;

	if (fsb == 0 || mem == 0)
		return NULL;

	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
		latency = &cxsr_latency_table[i];
		if (is_desktop == latency->is_desktop &&
3812
		    is_ddr3 == latency->is_ddr3 &&
3813 3814
		    fsb == latency->fsb_freq && mem == latency->mem_freq)
			return latency;
3815
	}
3816

3817
	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3818 3819

	return NULL;
3820 3821
}

3822
static void pineview_disable_cxsr(struct drm_device *dev)
3823 3824 3825 3826
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* deactivate cxsr */
3827
	I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3828 3829
}

3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843
/*
 * Latency for FIFO fetches is dependent on several factors:
 *   - memory configuration (speed, channels)
 *   - chipset
 *   - current MCH state
 * It can be fairly high in some situations, so here we assume a fairly
 * pessimal value.  It's a tradeoff between extra memory fetches (if we
 * set this value too high, the FIFO will fetch frequently to stay full)
 * and power consumption (set it too low to save power and we might see
 * FIFO underruns and display "flicker").
 *
 * A value of 5us seems to be a good balance; safe for very low end
 * platforms but not overly aggressive on lower latency configs.
 */
3844
static const int latency_ns = 5000;
3845

3846
static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3847 3848 3849 3850 3851
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

3852 3853 3854
	size = dsparb & 0x7f;
	if (plane)
		size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3855

3856
	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3857
		      plane ? "B" : "A", size);
3858 3859 3860

	return size;
}
3861

3862 3863 3864 3865 3866 3867
static int i85x_get_fifo_size(struct drm_device *dev, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

3868 3869 3870
	size = dsparb & 0x1ff;
	if (plane)
		size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3871
	size >>= 1; /* Convert to cachelines */
3872

3873
	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3874
		      plane ? "B" : "A", size);
3875 3876 3877

	return size;
}
3878

3879 3880 3881 3882 3883 3884 3885 3886 3887
static int i845_get_fifo_size(struct drm_device *dev, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

	size = dsparb & 0x7f;
	size >>= 2; /* Convert to cachelines */

3888
	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3889 3890
		      plane ? "B" : "A",
		      size);
3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903

	return size;
}

static int i830_get_fifo_size(struct drm_device *dev, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

	size = dsparb & 0x7f;
	size >>= 1; /* Convert to cachelines */

3904
	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3905
		      plane ? "B" : "A", size);
3906 3907 3908 3909

	return size;
}

3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925
static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
{
	struct drm_crtc *crtc, *enabled = NULL;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (crtc->enabled && crtc->fb) {
			if (enabled)
				return NULL;
			enabled = crtc;
		}
	}

	return enabled;
}

static void pineview_update_wm(struct drm_device *dev)
3926 3927
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3928
	struct drm_crtc *crtc;
3929
	const struct cxsr_latency *latency;
3930 3931 3932
	u32 reg;
	unsigned long wm;

3933
	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3934
					 dev_priv->fsb_freq, dev_priv->mem_freq);
3935 3936 3937 3938 3939 3940
	if (!latency) {
		DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
		pineview_disable_cxsr(dev);
		return;
	}

3941 3942 3943 3944
	crtc = single_enabled_crtc(dev);
	if (crtc) {
		int clock = crtc->mode.clock;
		int pixel_size = crtc->fb->bits_per_pixel / 8;
3945 3946

		/* Display SR */
3947 3948
		wm = intel_calculate_wm(clock, &pineview_display_wm,
					pineview_display_wm.fifo_size,
3949 3950 3951 3952 3953 3954 3955 3956
					pixel_size, latency->display_sr);
		reg = I915_READ(DSPFW1);
		reg &= ~DSPFW_SR_MASK;
		reg |= wm << DSPFW_SR_SHIFT;
		I915_WRITE(DSPFW1, reg);
		DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);

		/* cursor SR */
3957 3958
		wm = intel_calculate_wm(clock, &pineview_cursor_wm,
					pineview_display_wm.fifo_size,
3959 3960 3961 3962 3963 3964 3965
					pixel_size, latency->cursor_sr);
		reg = I915_READ(DSPFW3);
		reg &= ~DSPFW_CURSOR_SR_MASK;
		reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
		I915_WRITE(DSPFW3, reg);

		/* Display HPLL off SR */
3966 3967
		wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
					pineview_display_hplloff_wm.fifo_size,
3968 3969 3970 3971 3972 3973 3974
					pixel_size, latency->display_hpll_disable);
		reg = I915_READ(DSPFW3);
		reg &= ~DSPFW_HPLL_SR_MASK;
		reg |= wm & DSPFW_HPLL_SR_MASK;
		I915_WRITE(DSPFW3, reg);

		/* cursor HPLL off SR */
3975 3976
		wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
					pineview_display_hplloff_wm.fifo_size,
3977 3978 3979 3980 3981 3982 3983 3984
					pixel_size, latency->cursor_hpll_disable);
		reg = I915_READ(DSPFW3);
		reg &= ~DSPFW_HPLL_CURSOR_MASK;
		reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
		I915_WRITE(DSPFW3, reg);
		DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);

		/* activate cxsr */
3985 3986
		I915_WRITE(DSPFW3,
			   I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3987 3988 3989 3990 3991 3992 3993
		DRM_DEBUG_KMS("Self-refresh is enabled\n");
	} else {
		pineview_disable_cxsr(dev);
		DRM_DEBUG_KMS("Self-refresh is disabled\n");
	}
}

3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008
static bool g4x_compute_wm0(struct drm_device *dev,
			    int plane,
			    const struct intel_watermark_params *display,
			    int display_latency_ns,
			    const struct intel_watermark_params *cursor,
			    int cursor_latency_ns,
			    int *plane_wm,
			    int *cursor_wm)
{
	struct drm_crtc *crtc;
	int htotal, hdisplay, clock, pixel_size;
	int line_time_us, line_count;
	int entries, tlb_miss;

	crtc = intel_get_crtc_for_plane(dev, plane);
4009 4010 4011
	if (crtc->fb == NULL || !crtc->enabled) {
		*cursor_wm = cursor->guard_size;
		*plane_wm = display->guard_size;
4012
		return false;
4013
	}
4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055

	htotal = crtc->mode.htotal;
	hdisplay = crtc->mode.hdisplay;
	clock = crtc->mode.clock;
	pixel_size = crtc->fb->bits_per_pixel / 8;

	/* Use the small buffer method to calculate plane watermark */
	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
	tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
	if (tlb_miss > 0)
		entries += tlb_miss;
	entries = DIV_ROUND_UP(entries, display->cacheline_size);
	*plane_wm = entries + display->guard_size;
	if (*plane_wm > (int)display->max_wm)
		*plane_wm = display->max_wm;

	/* Use the large buffer method to calculate cursor watermark */
	line_time_us = ((htotal * 1000) / clock);
	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
	entries = line_count * 64 * pixel_size;
	tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
	if (tlb_miss > 0)
		entries += tlb_miss;
	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
	*cursor_wm = entries + cursor->guard_size;
	if (*cursor_wm > (int)cursor->max_wm)
		*cursor_wm = (int)cursor->max_wm;

	return true;
}

/*
 * Check the wm result.
 *
 * If any calculated watermark values is larger than the maximum value that
 * can be programmed into the associated watermark register, that watermark
 * must be disabled.
 */
static bool g4x_check_srwm(struct drm_device *dev,
			   int display_wm, int cursor_wm,
			   const struct intel_watermark_params *display,
			   const struct intel_watermark_params *cursor)
4056
{
4057 4058
	DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
		      display_wm, cursor_wm);
4059

4060
	if (display_wm > display->max_wm) {
4061
		DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4062 4063 4064
			      display_wm, display->max_wm);
		return false;
	}
4065

4066
	if (cursor_wm > cursor->max_wm) {
4067
		DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4068 4069 4070
			      cursor_wm, cursor->max_wm);
		return false;
	}
4071

4072 4073 4074 4075
	if (!(display_wm || cursor_wm)) {
		DRM_DEBUG_KMS("SR latency is 0, disabling\n");
		return false;
	}
4076

4077 4078
	return true;
}
4079

4080
static bool g4x_compute_srwm(struct drm_device *dev,
4081 4082
			     int plane,
			     int latency_ns,
4083 4084 4085 4086
			     const struct intel_watermark_params *display,
			     const struct intel_watermark_params *cursor,
			     int *display_wm, int *cursor_wm)
{
4087 4088
	struct drm_crtc *crtc;
	int hdisplay, htotal, pixel_size, clock;
4089 4090 4091 4092
	unsigned long line_time_us;
	int line_count, line_size;
	int small, large;
	int entries;
4093

4094 4095 4096 4097
	if (!latency_ns) {
		*display_wm = *cursor_wm = 0;
		return false;
	}
4098

4099 4100 4101 4102 4103 4104
	crtc = intel_get_crtc_for_plane(dev, plane);
	hdisplay = crtc->mode.hdisplay;
	htotal = crtc->mode.htotal;
	clock = crtc->mode.clock;
	pixel_size = crtc->fb->bits_per_pixel / 8;

4105 4106 4107
	line_time_us = (htotal * 1000) / clock;
	line_count = (latency_ns / line_time_us + 1000) / 1000;
	line_size = hdisplay * pixel_size;
4108

4109 4110 4111
	/* Use the minimum of the small and large buffer method for primary */
	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
	large = line_count * line_size;
4112

4113 4114
	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
	*display_wm = entries + display->guard_size;
4115

4116 4117 4118 4119
	/* calculate the self-refresh watermark for display cursor */
	entries = line_count * pixel_size * 64;
	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
	*cursor_wm = entries + cursor->guard_size;
4120

4121 4122 4123 4124
	return g4x_check_srwm(dev,
			      *display_wm, *cursor_wm,
			      display, cursor);
}
4125

Y
Yuanhan Liu 已提交
4126
#define single_plane_enabled(mask) is_power_of_2(mask)
4127 4128

static void g4x_update_wm(struct drm_device *dev)
4129 4130 4131 4132
{
	static const int sr_latency_ns = 12000;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4133 4134
	int plane_sr, cursor_sr;
	unsigned int enabled = 0;
4135 4136 4137 4138 4139

	if (g4x_compute_wm0(dev, 0,
			    &g4x_wm_info, latency_ns,
			    &g4x_cursor_wm_info, latency_ns,
			    &planea_wm, &cursora_wm))
4140
		enabled |= 1;
4141 4142 4143 4144 4145

	if (g4x_compute_wm0(dev, 1,
			    &g4x_wm_info, latency_ns,
			    &g4x_cursor_wm_info, latency_ns,
			    &planeb_wm, &cursorb_wm))
4146
		enabled |= 2;
4147 4148

	plane_sr = cursor_sr = 0;
4149 4150 4151
	if (single_plane_enabled(enabled) &&
	    g4x_compute_srwm(dev, ffs(enabled) - 1,
			     sr_latency_ns,
4152 4153 4154
			     &g4x_wm_info,
			     &g4x_cursor_wm_info,
			     &plane_sr, &cursor_sr))
4155
		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4156 4157 4158
	else
		I915_WRITE(FW_BLC_SELF,
			   I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4159

4160 4161 4162 4163
	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
		      planea_wm, cursora_wm,
		      planeb_wm, cursorb_wm,
		      plane_sr, cursor_sr);
4164

4165 4166
	I915_WRITE(DSPFW1,
		   (plane_sr << DSPFW_SR_SHIFT) |
4167
		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4168 4169 4170 4171
		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
		   planea_wm);
	I915_WRITE(DSPFW2,
		   (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4172 4173
		   (cursora_wm << DSPFW_CURSORA_SHIFT));
	/* HPLL off in SR has some issues on G4x... disable it */
4174 4175
	I915_WRITE(DSPFW3,
		   (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4176
		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4177 4178
}

4179
static void i965_update_wm(struct drm_device *dev)
4180 4181
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4182 4183
	struct drm_crtc *crtc;
	int srwm = 1;
4184
	int cursor_sr = 16;
4185 4186

	/* Calc sr entries for one plane configs */
4187 4188
	crtc = single_enabled_crtc(dev);
	if (crtc) {
4189
		/* self-refresh has much higher latency */
4190
		static const int sr_latency_ns = 12000;
4191 4192 4193 4194 4195 4196
		int clock = crtc->mode.clock;
		int htotal = crtc->mode.htotal;
		int hdisplay = crtc->mode.hdisplay;
		int pixel_size = crtc->fb->bits_per_pixel / 8;
		unsigned long line_time_us;
		int entries;
4197

4198
		line_time_us = ((htotal * 1000) / clock);
4199 4200

		/* Use ns/us then divide to preserve precision */
4201 4202 4203 4204
		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
			pixel_size * hdisplay;
		entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
		srwm = I965_FIFO_SIZE - entries;
4205 4206
		if (srwm < 0)
			srwm = 1;
4207
		srwm &= 0x1ff;
4208 4209
		DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
			      entries, srwm);
4210

4211
		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4212
			pixel_size * 64;
4213
		entries = DIV_ROUND_UP(entries,
4214
					  i965_cursor_wm_info.cacheline_size);
4215
		cursor_sr = i965_cursor_wm_info.fifo_size -
4216
			(entries + i965_cursor_wm_info.guard_size);
4217 4218 4219 4220 4221 4222 4223

		if (cursor_sr > i965_cursor_wm_info.max_wm)
			cursor_sr = i965_cursor_wm_info.max_wm;

		DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
			      "cursor %d\n", srwm, cursor_sr);

4224
		if (IS_CRESTLINE(dev))
4225
			I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4226 4227
	} else {
		/* Turn off self refresh if both pipes are enabled */
4228
		if (IS_CRESTLINE(dev))
4229 4230
			I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
				   & ~FW_BLC_SELF_EN);
4231
	}
4232

4233 4234
	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
		      srwm);
4235 4236

	/* 965 has limitations... */
4237 4238
	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
		   (8 << 16) | (8 << 8) | (8 << 0));
4239
	I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4240 4241
	/* update cursor SR watermark */
	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4242 4243
}

4244
static void i9xx_update_wm(struct drm_device *dev)
4245 4246
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4247
	const struct intel_watermark_params *wm_info;
4248 4249
	uint32_t fwater_lo;
	uint32_t fwater_hi;
4250 4251
	int cwm, srwm = 1;
	int fifo_size;
4252
	int planea_wm, planeb_wm;
4253
	struct drm_crtc *crtc, *enabled = NULL;
4254

4255
	if (IS_I945GM(dev))
4256
		wm_info = &i945_wm_info;
4257
	else if (!IS_GEN2(dev))
4258
		wm_info = &i915_wm_info;
4259
	else
4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285
		wm_info = &i855_wm_info;

	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
	crtc = intel_get_crtc_for_plane(dev, 0);
	if (crtc->enabled && crtc->fb) {
		planea_wm = intel_calculate_wm(crtc->mode.clock,
					       wm_info, fifo_size,
					       crtc->fb->bits_per_pixel / 8,
					       latency_ns);
		enabled = crtc;
	} else
		planea_wm = fifo_size - wm_info->guard_size;

	fifo_size = dev_priv->display.get_fifo_size(dev, 1);
	crtc = intel_get_crtc_for_plane(dev, 1);
	if (crtc->enabled && crtc->fb) {
		planeb_wm = intel_calculate_wm(crtc->mode.clock,
					       wm_info, fifo_size,
					       crtc->fb->bits_per_pixel / 8,
					       latency_ns);
		if (enabled == NULL)
			enabled = crtc;
		else
			enabled = NULL;
	} else
		planeb_wm = fifo_size - wm_info->guard_size;
4286

4287
	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4288 4289 4290 4291 4292 4293

	/*
	 * Overlay gets an aggressive default since video jitter is bad.
	 */
	cwm = 2;

4294 4295 4296 4297 4298 4299
	/* Play safe and disable self-refresh before adjusting watermarks. */
	if (IS_I945G(dev) || IS_I945GM(dev))
		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
	else if (IS_I915GM(dev))
		I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);

4300
	/* Calc sr entries for one plane configs */
4301
	if (HAS_FW_BLC(dev) && enabled) {
4302
		/* self-refresh has much higher latency */
4303
		static const int sr_latency_ns = 6000;
4304 4305 4306 4307 4308 4309
		int clock = enabled->mode.clock;
		int htotal = enabled->mode.htotal;
		int hdisplay = enabled->mode.hdisplay;
		int pixel_size = enabled->fb->bits_per_pixel / 8;
		unsigned long line_time_us;
		int entries;
4310

4311
		line_time_us = (htotal * 1000) / clock;
4312 4313

		/* Use ns/us then divide to preserve precision */
4314 4315 4316 4317 4318
		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
			pixel_size * hdisplay;
		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
		DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
		srwm = wm_info->fifo_size - entries;
4319 4320
		if (srwm < 0)
			srwm = 1;
4321 4322

		if (IS_I945G(dev) || IS_I945GM(dev))
4323 4324 4325
			I915_WRITE(FW_BLC_SELF,
				   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
		else if (IS_I915GM(dev))
4326
			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4327 4328
	}

4329
	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4330
		      planea_wm, planeb_wm, cwm, srwm);
4331

4332 4333 4334 4335 4336 4337
	fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
	fwater_hi = (cwm & 0x1f);

	/* Set request length to 8 cachelines per fetch */
	fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
	fwater_hi = fwater_hi | (1 << 8);
4338 4339 4340

	I915_WRITE(FW_BLC, fwater_lo);
	I915_WRITE(FW_BLC2, fwater_hi);
4341

4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352
	if (HAS_FW_BLC(dev)) {
		if (enabled) {
			if (IS_I945G(dev) || IS_I945GM(dev))
				I915_WRITE(FW_BLC_SELF,
					   FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
			else if (IS_I915GM(dev))
				I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
			DRM_DEBUG_KMS("memory self refresh enabled\n");
		} else
			DRM_DEBUG_KMS("memory self refresh disabled\n");
	}
4353 4354
}

4355
static void i830_update_wm(struct drm_device *dev)
4356 4357
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4358 4359
	struct drm_crtc *crtc;
	uint32_t fwater_lo;
4360
	int planea_wm;
4361

4362 4363 4364
	crtc = single_enabled_crtc(dev);
	if (crtc == NULL)
		return;
4365

4366 4367 4368 4369 4370
	planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
				       dev_priv->display.get_fifo_size(dev, 0),
				       crtc->fb->bits_per_pixel / 8,
				       latency_ns);
	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4371 4372
	fwater_lo |= (3<<8) | planea_wm;

4373
	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4374 4375 4376 4377

	I915_WRITE(FW_BLC, fwater_lo);
}

4378
#define ILK_LP0_PLANE_LATENCY		700
4379
#define ILK_LP0_CURSOR_LATENCY		1300
4380

4381 4382 4383 4384 4385 4386 4387
/*
 * Check the wm result.
 *
 * If any calculated watermark values is larger than the maximum value that
 * can be programmed into the associated watermark register, that watermark
 * must be disabled.
 */
4388 4389 4390 4391
static bool ironlake_check_srwm(struct drm_device *dev, int level,
				int fbc_wm, int display_wm, int cursor_wm,
				const struct intel_watermark_params *display,
				const struct intel_watermark_params *cursor)
4392 4393 4394 4395 4396 4397 4398 4399
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
		      " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);

	if (fbc_wm > SNB_FBC_MAX_SRWM) {
		DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4400
			      fbc_wm, SNB_FBC_MAX_SRWM, level);
4401 4402 4403 4404 4405 4406 4407

		/* fbc has it's own way to disable FBC WM */
		I915_WRITE(DISP_ARB_CTL,
			   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
		return false;
	}

4408
	if (display_wm > display->max_wm) {
4409
		DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4410
			      display_wm, SNB_DISPLAY_MAX_SRWM, level);
4411 4412 4413
		return false;
	}

4414
	if (cursor_wm > cursor->max_wm) {
4415
		DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4416
			      cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430
		return false;
	}

	if (!(fbc_wm || display_wm || cursor_wm)) {
		DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
		return false;
	}

	return true;
}

/*
 * Compute watermark values of WM[1-3],
 */
4431 4432
static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
				  int latency_ns,
4433 4434 4435
				  const struct intel_watermark_params *display,
				  const struct intel_watermark_params *cursor,
				  int *fbc_wm, int *display_wm, int *cursor_wm)
4436
{
4437
	struct drm_crtc *crtc;
4438
	unsigned long line_time_us;
4439
	int hdisplay, htotal, pixel_size, clock;
4440
	int line_count, line_size;
4441 4442 4443 4444 4445 4446 4447 4448
	int small, large;
	int entries;

	if (!latency_ns) {
		*fbc_wm = *display_wm = *cursor_wm = 0;
		return false;
	}

4449 4450 4451 4452 4453 4454
	crtc = intel_get_crtc_for_plane(dev, plane);
	hdisplay = crtc->mode.hdisplay;
	htotal = crtc->mode.htotal;
	clock = crtc->mode.clock;
	pixel_size = crtc->fb->bits_per_pixel / 8;

4455 4456 4457 4458 4459 4460 4461 4462
	line_time_us = (htotal * 1000) / clock;
	line_count = (latency_ns / line_time_us + 1000) / 1000;
	line_size = hdisplay * pixel_size;

	/* Use the minimum of the small and large buffer method for primary */
	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
	large = line_count * line_size;

4463 4464
	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
	*display_wm = entries + display->guard_size;
4465 4466

	/*
4467
	 * Spec says:
4468 4469 4470 4471 4472 4473
	 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
	 */
	*fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;

	/* calculate the self-refresh watermark for display cursor */
	entries = line_count * pixel_size * 64;
4474 4475
	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
	*cursor_wm = entries + cursor->guard_size;
4476

4477 4478 4479 4480 4481
	return ironlake_check_srwm(dev, level,
				   *fbc_wm, *display_wm, *cursor_wm,
				   display, cursor);
}

4482
static void ironlake_update_wm(struct drm_device *dev)
4483 4484
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4485 4486
	int fbc_wm, plane_wm, cursor_wm;
	unsigned int enabled;
4487 4488

	enabled = 0;
4489 4490 4491 4492 4493 4494
	if (g4x_compute_wm0(dev, 0,
			    &ironlake_display_wm_info,
			    ILK_LP0_PLANE_LATENCY,
			    &ironlake_cursor_wm_info,
			    ILK_LP0_CURSOR_LATENCY,
			    &plane_wm, &cursor_wm)) {
4495 4496 4497 4498 4499
		I915_WRITE(WM0_PIPEA_ILK,
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
			      " plane %d, " "cursor: %d\n",
			      plane_wm, cursor_wm);
4500
		enabled |= 1;
4501 4502
	}

4503 4504 4505 4506 4507 4508
	if (g4x_compute_wm0(dev, 1,
			    &ironlake_display_wm_info,
			    ILK_LP0_PLANE_LATENCY,
			    &ironlake_cursor_wm_info,
			    ILK_LP0_CURSOR_LATENCY,
			    &plane_wm, &cursor_wm)) {
4509 4510 4511 4512 4513
		I915_WRITE(WM0_PIPEB_ILK,
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
			      " plane %d, cursor: %d\n",
			      plane_wm, cursor_wm);
4514
		enabled |= 2;
4515 4516 4517 4518 4519 4520 4521 4522 4523 4524
	}

	/*
	 * Calculate and update the self-refresh watermark only when one
	 * display plane is used.
	 */
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

4525
	if (!single_plane_enabled(enabled))
4526
		return;
4527
	enabled = ffs(enabled) - 1;
4528 4529

	/* WM1 */
4530 4531
	if (!ironlake_compute_srwm(dev, 1, enabled,
				   ILK_READ_WM1_LATENCY() * 500,
4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544
				   &ironlake_display_srwm_info,
				   &ironlake_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM1_LP_ILK,
		   WM1_LP_SR_EN |
		   (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/* WM2 */
4545 4546
	if (!ironlake_compute_srwm(dev, 2, enabled,
				   ILK_READ_WM2_LATENCY() * 500,
4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562
				   &ironlake_display_srwm_info,
				   &ironlake_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM2_LP_ILK,
		   WM2_LP_EN |
		   (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/*
	 * WM3 is unsupported on ILK, probably because we don't have latency
	 * data for that power state
	 */
4563 4564
}

4565
void sandybridge_update_wm(struct drm_device *dev)
4566 4567
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4568
	int latency = SNB_READ_WM0_LATENCY() * 100;	/* In unit 0.1us */
4569
	u32 val;
4570 4571
	int fbc_wm, plane_wm, cursor_wm;
	unsigned int enabled;
4572 4573

	enabled = 0;
4574 4575 4576 4577
	if (g4x_compute_wm0(dev, 0,
			    &sandybridge_display_wm_info, latency,
			    &sandybridge_cursor_wm_info, latency,
			    &plane_wm, &cursor_wm)) {
4578 4579 4580 4581
		val = I915_READ(WM0_PIPEA_ILK);
		val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
		I915_WRITE(WM0_PIPEA_ILK, val |
			   ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4582 4583 4584
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
			      " plane %d, " "cursor: %d\n",
			      plane_wm, cursor_wm);
4585
		enabled |= 1;
4586 4587
	}

4588 4589 4590 4591
	if (g4x_compute_wm0(dev, 1,
			    &sandybridge_display_wm_info, latency,
			    &sandybridge_cursor_wm_info, latency,
			    &plane_wm, &cursor_wm)) {
4592 4593 4594 4595
		val = I915_READ(WM0_PIPEB_ILK);
		val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
		I915_WRITE(WM0_PIPEB_ILK, val |
			   ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4596 4597 4598
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
			      " plane %d, cursor: %d\n",
			      plane_wm, cursor_wm);
4599
		enabled |= 2;
4600 4601
	}

4602 4603 4604 4605 4606 4607
	/* IVB has 3 pipes */
	if (IS_IVYBRIDGE(dev) &&
	    g4x_compute_wm0(dev, 2,
			    &sandybridge_display_wm_info, latency,
			    &sandybridge_cursor_wm_info, latency,
			    &plane_wm, &cursor_wm)) {
4608 4609 4610 4611
		val = I915_READ(WM0_PIPEC_IVB);
		val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
		I915_WRITE(WM0_PIPEC_IVB, val |
			   ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4612 4613 4614 4615 4616 4617
		DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
			      " plane %d, cursor: %d\n",
			      plane_wm, cursor_wm);
		enabled |= 3;
	}

4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631
	/*
	 * Calculate and update the self-refresh watermark only when one
	 * display plane is used.
	 *
	 * SNB support 3 levels of watermark.
	 *
	 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
	 * and disabled in the descending order
	 *
	 */
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

4632 4633
	if (!single_plane_enabled(enabled) ||
	    dev_priv->sprite_scaling_enabled)
4634
		return;
4635
	enabled = ffs(enabled) - 1;
4636 4637

	/* WM1 */
4638 4639
	if (!ironlake_compute_srwm(dev, 1, enabled,
				   SNB_READ_WM1_LATENCY() * 500,
4640 4641 4642
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
4643 4644 4645 4646 4647 4648 4649 4650 4651 4652
		return;

	I915_WRITE(WM1_LP_ILK,
		   WM1_LP_SR_EN |
		   (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/* WM2 */
4653 4654
	if (!ironlake_compute_srwm(dev, 2, enabled,
				   SNB_READ_WM2_LATENCY() * 500,
4655 4656 4657
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
4658 4659 4660 4661 4662 4663 4664 4665 4666 4667
		return;

	I915_WRITE(WM2_LP_ILK,
		   WM2_LP_EN |
		   (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/* WM3 */
4668 4669
	if (!ironlake_compute_srwm(dev, 3, enabled,
				   SNB_READ_WM3_LATENCY() * 500,
4670 4671 4672
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
4673 4674 4675 4676 4677 4678 4679 4680 4681 4682
		return;

	I915_WRITE(WM3_LP_ILK,
		   WM3_LP_EN |
		   (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);
}

4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754
static bool
sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
			      uint32_t sprite_width, int pixel_size,
			      const struct intel_watermark_params *display,
			      int display_latency_ns, int *sprite_wm)
{
	struct drm_crtc *crtc;
	int clock;
	int entries, tlb_miss;

	crtc = intel_get_crtc_for_plane(dev, plane);
	if (crtc->fb == NULL || !crtc->enabled) {
		*sprite_wm = display->guard_size;
		return false;
	}

	clock = crtc->mode.clock;

	/* Use the small buffer method to calculate the sprite watermark */
	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
	tlb_miss = display->fifo_size*display->cacheline_size -
		sprite_width * 8;
	if (tlb_miss > 0)
		entries += tlb_miss;
	entries = DIV_ROUND_UP(entries, display->cacheline_size);
	*sprite_wm = entries + display->guard_size;
	if (*sprite_wm > (int)display->max_wm)
		*sprite_wm = display->max_wm;

	return true;
}

static bool
sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
				uint32_t sprite_width, int pixel_size,
				const struct intel_watermark_params *display,
				int latency_ns, int *sprite_wm)
{
	struct drm_crtc *crtc;
	unsigned long line_time_us;
	int clock;
	int line_count, line_size;
	int small, large;
	int entries;

	if (!latency_ns) {
		*sprite_wm = 0;
		return false;
	}

	crtc = intel_get_crtc_for_plane(dev, plane);
	clock = crtc->mode.clock;

	line_time_us = (sprite_width * 1000) / clock;
	line_count = (latency_ns / line_time_us + 1000) / 1000;
	line_size = sprite_width * pixel_size;

	/* Use the minimum of the small and large buffer method for primary */
	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
	large = line_count * line_size;

	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
	*sprite_wm = entries + display->guard_size;

	return *sprite_wm > 0x3ff ? false : true;
}

static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
					 uint32_t sprite_width, int pixel_size)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int latency = SNB_READ_WM0_LATENCY() * 100;	/* In unit 0.1us */
4755
	u32 val;
4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781
	int sprite_wm, reg;
	int ret;

	switch (pipe) {
	case 0:
		reg = WM0_PIPEA_ILK;
		break;
	case 1:
		reg = WM0_PIPEB_ILK;
		break;
	case 2:
		reg = WM0_PIPEC_IVB;
		break;
	default:
		return; /* bad pipe */
	}

	ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
					    &sandybridge_display_wm_info,
					    latency, &sprite_wm);
	if (!ret) {
		DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
			      pipe);
		return;
	}

4782 4783 4784
	val = I915_READ(reg);
	val &= ~WM0_PIPE_SPRITE_MASK;
	I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828
	DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);


	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
					      pixel_size,
					      &sandybridge_display_srwm_info,
					      SNB_READ_WM1_LATENCY() * 500,
					      &sprite_wm);
	if (!ret) {
		DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
			      pipe);
		return;
	}
	I915_WRITE(WM1S_LP_ILK, sprite_wm);

	/* Only IVB has two more LP watermarks for sprite */
	if (!IS_IVYBRIDGE(dev))
		return;

	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
					      pixel_size,
					      &sandybridge_display_srwm_info,
					      SNB_READ_WM2_LATENCY() * 500,
					      &sprite_wm);
	if (!ret) {
		DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
			      pipe);
		return;
	}
	I915_WRITE(WM2S_LP_IVB, sprite_wm);

	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
					      pixel_size,
					      &sandybridge_display_srwm_info,
					      SNB_READ_WM3_LATENCY() * 500,
					      &sprite_wm);
	if (!ret) {
		DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
			      pipe);
		return;
	}
	I915_WRITE(WM3S_LP_IVB, sprite_wm);
}

4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851
/**
 * intel_update_watermarks - update FIFO watermark values based on current modes
 *
 * Calculate watermark values for the various WM regs based on current mode
 * and plane configuration.
 *
 * There are several cases to deal with here:
 *   - normal (i.e. non-self-refresh)
 *   - self-refresh (SR) mode
 *   - lines are large relative to FIFO size (buffer can hold up to 2)
 *   - lines are small relative to FIFO size (buffer can hold more than 2
 *     lines), so need to account for TLB latency
 *
 *   The normal calculation is:
 *     watermark = dotclock * bytes per pixel * latency
 *   where latency is platform & configuration dependent (we assume pessimal
 *   values here).
 *
 *   The SR calculation is:
 *     watermark = (trunc(latency/line time)+1) * surface width *
 *       bytes per pixel
 *   where
 *     line time = htotal / dotclock
4852
 *     surface width = hdisplay for normal plane and 64 for cursor
4853 4854 4855 4856 4857 4858 4859
 *   and latency is assumed to be high, as above.
 *
 * The final value programmed to the register should always be rounded up,
 * and include an extra 2 entries to account for clock crossings.
 *
 * We don't use the sprite, so we can ignore that.  And on Crestline we have
 * to set the non-SR watermarks to 8.
4860
 */
4861 4862
static void intel_update_watermarks(struct drm_device *dev)
{
4863
	struct drm_i915_private *dev_priv = dev->dev_private;
4864

4865 4866
	if (dev_priv->display.update_wm)
		dev_priv->display.update_wm(dev);
4867 4868
}

4869 4870 4871 4872 4873 4874 4875 4876 4877 4878
void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
				    uint32_t sprite_width, int pixel_size)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev_priv->display.update_sprite_wm)
		dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
						   pixel_size);
}

4879 4880
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
{
4881 4882 4883
	if (i915_panel_use_ssc >= 0)
		return i915_panel_use_ssc != 0;
	return dev_priv->lvds_use_ssc
4884
		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4885 4886
}

4887 4888 4889
/**
 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
 * @crtc: CRTC structure
4890
 * @mode: requested mode
4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901
 *
 * A pipe may be connected to one or more outputs.  Based on the depth of the
 * attached framebuffer, choose a good color depth to use on the pipe.
 *
 * If possible, match the pipe depth to the fb depth.  In some cases, this
 * isn't ideal, because the connected output supports a lesser or restricted
 * set of depths.  Resolve that here:
 *    LVDS typically supports only 6bpc, so clamp down in that case
 *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
 *    Displays may support a restricted set as well, check EDID and clamp as
 *      appropriate.
4902
 *    DP may want to dither down to 6bpc to fit larger modes
4903 4904 4905 4906 4907 4908
 *
 * RETURNS:
 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
 * true if they don't match).
 */
static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4909 4910
					 unsigned int *pipe_bpp,
					 struct drm_display_mode *mode)
4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_encoder *encoder;
	struct drm_connector *connector;
	unsigned int display_bpc = UINT_MAX, bpc;

	/* Walk the encoders & connectors on this crtc, get min bpc */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

		if (encoder->crtc != crtc)
			continue;

		if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
			unsigned int lvds_bpc;

			if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
			    LVDS_A3_POWER_UP)
				lvds_bpc = 8;
			else
				lvds_bpc = 6;

			if (lvds_bpc < display_bpc) {
4935
				DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4936 4937 4938 4939 4940 4941 4942 4943 4944 4945
				display_bpc = lvds_bpc;
			}
			continue;
		}

		if (intel_encoder->type == INTEL_OUTPUT_EDP) {
			/* Use VBT settings if we have an eDP panel */
			unsigned int edp_bpc = dev_priv->edp.bpp / 3;

			if (edp_bpc < display_bpc) {
4946
				DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957
				display_bpc = edp_bpc;
			}
			continue;
		}

		/* Not one of the known troublemakers, check the EDID */
		list_for_each_entry(connector, &dev->mode_config.connector_list,
				    head) {
			if (connector->encoder != encoder)
				continue;

4958 4959 4960
			/* Don't use an invalid EDID bpc value */
			if (connector->display_info.bpc &&
			    connector->display_info.bpc < display_bpc) {
4961
				DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4962 4963 4964 4965 4966 4967 4968 4969 4970 4971
				display_bpc = connector->display_info.bpc;
			}
		}

		/*
		 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
		 * through, clamp it down.  (Note: >12bpc will be caught below.)
		 */
		if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
			if (display_bpc > 8 && display_bpc < 12) {
4972
				DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4973 4974
				display_bpc = 12;
			} else {
4975
				DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4976 4977 4978 4979 4980
				display_bpc = 8;
			}
		}
	}

4981 4982 4983 4984 4985
	if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
		DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
		display_bpc = 6;
	}

4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001
	/*
	 * We could just drive the pipe at the highest bpc all the time and
	 * enable dithering as needed, but that costs bandwidth.  So choose
	 * the minimum value that expresses the full color range of the fb but
	 * also stays within the max display bpc discovered above.
	 */

	switch (crtc->fb->depth) {
	case 8:
		bpc = 8; /* since we go through a colormap */
		break;
	case 15:
	case 16:
		bpc = 6; /* min is 18bpp */
		break;
	case 24:
5002
		bpc = 8;
5003 5004
		break;
	case 30:
5005
		bpc = 10;
5006 5007
		break;
	case 48:
5008
		bpc = 12;
5009 5010 5011 5012 5013 5014 5015
		break;
	default:
		DRM_DEBUG("unsupported depth, assuming 24 bits\n");
		bpc = min((unsigned int)8, display_bpc);
		break;
	}

5016 5017
	display_bpc = min(display_bpc, bpc);

5018 5019
	DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
		      bpc, display_bpc);
5020

5021
	*pipe_bpp = display_bpc * 3;
5022 5023 5024 5025

	return display_bpc != bpc;
}

5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067
static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int refclk;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		refclk = dev_priv->lvds_ssc_freq * 1000;
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
			      refclk / 1000);
	} else if (!IS_GEN2(dev)) {
		refclk = 96000;
	} else {
		refclk = 48000;
	}

	return refclk;
}

static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
				      intel_clock_t *clock)
{
	/* SDVO TV has fixed PLL values depend on its clock range,
	   this mirrors vbios setting. */
	if (adjusted_mode->clock >= 100000
	    && adjusted_mode->clock < 140500) {
		clock->p1 = 2;
		clock->p2 = 10;
		clock->n = 3;
		clock->m1 = 16;
		clock->m2 = 8;
	} else if (adjusted_mode->clock >= 140500
		   && adjusted_mode->clock <= 200000) {
		clock->p1 = 1;
		clock->p2 = 10;
		clock->n = 6;
		clock->m1 = 12;
		clock->m2 = 8;
	}
}

5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101
static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
				     intel_clock_t *clock,
				     intel_clock_t *reduced_clock)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 fp, fp2 = 0;

	if (IS_PINEVIEW(dev)) {
		fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
		if (reduced_clock)
			fp2 = (1 << reduced_clock->n) << 16 |
				reduced_clock->m1 << 8 | reduced_clock->m2;
	} else {
		fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
		if (reduced_clock)
			fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
				reduced_clock->m2;
	}

	I915_WRITE(FP0(pipe), fp);

	intel_crtc->lowfreq_avail = false;
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
	    reduced_clock && i915_powersave) {
		I915_WRITE(FP1(pipe), fp2);
		intel_crtc->lowfreq_avail = true;
	} else {
		I915_WRITE(FP1(pipe), fp);
	}
}

5102 5103 5104 5105 5106
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
			      struct drm_display_mode *mode,
			      struct drm_display_mode *adjusted_mode,
			      int x, int y,
			      struct drm_framebuffer *old_fb)
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5107 5108 5109 5110 5111
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
5112
	int plane = intel_crtc->plane;
5113
	int refclk, num_connectors = 0;
5114
	intel_clock_t clock, reduced_clock;
5115
	u32 dpll, dspcntr, pipeconf, vsyncshift;
5116
	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5117
	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
J
Jesse Barnes 已提交
5118
	struct drm_mode_config *mode_config = &dev->mode_config;
5119
	struct intel_encoder *encoder;
5120
	const intel_limit_t *limit;
5121
	int ret;
5122
	u32 temp;
5123
	u32 lvds_sync = 0;
J
Jesse Barnes 已提交
5124

5125 5126
	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		if (encoder->base.crtc != crtc)
J
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5127 5128
			continue;

5129
		switch (encoder->type) {
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5130 5131 5132 5133
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_SDVO:
5134
		case INTEL_OUTPUT_HDMI:
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5135
			is_sdvo = true;
5136
			if (encoder->needs_tv_clock)
5137
				is_tv = true;
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5138 5139 5140 5141 5142 5143 5144 5145 5146 5147
			break;
		case INTEL_OUTPUT_DVO:
			is_dvo = true;
			break;
		case INTEL_OUTPUT_TVOUT:
			is_tv = true;
			break;
		case INTEL_OUTPUT_ANALOG:
			is_crt = true;
			break;
5148 5149 5150
		case INTEL_OUTPUT_DISPLAYPORT:
			is_dp = true;
			break;
J
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5151
		}
5152

5153
		num_connectors++;
J
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5154 5155
	}

5156
	refclk = i9xx_get_refclk(crtc, num_connectors);
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5157

5158 5159 5160 5161 5162
	/*
	 * Returns a set of divisors for the desired target clock with the given
	 * refclk, or FALSE.  The returned values represent the clock equation:
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
	 */
5163
	limit = intel_limit(crtc, refclk);
5164 5165
	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
			     &clock);
J
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5166 5167
	if (!ok) {
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
5168
		return -EINVAL;
J
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5169 5170
	}

5171
	/* Ensure that the cursor is valid for the new mode before changing... */
5172
	intel_crtc_update_cursor(crtc, true);
5173

5174
	if (is_lvds && dev_priv->lvds_downclock_avail) {
5175 5176 5177 5178 5179 5180
		/*
		 * Ensure we match the reduced clock's P to the target clock.
		 * If the clocks don't match, we can't switch the display clock
		 * by using the FP0/FP1. In such case we will disable the LVDS
		 * downclock feature.
		*/
5181
		has_reduced_clock = limit->find_pll(limit, crtc,
5182 5183
						    dev_priv->lvds_downclock,
						    refclk,
5184
						    &clock,
5185
						    &reduced_clock);
5186
	}
5187 5188 5189

	if (is_sdvo && is_tv)
		i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
Z
Zhenyu Wang 已提交
5190

5191 5192
	i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
				 &reduced_clock : NULL);
J
Jesse Barnes 已提交
5193

5194
	dpll = DPLL_VGA_MODE_DIS;
5195

5196
	if (!IS_GEN2(dev)) {
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5197 5198 5199 5200 5201
		if (is_lvds)
			dpll |= DPLLB_MODE_LVDS;
		else
			dpll |= DPLLB_MODE_DAC_SERIAL;
		if (is_sdvo) {
5202 5203 5204 5205 5206
			int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
			if (pixel_multiplier > 1) {
				if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
					dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
			}
J
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5207 5208
			dpll |= DPLL_DVO_HIGH_SPEED;
		}
5209
		if (is_dp)
5210
			dpll |= DPLL_DVO_HIGH_SPEED;
J
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5211 5212

		/* compute bitmask from p1 value */
5213 5214
		if (IS_PINEVIEW(dev))
			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5215
		else {
5216
			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5217 5218
			if (IS_G4X(dev) && has_reduced_clock)
				dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5219
		}
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5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233
		switch (clock.p2) {
		case 5:
			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
			break;
		case 7:
			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
			break;
		case 10:
			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
			break;
		case 14:
			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
			break;
		}
5234
		if (INTEL_INFO(dev)->gen >= 4)
J
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5235 5236 5237 5238 5239 5240 5241 5242 5243 5244 5245 5246 5247 5248
			dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
	} else {
		if (is_lvds) {
			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		} else {
			if (clock.p1 == 2)
				dpll |= PLL_P1_DIVIDE_BY_TWO;
			else
				dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
			if (clock.p2 == 4)
				dpll |= PLL_P2_DIVIDE_BY_4;
		}
	}

5249 5250 5251
	if (is_sdvo && is_tv)
		dpll |= PLL_REF_INPUT_TVCLKINBC;
	else if (is_tv)
J
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5252
		/* XXX: just matching BIOS for now */
5253
		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
J
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5254
		dpll |= 3;
5255
	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5256
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
J
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5257 5258 5259 5260
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

	/* setup pipeconf */
5261
	pipeconf = I915_READ(PIPECONF(pipe));
J
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5262 5263 5264 5265

	/* Set up the display plane register */
	dspcntr = DISPPLANE_GAMMA_ENABLE;

5266 5267 5268 5269
	if (pipe == 0)
		dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
	else
		dspcntr |= DISPPLANE_SEL_PIPE_B;
J
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5270

5271
	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
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5272 5273 5274 5275 5276 5277
		/* Enable pixel doubling when the dot clock is > 90% of the (display)
		 * core speed.
		 *
		 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		 * pipe == 0 check?
		 */
5278 5279
		if (mode->clock >
		    dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5280
			pipeconf |= PIPECONF_DOUBLE_WIDE;
J
Jesse Barnes 已提交
5281
		else
5282
			pipeconf &= ~PIPECONF_DOUBLE_WIDE;
J
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5283 5284
	}

5285 5286 5287 5288 5289 5290 5291 5292 5293 5294
	/* default to 8bpc */
	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
	if (is_dp) {
		if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
			pipeconf |= PIPECONF_BPP_6 |
				    PIPECONF_DITHER_EN |
				    PIPECONF_DITHER_TYPE_SP;
		}
	}

5295
	dpll |= DPLL_VCO_ENABLE;
5296

5297
	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
J
Jesse Barnes 已提交
5298 5299
	drm_mode_debug_printmodeline(mode);

5300
	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5301

5302
	POSTING_READ(DPLL(pipe));
5303
	udelay(150);
5304

J
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5305 5306 5307 5308 5309
	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
	 * This is an exception to the general rule that mode_set doesn't turn
	 * things on.
	 */
	if (is_lvds) {
5310
		temp = I915_READ(LVDS);
5311
		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5312
		if (pipe == 1) {
5313
			temp |= LVDS_PIPEB_SELECT;
5314
		} else {
5315
			temp &= ~LVDS_PIPEB_SELECT;
5316
		}
5317
		/* set the corresponsding LVDS_BORDER bit */
5318
		temp |= dev_priv->lvds_border_bits;
J
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5319 5320 5321 5322
		/* Set the B0-B3 data pairs corresponding to whether we're going to
		 * set the DPLLs for dual-channel mode or not.
		 */
		if (clock.p2 == 7)
5323
			temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
J
Jesse Barnes 已提交
5324
		else
5325
			temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
J
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5326 5327 5328 5329 5330

		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		 * appropriately here, but we need to look more thoroughly into how
		 * panels behave in the two modes.
		 */
5331 5332
		/* set the dithering flag on LVDS as needed */
		if (INTEL_INFO(dev)->gen >= 4) {
5333
			if (dev_priv->lvds_dither)
5334
				temp |= LVDS_ENABLE_DITHER;
5335
			else
5336
				temp &= ~LVDS_ENABLE_DITHER;
5337
		}
5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353
		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
			lvds_sync |= LVDS_HSYNC_POLARITY;
		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
			lvds_sync |= LVDS_VSYNC_POLARITY;
		if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
		    != lvds_sync) {
			char flags[2] = "-+";
			DRM_INFO("Changing LVDS panel from "
				 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
				 flags[!(temp & LVDS_HSYNC_POLARITY)],
				 flags[!(temp & LVDS_VSYNC_POLARITY)],
				 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
				 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
			temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
			temp |= lvds_sync;
		}
5354
		I915_WRITE(LVDS, temp);
J
Jesse Barnes 已提交
5355
	}
5356

5357
	if (is_dp) {
5358
		intel_dp_set_m_n(crtc, mode, adjusted_mode);
5359 5360
	}

5361
	I915_WRITE(DPLL(pipe), dpll);
5362

5363
	/* Wait for the clocks to stabilize. */
5364
	POSTING_READ(DPLL(pipe));
5365
	udelay(150);
5366

5367 5368 5369 5370 5371 5372 5373 5374
	if (INTEL_INFO(dev)->gen >= 4) {
		temp = 0;
		if (is_sdvo) {
			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
			if (temp > 1)
				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
			else
				temp = 0;
5375
		}
5376 5377 5378 5379 5380 5381 5382
		I915_WRITE(DPLL_MD(pipe), temp);
	} else {
		/* The pixel multiplier can only be updated once the
		 * DPLL is enabled and the clocks are stable.
		 *
		 * So write it again.
		 */
5383
		I915_WRITE(DPLL(pipe), dpll);
J
Jesse Barnes 已提交
5384 5385
	}

5386 5387
	if (HAS_PIPE_CXSR(dev)) {
		if (intel_crtc->lowfreq_avail) {
5388
			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5389
			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5390
		} else {
5391
			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5392 5393 5394 5395
			pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		}
	}

5396
	pipeconf &= ~PIPECONF_INTERLACE_MASK;
5397 5398
	if (!IS_GEN2(dev) &&
	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5399 5400 5401 5402
		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		/* the chip adds 2 halflines automatically */
		adjusted_mode->crtc_vtotal -= 1;
		adjusted_mode->crtc_vblank_end -= 1;
5403 5404 5405
		vsyncshift = adjusted_mode->crtc_hsync_start
			     - adjusted_mode->crtc_htotal/2;
	} else {
5406
		pipeconf |= PIPECONF_PROGRESSIVE;
5407 5408 5409 5410 5411
		vsyncshift = 0;
	}

	if (!IS_GEN3(dev))
		I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5412

5413 5414
	I915_WRITE(HTOTAL(pipe),
		   (adjusted_mode->crtc_hdisplay - 1) |
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5415
		   ((adjusted_mode->crtc_htotal - 1) << 16));
5416 5417
	I915_WRITE(HBLANK(pipe),
		   (adjusted_mode->crtc_hblank_start - 1) |
J
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5418
		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
5419 5420
	I915_WRITE(HSYNC(pipe),
		   (adjusted_mode->crtc_hsync_start - 1) |
J
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5421
		   ((adjusted_mode->crtc_hsync_end - 1) << 16));
5422 5423 5424

	I915_WRITE(VTOTAL(pipe),
		   (adjusted_mode->crtc_vdisplay - 1) |
J
Jesse Barnes 已提交
5425
		   ((adjusted_mode->crtc_vtotal - 1) << 16));
5426 5427
	I915_WRITE(VBLANK(pipe),
		   (adjusted_mode->crtc_vblank_start - 1) |
J
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5428
		   ((adjusted_mode->crtc_vblank_end - 1) << 16));
5429 5430
	I915_WRITE(VSYNC(pipe),
		   (adjusted_mode->crtc_vsync_start - 1) |
J
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5431
		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
5432 5433 5434

	/* pipesrc and dspsize control the size that is scaled from,
	 * which should always be the user's requested size.
J
Jesse Barnes 已提交
5435
	 */
5436 5437 5438 5439
	I915_WRITE(DSPSIZE(plane),
		   ((mode->vdisplay - 1) << 16) |
		   (mode->hdisplay - 1));
	I915_WRITE(DSPPOS(plane), 0);
5440 5441
	I915_WRITE(PIPESRC(pipe),
		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5442

5443 5444
	I915_WRITE(PIPECONF(pipe), pipeconf);
	POSTING_READ(PIPECONF(pipe));
5445
	intel_enable_pipe(dev_priv, pipe, false);
5446 5447 5448 5449 5450

	intel_wait_for_vblank(dev, pipe);

	I915_WRITE(DSPCNTR(plane), dspcntr);
	POSTING_READ(DSPCNTR(plane));
5451
	intel_enable_plane(dev_priv, plane, pipe);
5452 5453 5454 5455 5456 5457 5458 5459

	ret = intel_pipe_set_base(crtc, x, y, old_fb);

	intel_update_watermarks(dev);

	return ret;
}

5460 5461 5462 5463
/*
 * Initialize reference clocks when the driver loads
 */
void ironlake_init_pch_refclk(struct drm_device *dev)
5464 5465 5466 5467 5468 5469
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
	u32 temp;
	bool has_lvds = false;
5470 5471 5472
	bool has_cpu_edp = false;
	bool has_pch_edp = false;
	bool has_panel = false;
5473 5474
	bool has_ck505 = false;
	bool can_ssc = false;
5475 5476

	/* We need to take the global config into account */
5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490
	list_for_each_entry(encoder, &mode_config->encoder_list,
			    base.head) {
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			has_panel = true;
			has_lvds = true;
			break;
		case INTEL_OUTPUT_EDP:
			has_panel = true;
			if (intel_encoder_is_pch_edp(&encoder->base))
				has_pch_edp = true;
			else
				has_cpu_edp = true;
			break;
5491 5492 5493
		}
	}

5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504
	if (HAS_PCH_IBX(dev)) {
		has_ck505 = dev_priv->display_clock_mode;
		can_ssc = has_ck505;
	} else {
		has_ck505 = false;
		can_ssc = true;
	}

	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
		      has_panel, has_lvds, has_pch_edp, has_cpu_edp,
		      has_ck505);
5505 5506 5507 5508 5509 5510 5511 5512 5513 5514

	/* Ironlake: try to setup display ref clock before DPLL
	 * enabling. This is only under driver's control after
	 * PCH B stepping, previous chipset stepping should be
	 * ignoring this setting.
	 */
	temp = I915_READ(PCH_DREF_CONTROL);
	/* Always enable nonspread source */
	temp &= ~DREF_NONSPREAD_SOURCE_MASK;

5515 5516 5517 5518
	if (has_ck505)
		temp |= DREF_NONSPREAD_CK505_ENABLE;
	else
		temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5519

5520 5521 5522
	if (has_panel) {
		temp &= ~DREF_SSC_SOURCE_MASK;
		temp |= DREF_SSC_SOURCE_ENABLE;
5523

5524
		/* SSC must be turned on before enabling the CPU output  */
5525
		if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5526
			DRM_DEBUG_KMS("Using SSC on panel\n");
5527 5528
			temp |= DREF_SSC1_ENABLE;
		}
5529 5530 5531 5532 5533 5534

		/* Get SSC going before enabling the outputs */
		I915_WRITE(PCH_DREF_CONTROL, temp);
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);

5535 5536 5537
		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;

		/* Enable CPU source on CPU attached eDP */
5538
		if (has_cpu_edp) {
5539
			if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5540
				DRM_DEBUG_KMS("Using SSC on eDP\n");
5541
				temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5542
			}
5543 5544
			else
				temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5545 5546 5547 5548 5549 5550 5551 5552 5553 5554 5555 5556 5557 5558 5559 5560 5561 5562 5563 5564 5565 5566 5567 5568 5569
		} else
			temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;

		I915_WRITE(PCH_DREF_CONTROL, temp);
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);
	} else {
		DRM_DEBUG_KMS("Disabling SSC entirely\n");

		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;

		/* Turn off CPU output */
		temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;

		I915_WRITE(PCH_DREF_CONTROL, temp);
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);

		/* Turn off the SSC source */
		temp &= ~DREF_SSC_SOURCE_MASK;
		temp |= DREF_SSC_SOURCE_DISABLE;

		/* Turn off SSC1 */
		temp &= ~ DREF_SSC1_ENABLE;

5570 5571 5572 5573 5574 5575
		I915_WRITE(PCH_DREF_CONTROL, temp);
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);
	}
}

5576 5577 5578 5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592 5593 5594 5595 5596 5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608 5609
static int ironlake_get_refclk(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *edp_encoder = NULL;
	int num_connectors = 0;
	bool is_lvds = false;

	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		if (encoder->base.crtc != crtc)
			continue;

		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_EDP:
			edp_encoder = encoder;
			break;
		}
		num_connectors++;
	}

	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
			      dev_priv->lvds_ssc_freq);
		return dev_priv->lvds_ssc_freq * 1000;
	}

	return 120000;
}

5610 5611 5612 5613 5614
static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
				  struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode,
				  int x, int y,
				  struct drm_framebuffer *old_fb)
J
Jesse Barnes 已提交
5615 5616 5617 5618 5619
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
5620
	int plane = intel_crtc->plane;
5621
	int refclk, num_connectors = 0;
5622
	intel_clock_t clock, reduced_clock;
5623
	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5624
	bool ok, has_reduced_clock = false, is_sdvo = false;
5625
	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5626
	struct intel_encoder *has_edp_encoder = NULL;
J
Jesse Barnes 已提交
5627
	struct drm_mode_config *mode_config = &dev->mode_config;
5628
	struct intel_encoder *encoder;
5629
	const intel_limit_t *limit;
5630
	int ret;
5631
	struct fdi_m_n m_n = {0};
5632
	u32 temp;
5633
	u32 lvds_sync = 0;
5634 5635 5636
	int target_clock, pixel_multiplier, lane, link_bw, factor;
	unsigned int pipe_bpp;
	bool dither;
J
Jesse Barnes 已提交
5637

5638 5639
	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		if (encoder->base.crtc != crtc)
J
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5640 5641
			continue;

5642
		switch (encoder->type) {
J
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5643 5644 5645 5646
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_SDVO:
5647
		case INTEL_OUTPUT_HDMI:
J
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5648
			is_sdvo = true;
5649
			if (encoder->needs_tv_clock)
5650
				is_tv = true;
J
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5651 5652 5653 5654 5655 5656 5657
			break;
		case INTEL_OUTPUT_TVOUT:
			is_tv = true;
			break;
		case INTEL_OUTPUT_ANALOG:
			is_crt = true;
			break;
5658 5659 5660
		case INTEL_OUTPUT_DISPLAYPORT:
			is_dp = true;
			break;
5661
		case INTEL_OUTPUT_EDP:
5662
			has_edp_encoder = encoder;
5663
			break;
J
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5664
		}
5665

5666
		num_connectors++;
J
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5667 5668
	}

5669
	refclk = ironlake_get_refclk(crtc);
J
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5670

5671 5672 5673 5674 5675
	/*
	 * Returns a set of divisors for the desired target clock with the given
	 * refclk, or FALSE.  The returned values represent the clock equation:
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
	 */
5676
	limit = intel_limit(crtc, refclk);
5677 5678
	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
			     &clock);
J
Jesse Barnes 已提交
5679 5680
	if (!ok) {
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
5681
		return -EINVAL;
J
Jesse Barnes 已提交
5682 5683
	}

5684
	/* Ensure that the cursor is valid for the new mode before changing... */
5685
	intel_crtc_update_cursor(crtc, true);
5686

5687
	if (is_lvds && dev_priv->lvds_downclock_avail) {
5688 5689 5690 5691 5692 5693
		/*
		 * Ensure we match the reduced clock's P to the target clock.
		 * If the clocks don't match, we can't switch the display clock
		 * by using the FP0/FP1. In such case we will disable the LVDS
		 * downclock feature.
		*/
5694
		has_reduced_clock = limit->find_pll(limit, crtc,
5695 5696
						    dev_priv->lvds_downclock,
						    refclk,
5697
						    &clock,
5698
						    &reduced_clock);
5699
	}
Z
Zhenyu Wang 已提交
5700 5701 5702 5703
	/* SDVO TV has fixed PLL values depend on its clock range,
	   this mirrors vbios setting. */
	if (is_sdvo && is_tv) {
		if (adjusted_mode->clock >= 100000
5704
		    && adjusted_mode->clock < 140500) {
Z
Zhenyu Wang 已提交
5705 5706 5707 5708 5709 5710
			clock.p1 = 2;
			clock.p2 = 10;
			clock.n = 3;
			clock.m1 = 16;
			clock.m2 = 8;
		} else if (adjusted_mode->clock >= 140500
5711
			   && adjusted_mode->clock <= 200000) {
Z
Zhenyu Wang 已提交
5712 5713 5714 5715 5716 5717 5718 5719
			clock.p1 = 1;
			clock.p2 = 10;
			clock.n = 6;
			clock.m1 = 12;
			clock.m2 = 8;
		}
	}

5720
	/* FDI link */
5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733
	pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
	lane = 0;
	/* CPU eDP doesn't require FDI link, so just set DP M/N
	   according to current link config */
	if (has_edp_encoder &&
	    !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		target_clock = mode->clock;
		intel_edp_link_config(has_edp_encoder,
				      &lane, &link_bw);
	} else {
		/* [e]DP over FDI requires target mode clock
		   instead of link clock */
		if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5734
			target_clock = mode->clock;
5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746
		else
			target_clock = adjusted_mode->clock;

		/* FDI is a binary signal running at ~2.7GHz, encoding
		 * each output octet as 10 bits. The actual frequency
		 * is stored as a divider into a 100MHz clock, and the
		 * mode pixel clock is stored in units of 1KHz.
		 * Hence the bw of each lane in terms of the mode signal
		 * is:
		 */
		link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
	}
5747

5748 5749 5750
	/* determine panel color depth */
	temp = I915_READ(PIPECONF(pipe));
	temp &= ~PIPE_BPC_MASK;
5751
	dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5752 5753 5754
	switch (pipe_bpp) {
	case 18:
		temp |= PIPE_6BPC;
5755
		break;
5756 5757
	case 24:
		temp |= PIPE_8BPC;
5758
		break;
5759 5760
	case 30:
		temp |= PIPE_10BPC;
5761
		break;
5762 5763
	case 36:
		temp |= PIPE_12BPC;
5764 5765
		break;
	default:
5766 5767
		WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
			pipe_bpp);
5768 5769 5770
		temp |= PIPE_8BPC;
		pipe_bpp = 24;
		break;
5771
	}
5772

5773 5774 5775
	intel_crtc->bpp = pipe_bpp;
	I915_WRITE(PIPECONF(pipe), temp);

5776 5777 5778 5779 5780 5781
	if (!lane) {
		/*
		 * Account for spread spectrum to avoid
		 * oversubscribing the link. Max center spread
		 * is 2.5%; use 5% for safety's sake.
		 */
5782
		u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5783
		lane = bps / (link_bw * 8) + 1;
5784
	}
5785

5786 5787 5788 5789
	intel_crtc->fdi_lanes = lane;

	if (pixel_multiplier > 1)
		link_bw *= pixel_multiplier;
5790 5791
	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
			     &m_n);
5792

5793 5794 5795 5796
	fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
	if (has_reduced_clock)
		fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
			reduced_clock.m2;
J
Jesse Barnes 已提交
5797

5798
	/* Enable autotuning of the PLL clock (if permissible) */
5799 5800 5801 5802 5803 5804 5805 5806
	factor = 21;
	if (is_lvds) {
		if ((intel_panel_use_ssc(dev_priv) &&
		     dev_priv->lvds_ssc_freq == 100) ||
		    (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
			factor = 25;
	} else if (is_sdvo && is_tv)
		factor = 20;
5807

5808
	if (clock.m < factor * clock.n)
5809
		fp |= FP_CB_TUNE;
5810

5811
	dpll = 0;
5812

5813 5814 5815 5816 5817 5818 5819 5820
	if (is_lvds)
		dpll |= DPLLB_MODE_LVDS;
	else
		dpll |= DPLLB_MODE_DAC_SERIAL;
	if (is_sdvo) {
		int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		if (pixel_multiplier > 1) {
			dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
J
Jesse Barnes 已提交
5821
		}
5822 5823 5824 5825
		dpll |= DPLL_DVO_HIGH_SPEED;
	}
	if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
		dpll |= DPLL_DVO_HIGH_SPEED;
J
Jesse Barnes 已提交
5826

5827 5828 5829 5830 5831 5832 5833 5834 5835 5836 5837 5838 5839 5840 5841 5842 5843 5844
	/* compute bitmask from p1 value */
	dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
	/* also FPA1 */
	dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

	switch (clock.p2) {
	case 5:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		break;
	case 7:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
		break;
	case 10:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		break;
	case 14:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
		break;
J
Jesse Barnes 已提交
5845 5846
	}

5847 5848 5849
	if (is_sdvo && is_tv)
		dpll |= PLL_REF_INPUT_TVCLKINBC;
	else if (is_tv)
J
Jesse Barnes 已提交
5850
		/* XXX: just matching BIOS for now */
5851
		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
J
Jesse Barnes 已提交
5852
		dpll |= 3;
5853
	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5854
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
J
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5855 5856 5857 5858
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

	/* setup pipeconf */
5859
	pipeconf = I915_READ(PIPECONF(pipe));
J
Jesse Barnes 已提交
5860 5861 5862 5863

	/* Set up the display plane register */
	dspcntr = DISPPLANE_GAMMA_ENABLE;

5864
	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
J
Jesse Barnes 已提交
5865 5866
	drm_mode_debug_printmodeline(mode);

5867
	/* PCH eDP needs FDI, but CPU eDP does not */
5868 5869 5870 5871 5872 5873 5874 5875 5876 5877 5878 5879 5880 5881 5882 5883 5884 5885 5886 5887 5888 5889
	if (!intel_crtc->no_pll) {
		if (!has_edp_encoder ||
		    intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
			I915_WRITE(PCH_FP0(pipe), fp);
			I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);

			POSTING_READ(PCH_DPLL(pipe));
			udelay(150);
		}
	} else {
		if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
		    fp == I915_READ(PCH_FP0(0))) {
			intel_crtc->use_pll_a = true;
			DRM_DEBUG_KMS("using pipe a dpll\n");
		} else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
			   fp == I915_READ(PCH_FP0(1))) {
			intel_crtc->use_pll_a = false;
			DRM_DEBUG_KMS("using pipe b dpll\n");
		} else {
			DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
			return -EINVAL;
		}
J
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5890 5891 5892 5893 5894 5895 5896
	}

	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
	 * This is an exception to the general rule that mode_set doesn't turn
	 * things on.
	 */
	if (is_lvds) {
5897
		temp = I915_READ(PCH_LVDS);
5898
		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5899 5900
		if (HAS_PCH_CPT(dev)) {
			temp &= ~PORT_TRANS_SEL_MASK;
5901
			temp |= PORT_TRANS_SEL_CPT(pipe);
5902 5903 5904 5905 5906 5907
		} else {
			if (pipe == 1)
				temp |= LVDS_PIPEB_SELECT;
			else
				temp &= ~LVDS_PIPEB_SELECT;
		}
5908

5909
		/* set the corresponsding LVDS_BORDER bit */
5910
		temp |= dev_priv->lvds_border_bits;
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5911 5912 5913 5914
		/* Set the B0-B3 data pairs corresponding to whether we're going to
		 * set the DPLLs for dual-channel mode or not.
		 */
		if (clock.p2 == 7)
5915
			temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
J
Jesse Barnes 已提交
5916
		else
5917
			temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
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5918 5919 5920 5921 5922

		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		 * appropriately here, but we need to look more thoroughly into how
		 * panels behave in the two modes.
		 */
5923 5924 5925 5926 5927 5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938
		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
			lvds_sync |= LVDS_HSYNC_POLARITY;
		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
			lvds_sync |= LVDS_VSYNC_POLARITY;
		if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
		    != lvds_sync) {
			char flags[2] = "-+";
			DRM_INFO("Changing LVDS panel from "
				 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
				 flags[!(temp & LVDS_HSYNC_POLARITY)],
				 flags[!(temp & LVDS_VSYNC_POLARITY)],
				 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
				 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
			temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
			temp |= lvds_sync;
		}
5939
		I915_WRITE(PCH_LVDS, temp);
J
Jesse Barnes 已提交
5940
	}
5941

5942 5943
	pipeconf &= ~PIPECONF_DITHER_EN;
	pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5944
	if ((is_lvds && dev_priv->lvds_dither) || dither) {
5945
		pipeconf |= PIPECONF_DITHER_EN;
5946
		pipeconf |= PIPECONF_DITHER_TYPE_SP;
5947
	}
5948
	if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5949
		intel_dp_set_m_n(crtc, mode, adjusted_mode);
5950
	} else {
5951
		/* For non-DP output, clear any trans DP clock recovery setting.*/
5952 5953 5954 5955
		I915_WRITE(TRANSDATA_M1(pipe), 0);
		I915_WRITE(TRANSDATA_N1(pipe), 0);
		I915_WRITE(TRANSDPLINK_M1(pipe), 0);
		I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5956
	}
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5957

5958 5959 5960
	if (!intel_crtc->no_pll &&
	    (!has_edp_encoder ||
	     intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5961
		I915_WRITE(PCH_DPLL(pipe), dpll);
5962

5963
		/* Wait for the clocks to stabilize. */
5964
		POSTING_READ(PCH_DPLL(pipe));
5965 5966
		udelay(150);

5967 5968 5969 5970 5971
		/* The pixel multiplier can only be updated once the
		 * DPLL is enabled and the clocks are stable.
		 *
		 * So write it again.
		 */
5972
		I915_WRITE(PCH_DPLL(pipe), dpll);
J
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5973 5974
	}

5975
	intel_crtc->lowfreq_avail = false;
5976 5977 5978 5979 5980 5981 5982 5983 5984 5985 5986 5987 5988 5989
	if (!intel_crtc->no_pll) {
		if (is_lvds && has_reduced_clock && i915_powersave) {
			I915_WRITE(PCH_FP1(pipe), fp2);
			intel_crtc->lowfreq_avail = true;
			if (HAS_PIPE_CXSR(dev)) {
				DRM_DEBUG_KMS("enabling CxSR downclocking\n");
				pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
			}
		} else {
			I915_WRITE(PCH_FP1(pipe), fp);
			if (HAS_PIPE_CXSR(dev)) {
				DRM_DEBUG_KMS("disabling CxSR downclocking\n");
				pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
			}
5990 5991 5992
		}
	}

5993
	pipeconf &= ~PIPECONF_INTERLACE_MASK;
5994
	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5995
		pipeconf |= PIPECONF_INTERLACED_ILK;
5996 5997 5998
		/* the chip adds 2 halflines automatically */
		adjusted_mode->crtc_vtotal -= 1;
		adjusted_mode->crtc_vblank_end -= 1;
5999 6000 6001 6002
		I915_WRITE(VSYNCSHIFT(pipe),
			   adjusted_mode->crtc_hsync_start
			   - adjusted_mode->crtc_htotal/2);
	} else {
6003
		pipeconf |= PIPECONF_PROGRESSIVE;
6004 6005
		I915_WRITE(VSYNCSHIFT(pipe), 0);
	}
6006

6007 6008
	I915_WRITE(HTOTAL(pipe),
		   (adjusted_mode->crtc_hdisplay - 1) |
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6009
		   ((adjusted_mode->crtc_htotal - 1) << 16));
6010 6011
	I915_WRITE(HBLANK(pipe),
		   (adjusted_mode->crtc_hblank_start - 1) |
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6012
		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
6013 6014
	I915_WRITE(HSYNC(pipe),
		   (adjusted_mode->crtc_hsync_start - 1) |
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6015
		   ((adjusted_mode->crtc_hsync_end - 1) << 16));
6016 6017 6018

	I915_WRITE(VTOTAL(pipe),
		   (adjusted_mode->crtc_vdisplay - 1) |
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6019
		   ((adjusted_mode->crtc_vtotal - 1) << 16));
6020 6021
	I915_WRITE(VBLANK(pipe),
		   (adjusted_mode->crtc_vblank_start - 1) |
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6022
		   ((adjusted_mode->crtc_vblank_end - 1) << 16));
6023 6024
	I915_WRITE(VSYNC(pipe),
		   (adjusted_mode->crtc_vsync_start - 1) |
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6025
		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
6026

6027 6028
	/* pipesrc controls the size that is scaled from, which should
	 * always be the user's requested size.
J
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6029
	 */
6030 6031
	I915_WRITE(PIPESRC(pipe),
		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
6032

6033 6034 6035 6036
	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
6037

6038 6039 6040
	if (has_edp_encoder &&
	    !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6041 6042
	}

6043 6044
	I915_WRITE(PIPECONF(pipe), pipeconf);
	POSTING_READ(PIPECONF(pipe));
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6045

6046
	intel_wait_for_vblank(dev, pipe);
J
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6047

6048
	I915_WRITE(DSPCNTR(plane), dspcntr);
6049
	POSTING_READ(DSPCNTR(plane));
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6050

6051
	ret = intel_pipe_set_base(crtc, x, y, old_fb);
6052 6053 6054

	intel_update_watermarks(dev);

6055
	return ret;
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6056 6057
}

6058 6059 6060 6061 6062 6063 6064 6065
static int intel_crtc_mode_set(struct drm_crtc *crtc,
			       struct drm_display_mode *mode,
			       struct drm_display_mode *adjusted_mode,
			       int x, int y,
			       struct drm_framebuffer *old_fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
6066 6067
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
6068 6069
	int ret;

6070
	drm_vblank_pre_modeset(dev, pipe);
6071

6072 6073
	ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
					      x, y, old_fb);
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6074
	drm_vblank_post_modeset(dev, pipe);
6075

6076 6077 6078 6079
	if (ret)
		intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
	else
		intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6080

6081
	return ret;
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6082 6083
}

6084 6085 6086 6087 6088 6089 6090 6091 6092 6093 6094 6095 6096 6097 6098 6099 6100 6101 6102 6103 6104 6105 6106 6107 6108 6109 6110 6111 6112
static bool intel_eld_uptodate(struct drm_connector *connector,
			       int reg_eldv, uint32_t bits_eldv,
			       int reg_elda, uint32_t bits_elda,
			       int reg_edid)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t i;

	i = I915_READ(reg_eldv);
	i &= bits_eldv;

	if (!eld[0])
		return !i;

	if (!i)
		return false;

	i = I915_READ(reg_elda);
	i &= ~bits_elda;
	I915_WRITE(reg_elda, i);

	for (i = 0; i < eld[2]; i++)
		if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
			return false;

	return true;
}

6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128
static void g4x_write_eld(struct drm_connector *connector,
			  struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t len;
	uint32_t i;

	i = I915_READ(G4X_AUD_VID_DID);

	if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

6129 6130 6131 6132 6133 6134
	if (intel_eld_uptodate(connector,
			       G4X_AUD_CNTL_ST, eldv,
			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
			       G4X_HDMIW_HDMIEDID))
		return;

6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145 6146 6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161
	i = I915_READ(G4X_AUD_CNTL_ST);
	i &= ~(eldv | G4X_ELD_ADDR);
	len = (i >> 9) & 0x1f;		/* ELD buffer size */
	I915_WRITE(G4X_AUD_CNTL_ST, i);

	if (!eld[0])
		return;

	len = min_t(uint8_t, eld[2], len);
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));

	i = I915_READ(G4X_AUD_CNTL_ST);
	i |= eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, i);
}

static void ironlake_write_eld(struct drm_connector *connector,
				     struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t i;
	int len;
	int hdmiw_hdmiedid;
6162
	int aud_config;
6163 6164 6165
	int aud_cntl_st;
	int aud_cntrl_st2;

6166
	if (HAS_PCH_IBX(connector->dev)) {
6167
		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6168
		aud_config = IBX_AUD_CONFIG_A;
6169 6170
		aud_cntl_st = IBX_AUD_CNTL_ST_A;
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6171
	} else {
6172
		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6173
		aud_config = CPT_AUD_CONFIG_A;
6174 6175
		aud_cntl_st = CPT_AUD_CNTL_ST_A;
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6176 6177 6178 6179 6180
	}

	i = to_intel_crtc(crtc)->pipe;
	hdmiw_hdmiedid += i * 0x100;
	aud_cntl_st += i * 0x100;
6181
	aud_config += i * 0x100;
6182 6183 6184 6185 6186 6187 6188 6189

	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));

	i = I915_READ(aud_cntl_st);
	i = (i >> 29) & 0x3;		/* DIP_Port_Select, 0x1 = PortB */
	if (!i) {
		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		/* operate blindly on all ports */
6190 6191 6192
		eldv = IBX_ELD_VALIDB;
		eldv |= IBX_ELD_VALIDB << 4;
		eldv |= IBX_ELD_VALIDB << 8;
6193 6194
	} else {
		DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6195
		eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6196 6197
	}

6198 6199 6200
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */
6201 6202 6203
		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
	} else
		I915_WRITE(aud_config, 0);
6204

6205 6206 6207 6208 6209 6210
	if (intel_eld_uptodate(connector,
			       aud_cntrl_st2, eldv,
			       aud_cntl_st, IBX_ELD_ADDRESS,
			       hdmiw_hdmiedid))
		return;

6211 6212 6213 6214 6215 6216 6217 6218
	i = I915_READ(aud_cntrl_st2);
	i &= ~eldv;
	I915_WRITE(aud_cntrl_st2, i);

	if (!eld[0])
		return;

	i = I915_READ(aud_cntl_st);
6219
	i &= ~IBX_ELD_ADDRESS;
6220 6221 6222 6223 6224 6225 6226 6227 6228 6229 6230 6231 6232 6233 6234 6235 6236 6237 6238 6239 6240 6241 6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252 6253 6254 6255
	I915_WRITE(aud_cntl_st, i);

	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	i = I915_READ(aud_cntrl_st2);
	i |= eldv;
	I915_WRITE(aud_cntrl_st2, i);
}

void intel_write_eld(struct drm_encoder *encoder,
		     struct drm_display_mode *mode)
{
	struct drm_crtc *crtc = encoder->crtc;
	struct drm_connector *connector;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	connector = drm_select_eld(encoder, mode);
	if (!connector)
		return;

	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
			 connector->base.id,
			 drm_get_connector_name(connector),
			 connector->encoder->base.id,
			 drm_get_encoder_name(connector->encoder));

	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;

	if (dev_priv->display.write_eld)
		dev_priv->display.write_eld(connector, crtc);
}

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6256 6257 6258 6259 6260 6261
/** Loads the palette/gamma unit for the CRTC with the prepared values */
void intel_crtc_load_lut(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6262
	int palreg = PALETTE(intel_crtc->pipe);
J
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6263 6264 6265 6266 6267 6268
	int i;

	/* The clocks have to be on to load the palette. */
	if (!crtc->enabled)
		return;

6269
	/* use legacy palette for Ironlake */
6270
	if (HAS_PCH_SPLIT(dev))
6271
		palreg = LGC_PALETTE(intel_crtc->pipe);
6272

J
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6273 6274 6275 6276 6277 6278 6279 6280
	for (i = 0; i < 256; i++) {
		I915_WRITE(palreg + 4 * i,
			   (intel_crtc->lut_r[i] << 16) |
			   (intel_crtc->lut_g[i] << 8) |
			   intel_crtc->lut_b[i]);
	}
}

6281 6282 6283 6284 6285 6286 6287 6288 6289 6290 6291
static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	bool visible = base != 0;
	u32 cntl;

	if (intel_crtc->cursor_visible == visible)
		return;

6292
	cntl = I915_READ(_CURACNTR);
6293 6294 6295 6296
	if (visible) {
		/* On these chipsets we can only modify the base whilst
		 * the cursor is disabled.
		 */
6297
		I915_WRITE(_CURABASE, base);
6298 6299 6300 6301 6302 6303 6304 6305

		cntl &= ~(CURSOR_FORMAT_MASK);
		/* XXX width must be 64, stride 256 => 0x00 << 28 */
		cntl |= CURSOR_ENABLE |
			CURSOR_GAMMA_ENABLE |
			CURSOR_FORMAT_ARGB;
	} else
		cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6306
	I915_WRITE(_CURACNTR, cntl);
6307 6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318 6319

	intel_crtc->cursor_visible = visible;
}

static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool visible = base != 0;

	if (intel_crtc->cursor_visible != visible) {
6320
		uint32_t cntl = I915_READ(CURCNTR(pipe));
6321 6322 6323 6324 6325 6326 6327 6328
		if (base) {
			cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
			cntl |= pipe << 28; /* Connect to correct pipe */
		} else {
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
			cntl |= CURSOR_MODE_DISABLE;
		}
6329
		I915_WRITE(CURCNTR(pipe), cntl);
6330 6331 6332 6333

		intel_crtc->cursor_visible = visible;
	}
	/* and commit changes on next vblank */
6334
	I915_WRITE(CURBASE(pipe), base);
6335 6336
}

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6337 6338 6339 6340 6341 6342 6343 6344 6345 6346 6347 6348 6349 6350 6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361
static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool visible = base != 0;

	if (intel_crtc->cursor_visible != visible) {
		uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		if (base) {
			cntl &= ~CURSOR_MODE;
			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
		} else {
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
			cntl |= CURSOR_MODE_DISABLE;
		}
		I915_WRITE(CURCNTR_IVB(pipe), cntl);

		intel_crtc->cursor_visible = visible;
	}
	/* and commit changes on next vblank */
	I915_WRITE(CURBASE_IVB(pipe), base);
}

6362
/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6363 6364
static void intel_crtc_update_cursor(struct drm_crtc *crtc,
				     bool on)
6365 6366 6367 6368 6369 6370 6371
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int x = intel_crtc->cursor_x;
	int y = intel_crtc->cursor_y;
6372
	u32 base, pos;
6373 6374 6375 6376
	bool visible;

	pos = 0;

6377
	if (on && crtc->enabled && crtc->fb) {
6378 6379 6380 6381 6382 6383 6384 6385 6386 6387 6388 6389 6390 6391 6392 6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405
		base = intel_crtc->cursor_addr;
		if (x > (int) crtc->fb->width)
			base = 0;

		if (y > (int) crtc->fb->height)
			base = 0;
	} else
		base = 0;

	if (x < 0) {
		if (x + intel_crtc->cursor_width < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		x = -x;
	}
	pos |= x << CURSOR_X_SHIFT;

	if (y < 0) {
		if (y + intel_crtc->cursor_height < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		y = -y;
	}
	pos |= y << CURSOR_Y_SHIFT;

	visible = base != 0;
6406
	if (!visible && !intel_crtc->cursor_visible)
6407 6408
		return;

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6409 6410 6411 6412 6413 6414 6415 6416 6417 6418
	if (IS_IVYBRIDGE(dev)) {
		I915_WRITE(CURPOS_IVB(pipe), pos);
		ivb_update_cursor(crtc, base);
	} else {
		I915_WRITE(CURPOS(pipe), pos);
		if (IS_845G(dev) || IS_I865G(dev))
			i845_update_cursor(crtc, base);
		else
			i9xx_update_cursor(crtc, base);
	}
6419 6420 6421 6422 6423

	if (visible)
		intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
}

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Jesse Barnes 已提交
6424
static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6425
				 struct drm_file *file,
J
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6426 6427 6428 6429 6430 6431
				 uint32_t handle,
				 uint32_t width, uint32_t height)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6432
	struct drm_i915_gem_object *obj;
6433
	uint32_t addr;
6434
	int ret;
J
Jesse Barnes 已提交
6435

6436
	DRM_DEBUG_KMS("\n");
J
Jesse Barnes 已提交
6437 6438 6439

	/* if we want to turn off the cursor ignore width and height */
	if (!handle) {
6440
		DRM_DEBUG_KMS("cursor off\n");
6441
		addr = 0;
6442
		obj = NULL;
6443
		mutex_lock(&dev->struct_mutex);
6444
		goto finish;
J
Jesse Barnes 已提交
6445 6446 6447 6448 6449 6450 6451 6452
	}

	/* Currently we only support 64x64 cursors */
	if (width != 64 || height != 64) {
		DRM_ERROR("we currently only support 64x64 cursors\n");
		return -EINVAL;
	}

6453
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6454
	if (&obj->base == NULL)
J
Jesse Barnes 已提交
6455 6456
		return -ENOENT;

6457
	if (obj->base.size < width * height * 4) {
J
Jesse Barnes 已提交
6458
		DRM_ERROR("buffer is to small\n");
6459 6460
		ret = -ENOMEM;
		goto fail;
J
Jesse Barnes 已提交
6461 6462
	}

6463
	/* we only need to pin inside GTT if cursor is non-phy */
6464
	mutex_lock(&dev->struct_mutex);
6465
	if (!dev_priv->info->cursor_needs_physical) {
6466 6467 6468 6469 6470 6471
		if (obj->tiling_mode) {
			DRM_ERROR("cursor cannot be tiled\n");
			ret = -EINVAL;
			goto fail_locked;
		}

6472
		ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6473 6474
		if (ret) {
			DRM_ERROR("failed to move cursor bo into the GTT\n");
6475
			goto fail_locked;
6476 6477
		}

6478 6479
		ret = i915_gem_object_put_fence(obj);
		if (ret) {
6480
			DRM_ERROR("failed to release fence for cursor");
6481 6482 6483
			goto fail_unpin;
		}

6484
		addr = obj->gtt_offset;
6485
	} else {
6486
		int align = IS_I830(dev) ? 16 * 1024 : 256;
6487
		ret = i915_gem_attach_phys_object(dev, obj,
6488 6489
						  (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
						  align);
6490 6491
		if (ret) {
			DRM_ERROR("failed to attach phys object\n");
6492
			goto fail_locked;
6493
		}
6494
		addr = obj->phys_obj->handle->busaddr;
6495 6496
	}

6497
	if (IS_GEN2(dev))
J
Jesse Barnes 已提交
6498 6499
		I915_WRITE(CURSIZE, (height << 12) | width);

6500 6501
 finish:
	if (intel_crtc->cursor_bo) {
6502
		if (dev_priv->info->cursor_needs_physical) {
6503
			if (intel_crtc->cursor_bo != obj)
6504 6505 6506
				i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		} else
			i915_gem_object_unpin(intel_crtc->cursor_bo);
6507
		drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6508
	}
6509

6510
	mutex_unlock(&dev->struct_mutex);
6511 6512

	intel_crtc->cursor_addr = addr;
6513
	intel_crtc->cursor_bo = obj;
6514 6515 6516
	intel_crtc->cursor_width = width;
	intel_crtc->cursor_height = height;

6517
	intel_crtc_update_cursor(crtc, true);
6518

J
Jesse Barnes 已提交
6519
	return 0;
6520
fail_unpin:
6521
	i915_gem_object_unpin(obj);
6522
fail_locked:
6523
	mutex_unlock(&dev->struct_mutex);
6524
fail:
6525
	drm_gem_object_unreference_unlocked(&obj->base);
6526
	return ret;
J
Jesse Barnes 已提交
6527 6528 6529 6530 6531 6532
}

static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6533 6534
	intel_crtc->cursor_x = x;
	intel_crtc->cursor_y = y;
6535

6536
	intel_crtc_update_cursor(crtc, true);
J
Jesse Barnes 已提交
6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547 6548 6549 6550 6551

	return 0;
}

/** Sets the color ramps on behalf of RandR */
void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				 u16 blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	intel_crtc->lut_r[regno] = red >> 8;
	intel_crtc->lut_g[regno] = green >> 8;
	intel_crtc->lut_b[regno] = blue >> 8;
}

6552 6553 6554 6555 6556 6557 6558 6559 6560 6561
void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
			     u16 *blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	*red = intel_crtc->lut_r[regno] << 8;
	*green = intel_crtc->lut_g[regno] << 8;
	*blue = intel_crtc->lut_b[regno] << 8;
}

J
Jesse Barnes 已提交
6562
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
J
James Simmons 已提交
6563
				 u16 *blue, uint32_t start, uint32_t size)
J
Jesse Barnes 已提交
6564
{
J
James Simmons 已提交
6565
	int end = (start + size > 256) ? 256 : start + size, i;
J
Jesse Barnes 已提交
6566 6567
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

J
James Simmons 已提交
6568
	for (i = start; i < end; i++) {
J
Jesse Barnes 已提交
6569 6570 6571 6572 6573 6574 6575 6576 6577 6578 6579 6580 6581
		intel_crtc->lut_r[i] = red[i] >> 8;
		intel_crtc->lut_g[i] = green[i] >> 8;
		intel_crtc->lut_b[i] = blue[i] >> 8;
	}

	intel_crtc_load_lut(crtc);
}

/**
 * Get a pipe with a simple mode set on it for doing load-based monitor
 * detection.
 *
 * It will be up to the load-detect code to adjust the pipe as appropriate for
6582
 * its requirements.  The pipe will be connected to no other encoders.
J
Jesse Barnes 已提交
6583
 *
6584
 * Currently this code will only succeed if there is a pipe with no encoders
J
Jesse Barnes 已提交
6585 6586 6587 6588 6589 6590 6591 6592 6593 6594 6595 6596
 * configured for it.  In the future, it could choose to temporarily disable
 * some outputs to free up a pipe for its use.
 *
 * \return crtc, or NULL if no pipes are available.
 */

/* VESA 640x480x72Hz mode to set on the pipe */
static struct drm_display_mode load_detect_mode = {
	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
};

6597 6598
static struct drm_framebuffer *
intel_framebuffer_create(struct drm_device *dev,
6599
			 struct drm_mode_fb_cmd2 *mode_cmd,
6600 6601 6602 6603 6604 6605 6606 6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620 6621 6622 6623 6624 6625 6626 6627 6628 6629 6630 6631 6632 6633 6634 6635 6636 6637 6638 6639 6640
			 struct drm_i915_gem_object *obj)
{
	struct intel_framebuffer *intel_fb;
	int ret;

	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
	if (!intel_fb) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return ERR_PTR(-ENOMEM);
	}

	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
	if (ret) {
		drm_gem_object_unreference_unlocked(&obj->base);
		kfree(intel_fb);
		return ERR_PTR(ret);
	}

	return &intel_fb->base;
}

static u32
intel_framebuffer_pitch_for_width(int width, int bpp)
{
	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
	return ALIGN(pitch, 64);
}

static u32
intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
{
	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
}

static struct drm_framebuffer *
intel_framebuffer_create_for_mode(struct drm_device *dev,
				  struct drm_display_mode *mode,
				  int depth, int bpp)
{
	struct drm_i915_gem_object *obj;
6641
	struct drm_mode_fb_cmd2 mode_cmd;
6642 6643 6644 6645 6646 6647 6648 6649

	obj = i915_gem_alloc_object(dev,
				    intel_framebuffer_size_for_mode(mode, bpp));
	if (obj == NULL)
		return ERR_PTR(-ENOMEM);

	mode_cmd.width = mode->hdisplay;
	mode_cmd.height = mode->vdisplay;
6650 6651 6652
	mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
								bpp);
	mode_cmd.pixel_format = 0;
6653 6654 6655 6656 6657 6658 6659 6660 6661 6662 6663 6664 6665 6666 6667 6668 6669 6670 6671 6672

	return intel_framebuffer_create(dev, &mode_cmd, obj);
}

static struct drm_framebuffer *
mode_fits_in_fbdev(struct drm_device *dev,
		   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	struct drm_framebuffer *fb;

	if (dev_priv->fbdev == NULL)
		return NULL;

	obj = dev_priv->fbdev->ifb.obj;
	if (obj == NULL)
		return NULL;

	fb = &dev_priv->fbdev->ifb.base;
6673 6674
	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
							       fb->bits_per_pixel))
6675 6676
		return NULL;

6677
	if (obj->base.size < mode->vdisplay * fb->pitches[0])
6678 6679 6680 6681 6682
		return NULL;

	return fb;
}

6683 6684 6685
bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
				struct drm_connector *connector,
				struct drm_display_mode *mode,
6686
				struct intel_load_detect_pipe *old)
J
Jesse Barnes 已提交
6687 6688 6689
{
	struct intel_crtc *intel_crtc;
	struct drm_crtc *possible_crtc;
6690
	struct drm_encoder *encoder = &intel_encoder->base;
J
Jesse Barnes 已提交
6691 6692
	struct drm_crtc *crtc = NULL;
	struct drm_device *dev = encoder->dev;
6693
	struct drm_framebuffer *old_fb;
J
Jesse Barnes 已提交
6694 6695
	int i = -1;

6696 6697 6698 6699
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector),
		      encoder->base.id, drm_get_encoder_name(encoder));

J
Jesse Barnes 已提交
6700 6701
	/*
	 * Algorithm gets a little messy:
6702
	 *
J
Jesse Barnes 已提交
6703 6704
	 *   - if the connector already has an assigned crtc, use it (but make
	 *     sure it's on first)
6705
	 *
J
Jesse Barnes 已提交
6706 6707 6708 6709 6710 6711 6712
	 *   - try to find the first unused crtc that can drive this connector,
	 *     and use that if we find one
	 */

	/* See if we already have a CRTC for this connector */
	if (encoder->crtc) {
		crtc = encoder->crtc;
6713

J
Jesse Barnes 已提交
6714
		intel_crtc = to_intel_crtc(crtc);
6715 6716 6717 6718
		old->dpms_mode = intel_crtc->dpms_mode;
		old->load_detect_temp = false;

		/* Make sure the crtc and connector are running */
J
Jesse Barnes 已提交
6719
		if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6720 6721 6722
			struct drm_encoder_helper_funcs *encoder_funcs;
			struct drm_crtc_helper_funcs *crtc_funcs;

J
Jesse Barnes 已提交
6723 6724
			crtc_funcs = crtc->helper_private;
			crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6725 6726

			encoder_funcs = encoder->helper_private;
J
Jesse Barnes 已提交
6727 6728
			encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
		}
6729

6730
		return true;
J
Jesse Barnes 已提交
6731 6732 6733 6734 6735 6736 6737 6738 6739 6740 6741 6742 6743 6744 6745 6746 6747
	}

	/* Find an unused one (if possible) */
	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		i++;
		if (!(encoder->possible_crtcs & (1 << i)))
			continue;
		if (!possible_crtc->enabled) {
			crtc = possible_crtc;
			break;
		}
	}

	/*
	 * If we didn't find an unused CRTC, don't use any.
	 */
	if (!crtc) {
6748 6749
		DRM_DEBUG_KMS("no pipe available for load-detect\n");
		return false;
J
Jesse Barnes 已提交
6750 6751 6752
	}

	encoder->crtc = crtc;
6753
	connector->encoder = encoder;
J
Jesse Barnes 已提交
6754 6755

	intel_crtc = to_intel_crtc(crtc);
6756 6757
	old->dpms_mode = intel_crtc->dpms_mode;
	old->load_detect_temp = true;
6758
	old->release_fb = NULL;
J
Jesse Barnes 已提交
6759

6760 6761
	if (!mode)
		mode = &load_detect_mode;
J
Jesse Barnes 已提交
6762

6763 6764 6765 6766 6767 6768 6769 6770 6771 6772 6773 6774 6775 6776 6777 6778 6779 6780 6781 6782
	old_fb = crtc->fb;

	/* We need a framebuffer large enough to accommodate all accesses
	 * that the plane may generate whilst we perform load detection.
	 * We can not rely on the fbcon either being present (we get called
	 * during its initialisation to detect all boot displays, or it may
	 * not even exist) or that it is large enough to satisfy the
	 * requested mode.
	 */
	crtc->fb = mode_fits_in_fbdev(dev, mode);
	if (crtc->fb == NULL) {
		DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
		crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		old->release_fb = crtc->fb;
	} else
		DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
	if (IS_ERR(crtc->fb)) {
		DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
		crtc->fb = old_fb;
		return false;
J
Jesse Barnes 已提交
6783 6784
	}

6785
	if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6786
		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6787 6788 6789
		if (old->release_fb)
			old->release_fb->funcs->destroy(old->release_fb);
		crtc->fb = old_fb;
6790
		return false;
J
Jesse Barnes 已提交
6791
	}
6792

J
Jesse Barnes 已提交
6793
	/* let the connector get through one full cycle before testing */
6794
	intel_wait_for_vblank(dev, intel_crtc->pipe);
J
Jesse Barnes 已提交
6795

6796
	return true;
J
Jesse Barnes 已提交
6797 6798
}

6799
void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6800 6801
				    struct drm_connector *connector,
				    struct intel_load_detect_pipe *old)
J
Jesse Barnes 已提交
6802
{
6803
	struct drm_encoder *encoder = &intel_encoder->base;
J
Jesse Barnes 已提交
6804 6805 6806 6807 6808
	struct drm_device *dev = encoder->dev;
	struct drm_crtc *crtc = encoder->crtc;
	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;

6809 6810 6811 6812
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector),
		      encoder->base.id, drm_get_encoder_name(encoder));

6813
	if (old->load_detect_temp) {
6814
		connector->encoder = NULL;
J
Jesse Barnes 已提交
6815
		drm_helper_disable_unused_functions(dev);
6816 6817 6818 6819

		if (old->release_fb)
			old->release_fb->funcs->destroy(old->release_fb);

6820
		return;
J
Jesse Barnes 已提交
6821 6822
	}

6823
	/* Switch crtc and encoder back off if necessary */
6824 6825
	if (old->dpms_mode != DRM_MODE_DPMS_ON) {
		encoder_funcs->dpms(encoder, old->dpms_mode);
6826
		crtc_funcs->dpms(crtc, old->dpms_mode);
J
Jesse Barnes 已提交
6827 6828 6829 6830 6831 6832 6833 6834 6835
	}
}

/* Returns the clock of the currently programmed mode of the given pipe. */
static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
6836
	u32 dpll = I915_READ(DPLL(pipe));
J
Jesse Barnes 已提交
6837 6838 6839 6840
	u32 fp;
	intel_clock_t clock;

	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6841
		fp = I915_READ(FP0(pipe));
J
Jesse Barnes 已提交
6842
	else
6843
		fp = I915_READ(FP1(pipe));
J
Jesse Barnes 已提交
6844 6845

	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6846 6847 6848
	if (IS_PINEVIEW(dev)) {
		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6849 6850 6851 6852 6853
	} else {
		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
	}

6854
	if (!IS_GEN2(dev)) {
6855 6856 6857
		if (IS_PINEVIEW(dev))
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6858 6859
		else
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
J
Jesse Barnes 已提交
6860 6861 6862 6863 6864 6865 6866 6867 6868 6869 6870 6871
			       DPLL_FPA01_P1_POST_DIV_SHIFT);

		switch (dpll & DPLL_MODE_MASK) {
		case DPLLB_MODE_DAC_SERIAL:
			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
				5 : 10;
			break;
		case DPLLB_MODE_LVDS:
			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
				7 : 14;
			break;
		default:
6872
			DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
J
Jesse Barnes 已提交
6873 6874 6875 6876 6877
				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
			return 0;
		}

		/* XXX: Handle the 100Mhz refclk */
6878
		intel_clock(dev, 96000, &clock);
J
Jesse Barnes 已提交
6879 6880 6881 6882 6883 6884 6885 6886 6887 6888 6889
	} else {
		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);

		if (is_lvds) {
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
				       DPLL_FPA01_P1_POST_DIV_SHIFT);
			clock.p2 = 14;

			if ((dpll & PLL_REF_INPUT_MASK) ==
			    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
				/* XXX: might not be 66MHz */
6890
				intel_clock(dev, 66000, &clock);
J
Jesse Barnes 已提交
6891
			} else
6892
				intel_clock(dev, 48000, &clock);
J
Jesse Barnes 已提交
6893 6894 6895 6896 6897 6898 6899 6900 6901 6902 6903 6904
		} else {
			if (dpll & PLL_P1_DIVIDE_BY_TWO)
				clock.p1 = 2;
			else {
				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
			}
			if (dpll & PLL_P2_DIVIDE_BY_4)
				clock.p2 = 4;
			else
				clock.p2 = 2;

6905
			intel_clock(dev, 48000, &clock);
J
Jesse Barnes 已提交
6906 6907 6908 6909 6910 6911 6912 6913 6914 6915 6916 6917 6918 6919 6920
		}
	}

	/* XXX: It would be nice to validate the clocks, but we can't reuse
	 * i830PllIsValid() because it relies on the xf86_config connector
	 * configuration being accurate, which it isn't necessarily.
	 */

	return clock.dot;
}

/** Returns the currently programmed mode of the given pipe. */
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
					     struct drm_crtc *crtc)
{
6921
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
6922 6923 6924
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	struct drm_display_mode *mode;
6925 6926 6927 6928
	int htot = I915_READ(HTOTAL(pipe));
	int hsync = I915_READ(HSYNC(pipe));
	int vtot = I915_READ(VTOTAL(pipe));
	int vsync = I915_READ(VSYNC(pipe));
J
Jesse Barnes 已提交
6929 6930 6931 6932 6933 6934 6935 6936 6937 6938 6939 6940 6941 6942 6943 6944 6945 6946 6947 6948 6949

	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
	if (!mode)
		return NULL;

	mode->clock = intel_crtc_clock_get(dev, crtc);
	mode->hdisplay = (htot & 0xffff) + 1;
	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
	mode->hsync_start = (hsync & 0xffff) + 1;
	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
	mode->vdisplay = (vtot & 0xffff) + 1;
	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
	mode->vsync_start = (vsync & 0xffff) + 1;
	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;

	drm_mode_set_name(mode);
	drm_mode_set_crtcinfo(mode, 0);

	return mode;
}

6950 6951 6952 6953 6954 6955 6956 6957
#define GPU_IDLE_TIMEOUT 500 /* ms */

/* When this timer fires, we've been idle for awhile */
static void intel_gpu_idle_timer(unsigned long arg)
{
	struct drm_device *dev = (struct drm_device *)arg;
	drm_i915_private_t *dev_priv = dev->dev_private;

6958 6959 6960 6961 6962 6963
	if (!list_empty(&dev_priv->mm.active_list)) {
		/* Still processing requests, so just re-arm the timer. */
		mod_timer(&dev_priv->idle_timer, jiffies +
			  msecs_to_jiffies(GPU_IDLE_TIMEOUT));
		return;
	}
6964

6965
	dev_priv->busy = false;
6966
	queue_work(dev_priv->wq, &dev_priv->idle_work);
6967 6968 6969 6970 6971 6972 6973 6974 6975
}

#define CRTC_IDLE_TIMEOUT 1000 /* ms */

static void intel_crtc_idle_timer(unsigned long arg)
{
	struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
	struct drm_crtc *crtc = &intel_crtc->base;
	drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6976
	struct intel_framebuffer *intel_fb;
6977

6978 6979 6980 6981 6982 6983 6984
	intel_fb = to_intel_framebuffer(crtc->fb);
	if (intel_fb && intel_fb->obj->active) {
		/* The framebuffer is still being accessed by the GPU. */
		mod_timer(&intel_crtc->idle_timer, jiffies +
			  msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
		return;
	}
6985

6986
	intel_crtc->busy = false;
6987
	queue_work(dev_priv->wq, &dev_priv->idle_work);
6988 6989
}

6990
static void intel_increase_pllclock(struct drm_crtc *crtc)
6991 6992 6993 6994 6995
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
6996 6997
	int dpll_reg = DPLL(pipe);
	int dpll;
6998

6999
	if (HAS_PCH_SPLIT(dev))
7000 7001 7002 7003 7004
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

7005
	dpll = I915_READ(dpll_reg);
7006
	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7007
		DRM_DEBUG_DRIVER("upclocking LVDS\n");
7008 7009

		/* Unlock panel regs */
7010 7011
		I915_WRITE(PP_CONTROL,
			   I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
7012 7013 7014

		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
7015
		intel_wait_for_vblank(dev, pipe);
7016

7017 7018
		dpll = I915_READ(dpll_reg);
		if (dpll & DISPLAY_RATE_SELECT_FPA1)
7019
			DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7020 7021 7022 7023 7024 7025

		/* ...and lock them again */
		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
	}

	/* Schedule downclock */
7026 7027
	mod_timer(&intel_crtc->idle_timer, jiffies +
		  msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7028 7029 7030 7031 7032 7033 7034 7035
}

static void intel_decrease_pllclock(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
7036
	int dpll_reg = DPLL(pipe);
7037 7038
	int dpll = I915_READ(dpll_reg);

7039
	if (HAS_PCH_SPLIT(dev))
7040 7041 7042 7043 7044 7045 7046 7047 7048 7049
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

	/*
	 * Since this is called by a timer, we should never get here in
	 * the manual case.
	 */
	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7050
		DRM_DEBUG_DRIVER("downclocking LVDS\n");
7051 7052

		/* Unlock panel regs */
7053 7054
		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
			   PANEL_UNLOCK_REGS);
7055 7056 7057

		dpll |= DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
7058
		intel_wait_for_vblank(dev, pipe);
7059 7060
		dpll = I915_READ(dpll_reg);
		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7061
			DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7062 7063 7064 7065 7066 7067 7068 7069 7070 7071 7072 7073 7074 7075 7076 7077 7078 7079 7080 7081 7082 7083 7084 7085 7086 7087 7088

		/* ...and lock them again */
		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
	}

}

/**
 * intel_idle_update - adjust clocks for idleness
 * @work: work struct
 *
 * Either the GPU or display (or both) went idle.  Check the busy status
 * here and adjust the CRTC and GPU clocks as necessary.
 */
static void intel_idle_update(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    idle_work);
	struct drm_device *dev = dev_priv->dev;
	struct drm_crtc *crtc;
	struct intel_crtc *intel_crtc;

	if (!i915_powersave)
		return;

	mutex_lock(&dev->struct_mutex);

7089 7090
	i915_update_gfx_val(dev_priv);

7091 7092 7093 7094 7095 7096 7097 7098 7099 7100
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		/* Skip inactive CRTCs */
		if (!crtc->fb)
			continue;

		intel_crtc = to_intel_crtc(crtc);
		if (!intel_crtc->busy)
			intel_decrease_pllclock(crtc);
	}

7101

7102 7103 7104 7105 7106 7107 7108 7109 7110 7111 7112 7113 7114
	mutex_unlock(&dev->struct_mutex);
}

/**
 * intel_mark_busy - mark the GPU and possibly the display busy
 * @dev: drm device
 * @obj: object we're operating on
 *
 * Callers can use this function to indicate that the GPU is busy processing
 * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
 * buffer), we'll also mark the display as busy, so we know to increase its
 * clock frequency.
 */
7115
void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7116 7117 7118 7119 7120 7121
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = NULL;
	struct intel_framebuffer *intel_fb;
	struct intel_crtc *intel_crtc;

7122 7123 7124
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		return;

7125
	if (!dev_priv->busy)
7126
		dev_priv->busy = true;
7127
	else
7128 7129
		mod_timer(&dev_priv->idle_timer, jiffies +
			  msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7130 7131 7132 7133 7134 7135 7136 7137 7138 7139

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (!crtc->fb)
			continue;

		intel_crtc = to_intel_crtc(crtc);
		intel_fb = to_intel_framebuffer(crtc->fb);
		if (intel_fb->obj == obj) {
			if (!intel_crtc->busy) {
				/* Non-busy -> busy, upclock */
7140
				intel_increase_pllclock(crtc);
7141 7142 7143 7144 7145 7146 7147 7148 7149 7150
				intel_crtc->busy = true;
			} else {
				/* Busy -> busy, put off timer */
				mod_timer(&intel_crtc->idle_timer, jiffies +
					  msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
			}
		}
	}
}

J
Jesse Barnes 已提交
7151 7152 7153
static void intel_crtc_destroy(struct drm_crtc *crtc)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7154 7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166
	struct drm_device *dev = crtc->dev;
	struct intel_unpin_work *work;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (work) {
		cancel_work_sync(&work->work);
		kfree(work);
	}
J
Jesse Barnes 已提交
7167 7168

	drm_crtc_cleanup(crtc);
7169

J
Jesse Barnes 已提交
7170 7171 7172
	kfree(intel_crtc);
}

7173 7174 7175 7176 7177 7178
static void intel_unpin_work_fn(struct work_struct *__work)
{
	struct intel_unpin_work *work =
		container_of(__work, struct intel_unpin_work, work);

	mutex_lock(&work->dev->struct_mutex);
7179
	intel_unpin_fb_obj(work->old_fb_obj);
7180 7181
	drm_gem_object_unreference(&work->pending_flip_obj->base);
	drm_gem_object_unreference(&work->old_fb_obj->base);
7182

7183
	intel_update_fbc(work->dev);
7184 7185 7186 7187
	mutex_unlock(&work->dev->struct_mutex);
	kfree(work);
}

7188
static void do_intel_finish_page_flip(struct drm_device *dev,
7189
				      struct drm_crtc *crtc)
7190 7191 7192 7193
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
7194
	struct drm_i915_gem_object *obj;
7195
	struct drm_pending_vblank_event *e;
7196
	struct timeval tnow, tvbl;
7197 7198 7199 7200 7201 7202
	unsigned long flags;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

7203 7204
	do_gettimeofday(&tnow);

7205 7206 7207 7208 7209 7210 7211 7212 7213 7214 7215
	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
	if (work == NULL || !work->pending) {
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

	intel_crtc->unpin_work = NULL;

	if (work->event) {
		e = work->event;
7216
		e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7217 7218 7219 7220 7221

		/* Called before vblank count and timestamps have
		 * been updated for the vblank interval of flip
		 * completion? Need to increment vblank count and
		 * add one videorefresh duration to returned timestamp
7222 7223 7224 7225 7226 7227 7228
		 * to account for this. We assume this happened if we
		 * get called over 0.9 frame durations after the last
		 * timestamped vblank.
		 *
		 * This calculation can not be used with vrefresh rates
		 * below 5Hz (10Hz to be on the safe side) without
		 * promoting to 64 integers.
7229
		 */
7230 7231
		if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
		    9 * crtc->framedur_ns) {
7232
			e->event.sequence++;
7233 7234
			tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
					     crtc->framedur_ns);
7235 7236
		}

7237 7238
		e->event.tv_sec = tvbl.tv_sec;
		e->event.tv_usec = tvbl.tv_usec;
7239

7240 7241 7242 7243 7244
		list_add_tail(&e->base.link,
			      &e->base.file_priv->event_list);
		wake_up_interruptible(&e->base.file_priv->event_wait);
	}

7245 7246
	drm_vblank_put(dev, intel_crtc->pipe);

7247 7248
	spin_unlock_irqrestore(&dev->event_lock, flags);

7249
	obj = work->old_fb_obj;
7250

7251
	atomic_clear_mask(1 << intel_crtc->plane,
7252 7253
			  &obj->pending_flip.counter);
	if (atomic_read(&obj->pending_flip) == 0)
7254
		wake_up(&dev_priv->pending_flip_queue);
7255

7256
	schedule_work(&work->work);
7257 7258

	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7259 7260
}

7261 7262 7263 7264 7265
void intel_finish_page_flip(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];

7266
	do_intel_finish_page_flip(dev, crtc);
7267 7268 7269 7270 7271 7272 7273
}

void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];

7274
	do_intel_finish_page_flip(dev, crtc);
7275 7276
}

7277 7278 7279 7280 7281 7282 7283 7284
void intel_prepare_page_flip(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
7285
	if (intel_crtc->unpin_work) {
7286 7287
		if ((++intel_crtc->unpin_work->pending) > 1)
			DRM_ERROR("Prepared flip multiple times\n");
7288 7289 7290
	} else {
		DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
	}
7291 7292 7293
	spin_unlock_irqrestore(&dev->event_lock, flags);
}

7294 7295 7296 7297 7298 7299 7300 7301 7302 7303 7304 7305 7306 7307 7308 7309
static int intel_gen2_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	unsigned long offset;
	u32 flip_mask;
	int ret;

	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
	if (ret)
		goto out;

	/* Offset into the new buffer for cases of shared fbs between CRTCs */
7310
	offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7311 7312 7313 7314 7315 7316 7317 7318 7319 7320 7321 7322 7323 7324 7325 7326

	ret = BEGIN_LP_RING(6);
	if (ret)
		goto out;

	/* Can't queue multiple flips, so wait for the previous
	 * one to finish before executing the next.
	 */
	if (intel_crtc->plane)
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
	else
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
	OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
	OUT_RING(MI_NOOP);
	OUT_RING(MI_DISPLAY_FLIP |
		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7327
	OUT_RING(fb->pitches[0]);
7328
	OUT_RING(obj->gtt_offset + offset);
7329
	OUT_RING(0); /* aux display base address, unused */
7330 7331 7332 7333 7334 7335 7336 7337 7338 7339 7340 7341 7342 7343 7344 7345 7346 7347 7348 7349 7350
	ADVANCE_LP_RING();
out:
	return ret;
}

static int intel_gen3_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	unsigned long offset;
	u32 flip_mask;
	int ret;

	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
	if (ret)
		goto out;

	/* Offset into the new buffer for cases of shared fbs between CRTCs */
7351
	offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7352 7353 7354 7355 7356 7357 7358 7359 7360 7361 7362 7363 7364

	ret = BEGIN_LP_RING(6);
	if (ret)
		goto out;

	if (intel_crtc->plane)
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
	else
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
	OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
	OUT_RING(MI_NOOP);
	OUT_RING(MI_DISPLAY_FLIP_I915 |
		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7365
	OUT_RING(fb->pitches[0]);
7366 7367 7368 7369 7370 7371 7372 7373 7374 7375 7376 7377 7378 7379 7380 7381 7382 7383 7384 7385 7386 7387 7388 7389 7390 7391 7392 7393 7394 7395 7396 7397
	OUT_RING(obj->gtt_offset + offset);
	OUT_RING(MI_NOOP);

	ADVANCE_LP_RING();
out:
	return ret;
}

static int intel_gen4_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	uint32_t pf, pipesrc;
	int ret;

	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
	if (ret)
		goto out;

	ret = BEGIN_LP_RING(4);
	if (ret)
		goto out;

	/* i965+ uses the linear or tiled offsets from the
	 * Display Registers (which do not change across a page-flip)
	 * so we need only reprogram the base address.
	 */
	OUT_RING(MI_DISPLAY_FLIP |
		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7398
	OUT_RING(fb->pitches[0]);
7399 7400 7401 7402 7403 7404 7405 7406 7407 7408 7409 7410 7411 7412 7413 7414 7415 7416 7417 7418 7419 7420 7421 7422 7423 7424 7425 7426 7427 7428 7429 7430 7431 7432
	OUT_RING(obj->gtt_offset | obj->tiling_mode);

	/* XXX Enabling the panel-fitter across page-flip is so far
	 * untested on non-native modes, so ignore it for now.
	 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
	 */
	pf = 0;
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
	OUT_RING(pf | pipesrc);
	ADVANCE_LP_RING();
out:
	return ret;
}

static int intel_gen6_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	uint32_t pf, pipesrc;
	int ret;

	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
	if (ret)
		goto out;

	ret = BEGIN_LP_RING(4);
	if (ret)
		goto out;

	OUT_RING(MI_DISPLAY_FLIP |
		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7433
	OUT_RING(fb->pitches[0] | obj->tiling_mode);
7434 7435 7436 7437 7438 7439 7440 7441 7442 7443
	OUT_RING(obj->gtt_offset);

	pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
	OUT_RING(pf | pipesrc);
	ADVANCE_LP_RING();
out:
	return ret;
}

7444 7445 7446 7447 7448 7449 7450 7451 7452 7453 7454 7455 7456 7457 7458 7459 7460 7461 7462 7463 7464 7465 7466 7467 7468
/*
 * On gen7 we currently use the blit ring because (in early silicon at least)
 * the render ring doesn't give us interrpts for page flip completion, which
 * means clients will hang after the first flip is queued.  Fortunately the
 * blit ring generates interrupts properly, so use it instead.
 */
static int intel_gen7_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
	int ret;

	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
	if (ret)
		goto out;

	ret = intel_ring_begin(ring, 4);
	if (ret)
		goto out;

	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7469
	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7470 7471 7472 7473 7474 7475 7476
	intel_ring_emit(ring, (obj->gtt_offset));
	intel_ring_emit(ring, (MI_NOOP));
	intel_ring_advance(ring);
out:
	return ret;
}

7477 7478 7479 7480 7481 7482 7483 7484
static int intel_default_queue_flip(struct drm_device *dev,
				    struct drm_crtc *crtc,
				    struct drm_framebuffer *fb,
				    struct drm_i915_gem_object *obj)
{
	return -ENODEV;
}

7485 7486 7487 7488 7489 7490 7491
static int intel_crtc_page_flip(struct drm_crtc *crtc,
				struct drm_framebuffer *fb,
				struct drm_pending_vblank_event *event)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_framebuffer *intel_fb;
7492
	struct drm_i915_gem_object *obj;
7493 7494
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
7495
	unsigned long flags;
7496
	int ret;
7497 7498 7499 7500 7501 7502 7503 7504

	work = kzalloc(sizeof *work, GFP_KERNEL);
	if (work == NULL)
		return -ENOMEM;

	work->event = event;
	work->dev = crtc->dev;
	intel_fb = to_intel_framebuffer(crtc->fb);
7505
	work->old_fb_obj = intel_fb->obj;
7506 7507
	INIT_WORK(&work->work, intel_unpin_work_fn);

7508 7509 7510 7511
	ret = drm_vblank_get(dev, intel_crtc->pipe);
	if (ret)
		goto free_work;

7512 7513 7514 7515 7516
	/* We borrow the event spin lock for protecting unpin_work */
	spin_lock_irqsave(&dev->event_lock, flags);
	if (intel_crtc->unpin_work) {
		spin_unlock_irqrestore(&dev->event_lock, flags);
		kfree(work);
7517
		drm_vblank_put(dev, intel_crtc->pipe);
7518 7519

		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7520 7521 7522 7523 7524 7525 7526 7527
		return -EBUSY;
	}
	intel_crtc->unpin_work = work;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

7528
	mutex_lock(&dev->struct_mutex);
7529

7530
	/* Reference the objects for the scheduled work. */
7531 7532
	drm_gem_object_reference(&work->old_fb_obj->base);
	drm_gem_object_reference(&obj->base);
7533 7534

	crtc->fb = fb;
7535

7536 7537
	work->pending_flip_obj = obj;

7538 7539
	work->enable_stall_check = true;

7540 7541 7542
	/* Block clients from rendering to the new back buffer until
	 * the flip occurs and the object is no longer visible.
	 */
7543
	atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7544

7545 7546 7547
	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
	if (ret)
		goto cleanup_pending;
7548

7549
	intel_disable_fbc(dev);
7550 7551
	mutex_unlock(&dev->struct_mutex);

7552 7553
	trace_i915_flip_request(intel_crtc->plane, obj);

7554
	return 0;
7555

7556 7557
cleanup_pending:
	atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7558 7559
	drm_gem_object_unreference(&work->old_fb_obj->base);
	drm_gem_object_unreference(&obj->base);
7560 7561 7562 7563 7564 7565
	mutex_unlock(&dev->struct_mutex);

	spin_lock_irqsave(&dev->event_lock, flags);
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

7566 7567
	drm_vblank_put(dev, intel_crtc->pipe);
free_work:
7568 7569 7570
	kfree(work);

	return ret;
7571 7572
}

7573 7574 7575 7576 7577 7578 7579 7580 7581 7582 7583 7584 7585 7586 7587 7588 7589 7590 7591 7592 7593 7594 7595 7596 7597 7598 7599 7600 7601 7602 7603 7604
static void intel_sanitize_modesetting(struct drm_device *dev,
				       int pipe, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 reg, val;

	if (HAS_PCH_SPLIT(dev))
		return;

	/* Who knows what state these registers were left in by the BIOS or
	 * grub?
	 *
	 * If we leave the registers in a conflicting state (e.g. with the
	 * display plane reading from the other pipe than the one we intend
	 * to use) then when we attempt to teardown the active mode, we will
	 * not disable the pipes and planes in the correct order -- leaving
	 * a plane reading from a disabled pipe and possibly leading to
	 * undefined behaviour.
	 */

	reg = DSPCNTR(plane);
	val = I915_READ(reg);

	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		return;
	if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
		return;

	/* This display plane is active and attached to the other CPU pipe. */
	pipe = !pipe;

	/* Disable the plane and wait for it to stop reading from the pipe. */
7605 7606
	intel_disable_plane(dev_priv, plane, pipe);
	intel_disable_pipe(dev_priv, pipe);
7607
}
J
Jesse Barnes 已提交
7608

7609 7610 7611 7612 7613 7614 7615 7616 7617 7618 7619 7620 7621 7622 7623 7624 7625 7626 7627 7628 7629 7630 7631 7632 7633 7634 7635 7636 7637 7638 7639 7640 7641 7642 7643 7644
static void intel_crtc_reset(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	/* Reset flags back to the 'unknown' status so that they
	 * will be correctly set on the initial modeset.
	 */
	intel_crtc->dpms_mode = -1;

	/* We need to fix up any BIOS configuration that conflicts with
	 * our expectations.
	 */
	intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
}

static struct drm_crtc_helper_funcs intel_helper_funcs = {
	.dpms = intel_crtc_dpms,
	.mode_fixup = intel_crtc_mode_fixup,
	.mode_set = intel_crtc_mode_set,
	.mode_set_base = intel_pipe_set_base,
	.mode_set_base_atomic = intel_pipe_set_base_atomic,
	.load_lut = intel_crtc_load_lut,
	.disable = intel_crtc_disable,
};

static const struct drm_crtc_funcs intel_crtc_funcs = {
	.reset = intel_crtc_reset,
	.cursor_set = intel_crtc_cursor_set,
	.cursor_move = intel_crtc_cursor_move,
	.gamma_set = intel_crtc_gamma_set,
	.set_config = drm_crtc_helper_set_config,
	.destroy = intel_crtc_destroy,
	.page_flip = intel_crtc_page_flip,
};

7645
static void intel_crtc_init(struct drm_device *dev, int pipe)
J
Jesse Barnes 已提交
7646
{
J
Jesse Barnes 已提交
7647
	drm_i915_private_t *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
7648 7649 7650 7651 7652 7653 7654 7655 7656 7657 7658 7659 7660 7661 7662 7663
	struct intel_crtc *intel_crtc;
	int i;

	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
	if (intel_crtc == NULL)
		return;

	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);

	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
	for (i = 0; i < 256; i++) {
		intel_crtc->lut_r[i] = i;
		intel_crtc->lut_g[i] = i;
		intel_crtc->lut_b[i] = i;
	}

7664 7665 7666
	/* Swap pipes & planes for FBC on pre-965 */
	intel_crtc->pipe = pipe;
	intel_crtc->plane = pipe;
7667
	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7668
		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7669
		intel_crtc->plane = !pipe;
7670 7671
	}

J
Jesse Barnes 已提交
7672 7673 7674 7675 7676
	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;

C
Chris Wilson 已提交
7677
	intel_crtc_reset(&intel_crtc->base);
7678
	intel_crtc->active = true; /* force the pipe off on setup_init_config */
7679
	intel_crtc->bpp = 24; /* default for pre-Ironlake */
7680 7681

	if (HAS_PCH_SPLIT(dev)) {
7682 7683
		if (pipe == 2 && IS_IVYBRIDGE(dev))
			intel_crtc->no_pll = true;
7684 7685 7686 7687 7688 7689 7690
		intel_helper_funcs.prepare = ironlake_crtc_prepare;
		intel_helper_funcs.commit = ironlake_crtc_commit;
	} else {
		intel_helper_funcs.prepare = i9xx_crtc_prepare;
		intel_helper_funcs.commit = i9xx_crtc_commit;
	}

J
Jesse Barnes 已提交
7691 7692
	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);

7693 7694 7695 7696
	intel_crtc->busy = false;

	setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
		    (unsigned long)intel_crtc);
J
Jesse Barnes 已提交
7697 7698
}

7699
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7700
				struct drm_file *file)
7701 7702 7703
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7704 7705
	struct drm_mode_object *drmmode_obj;
	struct intel_crtc *crtc;
7706 7707 7708 7709 7710 7711

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

7712 7713
	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
			DRM_MODE_OBJECT_CRTC);
7714

7715
	if (!drmmode_obj) {
7716 7717 7718 7719
		DRM_ERROR("no such CRTC id\n");
		return -EINVAL;
	}

7720 7721
	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
	pipe_from_crtc_id->pipe = crtc->pipe;
7722

7723
	return 0;
7724 7725
}

7726
static int intel_encoder_clones(struct drm_device *dev, int type_mask)
J
Jesse Barnes 已提交
7727
{
7728
	struct intel_encoder *encoder;
J
Jesse Barnes 已提交
7729 7730 7731
	int index_mask = 0;
	int entry = 0;

7732 7733
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		if (type_mask & encoder->clone_mask)
J
Jesse Barnes 已提交
7734 7735 7736
			index_mask |= (1 << entry);
		entry++;
	}
7737

J
Jesse Barnes 已提交
7738 7739 7740
	return index_mask;
}

7741 7742 7743 7744 7745 7746 7747 7748 7749 7750 7751 7752 7753 7754 7755 7756 7757
static bool has_edp_a(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!IS_MOBILE(dev))
		return false;

	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		return false;

	if (IS_GEN5(dev) &&
	    (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		return false;

	return true;
}

J
Jesse Barnes 已提交
7758 7759
static void intel_setup_outputs(struct drm_device *dev)
{
7760
	struct drm_i915_private *dev_priv = dev->dev_private;
7761
	struct intel_encoder *encoder;
7762
	bool dpd_is_edp = false;
7763
	bool has_lvds = false;
J
Jesse Barnes 已提交
7764

7765
	if (IS_MOBILE(dev) && !IS_I830(dev))
7766 7767 7768 7769 7770
		has_lvds = intel_lvds_init(dev);
	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
		/* disable the panel fitter on everything but LVDS */
		I915_WRITE(PFIT_CONTROL, 0);
	}
J
Jesse Barnes 已提交
7771

7772
	if (HAS_PCH_SPLIT(dev)) {
7773
		dpd_is_edp = intel_dpd_is_edp(dev);
7774

7775
		if (has_edp_a(dev))
7776 7777
			intel_dp_init(dev, DP_A);

7778 7779 7780 7781 7782 7783 7784 7785 7786
		if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
			intel_dp_init(dev, PCH_DP_D);
	}

	intel_crt_init(dev);

	if (HAS_PCH_SPLIT(dev)) {
		int found;

7787
		if (I915_READ(HDMIB) & PORT_DETECTED) {
7788 7789
			/* PCH SDVOB multiplex with HDMIB */
			found = intel_sdvo_init(dev, PCH_SDVOB);
7790 7791
			if (!found)
				intel_hdmi_init(dev, HDMIB);
7792 7793
			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
				intel_dp_init(dev, PCH_DP_B);
7794 7795 7796 7797 7798 7799 7800 7801
		}

		if (I915_READ(HDMIC) & PORT_DETECTED)
			intel_hdmi_init(dev, HDMIC);

		if (I915_READ(HDMID) & PORT_DETECTED)
			intel_hdmi_init(dev, HDMID);

7802 7803 7804
		if (I915_READ(PCH_DP_C) & DP_DETECTED)
			intel_dp_init(dev, PCH_DP_C);

7805
		if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7806 7807
			intel_dp_init(dev, PCH_DP_D);

7808
	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7809
		bool found = false;
7810

7811
		if (I915_READ(SDVOB) & SDVO_DETECTED) {
7812
			DRM_DEBUG_KMS("probing SDVOB\n");
7813
			found = intel_sdvo_init(dev, SDVOB);
7814 7815
			if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7816
				intel_hdmi_init(dev, SDVOB);
7817
			}
7818

7819 7820
			if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
				DRM_DEBUG_KMS("probing DP_B\n");
7821
				intel_dp_init(dev, DP_B);
7822
			}
7823
		}
7824 7825 7826

		/* Before G4X SDVOC doesn't have its own detect register */

7827 7828
		if (I915_READ(SDVOB) & SDVO_DETECTED) {
			DRM_DEBUG_KMS("probing SDVOC\n");
7829
			found = intel_sdvo_init(dev, SDVOC);
7830
		}
7831 7832 7833

		if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {

7834 7835
			if (SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7836
				intel_hdmi_init(dev, SDVOC);
7837 7838 7839
			}
			if (SUPPORTS_INTEGRATED_DP(dev)) {
				DRM_DEBUG_KMS("probing DP_C\n");
7840
				intel_dp_init(dev, DP_C);
7841
			}
7842
		}
7843

7844 7845 7846
		if (SUPPORTS_INTEGRATED_DP(dev) &&
		    (I915_READ(DP_D) & DP_DETECTED)) {
			DRM_DEBUG_KMS("probing DP_D\n");
7847
			intel_dp_init(dev, DP_D);
7848
		}
7849
	} else if (IS_GEN2(dev))
J
Jesse Barnes 已提交
7850 7851
		intel_dvo_init(dev);

7852
	if (SUPPORTS_TV(dev))
J
Jesse Barnes 已提交
7853 7854
		intel_tv_init(dev);

7855 7856 7857 7858
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		encoder->base.possible_crtcs = encoder->crtc_mask;
		encoder->base.possible_clones =
			intel_encoder_clones(dev, encoder->clone_mask);
J
Jesse Barnes 已提交
7859
	}
7860

7861 7862
	/* disable all the possible outputs/crtcs before entering KMS mode */
	drm_helper_disable_unused_functions(dev);
7863 7864 7865

	if (HAS_PCH_SPLIT(dev))
		ironlake_init_pch_refclk(dev);
J
Jesse Barnes 已提交
7866 7867 7868 7869 7870 7871 7872
}

static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

	drm_framebuffer_cleanup(fb);
7873
	drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
J
Jesse Barnes 已提交
7874 7875 7876 7877 7878

	kfree(intel_fb);
}

static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7879
						struct drm_file *file,
J
Jesse Barnes 已提交
7880 7881 7882
						unsigned int *handle)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7883
	struct drm_i915_gem_object *obj = intel_fb->obj;
J
Jesse Barnes 已提交
7884

7885
	return drm_gem_handle_create(file, &obj->base, handle);
J
Jesse Barnes 已提交
7886 7887 7888 7889 7890 7891 7892
}

static const struct drm_framebuffer_funcs intel_fb_funcs = {
	.destroy = intel_user_framebuffer_destroy,
	.create_handle = intel_user_framebuffer_create_handle,
};

7893 7894
int intel_framebuffer_init(struct drm_device *dev,
			   struct intel_framebuffer *intel_fb,
7895
			   struct drm_mode_fb_cmd2 *mode_cmd,
7896
			   struct drm_i915_gem_object *obj)
J
Jesse Barnes 已提交
7897 7898 7899
{
	int ret;

7900
	if (obj->tiling_mode == I915_TILING_Y)
7901 7902
		return -EINVAL;

7903
	if (mode_cmd->pitches[0] & 63)
7904 7905
		return -EINVAL;

7906
	switch (mode_cmd->pixel_format) {
V
Ville Syrjälä 已提交
7907 7908 7909 7910 7911 7912
	case DRM_FORMAT_RGB332:
	case DRM_FORMAT_RGB565:
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
7913
		/* RGB formats are common across chipsets */
7914
		break;
V
Ville Syrjälä 已提交
7915 7916 7917 7918
	case DRM_FORMAT_YUYV:
	case DRM_FORMAT_UYVY:
	case DRM_FORMAT_YVYU:
	case DRM_FORMAT_VYUY:
7919 7920
		break;
	default:
7921 7922
		DRM_DEBUG_KMS("unsupported pixel format %u\n",
				mode_cmd->pixel_format);
7923 7924 7925
		return -EINVAL;
	}

J
Jesse Barnes 已提交
7926 7927 7928 7929 7930 7931 7932 7933 7934 7935 7936 7937 7938 7939
	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
	if (ret) {
		DRM_ERROR("framebuffer init failed %d\n", ret);
		return ret;
	}

	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
	intel_fb->obj = obj;
	return 0;
}

static struct drm_framebuffer *
intel_user_framebuffer_create(struct drm_device *dev,
			      struct drm_file *filp,
7940
			      struct drm_mode_fb_cmd2 *mode_cmd)
J
Jesse Barnes 已提交
7941
{
7942
	struct drm_i915_gem_object *obj;
J
Jesse Barnes 已提交
7943

7944 7945
	obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
						mode_cmd->handles[0]));
7946
	if (&obj->base == NULL)
7947
		return ERR_PTR(-ENOENT);
J
Jesse Barnes 已提交
7948

7949
	return intel_framebuffer_create(dev, mode_cmd, obj);
J
Jesse Barnes 已提交
7950 7951 7952 7953
}

static const struct drm_mode_config_funcs intel_mode_funcs = {
	.fb_create = intel_user_framebuffer_create,
7954
	.output_poll_changed = intel_fb_output_poll_changed,
J
Jesse Barnes 已提交
7955 7956
};

7957
static struct drm_i915_gem_object *
7958
intel_alloc_context_page(struct drm_device *dev)
7959
{
7960
	struct drm_i915_gem_object *ctx;
7961 7962
	int ret;

7963 7964
	WARN_ON(!mutex_is_locked(&dev->struct_mutex));

7965 7966
	ctx = i915_gem_alloc_object(dev, 4096);
	if (!ctx) {
7967 7968 7969 7970
		DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
		return NULL;
	}

7971
	ret = i915_gem_object_pin(ctx, 4096, true);
7972 7973 7974 7975 7976
	if (ret) {
		DRM_ERROR("failed to pin power context: %d\n", ret);
		goto err_unref;
	}

7977
	ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7978 7979 7980 7981 7982
	if (ret) {
		DRM_ERROR("failed to set-domain on power context: %d\n", ret);
		goto err_unpin;
	}

7983
	return ctx;
7984 7985

err_unpin:
7986
	i915_gem_object_unpin(ctx);
7987
err_unref:
7988
	drm_gem_object_unreference(&ctx->base);
7989 7990 7991 7992
	mutex_unlock(&dev->struct_mutex);
	return NULL;
}

7993 7994 7995 7996 7997 7998 7999 8000 8001 8002 8003 8004 8005 8006 8007 8008 8009 8010 8011 8012 8013 8014
bool ironlake_set_drps(struct drm_device *dev, u8 val)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u16 rgvswctl;

	rgvswctl = I915_READ16(MEMSWCTL);
	if (rgvswctl & MEMCTL_CMD_STS) {
		DRM_DEBUG("gpu busy, RCS change rejected\n");
		return false; /* still busy with another command */
	}

	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
		(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
	I915_WRITE16(MEMSWCTL, rgvswctl);
	POSTING_READ16(MEMSWCTL);

	rgvswctl |= MEMCTL_CMD_STS;
	I915_WRITE16(MEMSWCTL, rgvswctl);

	return true;
}

8015 8016 8017
void ironlake_enable_drps(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
8018
	u32 rgvmodectl = I915_READ(MEMMODECTL);
8019 8020
	u8 fmax, fmin, fstart, vstart;

8021 8022 8023 8024
	/* Enable temp reporting */
	I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
	I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);

8025 8026 8027 8028 8029 8030 8031 8032 8033 8034 8035 8036 8037 8038 8039
	/* 100ms RC evaluation intervals */
	I915_WRITE(RCUPEI, 100000);
	I915_WRITE(RCDNEI, 100000);

	/* Set max/min thresholds to 90ms and 80ms respectively */
	I915_WRITE(RCBMAXAVG, 90000);
	I915_WRITE(RCBMINAVG, 80000);

	I915_WRITE(MEMIHYST, 1);

	/* Set up min, max, and cur for interrupt handling */
	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
		MEMMODE_FSTART_SHIFT;
8040

8041 8042 8043
	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
		PXVFREQ_PX_SHIFT;

8044
	dev_priv->fmax = fmax; /* IPS callback will increase this */
8045 8046
	dev_priv->fstart = fstart;

8047
	dev_priv->max_delay = fstart;
8048 8049 8050
	dev_priv->min_delay = fmin;
	dev_priv->cur_delay = fstart;

8051 8052
	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
			 fmax, fmin, fstart);
8053

8054 8055 8056 8057 8058 8059 8060 8061 8062 8063 8064 8065
	I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);

	/*
	 * Interrupts will be enabled in ironlake_irq_postinstall
	 */

	I915_WRITE(VIDSTART, vstart);
	POSTING_READ(VIDSTART);

	rgvmodectl |= MEMMODE_SWMODE_EN;
	I915_WRITE(MEMMODECTL, rgvmodectl);

8066
	if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8067
		DRM_ERROR("stuck trying to change perf mode\n");
8068 8069
	msleep(1);

8070
	ironlake_set_drps(dev, fstart);
8071

8072 8073 8074 8075 8076
	dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
		I915_READ(0x112e0);
	dev_priv->last_time1 = jiffies_to_msecs(jiffies);
	dev_priv->last_count2 = I915_READ(0x112f4);
	getrawmonotonic(&dev_priv->last_time2);
8077 8078 8079 8080 8081
}

void ironlake_disable_drps(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
8082
	u16 rgvswctl = I915_READ16(MEMSWCTL);
8083 8084 8085 8086 8087 8088 8089 8090 8091

	/* Ack interrupts, disable EFC interrupt */
	I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
	I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
	I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
	I915_WRITE(DEIIR, DE_PCU_EVENT);
	I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);

	/* Go back to the starting frequency */
8092
	ironlake_set_drps(dev, dev_priv->fstart);
8093 8094 8095 8096 8097 8098 8099
	msleep(1);
	rgvswctl |= MEMCTL_CMD_STS;
	I915_WRITE(MEMSWCTL, rgvswctl);
	msleep(1);

}

8100 8101 8102 8103 8104 8105 8106 8107 8108 8109 8110 8111 8112 8113 8114 8115
void gen6_set_rps(struct drm_device *dev, u8 val)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 swreq;

	swreq = (val & 0x3ff) << 25;
	I915_WRITE(GEN6_RPNSWREQ, swreq);
}

void gen6_disable_rps(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
	I915_WRITE(GEN6_PMIER, 0);
8116 8117 8118 8119
	/* Complete PM interrupt masking here doesn't race with the rps work
	 * item again unmasking PM interrupts because that is using a different
	 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
	 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8120 8121 8122 8123 8124

	spin_lock_irq(&dev_priv->rps_lock);
	dev_priv->pm_iir = 0;
	spin_unlock_irq(&dev_priv->rps_lock);

8125 8126 8127
	I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
}

8128 8129 8130 8131 8132 8133 8134 8135 8136 8137 8138 8139 8140 8141 8142 8143 8144 8145 8146 8147 8148 8149 8150 8151 8152 8153 8154 8155 8156 8157 8158 8159 8160 8161 8162 8163 8164 8165 8166 8167 8168 8169 8170 8171 8172 8173 8174 8175 8176 8177 8178 8179 8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 8201 8202 8203 8204 8205 8206 8207 8208 8209 8210 8211 8212 8213
static unsigned long intel_pxfreq(u32 vidfreq)
{
	unsigned long freq;
	int div = (vidfreq & 0x3f0000) >> 16;
	int post = (vidfreq & 0x3000) >> 12;
	int pre = (vidfreq & 0x7);

	if (!pre)
		return 0;

	freq = ((div * 133333) / ((1<<post) * pre));

	return freq;
}

void intel_init_emon(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 lcfuse;
	u8 pxw[16];
	int i;

	/* Disable to program */
	I915_WRITE(ECR, 0);
	POSTING_READ(ECR);

	/* Program energy weights for various events */
	I915_WRITE(SDEW, 0x15040d00);
	I915_WRITE(CSIEW0, 0x007f0000);
	I915_WRITE(CSIEW1, 0x1e220004);
	I915_WRITE(CSIEW2, 0x04000004);

	for (i = 0; i < 5; i++)
		I915_WRITE(PEW + (i * 4), 0);
	for (i = 0; i < 3; i++)
		I915_WRITE(DEW + (i * 4), 0);

	/* Program P-state weights to account for frequency power adjustment */
	for (i = 0; i < 16; i++) {
		u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
		unsigned long freq = intel_pxfreq(pxvidfreq);
		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
			PXVFREQ_PX_SHIFT;
		unsigned long val;

		val = vid * vid;
		val *= (freq / 1000);
		val *= 255;
		val /= (127*127*900);
		if (val > 0xff)
			DRM_ERROR("bad pxval: %ld\n", val);
		pxw[i] = val;
	}
	/* Render standby states get 0 weight */
	pxw[14] = 0;
	pxw[15] = 0;

	for (i = 0; i < 4; i++) {
		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
		I915_WRITE(PXW + (i * 4), val);
	}

	/* Adjust magic regs to magic values (more experimental results) */
	I915_WRITE(OGW0, 0);
	I915_WRITE(OGW1, 0);
	I915_WRITE(EG0, 0x00007f00);
	I915_WRITE(EG1, 0x0000000e);
	I915_WRITE(EG2, 0x000e0000);
	I915_WRITE(EG3, 0x68000300);
	I915_WRITE(EG4, 0x42000000);
	I915_WRITE(EG5, 0x00140031);
	I915_WRITE(EG6, 0);
	I915_WRITE(EG7, 0);

	for (i = 0; i < 8; i++)
		I915_WRITE(PXWL + (i * 4), 0);

	/* Enable PMON + select events */
	I915_WRITE(ECR, 0x80000019);

	lcfuse = I915_READ(LCFUSE02);

	dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
}

8214 8215 8216 8217 8218 8219 8220 8221 8222 8223 8224 8225 8226 8227 8228
static bool intel_enable_rc6(struct drm_device *dev)
{
	/*
	 * Respect the kernel parameter if it is set
	 */
	if (i915_enable_rc6 >= 0)
		return i915_enable_rc6;

	/*
	 * Disable RC6 on Ironlake
	 */
	if (INTEL_INFO(dev)->gen == 5)
		return 0;

	/*
8229
	 * Disable rc6 on Sandybridge
8230 8231
	 */
	if (INTEL_INFO(dev)->gen == 6) {
8232 8233
		DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
		return 0;
8234 8235 8236 8237 8238
	}
	DRM_DEBUG_DRIVER("RC6 enabled\n");
	return 1;
}

8239
void gen6_enable_rps(struct drm_i915_private *dev_priv)
8240
{
8241 8242
	u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8243
	u32 pcu_mbox, rc6_mask = 0;
B
Ben Widawsky 已提交
8244
	u32 gtfifodbg;
8245
	int cur_freq, min_freq, max_freq;
8246 8247 8248 8249 8250 8251 8252 8253 8254
	int i;

	/* Here begins a magic sequence of register writes to enable
	 * auto-downclocking.
	 *
	 * Perhaps there might be some value in exposing these to
	 * userspace...
	 */
	I915_WRITE(GEN6_RC_STATE, 0);
8255
	mutex_lock(&dev_priv->dev->struct_mutex);
B
Ben Widawsky 已提交
8256 8257 8258 8259 8260 8261 8262

	/* Clear the DBG now so we don't confuse earlier errors */
	if ((gtfifodbg = I915_READ(GTFIFODBG))) {
		DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
		I915_WRITE(GTFIFODBG, gtfifodbg);
	}

8263
	gen6_gt_force_wake_get(dev_priv);
8264

8265
	/* disable the counters and set deterministic thresholds */
8266 8267 8268 8269 8270 8271 8272 8273 8274 8275 8276 8277 8278 8279 8280 8281 8282
	I915_WRITE(GEN6_RC_CONTROL, 0);

	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);

	for (i = 0; i < I915_NUM_RINGS; i++)
		I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);

	I915_WRITE(GEN6_RC_SLEEP, 0);
	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */

8283
	if (intel_enable_rc6(dev_priv->dev))
8284 8285 8286
		rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
			GEN6_RC_CTL_RC6_ENABLE;

8287
	I915_WRITE(GEN6_RC_CONTROL,
8288
		   rc6_mask |
8289
		   GEN6_RC_CTL_EI_MODE(1) |
8290 8291
		   GEN6_RC_CTL_HW_ENABLE);

8292
	I915_WRITE(GEN6_RPNSWREQ,
8293 8294 8295 8296 8297 8298 8299 8300 8301 8302
		   GEN6_FREQUENCY(10) |
		   GEN6_OFFSET(0) |
		   GEN6_AGGRESSIVE_TURBO);
	I915_WRITE(GEN6_RC_VIDEO_FREQ,
		   GEN6_FREQUENCY(12));

	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
		   18 << 24 |
		   6 << 16);
8303 8304
	I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8305
	I915_WRITE(GEN6_RP_UP_EI, 100000);
8306
	I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8307 8308 8309
	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
	I915_WRITE(GEN6_RP_CONTROL,
		   GEN6_RP_MEDIA_TURBO |
8310
		   GEN6_RP_MEDIA_HW_MODE |
8311 8312
		   GEN6_RP_MEDIA_IS_GFX |
		   GEN6_RP_ENABLE |
8313 8314
		   GEN6_RP_UP_BUSY_AVG |
		   GEN6_RP_DOWN_IDLE_CONT);
8315 8316 8317 8318 8319 8320 8321 8322 8323 8324 8325 8326 8327

	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		     500))
		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");

	I915_WRITE(GEN6_PCODE_DATA, 0);
	I915_WRITE(GEN6_PCODE_MAILBOX,
		   GEN6_PCODE_READY |
		   GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		     500))
		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");

8328 8329 8330 8331 8332 8333 8334 8335 8336 8337 8338 8339 8340 8341 8342
	min_freq = (rp_state_cap & 0xff0000) >> 16;
	max_freq = rp_state_cap & 0xff;
	cur_freq = (gt_perf_status & 0xff00) >> 8;

	/* Check for overclock support */
	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		     500))
		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
	pcu_mbox = I915_READ(GEN6_PCODE_DATA);
	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		     500))
		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
	if (pcu_mbox & (1<<31)) { /* OC supported */
		max_freq = pcu_mbox & 0xff;
8343
		DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8344 8345 8346 8347 8348 8349 8350
	}

	/* In units of 100MHz */
	dev_priv->max_delay = max_freq;
	dev_priv->min_delay = min_freq;
	dev_priv->cur_delay = cur_freq;

8351 8352 8353 8354 8355 8356 8357 8358 8359
	/* requires MSI enabled */
	I915_WRITE(GEN6_PMIER,
		   GEN6_PM_MBOX_EVENT |
		   GEN6_PM_THERMAL_EVENT |
		   GEN6_PM_RP_DOWN_TIMEOUT |
		   GEN6_PM_RP_UP_THRESHOLD |
		   GEN6_PM_RP_DOWN_THRESHOLD |
		   GEN6_PM_RP_UP_EI_EXPIRED |
		   GEN6_PM_RP_DOWN_EI_EXPIRED);
8360 8361
	spin_lock_irq(&dev_priv->rps_lock);
	WARN_ON(dev_priv->pm_iir != 0);
8362
	I915_WRITE(GEN6_PMIMR, 0);
8363
	spin_unlock_irq(&dev_priv->rps_lock);
8364 8365
	/* enable all PM interrupts */
	I915_WRITE(GEN6_PMINTRMSK, 0);
8366

8367
	gen6_gt_force_wake_put(dev_priv);
8368
	mutex_unlock(&dev_priv->dev->struct_mutex);
8369 8370
}

8371 8372 8373 8374 8375 8376 8377 8378 8379 8380 8381 8382 8383 8384 8385 8386 8387 8388 8389 8390 8391 8392 8393 8394 8395 8396 8397 8398 8399 8400 8401 8402 8403 8404 8405 8406 8407 8408 8409 8410 8411 8412 8413 8414 8415 8416 8417 8418 8419 8420 8421 8422 8423
void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
{
	int min_freq = 15;
	int gpu_freq, ia_freq, max_ia_freq;
	int scaling_factor = 180;

	max_ia_freq = cpufreq_quick_get_max(0);
	/*
	 * Default to measured freq if none found, PCU will ensure we don't go
	 * over
	 */
	if (!max_ia_freq)
		max_ia_freq = tsc_khz;

	/* Convert from kHz to MHz */
	max_ia_freq /= 1000;

	mutex_lock(&dev_priv->dev->struct_mutex);

	/*
	 * For each potential GPU frequency, load a ring frequency we'd like
	 * to use for memory access.  We do this by specifying the IA frequency
	 * the PCU should use as a reference to determine the ring frequency.
	 */
	for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
	     gpu_freq--) {
		int diff = dev_priv->max_delay - gpu_freq;

		/*
		 * For GPU frequencies less than 750MHz, just use the lowest
		 * ring freq.
		 */
		if (gpu_freq < min_freq)
			ia_freq = 800;
		else
			ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
		ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);

		I915_WRITE(GEN6_PCODE_DATA,
			   (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
			   gpu_freq);
		I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
			   GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
		if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
			      GEN6_PCODE_READY) == 0, 10)) {
			DRM_ERROR("pcode write of freq table timed out\n");
			continue;
		}
	}

	mutex_unlock(&dev_priv->dev->struct_mutex);
}

8424 8425 8426 8427 8428 8429 8430 8431 8432 8433 8434 8435 8436 8437 8438 8439 8440 8441 8442 8443 8444 8445 8446 8447 8448 8449 8450 8451 8452 8453 8454 8455 8456 8457 8458 8459 8460 8461 8462 8463 8464 8465 8466 8467 8468 8469 8470 8471 8472 8473 8474 8475 8476 8477 8478 8479 8480 8481 8482 8483 8484 8485 8486 8487 8488 8489 8490
static void ironlake_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;

	/* Required for FBC */
	dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
		DPFCRUNIT_CLOCK_GATE_DISABLE |
		DPFDUNIT_CLOCK_GATE_DISABLE;
	/* Required for CxSR */
	dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;

	I915_WRITE(PCH_3DCGDIS0,
		   MARIUNIT_CLOCK_GATE_DISABLE |
		   SVSMUNIT_CLOCK_GATE_DISABLE);
	I915_WRITE(PCH_3DCGDIS1,
		   VFMUNIT_CLOCK_GATE_DISABLE);

	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);

	/*
	 * According to the spec the following bits should be set in
	 * order to enable memory self-refresh
	 * The bit 22/21 of 0x42004
	 * The bit 5 of 0x42020
	 * The bit 15 of 0x45000
	 */
	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		   (I915_READ(ILK_DISPLAY_CHICKEN2) |
		    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
	I915_WRITE(ILK_DSPCLK_GATE,
		   (I915_READ(ILK_DSPCLK_GATE) |
		    ILK_DPARB_CLK_GATE));
	I915_WRITE(DISP_ARB_CTL,
		   (I915_READ(DISP_ARB_CTL) |
		    DISP_FBC_WM_DIS));
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

	/*
	 * Based on the document from hardware guys the following bits
	 * should be set unconditionally in order to enable FBC.
	 * The bit 22 of 0x42000
	 * The bit 22 of 0x42004
	 * The bit 7,8,9 of 0x42020.
	 */
	if (IS_IRONLAKE_M(dev)) {
		I915_WRITE(ILK_DISPLAY_CHICKEN1,
			   I915_READ(ILK_DISPLAY_CHICKEN1) |
			   ILK_FBCQ_DIS);
		I915_WRITE(ILK_DISPLAY_CHICKEN2,
			   I915_READ(ILK_DISPLAY_CHICKEN2) |
			   ILK_DPARB_GATE);
		I915_WRITE(ILK_DSPCLK_GATE,
			   I915_READ(ILK_DSPCLK_GATE) |
			   ILK_DPFC_DIS1 |
			   ILK_DPFC_DIS2 |
			   ILK_CLK_FBC);
	}

	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		   I915_READ(ILK_DISPLAY_CHICKEN2) |
		   ILK_ELPIN_409_SELECT);
	I915_WRITE(_3D_CHICKEN2,
		   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
		   _3D_CHICKEN2_WM_READ_PIPELINED);
8491 8492
}

8493
static void gen6_init_clock_gating(struct drm_device *dev)
8494 8495
{
	struct drm_i915_private *dev_priv = dev->dev_private;
8496
	int pipe;
8497 8498 8499
	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;

	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8500

8501 8502 8503
	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		   I915_READ(ILK_DISPLAY_CHICKEN2) |
		   ILK_ELPIN_409_SELECT);
8504

8505 8506 8507
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);
8508

8509 8510 8511 8512 8513 8514
	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
	 * gating disable must be set.  Failure to set it results in
	 * flickering pixels due to Z write ordering failures after
	 * some amount of runtime in the Mesa "fire" demo, and Unigine
	 * Sanctuary and Tropics, and apparently anything else with
	 * alpha test or pixel discard.
8515 8516 8517
	 *
	 * According to the spec, bit 11 (RCCUNIT) must also be set,
	 * but we didn't debug actual testcases to find it out.
8518
	 */
8519 8520 8521
	I915_WRITE(GEN6_UCGCTL2,
		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8522

8523
	/*
8524 8525 8526 8527 8528 8529 8530
	 * According to the spec the following bits should be
	 * set in order to enable memory self-refresh and fbc:
	 * The bit21 and bit22 of 0x42000
	 * The bit21 and bit22 of 0x42004
	 * The bit5 and bit7 of 0x42020
	 * The bit14 of 0x70180
	 * The bit14 of 0x71180
8531
	 */
8532 8533 8534 8535 8536 8537 8538 8539 8540 8541
	I915_WRITE(ILK_DISPLAY_CHICKEN1,
		   I915_READ(ILK_DISPLAY_CHICKEN1) |
		   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		   I915_READ(ILK_DISPLAY_CHICKEN2) |
		   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
	I915_WRITE(ILK_DSPCLK_GATE,
		   I915_READ(ILK_DSPCLK_GATE) |
		   ILK_DPARB_CLK_GATE  |
		   ILK_DPFD_CLK_GATE);
8542

8543
	for_each_pipe(pipe) {
8544 8545 8546
		I915_WRITE(DSPCNTR(pipe),
			   I915_READ(DSPCNTR(pipe)) |
			   DISPPLANE_TRICKLE_FEED_DISABLE);
8547 8548
		intel_flush_display_plane(dev_priv, pipe);
	}
8549
}
8550

8551 8552 8553 8554 8555
static void ivybridge_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;
	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8556

8557
	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8558

8559 8560 8561
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);
8562

8563
	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8564

8565 8566 8567 8568
	I915_WRITE(IVB_CHICKEN3,
		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
		   CHICKEN3_DGMG_DONE_FIX_DISABLE);

8569
	for_each_pipe(pipe) {
8570 8571 8572
		I915_WRITE(DSPCNTR(pipe),
			   I915_READ(DSPCNTR(pipe)) |
			   DISPPLANE_TRICKLE_FEED_DISABLE);
8573 8574
		intel_flush_display_plane(dev_priv, pipe);
	}
8575 8576
}

8577 8578 8579 8580
static void g4x_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dspclk_gate;
8581

8582 8583 8584 8585 8586 8587 8588 8589 8590 8591 8592 8593
	I915_WRITE(RENCLK_GATE_D1, 0);
	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
		   GS_UNIT_CLOCK_GATE_DISABLE |
		   CL_UNIT_CLOCK_GATE_DISABLE);
	I915_WRITE(RAMCLK_GATE_D, 0);
	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
		OVRUNIT_CLOCK_GATE_DISABLE |
		OVCUNIT_CLOCK_GATE_DISABLE;
	if (IS_GM45(dev))
		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
}
8594

8595 8596 8597
static void crestline_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
8598

8599 8600 8601 8602 8603 8604
	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
	I915_WRITE(RENCLK_GATE_D2, 0);
	I915_WRITE(DSPCLK_GATE_D, 0);
	I915_WRITE(RAMCLK_GATE_D, 0);
	I915_WRITE16(DEUC, 0);
}
8605

8606 8607 8608 8609 8610 8611 8612 8613 8614 8615 8616 8617 8618 8619 8620 8621 8622 8623 8624 8625 8626 8627 8628 8629 8630 8631 8632 8633 8634 8635 8636 8637 8638 8639
static void broadwater_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
		   I965_RCC_CLOCK_GATE_DISABLE |
		   I965_RCPB_CLOCK_GATE_DISABLE |
		   I965_ISC_CLOCK_GATE_DISABLE |
		   I965_FBC_CLOCK_GATE_DISABLE);
	I915_WRITE(RENCLK_GATE_D2, 0);
}

static void gen3_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dstate = I915_READ(D_STATE);

	dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
		DSTATE_DOT_CLOCK_GATING;
	I915_WRITE(D_STATE, dstate);
}

static void i85x_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
}

static void i830_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8640 8641
}

8642 8643 8644 8645 8646 8647 8648 8649 8650 8651 8652 8653 8654 8655 8656
static void ibx_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/*
	 * On Ibex Peak and Cougar Point, we need to disable clock
	 * gating for the panel power sequencer or it will fail to
	 * start up when no ports are active.
	 */
	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
}

static void cpt_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
8657
	int pipe;
8658 8659 8660 8661 8662 8663 8664 8665 8666

	/*
	 * On Ibex Peak and Cougar Point, we need to disable clock
	 * gating for the panel power sequencer or it will fail to
	 * start up when no ports are active.
	 */
	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
		   DPLS_EDP_PPS_FIX_DIS);
8667 8668 8669
	/* Without this, mode sets may fail silently on FDI */
	for_each_pipe(pipe)
		I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8670 8671
}

C
Chris Wilson 已提交
8672
static void ironlake_teardown_rc6(struct drm_device *dev)
8673 8674 8675 8676
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev_priv->renderctx) {
C
Chris Wilson 已提交
8677 8678
		i915_gem_object_unpin(dev_priv->renderctx);
		drm_gem_object_unreference(&dev_priv->renderctx->base);
8679 8680 8681 8682
		dev_priv->renderctx = NULL;
	}

	if (dev_priv->pwrctx) {
C
Chris Wilson 已提交
8683 8684 8685 8686 8687 8688 8689 8690 8691 8692 8693 8694 8695 8696 8697
		i915_gem_object_unpin(dev_priv->pwrctx);
		drm_gem_object_unreference(&dev_priv->pwrctx->base);
		dev_priv->pwrctx = NULL;
	}
}

static void ironlake_disable_rc6(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (I915_READ(PWRCTXA)) {
		/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
		I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
		wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
			 50);
8698 8699 8700 8701

		I915_WRITE(PWRCTXA, 0);
		POSTING_READ(PWRCTXA);

C
Chris Wilson 已提交
8702 8703
		I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
		POSTING_READ(RSTDBYCTL);
8704
	}
C
Chris Wilson 已提交
8705

8706
	ironlake_teardown_rc6(dev);
8707 8708
}

C
Chris Wilson 已提交
8709
static int ironlake_setup_rc6(struct drm_device *dev)
J
Jesse Barnes 已提交
8710 8711 8712
{
	struct drm_i915_private *dev_priv = dev->dev_private;

C
Chris Wilson 已提交
8713 8714 8715 8716 8717 8718 8719 8720 8721 8722 8723 8724 8725
	if (dev_priv->renderctx == NULL)
		dev_priv->renderctx = intel_alloc_context_page(dev);
	if (!dev_priv->renderctx)
		return -ENOMEM;

	if (dev_priv->pwrctx == NULL)
		dev_priv->pwrctx = intel_alloc_context_page(dev);
	if (!dev_priv->pwrctx) {
		ironlake_teardown_rc6(dev);
		return -ENOMEM;
	}

	return 0;
J
Jesse Barnes 已提交
8726 8727 8728 8729 8730 8731 8732
}

void ironlake_enable_rc6(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

C
Chris Wilson 已提交
8733 8734 8735
	/* rc6 disabled by default due to repeated reports of hanging during
	 * boot and resume.
	 */
8736
	if (!intel_enable_rc6(dev))
C
Chris Wilson 已提交
8737 8738
		return;

8739
	mutex_lock(&dev->struct_mutex);
C
Chris Wilson 已提交
8740
	ret = ironlake_setup_rc6(dev);
8741 8742
	if (ret) {
		mutex_unlock(&dev->struct_mutex);
C
Chris Wilson 已提交
8743
		return;
8744
	}
C
Chris Wilson 已提交
8745

J
Jesse Barnes 已提交
8746 8747 8748 8749 8750 8751
	/*
	 * GPU can automatically power down the render unit if given a page
	 * to save state.
	 */
	ret = BEGIN_LP_RING(6);
	if (ret) {
C
Chris Wilson 已提交
8752
		ironlake_teardown_rc6(dev);
8753
		mutex_unlock(&dev->struct_mutex);
J
Jesse Barnes 已提交
8754 8755
		return;
	}
C
Chris Wilson 已提交
8756

J
Jesse Barnes 已提交
8757 8758 8759 8760 8761 8762 8763 8764 8765 8766 8767 8768
	OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
	OUT_RING(MI_SET_CONTEXT);
	OUT_RING(dev_priv->renderctx->gtt_offset |
		 MI_MM_SPACE_GTT |
		 MI_SAVE_EXT_STATE_EN |
		 MI_RESTORE_EXT_STATE_EN |
		 MI_RESTORE_INHIBIT);
	OUT_RING(MI_SUSPEND_FLUSH);
	OUT_RING(MI_NOOP);
	OUT_RING(MI_FLUSH);
	ADVANCE_LP_RING();

8769 8770 8771 8772 8773 8774 8775 8776 8777 8778 8779 8780 8781
	/*
	 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
	 * does an implicit flush, combined with MI_FLUSH above, it should be
	 * safe to assume that renderctx is valid
	 */
	ret = intel_wait_ring_idle(LP_RING(dev_priv));
	if (ret) {
		DRM_ERROR("failed to enable ironlake power power savings\n");
		ironlake_teardown_rc6(dev);
		mutex_unlock(&dev->struct_mutex);
		return;
	}

J
Jesse Barnes 已提交
8782 8783
	I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8784
	mutex_unlock(&dev->struct_mutex);
J
Jesse Barnes 已提交
8785 8786
}

8787 8788 8789 8790 8791 8792 8793 8794 8795
void intel_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	dev_priv->display.init_clock_gating(dev);

	if (dev_priv->display.init_pch_clock_gating)
		dev_priv->display.init_pch_clock_gating(dev);
}
C
Chris Wilson 已提交
8796

8797 8798 8799 8800 8801 8802
/* Set up chip specific display functions */
static void intel_init_display(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* We always want a DPMS function */
8803
	if (HAS_PCH_SPLIT(dev)) {
8804
		dev_priv->display.dpms = ironlake_crtc_dpms;
8805
		dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8806
		dev_priv->display.update_plane = ironlake_update_plane;
8807
	} else {
8808
		dev_priv->display.dpms = i9xx_crtc_dpms;
8809
		dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8810
		dev_priv->display.update_plane = i9xx_update_plane;
8811
	}
8812

8813
	if (I915_HAS_FBC(dev)) {
8814
		if (HAS_PCH_SPLIT(dev)) {
8815 8816 8817 8818
			dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
			dev_priv->display.enable_fbc = ironlake_enable_fbc;
			dev_priv->display.disable_fbc = ironlake_disable_fbc;
		} else if (IS_GM45(dev)) {
8819 8820 8821
			dev_priv->display.fbc_enabled = g4x_fbc_enabled;
			dev_priv->display.enable_fbc = g4x_enable_fbc;
			dev_priv->display.disable_fbc = g4x_disable_fbc;
8822
		} else if (IS_CRESTLINE(dev)) {
8823 8824 8825 8826
			dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
			dev_priv->display.enable_fbc = i8xx_enable_fbc;
			dev_priv->display.disable_fbc = i8xx_disable_fbc;
		}
8827
		/* 855GM needs testing */
8828 8829 8830
	}

	/* Returns the core display clock speed */
8831
	if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8832 8833 8834 8835 8836
		dev_priv->display.get_display_clock_speed =
			i945_get_display_clock_speed;
	else if (IS_I915G(dev))
		dev_priv->display.get_display_clock_speed =
			i915_get_display_clock_speed;
8837
	else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8838 8839 8840 8841 8842 8843 8844 8845
		dev_priv->display.get_display_clock_speed =
			i9xx_misc_get_display_clock_speed;
	else if (IS_I915GM(dev))
		dev_priv->display.get_display_clock_speed =
			i915gm_get_display_clock_speed;
	else if (IS_I865G(dev))
		dev_priv->display.get_display_clock_speed =
			i865_get_display_clock_speed;
8846
	else if (IS_I85X(dev))
8847 8848 8849 8850 8851 8852 8853
		dev_priv->display.get_display_clock_speed =
			i855_get_display_clock_speed;
	else /* 852, 830 */
		dev_priv->display.get_display_clock_speed =
			i830_get_display_clock_speed;

	/* For FIFO watermark updates */
8854
	if (HAS_PCH_SPLIT(dev)) {
8855 8856 8857 8858 8859 8860 8861
		dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
		dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;

		/* IVB configs may use multi-threaded forcewake */
		if (IS_IVYBRIDGE(dev)) {
			u32	ecobus;

8862 8863 8864 8865 8866 8867
			/* A small trick here - if the bios hasn't configured MT forcewake,
			 * and if the device is in RC6, then force_wake_mt_get will not wake
			 * the device and the ECOBUS read will return zero. Which will be
			 * (correctly) interpreted by the test below as MT forcewake being
			 * disabled.
			 */
8868 8869
			mutex_lock(&dev->struct_mutex);
			__gen6_gt_force_wake_mt_get(dev_priv);
8870
			ecobus = I915_READ_NOTRACE(ECOBUS);
8871 8872 8873 8874 8875 8876 8877 8878 8879 8880 8881 8882
			__gen6_gt_force_wake_mt_put(dev_priv);
			mutex_unlock(&dev->struct_mutex);

			if (ecobus & FORCEWAKE_MT_ENABLE) {
				DRM_DEBUG_KMS("Using MT version of forcewake\n");
				dev_priv->display.force_wake_get =
					__gen6_gt_force_wake_mt_get;
				dev_priv->display.force_wake_put =
					__gen6_gt_force_wake_mt_put;
			}
		}

8883 8884 8885 8886 8887
		if (HAS_PCH_IBX(dev))
			dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
		else if (HAS_PCH_CPT(dev))
			dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;

8888
		if (IS_GEN5(dev)) {
8889 8890 8891 8892 8893 8894
			if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
				dev_priv->display.update_wm = ironlake_update_wm;
			else {
				DRM_DEBUG_KMS("Failed to get proper latency. "
					      "Disable CxSR\n");
				dev_priv->display.update_wm = NULL;
8895
			}
8896
			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8897
			dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8898
			dev_priv->display.write_eld = ironlake_write_eld;
8899 8900 8901
		} else if (IS_GEN6(dev)) {
			if (SNB_READ_WM0_LATENCY()) {
				dev_priv->display.update_wm = sandybridge_update_wm;
8902
				dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8903 8904 8905 8906
			} else {
				DRM_DEBUG_KMS("Failed to read display plane latency. "
					      "Disable CxSR\n");
				dev_priv->display.update_wm = NULL;
8907
			}
8908
			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8909
			dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8910
			dev_priv->display.write_eld = ironlake_write_eld;
8911 8912 8913
		} else if (IS_IVYBRIDGE(dev)) {
			/* FIXME: detect B0+ stepping and use auto training */
			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8914 8915
			if (SNB_READ_WM0_LATENCY()) {
				dev_priv->display.update_wm = sandybridge_update_wm;
8916
				dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8917 8918 8919 8920 8921
			} else {
				DRM_DEBUG_KMS("Failed to read display plane latency. "
					      "Disable CxSR\n");
				dev_priv->display.update_wm = NULL;
			}
8922
			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8923
			dev_priv->display.write_eld = ironlake_write_eld;
8924 8925 8926
		} else
			dev_priv->display.update_wm = NULL;
	} else if (IS_PINEVIEW(dev)) {
8927
		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8928
					    dev_priv->is_ddr3,
8929 8930 8931
					    dev_priv->fsb_freq,
					    dev_priv->mem_freq)) {
			DRM_INFO("failed to find known CxSR latency "
8932
				 "(found ddr%s fsb freq %d, mem freq %d), "
8933
				 "disabling CxSR\n",
8934
				 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8935 8936 8937 8938 8939 8940
				 dev_priv->fsb_freq, dev_priv->mem_freq);
			/* Disable CxSR and never update its watermark again */
			pineview_disable_cxsr(dev);
			dev_priv->display.update_wm = NULL;
		} else
			dev_priv->display.update_wm = pineview_update_wm;
8941
		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8942
	} else if (IS_G4X(dev)) {
8943
		dev_priv->display.write_eld = g4x_write_eld;
8944
		dev_priv->display.update_wm = g4x_update_wm;
8945 8946
		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
	} else if (IS_GEN4(dev)) {
8947
		dev_priv->display.update_wm = i965_update_wm;
8948 8949 8950 8951 8952
		if (IS_CRESTLINE(dev))
			dev_priv->display.init_clock_gating = crestline_init_clock_gating;
		else if (IS_BROADWATER(dev))
			dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
	} else if (IS_GEN3(dev)) {
8953 8954
		dev_priv->display.update_wm = i9xx_update_wm;
		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8955 8956 8957 8958 8959
		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
	} else if (IS_I865G(dev)) {
		dev_priv->display.update_wm = i830_update_wm;
		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
		dev_priv->display.get_fifo_size = i830_get_fifo_size;
8960 8961 8962
	} else if (IS_I85X(dev)) {
		dev_priv->display.update_wm = i9xx_update_wm;
		dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8963
		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8964
	} else {
8965
		dev_priv->display.update_wm = i830_update_wm;
8966
		dev_priv->display.init_clock_gating = i830_init_clock_gating;
8967
		if (IS_845G(dev))
8968 8969 8970 8971
			dev_priv->display.get_fifo_size = i845_get_fifo_size;
		else
			dev_priv->display.get_fifo_size = i830_get_fifo_size;
	}
8972 8973 8974 8975 8976 8977 8978 8979 8980 8981 8982 8983 8984 8985 8986 8987 8988 8989 8990 8991 8992

	/* Default just returns -ENODEV to indicate unsupported */
	dev_priv->display.queue_flip = intel_default_queue_flip;

	switch (INTEL_INFO(dev)->gen) {
	case 2:
		dev_priv->display.queue_flip = intel_gen2_queue_flip;
		break;

	case 3:
		dev_priv->display.queue_flip = intel_gen3_queue_flip;
		break;

	case 4:
	case 5:
		dev_priv->display.queue_flip = intel_gen4_queue_flip;
		break;

	case 6:
		dev_priv->display.queue_flip = intel_gen6_queue_flip;
		break;
8993 8994 8995
	case 7:
		dev_priv->display.queue_flip = intel_gen7_queue_flip;
		break;
8996
	}
8997 8998
}

8999 9000 9001 9002 9003
/*
 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
 * resume, or other times.  This quirk makes sure that's the case for
 * affected systems.
 */
9004
static void quirk_pipea_force(struct drm_device *dev)
9005 9006 9007 9008 9009 9010 9011
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	dev_priv->quirks |= QUIRK_PIPEA_FORCE;
	DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
}

9012 9013 9014 9015 9016 9017 9018 9019 9020
/*
 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
 */
static void quirk_ssc_force_disable(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
}

9021 9022 9023 9024 9025 9026 9027 9028 9029 9030 9031
struct intel_quirk {
	int device;
	int subsystem_vendor;
	int subsystem_device;
	void (*hook)(struct drm_device *dev);
};

struct intel_quirk intel_quirks[] = {
	/* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
	{ 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
	/* HP Mini needs pipe A force quirk (LP: #322104) */
9032
	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9033 9034 9035 9036 9037 9038 9039 9040 9041 9042 9043 9044 9045 9046 9047 9048

	/* Thinkpad R31 needs pipe A force quirk */
	{ 0x3577, 0x1014, 0x0505, quirk_pipea_force },
	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },

	/* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
	{ 0x3577,  0x1014, 0x0513, quirk_pipea_force },
	/* ThinkPad X40 needs pipe A force quirk */

	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },

	/* 855 & before need to leave pipe A & dpll A up */
	{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9049 9050 9051

	/* Lenovo U160 cannot use SSC on LVDS */
	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9052 9053 9054

	/* Sony Vaio Y cannot use SSC on LVDS */
	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
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};

static void intel_init_quirks(struct drm_device *dev)
{
	struct pci_dev *d = dev->pdev;
	int i;

	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		struct intel_quirk *q = &intel_quirks[i];

		if (d->device == q->device &&
		    (d->subsystem_vendor == q->subsystem_vendor ||
		     q->subsystem_vendor == PCI_ANY_ID) &&
		    (d->subsystem_device == q->subsystem_device ||
		     q->subsystem_device == PCI_ANY_ID))
			q->hook(dev);
	}
}

9074 9075 9076 9077 9078 9079 9080 9081 9082 9083 9084 9085 9086 9087 9088 9089 9090 9091 9092 9093 9094 9095 9096
/* Disable the VGA plane that we never use */
static void i915_disable_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u8 sr1;
	u32 vga_reg;

	if (HAS_PCH_SPLIT(dev))
		vga_reg = CPU_VGACNTRL;
	else
		vga_reg = VGACNTRL;

	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
	outb(1, VGA_SR_INDEX);
	sr1 = inb(VGA_SR_DATA);
	outb(sr1 | 1<<5, VGA_SR_DATA);
	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
	udelay(300);

	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
	POSTING_READ(vga_reg);
}

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void intel_modeset_init(struct drm_device *dev)
{
9099
	struct drm_i915_private *dev_priv = dev->dev_private;
9100
	int i, ret;
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	drm_mode_config_init(dev);

	dev->mode_config.min_width = 0;
	dev->mode_config.min_height = 0;

	dev->mode_config.funcs = (void *)&intel_mode_funcs;

9109 9110
	intel_init_quirks(dev);

9111 9112
	intel_init_display(dev);

9113 9114 9115 9116
	if (IS_GEN2(dev)) {
		dev->mode_config.max_width = 2048;
		dev->mode_config.max_height = 2048;
	} else if (IS_GEN3(dev)) {
9117 9118
		dev->mode_config.max_width = 4096;
		dev->mode_config.max_height = 4096;
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	} else {
9120 9121
		dev->mode_config.max_width = 8192;
		dev->mode_config.max_height = 8192;
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	}
9123
	dev->mode_config.fb_base = dev->agp->base;
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9125
	DRM_DEBUG_KMS("%d display pipe%s available.\n",
9126
		      dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
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9128
	for (i = 0; i < dev_priv->num_pipe; i++) {
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		intel_crtc_init(dev, i);
9130 9131 9132
		ret = intel_plane_init(dev, i);
		if (ret)
			DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
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	}

9135 9136
	/* Just disable it once at startup */
	i915_disable_vga(dev);
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	intel_setup_outputs(dev);
9138

9139
	intel_init_clock_gating(dev);
9140

9141
	if (IS_IRONLAKE_M(dev)) {
9142
		ironlake_enable_drps(dev);
9143 9144
		intel_init_emon(dev);
	}
9145

9146
	if (IS_GEN6(dev) || IS_GEN7(dev)) {
9147
		gen6_enable_rps(dev_priv);
9148 9149
		gen6_update_ring_freq(dev_priv);
	}
9150

9151 9152 9153
	INIT_WORK(&dev_priv->idle_work, intel_idle_update);
	setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
		    (unsigned long)dev);
9154 9155 9156 9157 9158 9159
}

void intel_modeset_gem_init(struct drm_device *dev)
{
	if (IS_IRONLAKE_M(dev))
		ironlake_enable_rc6(dev);
9160 9161

	intel_setup_overlay(dev);
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}

void intel_modeset_cleanup(struct drm_device *dev)
{
9166 9167 9168 9169
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	struct intel_crtc *intel_crtc;

9170
	drm_kms_helper_poll_fini(dev);
9171 9172
	mutex_lock(&dev->struct_mutex);

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	intel_unregister_dsm_handler();


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	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		/* Skip inactive CRTCs */
		if (!crtc->fb)
			continue;

		intel_crtc = to_intel_crtc(crtc);
9182
		intel_increase_pllclock(crtc);
9183 9184
	}

9185
	intel_disable_fbc(dev);
9186

9187 9188
	if (IS_IRONLAKE_M(dev))
		ironlake_disable_drps(dev);
9189
	if (IS_GEN6(dev) || IS_GEN7(dev))
9190
		gen6_disable_rps(dev);
9191

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	if (IS_IRONLAKE_M(dev))
		ironlake_disable_rc6(dev);
9194

9195 9196
	mutex_unlock(&dev->struct_mutex);

9197 9198 9199 9200
	/* Disable the irq before mode object teardown, for the irq might
	 * enqueue unpin/hotplug work. */
	drm_irq_uninstall(dev);
	cancel_work_sync(&dev_priv->hotplug_work);
9201
	cancel_work_sync(&dev_priv->rps_work);
9202

9203 9204 9205
	/* flush any delayed tasks or pending work */
	flush_scheduled_work();

9206 9207 9208 9209 9210 9211 9212 9213
	/* Shut off idle work before the crtcs get freed. */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		intel_crtc = to_intel_crtc(crtc);
		del_timer_sync(&intel_crtc->idle_timer);
	}
	del_timer_sync(&dev_priv->idle_timer);
	cancel_work_sync(&dev_priv->idle_work);

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	drm_mode_config_cleanup(dev);
}

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/*
 * Return which encoder is currently attached for connector.
 */
9220
struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
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{
9222 9223
	return &intel_attached_encoder(connector)->base;
}
9224

9225 9226 9227 9228 9229 9230
void intel_connector_attach_encoder(struct intel_connector *connector,
				    struct intel_encoder *encoder)
{
	connector->encoder = encoder;
	drm_mode_connector_attach_encoder(&connector->base,
					  &encoder->base);
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}
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/*
 * set vga decode state - true == enable VGA decode
 */
int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u16 gmch_ctrl;

	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
	if (state)
		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
	else
		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
	return 0;
}
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#ifdef CONFIG_DEBUG_FS
#include <linux/seq_file.h>

struct intel_display_error_state {
	struct intel_cursor_error_state {
		u32 control;
		u32 position;
		u32 base;
		u32 size;
	} cursor[2];

	struct intel_pipe_error_state {
		u32 conf;
		u32 source;

		u32 htotal;
		u32 hblank;
		u32 hsync;
		u32 vtotal;
		u32 vblank;
		u32 vsync;
	} pipe[2];

	struct intel_plane_error_state {
		u32 control;
		u32 stride;
		u32 size;
		u32 pos;
		u32 addr;
		u32 surface;
		u32 tile_offset;
	} plane[2];
};

struct intel_display_error_state *
intel_display_capture_error_state(struct drm_device *dev)
{
9287
	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct intel_display_error_state *error;
	int i;

	error = kmalloc(sizeof(*error), GFP_ATOMIC);
	if (error == NULL)
		return NULL;

	for (i = 0; i < 2; i++) {
		error->cursor[i].control = I915_READ(CURCNTR(i));
		error->cursor[i].position = I915_READ(CURPOS(i));
		error->cursor[i].base = I915_READ(CURBASE(i));

		error->plane[i].control = I915_READ(DSPCNTR(i));
		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
		error->plane[i].size = I915_READ(DSPSIZE(i));
9303
		error->plane[i].pos = I915_READ(DSPPOS(i));
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		error->plane[i].addr = I915_READ(DSPADDR(i));
		if (INTEL_INFO(dev)->gen >= 4) {
			error->plane[i].surface = I915_READ(DSPSURF(i));
			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		}

		error->pipe[i].conf = I915_READ(PIPECONF(i));
		error->pipe[i].source = I915_READ(PIPESRC(i));
		error->pipe[i].htotal = I915_READ(HTOTAL(i));
		error->pipe[i].hblank = I915_READ(HBLANK(i));
		error->pipe[i].hsync = I915_READ(HSYNC(i));
		error->pipe[i].vtotal = I915_READ(VTOTAL(i));
		error->pipe[i].vblank = I915_READ(VBLANK(i));
		error->pipe[i].vsync = I915_READ(VSYNC(i));
	}

	return error;
}

void
intel_display_print_error_state(struct seq_file *m,
				struct drm_device *dev,
				struct intel_display_error_state *error)
{
	int i;

	for (i = 0; i < 2; i++) {
		seq_printf(m, "Pipe [%d]:\n", i);
		seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
		seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
		seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
		seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
		seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
		seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
		seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
		seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);

		seq_printf(m, "Plane [%d]:\n", i);
		seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
		seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
		seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
		seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
		seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
		if (INTEL_INFO(dev)->gen >= 4) {
			seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
			seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
		}

		seq_printf(m, "Cursor [%d]:\n", i);
		seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
		seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
		seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
	}
}
#endif