intel_display.c 264.9 KB
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/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

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#include <linux/dmi.h>
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#include <linux/module.h>
#include <linux/input.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/vgaarb.h>
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#include <drm/drm_edid.h>
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include <drm/drm_dp_helper.h>
#include <drm/drm_crtc_helper.h>
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#include <linux/dma_remapping.h>
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bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
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static void intel_increase_pllclock(struct drm_crtc *crtc);
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static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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typedef struct {
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	int	min, max;
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} intel_range_t;

typedef struct {
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	int	dot_limit;
	int	p2_slow, p2_fast;
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} intel_p2_t;

#define INTEL_P2_NUM		      2
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typedef struct intel_limit intel_limit_t;
struct intel_limit {
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	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
	intel_p2_t	    p2;
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	/**
	 * find_pll() - Find the best values for the PLL
	 * @limit: limits for the PLL
	 * @crtc: current CRTC
	 * @target: target frequency in kHz
	 * @refclk: reference clock frequency in kHz
	 * @match_clock: if provided, @best_clock P divider must
	 *               match the P divider from @match_clock
	 *               used for LVDS downclocking
	 * @best_clock: best PLL values found
	 *
	 * Returns true on success, false on failure.
	 */
	bool (*find_pll)(const intel_limit_t *limit,
			 struct drm_crtc *crtc,
			 int target, int refclk,
			 intel_clock_t *match_clock,
			 intel_clock_t *best_clock);
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};
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/* FDI */
#define IRONLAKE_FDI_FREQ		2700000 /* in kHz for mode->clock */

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int
intel_pch_rawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	WARN_ON(!HAS_PCH_SPLIT(dev));

	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
}

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static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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		    int target, int refclk, intel_clock_t *match_clock,
		    intel_clock_t *best_clock);
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static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock);
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static bool
intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock);

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static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev)
{
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	if (IS_GEN5(dev)) {
		struct drm_i915_private *dev_priv = dev->dev_private;
		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
	} else
		return 27;
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}

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static const intel_limit_t intel_limits_i8xx_dvo = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 2, .max = 33 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 4, .p2_fast = 2 },
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	.find_pll = intel_find_best_PLL,
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};

static const intel_limit_t intel_limits_i8xx_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 1, .max = 6 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 14, .p2_fast = 7 },
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	.find_pll = intel_find_best_PLL,
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};
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static const intel_limit_t intel_limits_i9xx_sdvo = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
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	.m1 = { .min = 8, .max = 18 },
	.m2 = { .min = 3, .max = 7 },
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	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_find_best_PLL,
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};

static const intel_limit_t intel_limits_i9xx_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
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	.m1 = { .min = 8, .max = 18 },
	.m2 = { .min = 3, .max = 7 },
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	.p = { .min = 7, .max = 98 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 7 },
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	.find_pll = intel_find_best_PLL,
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};

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static const intel_limit_t intel_limits_g4x_sdvo = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 1, .max = 3},
	.p2 = { .dot_limit = 270000,
		.p2_slow = 10,
		.p2_fast = 10
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_hdmi = {
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	.dot = { .min = 22000, .max = 400000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 16, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8},
	.p2 = { .dot_limit = 165000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
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	.dot = { .min = 20000, .max = 115000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 14, .p2_fast = 14
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
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	.dot = { .min = 80000, .max = 224000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 14, .max = 42 },
	.p1 = { .min = 2, .max = 6 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 7, .p2_fast = 7
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

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static const intel_limit_t intel_limits_pineview_sdvo = {
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	.dot = { .min = 20000, .max = 400000},
	.vco = { .min = 1700000, .max = 3500000 },
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	/* Pineview's Ncounter is a ring counter */
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	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
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	/* Pineview only has one combined m divider, which we treat as m2. */
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	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_find_best_PLL,
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};

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static const intel_limit_t intel_limits_pineview_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1700000, .max = 3500000 },
	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 7, .max = 112 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_find_best_PLL,
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};

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/* Ironlake / Sandybridge
 *
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
 * the range value for them is (actual_value - 2).
 */
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static const intel_limit_t intel_limits_ironlake_dac = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 5 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_g4x_find_best_PLL,
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};

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static const intel_limit_t intel_limits_ironlake_single_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 118 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 56 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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	.find_pll = intel_g4x_find_best_PLL,
};

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/* LVDS 100mhz refclk limits. */
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static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 2 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
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	.p1 = { .min = 2, .max = 8 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 42 },
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	.p1 = { .min = 2, .max = 6 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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	.find_pll = intel_g4x_find_best_PLL,
};

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static const intel_limit_t intel_limits_vlv_dac = {
	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 4000000, .max = 6000000 },
	.n = { .min = 1, .max = 7 },
	.m = { .min = 22, .max = 450 }, /* guess */
	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
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	.p1 = { .min = 1, .max = 3 },
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	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
	.find_pll = intel_vlv_find_best_pll,
};

static const intel_limit_t intel_limits_vlv_hdmi = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 4000000, .max = 6000000 },
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	.n = { .min = 1, .max = 7 },
	.m = { .min = 60, .max = 300 }, /* guess */
	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 2, .max = 3 },
	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
	.find_pll = intel_vlv_find_best_pll,
};

static const intel_limit_t intel_limits_vlv_dp = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 4000000, .max = 6000000 },
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	.n = { .min = 1, .max = 7 },
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	.m = { .min = 22, .max = 450 },
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	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
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	.p1 = { .min = 1, .max = 3 },
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	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
	.find_pll = intel_vlv_find_best_pll,
};

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static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
						int refclk)
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{
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	struct drm_device *dev = crtc->dev;
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	const intel_limit_t *limit;
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	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		if (intel_is_dual_link_lvds(dev)) {
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			if (refclk == 100000)
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				limit = &intel_limits_ironlake_dual_lvds_100m;
			else
				limit = &intel_limits_ironlake_dual_lvds;
		} else {
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			if (refclk == 100000)
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				limit = &intel_limits_ironlake_single_lvds_100m;
			else
				limit = &intel_limits_ironlake_single_lvds;
		}
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	} else
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		limit = &intel_limits_ironlake_dac;
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	return limit;
}

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static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	const intel_limit_t *limit;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		if (intel_is_dual_link_lvds(dev))
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			limit = &intel_limits_g4x_dual_channel_lvds;
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		else
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			limit = &intel_limits_g4x_single_channel_lvds;
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	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
		   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
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		limit = &intel_limits_g4x_hdmi;
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	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
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		limit = &intel_limits_g4x_sdvo;
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	} else /* The option is for other outputs */
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		limit = &intel_limits_i9xx_sdvo;
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	return limit;
}

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static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
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{
	struct drm_device *dev = crtc->dev;
	const intel_limit_t *limit;

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	if (HAS_PCH_SPLIT(dev))
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		limit = intel_ironlake_limit(crtc, refclk);
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	else if (IS_G4X(dev)) {
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		limit = intel_g4x_limit(crtc);
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	} else if (IS_PINEVIEW(dev)) {
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		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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			limit = &intel_limits_pineview_lvds;
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		else
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			limit = &intel_limits_pineview_sdvo;
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	} else if (IS_VALLEYVIEW(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
			limit = &intel_limits_vlv_dac;
		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
			limit = &intel_limits_vlv_hdmi;
		else
			limit = &intel_limits_vlv_dp;
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	} else if (!IS_GEN2(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
			limit = &intel_limits_i9xx_lvds;
		else
			limit = &intel_limits_i9xx_sdvo;
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	} else {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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			limit = &intel_limits_i8xx_lvds;
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		else
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			limit = &intel_limits_i8xx_dvo;
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	}
	return limit;
}

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/* m1 is reserved as 0 in Pineview, n is a ring counter */
static void pineview_clock(int refclk, intel_clock_t *clock)
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{
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	clock->m = clock->m2 + 2;
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / clock->n;
	clock->dot = clock->vco / clock->p;
}

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static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
{
	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
}

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static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
{
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	if (IS_PINEVIEW(dev)) {
		pineview_clock(refclk, clock);
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		return;
	}
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	clock->m = i9xx_dpll_compute_m(clock);
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	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / (clock->n + 2);
	clock->dot = clock->vco / clock->p;
}

/**
 * Returns whether any output on the specified pipe is of the specified type
 */
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bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
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{
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	struct drm_device *dev = crtc->dev;
	struct intel_encoder *encoder;

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	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->type == type)
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			return true;

	return false;
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}

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#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
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/**
 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */

511 512 513
static bool intel_PLL_is_valid(struct drm_device *dev,
			       const intel_limit_t *limit,
			       const intel_clock_t *clock)
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{
	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
516
		INTELPllInvalid("p1 out of range\n");
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	if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
518
		INTELPllInvalid("p out of range\n");
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	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
520
		INTELPllInvalid("m2 out of range\n");
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	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
522
		INTELPllInvalid("m1 out of range\n");
523
	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
524
		INTELPllInvalid("m1 <= m2\n");
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	if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
526
		INTELPllInvalid("m out of range\n");
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	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
528
		INTELPllInvalid("n out of range\n");
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	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
530
		INTELPllInvalid("vco out of range\n");
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	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
	 * connector, etc., rather than just a single range.
	 */
	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
535
		INTELPllInvalid("dot out of range\n");
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	return true;
}

540 541
static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
542 543
		    int target, int refclk, intel_clock_t *match_clock,
		    intel_clock_t *best_clock)
544

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{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;
	int err = target;

550
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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		/*
552 553 554
		 * For LVDS just rely on its current settings for dual-channel.
		 * We haven't figured out how to reliably set up different
		 * single/dual channel state, if we even can.
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		 */
556
		if (intel_is_dual_link_lvds(dev))
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			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

567
	memset(best_clock, 0, sizeof(*best_clock));
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569 570 571 572
	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
	     clock.m1++) {
		for (clock.m2 = limit->m2.min;
		     clock.m2 <= limit->m2.max; clock.m2++) {
573 574
			/* m1 is always 0 in Pineview */
			if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
575 576 577 578 579
				break;
			for (clock.n = limit->n.min;
			     clock.n <= limit->n.max; clock.n++) {
				for (clock.p1 = limit->p1.min;
					clock.p1 <= limit->p1.max; clock.p1++) {
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					int this_err;

582
					intel_clock(dev, refclk, &clock);
583 584
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
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						continue;
586 587 588
					if (match_clock &&
					    clock.p != match_clock->p)
						continue;
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					this_err = abs(clock.dot - target);
					if (this_err < err) {
						*best_clock = clock;
						err = this_err;
					}
				}
			}
		}
	}

	return (err != target);
}

603 604
static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
605 606
			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock)
607 608 609 610 611
{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;
	int max_n;
	bool found;
612 613
	/* approximately equals target * 0.00585 */
	int err_most = (target >> 8) + (target >> 9);
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	found = false;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
617
		if (intel_is_dual_link_lvds(dev))
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			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

	memset(best_clock, 0, sizeof(*best_clock));
	max_n = limit->n.max;
630
	/* based on hardware requirement, prefer smaller n to precision */
631
	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
632
		/* based on hardware requirement, prefere larger m1,m2 */
633 634 635 636 637 638 639 640
		for (clock.m1 = limit->m1.max;
		     clock.m1 >= limit->m1.min; clock.m1--) {
			for (clock.m2 = limit->m2.max;
			     clock.m2 >= limit->m2.min; clock.m2--) {
				for (clock.p1 = limit->p1.max;
				     clock.p1 >= limit->p1.min; clock.p1--) {
					int this_err;

641
					intel_clock(dev, refclk, &clock);
642 643
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
644
						continue;
645 646

					this_err = abs(clock.dot - target);
647 648 649 650 651 652 653 654 655 656
					if (this_err < err_most) {
						*best_clock = clock;
						err_most = this_err;
						max_n = clock.n;
						found = true;
					}
				}
			}
		}
	}
657 658 659
	return found;
}

660 661 662 663 664 665 666 667 668 669 670
static bool
intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock)
{
	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
	u32 m, n, fastclk;
	u32 updrate, minupdate, fracbits, p;
	unsigned long bestppm, ppm, absppm;
	int dotclk, flag;

671
	flag = 0;
672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727
	dotclk = target * 1000;
	bestppm = 1000000;
	ppm = absppm = 0;
	fastclk = dotclk / (2*100);
	updrate = 0;
	minupdate = 19200;
	fracbits = 1;
	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
	bestm1 = bestm2 = bestp1 = bestp2 = 0;

	/* based on hardware requirement, prefer smaller n to precision */
	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
		updrate = refclk / n;
		for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
			for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
				if (p2 > 10)
					p2 = p2 - 1;
				p = p1 * p2;
				/* based on hardware requirement, prefer bigger m1,m2 values */
				for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
					m2 = (((2*(fastclk * p * n / m1 )) +
					       refclk) / (2*refclk));
					m = m1 * m2;
					vco = updrate * m;
					if (vco >= limit->vco.min && vco < limit->vco.max) {
						ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
						absppm = (ppm > 0) ? ppm : (-ppm);
						if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
							bestppm = 0;
							flag = 1;
						}
						if (absppm < bestppm - 10) {
							bestppm = absppm;
							flag = 1;
						}
						if (flag) {
							bestn = n;
							bestm1 = m1;
							bestm2 = m2;
							bestp1 = p1;
							bestp2 = p2;
							flag = 0;
						}
					}
				}
			}
		}
	}
	best_clock->n = bestn;
	best_clock->m1 = bestm1;
	best_clock->m2 = bestm2;
	best_clock->p1 = bestp1;
	best_clock->p2 = bestp2;

	return true;
}
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enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
					     enum pipe pipe)
{
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

735
	return intel_crtc->config.cpu_transcoder;
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}

738 739 740 741 742 743 744 745 746 747 748
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 frame, frame_reg = PIPEFRAME(pipe);

	frame = I915_READ(frame_reg);

	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		DRM_DEBUG_KMS("vblank wait timed out\n");
}

749 750 751 752 753 754 755 756 757
/**
 * intel_wait_for_vblank - wait for vblank on a given pipe
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * Wait for vblank to occur on a given pipe.  Needed for various bits of
 * mode setting code.
 */
void intel_wait_for_vblank(struct drm_device *dev, int pipe)
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{
759
	struct drm_i915_private *dev_priv = dev->dev_private;
760
	int pipestat_reg = PIPESTAT(pipe);
761

762 763 764 765 766
	if (INTEL_INFO(dev)->gen >= 5) {
		ironlake_wait_for_vblank(dev, pipe);
		return;
	}

767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782
	/* Clear existing vblank status. Note this will clear any other
	 * sticky status fields as well.
	 *
	 * This races with i915_driver_irq_handler() with the result
	 * that either function could miss a vblank event.  Here it is not
	 * fatal, as we will either wait upon the next vblank interrupt or
	 * timeout.  Generally speaking intel_wait_for_vblank() is only
	 * called during modeset at which time the GPU should be idle and
	 * should *not* be performing page flips and thus not waiting on
	 * vblanks...
	 * Currently, the result of us stealing a vblank from the irq
	 * handler is that a single frame will be skipped during swapbuffers.
	 */
	I915_WRITE(pipestat_reg,
		   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

783
	/* Wait for vblank interrupt bit to set */
784 785 786
	if (wait_for(I915_READ(pipestat_reg) &
		     PIPE_VBLANK_INTERRUPT_STATUS,
		     50))
787 788 789
		DRM_DEBUG_KMS("vblank wait timed out\n");
}

790 791
/*
 * intel_wait_for_pipe_off - wait for pipe to turn off
792 793 794 795 796 797 798
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * After disabling a pipe, we can't wait for vblank in the usual way,
 * spinning on the vblank interrupt status bit, since we won't actually
 * see an interrupt when the pipe is disabled.
 *
799 800 801 802 803 804
 * On Gen4 and above:
 *   wait for the pipe register state bit to turn off
 *
 * Otherwise:
 *   wait for the display line value to settle (it usually
 *   ends up stopping at the start of the next frame).
805
 *
806
 */
807
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
808 809
{
	struct drm_i915_private *dev_priv = dev->dev_private;
810 811
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
812 813

	if (INTEL_INFO(dev)->gen >= 4) {
814
		int reg = PIPECONF(cpu_transcoder);
815 816

		/* Wait for the Pipe State to go off */
817 818
		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
			     100))
819
			WARN(1, "pipe_off wait timed out\n");
820
	} else {
821
		u32 last_line, line_mask;
822
		int reg = PIPEDSL(pipe);
823 824
		unsigned long timeout = jiffies + msecs_to_jiffies(100);

825 826 827 828 829
		if (IS_GEN2(dev))
			line_mask = DSL_LINEMASK_GEN2;
		else
			line_mask = DSL_LINEMASK_GEN3;

830 831
		/* Wait for the display line to settle */
		do {
832
			last_line = I915_READ(reg) & line_mask;
833
			mdelay(5);
834
		} while (((I915_READ(reg) & line_mask) != last_line) &&
835 836
			 time_after(timeout, jiffies));
		if (time_after(jiffies, timeout))
837
			WARN(1, "pipe_off wait timed out\n");
838
	}
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839 840
}

841 842 843 844 845 846 847 848 849 850 851 852
/*
 * ibx_digital_port_connected - is the specified port connected?
 * @dev_priv: i915 private structure
 * @port: the port to test
 *
 * Returns true if @port is connected, false otherwise.
 */
bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
				struct intel_digital_port *port)
{
	u32 bit;

853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880
	if (HAS_PCH_IBX(dev_priv->dev)) {
		switch(port->port) {
		case PORT_B:
			bit = SDE_PORTB_HOTPLUG;
			break;
		case PORT_C:
			bit = SDE_PORTC_HOTPLUG;
			break;
		case PORT_D:
			bit = SDE_PORTD_HOTPLUG;
			break;
		default:
			return true;
		}
	} else {
		switch(port->port) {
		case PORT_B:
			bit = SDE_PORTB_HOTPLUG_CPT;
			break;
		case PORT_C:
			bit = SDE_PORTC_HOTPLUG_CPT;
			break;
		case PORT_D:
			bit = SDE_PORTD_HOTPLUG_CPT;
			break;
		default:
			return true;
		}
881 882 883 884 885
	}

	return I915_READ(SDEISR) & bit;
}

886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908
static const char *state_string(bool enabled)
{
	return enabled ? "on" : "off";
}

/* Only for pre-ILK configs */
static void assert_pll(struct drm_i915_private *dev_priv,
		       enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

	reg = DPLL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & DPLL_VCO_ENABLE);
	WARN(cur_state != state,
	     "PLL state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
#define assert_pll_disabled(d, p) assert_pll(d, p, false)

909 910
/* For ILK+ */
static void assert_pch_pll(struct drm_i915_private *dev_priv,
911 912 913
			   struct intel_pch_pll *pll,
			   struct intel_crtc *crtc,
			   bool state)
914 915 916 917
{
	u32 val;
	bool cur_state;

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	if (HAS_PCH_LPT(dev_priv->dev)) {
		DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		return;
	}

923 924
	if (WARN (!pll,
		  "asserting PCH PLL %s with no PLL\n", state_string(state)))
925 926
		return;

927 928 929 930 931 932 933 934
	val = I915_READ(pll->pll_reg);
	cur_state = !!(val & DPLL_VCO_ENABLE);
	WARN(cur_state != state,
	     "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
	     pll->pll_reg, state_string(state), state_string(cur_state), val);

	/* Make sure the selected PLL is correctly attached to the transcoder */
	if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
935 936 937
		u32 pch_dpll;

		pch_dpll = I915_READ(PCH_DPLL_SEL);
938 939
		cur_state = pll->pll_reg == _PCH_DPLL_B;
		if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
940 941
			  "PLL[%d] not attached to this transcoder %c: %08x\n",
			  cur_state, pipe_name(crtc->pipe), pch_dpll)) {
942 943
			cur_state = !!(val >> (4*crtc->pipe + 3));
			WARN(cur_state != state,
944
			     "PLL[%d] not %s on this transcoder %c: %08x\n",
945 946
			     pll->pll_reg == _PCH_DPLL_B,
			     state_string(state),
947
			     pipe_name(crtc->pipe),
948 949
			     val);
		}
950
	}
951
}
952 953
#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
954 955 956 957 958 959 960

static void assert_fdi_tx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;
961 962
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
963

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	if (HAS_DDI(dev_priv->dev)) {
		/* DDI does not have a specific FDI_TX register */
966
		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
967
		val = I915_READ(reg);
968
		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
969 970 971 972 973
	} else {
		reg = FDI_TX_CTL(pipe);
		val = I915_READ(reg);
		cur_state = !!(val & FDI_TX_ENABLE);
	}
974 975 976 977 978 979 980 981 982 983 984 985 986 987
	WARN(cur_state != state,
	     "FDI TX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)

static void assert_fdi_rx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

988 989 990
	reg = FDI_RX_CTL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & FDI_RX_ENABLE);
991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007
	WARN(cur_state != state,
	     "FDI RX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)

static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

	/* ILK FDI PLL is always enabled */
	if (dev_priv->info->gen == 5)
		return;

1008
	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
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	if (HAS_DDI(dev_priv->dev))
1010 1011
		return;

1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027
	reg = FDI_TX_CTL(pipe);
	val = I915_READ(reg);
	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
}

static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

	reg = FDI_RX_CTL(pipe);
	val = I915_READ(reg);
	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
}

1028 1029 1030 1031 1032 1033
static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
				  enum pipe pipe)
{
	int pp_reg, lvds_reg;
	u32 val;
	enum pipe panel_pipe = PIPE_A;
1034
	bool locked = true;
1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053

	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		pp_reg = PCH_PP_CONTROL;
		lvds_reg = PCH_LVDS;
	} else {
		pp_reg = PP_CONTROL;
		lvds_reg = LVDS;
	}

	val = I915_READ(pp_reg);
	if (!(val & PANEL_POWER_ON) ||
	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		locked = false;

	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		panel_pipe = PIPE_B;

	WARN(panel_pipe == pipe && locked,
	     "panel assertion failure, pipe %c regs locked\n",
1054
	     pipe_name(pipe));
1055 1056
}

1057 1058
void assert_pipe(struct drm_i915_private *dev_priv,
		 enum pipe pipe, bool state)
1059 1060 1061
{
	int reg;
	u32 val;
1062
	bool cur_state;
1063 1064
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
1065

1066 1067 1068 1069
	/* if we need the pipe A quirk it must be always on */
	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		state = true;

1070 1071
	if (!intel_display_power_enabled(dev_priv->dev,
				POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1072 1073 1074 1075 1076 1077 1078
		cur_state = false;
	} else {
		reg = PIPECONF(cpu_transcoder);
		val = I915_READ(reg);
		cur_state = !!(val & PIPECONF_ENABLE);
	}

1079 1080
	WARN(cur_state != state,
	     "pipe %c assertion failure (expected %s, current %s)\n",
1081
	     pipe_name(pipe), state_string(state), state_string(cur_state));
1082 1083
}

1084 1085
static void assert_plane(struct drm_i915_private *dev_priv,
			 enum plane plane, bool state)
1086 1087 1088
{
	int reg;
	u32 val;
1089
	bool cur_state;
1090 1091 1092

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1093 1094 1095 1096
	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
	WARN(cur_state != state,
	     "plane %c assertion failure (expected %s, current %s)\n",
	     plane_name(plane), state_string(state), state_string(cur_state));
1097 1098
}

1099 1100 1101
#define assert_plane_enabled(d, p) assert_plane(d, p, true)
#define assert_plane_disabled(d, p) assert_plane(d, p, false)

1102 1103 1104 1105 1106 1107 1108
static void assert_planes_disabled(struct drm_i915_private *dev_priv,
				   enum pipe pipe)
{
	int reg, i;
	u32 val;
	int cur_pipe;

1109
	/* Planes are fixed to pipes on ILK+ */
1110
	if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1111 1112 1113 1114 1115
		reg = DSPCNTR(pipe);
		val = I915_READ(reg);
		WARN((val & DISPLAY_PLANE_ENABLE),
		     "plane %c assertion failure, should be disabled but not\n",
		     plane_name(pipe));
1116
		return;
1117
	}
1118

1119 1120 1121 1122 1123 1124 1125
	/* Need to check both planes against the pipe */
	for (i = 0; i < 2; i++) {
		reg = DSPCNTR(i);
		val = I915_READ(reg);
		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
			DISPPLANE_SEL_PIPE_SHIFT;
		WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1126 1127
		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
		     plane_name(i), pipe_name(pipe));
1128 1129 1130
	}
}

1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144
static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
				    enum pipe pipe)
{
	int reg, i;
	u32 val;

	if (!IS_VALLEYVIEW(dev_priv->dev))
		return;

	/* Need to check both planes against the pipe */
	for (i = 0; i < dev_priv->num_plane; i++) {
		reg = SPCNTR(pipe, i);
		val = I915_READ(reg);
		WARN((val & SP_ENABLE),
1145 1146
		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
		     sprite_name(pipe, i), pipe_name(pipe));
1147 1148 1149
	}
}

1150 1151 1152 1153 1154
static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
{
	u32 val;
	bool enabled;

E
Eugeni Dodonov 已提交
1155 1156 1157 1158 1159
	if (HAS_PCH_LPT(dev_priv->dev)) {
		DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		return;
	}

1160 1161 1162 1163 1164 1165
	val = I915_READ(PCH_DREF_CONTROL);
	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
			    DREF_SUPERSPREAD_SOURCE_MASK));
	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
}

1166 1167
static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
					   enum pipe pipe)
1168 1169 1170 1171 1172
{
	int reg;
	u32 val;
	bool enabled;

1173
	reg = PCH_TRANSCONF(pipe);
1174 1175
	val = I915_READ(reg);
	enabled = !!(val & TRANS_ENABLE);
1176 1177 1178
	WARN(enabled,
	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
	     pipe_name(pipe));
1179 1180
}

1181 1182
static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
			    enum pipe pipe, u32 port_sel, u32 val)
1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198
{
	if ((val & DP_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
			return false;
	} else {
		if ((val & DP_PIPE_MASK) != (pipe << 30))
			return false;
	}
	return true;
}

1199 1200 1201
static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
1202
	if ((val & SDVO_ENABLE) == 0)
1203 1204 1205
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
1206
		if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1207 1208
			return false;
	} else {
1209
		if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245
			return false;
	}
	return true;
}

static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & LVDS_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
			return false;
	}
	return true;
}

static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & ADPA_DAC_ENABLE) == 0)
		return false;
	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
			return false;
	}
	return true;
}

1246
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1247
				   enum pipe pipe, int reg, u32 port_sel)
1248
{
1249
	u32 val = I915_READ(reg);
1250
	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1251
	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1252
	     reg, pipe_name(pipe));
1253

1254 1255
	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
	     && (val & DP_PIPEB_SELECT),
1256
	     "IBX PCH dp port still using transcoder B\n");
1257 1258 1259 1260 1261
}

static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
				     enum pipe pipe, int reg)
{
1262
	u32 val = I915_READ(reg);
1263
	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1264
	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1265
	     reg, pipe_name(pipe));
1266

1267
	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1268
	     && (val & SDVO_PIPE_B_SELECT),
1269
	     "IBX PCH hdmi port still using transcoder B\n");
1270 1271 1272 1273 1274 1275 1276 1277
}

static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

1278 1279 1280
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1281 1282 1283

	reg = PCH_ADPA;
	val = I915_READ(reg);
1284
	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1285
	     "PCH VGA enabled on transcoder %c, should be disabled\n",
1286
	     pipe_name(pipe));
1287 1288 1289

	reg = PCH_LVDS;
	val = I915_READ(reg);
1290
	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1291
	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
1292
	     pipe_name(pipe));
1293

1294 1295 1296
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1297 1298
}

1299 1300 1301 1302 1303 1304 1305 1306 1307 1308
/**
 * intel_enable_pll - enable a PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
 * make sure the PLL reg is writable first though, since the panel write
 * protect mechanism may be enabled.
 *
 * Note!  This is for pre-ILK only.
1309 1310
 *
 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1311 1312 1313 1314 1315 1316
 */
static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
	int reg;
	u32 val;

1317 1318
	assert_pipe_disabled(dev_priv, pipe);

1319
	/* No really, not for ILK+ */
1320
	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369

	/* PLL is protected by panel, make sure we can write it */
	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
		assert_panel_unlocked(dev_priv, pipe);

	reg = DPLL(pipe);
	val = I915_READ(reg);
	val |= DPLL_VCO_ENABLE;

	/* We do this three times for luck */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
}

/**
 * intel_disable_pll - disable a PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to disable
 *
 * Disable the PLL for @pipe, making sure the pipe is off first.
 *
 * Note!  This is for pre-ILK only.
 */
static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
	int reg;
	u32 val;

	/* Don't disable pipe A or pipe A PLLs if needed */
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		return;

	/* Make sure the pipe isn't still relying on us */
	assert_pipe_disabled(dev_priv, pipe);

	reg = DPLL(pipe);
	val = I915_READ(reg);
	val &= ~DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
}

1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383
void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
{
	u32 port_mask;

	if (!port)
		port_mask = DPLL_PORTB_READY_MASK;
	else
		port_mask = DPLL_PORTC_READY_MASK;

	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
		WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
		     'B' + port, I915_READ(DPLL(0)));
}

1384
/**
1385
 * ironlake_enable_pch_pll - enable PCH PLL
1386 1387 1388 1389 1390 1391
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * The PCH PLL needs to be enabled before the PCH transcoder, since it
 * drives the transcoder clock.
 */
1392
static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1393
{
1394
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1395
	struct intel_pch_pll *pll;
1396 1397 1398
	int reg;
	u32 val;

1399
	/* PCH PLLs only available on ILK, SNB and IVB */
1400
	BUG_ON(dev_priv->info->gen < 5);
1401 1402 1403 1404 1405 1406
	pll = intel_crtc->pch_pll;
	if (pll == NULL)
		return;

	if (WARN_ON(pll->refcount == 0))
		return;
1407 1408 1409 1410

	DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
		      pll->pll_reg, pll->active, pll->on,
		      intel_crtc->base.base.id);
1411 1412 1413 1414

	/* PCH refclock must be enabled first */
	assert_pch_refclk_enabled(dev_priv);

1415
	if (pll->active++ && pll->on) {
1416
		assert_pch_pll_enabled(dev_priv, pll, NULL);
1417 1418 1419 1420 1421 1422
		return;
	}

	DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);

	reg = pll->pll_reg;
1423 1424 1425 1426 1427
	val = I915_READ(reg);
	val |= DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(200);
1428 1429

	pll->on = true;
1430 1431
}

1432
static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1433
{
1434 1435
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
	struct intel_pch_pll *pll = intel_crtc->pch_pll;
1436
	int reg;
1437
	u32 val;
1438

1439 1440
	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);
1441 1442
	if (pll == NULL)
	       return;
1443

1444 1445
	if (WARN_ON(pll->refcount == 0))
		return;
1446

1447 1448 1449
	DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
		      pll->pll_reg, pll->active, pll->on,
		      intel_crtc->base.base.id);
1450

1451
	if (WARN_ON(pll->active == 0)) {
1452
		assert_pch_pll_disabled(dev_priv, pll, NULL);
1453 1454 1455
		return;
	}

1456
	if (--pll->active) {
1457
		assert_pch_pll_enabled(dev_priv, pll, NULL);
1458
		return;
1459 1460 1461 1462 1463
	}

	DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);

	/* Make sure transcoder isn't still depending on us */
1464
	assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1465

1466
	reg = pll->pll_reg;
1467 1468 1469 1470 1471
	val = I915_READ(reg);
	val &= ~DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(200);
1472 1473

	pll->on = false;
1474 1475
}

1476 1477
static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
					   enum pipe pipe)
1478
{
1479
	struct drm_device *dev = dev_priv->dev;
1480
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1481
	uint32_t reg, val, pipeconf_val;
1482 1483 1484 1485 1486

	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);

	/* Make sure PCH DPLL is enabled */
1487 1488 1489
	assert_pch_pll_enabled(dev_priv,
			       to_intel_crtc(crtc)->pch_pll,
			       to_intel_crtc(crtc));
1490 1491 1492 1493 1494

	/* FDI must be feeding us bits for PCH ports */
	assert_fdi_tx_enabled(dev_priv, pipe);
	assert_fdi_rx_enabled(dev_priv, pipe);

1495 1496 1497 1498 1499 1500 1501
	if (HAS_PCH_CPT(dev)) {
		/* Workaround: Set the timing override bit before enabling the
		 * pch transcoder. */
		reg = TRANS_CHICKEN2(pipe);
		val = I915_READ(reg);
		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
		I915_WRITE(reg, val);
1502
	}
1503

1504
	reg = PCH_TRANSCONF(pipe);
1505
	val = I915_READ(reg);
1506
	pipeconf_val = I915_READ(PIPECONF(pipe));
1507 1508 1509 1510 1511 1512

	if (HAS_PCH_IBX(dev_priv->dev)) {
		/*
		 * make the BPC in transcoder be consistent with
		 * that in pipeconf reg.
		 */
1513 1514
		val &= ~PIPECONF_BPC_MASK;
		val |= pipeconf_val & PIPECONF_BPC_MASK;
1515
	}
1516 1517 1518

	val &= ~TRANS_INTERLACE_MASK;
	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1519 1520 1521 1522 1523
		if (HAS_PCH_IBX(dev_priv->dev) &&
		    intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
			val |= TRANS_LEGACY_INTERLACED_ILK;
		else
			val |= TRANS_INTERLACED;
1524 1525 1526
	else
		val |= TRANS_PROGRESSIVE;

1527 1528
	I915_WRITE(reg, val | TRANS_ENABLE);
	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1529
		DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1530 1531
}

1532
static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1533
				      enum transcoder cpu_transcoder)
1534
{
1535 1536 1537 1538 1539 1540
	u32 val, pipeconf_val;

	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);

	/* FDI must be feeding us bits for PCH ports */
D
Daniel Vetter 已提交
1541
	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1542
	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1543

1544 1545
	/* Workaround: set timing override bit. */
	val = I915_READ(_TRANSA_CHICKEN2);
1546
	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1547 1548
	I915_WRITE(_TRANSA_CHICKEN2, val);

1549
	val = TRANS_ENABLE;
1550
	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1551

1552 1553
	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
	    PIPECONF_INTERLACED_ILK)
1554
		val |= TRANS_INTERLACED;
1555 1556 1557
	else
		val |= TRANS_PROGRESSIVE;

1558 1559
	I915_WRITE(LPT_TRANSCONF, val);
	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1560
		DRM_ERROR("Failed to enable PCH transcoder\n");
1561 1562
}

1563 1564
static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
					    enum pipe pipe)
1565
{
1566 1567
	struct drm_device *dev = dev_priv->dev;
	uint32_t reg, val;
1568 1569 1570 1571 1572

	/* FDI relies on the transcoder */
	assert_fdi_tx_disabled(dev_priv, pipe);
	assert_fdi_rx_disabled(dev_priv, pipe);

1573 1574 1575
	/* Ports must be off as well */
	assert_pch_ports_disabled(dev_priv, pipe);

1576
	reg = PCH_TRANSCONF(pipe);
1577 1578 1579 1580 1581
	val = I915_READ(reg);
	val &= ~TRANS_ENABLE;
	I915_WRITE(reg, val);
	/* wait for PCH transcoder off, transcoder state */
	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1582
		DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1583 1584 1585 1586 1587 1588 1589 1590

	if (!HAS_PCH_IBX(dev)) {
		/* Workaround: Clear the timing override chicken bit again. */
		reg = TRANS_CHICKEN2(pipe);
		val = I915_READ(reg);
		val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
		I915_WRITE(reg, val);
	}
1591 1592
}

1593
static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1594 1595 1596
{
	u32 val;

1597
	val = I915_READ(LPT_TRANSCONF);
1598
	val &= ~TRANS_ENABLE;
1599
	I915_WRITE(LPT_TRANSCONF, val);
1600
	/* wait for PCH transcoder off, transcoder state */
1601
	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1602
		DRM_ERROR("Failed to disable PCH transcoder\n");
1603 1604 1605

	/* Workaround: clear timing override bit. */
	val = I915_READ(_TRANSA_CHICKEN2);
1606
	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1607
	I915_WRITE(_TRANSA_CHICKEN2, val);
1608 1609
}

1610
/**
1611
 * intel_enable_pipe - enable a pipe, asserting requirements
1612 1613
 * @dev_priv: i915 private structure
 * @pipe: pipe to enable
1614
 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1615 1616 1617 1618 1619 1620 1621 1622 1623
 *
 * Enable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe is actually running (i.e. first vblank) before
 * returning.
 */
1624 1625
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
			      bool pch_port)
1626
{
1627 1628
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
D
Daniel Vetter 已提交
1629
	enum pipe pch_transcoder;
1630 1631 1632
	int reg;
	u32 val;

1633 1634 1635
	assert_planes_disabled(dev_priv, pipe);
	assert_sprites_disabled(dev_priv, pipe);

1636
	if (HAS_PCH_LPT(dev_priv->dev))
1637 1638 1639 1640
		pch_transcoder = TRANSCODER_A;
	else
		pch_transcoder = pipe;

1641 1642 1643 1644 1645 1646 1647
	/*
	 * A pipe without a PLL won't actually be able to drive bits from
	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
	 * need the check.
	 */
	if (!HAS_PCH_SPLIT(dev_priv->dev))
		assert_pll_enabled(dev_priv, pipe);
1648 1649 1650
	else {
		if (pch_port) {
			/* if driving the PCH, we need FDI enabled */
1651
			assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
D
Daniel Vetter 已提交
1652 1653
			assert_fdi_tx_pll_enabled(dev_priv,
						  (enum pipe) cpu_transcoder);
1654 1655 1656
		}
		/* FIXME: assert CPU port conditions for SNB+ */
	}
1657

1658
	reg = PIPECONF(cpu_transcoder);
1659
	val = I915_READ(reg);
1660 1661 1662 1663
	if (val & PIPECONF_ENABLE)
		return;

	I915_WRITE(reg, val | PIPECONF_ENABLE);
1664 1665 1666 1667
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
1668
 * intel_disable_pipe - disable a pipe, asserting requirements
1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681
 * @dev_priv: i915 private structure
 * @pipe: pipe to disable
 *
 * Disable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe has shut down before returning.
 */
static void intel_disable_pipe(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
1682 1683
	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
1684 1685 1686 1687 1688 1689 1690 1691
	int reg;
	u32 val;

	/*
	 * Make sure planes won't keep trying to pump pixels to us,
	 * or we might hang the display.
	 */
	assert_planes_disabled(dev_priv, pipe);
1692
	assert_sprites_disabled(dev_priv, pipe);
1693 1694 1695 1696 1697

	/* Don't disable pipe A or pipe A PLLs if needed */
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		return;

1698
	reg = PIPECONF(cpu_transcoder);
1699
	val = I915_READ(reg);
1700 1701 1702 1703
	if ((val & PIPECONF_ENABLE) == 0)
		return;

	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1704 1705 1706
	intel_wait_for_pipe_off(dev_priv->dev, pipe);
}

1707 1708 1709 1710
/*
 * Plane regs are double buffered, going from enabled->disabled needs a
 * trigger in order to latch.  The display address reg provides this.
 */
1711
void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1712 1713
				      enum plane plane)
{
1714 1715 1716 1717
	if (dev_priv->info->gen >= 4)
		I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
	else
		I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1718 1719
}

1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738
/**
 * intel_enable_plane - enable a display plane on a given pipe
 * @dev_priv: i915 private structure
 * @plane: plane to enable
 * @pipe: pipe being fed
 *
 * Enable @plane on @pipe, making sure that @pipe is running first.
 */
static void intel_enable_plane(struct drm_i915_private *dev_priv,
			       enum plane plane, enum pipe pipe)
{
	int reg;
	u32 val;

	/* If the pipe isn't enabled, we can't pump pixels and may hang */
	assert_pipe_enabled(dev_priv, pipe);

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1739 1740 1741 1742
	if (val & DISPLAY_PLANE_ENABLE)
		return;

	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1743
	intel_flush_display_plane(dev_priv, plane);
1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
 * intel_disable_plane - disable a display plane
 * @dev_priv: i915 private structure
 * @plane: plane to disable
 * @pipe: pipe consuming the data
 *
 * Disable @plane; should be an independent operation.
 */
static void intel_disable_plane(struct drm_i915_private *dev_priv,
				enum plane plane, enum pipe pipe)
{
	int reg;
	u32 val;

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1763 1764 1765 1766
	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		return;

	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1767 1768 1769 1770
	intel_flush_display_plane(dev_priv, plane);
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

1771 1772 1773 1774 1775 1776 1777 1778 1779
static bool need_vtd_wa(struct drm_device *dev)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

1780
int
1781
intel_pin_and_fence_fb_obj(struct drm_device *dev,
1782
			   struct drm_i915_gem_object *obj,
1783
			   struct intel_ring_buffer *pipelined)
1784
{
1785
	struct drm_i915_private *dev_priv = dev->dev_private;
1786 1787 1788
	u32 alignment;
	int ret;

1789
	switch (obj->tiling_mode) {
1790
	case I915_TILING_NONE:
1791 1792
		if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
			alignment = 128 * 1024;
1793
		else if (INTEL_INFO(dev)->gen >= 4)
1794 1795 1796
			alignment = 4 * 1024;
		else
			alignment = 64 * 1024;
1797 1798 1799 1800 1801 1802
		break;
	case I915_TILING_X:
		/* pin() will align the object as required by fence */
		alignment = 0;
		break;
	case I915_TILING_Y:
1803 1804 1805 1806
		/* Despite that we check this in framebuffer_init userspace can
		 * screw us over and change the tiling after the fact. Only
		 * pinned buffers can't change their tiling. */
		DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1807 1808 1809 1810 1811
		return -EINVAL;
	default:
		BUG();
	}

1812 1813 1814 1815 1816 1817 1818 1819
	/* Note that the w/a also requires 64 PTE of padding following the
	 * bo. We currently fill all unused PTE with the shadow page and so
	 * we should always have valid PTE following the scanout preventing
	 * the VT-d warning.
	 */
	if (need_vtd_wa(dev) && alignment < 256 * 1024)
		alignment = 256 * 1024;

1820
	dev_priv->mm.interruptible = false;
1821
	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1822
	if (ret)
1823
		goto err_interruptible;
1824 1825 1826 1827 1828 1829

	/* Install a fence for tiled scan-out. Pre-i965 always needs a
	 * fence, whereas 965+ only requires a fence if using
	 * framebuffer compression.  For simplicity, we always install
	 * a fence as the cost is not that onerous.
	 */
1830
	ret = i915_gem_object_get_fence(obj);
1831 1832
	if (ret)
		goto err_unpin;
1833

1834
	i915_gem_object_pin_fence(obj);
1835

1836
	dev_priv->mm.interruptible = true;
1837
	return 0;
1838 1839 1840

err_unpin:
	i915_gem_object_unpin(obj);
1841 1842
err_interruptible:
	dev_priv->mm.interruptible = true;
1843
	return ret;
1844 1845
}

1846 1847 1848 1849 1850 1851
void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_fence(obj);
	i915_gem_object_unpin(obj);
}

1852 1853
/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
 * is assumed to be a power-of-two. */
1854 1855 1856 1857
unsigned long intel_gen4_compute_page_offset(int *x, int *y,
					     unsigned int tiling_mode,
					     unsigned int cpp,
					     unsigned int pitch)
1858
{
1859 1860
	if (tiling_mode != I915_TILING_NONE) {
		unsigned int tile_rows, tiles;
1861

1862 1863
		tile_rows = *y / 8;
		*y %= 8;
1864

1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876
		tiles = *x / (512/cpp);
		*x %= 512/cpp;

		return tile_rows * pitch * 8 + tiles * 4096;
	} else {
		unsigned int offset;

		offset = *y * pitch + *x * cpp;
		*y = 0;
		*x = (offset & 4095) / cpp;
		return offset & -4096;
	}
1877 1878
}

1879 1880
static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			     int x, int y)
J
Jesse Barnes 已提交
1881 1882 1883 1884 1885
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_framebuffer *intel_fb;
1886
	struct drm_i915_gem_object *obj;
J
Jesse Barnes 已提交
1887
	int plane = intel_crtc->plane;
1888
	unsigned long linear_offset;
J
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1889
	u32 dspcntr;
1890
	u32 reg;
J
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1891 1892 1893 1894 1895 1896

	switch (plane) {
	case 0:
	case 1:
		break;
	default:
1897
		DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
J
Jesse Barnes 已提交
1898 1899 1900 1901 1902 1903
		return -EINVAL;
	}

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

1904 1905
	reg = DSPCNTR(plane);
	dspcntr = I915_READ(reg);
J
Jesse Barnes 已提交
1906 1907
	/* Mask out pixel format bits in case we change it */
	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1908 1909
	switch (fb->pixel_format) {
	case DRM_FORMAT_C8:
J
Jesse Barnes 已提交
1910 1911
		dspcntr |= DISPPLANE_8BPP;
		break;
1912 1913 1914
	case DRM_FORMAT_XRGB1555:
	case DRM_FORMAT_ARGB1555:
		dspcntr |= DISPPLANE_BGRX555;
J
Jesse Barnes 已提交
1915
		break;
1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933
	case DRM_FORMAT_RGB565:
		dspcntr |= DISPPLANE_BGRX565;
		break;
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
		dspcntr |= DISPPLANE_BGRX888;
		break;
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
		dspcntr |= DISPPLANE_RGBX888;
		break;
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
		dspcntr |= DISPPLANE_BGRX101010;
		break;
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
		dspcntr |= DISPPLANE_RGBX101010;
J
Jesse Barnes 已提交
1934 1935
		break;
	default:
1936
		BUG();
J
Jesse Barnes 已提交
1937
	}
1938

1939
	if (INTEL_INFO(dev)->gen >= 4) {
1940
		if (obj->tiling_mode != I915_TILING_NONE)
J
Jesse Barnes 已提交
1941 1942 1943 1944 1945
			dspcntr |= DISPPLANE_TILED;
		else
			dspcntr &= ~DISPPLANE_TILED;
	}

1946
	I915_WRITE(reg, dspcntr);
J
Jesse Barnes 已提交
1947

1948
	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
J
Jesse Barnes 已提交
1949

1950 1951
	if (INTEL_INFO(dev)->gen >= 4) {
		intel_crtc->dspaddr_offset =
1952 1953 1954
			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
						       fb->bits_per_pixel / 8,
						       fb->pitches[0]);
1955 1956
		linear_offset -= intel_crtc->dspaddr_offset;
	} else {
1957
		intel_crtc->dspaddr_offset = linear_offset;
1958
	}
1959 1960 1961

	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		      obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1962
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1963
	if (INTEL_INFO(dev)->gen >= 4) {
1964 1965
		I915_MODIFY_DISPBASE(DSPSURF(plane),
				     obj->gtt_offset + intel_crtc->dspaddr_offset);
1966
		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1967
		I915_WRITE(DSPLINOFF(plane), linear_offset);
1968
	} else
1969
		I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1970
	POSTING_READ(reg);
J
Jesse Barnes 已提交
1971

1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983
	return 0;
}

static int ironlake_update_plane(struct drm_crtc *crtc,
				 struct drm_framebuffer *fb, int x, int y)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_framebuffer *intel_fb;
	struct drm_i915_gem_object *obj;
	int plane = intel_crtc->plane;
1984
	unsigned long linear_offset;
1985 1986 1987 1988 1989 1990
	u32 dspcntr;
	u32 reg;

	switch (plane) {
	case 0:
	case 1:
J
Jesse Barnes 已提交
1991
	case 2:
1992 1993
		break;
	default:
1994
		DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1995 1996 1997 1998 1999 2000 2001 2002 2003 2004
		return -EINVAL;
	}

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

	reg = DSPCNTR(plane);
	dspcntr = I915_READ(reg);
	/* Mask out pixel format bits in case we change it */
	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2005 2006
	switch (fb->pixel_format) {
	case DRM_FORMAT_C8:
2007 2008
		dspcntr |= DISPPLANE_8BPP;
		break;
2009 2010
	case DRM_FORMAT_RGB565:
		dspcntr |= DISPPLANE_BGRX565;
2011
		break;
2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
		dspcntr |= DISPPLANE_BGRX888;
		break;
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
		dspcntr |= DISPPLANE_RGBX888;
		break;
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
		dspcntr |= DISPPLANE_BGRX101010;
		break;
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
		dspcntr |= DISPPLANE_RGBX101010;
2027 2028
		break;
	default:
2029
		BUG();
2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041
	}

	if (obj->tiling_mode != I915_TILING_NONE)
		dspcntr |= DISPPLANE_TILED;
	else
		dspcntr &= ~DISPPLANE_TILED;

	/* must disable */
	dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

	I915_WRITE(reg, dspcntr);

2042
	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2043
	intel_crtc->dspaddr_offset =
2044 2045 2046
		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
					       fb->bits_per_pixel / 8,
					       fb->pitches[0]);
2047
	linear_offset -= intel_crtc->dspaddr_offset;
2048

2049 2050
	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		      obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2051
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2052 2053
	I915_MODIFY_DISPBASE(DSPSURF(plane),
			     obj->gtt_offset + intel_crtc->dspaddr_offset);
2054 2055 2056 2057 2058 2059
	if (IS_HASWELL(dev)) {
		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
	} else {
		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
		I915_WRITE(DSPLINOFF(plane), linear_offset);
	}
2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072
	POSTING_READ(reg);

	return 0;
}

/* Assume fb object is pinned & idle & fenced and just update base pointers */
static int
intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			   int x, int y, enum mode_set_atomic state)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

2073 2074
	if (dev_priv->display.disable_fbc)
		dev_priv->display.disable_fbc(dev);
2075
	intel_increase_pllclock(crtc);
J
Jesse Barnes 已提交
2076

2077
	return dev_priv->display.update_plane(crtc, fb, x, y);
J
Jesse Barnes 已提交
2078 2079
}

2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117
void intel_display_handle_reset(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;

	/*
	 * Flips in the rings have been nuked by the reset,
	 * so complete all pending flips so that user space
	 * will get its events and not get stuck.
	 *
	 * Also update the base address of all primary
	 * planes to the the last fb to make sure we're
	 * showing the correct fb after a reset.
	 *
	 * Need to make two loops over the crtcs so that we
	 * don't try to grab a crtc mutex before the
	 * pending_flip_queue really got woken up.
	 */

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		enum plane plane = intel_crtc->plane;

		intel_prepare_page_flip(dev, plane);
		intel_finish_page_flip_plane(dev, plane);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

		mutex_lock(&crtc->mutex);
		if (intel_crtc->active)
			dev_priv->display.update_plane(crtc, crtc->fb,
						       crtc->x, crtc->y);
		mutex_unlock(&crtc->mutex);
	}
}

2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140
static int
intel_finish_fb(struct drm_framebuffer *old_fb)
{
	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	bool was_interruptible = dev_priv->mm.interruptible;
	int ret;

	/* Big Hammer, we also need to ensure that any pending
	 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
	 * current scanout is retired before unpinning the old
	 * framebuffer.
	 *
	 * This should only fail upon a hung GPU, in which case we
	 * can safely continue.
	 */
	dev_priv->mm.interruptible = false;
	ret = i915_gem_object_finish_gpu(obj);
	dev_priv->mm.interruptible = was_interruptible;

	return ret;
}

2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167
static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!dev->primary->master)
		return;

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
		return;

	switch (intel_crtc->pipe) {
	case 0:
		master_priv->sarea_priv->pipeA_x = x;
		master_priv->sarea_priv->pipeA_y = y;
		break;
	case 1:
		master_priv->sarea_priv->pipeB_x = x;
		master_priv->sarea_priv->pipeB_y = y;
		break;
	default:
		break;
	}
}

2168
static int
2169
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2170
		    struct drm_framebuffer *fb)
J
Jesse Barnes 已提交
2171 2172
{
	struct drm_device *dev = crtc->dev;
2173
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2174
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2175
	struct drm_framebuffer *old_fb;
2176
	int ret;
J
Jesse Barnes 已提交
2177 2178

	/* no fb bound */
2179
	if (!fb) {
2180
		DRM_ERROR("No FB bound\n");
2181 2182 2183
		return 0;
	}

2184
	if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2185 2186 2187
		DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
			  plane_name(intel_crtc->plane),
			  INTEL_INFO(dev)->num_pipes);
2188
		return -EINVAL;
J
Jesse Barnes 已提交
2189 2190
	}

2191
	mutex_lock(&dev->struct_mutex);
2192
	ret = intel_pin_and_fence_fb_obj(dev,
2193
					 to_intel_framebuffer(fb)->obj,
2194
					 NULL);
2195 2196
	if (ret != 0) {
		mutex_unlock(&dev->struct_mutex);
2197
		DRM_ERROR("pin & fence failed\n");
2198 2199
		return ret;
	}
J
Jesse Barnes 已提交
2200

2201
	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2202
	if (ret) {
2203
		intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2204
		mutex_unlock(&dev->struct_mutex);
2205
		DRM_ERROR("failed to update base address\n");
2206
		return ret;
J
Jesse Barnes 已提交
2207
	}
2208

2209 2210
	old_fb = crtc->fb;
	crtc->fb = fb;
2211 2212
	crtc->x = x;
	crtc->y = y;
2213

2214 2215
	if (old_fb) {
		intel_wait_for_vblank(dev, intel_crtc->pipe);
2216
		intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2217
	}
2218

2219
	intel_update_fbc(dev);
2220
	mutex_unlock(&dev->struct_mutex);
J
Jesse Barnes 已提交
2221

2222
	intel_crtc_update_sarea_pos(crtc, x, y);
2223 2224

	return 0;
J
Jesse Barnes 已提交
2225 2226
}

2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237
static void intel_fdi_normal_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* enable normal train */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2238
	if (IS_IVYBRIDGE(dev)) {
2239 2240
		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2241 2242 2243
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2244
	}
2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_NORMAL_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_NONE;
	}
	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

	/* wait one idle pattern time */
	POSTING_READ(reg);
	udelay(1000);
2261 2262 2263 2264 2265

	/* IVB wants error correction enabled */
	if (IS_IVYBRIDGE(dev))
		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
			   FDI_FE_ERRC_ENABLE);
2266 2267
}

2268 2269 2270 2271 2272
static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
{
	return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
}

2273 2274 2275 2276 2277 2278 2279 2280 2281
static void ivb_modeset_global_resources(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *pipe_B_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
	struct intel_crtc *pipe_C_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
	uint32_t temp;

2282 2283 2284 2285 2286 2287 2288
	/*
	 * When everything is off disable fdi C so that we could enable fdi B
	 * with all lanes. Note that we don't care about enabled pipes without
	 * an enabled pch encoder.
	 */
	if (!pipe_has_enabled_pch(pipe_B_crtc) &&
	    !pipe_has_enabled_pch(pipe_C_crtc)) {
2289 2290 2291 2292 2293 2294 2295 2296 2297 2298
		WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
		WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);

		temp = I915_READ(SOUTH_CHICKEN1);
		temp &= ~FDI_BC_BIFURCATION_SELECT;
		DRM_DEBUG_KMS("disabling fdi C rx\n");
		I915_WRITE(SOUTH_CHICKEN1, temp);
	}
}

2299 2300 2301 2302 2303 2304 2305
/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2306
	int plane = intel_crtc->plane;
2307
	u32 reg, temp, tries;
2308

2309 2310 2311 2312
	/* FDI needs bits from pipe & plane first */
	assert_pipe_enabled(dev_priv, pipe);
	assert_plane_enabled(dev_priv, plane);

2313 2314
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
2315 2316
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
2317 2318
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
2319 2320
	I915_WRITE(reg, temp);
	I915_READ(reg);
2321 2322
	udelay(150);

2323
	/* enable CPU FDI TX and PCH FDI RX */
2324 2325
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2326 2327
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2328 2329
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
2330
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2331

2332 2333
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2334 2335
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
2336 2337 2338
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
2339 2340
	udelay(150);

2341
	/* Ironlake workaround, enable clock pointer after FDI enable*/
2342 2343 2344
	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
		   FDI_RX_PHASE_SYNC_POINTER_EN);
2345

2346
	reg = FDI_RX_IIR(pipe);
2347
	for (tries = 0; tries < 5; tries++) {
2348
		temp = I915_READ(reg);
2349 2350 2351 2352
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if ((temp & FDI_RX_BIT_LOCK)) {
			DRM_DEBUG_KMS("FDI train 1 done.\n");
2353
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2354 2355 2356
			break;
		}
	}
2357
	if (tries == 5)
2358
		DRM_ERROR("FDI train 1 fail!\n");
2359 2360

	/* Train 2 */
2361 2362
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2363 2364
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
2365
	I915_WRITE(reg, temp);
2366

2367 2368
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2369 2370
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
2371
	I915_WRITE(reg, temp);
2372

2373 2374
	POSTING_READ(reg);
	udelay(150);
2375

2376
	reg = FDI_RX_IIR(pipe);
2377
	for (tries = 0; tries < 5; tries++) {
2378
		temp = I915_READ(reg);
2379 2380 2381
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
2382
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2383 2384 2385 2386
			DRM_DEBUG_KMS("FDI train 2 done.\n");
			break;
		}
	}
2387
	if (tries == 5)
2388
		DRM_ERROR("FDI train 2 fail!\n");
2389 2390

	DRM_DEBUG_KMS("FDI train done\n");
2391

2392 2393
}

2394
static const int snb_b_fdi_train_param[] = {
2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407
	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
};

/* The FDI link training functions for SNB/Cougarpoint. */
static void gen6_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2408
	u32 reg, temp, i, retry;
2409

2410 2411
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
2412 2413
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
2414 2415
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
2416 2417 2418
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
2419 2420
	udelay(150);

2421
	/* enable CPU FDI TX and PCH FDI RX */
2422 2423
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2424 2425
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2426 2427 2428 2429 2430
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	/* SNB-B */
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2431
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2432

2433 2434 2435
	I915_WRITE(FDI_RX_MISC(pipe),
		   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

2436 2437
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2438 2439 2440 2441 2442 2443 2444
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
2445 2446 2447
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
2448 2449
	udelay(150);

2450
	for (i = 0; i < 4; i++) {
2451 2452
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2453 2454
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
2455 2456 2457
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
2458 2459
		udelay(500);

2460 2461 2462 2463 2464 2465 2466 2467 2468 2469
		for (retry = 0; retry < 5; retry++) {
			reg = FDI_RX_IIR(pipe);
			temp = I915_READ(reg);
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
			if (temp & FDI_RX_BIT_LOCK) {
				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
				DRM_DEBUG_KMS("FDI train 1 done.\n");
				break;
			}
			udelay(50);
2470
		}
2471 2472
		if (retry < 5)
			break;
2473 2474
	}
	if (i == 4)
2475
		DRM_ERROR("FDI train 1 fail!\n");
2476 2477

	/* Train 2 */
2478 2479
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2480 2481 2482 2483 2484 2485 2486
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
	if (IS_GEN6(dev)) {
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		/* SNB-B */
		temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
	}
2487
	I915_WRITE(reg, temp);
2488

2489 2490
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2491 2492 2493 2494 2495 2496 2497
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_2;
	}
2498 2499 2500
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
2501 2502
	udelay(150);

2503
	for (i = 0; i < 4; i++) {
2504 2505
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2506 2507
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
2508 2509 2510
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
2511 2512
		udelay(500);

2513 2514 2515 2516 2517 2518 2519 2520 2521 2522
		for (retry = 0; retry < 5; retry++) {
			reg = FDI_RX_IIR(pipe);
			temp = I915_READ(reg);
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
			if (temp & FDI_RX_SYMBOL_LOCK) {
				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
				DRM_DEBUG_KMS("FDI train 2 done.\n");
				break;
			}
			udelay(50);
2523
		}
2524 2525
		if (retry < 5)
			break;
2526 2527
	}
	if (i == 4)
2528
		DRM_ERROR("FDI train 2 fail!\n");
2529 2530 2531 2532

	DRM_DEBUG_KMS("FDI train done.\n");
}

2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552
/* Manual link training for Ivy Bridge A0 parts */
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp, i;

	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

2553 2554 2555
	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
		      I915_READ(FDI_RX_IIR(pipe)));

2556 2557 2558
	/* enable CPU FDI TX and PCH FDI RX */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2559 2560
	temp &= ~FDI_DP_PORT_WIDTH_MASK;
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2561 2562 2563 2564
	temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
	temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2565
	temp |= FDI_COMPOSITE_SYNC;
2566 2567
	I915_WRITE(reg, temp | FDI_TX_ENABLE);

2568 2569 2570
	I915_WRITE(FDI_RX_MISC(pipe),
		   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

2571 2572 2573 2574 2575
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_AUTO;
	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
	temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2576
	temp |= FDI_COMPOSITE_SYNC;
2577 2578 2579 2580 2581
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(150);

2582
	for (i = 0; i < 4; i++) {
2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
		udelay(500);

		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_BIT_LOCK ||
		    (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2599
			DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623
			break;
		}
	}
	if (i == 4)
		DRM_ERROR("FDI train 1 fail!\n");

	/* Train 2 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
	temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
	temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

2624
	for (i = 0; i < 4; i++) {
2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
		udelay(500);

		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2640
			DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2641 2642 2643 2644 2645 2646 2647 2648 2649
			break;
		}
	}
	if (i == 4)
		DRM_ERROR("FDI train 2 fail!\n");

	DRM_DEBUG_KMS("FDI train done.\n");
}

2650
static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2651
{
2652
	struct drm_device *dev = intel_crtc->base.dev;
2653 2654
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = intel_crtc->pipe;
2655
	u32 reg, temp;
J
Jesse Barnes 已提交
2656

2657

2658
	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2659 2660
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2661 2662
	temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2663
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2664 2665 2666
	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

	POSTING_READ(reg);
2667 2668 2669
	udelay(200);

	/* Switch from Rawclk to PCDclk */
2670 2671 2672 2673
	temp = I915_READ(reg);
	I915_WRITE(reg, temp | FDI_PCDCLK);

	POSTING_READ(reg);
2674 2675
	udelay(200);

2676 2677 2678 2679 2680
	/* Enable CPU FDI TX PLL, always on for Ironlake */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2681

2682 2683
		POSTING_READ(reg);
		udelay(100);
2684
	}
2685 2686
}

2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715
static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* Switch from PCDclk to Rawclk */
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_PCDCLK);

	/* Disable CPU FDI TX PLL */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);

	POSTING_READ(reg);
	udelay(100);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);

	/* Wait for the clocks to turn off. */
	POSTING_READ(reg);
	udelay(100);
}

2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732
static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* disable CPU FDI tx and PCH FDI rx */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
	POSTING_READ(reg);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~(0x7 << 16);
2733
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2734 2735 2736 2737 2738 2739
	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(100);

	/* Ironlake workaround, disable clock pointer after downing FDI */
2740 2741 2742
	if (HAS_PCH_IBX(dev)) {
		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
	}
2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761

	/* still set train pattern 1 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
	/* BPC in FDI rx is consistent with that in PIPECONF */
	temp &= ~(0x07 << 16);
2762
	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2763 2764 2765 2766 2767 2768
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(100);
}

2769 2770 2771 2772
static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2773
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774 2775 2776
	unsigned long flags;
	bool pending;

2777 2778
	if (i915_reset_in_progress(&dev_priv->gpu_error) ||
	    intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2779 2780 2781 2782 2783 2784 2785 2786 2787
		return false;

	spin_lock_irqsave(&dev->event_lock, flags);
	pending = to_intel_crtc(crtc)->unpin_work != NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	return pending;
}

2788 2789
static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
{
2790
	struct drm_device *dev = crtc->dev;
2791
	struct drm_i915_private *dev_priv = dev->dev_private;
2792 2793 2794 2795

	if (crtc->fb == NULL)
		return;

2796 2797
	WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));

2798 2799 2800
	wait_event(dev_priv->pending_flip_queue,
		   !intel_crtc_has_pending_flip(crtc));

2801 2802 2803
	mutex_lock(&dev->struct_mutex);
	intel_finish_fb(crtc->fb);
	mutex_unlock(&dev->struct_mutex);
2804 2805
}

2806 2807 2808 2809 2810 2811 2812 2813
/* Program iCLKIP clock to the desired frequency */
static void lpt_program_iclkip(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 divsel, phaseinc, auxdiv, phasedir = 0;
	u32 temp;

2814 2815
	mutex_lock(&dev_priv->dpio_lock);

2816 2817 2818 2819 2820 2821 2822
	/* It is necessary to ungate the pixclk gate prior to programming
	 * the divisors, and gate it back when it is done.
	 */
	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);

	/* Disable SSCCTL */
	intel_sbi_write(dev_priv, SBI_SSCCTL6,
2823 2824 2825
			intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
				SBI_SSCCTL_DISABLE,
			SBI_ICLK);
2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865

	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
	if (crtc->mode.clock == 20000) {
		auxdiv = 1;
		divsel = 0x41;
		phaseinc = 0x20;
	} else {
		/* The iCLK virtual clock root frequency is in MHz,
		 * but the crtc->mode.clock in in KHz. To get the divisors,
		 * it is necessary to divide one by another, so we
		 * convert the virtual clock precision to KHz here for higher
		 * precision.
		 */
		u32 iclk_virtual_root_freq = 172800 * 1000;
		u32 iclk_pi_range = 64;
		u32 desired_divisor, msb_divisor_value, pi_value;

		desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
		msb_divisor_value = desired_divisor / iclk_pi_range;
		pi_value = desired_divisor % iclk_pi_range;

		auxdiv = 0;
		divsel = msb_divisor_value - 2;
		phaseinc = pi_value;
	}

	/* This should not happen with any sane values */
	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		~SBI_SSCDIVINTPHASE_INCVAL_MASK);

	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
			crtc->mode.clock,
			auxdiv,
			divsel,
			phasedir,
			phaseinc);

	/* Program SSCDIVINTPHASE6 */
2866
	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2867 2868 2869 2870 2871 2872
	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2873
	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2874 2875

	/* Program SSCAUXDIV */
2876
	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2877 2878
	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2879
	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2880 2881

	/* Enable modulator and associated divider */
2882
	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2883
	temp &= ~SBI_SSCCTL_DISABLE;
2884
	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2885 2886 2887 2888 2889

	/* Wait for initialization time */
	udelay(24);

	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2890 2891

	mutex_unlock(&dev_priv->dpio_lock);
2892 2893
}

2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917
static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
						enum pipe pch_transcoder)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;

	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
		   I915_READ(HTOTAL(cpu_transcoder)));
	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
		   I915_READ(HBLANK(cpu_transcoder)));
	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
		   I915_READ(HSYNC(cpu_transcoder)));

	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
		   I915_READ(VTOTAL(cpu_transcoder)));
	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
		   I915_READ(VBLANK(cpu_transcoder)));
	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
		   I915_READ(VSYNC(cpu_transcoder)));
	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
		   I915_READ(VSYNCSHIFT(cpu_transcoder)));
}

2918 2919 2920 2921 2922 2923 2924 2925 2926
/*
 * Enable PCH resources required for PCH ports:
 *   - PCH PLLs
 *   - FDI training & RX/TX
 *   - update transcoder timings
 *   - DP transcoding bits
 *   - transcoder
 */
static void ironlake_pch_enable(struct drm_crtc *crtc)
2927 2928 2929 2930 2931
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2932
	u32 reg, temp;
2933

2934
	assert_pch_transcoder_disabled(dev_priv, pipe);
2935

2936 2937 2938 2939 2940
	/* Write the TU size bits before fdi link training, so that error
	 * detection works. */
	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);

2941
	/* For PCH output, training FDI link */
2942
	dev_priv->display.fdi_link_train(crtc);
2943

2944 2945 2946 2947 2948 2949 2950
	/* XXX: pch pll's can be enabled any time before we enable the PCH
	 * transcoder, and we actually should do this to not upset any PCH
	 * transcoder that already use the clock when we share it.
	 *
	 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
	 * unconditionally resets the pll - we need that to have the right LVDS
	 * enable sequence. */
2951
	ironlake_enable_pch_pll(intel_crtc);
2952

2953
	if (HAS_PCH_CPT(dev)) {
2954
		u32 sel;
2955

2956
		temp = I915_READ(PCH_DPLL_SEL);
2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970
		switch (pipe) {
		default:
		case 0:
			temp |= TRANSA_DPLL_ENABLE;
			sel = TRANSA_DPLLB_SEL;
			break;
		case 1:
			temp |= TRANSB_DPLL_ENABLE;
			sel = TRANSB_DPLLB_SEL;
			break;
		case 2:
			temp |= TRANSC_DPLL_ENABLE;
			sel = TRANSC_DPLLB_SEL;
			break;
2971
		}
2972 2973 2974 2975
		if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
			temp |= sel;
		else
			temp &= ~sel;
2976 2977
		I915_WRITE(PCH_DPLL_SEL, temp);
	}
2978

2979 2980
	/* set transcoder timing, panel must allow it */
	assert_panel_unlocked(dev_priv, pipe);
2981
	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2982

2983
	intel_fdi_normal_train(crtc);
2984

2985 2986
	/* For PCH DP, enable TRANS_DP_CTL */
	if (HAS_PCH_CPT(dev) &&
2987 2988
	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2989
		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2990 2991 2992
		reg = TRANS_DP_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(TRANS_DP_PORT_SEL_MASK |
2993 2994
			  TRANS_DP_SYNC_MASK |
			  TRANS_DP_BPC_MASK);
2995 2996
		temp |= (TRANS_DP_OUTPUT_ENABLE |
			 TRANS_DP_ENH_FRAMING);
2997
		temp |= bpc << 9; /* same format but at 11:9 */
2998 2999

		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3000
			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3001
		if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3002
			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3003 3004 3005

		switch (intel_trans_dp_port_sel(crtc)) {
		case PCH_DP_B:
3006
			temp |= TRANS_DP_PORT_SEL_B;
3007 3008
			break;
		case PCH_DP_C:
3009
			temp |= TRANS_DP_PORT_SEL_C;
3010 3011
			break;
		case PCH_DP_D:
3012
			temp |= TRANS_DP_PORT_SEL_D;
3013 3014
			break;
		default:
3015
			BUG();
3016
		}
3017

3018
		I915_WRITE(reg, temp);
3019
	}
3020

3021
	ironlake_enable_pch_transcoder(dev_priv, pipe);
3022 3023
}

P
Paulo Zanoni 已提交
3024 3025 3026 3027 3028
static void lpt_pch_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
P
Paulo Zanoni 已提交
3030

3031
	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
P
Paulo Zanoni 已提交
3032

3033
	lpt_program_iclkip(crtc);
P
Paulo Zanoni 已提交
3034

3035
	/* Set transcoder timing. */
3036
	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
P
Paulo Zanoni 已提交
3037

3038
	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3039 3040
}

3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069
static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
{
	struct intel_pch_pll *pll = intel_crtc->pch_pll;

	if (pll == NULL)
		return;

	if (pll->refcount == 0) {
		WARN(1, "bad PCH PLL refcount\n");
		return;
	}

	--pll->refcount;
	intel_crtc->pch_pll = NULL;
}

static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
{
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
	struct intel_pch_pll *pll;
	int i;

	pll = intel_crtc->pch_pll;
	if (pll) {
		DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
			      intel_crtc->base.base.id, pll->pll_reg);
		goto prepare;
	}

3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080
	if (HAS_PCH_IBX(dev_priv->dev)) {
		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
		i = intel_crtc->pipe;
		pll = &dev_priv->pch_plls[i];

		DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
			      intel_crtc->base.base.id, pll->pll_reg);

		goto found;
	}

3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112
	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		pll = &dev_priv->pch_plls[i];

		/* Only want to check enabled timings first */
		if (pll->refcount == 0)
			continue;

		if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
		    fp == I915_READ(pll->fp0_reg)) {
			DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
				      intel_crtc->base.base.id,
				      pll->pll_reg, pll->refcount, pll->active);

			goto found;
		}
	}

	/* Ok no matching timings, maybe there's a free one? */
	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		pll = &dev_priv->pch_plls[i];
		if (pll->refcount == 0) {
			DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
				      intel_crtc->base.base.id, pll->pll_reg);
			goto found;
		}
	}

	return NULL;

found:
	intel_crtc->pch_pll = pll;
	pll->refcount++;
3113
	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3114 3115 3116
prepare: /* separate function? */
	DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);

3117 3118
	/* Wait for the clocks to stabilize before rewriting the regs */
	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3119 3120
	POSTING_READ(pll->pll_reg);
	udelay(150);
3121 3122 3123

	I915_WRITE(pll->fp0_reg, fp);
	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3124 3125 3126 3127
	pll->on = false;
	return pll;
}

3128
static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3129 3130
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3131
	int dslreg = PIPEDSL(pipe);
3132 3133 3134 3135 3136 3137
	u32 temp;

	temp = I915_READ(dslreg);
	udelay(500);
	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		if (wait_for(I915_READ(dslreg) != temp, 5))
3138
			DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3139 3140 3141
	}
}

3142 3143 3144 3145 3146 3147
static void ironlake_pfit_enable(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = crtc->pipe;

3148
	if (crtc->config.pch_pfit.size) {
3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162
		/* Force use of hard-coded filter coefficients
		 * as some pre-programmed values are broken,
		 * e.g. x201.
		 */
		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
						 PF_PIPE_SEL_IVB(pipe));
		else
			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
		I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
		I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
	}
}

3163 3164 3165 3166 3167
static void ironlake_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168
	struct intel_encoder *encoder;
3169 3170 3171 3172
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	u32 temp;

3173 3174
	WARN_ON(!crtc->enabled);

3175 3176 3177 3178
	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
3179 3180 3181 3182

	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);

3183 3184 3185 3186 3187 3188 3189 3190 3191
	intel_update_watermarks(dev);

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		temp = I915_READ(PCH_LVDS);
		if ((temp & LVDS_PORT_EN) == 0)
			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
	}


3192
	if (intel_crtc->config.has_pch_encoder) {
3193 3194 3195
		/* Note: FDI PLL enabling _must_ be done before we enable the
		 * cpu pipes, hence this is separate from all the other fdi/pch
		 * enabling. */
3196
		ironlake_fdi_pll_enable(intel_crtc);
3197 3198 3199 3200
	} else {
		assert_fdi_tx_disabled(dev_priv, pipe);
		assert_fdi_rx_disabled(dev_priv, pipe);
	}
3201

3202 3203 3204
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);
3205 3206

	/* Enable panel fitting for LVDS */
3207
	ironlake_pfit_enable(intel_crtc);
3208

3209 3210 3211 3212 3213 3214
	/*
	 * On ILK+ LUT must be loaded before the pipe is running but with
	 * clocks enabled
	 */
	intel_crtc_load_lut(crtc);

3215 3216
	intel_enable_pipe(dev_priv, pipe,
			  intel_crtc->config.has_pch_encoder);
3217 3218
	intel_enable_plane(dev_priv, plane, pipe);

3219
	if (intel_crtc->config.has_pch_encoder)
3220
		ironlake_pch_enable(crtc);
3221

3222
	mutex_lock(&dev->struct_mutex);
C
Chris Wilson 已提交
3223
	intel_update_fbc(dev);
3224 3225
	mutex_unlock(&dev->struct_mutex);

3226
	intel_crtc_update_cursor(crtc, true);
3227

3228 3229
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);
3230 3231

	if (HAS_PCH_CPT(dev))
3232
		cpt_verify_modeset(dev, intel_crtc->pipe);
3233 3234 3235 3236 3237 3238 3239 3240 3241 3242

	/*
	 * There seems to be a race in PCH platform hw (at least on some
	 * outputs) where an enabled pipe still completes any pageflip right
	 * away (as if the pipe is off) instead of waiting for vblank. As soon
	 * as the first vblank happend, everything works as expected. Hence just
	 * wait for one vblank before returning to avoid strange things
	 * happening.
	 */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
3243 3244
}

3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259
static void haswell_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_encoder *encoder;
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;

	WARN_ON(!crtc->enabled);

	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
3260 3261 3262 3263 3264

	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
	if (intel_crtc->config.has_pch_encoder)
		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);

3265 3266
	intel_update_watermarks(dev);

3267
	if (intel_crtc->config.has_pch_encoder)
3268
		dev_priv->display.fdi_link_train(crtc);
3269 3270 3271 3272 3273

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);

3274
	intel_ddi_enable_pipe_clock(intel_crtc);
3275

3276
	/* Enable panel fitting for eDP */
3277
	ironlake_pfit_enable(intel_crtc);
3278 3279 3280 3281 3282 3283 3284

	/*
	 * On ILK+ LUT must be loaded before the pipe is running but with
	 * clocks enabled
	 */
	intel_crtc_load_lut(crtc);

3285
	intel_ddi_set_pipe_settings(crtc);
3286
	intel_ddi_enable_transcoder_func(crtc);
3287

3288 3289
	intel_enable_pipe(dev_priv, pipe,
			  intel_crtc->config.has_pch_encoder);
3290 3291
	intel_enable_plane(dev_priv, plane, pipe);

3292
	if (intel_crtc->config.has_pch_encoder)
P
Paulo Zanoni 已提交
3293
		lpt_pch_enable(crtc);
3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314

	mutex_lock(&dev->struct_mutex);
	intel_update_fbc(dev);
	mutex_unlock(&dev->struct_mutex);

	intel_crtc_update_cursor(crtc, true);

	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);

	/*
	 * There seems to be a race in PCH platform hw (at least on some
	 * outputs) where an enabled pipe still completes any pageflip right
	 * away (as if the pipe is off) instead of waiting for vblank. As soon
	 * as the first vblank happend, everything works as expected. Hence just
	 * wait for one vblank before returning to avoid strange things
	 * happening.
	 */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
}

3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329
static void ironlake_pfit_disable(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = crtc->pipe;

	/* To avoid upsetting the power well on haswell only disable the pfit if
	 * it's in use. The hw state code will make sure we get this right. */
	if (crtc->config.pch_pfit.size) {
		I915_WRITE(PF_CTL(pipe), 0);
		I915_WRITE(PF_WIN_POS(pipe), 0);
		I915_WRITE(PF_WIN_SZ(pipe), 0);
	}
}

3330 3331 3332 3333 3334
static void ironlake_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3335
	struct intel_encoder *encoder;
3336 3337
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3338
	u32 reg, temp;
3339

3340

3341 3342 3343
	if (!intel_crtc->active)
		return;

3344 3345 3346
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->disable(encoder);

3347
	intel_crtc_wait_for_pending_flips(crtc);
3348
	drm_vblank_off(dev, pipe);
3349
	intel_crtc_update_cursor(crtc, false);
3350

3351
	intel_disable_plane(dev_priv, plane, pipe);
3352

3353 3354
	if (dev_priv->cfb_plane == plane)
		intel_disable_fbc(dev);
3355

3356
	intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3357
	intel_disable_pipe(dev_priv, pipe);
3358

3359
	ironlake_pfit_disable(intel_crtc);
3360

3361 3362 3363
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->post_disable)
			encoder->post_disable(encoder);
3364

3365
	ironlake_fdi_disable(crtc);
3366

3367
	ironlake_disable_pch_transcoder(dev_priv, pipe);
3368
	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3369

3370 3371
	if (HAS_PCH_CPT(dev)) {
		/* disable TRANS_DP_CTL */
3372 3373 3374
		reg = TRANS_DP_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3375
		temp |= TRANS_DP_PORT_SEL_NONE;
3376
		I915_WRITE(reg, temp);
3377 3378 3379

		/* disable DPLL_SEL */
		temp = I915_READ(PCH_DPLL_SEL);
3380 3381
		switch (pipe) {
		case 0:
3382
			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3383 3384
			break;
		case 1:
3385
			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3386 3387
			break;
		case 2:
3388
			/* C shares PLL A or B */
3389
			temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3390 3391 3392 3393
			break;
		default:
			BUG(); /* wtf */
		}
3394 3395
		I915_WRITE(PCH_DPLL_SEL, temp);
	}
3396

3397
	/* disable PCH DPLL */
3398
	intel_disable_pch_pll(intel_crtc);
3399

3400
	ironlake_fdi_pll_disable(intel_crtc);
3401

3402
	intel_crtc->active = false;
3403
	intel_update_watermarks(dev);
3404 3405

	mutex_lock(&dev->struct_mutex);
3406
	intel_update_fbc(dev);
3407
	mutex_unlock(&dev->struct_mutex);
3408
}
3409

3410
static void haswell_crtc_disable(struct drm_crtc *crtc)
3411
{
3412 3413
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
3414
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3415 3416 3417
	struct intel_encoder *encoder;
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3418
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3419

3420 3421 3422 3423 3424 3425 3426 3427 3428 3429
	if (!intel_crtc->active)
		return;

	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->disable(encoder);

	intel_crtc_wait_for_pending_flips(crtc);
	drm_vblank_off(dev, pipe);
	intel_crtc_update_cursor(crtc, false);

R
Rodrigo Vivi 已提交
3430
	/* FBC must be disabled before disabling the plane on HSW. */
3431 3432 3433
	if (dev_priv->cfb_plane == plane)
		intel_disable_fbc(dev);

R
Rodrigo Vivi 已提交
3434 3435
	intel_disable_plane(dev_priv, plane, pipe);

3436 3437
	if (intel_crtc->config.has_pch_encoder)
		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3438 3439
	intel_disable_pipe(dev_priv, pipe);

3440
	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3441

3442
	ironlake_pfit_disable(intel_crtc);
3443

3444
	intel_ddi_disable_pipe_clock(intel_crtc);
3445 3446 3447 3448 3449

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->post_disable)
			encoder->post_disable(encoder);

3450
	if (intel_crtc->config.has_pch_encoder) {
3451
		lpt_disable_pch_transcoder(dev_priv);
3452
		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3453
		intel_ddi_fdi_disable(crtc);
3454
	}
3455 3456 3457 3458 3459 3460 3461 3462 3463

	intel_crtc->active = false;
	intel_update_watermarks(dev);

	mutex_lock(&dev->struct_mutex);
	intel_update_fbc(dev);
	mutex_unlock(&dev->struct_mutex);
}

3464 3465 3466 3467 3468 3469
static void ironlake_crtc_off(struct drm_crtc *crtc)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	intel_put_pch_pll(intel_crtc);
}

3470 3471 3472 3473 3474
static void haswell_crtc_off(struct drm_crtc *crtc)
{
	intel_ddi_put_crtc_pll(crtc);
}

3475 3476 3477
static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
{
	if (!enable && intel_crtc->overlay) {
3478
		struct drm_device *dev = intel_crtc->base.dev;
3479
		struct drm_i915_private *dev_priv = dev->dev_private;
3480

3481
		mutex_lock(&dev->struct_mutex);
3482 3483 3484
		dev_priv->mm.interruptible = false;
		(void) intel_overlay_switch_off(intel_crtc->overlay);
		dev_priv->mm.interruptible = true;
3485
		mutex_unlock(&dev->struct_mutex);
3486 3487
	}

3488 3489 3490
	/* Let userspace switch the overlay on again. In most cases userspace
	 * has to recompute where to put it anyway.
	 */
3491 3492
}

3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516
/**
 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
 * cursor plane briefly if not already running after enabling the display
 * plane.
 * This workaround avoids occasional blank screens when self refresh is
 * enabled.
 */
static void
g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
{
	u32 cntl = I915_READ(CURCNTR(pipe));

	if ((cntl & CURSOR_MODE) == 0) {
		u32 fw_bcl_self = I915_READ(FW_BLC_SELF);

		I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
		I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
		intel_wait_for_vblank(dev_priv->dev, pipe);
		I915_WRITE(CURCNTR(pipe), cntl);
		I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
		I915_WRITE(FW_BLC_SELF, fw_bcl_self);
	}
}

3517 3518 3519 3520 3521 3522
static void i9xx_pfit_enable(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc_config *pipe_config = &crtc->config;

3523
	if (!crtc->config.gmch_pfit.control)
3524 3525 3526
		return;

	/*
3527 3528
	 * The panel fitter should only be adjusted whilst the pipe is disabled,
	 * according to register description and PRM.
3529
	 */
3530 3531
	WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
	assert_pipe_disabled(dev_priv, crtc->pipe);
3532

3533 3534
	I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
	I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3535 3536 3537 3538

	/* Border color in case we don't scale up to the full screen. Black by
	 * default, change to something else for debugging. */
	I915_WRITE(BCLRPAT(crtc->pipe), 0);
3539 3540
}

3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573
static void valleyview_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_encoder *encoder;
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;

	WARN_ON(!crtc->enabled);

	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
	intel_update_watermarks(dev);

	mutex_lock(&dev_priv->dpio_lock);

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_pll_enable)
			encoder->pre_pll_enable(encoder);

	intel_enable_pll(dev_priv, pipe);

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);

	/* VLV wants encoder enabling _before_ the pipe is up. */
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);

3574 3575 3576
	/* Enable panel fitting for eDP */
	i9xx_pfit_enable(intel_crtc);

3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589
	intel_enable_pipe(dev_priv, pipe, false);
	intel_enable_plane(dev_priv, plane, pipe);

	intel_crtc_load_lut(crtc);
	intel_update_fbc(dev);

	/* Give the overlay scaler a chance to enable if it's on this pipe */
	intel_crtc_dpms_overlay(intel_crtc, true);
	intel_crtc_update_cursor(crtc, true);

	mutex_unlock(&dev_priv->dpio_lock);
}

3590
static void i9xx_crtc_enable(struct drm_crtc *crtc)
J
Jesse Barnes 已提交
3591 3592 3593 3594
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3595
	struct intel_encoder *encoder;
J
Jesse Barnes 已提交
3596
	int pipe = intel_crtc->pipe;
3597
	int plane = intel_crtc->plane;
J
Jesse Barnes 已提交
3598

3599 3600
	WARN_ON(!crtc->enabled);

3601 3602 3603 3604
	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
3605 3606
	intel_update_watermarks(dev);

3607
	intel_enable_pll(dev_priv, pipe);
3608 3609 3610 3611 3612

	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);

3613 3614 3615
	/* Enable panel fitting for LVDS */
	i9xx_pfit_enable(intel_crtc);

3616
	intel_enable_pipe(dev_priv, pipe, false);
3617
	intel_enable_plane(dev_priv, plane, pipe);
3618 3619
	if (IS_G4X(dev))
		g4x_fixup_plane(dev_priv, pipe);
J
Jesse Barnes 已提交
3620

3621
	intel_crtc_load_lut(crtc);
C
Chris Wilson 已提交
3622
	intel_update_fbc(dev);
J
Jesse Barnes 已提交
3623

3624 3625
	/* Give the overlay scaler a chance to enable if it's on this pipe */
	intel_crtc_dpms_overlay(intel_crtc, true);
3626
	intel_crtc_update_cursor(crtc, true);
3627

3628 3629
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);
3630
}
J
Jesse Barnes 已提交
3631

3632 3633 3634 3635 3636
static void i9xx_pfit_disable(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

3637 3638
	if (!crtc->config.gmch_pfit.control)
		return;
3639

3640
	assert_pipe_disabled(dev_priv, crtc->pipe);
3641

3642 3643 3644
	DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
			 I915_READ(PFIT_CONTROL));
	I915_WRITE(PFIT_CONTROL, 0);
3645 3646
}

3647 3648 3649 3650 3651
static void i9xx_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3652
	struct intel_encoder *encoder;
3653 3654
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3655

3656 3657 3658
	if (!intel_crtc->active)
		return;

3659 3660 3661
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->disable(encoder);

3662
	/* Give the overlay scaler a chance to disable if it's on this pipe */
3663 3664
	intel_crtc_wait_for_pending_flips(crtc);
	drm_vblank_off(dev, pipe);
3665
	intel_crtc_dpms_overlay(intel_crtc, false);
3666
	intel_crtc_update_cursor(crtc, false);
3667

3668 3669
	if (dev_priv->cfb_plane == plane)
		intel_disable_fbc(dev);
J
Jesse Barnes 已提交
3670

3671 3672
	intel_disable_plane(dev_priv, plane, pipe);
	intel_disable_pipe(dev_priv, pipe);
3673

3674
	i9xx_pfit_disable(intel_crtc);
3675

3676 3677 3678 3679
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->post_disable)
			encoder->post_disable(encoder);

3680
	intel_disable_pll(dev_priv, pipe);
3681

3682
	intel_crtc->active = false;
3683 3684
	intel_update_fbc(dev);
	intel_update_watermarks(dev);
3685 3686
}

3687 3688 3689 3690
static void i9xx_crtc_off(struct drm_crtc *crtc)
{
}

3691 3692
static void intel_crtc_update_sarea(struct drm_crtc *crtc,
				    bool enabled)
3693 3694 3695 3696 3697
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
J
Jesse Barnes 已提交
3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715

	if (!dev->primary->master)
		return;

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
		return;

	switch (pipe) {
	case 0:
		master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	case 1:
		master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	default:
3716
		DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
J
Jesse Barnes 已提交
3717 3718 3719 3720
		break;
	}
}

3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741
/**
 * Sets the power management mode of the pipe and plane.
 */
void intel_crtc_update_dpms(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	bool enable = false;

	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		enable |= intel_encoder->connectors_active;

	if (enable)
		dev_priv->display.crtc_enable(crtc);
	else
		dev_priv->display.crtc_disable(crtc);

	intel_crtc_update_sarea(crtc, enable);
}

3742 3743 3744
static void intel_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
3745
	struct drm_connector *connector;
3746
	struct drm_i915_private *dev_priv = dev->dev_private;
3747
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3748

3749 3750 3751 3752
	/* crtc should still be enabled when we disable it. */
	WARN_ON(!crtc->enabled);

	dev_priv->display.crtc_disable(crtc);
3753
	intel_crtc->eld_vld = false;
3754
	intel_crtc_update_sarea(crtc, false);
3755 3756
	dev_priv->display.off(crtc);

3757 3758
	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3759 3760 3761

	if (crtc->fb) {
		mutex_lock(&dev->struct_mutex);
3762
		intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3763
		mutex_unlock(&dev->struct_mutex);
3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776
		crtc->fb = NULL;
	}

	/* Update computed state. */
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		if (!connector->encoder || !connector->encoder->crtc)
			continue;

		if (connector->encoder->crtc != crtc)
			continue;

		connector->dpms = DRM_MODE_DPMS_OFF;
		to_intel_encoder(connector->encoder)->connectors_active = false;
3777 3778 3779
	}
}

3780
void intel_modeset_disable(struct drm_device *dev)
J
Jesse Barnes 已提交
3781
{
3782 3783 3784 3785 3786 3787
	struct drm_crtc *crtc;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (crtc->enabled)
			intel_crtc_disable(crtc);
	}
J
Jesse Barnes 已提交
3788 3789
}

C
Chris Wilson 已提交
3790
void intel_encoder_destroy(struct drm_encoder *encoder)
3791
{
3792
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
C
Chris Wilson 已提交
3793 3794 3795

	drm_encoder_cleanup(encoder);
	kfree(intel_encoder);
3796 3797
}

3798 3799 3800 3801
/* Simple dpms helper for encodres with just one connector, no cloning and only
 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
 * state of the entire output pipe. */
void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3802
{
3803 3804 3805
	if (mode == DRM_MODE_DPMS_ON) {
		encoder->connectors_active = true;

3806
		intel_crtc_update_dpms(encoder->base.crtc);
3807 3808 3809
	} else {
		encoder->connectors_active = false;

3810
		intel_crtc_update_dpms(encoder->base.crtc);
3811
	}
J
Jesse Barnes 已提交
3812 3813
}

3814 3815
/* Cross check the actual hw state with our own modeset state tracking (and it's
 * internal consistency). */
3816
static void intel_connector_check_state(struct intel_connector *connector)
J
Jesse Barnes 已提交
3817
{
3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846
	if (connector->get_hw_state(connector)) {
		struct intel_encoder *encoder = connector->encoder;
		struct drm_crtc *crtc;
		bool encoder_enabled;
		enum pipe pipe;

		DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
			      connector->base.base.id,
			      drm_get_connector_name(&connector->base));

		WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		     "wrong connector dpms state\n");
		WARN(connector->base.encoder != &encoder->base,
		     "active connector not linked to encoder\n");
		WARN(!encoder->connectors_active,
		     "encoder->connectors_active not set\n");

		encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		WARN(!encoder_enabled, "encoder not enabled\n");
		if (WARN_ON(!encoder->base.crtc))
			return;

		crtc = encoder->base.crtc;

		WARN(!crtc->enabled, "crtc not enabled\n");
		WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		WARN(pipe != to_intel_crtc(crtc)->pipe,
		     "encoder active on the wrong pipe\n");
	}
J
Jesse Barnes 已提交
3847 3848
}

3849 3850 3851
/* Even simpler default implementation, if there's really no special case to
 * consider. */
void intel_connector_dpms(struct drm_connector *connector, int mode)
J
Jesse Barnes 已提交
3852
{
3853
	struct intel_encoder *encoder = intel_attached_encoder(connector);
3854

3855 3856 3857
	/* All the simple cases only support two dpms states. */
	if (mode != DRM_MODE_DPMS_ON)
		mode = DRM_MODE_DPMS_OFF;
3858

3859 3860 3861 3862 3863 3864 3865 3866 3867
	if (mode == connector->dpms)
		return;

	connector->dpms = mode;

	/* Only need to change hw state when actually enabled */
	if (encoder->base.crtc)
		intel_encoder_dpms(encoder, mode);
	else
3868
		WARN_ON(encoder->connectors_active != false);
3869

3870
	intel_modeset_check_state(connector->dev);
J
Jesse Barnes 已提交
3871 3872
}

3873 3874 3875 3876
/* Simple connector->get_hw_state implementation for encoders that support only
 * one connector and no cloning and hence the encoder state determines the state
 * of the connector. */
bool intel_connector_get_hw_state(struct intel_connector *connector)
C
Chris Wilson 已提交
3877
{
3878
	enum pipe pipe = 0;
3879
	struct intel_encoder *encoder = connector->encoder;
C
Chris Wilson 已提交
3880

3881
	return encoder->get_hw_state(encoder, &pipe);
C
Chris Wilson 已提交
3882 3883
}

3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924
static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
				     struct intel_crtc_config *pipe_config)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *pipe_B_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);

	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
		      pipe_name(pipe), pipe_config->fdi_lanes);
	if (pipe_config->fdi_lanes > 4) {
		DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
			      pipe_name(pipe), pipe_config->fdi_lanes);
		return false;
	}

	if (IS_HASWELL(dev)) {
		if (pipe_config->fdi_lanes > 2) {
			DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
				      pipe_config->fdi_lanes);
			return false;
		} else {
			return true;
		}
	}

	if (INTEL_INFO(dev)->num_pipes == 2)
		return true;

	/* Ivybridge 3 pipe is really complicated */
	switch (pipe) {
	case PIPE_A:
		return true;
	case PIPE_B:
		if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
		    pipe_config->fdi_lanes > 2) {
			DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
				      pipe_name(pipe), pipe_config->fdi_lanes);
			return false;
		}
		return true;
	case PIPE_C:
3925
		if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941
		    pipe_B_crtc->config.fdi_lanes <= 2) {
			if (pipe_config->fdi_lanes > 2) {
				DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
					      pipe_name(pipe), pipe_config->fdi_lanes);
				return false;
			}
		} else {
			DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
			return false;
		}
		return true;
	default:
		BUG();
	}
}

3942 3943 3944
#define RETRY 1
static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
				       struct intel_crtc_config *pipe_config)
3945
{
3946
	struct drm_device *dev = intel_crtc->base.dev;
3947 3948
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
	int target_clock, lane, link_bw;
3949
	bool setup_ok, needs_recompute = false;
3950

3951
retry:
3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974
	/* FDI is a binary signal running at ~2.7GHz, encoding
	 * each output octet as 10 bits. The actual frequency
	 * is stored as a divider into a 100MHz clock, and the
	 * mode pixel clock is stored in units of 1KHz.
	 * Hence the bw of each lane in terms of the mode signal
	 * is:
	 */
	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;

	if (pipe_config->pixel_target_clock)
		target_clock = pipe_config->pixel_target_clock;
	else
		target_clock = adjusted_mode->clock;

	lane = ironlake_get_lanes_required(target_clock, link_bw,
					   pipe_config->pipe_bpp);

	pipe_config->fdi_lanes = lane;

	if (pipe_config->pixel_multiplier > 1)
		link_bw *= pipe_config->pixel_multiplier;
	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
			       link_bw, &pipe_config->fdi_m_n);
3975

3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991
	setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
					    intel_crtc->pipe, pipe_config);
	if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
		pipe_config->pipe_bpp -= 2*3;
		DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
			      pipe_config->pipe_bpp);
		needs_recompute = true;
		pipe_config->bw_constrained = true;

		goto retry;
	}

	if (needs_recompute)
		return RETRY;

	return setup_ok ? 0 : -EINVAL;
3992 3993
}

3994 3995
static int intel_crtc_compute_config(struct drm_crtc *crtc,
				     struct intel_crtc_config *pipe_config)
J
Jesse Barnes 已提交
3996
{
3997
	struct drm_device *dev = crtc->dev;
3998
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3999

4000
	if (HAS_PCH_SPLIT(dev)) {
4001
		/* FDI link clock is fixed at 2.7G */
4002 4003
		if (pipe_config->requested_mode.clock * 3
		    > IRONLAKE_FDI_FREQ * 4)
4004
			return -EINVAL;
4005
	}
4006

4007 4008 4009
	/* All interlaced capable intel hw wants timings in frames. Note though
	 * that intel_lvds_mode_fixup does some funny tricks with the crtc
	 * timings, so we need to be careful not to clobber these.*/
4010
	if (!pipe_config->timings_set)
4011
		drm_mode_set_crtcinfo(adjusted_mode, 0);
4012

4013 4014
	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4015 4016 4017
	 */
	if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
		adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4018
		return -EINVAL;
4019

4020
	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4021
		pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4022
	} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4023 4024 4025 4026 4027
		/* only a 8bpc pipe, with 6bpc dither through the panel fitter
		 * for lvds. */
		pipe_config->pipe_bpp = 8*3;
	}

4028
	if (pipe_config->has_pch_encoder)
4029
		return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
4030

4031
	return 0;
J
Jesse Barnes 已提交
4032 4033
}

J
Jesse Barnes 已提交
4034 4035 4036 4037 4038
static int valleyview_get_display_clock_speed(struct drm_device *dev)
{
	return 400000; /* FIXME */
}

4039 4040 4041 4042
static int i945_get_display_clock_speed(struct drm_device *dev)
{
	return 400000;
}
J
Jesse Barnes 已提交
4043

4044
static int i915_get_display_clock_speed(struct drm_device *dev)
J
Jesse Barnes 已提交
4045
{
4046 4047
	return 333000;
}
J
Jesse Barnes 已提交
4048

4049 4050 4051 4052
static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
{
	return 200000;
}
J
Jesse Barnes 已提交
4053

4054 4055 4056
static int i915gm_get_display_clock_speed(struct drm_device *dev)
{
	u16 gcfgc = 0;
J
Jesse Barnes 已提交
4057

4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);

	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		return 133000;
	else {
		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		case GC_DISPLAY_CLOCK_333_MHZ:
			return 333000;
		default:
		case GC_DISPLAY_CLOCK_190_200_MHZ:
			return 190000;
J
Jesse Barnes 已提交
4069
		}
4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090
	}
}

static int i865_get_display_clock_speed(struct drm_device *dev)
{
	return 266000;
}

static int i855_get_display_clock_speed(struct drm_device *dev)
{
	u16 hpllcc = 0;
	/* Assume that the hardware is in the high speed state.  This
	 * should be the default.
	 */
	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
	case GC_CLOCK_133_200:
	case GC_CLOCK_100_200:
		return 200000;
	case GC_CLOCK_166_250:
		return 250000;
	case GC_CLOCK_100_133:
J
Jesse Barnes 已提交
4091
		return 133000;
4092
	}
J
Jesse Barnes 已提交
4093

4094 4095 4096
	/* Shouldn't happen */
	return 0;
}
J
Jesse Barnes 已提交
4097

4098 4099 4100
static int i830_get_display_clock_speed(struct drm_device *dev)
{
	return 133000;
J
Jesse Barnes 已提交
4101 4102
}

4103
static void
4104
intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4105
{
4106 4107
	while (*num > DATA_LINK_M_N_MASK ||
	       *den > DATA_LINK_M_N_MASK) {
4108 4109 4110 4111 4112
		*num >>= 1;
		*den >>= 1;
	}
}

4113 4114 4115 4116 4117 4118 4119 4120
static void compute_m_n(unsigned int m, unsigned int n,
			uint32_t *ret_m, uint32_t *ret_n)
{
	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
	*ret_m = div_u64((uint64_t) m * *ret_n, n);
	intel_reduce_m_n_ratio(ret_m, ret_n);
}

4121 4122 4123 4124
void
intel_link_compute_m_n(int bits_per_pixel, int nlanes,
		       int pixel_clock, int link_clock,
		       struct intel_link_m_n *m_n)
4125
{
4126
	m_n->tu = 64;
4127 4128 4129 4130 4131 4132 4133

	compute_m_n(bits_per_pixel * pixel_clock,
		    link_clock * nlanes * 8,
		    &m_n->gmch_m, &m_n->gmch_n);

	compute_m_n(pixel_clock, link_clock,
		    &m_n->link_m, &m_n->link_n);
4134 4135
}

4136 4137
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
{
4138 4139
	if (i915_panel_use_ssc >= 0)
		return i915_panel_use_ssc != 0;
4140
	return dev_priv->vbt.lvds_use_ssc
4141
		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4142 4143
}

4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165
static int vlv_get_refclk(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int refclk = 27000; /* for DP & HDMI */

	return 100000; /* only one validated so far */

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		refclk = 96000;
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		if (intel_panel_use_ssc(dev_priv))
			refclk = 100000;
		else
			refclk = 96000;
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		refclk = 100000;
	}

	return refclk;
}

4166 4167 4168 4169 4170 4171
static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int refclk;

4172 4173 4174
	if (IS_VALLEYVIEW(dev)) {
		refclk = vlv_get_refclk(crtc);
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4175
	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4176
		refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
			      refclk / 1000);
	} else if (!IS_GEN2(dev)) {
		refclk = 96000;
	} else {
		refclk = 48000;
	}

	return refclk;
}

4188 4189 4190 4191 4192 4193 4194 4195 4196 4197
static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
{
	return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
}

static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
{
	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
}

4198
static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4199 4200
				     intel_clock_t *reduced_clock)
{
4201
	struct drm_device *dev = crtc->base.dev;
4202
	struct drm_i915_private *dev_priv = dev->dev_private;
4203
	int pipe = crtc->pipe;
4204 4205 4206
	u32 fp, fp2 = 0;

	if (IS_PINEVIEW(dev)) {
4207
		fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4208
		if (reduced_clock)
4209
			fp2 = pnv_dpll_compute_fp(reduced_clock);
4210
	} else {
4211
		fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4212
		if (reduced_clock)
4213
			fp2 = i9xx_dpll_compute_fp(reduced_clock);
4214 4215 4216 4217
	}

	I915_WRITE(FP0(pipe), fp);

4218 4219
	crtc->lowfreq_avail = false;
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4220 4221
	    reduced_clock && i915_powersave) {
		I915_WRITE(FP1(pipe), fp2);
4222
		crtc->lowfreq_avail = true;
4223 4224 4225 4226 4227
	} else {
		I915_WRITE(FP1(pipe), fp);
	}
}

4228 4229 4230 4231 4232 4233 4234 4235
static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
{
	u32 reg_val;

	/*
	 * PLLB opamp always calibrates to max value of 0x3f, force enable it
	 * and set it to a reasonable value instead.
	 */
4236
	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4237 4238
	reg_val &= 0xffffff00;
	reg_val |= 0x00000030;
4239
	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4240

4241
	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4242 4243
	reg_val &= 0x8cffffff;
	reg_val = 0x8c000000;
4244
	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4245

4246
	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4247
	reg_val &= 0xffffff00;
4248
	vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4249

4250
	reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4251 4252
	reg_val &= 0x00ffffff;
	reg_val |= 0xb0000000;
4253
	vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4254 4255
}

4256 4257 4258 4259 4260 4261 4262
static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
					 struct intel_link_m_n *m_n)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = crtc->pipe;

4263 4264 4265 4266
	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282
}

static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
					 struct intel_link_m_n *m_n)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = crtc->pipe;
	enum transcoder transcoder = crtc->config.cpu_transcoder;

	if (INTEL_INFO(dev)->gen >= 5) {
		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
	} else {
4283 4284 4285 4286
		I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
		I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
		I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
		I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4287 4288 4289
	}
}

4290 4291 4292 4293 4294 4295 4296 4297
static void intel_dp_set_m_n(struct intel_crtc *crtc)
{
	if (crtc->config.has_pch_encoder)
		intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
	else
		intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
}

4298
static void vlv_update_pll(struct intel_crtc *crtc)
4299
{
4300
	struct drm_device *dev = crtc->base.dev;
4301
	struct drm_i915_private *dev_priv = dev->dev_private;
4302 4303 4304
	struct drm_display_mode *adjusted_mode =
		&crtc->config.adjusted_mode;
	struct intel_encoder *encoder;
4305
	int pipe = crtc->pipe;
4306
	u32 dpll, mdiv;
4307
	u32 bestn, bestm1, bestm2, bestp1, bestp2;
4308
	bool is_hdmi;
4309
	u32 coreclk, reg_val, dpll_md;
4310

4311 4312
	mutex_lock(&dev_priv->dpio_lock);

4313
	is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4314

4315 4316 4317 4318 4319
	bestn = crtc->config.dpll.n;
	bestm1 = crtc->config.dpll.m1;
	bestm2 = crtc->config.dpll.m2;
	bestp1 = crtc->config.dpll.p1;
	bestp2 = crtc->config.dpll.p2;
4320

4321 4322 4323 4324 4325 4326 4327
	/* See eDP HDMI DPIO driver vbios notes doc */

	/* PLL B needs special handling */
	if (pipe)
		vlv_pllb_recal_opamp(dev_priv);

	/* Set up Tx target for periodic Rcomp update */
4328
	vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4329 4330

	/* Disable target IRef on PLL */
4331
	reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4332
	reg_val &= 0x00ffffff;
4333
	vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4334 4335

	/* Disable fast lock */
4336
	vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4337 4338

	/* Set idtafcrecal before PLL is enabled */
4339 4340 4341 4342
	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
	mdiv |= ((bestn << DPIO_N_SHIFT));
	mdiv |= (1 << DPIO_K_SHIFT);
4343 4344 4345 4346 4347 4348 4349

	/*
	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
	 * but we don't support that).
	 * Note: don't use the DAC post divider as it seems unstable.
	 */
	mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4350
	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4351

4352
	mdiv |= DPIO_ENABLE_CALIBRATION;
4353
	vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4354

4355 4356 4357
	/* Set HBR and RBR LPF coefficients */
	if (adjusted_mode->clock == 162000 ||
	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4358
		vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4359 4360
				 0x005f0021);
	else
4361
		vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4362 4363 4364 4365 4366 4367
				 0x00d0000f);

	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
		/* Use SSC source */
		if (!pipe)
4368
			vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4369 4370
					 0x0df40000);
		else
4371
			vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4372 4373 4374 4375
					 0x0df70000);
	} else { /* HDMI or VGA */
		/* Use bend source */
		if (!pipe)
4376
			vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4377 4378
					 0x0df70000);
		else
4379
			vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4380 4381
					 0x0df40000);
	}
4382

4383
	coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4384 4385 4386 4387
	coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
		coreclk |= 0x01000000;
4388
	vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4389

4390
	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4391

4392 4393 4394
	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
		if (encoder->pre_pll_enable)
			encoder->pre_pll_enable(encoder);
4395

4396 4397 4398 4399 4400
	/* Enable DPIO clock input */
	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
	if (pipe)
		dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4401

4402
	dpll |= DPLL_VCO_ENABLE;
4403 4404 4405
	I915_WRITE(DPLL(pipe), dpll);
	POSTING_READ(DPLL(pipe));
	udelay(150);
4406

4407 4408 4409
	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		DRM_ERROR("DPLL %d failed to lock\n", pipe);

4410 4411 4412 4413
	dpll_md = 0;
	if (crtc->config.pixel_multiplier > 1) {
		dpll_md = (crtc->config.pixel_multiplier - 1)
			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
4414
	}
4415 4416
	I915_WRITE(DPLL_MD(pipe), dpll_md);
	POSTING_READ(DPLL_MD(pipe));
4417

4418 4419
	if (crtc->config.has_dp_encoder)
		intel_dp_set_m_n(crtc);
4420 4421

	mutex_unlock(&dev_priv->dpio_lock);
4422 4423
}

4424 4425
static void i9xx_update_pll(struct intel_crtc *crtc,
			    intel_clock_t *reduced_clock,
4426 4427
			    int num_connectors)
{
4428
	struct drm_device *dev = crtc->base.dev;
4429
	struct drm_i915_private *dev_priv = dev->dev_private;
4430
	struct intel_encoder *encoder;
4431
	int pipe = crtc->pipe;
4432 4433
	u32 dpll;
	bool is_sdvo;
4434
	struct dpll *clock = &crtc->config.dpll;
4435

4436
	i9xx_update_pll_dividers(crtc, reduced_clock);
4437

4438 4439
	is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
		intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4440 4441 4442

	dpll = DPLL_VGA_MODE_DIS;

4443
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4444 4445 4446
		dpll |= DPLLB_MODE_LVDS;
	else
		dpll |= DPLLB_MODE_DAC_SERIAL;
4447

4448 4449 4450 4451
	if ((crtc->config.pixel_multiplier > 1) &&
	    (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
		dpll |= (crtc->config.pixel_multiplier - 1)
			<< SDVO_MULTIPLIER_SHIFT_HIRES;
4452
	}
4453 4454 4455 4456

	if (is_sdvo)
		dpll |= DPLL_DVO_HIGH_SPEED;

4457
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484
		dpll |= DPLL_DVO_HIGH_SPEED;

	/* compute bitmask from p1 value */
	if (IS_PINEVIEW(dev))
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
	else {
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		if (IS_G4X(dev) && reduced_clock)
			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
	}
	switch (clock->p2) {
	case 5:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		break;
	case 7:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
		break;
	case 10:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		break;
	case 14:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
		break;
	}
	if (INTEL_INFO(dev)->gen >= 4)
		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);

4485
	if (crtc->config.sdvo_tv_clock)
4486
		dpll |= PLL_REF_INPUT_TVCLKINBC;
4487
	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4488 4489 4490 4491 4492 4493 4494 4495 4496 4497
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

	dpll |= DPLL_VCO_ENABLE;
	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
	POSTING_READ(DPLL(pipe));
	udelay(150);

4498
	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4499 4500
		if (encoder->pre_pll_enable)
			encoder->pre_pll_enable(encoder);
4501

4502 4503
	if (crtc->config.has_dp_encoder)
		intel_dp_set_m_n(crtc);
4504 4505 4506 4507 4508 4509 4510 4511

	I915_WRITE(DPLL(pipe), dpll);

	/* Wait for the clocks to stabilize. */
	POSTING_READ(DPLL(pipe));
	udelay(150);

	if (INTEL_INFO(dev)->gen >= 4) {
4512 4513 4514 4515
		u32 dpll_md = 0;
		if (crtc->config.pixel_multiplier > 1) {
			dpll_md = (crtc->config.pixel_multiplier - 1)
				<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
4516
		}
4517
		I915_WRITE(DPLL_MD(pipe), dpll_md);
4518 4519 4520 4521 4522 4523 4524 4525 4526 4527
	} else {
		/* The pixel multiplier can only be updated once the
		 * DPLL is enabled and the clocks are stable.
		 *
		 * So write it again.
		 */
		I915_WRITE(DPLL(pipe), dpll);
	}
}

4528
static void i8xx_update_pll(struct intel_crtc *crtc,
4529
			    struct drm_display_mode *adjusted_mode,
4530
			    intel_clock_t *reduced_clock,
4531 4532
			    int num_connectors)
{
4533
	struct drm_device *dev = crtc->base.dev;
4534
	struct drm_i915_private *dev_priv = dev->dev_private;
4535
	struct intel_encoder *encoder;
4536
	int pipe = crtc->pipe;
4537
	u32 dpll;
4538
	struct dpll *clock = &crtc->config.dpll;
4539

4540
	i9xx_update_pll_dividers(crtc, reduced_clock);
4541

4542 4543
	dpll = DPLL_VGA_MODE_DIS;

4544
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4545 4546 4547 4548 4549 4550 4551 4552 4553 4554
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
	} else {
		if (clock->p1 == 2)
			dpll |= PLL_P1_DIVIDE_BY_TWO;
		else
			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		if (clock->p2 == 4)
			dpll |= PLL_P2_DIVIDE_BY_4;
	}

4555
	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4556 4557 4558 4559 4560 4561 4562 4563 4564 4565
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

	dpll |= DPLL_VCO_ENABLE;
	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
	POSTING_READ(DPLL(pipe));
	udelay(150);

4566
	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4567 4568
		if (encoder->pre_pll_enable)
			encoder->pre_pll_enable(encoder);
4569

4570 4571 4572 4573 4574 4575
	I915_WRITE(DPLL(pipe), dpll);

	/* Wait for the clocks to stabilize. */
	POSTING_READ(DPLL(pipe));
	udelay(150);

4576 4577 4578 4579 4580 4581 4582 4583
	/* The pixel multiplier can only be updated once the
	 * DPLL is enabled and the clocks are stable.
	 *
	 * So write it again.
	 */
	I915_WRITE(DPLL(pipe), dpll);
}

4584 4585 4586 4587 4588 4589 4590
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
				   struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe = intel_crtc->pipe;
4591
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4592 4593 4594 4595 4596 4597
	uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;

	/* We need to be careful not to changed the adjusted mode, for otherwise
	 * the hw state checker will get angry at the mismatch. */
	crtc_vtotal = adjusted_mode->crtc_vtotal;
	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4598 4599 4600

	if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		/* the chip adds 2 halflines automatically */
4601 4602
		crtc_vtotal -= 1;
		crtc_vblank_end -= 1;
4603 4604 4605 4606 4607 4608 4609
		vsyncshift = adjusted_mode->crtc_hsync_start
			     - adjusted_mode->crtc_htotal / 2;
	} else {
		vsyncshift = 0;
	}

	if (INTEL_INFO(dev)->gen > 3)
4610
		I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4611

4612
	I915_WRITE(HTOTAL(cpu_transcoder),
4613 4614
		   (adjusted_mode->crtc_hdisplay - 1) |
		   ((adjusted_mode->crtc_htotal - 1) << 16));
4615
	I915_WRITE(HBLANK(cpu_transcoder),
4616 4617
		   (adjusted_mode->crtc_hblank_start - 1) |
		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
4618
	I915_WRITE(HSYNC(cpu_transcoder),
4619 4620 4621
		   (adjusted_mode->crtc_hsync_start - 1) |
		   ((adjusted_mode->crtc_hsync_end - 1) << 16));

4622
	I915_WRITE(VTOTAL(cpu_transcoder),
4623
		   (adjusted_mode->crtc_vdisplay - 1) |
4624
		   ((crtc_vtotal - 1) << 16));
4625
	I915_WRITE(VBLANK(cpu_transcoder),
4626
		   (adjusted_mode->crtc_vblank_start - 1) |
4627
		   ((crtc_vblank_end - 1) << 16));
4628
	I915_WRITE(VSYNC(cpu_transcoder),
4629 4630 4631
		   (adjusted_mode->crtc_vsync_start - 1) |
		   ((adjusted_mode->crtc_vsync_end - 1) << 16));

4632 4633 4634 4635 4636 4637 4638 4639
	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
	 * bits. */
	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
	    (pipe == PIPE_B || pipe == PIPE_C))
		I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));

4640 4641 4642 4643 4644 4645 4646
	/* pipesrc controls the size that is scaled from, which should
	 * always be the user's requested size.
	 */
	I915_WRITE(PIPESRC(pipe),
		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
}

4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685
static void intel_get_pipe_timings(struct intel_crtc *crtc,
				   struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
	uint32_t tmp;

	tmp = I915_READ(HTOTAL(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
	tmp = I915_READ(HBLANK(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
	tmp = I915_READ(HSYNC(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;

	tmp = I915_READ(VTOTAL(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
	tmp = I915_READ(VBLANK(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
	tmp = I915_READ(VSYNC(cpu_transcoder));
	pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
	pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;

	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
		pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
		pipe_config->adjusted_mode.crtc_vtotal += 1;
		pipe_config->adjusted_mode.crtc_vblank_end += 1;
	}

	tmp = I915_READ(PIPESRC(crtc->pipe));
	pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
	pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
}

4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t pipeconf;

	pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));

	if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		/* Enable pixel doubling when the dot clock is > 90% of the (display)
		 * core speed.
		 *
		 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		 * pipe == 0 check?
		 */
		if (intel_crtc->config.requested_mode.clock >
		    dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
			pipeconf |= PIPECONF_DOUBLE_WIDE;
		else
			pipeconf &= ~PIPECONF_DOUBLE_WIDE;
	}

4708 4709 4710 4711 4712 4713 4714 4715
	/* only g4x and later have fancy bpc/dither controls */
	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
		pipeconf &= ~(PIPECONF_BPC_MASK |
			      PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);

		/* Bspec claims that we can't use dithering for 30bpp pipes. */
		if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
			pipeconf |= PIPECONF_DITHER_EN |
4716 4717
				    PIPECONF_DITHER_TYPE_SP;

4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730
		switch (intel_crtc->config.pipe_bpp) {
		case 18:
			pipeconf |= PIPECONF_6BPC;
			break;
		case 24:
			pipeconf |= PIPECONF_8BPC;
			break;
		case 30:
			pipeconf |= PIPECONF_10BPC;
			break;
		default:
			/* Case prevented by intel_choose_pipe_bpp_dither. */
			BUG();
4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750
		}
	}

	if (HAS_PIPE_CXSR(dev)) {
		if (intel_crtc->lowfreq_avail) {
			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
		} else {
			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
			pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		}
	}

	pipeconf &= ~PIPECONF_INTERLACE_MASK;
	if (!IS_GEN2(dev) &&
	    intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
	else
		pipeconf |= PIPECONF_PROGRESSIVE;

4751 4752 4753 4754 4755 4756 4757
	if (IS_VALLEYVIEW(dev)) {
		if (intel_crtc->config.limited_color_range)
			pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
		else
			pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
	}

4758 4759 4760 4761
	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
	POSTING_READ(PIPECONF(intel_crtc->pipe));
}

4762 4763
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
			      int x, int y,
4764
			      struct drm_framebuffer *fb)
J
Jesse Barnes 已提交
4765 4766 4767 4768
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4769 4770 4771
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;
	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
J
Jesse Barnes 已提交
4772
	int pipe = intel_crtc->pipe;
4773
	int plane = intel_crtc->plane;
4774
	int refclk, num_connectors = 0;
4775
	intel_clock_t clock, reduced_clock;
4776
	u32 dspcntr;
4777 4778
	bool ok, has_reduced_clock = false;
	bool is_lvds = false;
4779
	struct intel_encoder *encoder;
4780
	const intel_limit_t *limit;
4781
	int ret;
J
Jesse Barnes 已提交
4782

4783
	for_each_encoder_on_crtc(dev, crtc, encoder) {
4784
		switch (encoder->type) {
J
Jesse Barnes 已提交
4785 4786 4787 4788
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		}
4789

4790
		num_connectors++;
J
Jesse Barnes 已提交
4791 4792
	}

4793
	refclk = i9xx_get_refclk(crtc, num_connectors);
J
Jesse Barnes 已提交
4794

4795 4796 4797 4798 4799
	/*
	 * Returns a set of divisors for the desired target clock with the given
	 * refclk, or FALSE.  The returned values represent the clock equation:
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
	 */
4800
	limit = intel_limit(crtc, refclk);
4801 4802
	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
			     &clock);
J
Jesse Barnes 已提交
4803 4804
	if (!ok) {
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
4805
		return -EINVAL;
J
Jesse Barnes 已提交
4806 4807
	}

4808
	/* Ensure that the cursor is valid for the new mode before changing... */
4809
	intel_crtc_update_cursor(crtc, true);
4810

4811
	if (is_lvds && dev_priv->lvds_downclock_avail) {
4812 4813 4814 4815 4816 4817
		/*
		 * Ensure we match the reduced clock's P to the target clock.
		 * If the clocks don't match, we can't switch the display clock
		 * by using the FP0/FP1. In such case we will disable the LVDS
		 * downclock feature.
		*/
4818
		has_reduced_clock = limit->find_pll(limit, crtc,
4819 4820
						    dev_priv->lvds_downclock,
						    refclk,
4821
						    &clock,
4822
						    &reduced_clock);
Z
Zhenyu Wang 已提交
4823
	}
4824 4825 4826 4827 4828 4829 4830 4831
	/* Compat-code for transition, will disappear. */
	if (!intel_crtc->config.clock_set) {
		intel_crtc->config.dpll.n = clock.n;
		intel_crtc->config.dpll.m1 = clock.m1;
		intel_crtc->config.dpll.m2 = clock.m2;
		intel_crtc->config.dpll.p1 = clock.p1;
		intel_crtc->config.dpll.p2 = clock.p2;
	}
Z
Zhenyu Wang 已提交
4832

4833
	if (IS_GEN2(dev))
4834
		i8xx_update_pll(intel_crtc, adjusted_mode,
4835 4836
				has_reduced_clock ? &reduced_clock : NULL,
				num_connectors);
4837
	else if (IS_VALLEYVIEW(dev))
4838
		vlv_update_pll(intel_crtc);
J
Jesse Barnes 已提交
4839
	else
4840
		i9xx_update_pll(intel_crtc,
4841
				has_reduced_clock ? &reduced_clock : NULL,
4842
                                num_connectors);
J
Jesse Barnes 已提交
4843 4844 4845 4846

	/* Set up the display plane register */
	dspcntr = DISPPLANE_GAMMA_ENABLE;

4847 4848 4849 4850 4851 4852
	if (!IS_VALLEYVIEW(dev)) {
		if (pipe == 0)
			dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		else
			dspcntr |= DISPPLANE_SEL_PIPE_B;
	}
J
Jesse Barnes 已提交
4853

4854
	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4855 4856 4857

	/* pipesrc and dspsize control the size that is scaled from,
	 * which should always be the user's requested size.
J
Jesse Barnes 已提交
4858
	 */
4859 4860 4861 4862
	I915_WRITE(DSPSIZE(plane),
		   ((mode->vdisplay - 1) << 16) |
		   (mode->hdisplay - 1));
	I915_WRITE(DSPPOS(plane), 0);
4863

4864 4865
	i9xx_set_pipeconf(intel_crtc);

4866 4867 4868
	I915_WRITE(DSPCNTR(plane), dspcntr);
	POSTING_READ(DSPCNTR(plane));

4869
	ret = intel_pipe_set_base(crtc, x, y, fb);
4870 4871 4872 4873 4874 4875

	intel_update_watermarks(dev);

	return ret;
}

4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905
static void i9xx_get_pfit_config(struct intel_crtc *crtc,
				 struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

	tmp = I915_READ(PFIT_CONTROL);

	if (INTEL_INFO(dev)->gen < 4) {
		if (crtc->pipe != PIPE_B)
			return;

		/* gen2/3 store dither state in pfit control, needs to match */
		pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
	} else {
		if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
			return;
	}

	if (!(tmp & PFIT_ENABLE))
		return;

	pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
	pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
	if (INTEL_INFO(dev)->gen < 5)
		pipe_config->gmch_pfit.lvds_border_bits =
			I915_READ(LVDS) & LVDS_BORDER_ENABLE;
}

4906 4907 4908 4909 4910 4911 4912
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
				 struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

4913 4914
	pipe_config->cpu_transcoder = crtc->pipe;

4915 4916 4917 4918
	tmp = I915_READ(PIPECONF(crtc->pipe));
	if (!(tmp & PIPECONF_ENABLE))
		return false;

4919 4920
	intel_get_pipe_timings(crtc, pipe_config);

4921 4922
	i9xx_get_pfit_config(crtc, pipe_config);

4923 4924 4925
	return true;
}

P
Paulo Zanoni 已提交
4926
static void ironlake_init_pch_refclk(struct drm_device *dev)
4927 4928 4929 4930
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
4931
	u32 val, final;
4932
	bool has_lvds = false;
4933 4934
	bool has_cpu_edp = false;
	bool has_panel = false;
4935 4936
	bool has_ck505 = false;
	bool can_ssc = false;
4937 4938

	/* We need to take the global config into account */
4939 4940 4941 4942 4943 4944 4945 4946 4947
	list_for_each_entry(encoder, &mode_config->encoder_list,
			    base.head) {
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			has_panel = true;
			has_lvds = true;
			break;
		case INTEL_OUTPUT_EDP:
			has_panel = true;
4948
			if (enc_to_dig_port(&encoder->base)->port == PORT_A)
4949 4950
				has_cpu_edp = true;
			break;
4951 4952 4953
		}
	}

4954
	if (HAS_PCH_IBX(dev)) {
4955
		has_ck505 = dev_priv->vbt.display_clock_mode;
4956 4957 4958 4959 4960 4961
		can_ssc = has_ck505;
	} else {
		has_ck505 = false;
		can_ssc = true;
	}

4962 4963
	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
		      has_panel, has_lvds, has_ck505);
4964 4965 4966 4967 4968 4969

	/* Ironlake: try to setup display ref clock before DPLL
	 * enabling. This is only under driver's control after
	 * PCH B stepping, previous chipset stepping should be
	 * ignoring this setting.
	 */
4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007
	val = I915_READ(PCH_DREF_CONTROL);

	/* As we must carefully and slowly disable/enable each source in turn,
	 * compute the final state we want first and check if we need to
	 * make any changes at all.
	 */
	final = val;
	final &= ~DREF_NONSPREAD_SOURCE_MASK;
	if (has_ck505)
		final |= DREF_NONSPREAD_CK505_ENABLE;
	else
		final |= DREF_NONSPREAD_SOURCE_ENABLE;

	final &= ~DREF_SSC_SOURCE_MASK;
	final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
	final &= ~DREF_SSC1_ENABLE;

	if (has_panel) {
		final |= DREF_SSC_SOURCE_ENABLE;

		if (intel_panel_use_ssc(dev_priv) && can_ssc)
			final |= DREF_SSC1_ENABLE;

		if (has_cpu_edp) {
			if (intel_panel_use_ssc(dev_priv) && can_ssc)
				final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
			else
				final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
		} else
			final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
	} else {
		final |= DREF_SSC_SOURCE_DISABLE;
		final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
	}

	if (final == val)
		return;

5008
	/* Always enable nonspread source */
5009
	val &= ~DREF_NONSPREAD_SOURCE_MASK;
5010

5011
	if (has_ck505)
5012
		val |= DREF_NONSPREAD_CK505_ENABLE;
5013
	else
5014
		val |= DREF_NONSPREAD_SOURCE_ENABLE;
5015

5016
	if (has_panel) {
5017 5018
		val &= ~DREF_SSC_SOURCE_MASK;
		val |= DREF_SSC_SOURCE_ENABLE;
5019

5020
		/* SSC must be turned on before enabling the CPU output  */
5021
		if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5022
			DRM_DEBUG_KMS("Using SSC on panel\n");
5023
			val |= DREF_SSC1_ENABLE;
5024
		} else
5025
			val &= ~DREF_SSC1_ENABLE;
5026 5027

		/* Get SSC going before enabling the outputs */
5028
		I915_WRITE(PCH_DREF_CONTROL, val);
5029 5030 5031
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);

5032
		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5033 5034

		/* Enable CPU source on CPU attached eDP */
5035
		if (has_cpu_edp) {
5036
			if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5037
				DRM_DEBUG_KMS("Using SSC on eDP\n");
5038
				val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5039
			}
5040
			else
5041
				val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5042
		} else
5043
			val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5044

5045
		I915_WRITE(PCH_DREF_CONTROL, val);
5046 5047 5048 5049 5050
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);
	} else {
		DRM_DEBUG_KMS("Disabling SSC entirely\n");

5051
		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5052 5053

		/* Turn off CPU output */
5054
		val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5055

5056
		I915_WRITE(PCH_DREF_CONTROL, val);
5057 5058 5059 5060
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);

		/* Turn off the SSC source */
5061 5062
		val &= ~DREF_SSC_SOURCE_MASK;
		val |= DREF_SSC_SOURCE_DISABLE;
5063 5064

		/* Turn off SSC1 */
5065
		val &= ~DREF_SSC1_ENABLE;
5066

5067
		I915_WRITE(PCH_DREF_CONTROL, val);
5068 5069 5070
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);
	}
5071 5072

	BUG_ON(val != final);
5073 5074
}

P
Paulo Zanoni 已提交
5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095
/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
static void lpt_init_pch_refclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
	bool has_vga = false;
	bool is_sdv = false;
	u32 tmp;

	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		switch (encoder->type) {
		case INTEL_OUTPUT_ANALOG:
			has_vga = true;
			break;
		}
	}

	if (!has_vga)
		return;

5096 5097
	mutex_lock(&dev_priv->dpio_lock);

P
Paulo Zanoni 已提交
5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232
	/* XXX: Rip out SDV support once Haswell ships for real. */
	if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
		is_sdv = true;

	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
	tmp &= ~SBI_SSCCTL_DISABLE;
	tmp |= SBI_SSCCTL_PATHALT;
	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);

	udelay(24);

	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
	tmp &= ~SBI_SSCCTL_PATHALT;
	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);

	if (!is_sdv) {
		tmp = I915_READ(SOUTH_CHICKEN2);
		tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
		I915_WRITE(SOUTH_CHICKEN2, tmp);

		if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
				       FDI_MPHY_IOSFSB_RESET_STATUS, 100))
			DRM_ERROR("FDI mPHY reset assert timeout\n");

		tmp = I915_READ(SOUTH_CHICKEN2);
		tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
		I915_WRITE(SOUTH_CHICKEN2, tmp);

		if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
				        FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
				       100))
			DRM_ERROR("FDI mPHY reset de-assert timeout\n");
	}

	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
	tmp &= ~(0xFF << 24);
	tmp |= (0x12 << 24);
	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);

	if (is_sdv) {
		tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
		tmp |= 0x7FFF;
		intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
	}

	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
	tmp |= (1 << 11);
	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
	tmp |= (1 << 11);
	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);

	if (is_sdv) {
		tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
		tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
		intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
		tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
		intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
		tmp |= (0x3F << 8);
		intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
		tmp |= (0x3F << 8);
		intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
	}

	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
	tmp |= (1 << 24) | (1 << 21) | (1 << 18);
	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
	tmp |= (1 << 24) | (1 << 21) | (1 << 18);
	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);

	if (!is_sdv) {
		tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
		tmp &= ~(7 << 13);
		tmp |= (5 << 13);
		intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
		tmp &= ~(7 << 13);
		tmp |= (5 << 13);
		intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
	}

	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
	tmp &= ~0xFF;
	tmp |= 0x1C;
	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
	tmp &= ~0xFF;
	tmp |= 0x1C;
	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
	tmp &= ~(0xFF << 16);
	tmp |= (0x1C << 16);
	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);

	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
	tmp &= ~(0xFF << 16);
	tmp |= (0x1C << 16);
	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);

	if (!is_sdv) {
		tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
		tmp |= (1 << 27);
		intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
		tmp |= (1 << 27);
		intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
		tmp &= ~(0xF << 28);
		tmp |= (4 << 28);
		intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);

		tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
		tmp &= ~(0xF << 28);
		tmp |= (4 << 28);
		intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
	}

	/* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
	tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
	tmp |= SBI_DBUFF0_ENABLE;
	intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5233 5234

	mutex_unlock(&dev_priv->dpio_lock);
P
Paulo Zanoni 已提交
5235 5236 5237 5238 5239 5240 5241 5242 5243 5244 5245 5246 5247
}

/*
 * Initialize reference clocks when the driver loads
 */
void intel_init_pch_refclk(struct drm_device *dev)
{
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
		ironlake_init_pch_refclk(dev);
	else if (HAS_PCH_LPT(dev))
		lpt_init_pch_refclk(dev);
}

5248 5249 5250 5251 5252 5253 5254 5255
static int ironlake_get_refclk(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
	int num_connectors = 0;
	bool is_lvds = false;

5256
	for_each_encoder_on_crtc(dev, crtc, encoder) {
5257 5258 5259 5260 5261 5262 5263 5264 5265 5266
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		}
		num_connectors++;
	}

	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5267 5268
			      dev_priv->vbt.lvds_ssc_freq);
		return dev_priv->vbt.lvds_ssc_freq * 1000;
5269 5270 5271 5272 5273
	}

	return 120000;
}

5274
static void ironlake_set_pipeconf(struct drm_crtc *crtc)
J
Jesse Barnes 已提交
5275
{
5276
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
J
Jesse Barnes 已提交
5277 5278
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
5279 5280 5281 5282
	uint32_t val;

	val = I915_READ(PIPECONF(pipe));

5283
	val &= ~PIPECONF_BPC_MASK;
5284
	switch (intel_crtc->config.pipe_bpp) {
5285
	case 18:
5286
		val |= PIPECONF_6BPC;
5287 5288
		break;
	case 24:
5289
		val |= PIPECONF_8BPC;
5290 5291
		break;
	case 30:
5292
		val |= PIPECONF_10BPC;
5293 5294
		break;
	case 36:
5295
		val |= PIPECONF_12BPC;
5296 5297
		break;
	default:
5298 5299
		/* Case prevented by intel_choose_pipe_bpp_dither. */
		BUG();
5300 5301 5302
	}

	val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5303
	if (intel_crtc->config.dither)
5304 5305 5306
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);

	val &= ~PIPECONF_INTERLACE_MASK;
5307
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5308 5309 5310 5311
		val |= PIPECONF_INTERLACED_ILK;
	else
		val |= PIPECONF_PROGRESSIVE;

5312
	if (intel_crtc->config.limited_color_range)
5313 5314 5315 5316
		val |= PIPECONF_COLOR_RANGE_SELECT;
	else
		val &= ~PIPECONF_COLOR_RANGE_SELECT;

5317 5318 5319 5320
	I915_WRITE(PIPECONF(pipe), val);
	POSTING_READ(PIPECONF(pipe));
}

5321 5322 5323 5324 5325 5326 5327
/*
 * Set up the pipe CSC unit.
 *
 * Currently only full range RGB to limited range RGB conversion
 * is supported, but eventually this should handle various
 * RGB<->YCbCr scenarios as well.
 */
5328
static void intel_set_pipe_csc(struct drm_crtc *crtc)
5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	uint16_t coeff = 0x7800; /* 1.0 */

	/*
	 * TODO: Check what kind of values actually come out of the pipe
	 * with these coeff/postoff values and adjust to get the best
	 * accuracy. Perhaps we even need to take the bpc value into
	 * consideration.
	 */

5343
	if (intel_crtc->config.limited_color_range)
5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366
		coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */

	/*
	 * GY/GU and RY/RU should be the other way around according
	 * to BSpec, but reality doesn't agree. Just set them up in
	 * a way that results in the correct picture.
	 */
	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);

	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);

	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);

	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);

	if (INTEL_INFO(dev)->gen > 6) {
		uint16_t postoff = 0;

5367
		if (intel_crtc->config.limited_color_range)
5368 5369 5370 5371 5372 5373 5374 5375 5376 5377
			postoff = (16 * (1 << 13) / 255) & 0x1fff;

		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);

		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
	} else {
		uint32_t mode = CSC_MODE_YUV_TO_RGB;

5378
		if (intel_crtc->config.limited_color_range)
5379 5380 5381 5382 5383 5384
			mode |= CSC_BLACK_SCREEN_OFFSET;

		I915_WRITE(PIPE_CSC_MODE(pipe), mode);
	}
}

5385
static void haswell_set_pipeconf(struct drm_crtc *crtc)
P
Paulo Zanoni 已提交
5386 5387 5388
{
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5389
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
P
Paulo Zanoni 已提交
5390 5391
	uint32_t val;

5392
	val = I915_READ(PIPECONF(cpu_transcoder));
P
Paulo Zanoni 已提交
5393 5394

	val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5395
	if (intel_crtc->config.dither)
P
Paulo Zanoni 已提交
5396 5397 5398
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);

	val &= ~PIPECONF_INTERLACE_MASK_HSW;
5399
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
P
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5400 5401 5402 5403
		val |= PIPECONF_INTERLACED_ILK;
	else
		val |= PIPECONF_PROGRESSIVE;

5404 5405
	I915_WRITE(PIPECONF(cpu_transcoder), val);
	POSTING_READ(PIPECONF(cpu_transcoder));
P
Paulo Zanoni 已提交
5406 5407
}

5408 5409 5410 5411 5412 5413 5414 5415 5416 5417
static bool ironlake_compute_clocks(struct drm_crtc *crtc,
				    struct drm_display_mode *adjusted_mode,
				    intel_clock_t *clock,
				    bool *has_reduced_clock,
				    intel_clock_t *reduced_clock)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	int refclk;
5418
	const intel_limit_t *limit;
5419
	bool ret, is_lvds = false;
J
Jesse Barnes 已提交
5420

5421 5422
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		switch (intel_encoder->type) {
J
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5423 5424 5425 5426 5427 5428
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		}
	}

5429
	refclk = ironlake_get_refclk(crtc);
J
Jesse Barnes 已提交
5430

5431 5432 5433 5434 5435
	/*
	 * Returns a set of divisors for the desired target clock with the given
	 * refclk, or FALSE.  The returned values represent the clock equation:
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
	 */
5436
	limit = intel_limit(crtc, refclk);
5437 5438 5439 5440
	ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
			      clock);
	if (!ret)
		return false;
5441

5442
	if (is_lvds && dev_priv->lvds_downclock_avail) {
5443 5444 5445 5446 5447 5448
		/*
		 * Ensure we match the reduced clock's P to the target clock.
		 * If the clocks don't match, we can't switch the display clock
		 * by using the FP0/FP1. In such case we will disable the LVDS
		 * downclock feature.
		*/
5449 5450 5451 5452 5453
		*has_reduced_clock = limit->find_pll(limit, crtc,
						     dev_priv->lvds_downclock,
						     refclk,
						     clock,
						     reduced_clock);
5454
	}
5455

5456 5457 5458
	return true;
}

5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476
static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t temp;

	temp = I915_READ(SOUTH_CHICKEN1);
	if (temp & FDI_BC_BIFURCATION_SELECT)
		return;

	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);

	temp |= FDI_BC_BIFURCATION_SELECT;
	DRM_DEBUG_KMS("enabling fdi C rx\n");
	I915_WRITE(SOUTH_CHICKEN1, temp);
	POSTING_READ(SOUTH_CHICKEN1);
}

5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492
static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	switch (intel_crtc->pipe) {
	case PIPE_A:
		break;
	case PIPE_B:
		if (intel_crtc->config.fdi_lanes > 2)
			WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
		else
			cpt_enable_fdi_bc_bifurcation(dev);

		break;
	case PIPE_C:
5493 5494
		cpt_enable_fdi_bc_bifurcation(dev);

5495
		break;
5496 5497 5498 5499 5500
	default:
		BUG();
	}
}

5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
{
	/*
	 * Account for spread spectrum to avoid
	 * oversubscribing the link. Max center spread
	 * is 2.5%; use 5% for safety's sake.
	 */
	u32 bps = target_clock * bpp * 21 / 20;
	return bps / (link_bw * 8) + 1;
}

5512 5513 5514 5515 5516
static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
{
	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
}

5517
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5518
				      u32 *fp,
5519
				      intel_clock_t *reduced_clock, u32 *fp2)
J
Jesse Barnes 已提交
5520
{
5521
	struct drm_crtc *crtc = &intel_crtc->base;
J
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5522 5523
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
5524 5525
	struct intel_encoder *intel_encoder;
	uint32_t dpll;
5526
	int factor, num_connectors = 0;
5527
	bool is_lvds = false, is_sdvo = false;
J
Jesse Barnes 已提交
5528

5529 5530
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		switch (intel_encoder->type) {
J
Jesse Barnes 已提交
5531 5532 5533 5534
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_SDVO:
5535
		case INTEL_OUTPUT_HDMI:
J
Jesse Barnes 已提交
5536 5537 5538
			is_sdvo = true;
			break;
		}
5539

5540
		num_connectors++;
J
Jesse Barnes 已提交
5541 5542
	}

5543
	/* Enable autotuning of the PLL clock (if permissible) */
5544 5545 5546
	factor = 21;
	if (is_lvds) {
		if ((intel_panel_use_ssc(dev_priv) &&
5547
		     dev_priv->vbt.lvds_ssc_freq == 100) ||
5548
		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5549
			factor = 25;
5550
	} else if (intel_crtc->config.sdvo_tv_clock)
5551
		factor = 20;
5552

5553
	if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5554
		*fp |= FP_CB_TUNE;
5555

5556 5557 5558
	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
		*fp2 |= FP_CB_TUNE;

5559
	dpll = 0;
5560

5561 5562 5563 5564
	if (is_lvds)
		dpll |= DPLLB_MODE_LVDS;
	else
		dpll |= DPLLB_MODE_DAC_SERIAL;
5565 5566 5567 5568

	if (intel_crtc->config.pixel_multiplier > 1) {
		dpll |= (intel_crtc->config.pixel_multiplier - 1)
			<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5569
	}
5570 5571 5572

	if (is_sdvo)
		dpll |= DPLL_DVO_HIGH_SPEED;
5573
	if (intel_crtc->config.has_dp_encoder)
5574
		dpll |= DPLL_DVO_HIGH_SPEED;
J
Jesse Barnes 已提交
5575

5576
	/* compute bitmask from p1 value */
5577
	dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5578
	/* also FPA1 */
5579
	dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5580

5581
	switch (intel_crtc->config.dpll.p2) {
5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592 5593
	case 5:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		break;
	case 7:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
		break;
	case 10:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		break;
	case 14:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
		break;
J
Jesse Barnes 已提交
5594 5595
	}

5596
	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5597
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
J
Jesse Barnes 已提交
5598 5599 5600
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

5601 5602 5603 5604 5605 5606 5607 5608 5609 5610
	return dpll;
}

static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
				  int x, int y,
				  struct drm_framebuffer *fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5611 5612 5613
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;
	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5614 5615 5616 5617
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	int num_connectors = 0;
	intel_clock_t clock, reduced_clock;
5618
	u32 dpll = 0, fp = 0, fp2 = 0;
5619
	bool ok, has_reduced_clock = false;
5620
	bool is_lvds = false;
5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631
	struct intel_encoder *encoder;
	int ret;

	for_each_encoder_on_crtc(dev, crtc, encoder) {
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		}

		num_connectors++;
5632
	}
J
Jesse Barnes 已提交
5633

5634 5635
	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5636

5637 5638 5639 5640 5641
	ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
				     &has_reduced_clock, &reduced_clock);
	if (!ok) {
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
		return -EINVAL;
J
Jesse Barnes 已提交
5642
	}
5643 5644 5645 5646 5647 5648 5649 5650
	/* Compat-code for transition, will disappear. */
	if (!intel_crtc->config.clock_set) {
		intel_crtc->config.dpll.n = clock.n;
		intel_crtc->config.dpll.m1 = clock.m1;
		intel_crtc->config.dpll.m2 = clock.m2;
		intel_crtc->config.dpll.p1 = clock.p1;
		intel_crtc->config.dpll.p2 = clock.p2;
	}
J
Jesse Barnes 已提交
5651

5652 5653 5654
	/* Ensure that the cursor is valid for the new mode before changing... */
	intel_crtc_update_cursor(crtc, true);

5655
	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5656
	if (intel_crtc->config.has_pch_encoder) {
5657
		struct intel_pch_pll *pll;
5658

5659
		fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5660
		if (has_reduced_clock)
5661
			fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5662

5663
		dpll = ironlake_compute_dpll(intel_crtc,
5664 5665 5666
					     &fp, &reduced_clock,
					     has_reduced_clock ? &fp2 : NULL);

5667 5668
		pll = intel_get_pch_pll(intel_crtc, dpll, fp);
		if (pll == NULL) {
5669 5670
			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
					 pipe_name(pipe));
5671 5672
			return -EINVAL;
		}
5673 5674
	} else
		intel_put_pch_pll(intel_crtc);
J
Jesse Barnes 已提交
5675

5676 5677
	if (intel_crtc->config.has_dp_encoder)
		intel_dp_set_m_n(intel_crtc);
J
Jesse Barnes 已提交
5678

5679 5680 5681
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_pll_enable)
			encoder->pre_pll_enable(encoder);
J
Jesse Barnes 已提交
5682

5683 5684
	if (intel_crtc->pch_pll) {
		I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5685

5686
		/* Wait for the clocks to stabilize. */
5687
		POSTING_READ(intel_crtc->pch_pll->pll_reg);
5688 5689
		udelay(150);

5690 5691 5692 5693 5694
		/* The pixel multiplier can only be updated once the
		 * DPLL is enabled and the clocks are stable.
		 *
		 * So write it again.
		 */
5695
		I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
J
Jesse Barnes 已提交
5696 5697
	}

5698
	intel_crtc->lowfreq_avail = false;
5699
	if (intel_crtc->pch_pll) {
5700
		if (is_lvds && has_reduced_clock && i915_powersave) {
5701
			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5702 5703
			intel_crtc->lowfreq_avail = true;
		} else {
5704
			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5705 5706 5707
		}
	}

5708
	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5709

5710 5711 5712 5713
	if (intel_crtc->config.has_pch_encoder) {
		intel_cpu_transcoder_set_m_n(intel_crtc,
					     &intel_crtc->config.fdi_m_n);
	}
5714

5715 5716
	if (IS_IVYBRIDGE(dev))
		ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5717

5718
	ironlake_set_pipeconf(crtc);
J
Jesse Barnes 已提交
5719

5720 5721
	/* Set up the display plane register */
	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5722
	POSTING_READ(DSPCNTR(plane));
J
Jesse Barnes 已提交
5723

5724
	ret = intel_pipe_set_base(crtc, x, y, fb);
5725 5726 5727

	intel_update_watermarks(dev);

5728
	return ret;
J
Jesse Barnes 已提交
5729 5730
}

5731 5732 5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746
static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
					struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum transcoder transcoder = pipe_config->cpu_transcoder;

	pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
	pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
	pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
					& ~TU_SIZE_MASK;
	pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
	pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
				   & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
}

5747 5748 5749 5750 5751 5752 5753 5754 5755 5756 5757 5758 5759 5760 5761
static void ironlake_get_pfit_config(struct intel_crtc *crtc,
				     struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

	tmp = I915_READ(PF_CTL(crtc->pipe));

	if (tmp & PF_ENABLE) {
		pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
		pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
	}
}

5762 5763 5764 5765 5766 5767 5768
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
				     struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

5769 5770
	pipe_config->cpu_transcoder = crtc->pipe;

5771 5772 5773 5774
	tmp = I915_READ(PIPECONF(crtc->pipe));
	if (!(tmp & PIPECONF_ENABLE))
		return false;

5775
	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5776 5777
		pipe_config->has_pch_encoder = true;

5778 5779 5780
		tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
5781 5782

		ironlake_get_fdi_m_n_config(crtc, pipe_config);
5783 5784
	}

5785 5786
	intel_get_pipe_timings(crtc, pipe_config);

5787 5788
	ironlake_get_pfit_config(crtc, pipe_config);

5789 5790 5791
	return true;
}

5792 5793 5794 5795 5796 5797 5798 5799 5800 5801 5802 5803
static void haswell_modeset_global_resources(struct drm_device *dev)
{
	bool enable = false;
	struct intel_crtc *crtc;
	struct intel_encoder *encoder;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
		if (crtc->pipe != PIPE_A && crtc->base.enabled)
			enable = true;
		/* XXX: Should check for edp transcoder here, but thanks to init
		 * sequence that's not yet available. Just in case desktop eDP
		 * on PORT D is possible on haswell, too. */
5804
		/* Even the eDP panel fitter is outside the always-on well. */
5805
		if (crtc->config.pch_pfit.size && crtc->base.enabled)
5806
			enable = true;
5807 5808 5809 5810 5811 5812 5813 5814 5815 5816 5817 5818
	}

	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		if (encoder->type != INTEL_OUTPUT_EDP &&
		    encoder->connectors_active)
			enable = true;
	}

	intel_set_power_well(dev, enable);
}

P
Paulo Zanoni 已提交
5819 5820 5821 5822 5823 5824 5825
static int haswell_crtc_mode_set(struct drm_crtc *crtc,
				 int x, int y,
				 struct drm_framebuffer *fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5826 5827 5828
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;
	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
P
Paulo Zanoni 已提交
5829 5830 5831
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	int num_connectors = 0;
5832
	bool is_cpu_edp = false;
P
Paulo Zanoni 已提交
5833 5834 5835 5836 5837 5838
	struct intel_encoder *encoder;
	int ret;

	for_each_encoder_on_crtc(dev, crtc, encoder) {
		switch (encoder->type) {
		case INTEL_OUTPUT_EDP:
5839
			if (enc_to_dig_port(&encoder->base)->port == PORT_A)
P
Paulo Zanoni 已提交
5840 5841 5842 5843 5844 5845 5846
				is_cpu_edp = true;
			break;
		}

		num_connectors++;
	}

5847 5848 5849
	WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
	     num_connectors, pipe_name(pipe));

5850 5851 5852
	if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
		return -EINVAL;

P
Paulo Zanoni 已提交
5853 5854 5855
	/* Ensure that the cursor is valid for the new mode before changing... */
	intel_crtc_update_cursor(crtc, true);

5856 5857
	if (intel_crtc->config.has_dp_encoder)
		intel_dp_set_m_n(intel_crtc);
P
Paulo Zanoni 已提交
5858 5859 5860 5861 5862

	intel_crtc->lowfreq_avail = false;

	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);

5863 5864 5865 5866
	if (intel_crtc->config.has_pch_encoder) {
		intel_cpu_transcoder_set_m_n(intel_crtc,
					     &intel_crtc->config.fdi_m_n);
	}
P
Paulo Zanoni 已提交
5867

5868
	haswell_set_pipeconf(crtc);
P
Paulo Zanoni 已提交
5869

5870
	intel_set_pipe_csc(crtc);
5871

P
Paulo Zanoni 已提交
5872
	/* Set up the display plane register */
5873
	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
P
Paulo Zanoni 已提交
5874 5875 5876 5877 5878 5879
	POSTING_READ(DSPCNTR(plane));

	ret = intel_pipe_set_base(crtc, x, y, fb);

	intel_update_watermarks(dev);

5880
	return ret;
J
Jesse Barnes 已提交
5881 5882
}

5883 5884 5885 5886 5887
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
				    struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
5888
	enum intel_display_power_domain pfit_domain;
5889 5890
	uint32_t tmp;

5891 5892 5893 5894 5895 5896 5897 5898 5899 5900 5901 5902 5903 5904 5905 5906 5907 5908 5909 5910 5911 5912 5913
	pipe_config->cpu_transcoder = crtc->pipe;
	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
	if (tmp & TRANS_DDI_FUNC_ENABLE) {
		enum pipe trans_edp_pipe;
		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		default:
			WARN(1, "unknown pipe linked to edp transcoder\n");
		case TRANS_DDI_EDP_INPUT_A_ONOFF:
		case TRANS_DDI_EDP_INPUT_A_ON:
			trans_edp_pipe = PIPE_A;
			break;
		case TRANS_DDI_EDP_INPUT_B_ONOFF:
			trans_edp_pipe = PIPE_B;
			break;
		case TRANS_DDI_EDP_INPUT_C_ONOFF:
			trans_edp_pipe = PIPE_C;
			break;
		}

		if (trans_edp_pipe == crtc->pipe)
			pipe_config->cpu_transcoder = TRANSCODER_EDP;
	}

5914
	if (!intel_display_power_enabled(dev,
5915
			POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5916 5917
		return false;

5918
	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5919 5920 5921
	if (!(tmp & PIPECONF_ENABLE))
		return false;

5922
	/*
5923
	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5924 5925 5926
	 * DDI E. So just check whether this pipe is wired to DDI E and whether
	 * the PCH transcoder is on.
	 */
5927
	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5928
	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5929
	    I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5930 5931
		pipe_config->has_pch_encoder = true;

5932 5933 5934
		tmp = I915_READ(FDI_RX_CTL(PIPE_A));
		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
5935 5936

		ironlake_get_fdi_m_n_config(crtc, pipe_config);
5937 5938
	}

5939 5940
	intel_get_pipe_timings(crtc, pipe_config);

5941 5942 5943 5944
	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
	if (intel_display_power_enabled(dev, pfit_domain))
		ironlake_get_pfit_config(crtc, pipe_config);

5945 5946 5947
	return true;
}

5948 5949
static int intel_crtc_mode_set(struct drm_crtc *crtc,
			       int x, int y,
5950
			       struct drm_framebuffer *fb)
5951 5952 5953
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
5954 5955
	struct drm_encoder_helper_funcs *encoder_funcs;
	struct intel_encoder *encoder;
5956
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5957 5958 5959
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;
	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5960
	int pipe = intel_crtc->pipe;
5961 5962
	int ret;

5963
	drm_vblank_pre_modeset(dev, pipe);
5964

5965 5966
	ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);

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Jesse Barnes 已提交
5967
	drm_vblank_post_modeset(dev, pipe);
5968

5969 5970 5971 5972 5973 5974 5975 5976
	if (ret != 0)
		return ret;

	for_each_encoder_on_crtc(dev, crtc, encoder) {
		DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
			encoder->base.base.id,
			drm_get_encoder_name(&encoder->base),
			mode->base.id, mode->name);
5977 5978 5979 5980 5981 5982
		if (encoder->mode_set) {
			encoder->mode_set(encoder);
		} else {
			encoder_funcs = encoder->base.helper_private;
			encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
		}
5983 5984 5985
	}

	return 0;
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Jesse Barnes 已提交
5986 5987
}

5988 5989 5990 5991 5992 5993 5994 5995 5996 5997 5998 5999 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009 6010 6011 6012 6013 6014 6015 6016
static bool intel_eld_uptodate(struct drm_connector *connector,
			       int reg_eldv, uint32_t bits_eldv,
			       int reg_elda, uint32_t bits_elda,
			       int reg_edid)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t i;

	i = I915_READ(reg_eldv);
	i &= bits_eldv;

	if (!eld[0])
		return !i;

	if (!i)
		return false;

	i = I915_READ(reg_elda);
	i &= ~bits_elda;
	I915_WRITE(reg_elda, i);

	for (i = 0; i < eld[2]; i++)
		if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
			return false;

	return true;
}

6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031 6032
static void g4x_write_eld(struct drm_connector *connector,
			  struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t len;
	uint32_t i;

	i = I915_READ(G4X_AUD_VID_DID);

	if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

6033 6034 6035 6036 6037 6038
	if (intel_eld_uptodate(connector,
			       G4X_AUD_CNTL_ST, eldv,
			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
			       G4X_HDMIW_HDMIEDID))
		return;

6039 6040 6041 6042 6043 6044 6045 6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056
	i = I915_READ(G4X_AUD_CNTL_ST);
	i &= ~(eldv | G4X_ELD_ADDR);
	len = (i >> 9) & 0x1f;		/* ELD buffer size */
	I915_WRITE(G4X_AUD_CNTL_ST, i);

	if (!eld[0])
		return;

	len = min_t(uint8_t, eld[2], len);
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));

	i = I915_READ(G4X_AUD_CNTL_ST);
	i |= eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, i);
}

6057 6058 6059 6060 6061 6062
static void haswell_write_eld(struct drm_connector *connector,
				     struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	struct drm_device *dev = crtc->dev;
6063
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6064 6065 6066 6067 6068 6069 6070 6071 6072 6073 6074 6075 6076 6077 6078 6079 6080 6081 6082 6083 6084 6085 6086 6087 6088 6089 6090 6091 6092 6093 6094 6095 6096 6097 6098 6099 6100 6101 6102 6103 6104
	uint32_t eldv;
	uint32_t i;
	int len;
	int pipe = to_intel_crtc(crtc)->pipe;
	int tmp;

	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
	int aud_config = HSW_AUD_CFG(pipe);
	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;


	DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");

	/* Audio output enable */
	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
	tmp = I915_READ(aud_cntrl_st2);
	tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
	I915_WRITE(aud_cntrl_st2, tmp);

	/* Wait for 1 vertical blank */
	intel_wait_for_vblank(dev, pipe);

	/* Set ELD valid state */
	tmp = I915_READ(aud_cntrl_st2);
	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
	tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
	I915_WRITE(aud_cntrl_st2, tmp);
	tmp = I915_READ(aud_cntrl_st2);
	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);

	/* Enable HDMI mode */
	tmp = I915_READ(aud_config);
	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
	/* clear N_programing_enable and N_value_index */
	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
	I915_WRITE(aud_config, tmp);

	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));

	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6105
	intel_crtc->eld_vld = true;
6106 6107 6108 6109 6110 6111 6112 6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */
		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
	} else
		I915_WRITE(aud_config, 0);

	if (intel_eld_uptodate(connector,
			       aud_cntrl_st2, eldv,
			       aud_cntl_st, IBX_ELD_ADDRESS,
			       hdmiw_hdmiedid))
		return;

	i = I915_READ(aud_cntrl_st2);
	i &= ~eldv;
	I915_WRITE(aud_cntrl_st2, i);

	if (!eld[0])
		return;

	i = I915_READ(aud_cntl_st);
	i &= ~IBX_ELD_ADDRESS;
	I915_WRITE(aud_cntl_st, i);
	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */
	DRM_DEBUG_DRIVER("port num:%d\n", i);

	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	i = I915_READ(aud_cntrl_st2);
	i |= eldv;
	I915_WRITE(aud_cntrl_st2, i);

}

6144 6145 6146 6147 6148 6149 6150 6151 6152
static void ironlake_write_eld(struct drm_connector *connector,
				     struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t i;
	int len;
	int hdmiw_hdmiedid;
6153
	int aud_config;
6154 6155
	int aud_cntl_st;
	int aud_cntrl_st2;
6156
	int pipe = to_intel_crtc(crtc)->pipe;
6157

6158
	if (HAS_PCH_IBX(connector->dev)) {
6159 6160 6161
		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6162
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6163
	} else {
6164 6165 6166
		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6167
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6168 6169
	}

6170
	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6171 6172

	i = I915_READ(aud_cntl_st);
6173
	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */
6174 6175 6176
	if (!i) {
		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		/* operate blindly on all ports */
6177 6178 6179
		eldv = IBX_ELD_VALIDB;
		eldv |= IBX_ELD_VALIDB << 4;
		eldv |= IBX_ELD_VALIDB << 8;
6180
	} else {
6181
		DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6182
		eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6183 6184
	}

6185 6186 6187
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */
6188 6189 6190
		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
	} else
		I915_WRITE(aud_config, 0);
6191

6192 6193 6194 6195 6196 6197
	if (intel_eld_uptodate(connector,
			       aud_cntrl_st2, eldv,
			       aud_cntl_st, IBX_ELD_ADDRESS,
			       hdmiw_hdmiedid))
		return;

6198 6199 6200 6201 6202 6203 6204 6205
	i = I915_READ(aud_cntrl_st2);
	i &= ~eldv;
	I915_WRITE(aud_cntrl_st2, i);

	if (!eld[0])
		return;

	i = I915_READ(aud_cntl_st);
6206
	i &= ~IBX_ELD_ADDRESS;
6207 6208 6209 6210 6211 6212 6213 6214 6215 6216 6217 6218 6219 6220 6221 6222 6223 6224 6225 6226 6227 6228 6229 6230 6231 6232 6233 6234 6235 6236 6237 6238 6239 6240 6241 6242
	I915_WRITE(aud_cntl_st, i);

	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	i = I915_READ(aud_cntrl_st2);
	i |= eldv;
	I915_WRITE(aud_cntrl_st2, i);
}

void intel_write_eld(struct drm_encoder *encoder,
		     struct drm_display_mode *mode)
{
	struct drm_crtc *crtc = encoder->crtc;
	struct drm_connector *connector;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	connector = drm_select_eld(encoder, mode);
	if (!connector)
		return;

	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
			 connector->base.id,
			 drm_get_connector_name(connector),
			 connector->encoder->base.id,
			 drm_get_encoder_name(connector->encoder));

	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;

	if (dev_priv->display.write_eld)
		dev_priv->display.write_eld(connector, crtc);
}

J
Jesse Barnes 已提交
6243 6244 6245 6246 6247 6248
/** Loads the palette/gamma unit for the CRTC with the prepared values */
void intel_crtc_load_lut(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6249
	int palreg = PALETTE(intel_crtc->pipe);
J
Jesse Barnes 已提交
6250 6251 6252
	int i;

	/* The clocks have to be on to load the palette. */
6253
	if (!crtc->enabled || !intel_crtc->active)
J
Jesse Barnes 已提交
6254 6255
		return;

6256
	/* use legacy palette for Ironlake */
6257
	if (HAS_PCH_SPLIT(dev))
6258
		palreg = LGC_PALETTE(intel_crtc->pipe);
6259

J
Jesse Barnes 已提交
6260 6261 6262 6263 6264 6265 6266 6267
	for (i = 0; i < 256; i++) {
		I915_WRITE(palreg + 4 * i,
			   (intel_crtc->lut_r[i] << 16) |
			   (intel_crtc->lut_g[i] << 8) |
			   intel_crtc->lut_b[i]);
	}
}

6268 6269 6270 6271 6272 6273 6274 6275 6276 6277 6278
static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	bool visible = base != 0;
	u32 cntl;

	if (intel_crtc->cursor_visible == visible)
		return;

6279
	cntl = I915_READ(_CURACNTR);
6280 6281 6282 6283
	if (visible) {
		/* On these chipsets we can only modify the base whilst
		 * the cursor is disabled.
		 */
6284
		I915_WRITE(_CURABASE, base);
6285 6286 6287 6288 6289 6290 6291 6292

		cntl &= ~(CURSOR_FORMAT_MASK);
		/* XXX width must be 64, stride 256 => 0x00 << 28 */
		cntl |= CURSOR_ENABLE |
			CURSOR_GAMMA_ENABLE |
			CURSOR_FORMAT_ARGB;
	} else
		cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6293
	I915_WRITE(_CURACNTR, cntl);
6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306

	intel_crtc->cursor_visible = visible;
}

static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool visible = base != 0;

	if (intel_crtc->cursor_visible != visible) {
6307
		uint32_t cntl = I915_READ(CURCNTR(pipe));
6308 6309 6310 6311 6312 6313 6314 6315
		if (base) {
			cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
			cntl |= pipe << 28; /* Connect to correct pipe */
		} else {
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
			cntl |= CURSOR_MODE_DISABLE;
		}
6316
		I915_WRITE(CURCNTR(pipe), cntl);
6317 6318 6319 6320

		intel_crtc->cursor_visible = visible;
	}
	/* and commit changes on next vblank */
6321
	I915_WRITE(CURBASE(pipe), base);
6322 6323
}

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Jesse Barnes 已提交
6324 6325 6326 6327 6328 6329 6330 6331 6332 6333 6334 6335 6336 6337 6338 6339 6340
static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool visible = base != 0;

	if (intel_crtc->cursor_visible != visible) {
		uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		if (base) {
			cntl &= ~CURSOR_MODE;
			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
		} else {
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
			cntl |= CURSOR_MODE_DISABLE;
		}
6341 6342
		if (IS_HASWELL(dev))
			cntl |= CURSOR_PIPE_CSC_ENABLE;
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Jesse Barnes 已提交
6343 6344 6345 6346 6347 6348 6349 6350
		I915_WRITE(CURCNTR_IVB(pipe), cntl);

		intel_crtc->cursor_visible = visible;
	}
	/* and commit changes on next vblank */
	I915_WRITE(CURBASE_IVB(pipe), base);
}

6351
/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6352 6353
static void intel_crtc_update_cursor(struct drm_crtc *crtc,
				     bool on)
6354 6355 6356 6357 6358 6359 6360
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int x = intel_crtc->cursor_x;
	int y = intel_crtc->cursor_y;
6361
	u32 base, pos;
6362 6363 6364 6365
	bool visible;

	pos = 0;

6366
	if (on && crtc->enabled && crtc->fb) {
6367 6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379 6380 6381 6382 6383 6384 6385 6386 6387 6388 6389 6390 6391 6392 6393 6394
		base = intel_crtc->cursor_addr;
		if (x > (int) crtc->fb->width)
			base = 0;

		if (y > (int) crtc->fb->height)
			base = 0;
	} else
		base = 0;

	if (x < 0) {
		if (x + intel_crtc->cursor_width < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		x = -x;
	}
	pos |= x << CURSOR_X_SHIFT;

	if (y < 0) {
		if (y + intel_crtc->cursor_height < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		y = -y;
	}
	pos |= y << CURSOR_Y_SHIFT;

	visible = base != 0;
6395
	if (!visible && !intel_crtc->cursor_visible)
6396 6397
		return;

6398
	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
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Jesse Barnes 已提交
6399 6400 6401 6402 6403 6404 6405 6406 6407
		I915_WRITE(CURPOS_IVB(pipe), pos);
		ivb_update_cursor(crtc, base);
	} else {
		I915_WRITE(CURPOS(pipe), pos);
		if (IS_845G(dev) || IS_I865G(dev))
			i845_update_cursor(crtc, base);
		else
			i9xx_update_cursor(crtc, base);
	}
6408 6409
}

J
Jesse Barnes 已提交
6410
static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6411
				 struct drm_file *file,
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6412 6413 6414 6415 6416 6417
				 uint32_t handle,
				 uint32_t width, uint32_t height)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6418
	struct drm_i915_gem_object *obj;
6419
	uint32_t addr;
6420
	int ret;
J
Jesse Barnes 已提交
6421 6422 6423

	/* if we want to turn off the cursor ignore width and height */
	if (!handle) {
6424
		DRM_DEBUG_KMS("cursor off\n");
6425
		addr = 0;
6426
		obj = NULL;
6427
		mutex_lock(&dev->struct_mutex);
6428
		goto finish;
J
Jesse Barnes 已提交
6429 6430 6431 6432 6433 6434 6435 6436
	}

	/* Currently we only support 64x64 cursors */
	if (width != 64 || height != 64) {
		DRM_ERROR("we currently only support 64x64 cursors\n");
		return -EINVAL;
	}

6437
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6438
	if (&obj->base == NULL)
J
Jesse Barnes 已提交
6439 6440
		return -ENOENT;

6441
	if (obj->base.size < width * height * 4) {
J
Jesse Barnes 已提交
6442
		DRM_ERROR("buffer is to small\n");
6443 6444
		ret = -ENOMEM;
		goto fail;
J
Jesse Barnes 已提交
6445 6446
	}

6447
	/* we only need to pin inside GTT if cursor is non-phy */
6448
	mutex_lock(&dev->struct_mutex);
6449
	if (!dev_priv->info->cursor_needs_physical) {
6450 6451
		unsigned alignment;

6452 6453 6454 6455 6456 6457
		if (obj->tiling_mode) {
			DRM_ERROR("cursor cannot be tiled\n");
			ret = -EINVAL;
			goto fail_locked;
		}

6458 6459 6460 6461 6462 6463 6464 6465 6466 6467
		/* Note that the w/a also requires 2 PTE of padding following
		 * the bo. We currently fill all unused PTE with the shadow
		 * page and so we should always have valid PTE following the
		 * cursor preventing the VT-d warning.
		 */
		alignment = 0;
		if (need_vtd_wa(dev))
			alignment = 64*1024;

		ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6468 6469
		if (ret) {
			DRM_ERROR("failed to move cursor bo into the GTT\n");
6470
			goto fail_locked;
6471 6472
		}

6473 6474
		ret = i915_gem_object_put_fence(obj);
		if (ret) {
6475
			DRM_ERROR("failed to release fence for cursor");
6476 6477 6478
			goto fail_unpin;
		}

6479
		addr = obj->gtt_offset;
6480
	} else {
6481
		int align = IS_I830(dev) ? 16 * 1024 : 256;
6482
		ret = i915_gem_attach_phys_object(dev, obj,
6483 6484
						  (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
						  align);
6485 6486
		if (ret) {
			DRM_ERROR("failed to attach phys object\n");
6487
			goto fail_locked;
6488
		}
6489
		addr = obj->phys_obj->handle->busaddr;
6490 6491
	}

6492
	if (IS_GEN2(dev))
J
Jesse Barnes 已提交
6493 6494
		I915_WRITE(CURSIZE, (height << 12) | width);

6495 6496
 finish:
	if (intel_crtc->cursor_bo) {
6497
		if (dev_priv->info->cursor_needs_physical) {
6498
			if (intel_crtc->cursor_bo != obj)
6499 6500 6501
				i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		} else
			i915_gem_object_unpin(intel_crtc->cursor_bo);
6502
		drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6503
	}
6504

6505
	mutex_unlock(&dev->struct_mutex);
6506 6507

	intel_crtc->cursor_addr = addr;
6508
	intel_crtc->cursor_bo = obj;
6509 6510 6511
	intel_crtc->cursor_width = width;
	intel_crtc->cursor_height = height;

6512
	intel_crtc_update_cursor(crtc, true);
6513

J
Jesse Barnes 已提交
6514
	return 0;
6515
fail_unpin:
6516
	i915_gem_object_unpin(obj);
6517
fail_locked:
6518
	mutex_unlock(&dev->struct_mutex);
6519
fail:
6520
	drm_gem_object_unreference_unlocked(&obj->base);
6521
	return ret;
J
Jesse Barnes 已提交
6522 6523 6524 6525 6526 6527
}

static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6528 6529
	intel_crtc->cursor_x = x;
	intel_crtc->cursor_y = y;
6530

6531
	intel_crtc_update_cursor(crtc, true);
J
Jesse Barnes 已提交
6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546

	return 0;
}

/** Sets the color ramps on behalf of RandR */
void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				 u16 blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	intel_crtc->lut_r[regno] = red >> 8;
	intel_crtc->lut_g[regno] = green >> 8;
	intel_crtc->lut_b[regno] = blue >> 8;
}

6547 6548 6549 6550 6551 6552 6553 6554 6555 6556
void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
			     u16 *blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	*red = intel_crtc->lut_r[regno] << 8;
	*green = intel_crtc->lut_g[regno] << 8;
	*blue = intel_crtc->lut_b[regno] << 8;
}

J
Jesse Barnes 已提交
6557
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
J
James Simmons 已提交
6558
				 u16 *blue, uint32_t start, uint32_t size)
J
Jesse Barnes 已提交
6559
{
J
James Simmons 已提交
6560
	int end = (start + size > 256) ? 256 : start + size, i;
J
Jesse Barnes 已提交
6561 6562
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

J
James Simmons 已提交
6563
	for (i = start; i < end; i++) {
J
Jesse Barnes 已提交
6564 6565 6566 6567 6568 6569 6570 6571 6572 6573 6574 6575 6576 6577
		intel_crtc->lut_r[i] = red[i] >> 8;
		intel_crtc->lut_g[i] = green[i] >> 8;
		intel_crtc->lut_b[i] = blue[i] >> 8;
	}

	intel_crtc_load_lut(crtc);
}

/* VESA 640x480x72Hz mode to set on the pipe */
static struct drm_display_mode load_detect_mode = {
	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
};

6578 6579
static struct drm_framebuffer *
intel_framebuffer_create(struct drm_device *dev,
6580
			 struct drm_mode_fb_cmd2 *mode_cmd,
6581 6582 6583 6584 6585 6586 6587 6588 6589 6590 6591 6592 6593 6594 6595 6596 6597 6598 6599 6600 6601 6602 6603 6604 6605 6606 6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620 6621
			 struct drm_i915_gem_object *obj)
{
	struct intel_framebuffer *intel_fb;
	int ret;

	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
	if (!intel_fb) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return ERR_PTR(-ENOMEM);
	}

	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
	if (ret) {
		drm_gem_object_unreference_unlocked(&obj->base);
		kfree(intel_fb);
		return ERR_PTR(ret);
	}

	return &intel_fb->base;
}

static u32
intel_framebuffer_pitch_for_width(int width, int bpp)
{
	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
	return ALIGN(pitch, 64);
}

static u32
intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
{
	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
}

static struct drm_framebuffer *
intel_framebuffer_create_for_mode(struct drm_device *dev,
				  struct drm_display_mode *mode,
				  int depth, int bpp)
{
	struct drm_i915_gem_object *obj;
6622
	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6623 6624 6625 6626 6627 6628 6629 6630

	obj = i915_gem_alloc_object(dev,
				    intel_framebuffer_size_for_mode(mode, bpp));
	if (obj == NULL)
		return ERR_PTR(-ENOMEM);

	mode_cmd.width = mode->hdisplay;
	mode_cmd.height = mode->vdisplay;
6631 6632
	mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
								bpp);
6633
	mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6634 6635 6636 6637 6638 6639 6640 6641 6642 6643 6644 6645 6646 6647 6648 6649 6650 6651 6652 6653

	return intel_framebuffer_create(dev, &mode_cmd, obj);
}

static struct drm_framebuffer *
mode_fits_in_fbdev(struct drm_device *dev,
		   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	struct drm_framebuffer *fb;

	if (dev_priv->fbdev == NULL)
		return NULL;

	obj = dev_priv->fbdev->ifb.obj;
	if (obj == NULL)
		return NULL;

	fb = &dev_priv->fbdev->ifb.base;
6654 6655
	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
							       fb->bits_per_pixel))
6656 6657
		return NULL;

6658
	if (obj->base.size < mode->vdisplay * fb->pitches[0])
6659 6660 6661 6662 6663
		return NULL;

	return fb;
}

6664
bool intel_get_load_detect_pipe(struct drm_connector *connector,
6665
				struct drm_display_mode *mode,
6666
				struct intel_load_detect_pipe *old)
J
Jesse Barnes 已提交
6667 6668
{
	struct intel_crtc *intel_crtc;
6669 6670
	struct intel_encoder *intel_encoder =
		intel_attached_encoder(connector);
J
Jesse Barnes 已提交
6671
	struct drm_crtc *possible_crtc;
6672
	struct drm_encoder *encoder = &intel_encoder->base;
J
Jesse Barnes 已提交
6673 6674
	struct drm_crtc *crtc = NULL;
	struct drm_device *dev = encoder->dev;
6675
	struct drm_framebuffer *fb;
J
Jesse Barnes 已提交
6676 6677
	int i = -1;

6678 6679 6680 6681
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector),
		      encoder->base.id, drm_get_encoder_name(encoder));

J
Jesse Barnes 已提交
6682 6683
	/*
	 * Algorithm gets a little messy:
6684
	 *
J
Jesse Barnes 已提交
6685 6686
	 *   - if the connector already has an assigned crtc, use it (but make
	 *     sure it's on first)
6687
	 *
J
Jesse Barnes 已提交
6688 6689 6690 6691 6692 6693 6694
	 *   - try to find the first unused crtc that can drive this connector,
	 *     and use that if we find one
	 */

	/* See if we already have a CRTC for this connector */
	if (encoder->crtc) {
		crtc = encoder->crtc;
6695

6696 6697
		mutex_lock(&crtc->mutex);

6698
		old->dpms_mode = connector->dpms;
6699 6700 6701
		old->load_detect_temp = false;

		/* Make sure the crtc and connector are running */
6702 6703
		if (connector->dpms != DRM_MODE_DPMS_ON)
			connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6704

6705
		return true;
J
Jesse Barnes 已提交
6706 6707 6708 6709 6710 6711 6712 6713 6714 6715 6716 6717 6718 6719 6720 6721 6722
	}

	/* Find an unused one (if possible) */
	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		i++;
		if (!(encoder->possible_crtcs & (1 << i)))
			continue;
		if (!possible_crtc->enabled) {
			crtc = possible_crtc;
			break;
		}
	}

	/*
	 * If we didn't find an unused CRTC, don't use any.
	 */
	if (!crtc) {
6723 6724
		DRM_DEBUG_KMS("no pipe available for load-detect\n");
		return false;
J
Jesse Barnes 已提交
6725 6726
	}

6727
	mutex_lock(&crtc->mutex);
6728 6729
	intel_encoder->new_crtc = to_intel_crtc(crtc);
	to_intel_connector(connector)->new_encoder = intel_encoder;
J
Jesse Barnes 已提交
6730 6731

	intel_crtc = to_intel_crtc(crtc);
6732
	old->dpms_mode = connector->dpms;
6733
	old->load_detect_temp = true;
6734
	old->release_fb = NULL;
J
Jesse Barnes 已提交
6735

6736 6737
	if (!mode)
		mode = &load_detect_mode;
J
Jesse Barnes 已提交
6738

6739 6740 6741 6742 6743 6744 6745
	/* We need a framebuffer large enough to accommodate all accesses
	 * that the plane may generate whilst we perform load detection.
	 * We can not rely on the fbcon either being present (we get called
	 * during its initialisation to detect all boot displays, or it may
	 * not even exist) or that it is large enough to satisfy the
	 * requested mode.
	 */
6746 6747
	fb = mode_fits_in_fbdev(dev, mode);
	if (fb == NULL) {
6748
		DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6749 6750
		fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		old->release_fb = fb;
6751 6752
	} else
		DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6753
	if (IS_ERR(fb)) {
6754
		DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6755
		mutex_unlock(&crtc->mutex);
6756
		return false;
J
Jesse Barnes 已提交
6757 6758
	}

6759
	if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6760
		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6761 6762
		if (old->release_fb)
			old->release_fb->funcs->destroy(old->release_fb);
6763
		mutex_unlock(&crtc->mutex);
6764
		return false;
J
Jesse Barnes 已提交
6765
	}
6766

J
Jesse Barnes 已提交
6767
	/* let the connector get through one full cycle before testing */
6768
	intel_wait_for_vblank(dev, intel_crtc->pipe);
6769
	return true;
J
Jesse Barnes 已提交
6770 6771
}

6772
void intel_release_load_detect_pipe(struct drm_connector *connector,
6773
				    struct intel_load_detect_pipe *old)
J
Jesse Barnes 已提交
6774
{
6775 6776
	struct intel_encoder *intel_encoder =
		intel_attached_encoder(connector);
6777
	struct drm_encoder *encoder = &intel_encoder->base;
6778
	struct drm_crtc *crtc = encoder->crtc;
J
Jesse Barnes 已提交
6779

6780 6781 6782 6783
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector),
		      encoder->base.id, drm_get_encoder_name(encoder));

6784
	if (old->load_detect_temp) {
6785 6786 6787
		to_intel_connector(connector)->new_encoder = NULL;
		intel_encoder->new_crtc = NULL;
		intel_set_mode(crtc, NULL, 0, 0, NULL);
6788

6789 6790 6791 6792
		if (old->release_fb) {
			drm_framebuffer_unregister_private(old->release_fb);
			drm_framebuffer_unreference(old->release_fb);
		}
6793

6794
		mutex_unlock(&crtc->mutex);
6795
		return;
J
Jesse Barnes 已提交
6796 6797
	}

6798
	/* Switch crtc and encoder back off if necessary */
6799 6800
	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		connector->funcs->dpms(connector, old->dpms_mode);
6801 6802

	mutex_unlock(&crtc->mutex);
J
Jesse Barnes 已提交
6803 6804 6805 6806 6807 6808 6809 6810
}

/* Returns the clock of the currently programmed mode of the given pipe. */
static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
6811
	u32 dpll = I915_READ(DPLL(pipe));
J
Jesse Barnes 已提交
6812 6813 6814 6815
	u32 fp;
	intel_clock_t clock;

	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6816
		fp = I915_READ(FP0(pipe));
J
Jesse Barnes 已提交
6817
	else
6818
		fp = I915_READ(FP1(pipe));
J
Jesse Barnes 已提交
6819 6820

	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6821 6822 6823
	if (IS_PINEVIEW(dev)) {
		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6824 6825 6826 6827 6828
	} else {
		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
	}

6829
	if (!IS_GEN2(dev)) {
6830 6831 6832
		if (IS_PINEVIEW(dev))
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6833 6834
		else
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
J
Jesse Barnes 已提交
6835 6836 6837 6838 6839 6840 6841 6842 6843 6844 6845 6846
			       DPLL_FPA01_P1_POST_DIV_SHIFT);

		switch (dpll & DPLL_MODE_MASK) {
		case DPLLB_MODE_DAC_SERIAL:
			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
				5 : 10;
			break;
		case DPLLB_MODE_LVDS:
			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
				7 : 14;
			break;
		default:
6847
			DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
J
Jesse Barnes 已提交
6848 6849 6850 6851 6852
				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
			return 0;
		}

		/* XXX: Handle the 100Mhz refclk */
6853
		intel_clock(dev, 96000, &clock);
J
Jesse Barnes 已提交
6854 6855 6856 6857 6858 6859 6860 6861 6862 6863 6864
	} else {
		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);

		if (is_lvds) {
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
				       DPLL_FPA01_P1_POST_DIV_SHIFT);
			clock.p2 = 14;

			if ((dpll & PLL_REF_INPUT_MASK) ==
			    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
				/* XXX: might not be 66MHz */
6865
				intel_clock(dev, 66000, &clock);
J
Jesse Barnes 已提交
6866
			} else
6867
				intel_clock(dev, 48000, &clock);
J
Jesse Barnes 已提交
6868 6869 6870 6871 6872 6873 6874 6875 6876 6877 6878 6879
		} else {
			if (dpll & PLL_P1_DIVIDE_BY_TWO)
				clock.p1 = 2;
			else {
				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
			}
			if (dpll & PLL_P2_DIVIDE_BY_4)
				clock.p2 = 4;
			else
				clock.p2 = 2;

6880
			intel_clock(dev, 48000, &clock);
J
Jesse Barnes 已提交
6881 6882 6883 6884 6885 6886 6887 6888 6889 6890 6891 6892 6893 6894 6895
		}
	}

	/* XXX: It would be nice to validate the clocks, but we can't reuse
	 * i830PllIsValid() because it relies on the xf86_config connector
	 * configuration being accurate, which it isn't necessarily.
	 */

	return clock.dot;
}

/** Returns the currently programmed mode of the given pipe. */
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
					     struct drm_crtc *crtc)
{
6896
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
6897
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6898
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
J
Jesse Barnes 已提交
6899
	struct drm_display_mode *mode;
6900 6901 6902 6903
	int htot = I915_READ(HTOTAL(cpu_transcoder));
	int hsync = I915_READ(HSYNC(cpu_transcoder));
	int vtot = I915_READ(VTOTAL(cpu_transcoder));
	int vsync = I915_READ(VSYNC(cpu_transcoder));
J
Jesse Barnes 已提交
6904 6905 6906 6907 6908 6909 6910 6911 6912 6913 6914 6915 6916 6917 6918 6919 6920 6921 6922 6923

	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
	if (!mode)
		return NULL;

	mode->clock = intel_crtc_clock_get(dev, crtc);
	mode->hdisplay = (htot & 0xffff) + 1;
	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
	mode->hsync_start = (hsync & 0xffff) + 1;
	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
	mode->vdisplay = (vtot & 0xffff) + 1;
	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
	mode->vsync_start = (vsync & 0xffff) + 1;
	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;

	drm_mode_set_name(mode);

	return mode;
}

6924
static void intel_increase_pllclock(struct drm_crtc *crtc)
6925 6926 6927 6928 6929
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
6930 6931
	int dpll_reg = DPLL(pipe);
	int dpll;
6932

6933
	if (HAS_PCH_SPLIT(dev))
6934 6935 6936 6937 6938
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

6939
	dpll = I915_READ(dpll_reg);
6940
	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6941
		DRM_DEBUG_DRIVER("upclocking LVDS\n");
6942

6943
		assert_panel_unlocked(dev_priv, pipe);
6944 6945 6946

		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
6947
		intel_wait_for_vblank(dev, pipe);
6948

6949 6950
		dpll = I915_READ(dpll_reg);
		if (dpll & DISPLAY_RATE_SELECT_FPA1)
6951
			DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6952 6953 6954 6955 6956 6957 6958 6959 6960
	}
}

static void intel_decrease_pllclock(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6961
	if (HAS_PCH_SPLIT(dev))
6962 6963 6964 6965 6966 6967 6968 6969 6970 6971
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

	/*
	 * Since this is called by a timer, we should never get here in
	 * the manual case.
	 */
	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6972 6973 6974
		int pipe = intel_crtc->pipe;
		int dpll_reg = DPLL(pipe);
		int dpll;
6975

6976
		DRM_DEBUG_DRIVER("downclocking LVDS\n");
6977

6978
		assert_panel_unlocked(dev_priv, pipe);
6979

6980
		dpll = I915_READ(dpll_reg);
6981 6982
		dpll |= DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
6983
		intel_wait_for_vblank(dev, pipe);
6984 6985
		dpll = I915_READ(dpll_reg);
		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6986
			DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6987 6988 6989 6990
	}

}

6991 6992 6993 6994 6995 6996
void intel_mark_busy(struct drm_device *dev)
{
	i915_update_gfx_val(dev->dev_private);
}

void intel_mark_idle(struct drm_device *dev)
6997 6998 6999 7000 7001 7002 7003 7004 7005 7006
{
	struct drm_crtc *crtc;

	if (!i915_powersave)
		return;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (!crtc->fb)
			continue;

7007
		intel_decrease_pllclock(crtc);
7008 7009 7010
	}
}

7011
void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7012
{
7013 7014
	struct drm_device *dev = obj->base.dev;
	struct drm_crtc *crtc;
7015

7016
	if (!i915_powersave)
7017 7018
		return;

7019 7020 7021 7022
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (!crtc->fb)
			continue;

7023
		if (to_intel_framebuffer(crtc->fb)->obj == obj)
7024
			intel_increase_pllclock(crtc);
7025 7026 7027
	}
}

J
Jesse Barnes 已提交
7028 7029 7030
static void intel_crtc_destroy(struct drm_crtc *crtc)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7031 7032 7033 7034 7035 7036 7037 7038 7039 7040 7041 7042 7043
	struct drm_device *dev = crtc->dev;
	struct intel_unpin_work *work;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (work) {
		cancel_work_sync(&work->work);
		kfree(work);
	}
J
Jesse Barnes 已提交
7044 7045

	drm_crtc_cleanup(crtc);
7046

J
Jesse Barnes 已提交
7047 7048 7049
	kfree(intel_crtc);
}

7050 7051 7052 7053
static void intel_unpin_work_fn(struct work_struct *__work)
{
	struct intel_unpin_work *work =
		container_of(__work, struct intel_unpin_work, work);
7054
	struct drm_device *dev = work->crtc->dev;
7055

7056
	mutex_lock(&dev->struct_mutex);
7057
	intel_unpin_fb_obj(work->old_fb_obj);
7058 7059
	drm_gem_object_unreference(&work->pending_flip_obj->base);
	drm_gem_object_unreference(&work->old_fb_obj->base);
7060

7061 7062 7063 7064 7065 7066
	intel_update_fbc(dev);
	mutex_unlock(&dev->struct_mutex);

	BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
	atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);

7067 7068 7069
	kfree(work);
}

7070
static void do_intel_finish_page_flip(struct drm_device *dev,
7071
				      struct drm_crtc *crtc)
7072 7073 7074 7075 7076 7077 7078 7079 7080 7081 7082 7083
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
	unsigned long flags;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
7084 7085 7086 7087 7088

	/* Ensure we don't miss a work->pending update ... */
	smp_rmb();

	if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7089 7090 7091 7092
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

7093 7094 7095
	/* and that the unpin work is consistent wrt ->pending. */
	smp_rmb();

7096 7097
	intel_crtc->unpin_work = NULL;

7098 7099
	if (work->event)
		drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7100

7101 7102
	drm_vblank_put(dev, intel_crtc->pipe);

7103 7104
	spin_unlock_irqrestore(&dev->event_lock, flags);

7105
	wake_up_all(&dev_priv->pending_flip_queue);
7106 7107

	queue_work(dev_priv->wq, &work->work);
7108 7109

	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7110 7111
}

7112 7113 7114 7115 7116
void intel_finish_page_flip(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];

7117
	do_intel_finish_page_flip(dev, crtc);
7118 7119 7120 7121 7122 7123 7124
}

void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];

7125
	do_intel_finish_page_flip(dev, crtc);
7126 7127
}

7128 7129 7130 7131 7132 7133 7134
void intel_prepare_page_flip(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
	unsigned long flags;

7135 7136 7137 7138
	/* NB: An MMIO update of the plane base pointer will also
	 * generate a page-flip completion irq, i.e. every modeset
	 * is also accompanied by a spurious intel_prepare_page_flip().
	 */
7139
	spin_lock_irqsave(&dev->event_lock, flags);
7140 7141
	if (intel_crtc->unpin_work)
		atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7142 7143 7144
	spin_unlock_irqrestore(&dev->event_lock, flags);
}

7145 7146 7147 7148 7149 7150 7151 7152 7153
inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
{
	/* Ensure that the work item is consistent when activating it ... */
	smp_wmb();
	atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
	/* and that it is marked active as soon as the irq could fire. */
	smp_wmb();
}

7154 7155 7156 7157 7158 7159 7160 7161
static int intel_gen2_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	u32 flip_mask;
7162
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7163 7164
	int ret;

7165
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7166
	if (ret)
7167
		goto err;
7168

7169
	ret = intel_ring_begin(ring, 6);
7170
	if (ret)
7171
		goto err_unpin;
7172 7173 7174 7175 7176 7177 7178 7179

	/* Can't queue multiple flips, so wait for the previous
	 * one to finish before executing the next.
	 */
	if (intel_crtc->plane)
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
	else
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7180 7181 7182 7183 7184
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
7185
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7186
	intel_ring_emit(ring, 0); /* aux display base address, unused */
7187 7188

	intel_mark_page_flip_active(intel_crtc);
7189
	intel_ring_advance(ring);
7190 7191 7192 7193 7194
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7195 7196 7197 7198 7199 7200 7201 7202 7203 7204 7205
	return ret;
}

static int intel_gen3_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	u32 flip_mask;
7206
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7207 7208
	int ret;

7209
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7210
	if (ret)
7211
		goto err;
7212

7213
	ret = intel_ring_begin(ring, 6);
7214
	if (ret)
7215
		goto err_unpin;
7216 7217 7218 7219 7220

	if (intel_crtc->plane)
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
	else
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7221 7222 7223 7224 7225
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
7226
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7227 7228
	intel_ring_emit(ring, MI_NOOP);

7229
	intel_mark_page_flip_active(intel_crtc);
7230
	intel_ring_advance(ring);
7231 7232 7233 7234 7235
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7236 7237 7238 7239 7240 7241 7242 7243 7244 7245 7246
	return ret;
}

static int intel_gen4_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	uint32_t pf, pipesrc;
7247
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7248 7249
	int ret;

7250
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7251
	if (ret)
7252
		goto err;
7253

7254
	ret = intel_ring_begin(ring, 4);
7255
	if (ret)
7256
		goto err_unpin;
7257 7258 7259 7260 7261

	/* i965+ uses the linear or tiled offsets from the
	 * Display Registers (which do not change across a page-flip)
	 * so we need only reprogram the base address.
	 */
7262 7263 7264
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
7265 7266 7267
	intel_ring_emit(ring,
			(obj->gtt_offset + intel_crtc->dspaddr_offset) |
			obj->tiling_mode);
7268 7269 7270 7271 7272 7273 7274

	/* XXX Enabling the panel-fitter across page-flip is so far
	 * untested on non-native modes, so ignore it for now.
	 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
	 */
	pf = 0;
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7275
	intel_ring_emit(ring, pf | pipesrc);
7276 7277

	intel_mark_page_flip_active(intel_crtc);
7278
	intel_ring_advance(ring);
7279 7280 7281 7282 7283
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7284 7285 7286 7287 7288 7289 7290 7291 7292 7293
	return ret;
}

static int intel_gen6_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7294
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7295 7296 7297
	uint32_t pf, pipesrc;
	int ret;

7298
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7299
	if (ret)
7300
		goto err;
7301

7302
	ret = intel_ring_begin(ring, 4);
7303
	if (ret)
7304
		goto err_unpin;
7305

7306 7307 7308
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7309
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7310

7311 7312 7313 7314 7315 7316 7317
	/* Contrary to the suggestions in the documentation,
	 * "Enable Panel Fitter" does not seem to be required when page
	 * flipping with a non-native mode, and worse causes a normal
	 * modeset to fail.
	 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
	 */
	pf = 0;
7318
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7319
	intel_ring_emit(ring, pf | pipesrc);
7320 7321

	intel_mark_page_flip_active(intel_crtc);
7322
	intel_ring_advance(ring);
7323 7324 7325 7326 7327
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7328 7329 7330
	return ret;
}

7331 7332 7333 7334 7335 7336 7337 7338 7339 7340 7341 7342 7343 7344
/*
 * On gen7 we currently use the blit ring because (in early silicon at least)
 * the render ring doesn't give us interrpts for page flip completion, which
 * means clients will hang after the first flip is queued.  Fortunately the
 * blit ring generates interrupts properly, so use it instead.
 */
static int intel_gen7_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7345
	uint32_t plane_bit = 0;
7346 7347 7348 7349
	int ret;

	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
	if (ret)
7350
		goto err;
7351

7352 7353 7354 7355 7356 7357 7358 7359 7360 7361 7362 7363 7364
	switch(intel_crtc->plane) {
	case PLANE_A:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		break;
	case PLANE_B:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		break;
	case PLANE_C:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		break;
	default:
		WARN_ONCE(1, "unknown plane in flip command\n");
		ret = -ENODEV;
7365
		goto err_unpin;
7366 7367
	}

7368 7369
	ret = intel_ring_begin(ring, 4);
	if (ret)
7370
		goto err_unpin;
7371

7372
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7373
	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7374
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7375
	intel_ring_emit(ring, (MI_NOOP));
7376 7377

	intel_mark_page_flip_active(intel_crtc);
7378
	intel_ring_advance(ring);
7379 7380 7381 7382 7383
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
7384 7385 7386
	return ret;
}

7387 7388 7389 7390 7391 7392 7393 7394
static int intel_default_queue_flip(struct drm_device *dev,
				    struct drm_crtc *crtc,
				    struct drm_framebuffer *fb,
				    struct drm_i915_gem_object *obj)
{
	return -ENODEV;
}

7395 7396 7397 7398 7399 7400
static int intel_crtc_page_flip(struct drm_crtc *crtc,
				struct drm_framebuffer *fb,
				struct drm_pending_vblank_event *event)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
7401 7402
	struct drm_framebuffer *old_fb = crtc->fb;
	struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7403 7404
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
7405
	unsigned long flags;
7406
	int ret;
7407

7408 7409 7410 7411 7412 7413 7414 7415 7416 7417 7418 7419 7420
	/* Can't change pixel format via MI display flips. */
	if (fb->pixel_format != crtc->fb->pixel_format)
		return -EINVAL;

	/*
	 * TILEOFF/LINOFF registers can't be changed via MI display flips.
	 * Note that pitch changes could also affect these register.
	 */
	if (INTEL_INFO(dev)->gen > 3 &&
	    (fb->offsets[0] != crtc->fb->offsets[0] ||
	     fb->pitches[0] != crtc->fb->pitches[0]))
		return -EINVAL;

7421 7422 7423 7424 7425
	work = kzalloc(sizeof *work, GFP_KERNEL);
	if (work == NULL)
		return -ENOMEM;

	work->event = event;
7426
	work->crtc = crtc;
7427
	work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7428 7429
	INIT_WORK(&work->work, intel_unpin_work_fn);

7430 7431 7432 7433
	ret = drm_vblank_get(dev, intel_crtc->pipe);
	if (ret)
		goto free_work;

7434 7435 7436 7437 7438
	/* We borrow the event spin lock for protecting unpin_work */
	spin_lock_irqsave(&dev->event_lock, flags);
	if (intel_crtc->unpin_work) {
		spin_unlock_irqrestore(&dev->event_lock, flags);
		kfree(work);
7439
		drm_vblank_put(dev, intel_crtc->pipe);
7440 7441

		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7442 7443 7444 7445 7446
		return -EBUSY;
	}
	intel_crtc->unpin_work = work;
	spin_unlock_irqrestore(&dev->event_lock, flags);

7447 7448 7449
	if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
		flush_workqueue(dev_priv->wq);

7450 7451 7452
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		goto cleanup;
7453

7454
	/* Reference the objects for the scheduled work. */
7455 7456
	drm_gem_object_reference(&work->old_fb_obj->base);
	drm_gem_object_reference(&obj->base);
7457 7458

	crtc->fb = fb;
7459

7460 7461
	work->pending_flip_obj = obj;

7462 7463
	work->enable_stall_check = true;

7464
	atomic_inc(&intel_crtc->unpin_work_count);
7465
	intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7466

7467 7468 7469
	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
	if (ret)
		goto cleanup_pending;
7470

7471
	intel_disable_fbc(dev);
7472
	intel_mark_fb_busy(obj);
7473 7474
	mutex_unlock(&dev->struct_mutex);

7475 7476
	trace_i915_flip_request(intel_crtc->plane, obj);

7477
	return 0;
7478

7479
cleanup_pending:
7480
	atomic_dec(&intel_crtc->unpin_work_count);
7481
	crtc->fb = old_fb;
7482 7483
	drm_gem_object_unreference(&work->old_fb_obj->base);
	drm_gem_object_unreference(&obj->base);
7484 7485
	mutex_unlock(&dev->struct_mutex);

7486
cleanup:
7487 7488 7489 7490
	spin_lock_irqsave(&dev->event_lock, flags);
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

7491 7492
	drm_vblank_put(dev, intel_crtc->pipe);
free_work:
7493 7494 7495
	kfree(work);

	return ret;
7496 7497
}

7498 7499 7500 7501 7502
static struct drm_crtc_helper_funcs intel_helper_funcs = {
	.mode_set_base_atomic = intel_pipe_set_base_atomic,
	.load_lut = intel_crtc_load_lut,
};

7503
bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7504
{
7505 7506
	struct intel_encoder *other_encoder;
	struct drm_crtc *crtc = &encoder->new_crtc->base;
7507

7508 7509 7510 7511 7512 7513 7514 7515 7516 7517 7518 7519
	if (WARN_ON(!crtc))
		return false;

	list_for_each_entry(other_encoder,
			    &crtc->dev->mode_config.encoder_list,
			    base.head) {

		if (&other_encoder->new_crtc->base != crtc ||
		    encoder == other_encoder)
			continue;
		else
			return true;
7520 7521
	}

7522 7523
	return false;
}
7524

7525 7526 7527 7528 7529 7530
static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
				  struct drm_crtc *crtc)
{
	struct drm_device *dev;
	struct drm_crtc *tmp;
	int crtc_mask = 1;
7531

7532
	WARN(!crtc, "checking null crtc?\n");
7533

7534
	dev = crtc->dev;
7535

7536 7537 7538 7539 7540
	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
		if (tmp == crtc)
			break;
		crtc_mask <<= 1;
	}
7541

7542 7543 7544
	if (encoder->possible_crtcs & crtc_mask)
		return true;
	return false;
7545
}
J
Jesse Barnes 已提交
7546

7547 7548 7549 7550 7551 7552 7553
/**
 * intel_modeset_update_staged_output_state
 *
 * Updates the staged output configuration state, e.g. after we've read out the
 * current hw state.
 */
static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7554
{
7555 7556
	struct intel_encoder *encoder;
	struct intel_connector *connector;
7557

7558 7559 7560 7561 7562
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		connector->new_encoder =
			to_intel_encoder(connector->base.encoder);
	}
7563

7564 7565 7566 7567 7568
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		encoder->new_crtc =
			to_intel_crtc(encoder->base.crtc);
	}
7569 7570
}

7571 7572 7573 7574 7575 7576 7577 7578 7579
/**
 * intel_modeset_commit_output_state
 *
 * This function copies the stage display pipe configuration to the real one.
 */
static void intel_modeset_commit_output_state(struct drm_device *dev)
{
	struct intel_encoder *encoder;
	struct intel_connector *connector;
7580

7581 7582 7583 7584
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		connector->base.encoder = &connector->new_encoder->base;
	}
7585

7586 7587 7588 7589 7590 7591
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		encoder->base.crtc = &encoder->new_crtc->base;
	}
}

7592 7593 7594 7595 7596 7597 7598 7599 7600
static int
pipe_config_set_bpp(struct drm_crtc *crtc,
		    struct drm_framebuffer *fb,
		    struct intel_crtc_config *pipe_config)
{
	struct drm_device *dev = crtc->dev;
	struct drm_connector *connector;
	int bpp;

7601 7602
	switch (fb->pixel_format) {
	case DRM_FORMAT_C8:
7603 7604
		bpp = 8*3; /* since we go through a colormap */
		break;
7605 7606 7607 7608 7609 7610
	case DRM_FORMAT_XRGB1555:
	case DRM_FORMAT_ARGB1555:
		/* checked in intel_framebuffer_init already */
		if (WARN_ON(INTEL_INFO(dev)->gen > 3))
			return -EINVAL;
	case DRM_FORMAT_RGB565:
7611 7612
		bpp = 6*3; /* min is 18bpp */
		break;
7613 7614 7615 7616 7617 7618 7619
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
		/* checked in intel_framebuffer_init already */
		if (WARN_ON(INTEL_INFO(dev)->gen < 4))
			return -EINVAL;
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
7620 7621
		bpp = 8*3;
		break;
7622 7623 7624 7625 7626 7627
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
		/* checked in intel_framebuffer_init already */
		if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7628
			return -EINVAL;
7629 7630
		bpp = 10*3;
		break;
7631
	/* TODO: gen4+ supports 16 bpc floating point, too. */
7632 7633 7634 7635 7636 7637 7638 7639 7640 7641 7642 7643 7644 7645 7646 7647 7648 7649 7650 7651
	default:
		DRM_DEBUG_KMS("unsupported depth\n");
		return -EINVAL;
	}

	pipe_config->pipe_bpp = bpp;

	/* Clamp display bpp to EDID value */
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    head) {
		if (connector->encoder && connector->encoder->crtc != crtc)
			continue;

		/* Don't use an invalid EDID bpc value */
		if (connector->display_info.bpc &&
		    connector->display_info.bpc * 3 < bpp) {
			DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
				      bpp, connector->display_info.bpc*3);
			pipe_config->pipe_bpp = connector->display_info.bpc*3;
		}
7652 7653 7654 7655 7656 7657 7658

		/* Clamp bpp to 8 on screens without EDID 1.4 */
		if (connector->display_info.bpc == 0 && bpp > 24) {
			DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
				      bpp);
			pipe_config->pipe_bpp = 24;
		}
7659 7660 7661 7662 7663
	}

	return bpp;
}

7664 7665 7666 7667 7668 7669 7670 7671 7672 7673 7674 7675 7676 7677 7678 7679 7680 7681 7682 7683 7684 7685 7686 7687 7688 7689 7690 7691 7692
static void intel_dump_pipe_config(struct intel_crtc *crtc,
				   struct intel_crtc_config *pipe_config,
				   const char *context)
{
	DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
		      context, pipe_name(crtc->pipe));

	DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
	DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
		      pipe_config->pipe_bpp, pipe_config->dither);
	DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
		      pipe_config->has_pch_encoder,
		      pipe_config->fdi_lanes,
		      pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
		      pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
		      pipe_config->fdi_m_n.tu);
	DRM_DEBUG_KMS("requested mode:\n");
	drm_mode_debug_printmodeline(&pipe_config->requested_mode);
	DRM_DEBUG_KMS("adjusted mode:\n");
	drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
	DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
		      pipe_config->gmch_pfit.control,
		      pipe_config->gmch_pfit.pgm_ratios,
		      pipe_config->gmch_pfit.lvds_border_bits);
	DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
		      pipe_config->pch_pfit.pos,
		      pipe_config->pch_pfit.size);
}

7693 7694
static struct intel_crtc_config *
intel_modeset_pipe_config(struct drm_crtc *crtc,
7695
			  struct drm_framebuffer *fb,
7696
			  struct drm_display_mode *mode)
7697
{
7698 7699 7700
	struct drm_device *dev = crtc->dev;
	struct drm_encoder_helper_funcs *encoder_funcs;
	struct intel_encoder *encoder;
7701
	struct intel_crtc_config *pipe_config;
7702 7703
	int plane_bpp, ret = -EINVAL;
	bool retry = true;
7704

7705 7706
	pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
	if (!pipe_config)
7707 7708
		return ERR_PTR(-ENOMEM);

7709 7710
	drm_mode_copy(&pipe_config->adjusted_mode, mode);
	drm_mode_copy(&pipe_config->requested_mode, mode);
7711
	pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7712

7713 7714 7715 7716
	plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
	if (plane_bpp < 0)
		goto fail;

7717
encoder_retry:
7718 7719 7720
	/* Pass our mode to the connectors and the CRTC to give them a chance to
	 * adjust it according to limitations or connector properties, and also
	 * a chance to reject the mode entirely.
7721
	 */
7722 7723
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
7724

7725 7726
		if (&encoder->new_crtc->base != crtc)
			continue;
7727 7728 7729 7730 7731 7732 7733 7734 7735 7736

		if (encoder->compute_config) {
			if (!(encoder->compute_config(encoder, pipe_config))) {
				DRM_DEBUG_KMS("Encoder config failure\n");
				goto fail;
			}

			continue;
		}

7737
		encoder_funcs = encoder->base.helper_private;
7738 7739 7740
		if (!(encoder_funcs->mode_fixup(&encoder->base,
						&pipe_config->requested_mode,
						&pipe_config->adjusted_mode))) {
7741 7742 7743
			DRM_DEBUG_KMS("Encoder fixup failed\n");
			goto fail;
		}
7744
	}
7745

7746 7747
	ret = intel_crtc_compute_config(crtc, pipe_config);
	if (ret < 0) {
7748 7749
		DRM_DEBUG_KMS("CRTC fixup failed\n");
		goto fail;
7750
	}
7751 7752 7753 7754 7755 7756 7757 7758 7759 7760 7761 7762

	if (ret == RETRY) {
		if (WARN(!retry, "loop in pipe configuration computation\n")) {
			ret = -EINVAL;
			goto fail;
		}

		DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
		retry = false;
		goto encoder_retry;
	}

7763 7764 7765 7766
	pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
	DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
		      plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);

7767
	return pipe_config;
7768
fail:
7769
	kfree(pipe_config);
7770
	return ERR_PTR(ret);
7771
}
7772

7773 7774 7775 7776 7777
/* Computes which crtcs are affected and sets the relevant bits in the mask. For
 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
static void
intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
			     unsigned *prepare_pipes, unsigned *disable_pipes)
J
Jesse Barnes 已提交
7778 7779
{
	struct intel_crtc *intel_crtc;
7780 7781 7782 7783
	struct drm_device *dev = crtc->dev;
	struct intel_encoder *encoder;
	struct intel_connector *connector;
	struct drm_crtc *tmp_crtc;
J
Jesse Barnes 已提交
7784

7785
	*disable_pipes = *modeset_pipes = *prepare_pipes = 0;
J
Jesse Barnes 已提交
7786

7787 7788 7789 7790 7791 7792 7793 7794
	/* Check which crtcs have changed outputs connected to them, these need
	 * to be part of the prepare_pipes mask. We don't (yet) support global
	 * modeset across multiple crtcs, so modeset_pipes will only have one
	 * bit set at most. */
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (connector->base.encoder == &connector->new_encoder->base)
			continue;
J
Jesse Barnes 已提交
7795

7796 7797 7798 7799 7800 7801 7802 7803 7804
		if (connector->base.encoder) {
			tmp_crtc = connector->base.encoder->crtc;

			*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
		}

		if (connector->new_encoder)
			*prepare_pipes |=
				1 << connector->new_encoder->new_crtc->pipe;
J
Jesse Barnes 已提交
7805 7806
	}

7807 7808 7809 7810 7811 7812 7813 7814 7815 7816 7817 7818 7819
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		if (encoder->base.crtc == &encoder->new_crtc->base)
			continue;

		if (encoder->base.crtc) {
			tmp_crtc = encoder->base.crtc;

			*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
		}

		if (encoder->new_crtc)
			*prepare_pipes |= 1 << encoder->new_crtc->pipe;
7820 7821
	}

7822 7823 7824 7825
	/* Check for any pipes that will be fully disabled ... */
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
			    base.head) {
		bool used = false;
J
Jesse Barnes 已提交
7826

7827 7828 7829
		/* Don't try to disable disabled crtcs. */
		if (!intel_crtc->base.enabled)
			continue;
7830

7831 7832 7833 7834 7835 7836 7837 7838
		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
				    base.head) {
			if (encoder->new_crtc == intel_crtc)
				used = true;
		}

		if (!used)
			*disable_pipes |= 1 << intel_crtc->pipe;
7839 7840
	}

7841 7842 7843 7844 7845 7846

	/* set_mode is also used to update properties on life display pipes. */
	intel_crtc = to_intel_crtc(crtc);
	if (crtc->enabled)
		*prepare_pipes |= 1 << intel_crtc->pipe;

7847 7848 7849 7850 7851
	/*
	 * For simplicity do a full modeset on any pipe where the output routing
	 * changed. We could be more clever, but that would require us to be
	 * more careful with calling the relevant encoder->mode_set functions.
	 */
7852 7853 7854 7855 7856 7857
	if (*prepare_pipes)
		*modeset_pipes = *prepare_pipes;

	/* ... and mask these out. */
	*modeset_pipes &= ~(*disable_pipes);
	*prepare_pipes &= ~(*disable_pipes);
7858 7859 7860 7861 7862 7863 7864 7865

	/*
	 * HACK: We don't (yet) fully support global modesets. intel_set_config
	 * obies this rule, but the modeset restore mode of
	 * intel_modeset_setup_hw_state does not.
	 */
	*modeset_pipes &= 1 << intel_crtc->pipe;
	*prepare_pipes &= 1 << intel_crtc->pipe;
7866 7867 7868

	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		      *modeset_pipes, *prepare_pipes, *disable_pipes);
7869
}
J
Jesse Barnes 已提交
7870

7871
static bool intel_crtc_in_use(struct drm_crtc *crtc)
7872
{
7873
	struct drm_encoder *encoder;
7874 7875
	struct drm_device *dev = crtc->dev;

7876 7877 7878 7879 7880 7881 7882 7883 7884 7885 7886 7887 7888 7889 7890 7891 7892 7893 7894 7895 7896 7897 7898 7899 7900 7901 7902 7903 7904 7905 7906 7907 7908 7909 7910 7911 7912 7913 7914 7915
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		if (encoder->crtc == crtc)
			return true;

	return false;
}

static void
intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
{
	struct intel_encoder *intel_encoder;
	struct intel_crtc *intel_crtc;
	struct drm_connector *connector;

	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
			    base.head) {
		if (!intel_encoder->base.crtc)
			continue;

		intel_crtc = to_intel_crtc(intel_encoder->base.crtc);

		if (prepare_pipes & (1 << intel_crtc->pipe))
			intel_encoder->connectors_active = false;
	}

	intel_modeset_commit_output_state(dev);

	/* Update computed state. */
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
			    base.head) {
		intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
	}

	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		if (!connector->encoder || !connector->encoder->crtc)
			continue;

		intel_crtc = to_intel_crtc(connector->encoder->crtc);

		if (prepare_pipes & (1 << intel_crtc->pipe)) {
7916 7917 7918
			struct drm_property *dpms_property =
				dev->mode_config.dpms_property;

7919
			connector->dpms = DRM_MODE_DPMS_ON;
7920
			drm_object_property_set_value(&connector->base,
7921 7922
							 dpms_property,
							 DRM_MODE_DPMS_ON);
7923 7924 7925 7926 7927 7928 7929 7930

			intel_encoder = to_intel_encoder(connector->encoder);
			intel_encoder->connectors_active = true;
		}
	}

}

7931 7932 7933 7934
#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
	list_for_each_entry((intel_crtc), \
			    &(dev)->mode_config.crtc_list, \
			    base.head) \
7935
		if (mask & (1 <<(intel_crtc)->pipe))
7936

7937
static bool
7938 7939
intel_pipe_config_compare(struct drm_device *dev,
			  struct intel_crtc_config *current_config,
7940 7941
			  struct intel_crtc_config *pipe_config)
{
7942 7943 7944 7945 7946 7947 7948
#define PIPE_CONF_CHECK_I(name)	\
	if (current_config->name != pipe_config->name) { \
		DRM_ERROR("mismatch in " #name " " \
			  "(expected %i, found %i)\n", \
			  current_config->name, \
			  pipe_config->name); \
		return false; \
7949 7950
	}

7951 7952 7953 7954 7955 7956 7957 7958 7959
#define PIPE_CONF_CHECK_FLAGS(name, mask)	\
	if ((current_config->name ^ pipe_config->name) & (mask)) { \
		DRM_ERROR("mismatch in " #name " " \
			  "(expected %i, found %i)\n", \
			  current_config->name & (mask), \
			  pipe_config->name & (mask)); \
		return false; \
	}

7960 7961
	PIPE_CONF_CHECK_I(cpu_transcoder);

7962 7963
	PIPE_CONF_CHECK_I(has_pch_encoder);
	PIPE_CONF_CHECK_I(fdi_lanes);
7964 7965 7966 7967 7968
	PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
	PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
	PIPE_CONF_CHECK_I(fdi_m_n.link_m);
	PIPE_CONF_CHECK_I(fdi_m_n.link_n);
	PIPE_CONF_CHECK_I(fdi_m_n.tu);
7969

7970 7971 7972 7973 7974 7975 7976 7977 7978 7979 7980 7981 7982 7983 7984 7985 7986
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);

	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
			      DRM_MODE_FLAG_INTERLACE);

7987 7988 7989 7990 7991 7992 7993 7994 7995
	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
			      DRM_MODE_FLAG_PHSYNC);
	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
			      DRM_MODE_FLAG_NHSYNC);
	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
			      DRM_MODE_FLAG_PVSYNC);
	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
			      DRM_MODE_FLAG_NVSYNC);

7996 7997 7998
	PIPE_CONF_CHECK_I(requested_mode.hdisplay);
	PIPE_CONF_CHECK_I(requested_mode.vdisplay);

7999 8000 8001 8002 8003 8004 8005 8006
	PIPE_CONF_CHECK_I(gmch_pfit.control);
	/* pfit ratios are autocomputed by the hw on gen4+ */
	if (INTEL_INFO(dev)->gen < 4)
		PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
	PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
	PIPE_CONF_CHECK_I(pch_pfit.pos);
	PIPE_CONF_CHECK_I(pch_pfit.size);

8007
#undef PIPE_CONF_CHECK_I
8008
#undef PIPE_CONF_CHECK_FLAGS
8009

8010 8011 8012
	return true;
}

8013
void
8014 8015
intel_modeset_check_state(struct drm_device *dev)
{
8016
	drm_i915_private_t *dev_priv = dev->dev_private;
8017 8018 8019
	struct intel_crtc *crtc;
	struct intel_encoder *encoder;
	struct intel_connector *connector;
8020
	struct intel_crtc_config pipe_config;
8021 8022 8023 8024 8025 8026 8027 8028 8029 8030 8031 8032 8033 8034 8035 8036 8037 8038 8039 8040 8041 8042 8043 8044 8045 8046 8047 8048 8049 8050 8051 8052 8053 8054 8055 8056 8057 8058 8059 8060 8061 8062 8063 8064 8065 8066 8067 8068 8069 8070 8071 8072 8073 8074 8075 8076 8077 8078 8079 8080 8081 8082 8083 8084 8085 8086 8087

	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		/* This also checks the encoder/connector hw state with the
		 * ->get_hw_state callbacks. */
		intel_connector_check_state(connector);

		WARN(&connector->new_encoder->base != connector->base.encoder,
		     "connector's staged encoder doesn't match current encoder\n");
	}

	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		bool enabled = false;
		bool active = false;
		enum pipe pipe, tracked_pipe;

		DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base));

		WARN(&encoder->new_crtc->base != encoder->base.crtc,
		     "encoder's stage crtc doesn't match current crtc\n");
		WARN(encoder->connectors_active && !encoder->base.crtc,
		     "encoder's active_connectors set, but no crtc\n");

		list_for_each_entry(connector, &dev->mode_config.connector_list,
				    base.head) {
			if (connector->base.encoder != &encoder->base)
				continue;
			enabled = true;
			if (connector->base.dpms != DRM_MODE_DPMS_OFF)
				active = true;
		}
		WARN(!!encoder->base.crtc != enabled,
		     "encoder's enabled state mismatch "
		     "(expected %i, found %i)\n",
		     !!encoder->base.crtc, enabled);
		WARN(active && !encoder->base.crtc,
		     "active encoder with no crtc\n");

		WARN(encoder->connectors_active != active,
		     "encoder's computed active state doesn't match tracked active state "
		     "(expected %i, found %i)\n", active, encoder->connectors_active);

		active = encoder->get_hw_state(encoder, &pipe);
		WARN(active != encoder->connectors_active,
		     "encoder's hw state doesn't match sw tracking "
		     "(expected %i, found %i)\n",
		     encoder->connectors_active, active);

		if (!encoder->base.crtc)
			continue;

		tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		WARN(active && pipe != tracked_pipe,
		     "active encoder's pipe doesn't match"
		     "(expected %i, found %i)\n",
		     tracked_pipe, pipe);

	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
			    base.head) {
		bool enabled = false;
		bool active = false;

8088 8089
		memset(&pipe_config, 0, sizeof(pipe_config));

8090 8091 8092 8093 8094 8095 8096 8097 8098 8099 8100 8101 8102
		DRM_DEBUG_KMS("[CRTC:%d]\n",
			      crtc->base.base.id);

		WARN(crtc->active && !crtc->base.enabled,
		     "active crtc, but not enabled in sw tracking\n");

		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
				    base.head) {
			if (encoder->base.crtc != &crtc->base)
				continue;
			enabled = true;
			if (encoder->connectors_active)
				active = true;
8103 8104
			if (encoder->get_config)
				encoder->get_config(encoder, &pipe_config);
8105 8106 8107 8108 8109 8110 8111 8112
		}
		WARN(active != crtc->active,
		     "crtc's computed active state doesn't match tracked active state "
		     "(expected %i, found %i)\n", active, crtc->active);
		WARN(enabled != crtc->base.enabled,
		     "crtc's computed enabled state doesn't match tracked enabled state "
		     "(expected %i, found %i)\n", enabled, crtc->base.enabled);

8113 8114 8115 8116 8117 8118
		active = dev_priv->display.get_pipe_config(crtc,
							   &pipe_config);
		WARN(crtc->active != active,
		     "crtc active state doesn't match with hw state "
		     "(expected %i, found %i)\n", crtc->active, active);

8119 8120 8121 8122 8123 8124 8125 8126
		if (active &&
		    !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
			WARN(1, "pipe state doesn't match!\n");
			intel_dump_pipe_config(crtc, &pipe_config,
					       "[hw state]");
			intel_dump_pipe_config(crtc, &crtc->config,
					       "[sw state]");
		}
8127 8128 8129
	}
}

8130 8131 8132
static int __intel_set_mode(struct drm_crtc *crtc,
			    struct drm_display_mode *mode,
			    int x, int y, struct drm_framebuffer *fb)
8133 8134
{
	struct drm_device *dev = crtc->dev;
8135
	drm_i915_private_t *dev_priv = dev->dev_private;
8136 8137
	struct drm_display_mode *saved_mode, *saved_hwmode;
	struct intel_crtc_config *pipe_config = NULL;
8138 8139
	struct intel_crtc *intel_crtc;
	unsigned disable_pipes, prepare_pipes, modeset_pipes;
8140
	int ret = 0;
8141

8142
	saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8143 8144
	if (!saved_mode)
		return -ENOMEM;
8145
	saved_hwmode = saved_mode + 1;
8146

8147
	intel_modeset_affected_pipes(crtc, &modeset_pipes,
8148 8149
				     &prepare_pipes, &disable_pipes);

8150 8151
	*saved_hwmode = crtc->hwmode;
	*saved_mode = crtc->mode;
8152

8153 8154 8155 8156 8157 8158
	/* Hack: Because we don't (yet) support global modeset on multiple
	 * crtcs, we don't keep track of the new mode for more than one crtc.
	 * Hence simply check whether any bit is set in modeset_pipes in all the
	 * pieces of code that are not yet converted to deal with mutliple crtcs
	 * changing their mode at the same time. */
	if (modeset_pipes) {
8159
		pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8160 8161 8162 8163
		if (IS_ERR(pipe_config)) {
			ret = PTR_ERR(pipe_config);
			pipe_config = NULL;

8164
			goto out;
8165
		}
8166 8167
		intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
				       "[modeset]");
8168
	}
8169

8170 8171 8172
	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		intel_crtc_disable(&intel_crtc->base);

8173 8174 8175 8176
	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		if (intel_crtc->base.enabled)
			dev_priv->display.crtc_disable(&intel_crtc->base);
	}
8177

8178 8179
	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
	 * to set it here already despite that we pass it down the callchain.
8180
	 */
8181
	if (modeset_pipes) {
8182
		crtc->mode = *mode;
8183 8184 8185 8186
		/* mode_set/enable/disable functions rely on a correct pipe
		 * config. */
		to_intel_crtc(crtc)->config = *pipe_config;
	}
8187

8188 8189 8190
	/* Only after disabling all output pipelines that will be changed can we
	 * update the the output configuration. */
	intel_modeset_update_state(dev, prepare_pipes);
8191

8192 8193 8194
	if (dev_priv->display.modeset_global_resources)
		dev_priv->display.modeset_global_resources(dev);

8195 8196
	/* Set up the DPLL and any encoders state that needs to adjust or depend
	 * on the DPLL.
8197
	 */
8198
	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8199 8200 8201 8202
		ret = intel_crtc_mode_set(&intel_crtc->base,
					  x, y, fb);
		if (ret)
			goto done;
8203 8204 8205
	}

	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
8206 8207
	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
		dev_priv->display.crtc_enable(&intel_crtc->base);
8208

8209 8210
	if (modeset_pipes) {
		/* Store real post-adjustment hardware mode. */
8211
		crtc->hwmode = pipe_config->adjusted_mode;
8212

8213 8214 8215 8216 8217 8218
		/* Calculate and store various constants which
		 * are later needed by vblank and swap-completion
		 * timestamping. They are derived from true hwmode.
		 */
		drm_calc_timestamping_constants(crtc);
	}
8219 8220 8221

	/* FIXME: add subpixel order */
done:
8222
	if (ret && crtc->enabled) {
8223 8224
		crtc->hwmode = *saved_hwmode;
		crtc->mode = *saved_mode;
8225 8226
	}

8227
out:
8228
	kfree(pipe_config);
8229
	kfree(saved_mode);
8230
	return ret;
8231 8232
}

8233 8234 8235 8236 8237 8238 8239 8240 8241 8242 8243 8244 8245 8246
int intel_set_mode(struct drm_crtc *crtc,
		     struct drm_display_mode *mode,
		     int x, int y, struct drm_framebuffer *fb)
{
	int ret;

	ret = __intel_set_mode(crtc, mode, x, y, fb);

	if (ret == 0)
		intel_modeset_check_state(crtc->dev);

	return ret;
}

8247 8248 8249 8250 8251
void intel_crtc_restore_mode(struct drm_crtc *crtc)
{
	intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
}

8252 8253
#undef for_each_intel_crtc_masked

8254 8255 8256 8257 8258
static void intel_set_config_free(struct intel_set_config *config)
{
	if (!config)
		return;

8259 8260
	kfree(config->save_connector_encoders);
	kfree(config->save_encoder_crtcs);
8261 8262 8263
	kfree(config);
}

8264 8265 8266 8267 8268 8269 8270
static int intel_set_config_save_state(struct drm_device *dev,
				       struct intel_set_config *config)
{
	struct drm_encoder *encoder;
	struct drm_connector *connector;
	int count;

8271 8272 8273 8274
	config->save_encoder_crtcs =
		kcalloc(dev->mode_config.num_encoder,
			sizeof(struct drm_crtc *), GFP_KERNEL);
	if (!config->save_encoder_crtcs)
8275 8276
		return -ENOMEM;

8277 8278 8279 8280
	config->save_connector_encoders =
		kcalloc(dev->mode_config.num_connector,
			sizeof(struct drm_encoder *), GFP_KERNEL);
	if (!config->save_connector_encoders)
8281 8282 8283 8284 8285 8286 8287 8288
		return -ENOMEM;

	/* Copy data. Note that driver private data is not affected.
	 * Should anything bad happen only the expected state is
	 * restored, not the drivers personal bookkeeping.
	 */
	count = 0;
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8289
		config->save_encoder_crtcs[count++] = encoder->crtc;
8290 8291 8292 8293
	}

	count = 0;
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8294
		config->save_connector_encoders[count++] = connector->encoder;
8295 8296 8297 8298 8299 8300 8301 8302
	}

	return 0;
}

static void intel_set_config_restore_state(struct drm_device *dev,
					   struct intel_set_config *config)
{
8303 8304
	struct intel_encoder *encoder;
	struct intel_connector *connector;
8305 8306 8307
	int count;

	count = 0;
8308 8309 8310
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		encoder->new_crtc =
			to_intel_crtc(config->save_encoder_crtcs[count++]);
8311 8312 8313
	}

	count = 0;
8314 8315 8316
	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		connector->new_encoder =
			to_intel_encoder(config->save_connector_encoders[count++]);
8317 8318 8319
	}
}

8320 8321 8322 8323 8324 8325 8326 8327 8328 8329 8330 8331 8332 8333
static void
intel_set_config_compute_mode_changes(struct drm_mode_set *set,
				      struct intel_set_config *config)
{

	/* We should be able to check here if the fb has the same properties
	 * and then just flip_or_move it */
	if (set->crtc->fb != set->fb) {
		/* If we have no fb then treat it as a full mode set */
		if (set->crtc->fb == NULL) {
			DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
			config->mode_changed = true;
		} else if (set->fb == NULL) {
			config->mode_changed = true;
8334 8335
		} else if (set->fb->pixel_format !=
			   set->crtc->fb->pixel_format) {
8336 8337 8338 8339 8340
			config->mode_changed = true;
		} else
			config->fb_changed = true;
	}

8341
	if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8342 8343 8344 8345 8346 8347 8348 8349 8350 8351
		config->fb_changed = true;

	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		DRM_DEBUG_KMS("modes are different, full mode set\n");
		drm_mode_debug_printmodeline(&set->crtc->mode);
		drm_mode_debug_printmodeline(set->mode);
		config->mode_changed = true;
	}
}

8352
static int
8353 8354 8355
intel_modeset_stage_output_state(struct drm_device *dev,
				 struct drm_mode_set *set,
				 struct intel_set_config *config)
8356
{
8357
	struct drm_crtc *new_crtc;
8358 8359
	struct intel_connector *connector;
	struct intel_encoder *encoder;
8360
	int count, ro;
8361

8362
	/* The upper layers ensure that we either disable a crtc or have a list
8363 8364 8365 8366
	 * of connectors. For paranoia, double-check this. */
	WARN_ON(!set->fb && (set->num_connectors != 0));
	WARN_ON(set->fb && (set->num_connectors == 0));

8367
	count = 0;
8368 8369 8370 8371
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		/* Otherwise traverse passed in connector list and get encoders
		 * for them. */
8372
		for (ro = 0; ro < set->num_connectors; ro++) {
8373 8374
			if (set->connectors[ro] == &connector->base) {
				connector->new_encoder = connector->encoder;
8375 8376 8377 8378
				break;
			}
		}

8379 8380 8381 8382 8383 8384 8385 8386 8387 8388 8389 8390 8391 8392 8393
		/* If we disable the crtc, disable all its connectors. Also, if
		 * the connector is on the changing crtc but not on the new
		 * connector list, disable it. */
		if ((!set->fb || ro == set->num_connectors) &&
		    connector->base.encoder &&
		    connector->base.encoder->crtc == set->crtc) {
			connector->new_encoder = NULL;

			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
				connector->base.base.id,
				drm_get_connector_name(&connector->base));
		}


		if (&connector->new_encoder->base != connector->base.encoder) {
8394
			DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8395
			config->mode_changed = true;
8396 8397
		}
	}
8398
	/* connector->new_encoder is now updated for all connectors. */
8399

8400
	/* Update crtc of enabled connectors. */
8401
	count = 0;
8402 8403 8404
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (!connector->new_encoder)
8405 8406
			continue;

8407
		new_crtc = connector->new_encoder->base.crtc;
8408 8409

		for (ro = 0; ro < set->num_connectors; ro++) {
8410
			if (set->connectors[ro] == &connector->base)
8411 8412 8413 8414
				new_crtc = set->crtc;
		}

		/* Make sure the new CRTC will work with the encoder */
8415 8416
		if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
					   new_crtc)) {
8417
			return -EINVAL;
8418
		}
8419 8420 8421 8422 8423 8424 8425 8426 8427 8428 8429 8430 8431 8432 8433 8434 8435 8436 8437 8438 8439 8440 8441 8442 8443
		connector->encoder->new_crtc = to_intel_crtc(new_crtc);

		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
			connector->base.base.id,
			drm_get_connector_name(&connector->base),
			new_crtc->base.id);
	}

	/* Check for any encoders that needs to be disabled. */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		list_for_each_entry(connector,
				    &dev->mode_config.connector_list,
				    base.head) {
			if (connector->new_encoder == encoder) {
				WARN_ON(!connector->new_encoder->new_crtc);

				goto next_encoder;
			}
		}
		encoder->new_crtc = NULL;
next_encoder:
		/* Only now check for crtc changes so we don't miss encoders
		 * that will be disabled. */
		if (&encoder->new_crtc->base != encoder->base.crtc) {
8444
			DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8445
			config->mode_changed = true;
8446 8447
		}
	}
8448
	/* Now we've also updated encoder->new_crtc for all encoders. */
8449

8450 8451 8452 8453 8454 8455 8456 8457 8458 8459
	return 0;
}

static int intel_crtc_set_config(struct drm_mode_set *set)
{
	struct drm_device *dev;
	struct drm_mode_set save_set;
	struct intel_set_config *config;
	int ret;

8460 8461 8462
	BUG_ON(!set);
	BUG_ON(!set->crtc);
	BUG_ON(!set->crtc->helper_private);
8463

8464 8465 8466
	/* Enforce sane interface api - has been abused by the fb helper. */
	BUG_ON(!set->mode && set->fb);
	BUG_ON(set->fb && set->num_connectors == 0);
8467

8468 8469 8470 8471 8472 8473 8474 8475 8476 8477 8478 8479 8480 8481 8482 8483 8484 8485 8486 8487 8488 8489 8490 8491 8492 8493 8494 8495 8496 8497 8498
	if (set->fb) {
		DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
				set->crtc->base.id, set->fb->base.id,
				(int)set->num_connectors, set->x, set->y);
	} else {
		DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
	}

	dev = set->crtc->dev;

	ret = -ENOMEM;
	config = kzalloc(sizeof(*config), GFP_KERNEL);
	if (!config)
		goto out_config;

	ret = intel_set_config_save_state(dev, config);
	if (ret)
		goto out_config;

	save_set.crtc = set->crtc;
	save_set.mode = &set->crtc->mode;
	save_set.x = set->crtc->x;
	save_set.y = set->crtc->y;
	save_set.fb = set->crtc->fb;

	/* Compute whether we need a full modeset, only an fb base update or no
	 * change at all. In the future we might also check whether only the
	 * mode changed, e.g. for LVDS where we only change the panel fitter in
	 * such cases. */
	intel_set_config_compute_mode_changes(set, config);

8499
	ret = intel_modeset_stage_output_state(dev, set, config);
8500 8501 8502
	if (ret)
		goto fail;

8503
	if (config->mode_changed) {
8504 8505 8506 8507 8508
		ret = intel_set_mode(set->crtc, set->mode,
				     set->x, set->y, set->fb);
		if (ret) {
			DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
				  set->crtc->base.id, ret);
8509 8510
			goto fail;
		}
8511
	} else if (config->fb_changed) {
8512 8513
		intel_crtc_wait_for_pending_flips(set->crtc);

D
Daniel Vetter 已提交
8514
		ret = intel_pipe_set_base(set->crtc,
8515
					  set->x, set->y, set->fb);
8516 8517
	}

8518 8519
	intel_set_config_free(config);

8520 8521 8522
	return 0;

fail:
8523
	intel_set_config_restore_state(dev, config);
8524 8525

	/* Try to restore the config */
8526
	if (config->mode_changed &&
8527 8528
	    intel_set_mode(save_set.crtc, save_set.mode,
			   save_set.x, save_set.y, save_set.fb))
8529 8530
		DRM_ERROR("failed to restore config after modeset failure\n");

8531 8532
out_config:
	intel_set_config_free(config);
8533 8534
	return ret;
}
8535 8536 8537 8538 8539

static const struct drm_crtc_funcs intel_crtc_funcs = {
	.cursor_set = intel_crtc_cursor_set,
	.cursor_move = intel_crtc_cursor_move,
	.gamma_set = intel_crtc_gamma_set,
8540
	.set_config = intel_crtc_set_config,
8541 8542 8543 8544
	.destroy = intel_crtc_destroy,
	.page_flip = intel_crtc_page_flip,
};

P
Paulo Zanoni 已提交
8545 8546
static void intel_cpu_pll_init(struct drm_device *dev)
{
P
Paulo Zanoni 已提交
8547
	if (HAS_DDI(dev))
P
Paulo Zanoni 已提交
8548 8549 8550
		intel_ddi_pll_init(dev);
}

8551 8552 8553 8554 8555 8556 8557 8558 8559 8560 8561 8562 8563 8564 8565 8566 8567
static void intel_pch_pll_init(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int i;

	if (dev_priv->num_pch_pll == 0) {
		DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
		return;
	}

	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
		dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
		dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
	}
}

8568
static void intel_crtc_init(struct drm_device *dev, int pipe)
J
Jesse Barnes 已提交
8569
{
J
Jesse Barnes 已提交
8570
	drm_i915_private_t *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
8571 8572 8573 8574 8575 8576 8577 8578 8579 8580 8581 8582 8583 8584 8585 8586
	struct intel_crtc *intel_crtc;
	int i;

	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
	if (intel_crtc == NULL)
		return;

	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);

	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
	for (i = 0; i < 256; i++) {
		intel_crtc->lut_r[i] = i;
		intel_crtc->lut_g[i] = i;
		intel_crtc->lut_b[i] = i;
	}

8587 8588 8589
	/* Swap pipes & planes for FBC on pre-965 */
	intel_crtc->pipe = pipe;
	intel_crtc->plane = pipe;
8590
	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8591
		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8592
		intel_crtc->plane = !pipe;
8593 8594
	}

J
Jesse Barnes 已提交
8595 8596 8597 8598 8599
	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;

J
Jesse Barnes 已提交
8600 8601 8602
	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
}

8603
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8604
				struct drm_file *file)
8605 8606
{
	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8607 8608
	struct drm_mode_object *drmmode_obj;
	struct intel_crtc *crtc;
8609

8610 8611
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
8612

8613 8614
	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
			DRM_MODE_OBJECT_CRTC);
8615

8616
	if (!drmmode_obj) {
8617 8618 8619 8620
		DRM_ERROR("no such CRTC id\n");
		return -EINVAL;
	}

8621 8622
	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
	pipe_from_crtc_id->pipe = crtc->pipe;
8623

8624
	return 0;
8625 8626
}

8627
static int intel_encoder_clones(struct intel_encoder *encoder)
J
Jesse Barnes 已提交
8628
{
8629 8630
	struct drm_device *dev = encoder->base.dev;
	struct intel_encoder *source_encoder;
J
Jesse Barnes 已提交
8631 8632 8633
	int index_mask = 0;
	int entry = 0;

8634 8635 8636 8637
	list_for_each_entry(source_encoder,
			    &dev->mode_config.encoder_list, base.head) {

		if (encoder == source_encoder)
J
Jesse Barnes 已提交
8638
			index_mask |= (1 << entry);
8639 8640 8641 8642 8643

		/* Intel hw has only one MUX where enocoders could be cloned. */
		if (encoder->cloneable && source_encoder->cloneable)
			index_mask |= (1 << entry);

J
Jesse Barnes 已提交
8644 8645
		entry++;
	}
8646

J
Jesse Barnes 已提交
8647 8648 8649
	return index_mask;
}

8650 8651 8652 8653 8654 8655 8656 8657 8658 8659 8660 8661 8662 8663 8664 8665 8666
static bool has_edp_a(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!IS_MOBILE(dev))
		return false;

	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		return false;

	if (IS_GEN5(dev) &&
	    (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		return false;

	return true;
}

J
Jesse Barnes 已提交
8667 8668
static void intel_setup_outputs(struct drm_device *dev)
{
8669
	struct drm_i915_private *dev_priv = dev->dev_private;
8670
	struct intel_encoder *encoder;
8671
	bool dpd_is_edp = false;
8672
	bool has_lvds;
J
Jesse Barnes 已提交
8673

8674
	has_lvds = intel_lvds_init(dev);
8675 8676 8677 8678
	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
		/* disable the panel fitter on everything but LVDS */
		I915_WRITE(PFIT_CONTROL, 0);
	}
J
Jesse Barnes 已提交
8679

8680
	if (!IS_ULT(dev))
8681
		intel_crt_init(dev);
8682

P
Paulo Zanoni 已提交
8683
	if (HAS_DDI(dev)) {
8684 8685 8686 8687 8688 8689 8690 8691 8692 8693 8694 8695 8696 8697 8698 8699 8700 8701 8702
		int found;

		/* Haswell uses DDI functions to detect digital outputs */
		found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		/* DDI A only supports eDP */
		if (found)
			intel_ddi_init(dev, PORT_A);

		/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		 * register */
		found = I915_READ(SFUSE_STRAP);

		if (found & SFUSE_STRAP_DDIB_DETECTED)
			intel_ddi_init(dev, PORT_B);
		if (found & SFUSE_STRAP_DDIC_DETECTED)
			intel_ddi_init(dev, PORT_C);
		if (found & SFUSE_STRAP_DDID_DETECTED)
			intel_ddi_init(dev, PORT_D);
	} else if (HAS_PCH_SPLIT(dev)) {
8703
		int found;
8704 8705 8706 8707
		dpd_is_edp = intel_dpd_is_edp(dev);

		if (has_edp_a(dev))
			intel_dp_init(dev, DP_A, PORT_A);
8708

8709
		if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8710
			/* PCH SDVOB multiplex with HDMIB */
8711
			found = intel_sdvo_init(dev, PCH_SDVOB, true);
8712
			if (!found)
8713
				intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8714
			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8715
				intel_dp_init(dev, PCH_DP_B, PORT_B);
8716 8717
		}

8718
		if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8719
			intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8720

8721
		if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8722
			intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8723

8724
		if (I915_READ(PCH_DP_C) & DP_DETECTED)
8725
			intel_dp_init(dev, PCH_DP_C, PORT_C);
8726

8727
		if (I915_READ(PCH_DP_D) & DP_DETECTED)
8728
			intel_dp_init(dev, PCH_DP_D, PORT_D);
8729
	} else if (IS_VALLEYVIEW(dev)) {
8730
		/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8731 8732
		if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
			intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8733

8734
		if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8735 8736
			intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
					PORT_B);
8737 8738
			if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
				intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8739
		}
8740
	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8741
		bool found = false;
8742

8743
		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8744
			DRM_DEBUG_KMS("probing SDVOB\n");
8745
			found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8746 8747
			if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8748
				intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8749
			}
8750

8751
			if (!found && SUPPORTS_INTEGRATED_DP(dev))
8752
				intel_dp_init(dev, DP_B, PORT_B);
8753
		}
8754 8755 8756

		/* Before G4X SDVOC doesn't have its own detect register */

8757
		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8758
			DRM_DEBUG_KMS("probing SDVOC\n");
8759
			found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8760
		}
8761

8762
		if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8763

8764 8765
			if (SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8766
				intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8767
			}
8768
			if (SUPPORTS_INTEGRATED_DP(dev))
8769
				intel_dp_init(dev, DP_C, PORT_C);
8770
		}
8771

8772
		if (SUPPORTS_INTEGRATED_DP(dev) &&
8773
		    (I915_READ(DP_D) & DP_DETECTED))
8774
			intel_dp_init(dev, DP_D, PORT_D);
8775
	} else if (IS_GEN2(dev))
J
Jesse Barnes 已提交
8776 8777
		intel_dvo_init(dev);

8778
	if (SUPPORTS_TV(dev))
J
Jesse Barnes 已提交
8779 8780
		intel_tv_init(dev);

8781 8782 8783
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		encoder->base.possible_crtcs = encoder->crtc_mask;
		encoder->base.possible_clones =
8784
			intel_encoder_clones(encoder);
J
Jesse Barnes 已提交
8785
	}
8786

P
Paulo Zanoni 已提交
8787
	intel_init_pch_refclk(dev);
8788 8789

	drm_helper_move_panel_connectors_to_head(dev);
J
Jesse Barnes 已提交
8790 8791 8792 8793 8794 8795 8796
}

static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

	drm_framebuffer_cleanup(fb);
8797
	drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
J
Jesse Barnes 已提交
8798 8799 8800 8801 8802

	kfree(intel_fb);
}

static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8803
						struct drm_file *file,
J
Jesse Barnes 已提交
8804 8805 8806
						unsigned int *handle)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8807
	struct drm_i915_gem_object *obj = intel_fb->obj;
J
Jesse Barnes 已提交
8808

8809
	return drm_gem_handle_create(file, &obj->base, handle);
J
Jesse Barnes 已提交
8810 8811 8812 8813 8814 8815 8816
}

static const struct drm_framebuffer_funcs intel_fb_funcs = {
	.destroy = intel_user_framebuffer_destroy,
	.create_handle = intel_user_framebuffer_create_handle,
};

8817 8818
int intel_framebuffer_init(struct drm_device *dev,
			   struct intel_framebuffer *intel_fb,
8819
			   struct drm_mode_fb_cmd2 *mode_cmd,
8820
			   struct drm_i915_gem_object *obj)
J
Jesse Barnes 已提交
8821 8822 8823
{
	int ret;

8824 8825
	if (obj->tiling_mode == I915_TILING_Y) {
		DRM_DEBUG("hardware does not support tiling Y\n");
8826
		return -EINVAL;
8827
	}
8828

8829 8830 8831
	if (mode_cmd->pitches[0] & 63) {
		DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
			  mode_cmd->pitches[0]);
8832
		return -EINVAL;
8833
	}
8834

8835
	/* FIXME <= Gen4 stride limits are bit unclear */
8836 8837 8838
	if (mode_cmd->pitches[0] > 32768) {
		DRM_DEBUG("pitch (%d) must be at less than 32768\n",
			  mode_cmd->pitches[0]);
8839
		return -EINVAL;
8840
	}
8841 8842

	if (obj->tiling_mode != I915_TILING_NONE &&
8843 8844 8845
	    mode_cmd->pitches[0] != obj->stride) {
		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
			  mode_cmd->pitches[0], obj->stride);
8846
		return -EINVAL;
8847
	}
8848

8849
	/* Reject formats not supported by any plane early. */
8850
	switch (mode_cmd->pixel_format) {
8851
	case DRM_FORMAT_C8:
V
Ville Syrjälä 已提交
8852 8853 8854
	case DRM_FORMAT_RGB565:
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
8855 8856 8857
		break;
	case DRM_FORMAT_XRGB1555:
	case DRM_FORMAT_ARGB1555:
8858 8859
		if (INTEL_INFO(dev)->gen > 3) {
			DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8860
			return -EINVAL;
8861
		}
8862 8863 8864
		break;
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
V
Ville Syrjälä 已提交
8865 8866
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
8867 8868
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
8869 8870
		if (INTEL_INFO(dev)->gen < 4) {
			DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8871
			return -EINVAL;
8872
		}
8873
		break;
V
Ville Syrjälä 已提交
8874 8875 8876 8877
	case DRM_FORMAT_YUYV:
	case DRM_FORMAT_UYVY:
	case DRM_FORMAT_YVYU:
	case DRM_FORMAT_VYUY:
8878 8879
		if (INTEL_INFO(dev)->gen < 5) {
			DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8880
			return -EINVAL;
8881
		}
8882 8883
		break;
	default:
8884
		DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8885 8886 8887
		return -EINVAL;
	}

8888 8889 8890 8891
	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
	if (mode_cmd->offsets[0] != 0)
		return -EINVAL;

8892 8893 8894
	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
	intel_fb->obj = obj;

J
Jesse Barnes 已提交
8895 8896 8897 8898 8899 8900 8901 8902 8903 8904 8905 8906
	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
	if (ret) {
		DRM_ERROR("framebuffer init failed %d\n", ret);
		return ret;
	}

	return 0;
}

static struct drm_framebuffer *
intel_user_framebuffer_create(struct drm_device *dev,
			      struct drm_file *filp,
8907
			      struct drm_mode_fb_cmd2 *mode_cmd)
J
Jesse Barnes 已提交
8908
{
8909
	struct drm_i915_gem_object *obj;
J
Jesse Barnes 已提交
8910

8911 8912
	obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
						mode_cmd->handles[0]));
8913
	if (&obj->base == NULL)
8914
		return ERR_PTR(-ENOENT);
J
Jesse Barnes 已提交
8915

8916
	return intel_framebuffer_create(dev, mode_cmd, obj);
J
Jesse Barnes 已提交
8917 8918 8919 8920
}

static const struct drm_mode_config_funcs intel_mode_funcs = {
	.fb_create = intel_user_framebuffer_create,
8921
	.output_poll_changed = intel_fb_output_poll_changed,
J
Jesse Barnes 已提交
8922 8923
};

8924 8925 8926 8927 8928
/* Set up chip specific display functions */
static void intel_init_display(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

P
Paulo Zanoni 已提交
8929
	if (HAS_DDI(dev)) {
8930
		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
P
Paulo Zanoni 已提交
8931
		dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8932 8933
		dev_priv->display.crtc_enable = haswell_crtc_enable;
		dev_priv->display.crtc_disable = haswell_crtc_disable;
8934
		dev_priv->display.off = haswell_crtc_off;
P
Paulo Zanoni 已提交
8935 8936
		dev_priv->display.update_plane = ironlake_update_plane;
	} else if (HAS_PCH_SPLIT(dev)) {
8937
		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8938
		dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8939 8940
		dev_priv->display.crtc_enable = ironlake_crtc_enable;
		dev_priv->display.crtc_disable = ironlake_crtc_disable;
8941
		dev_priv->display.off = ironlake_crtc_off;
8942
		dev_priv->display.update_plane = ironlake_update_plane;
8943 8944 8945 8946 8947 8948 8949
	} else if (IS_VALLEYVIEW(dev)) {
		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
		dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
		dev_priv->display.crtc_enable = valleyview_crtc_enable;
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
		dev_priv->display.off = i9xx_crtc_off;
		dev_priv->display.update_plane = i9xx_update_plane;
8950
	} else {
8951
		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8952
		dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8953 8954
		dev_priv->display.crtc_enable = i9xx_crtc_enable;
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
8955
		dev_priv->display.off = i9xx_crtc_off;
8956
		dev_priv->display.update_plane = i9xx_update_plane;
8957
	}
8958 8959

	/* Returns the core display clock speed */
J
Jesse Barnes 已提交
8960 8961 8962 8963
	if (IS_VALLEYVIEW(dev))
		dev_priv->display.get_display_clock_speed =
			valleyview_get_display_clock_speed;
	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8964 8965 8966 8967 8968
		dev_priv->display.get_display_clock_speed =
			i945_get_display_clock_speed;
	else if (IS_I915G(dev))
		dev_priv->display.get_display_clock_speed =
			i915_get_display_clock_speed;
8969
	else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8970 8971 8972 8973 8974 8975 8976 8977
		dev_priv->display.get_display_clock_speed =
			i9xx_misc_get_display_clock_speed;
	else if (IS_I915GM(dev))
		dev_priv->display.get_display_clock_speed =
			i915gm_get_display_clock_speed;
	else if (IS_I865G(dev))
		dev_priv->display.get_display_clock_speed =
			i865_get_display_clock_speed;
8978
	else if (IS_I85X(dev))
8979 8980 8981 8982 8983 8984
		dev_priv->display.get_display_clock_speed =
			i855_get_display_clock_speed;
	else /* 852, 830 */
		dev_priv->display.get_display_clock_speed =
			i830_get_display_clock_speed;

8985
	if (HAS_PCH_SPLIT(dev)) {
8986
		if (IS_GEN5(dev)) {
8987
			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8988
			dev_priv->display.write_eld = ironlake_write_eld;
8989
		} else if (IS_GEN6(dev)) {
8990
			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8991
			dev_priv->display.write_eld = ironlake_write_eld;
8992 8993 8994
		} else if (IS_IVYBRIDGE(dev)) {
			/* FIXME: detect B0+ stepping and use auto training */
			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8995
			dev_priv->display.write_eld = ironlake_write_eld;
8996 8997
			dev_priv->display.modeset_global_resources =
				ivb_modeset_global_resources;
8998 8999
		} else if (IS_HASWELL(dev)) {
			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9000
			dev_priv->display.write_eld = haswell_write_eld;
9001 9002
			dev_priv->display.modeset_global_resources =
				haswell_modeset_global_resources;
9003
		}
9004
	} else if (IS_G4X(dev)) {
9005
		dev_priv->display.write_eld = g4x_write_eld;
9006
	}
9007 9008 9009 9010 9011 9012 9013 9014 9015 9016 9017 9018 9019 9020 9021 9022 9023 9024 9025 9026 9027

	/* Default just returns -ENODEV to indicate unsupported */
	dev_priv->display.queue_flip = intel_default_queue_flip;

	switch (INTEL_INFO(dev)->gen) {
	case 2:
		dev_priv->display.queue_flip = intel_gen2_queue_flip;
		break;

	case 3:
		dev_priv->display.queue_flip = intel_gen3_queue_flip;
		break;

	case 4:
	case 5:
		dev_priv->display.queue_flip = intel_gen4_queue_flip;
		break;

	case 6:
		dev_priv->display.queue_flip = intel_gen6_queue_flip;
		break;
9028 9029 9030
	case 7:
		dev_priv->display.queue_flip = intel_gen7_queue_flip;
		break;
9031
	}
9032 9033
}

9034 9035 9036 9037 9038
/*
 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
 * resume, or other times.  This quirk makes sure that's the case for
 * affected systems.
 */
9039
static void quirk_pipea_force(struct drm_device *dev)
9040 9041 9042 9043
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9044
	DRM_INFO("applying pipe a force quirk\n");
9045 9046
}

9047 9048 9049 9050 9051 9052 9053
/*
 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
 */
static void quirk_ssc_force_disable(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9054
	DRM_INFO("applying lvds SSC disable quirk\n");
9055 9056
}

9057
/*
9058 9059
 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
 * brightness value
9060 9061 9062 9063 9064
 */
static void quirk_invert_brightness(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9065
	DRM_INFO("applying inverted panel brightness quirk\n");
9066 9067
}

9068 9069 9070 9071 9072 9073 9074
struct intel_quirk {
	int device;
	int subsystem_vendor;
	int subsystem_device;
	void (*hook)(struct drm_device *dev);
};

9075 9076 9077 9078 9079 9080 9081 9082 9083 9084 9085 9086 9087 9088 9089 9090 9091 9092 9093 9094 9095 9096 9097 9098 9099 9100 9101 9102
/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
struct intel_dmi_quirk {
	void (*hook)(struct drm_device *dev);
	const struct dmi_system_id (*dmi_id_list)[];
};

static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
{
	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
	return 1;
}

static const struct intel_dmi_quirk intel_dmi_quirks[] = {
	{
		.dmi_id_list = &(const struct dmi_system_id[]) {
			{
				.callback = intel_dmi_reverse_brightness,
				.ident = "NCR Corporation",
				.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
					    DMI_MATCH(DMI_PRODUCT_NAME, ""),
				},
			},
			{ }  /* terminating entry */
		},
		.hook = quirk_invert_brightness,
	},
};

9103
static struct intel_quirk intel_quirks[] = {
9104
	/* HP Mini needs pipe A force quirk (LP: #322104) */
9105
	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9106 9107 9108 9109 9110 9111 9112

	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },

	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },

9113
	/* 830/845 need to leave pipe A & dpll A up */
9114
	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9115
	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9116 9117 9118

	/* Lenovo U160 cannot use SSC on LVDS */
	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9119 9120 9121

	/* Sony Vaio Y cannot use SSC on LVDS */
	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9122 9123 9124

	/* Acer Aspire 5734Z must invert backlight brightness */
	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9125 9126 9127

	/* Acer/eMachines G725 */
	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9128 9129 9130

	/* Acer/eMachines e725 */
	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9131 9132 9133

	/* Acer/Packard Bell NCL20 */
	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9134 9135 9136

	/* Acer Aspire 4736Z */
	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9137 9138 9139 9140 9141 9142 9143 9144 9145 9146 9147 9148 9149 9150 9151 9152 9153
};

static void intel_init_quirks(struct drm_device *dev)
{
	struct pci_dev *d = dev->pdev;
	int i;

	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		struct intel_quirk *q = &intel_quirks[i];

		if (d->device == q->device &&
		    (d->subsystem_vendor == q->subsystem_vendor ||
		     q->subsystem_vendor == PCI_ANY_ID) &&
		    (d->subsystem_device == q->subsystem_device ||
		     q->subsystem_device == PCI_ANY_ID))
			q->hook(dev);
	}
9154 9155 9156 9157
	for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
		if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
			intel_dmi_quirks[i].hook(dev);
	}
9158 9159
}

9160 9161 9162 9163 9164
/* Disable the VGA plane that we never use */
static void i915_disable_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u8 sr1;
9165
	u32 vga_reg = i915_vgacntrl_reg(dev);
9166 9167

	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9168
	outb(SR01, VGA_SR_INDEX);
9169 9170 9171 9172 9173 9174 9175 9176 9177
	sr1 = inb(VGA_SR_DATA);
	outb(sr1 | 1<<5, VGA_SR_DATA);
	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
	udelay(300);

	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
	POSTING_READ(vga_reg);
}

9178 9179
void intel_modeset_init_hw(struct drm_device *dev)
{
9180
	intel_init_power_well(dev);
9181

9182 9183
	intel_prepare_ddi(dev);

9184 9185
	intel_init_clock_gating(dev);

9186
	mutex_lock(&dev->struct_mutex);
9187
	intel_enable_gt_powersave(dev);
9188
	mutex_unlock(&dev->struct_mutex);
9189 9190
}

9191 9192 9193 9194 9195
void intel_modeset_suspend_hw(struct drm_device *dev)
{
	intel_suspend_hw(dev);
}

J
Jesse Barnes 已提交
9196 9197
void intel_modeset_init(struct drm_device *dev)
{
9198
	struct drm_i915_private *dev_priv = dev->dev_private;
9199
	int i, j, ret;
J
Jesse Barnes 已提交
9200 9201 9202 9203 9204 9205

	drm_mode_config_init(dev);

	dev->mode_config.min_width = 0;
	dev->mode_config.min_height = 0;

9206 9207 9208
	dev->mode_config.preferred_depth = 24;
	dev->mode_config.prefer_shadow = 1;

9209
	dev->mode_config.funcs = &intel_mode_funcs;
J
Jesse Barnes 已提交
9210

9211 9212
	intel_init_quirks(dev);

9213 9214
	intel_init_pm(dev);

B
Ben Widawsky 已提交
9215 9216 9217
	if (INTEL_INFO(dev)->num_pipes == 0)
		return;

9218 9219
	intel_init_display(dev);

9220 9221 9222 9223
	if (IS_GEN2(dev)) {
		dev->mode_config.max_width = 2048;
		dev->mode_config.max_height = 2048;
	} else if (IS_GEN3(dev)) {
9224 9225
		dev->mode_config.max_width = 4096;
		dev->mode_config.max_height = 4096;
J
Jesse Barnes 已提交
9226
	} else {
9227 9228
		dev->mode_config.max_width = 8192;
		dev->mode_config.max_height = 8192;
J
Jesse Barnes 已提交
9229
	}
B
Ben Widawsky 已提交
9230
	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
J
Jesse Barnes 已提交
9231

9232
	DRM_DEBUG_KMS("%d display pipe%s available.\n",
9233 9234
		      INTEL_INFO(dev)->num_pipes,
		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
J
Jesse Barnes 已提交
9235

9236
	for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
J
Jesse Barnes 已提交
9237
		intel_crtc_init(dev, i);
9238 9239 9240
		for (j = 0; j < dev_priv->num_plane; j++) {
			ret = intel_plane_init(dev, i, j);
			if (ret)
9241 9242
				DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
					      pipe_name(i), sprite_name(i, j), ret);
9243
		}
J
Jesse Barnes 已提交
9244 9245
	}

P
Paulo Zanoni 已提交
9246
	intel_cpu_pll_init(dev);
9247 9248
	intel_pch_pll_init(dev);

9249 9250
	/* Just disable it once at startup */
	i915_disable_vga(dev);
J
Jesse Barnes 已提交
9251
	intel_setup_outputs(dev);
9252 9253 9254

	/* Just in case the BIOS is doing something questionable. */
	intel_disable_fbc(dev);
9255 9256
}

9257 9258 9259 9260 9261 9262 9263 9264 9265
static void
intel_connector_break_all_links(struct intel_connector *connector)
{
	connector->base.dpms = DRM_MODE_DPMS_OFF;
	connector->base.encoder = NULL;
	connector->encoder->connectors_active = false;
	connector->encoder->base.crtc = NULL;
}

9266 9267 9268 9269 9270 9271 9272 9273 9274 9275 9276 9277 9278 9279 9280 9281 9282 9283 9284 9285 9286 9287 9288 9289
static void intel_enable_pipe_a(struct drm_device *dev)
{
	struct intel_connector *connector;
	struct drm_connector *crt = NULL;
	struct intel_load_detect_pipe load_detect_temp;

	/* We can't just switch on the pipe A, we need to set things up with a
	 * proper mode and output configuration. As a gross hack, enable pipe A
	 * by enabling the load detect pipe once. */
	list_for_each_entry(connector,
			    &dev->mode_config.connector_list,
			    base.head) {
		if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
			crt = &connector->base;
			break;
		}
	}

	if (!crt)
		return;

	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
		intel_release_load_detect_pipe(crt, &load_detect_temp);

9290

9291 9292
}

9293 9294 9295
static bool
intel_check_plane_mapping(struct intel_crtc *crtc)
{
9296 9297
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
9298 9299
	u32 reg, val;

9300
	if (INTEL_INFO(dev)->num_pipes == 1)
9301 9302 9303 9304 9305 9306 9307 9308 9309 9310 9311 9312
		return true;

	reg = DSPCNTR(!crtc->plane);
	val = I915_READ(reg);

	if ((val & DISPLAY_PLANE_ENABLE) &&
	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
		return false;

	return true;
}

9313 9314 9315 9316
static void intel_sanitize_crtc(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
9317
	u32 reg;
9318 9319

	/* Clear any frame start delays used for debugging left by the BIOS */
9320
	reg = PIPECONF(crtc->config.cpu_transcoder);
9321 9322 9323
	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);

	/* We need to sanitize the plane -> pipe mapping first because this will
9324 9325 9326
	 * disable the crtc (and hence change the state) if it is wrong. Note
	 * that gen4+ has a fixed plane -> pipe mapping.  */
	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9327 9328 9329 9330 9331 9332 9333 9334 9335 9336 9337 9338 9339 9340 9341 9342 9343 9344 9345 9346 9347 9348 9349 9350 9351 9352 9353
		struct intel_connector *connector;
		bool plane;

		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
			      crtc->base.base.id);

		/* Pipe has the wrong plane attached and the plane is active.
		 * Temporarily change the plane mapping and disable everything
		 * ...  */
		plane = crtc->plane;
		crtc->plane = !plane;
		dev_priv->display.crtc_disable(&crtc->base);
		crtc->plane = plane;

		/* ... and break all links. */
		list_for_each_entry(connector, &dev->mode_config.connector_list,
				    base.head) {
			if (connector->encoder->base.crtc != &crtc->base)
				continue;

			intel_connector_break_all_links(connector);
		}

		WARN_ON(crtc->active);
		crtc->base.enabled = false;
	}

9354 9355 9356 9357 9358 9359 9360 9361 9362
	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
	    crtc->pipe == PIPE_A && !crtc->active) {
		/* BIOS forgot to enable pipe A, this mostly happens after
		 * resume. Force-enable the pipe to fix this, the update_dpms
		 * call below we restore the pipe to the right state, but leave
		 * the required bits on. */
		intel_enable_pipe_a(dev);
	}

9363 9364 9365 9366 9367 9368 9369 9370 9371 9372 9373 9374 9375 9376 9377 9378 9379 9380 9381 9382 9383 9384 9385 9386 9387 9388 9389 9390 9391 9392 9393 9394 9395 9396 9397 9398 9399 9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 9410 9411 9412 9413 9414 9415 9416 9417 9418 9419 9420 9421 9422 9423 9424 9425 9426 9427 9428 9429 9430 9431 9432 9433 9434 9435 9436
	/* Adjust the state of the output pipe according to whether we
	 * have active connectors/encoders. */
	intel_crtc_update_dpms(&crtc->base);

	if (crtc->active != crtc->base.enabled) {
		struct intel_encoder *encoder;

		/* This can happen either due to bugs in the get_hw_state
		 * functions or because the pipe is force-enabled due to the
		 * pipe A quirk. */
		DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
			      crtc->base.base.id,
			      crtc->base.enabled ? "enabled" : "disabled",
			      crtc->active ? "enabled" : "disabled");

		crtc->base.enabled = crtc->active;

		/* Because we only establish the connector -> encoder ->
		 * crtc links if something is active, this means the
		 * crtc is now deactivated. Break the links. connector
		 * -> encoder links are only establish when things are
		 *  actually up, hence no need to break them. */
		WARN_ON(crtc->active);

		for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
			WARN_ON(encoder->connectors_active);
			encoder->base.crtc = NULL;
		}
	}
}

static void intel_sanitize_encoder(struct intel_encoder *encoder)
{
	struct intel_connector *connector;
	struct drm_device *dev = encoder->base.dev;

	/* We need to check both for a crtc link (meaning that the
	 * encoder is active and trying to read from a pipe) and the
	 * pipe itself being active. */
	bool has_active_crtc = encoder->base.crtc &&
		to_intel_crtc(encoder->base.crtc)->active;

	if (encoder->connectors_active && !has_active_crtc) {
		DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base));

		/* Connector is active, but has no active pipe. This is
		 * fallout from our resume register restoring. Disable
		 * the encoder manually again. */
		if (encoder->base.crtc) {
			DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
				      encoder->base.base.id,
				      drm_get_encoder_name(&encoder->base));
			encoder->disable(encoder);
		}

		/* Inconsistent output/port/pipe state happens presumably due to
		 * a bug in one of the get_hw_state functions. Or someplace else
		 * in our code, like the register restore mess on resume. Clamp
		 * things to off as a safer default. */
		list_for_each_entry(connector,
				    &dev->mode_config.connector_list,
				    base.head) {
			if (connector->encoder != encoder)
				continue;

			intel_connector_break_all_links(connector);
		}
	}
	/* Enabled encoders without active connectors will be fixed in
	 * the crtc fixup. */
}

9437
void i915_redisable_vga(struct drm_device *dev)
9438 9439
{
	struct drm_i915_private *dev_priv = dev->dev_private;
9440
	u32 vga_reg = i915_vgacntrl_reg(dev);
9441 9442 9443

	if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
		DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9444
		i915_disable_vga(dev);
9445 9446 9447
	}
}

9448 9449
/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
 * and i915 state tracking structures. */
9450 9451
void intel_modeset_setup_hw_state(struct drm_device *dev,
				  bool force_restore)
9452 9453 9454
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe;
9455
	struct drm_plane *plane;
9456 9457 9458 9459
	struct intel_crtc *crtc;
	struct intel_encoder *encoder;
	struct intel_connector *connector;

9460 9461
	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
			    base.head) {
9462
		memset(&crtc->config, 0, sizeof(crtc->config));
9463

9464 9465
		crtc->active = dev_priv->display.get_pipe_config(crtc,
								 &crtc->config);
9466 9467 9468 9469 9470 9471 9472 9473

		crtc->base.enabled = crtc->active;

		DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
			      crtc->base.base.id,
			      crtc->active ? "enabled" : "disabled");
	}

P
Paulo Zanoni 已提交
9474
	if (HAS_DDI(dev))
9475 9476
		intel_ddi_setup_hw_pll_state(dev);

9477 9478 9479 9480 9481
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		pipe = 0;

		if (encoder->get_hw_state(encoder, &pipe)) {
9482 9483 9484 9485
			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
			encoder->base.crtc = &crtc->base;
			if (encoder->get_config)
				encoder->get_config(encoder, &crtc->config);
9486 9487 9488 9489 9490 9491 9492 9493 9494 9495 9496 9497 9498 9499 9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 9510 9511 9512 9513 9514 9515 9516 9517 9518 9519 9520 9521 9522
		} else {
			encoder->base.crtc = NULL;
		}

		encoder->connectors_active = false;
		DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base),
			      encoder->base.crtc ? "enabled" : "disabled",
			      pipe);
	}

	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (connector->get_hw_state(connector)) {
			connector->base.dpms = DRM_MODE_DPMS_ON;
			connector->encoder->connectors_active = true;
			connector->base.encoder = &connector->encoder->base;
		} else {
			connector->base.dpms = DRM_MODE_DPMS_OFF;
			connector->base.encoder = NULL;
		}
		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
			      connector->base.base.id,
			      drm_get_connector_name(&connector->base),
			      connector->base.encoder ? "enabled" : "disabled");
	}

	/* HW state is read out, now we need to sanitize this mess. */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		intel_sanitize_encoder(encoder);
	}

	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		intel_sanitize_crtc(crtc);
9523
		intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9524
	}
9525

9526
	if (force_restore) {
9527 9528 9529 9530
		/*
		 * We need to use raw interfaces for restoring state to avoid
		 * checking (bogus) intermediate states.
		 */
9531
		for_each_pipe(pipe) {
9532 9533
			struct drm_crtc *crtc =
				dev_priv->pipe_to_crtc_mapping[pipe];
9534 9535 9536

			__intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
					 crtc->fb);
9537
		}
9538 9539
		list_for_each_entry(plane, &dev->mode_config.plane_list, head)
			intel_plane_restore(plane);
9540 9541

		i915_redisable_vga(dev);
9542 9543 9544
	} else {
		intel_modeset_update_staged_output_state(dev);
	}
9545 9546

	intel_modeset_check_state(dev);
9547 9548

	drm_mode_config_reset(dev);
9549 9550 9551 9552
}

void intel_modeset_gem_init(struct drm_device *dev)
{
9553
	intel_modeset_init_hw(dev);
9554 9555

	intel_setup_overlay(dev);
9556

9557
	intel_modeset_setup_hw_state(dev, false);
J
Jesse Barnes 已提交
9558 9559 9560 9561
}

void intel_modeset_cleanup(struct drm_device *dev)
{
9562 9563 9564 9565
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	struct intel_crtc *intel_crtc;

9566 9567 9568 9569 9570 9571 9572 9573 9574 9575 9576
	/*
	 * Interrupts and polling as the first thing to avoid creating havoc.
	 * Too much stuff here (turning of rps, connectors, ...) would
	 * experience fancy races otherwise.
	 */
	drm_irq_uninstall(dev);
	cancel_work_sync(&dev_priv->hotplug_work);
	/*
	 * Due to the hpd irq storm handling the hotplug work can re-arm the
	 * poll handlers. Hence disable polling after hpd handling is shut down.
	 */
9577
	drm_kms_helper_poll_fini(dev);
9578

9579 9580
	mutex_lock(&dev->struct_mutex);

J
Jesse Barnes 已提交
9581 9582
	intel_unregister_dsm_handler();

9583 9584 9585 9586 9587 9588
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		/* Skip inactive CRTCs */
		if (!crtc->fb)
			continue;

		intel_crtc = to_intel_crtc(crtc);
9589
		intel_increase_pllclock(crtc);
9590 9591
	}

9592
	intel_disable_fbc(dev);
9593

9594
	intel_disable_gt_powersave(dev);
9595

9596 9597
	ironlake_teardown_rc6(dev);

9598 9599
	mutex_unlock(&dev->struct_mutex);

9600 9601 9602
	/* flush any delayed tasks or pending work */
	flush_scheduled_work();

9603 9604 9605
	/* destroy backlight, if any, before the connectors */
	intel_panel_destroy_backlight(dev);

J
Jesse Barnes 已提交
9606
	drm_mode_config_cleanup(dev);
9607 9608

	intel_cleanup_overlay(dev);
J
Jesse Barnes 已提交
9609 9610
}

9611 9612 9613
/*
 * Return which encoder is currently attached for connector.
 */
9614
struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
J
Jesse Barnes 已提交
9615
{
9616 9617
	return &intel_attached_encoder(connector)->base;
}
9618

9619 9620 9621 9622 9623 9624
void intel_connector_attach_encoder(struct intel_connector *connector,
				    struct intel_encoder *encoder)
{
	connector->encoder = encoder;
	drm_mode_connector_attach_encoder(&connector->base,
					  &encoder->base);
J
Jesse Barnes 已提交
9625
}
9626 9627 9628 9629 9630 9631 9632 9633 9634 9635 9636 9637 9638 9639 9640 9641 9642

/*
 * set vga decode state - true == enable VGA decode
 */
int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u16 gmch_ctrl;

	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
	if (state)
		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
	else
		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
	return 0;
}
9643 9644 9645 9646 9647

#ifdef CONFIG_DEBUG_FS
#include <linux/seq_file.h>

struct intel_display_error_state {
9648 9649 9650

	u32 power_well_driver;

9651 9652 9653 9654 9655
	struct intel_cursor_error_state {
		u32 control;
		u32 position;
		u32 base;
		u32 size;
9656
	} cursor[I915_MAX_PIPES];
9657 9658

	struct intel_pipe_error_state {
9659
		enum transcoder cpu_transcoder;
9660 9661 9662 9663 9664 9665 9666 9667 9668
		u32 conf;
		u32 source;

		u32 htotal;
		u32 hblank;
		u32 hsync;
		u32 vtotal;
		u32 vblank;
		u32 vsync;
9669
	} pipe[I915_MAX_PIPES];
9670 9671 9672 9673 9674 9675 9676 9677 9678

	struct intel_plane_error_state {
		u32 control;
		u32 stride;
		u32 size;
		u32 pos;
		u32 addr;
		u32 surface;
		u32 tile_offset;
9679
	} plane[I915_MAX_PIPES];
9680 9681 9682 9683 9684
};

struct intel_display_error_state *
intel_display_capture_error_state(struct drm_device *dev)
{
9685
	drm_i915_private_t *dev_priv = dev->dev_private;
9686
	struct intel_display_error_state *error;
9687
	enum transcoder cpu_transcoder;
9688 9689 9690 9691 9692 9693
	int i;

	error = kmalloc(sizeof(*error), GFP_ATOMIC);
	if (error == NULL)
		return NULL;

9694 9695 9696
	if (HAS_POWER_WELL(dev))
		error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);

9697
	for_each_pipe(i) {
9698
		cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9699
		error->pipe[i].cpu_transcoder = cpu_transcoder;
9700

9701 9702 9703 9704 9705 9706 9707 9708 9709
		if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
			error->cursor[i].control = I915_READ(CURCNTR(i));
			error->cursor[i].position = I915_READ(CURPOS(i));
			error->cursor[i].base = I915_READ(CURBASE(i));
		} else {
			error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
			error->cursor[i].position = I915_READ(CURPOS_IVB(i));
			error->cursor[i].base = I915_READ(CURBASE_IVB(i));
		}
9710 9711 9712

		error->plane[i].control = I915_READ(DSPCNTR(i));
		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9713
		if (INTEL_INFO(dev)->gen <= 3) {
9714
			error->plane[i].size = I915_READ(DSPSIZE(i));
9715 9716
			error->plane[i].pos = I915_READ(DSPPOS(i));
		}
9717 9718
		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
			error->plane[i].addr = I915_READ(DSPADDR(i));
9719 9720 9721 9722 9723
		if (INTEL_INFO(dev)->gen >= 4) {
			error->plane[i].surface = I915_READ(DSPSURF(i));
			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		}

9724
		error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9725
		error->pipe[i].source = I915_READ(PIPESRC(i));
9726 9727 9728 9729 9730 9731
		error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
		error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
		error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
		error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
		error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
		error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9732 9733
	}

9734 9735 9736 9737 9738 9739 9740
	/* In the code above we read the registers without checking if the power
	 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
	 * prevent the next I915_WRITE from detecting it and printing an error
	 * message. */
	if (HAS_POWER_WELL(dev))
		I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);

9741 9742 9743
	return error;
}

9744 9745
#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)

9746
void
9747
intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9748 9749 9750 9751 9752
				struct drm_device *dev,
				struct intel_display_error_state *error)
{
	int i;

9753
	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9754
	if (HAS_POWER_WELL(dev))
9755
		err_printf(m, "PWR_WELL_CTL2: %08x\n",
9756
			   error->power_well_driver);
9757
	for_each_pipe(i) {
9758 9759
		err_printf(m, "Pipe [%d]:\n", i);
		err_printf(m, "  CPU transcoder: %c\n",
9760
			   transcoder_name(error->pipe[i].cpu_transcoder));
9761 9762 9763 9764 9765 9766 9767 9768 9769 9770 9771 9772
		err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
		err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
		err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
		err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
		err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
		err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
		err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
		err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);

		err_printf(m, "Plane [%d]:\n", i);
		err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
		err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9773
		if (INTEL_INFO(dev)->gen <= 3) {
9774 9775
			err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
			err_printf(m, "  POS: %08x\n", error->plane[i].pos);
9776
		}
P
Paulo Zanoni 已提交
9777
		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9778
			err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9779
		if (INTEL_INFO(dev)->gen >= 4) {
9780 9781
			err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
			err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9782 9783
		}

9784 9785 9786 9787
		err_printf(m, "Cursor [%d]:\n", i);
		err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
		err_printf(m, "  POS: %08x\n", error->cursor[i].position);
		err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9788 9789 9790
	}
}
#endif