i915_drv.h 122.7 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include <drm/drm_cache.h>
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#include "i915_params.h"
#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_uc.h"
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#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_context.h"
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#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20170206"
#define DRIVER_TIMESTAMP	1486372993
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
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#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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#endif

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#undef WARN_ON_ONCE
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#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
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#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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typedef struct {
	uint32_t val;
} uint_fixed_16_16_t;

#define FP_16_16_MAX ({ \
	uint_fixed_16_16_t fp; \
	fp.val = UINT_MAX; \
	fp; \
})

static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
{
	uint_fixed_16_16_t fp;

	WARN_ON(val >> 16);

	fp.val = val << 16;
	return fp;
}

static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
{
	return DIV_ROUND_UP(fp.val, 1 << 16);
}

static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
{
	return fp.val >> 16;
}

static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
						 uint_fixed_16_16_t min2)
{
	uint_fixed_16_16_t min;

	min.val = min(min1.val, min2.val);
	return min;
}

static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
						 uint_fixed_16_16_t max2)
{
	uint_fixed_16_16_t max;

	max.val = max(max1.val, max2.val);
	return max;
}

static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
							  uint32_t d)
{
	uint_fixed_16_16_t fp, res;

	fp = u32_to_fixed_16_16(val);
	res.val = DIV_ROUND_UP(fp.val, d);
	return res;
}

static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
							      uint32_t d)
{
	uint_fixed_16_16_t res;
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
	WARN_ON(interm_val >> 32);
	res.val = (uint32_t) interm_val;

	return res;
}

static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
						     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;
	uint_fixed_16_16_t fp;

	intermediate_val = (uint64_t) val * mul.val;
	WARN_ON(intermediate_val >> 32);
	fp.val = (uint32_t) intermediate_val;
	return fp;
}

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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static inline const char *enableddisabled(bool v)
{
	return v ? "enabled" : "disabled";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * Global legacy plane identifier. Valid only for primary/sprite
 * planes on pre-g4x, and only for primary planes on g4x+.
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 */
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enum plane {
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	PLANE_A,
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	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
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/*
 * Per-pipe plane identifier.
 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
 *
 * This is expected to be passed to various register macros
 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 */
enum plane_id {
	PLANE_PRIMARY,
	PLANE_SPRITE0,
	PLANE_SPRITE1,
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	PLANE_SPRITE2,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
};

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#define for_each_plane_id_on_crtc(__crtc, __p) \
	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
		for_each_if ((__crtc)->plane_ids_mask & BIT(__p))

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enum port {
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	PORT_NONE = -1,
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	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
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	DPIO_PHY1,
	DPIO_PHY2,
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};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DDI_A_IO,
	POWER_DOMAIN_PORT_DDI_B_IO,
	POWER_DOMAIN_PORT_DDI_C_IO,
	POWER_DOMAIN_PORT_DDI_D_IO,
	POWER_DOMAIN_PORT_DDI_E_IO,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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#define HPD_STORM_DEFAULT_THRESHOLD 5

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	unsigned int hpd_storm_threshold;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_universal_plane(__dev_priv, __pipe, __p)		\
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	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
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			    &(dev)->mode_config.connector_list,	\
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			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if (BIT_ULL(domain) & (mask))
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#define for_each_power_well(__dev_priv, __power_well)				\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells <	\
		(__dev_priv)->power_domains.power_well_count;		\
	     (__power_well)++)

#define for_each_power_well_rev(__dev_priv, __power_well)			\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells +		\
			      (__dev_priv)->power_domains.power_well_count - 1;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;	\
	     (__power_well)--)

#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)	\
	for_each_power_well(__dev_priv, __power_well)				\
		for_each_if ((__power_well)->domains & (__domain_mask))

#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
	for_each_power_well_rev(__dev_priv, __power_well)		        \
		for_each_if ((__power_well)->domains & (__domain_mask))

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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	unsigned int bsd_engine;
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/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
	int context_bans;
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};

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

L
Linus Torvalds 已提交
579 580 581
/* Interface history:
 *
 * 1.1: Original.
D
Dave Airlie 已提交
582 583
 * 1.2: Add Power Management
 * 1.3: Add vblank support
584
 * 1.4: Fix cmdbuffer path, add heap destroy
585
 * 1.5: Add vblank pipe configuration
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
586 587
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
L
Linus Torvalds 已提交
588 589
 */
#define DRIVER_MAJOR		1
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
590
#define DRIVER_MINOR		6
L
Linus Torvalds 已提交
591 592
#define DRIVER_PATCHLEVEL	0

593 594 595 596 597
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

598
struct intel_opregion {
599 600 601
	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
J
Jani Nikula 已提交
602 603
	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
604
	struct opregion_asle *asle;
605
	void *rvda;
606
	const void *vbt;
607
	u32 vbt_size;
608
	u32 *lid_state;
609
	struct work_struct asle_work;
610
};
611
#define OPREGION_SIZE            (8*1024)
612

613 614 615
struct intel_overlay;
struct intel_overlay_error_state;

616
struct sdvo_device_mapping {
C
Chris Wilson 已提交
617
	u8 initialized;
618 619 620
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
C
Chris Wilson 已提交
621
	u8 i2c_pin;
622
	u8 ddc_pin;
623 624
};

625
struct intel_connector;
626
struct intel_encoder;
627
struct intel_atomic_state;
628
struct intel_crtc_state;
629
struct intel_initial_plane_config;
630
struct intel_crtc;
631 632
struct intel_limit;
struct dpll;
633
struct intel_cdclk_state;
634

635
struct drm_i915_display_funcs {
636 637
	void (*get_cdclk)(struct drm_i915_private *dev_priv,
			  struct intel_cdclk_state *cdclk_state);
638 639
	void (*set_cdclk)(struct drm_i915_private *dev_priv,
			  const struct intel_cdclk_state *cdclk_state);
640
	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
641
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
642 643 644
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
645 646 647 648 649 650
	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
651
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
652
	void (*update_wm)(struct intel_crtc *crtc);
653
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
654 655 656
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
657
				struct intel_crtc_state *);
658 659
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
660 661
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
662 663 664 665
	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
666 667
	void (*update_crtcs)(struct drm_atomic_state *state,
			     unsigned int *crtc_vblank_mask);
668 669
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
670
				   const struct drm_display_mode *adjusted_mode);
671
	void (*audio_codec_disable)(struct intel_encoder *encoder);
672
	void (*fdi_link_train)(struct drm_crtc *crtc);
673
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
674 675 676 677 678
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
679
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
680 681 682 683 684
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
685

686 687
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
688 689
};

690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

707 708 709
#define FW_REG_READ  (1)
#define FW_REG_WRITE (2)

710 711 712 713 714 715 716 717 718 719 720 721
enum decoupled_power_domain {
	GEN9_DECOUPLED_PD_BLITTER = 0,
	GEN9_DECOUPLED_PD_RENDER,
	GEN9_DECOUPLED_PD_MEDIA,
	GEN9_DECOUPLED_PD_ALL
};

enum decoupled_ops {
	GEN9_DECOUPLED_OP_WRITE = 0,
	GEN9_DECOUPLED_OP_READ
};

722 723 724 725
enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op);

726
struct intel_uncore_funcs {
727
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
728
							enum forcewake_domains domains);
729
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
730
							enum forcewake_domains domains);
731

732 733 734 735
	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
736

737
	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
738
				uint8_t val, bool trace);
739
	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
740
				uint16_t val, bool trace);
741
	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
742
				uint32_t val, bool trace);
743 744
};

745 746 747 748 749 750 751
struct intel_forcewake_range {
	u32 start;
	u32 end;

	enum forcewake_domains domains;
};

752 753 754
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

755 756 757
	const struct intel_forcewake_range *fw_domains_table;
	unsigned int fw_domains_table_entries;

758 759 760
	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
761

762
	enum forcewake_domains fw_domains;
763
	enum forcewake_domains fw_domains_active;
764 765 766

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
767
		enum forcewake_domain_id id;
768
		enum forcewake_domains mask;
769
		unsigned wake_count;
770
		struct hrtimer timer;
771
		i915_reg_t reg_set;
772 773
		u32 val_set;
		u32 val_clear;
774 775
		i915_reg_t reg_ack;
		i915_reg_t reg_post;
776
		u32 val_reset;
777
	} fw_domain[FW_DOMAIN_ID_COUNT];
778 779

	int unclaimed_mmio_check;
780 781 782
};

/* Iterate over initialised fw domains */
783 784 785 786 787 788 789 790
#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
	for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
	     (domain__)++) \
		for_each_if ((mask__) & (domain__)->mask)

#define for_each_fw_domain(domain__, dev_priv__) \
	for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
791

792 793 794 795
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

796
struct intel_csr {
797
	struct work_struct work;
798
	const char *fw_path;
799
	uint32_t *dmc_payload;
800
	uint32_t dmc_fw_size;
801
	uint32_t version;
802
	uint32_t mmio_count;
803
	i915_reg_t mmioaddr[8];
804
	uint32_t mmiodata[8];
805
	uint32_t dc_state;
806
	uint32_t allowed_dc_mask;
807 808
};

809 810
#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
811
	func(is_lp); \
812
	func(is_alpha_support); \
813
	/* Keep has_* in alphabetical order */ \
814
	func(has_64bit_reloc); \
815
	func(has_aliasing_ppgtt); \
816
	func(has_csr); \
817
	func(has_ddi); \
818
	func(has_decoupled_mmio); \
819
	func(has_dp_mst); \
820 821
	func(has_fbc); \
	func(has_fpga_dbg); \
822 823
	func(has_full_ppgtt); \
	func(has_full_48bit_ppgtt); \
824 825 826 827
	func(has_gmbus_irq); \
	func(has_gmch_display); \
	func(has_guc); \
	func(has_hotplug); \
828 829
	func(has_hw_contexts); \
	func(has_l3_dpf); \
830
	func(has_llc); \
831 832 833 834 835 836 837 838 839
	func(has_logical_ring_contexts); \
	func(has_overlay); \
	func(has_pipe_cxsr); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
840
	func(has_snoop); \
841 842 843
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
844
	func(supports_tv);
D
Daniel Vetter 已提交
845

846
struct sseu_dev_info {
847
	u8 slice_mask;
848
	u8 subslice_mask;
849 850
	u8 eu_total;
	u8 eu_per_subslice;
851 852 853 854 855 856
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
857 858
};

859 860 861 862 863
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

864 865 866 867 868 869 870 871 872 873 874 875 876
/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
877 878
	INTEL_I965G,
	INTEL_I965GM,
879 880
	INTEL_G45,
	INTEL_GM45,
881 882 883 884 885 886 887 888 889 890 891
	INTEL_IRONLAKE,
	INTEL_SANDYBRIDGE,
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
892
	INTEL_MAX_PLATFORMS
893 894
};

895
struct intel_device_info {
896
	u32 display_mmio_offset;
897
	u16 device_id;
898
	u8 num_pipes;
899
	u8 num_sprites[I915_MAX_PIPES];
900
	u8 num_scalers[I915_MAX_PIPES];
901
	u8 gen;
902
	u16 gen_mask;
903
	enum intel_platform platform;
904
	u8 ring_mask; /* Rings supported by the HW */
905
	u8 num_rings;
906 907 908
#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
909
	u16 ddb_size; /* in blocks */
910 911 912 913
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
914
	int cursor_offsets[I915_MAX_PIPES];
915 916

	/* Slice/subslice/EU info */
917
	struct sseu_dev_info sseu;
918 919 920 921 922

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
923 924
};

925 926
struct intel_display_error_state;

927
struct i915_gpu_state {
928 929
	struct kref ref;
	struct timeval time;
930 931
	struct timeval boottime;
	struct timeval uptime;
932

933 934
	struct drm_i915_private *i915;

935 936 937 938 939 940
	char error_msg[128];
	bool simulated;
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;
941
	struct i915_params params;
942 943 944 945 946

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
947
	u32 gtier[4], ngtier;
948 949 950 951 952 953 954 955 956 957 958 959
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
960

961
	u32 nfence;
962 963 964
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
965
	struct drm_i915_error_object *semaphore;
966
	struct drm_i915_error_object *guc_log;
967 968 969 970 971 972

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
973 974
		unsigned long hangcheck_timestamp;
		bool hangcheck_stalled;
975 976 977 978
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;

979 980 981
		/* position of active request inside the ring */
		u32 rq_head, rq_post, rq_tail;

982 983 984 985 986 987 988 989 990 991 992
		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
993
		u32 mode;
994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
1007
		struct intel_instdone instdone;
1008

1009 1010 1011 1012 1013 1014 1015 1016 1017 1018
		struct drm_i915_error_context {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 handle;
			u32 hw_id;
			int ban_score;
			int active;
			int guilty;
		} context;

1019 1020
		struct drm_i915_error_object {
			u64 gtt_offset;
1021
			u64 gtt_size;
1022 1023
			int page_count;
			int unused;
1024 1025 1026 1027 1028 1029 1030
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
1031
			pid_t pid;
1032
			u32 context;
1033
			int ban_score;
1034 1035 1036
			u32 seqno;
			u32 head;
			u32 tail;
1037
		} *requests, execlist[2];
1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

1073 1074
enum i915_cache_level {
	I915_CACHE_NONE = 0,
1075 1076 1077 1078 1079
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
1080
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1081 1082
};

1083 1084
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

1085 1086 1087 1088 1089
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
1090
	ORIGIN_DIRTYFB,
1091 1092
};

1093
struct intel_fbc {
P
Paulo Zanoni 已提交
1094 1095 1096
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
1097
	unsigned threshold;
1098 1099
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
1100
	unsigned int visible_pipes_mask;
1101
	struct intel_crtc *crtc;
1102

1103
	struct drm_mm_node compressed_fb;
1104 1105
	struct drm_mm_node *compressed_llb;

1106 1107
	bool false_color;

1108
	bool enabled;
1109
	bool active;
1110

1111 1112 1113
	bool underrun_detected;
	struct work_struct underrun_work;

1114
	struct intel_fbc_state_cache {
1115 1116
		struct i915_vma *vma;

1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
1130
			const struct drm_format_info *format;
1131 1132 1133 1134
			unsigned int stride;
		} fb;
	} state_cache;

1135
	struct intel_fbc_reg_params {
1136 1137
		struct i915_vma *vma;

1138 1139 1140 1141 1142 1143 1144
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
1145
			const struct drm_format_info *format;
1146 1147 1148 1149 1150 1151
			unsigned int stride;
		} fb;

		int cfb_size;
	} params;

1152
	struct intel_fbc_work {
1153
		bool scheduled;
1154
		u32 scheduled_vblank;
1155 1156
		struct work_struct work;
	} work;
1157

1158
	const char *no_fbc_reason;
1159 1160
};

1161
/*
1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1176 1177
};

1178
struct intel_dp;
1179 1180 1181 1182 1183 1184 1185 1186 1187
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

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Rodrigo Vivi 已提交
1188
struct i915_psr {
1189
	struct mutex lock;
R
Rodrigo Vivi 已提交
1190 1191
	bool sink_support;
	bool source_ok;
1192
	struct intel_dp *enabled;
1193 1194
	bool active;
	struct delayed_work work;
1195
	unsigned busy_frontbuffer_bits;
1196 1197
	bool psr2_support;
	bool aux_frame_sync;
1198
	bool link_standby;
1199 1200
	bool y_cord_support;
	bool colorimetry_support;
1201
	bool alpm;
1202
};
1203

1204
enum intel_pch {
1205
	PCH_NONE = 0,	/* No PCH present */
1206 1207
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1208
	PCH_LPT,	/* Lynxpoint PCH */
1209
	PCH_SPT,        /* Sunrisepoint PCH */
1210
	PCH_KBP,        /* Kabypoint PCH */
B
Ben Widawsky 已提交
1211
	PCH_NOP,
1212 1213
};

1214 1215 1216 1217 1218
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1219
#define QUIRK_PIPEA_FORCE (1<<0)
1220
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1221
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1222
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1223
#define QUIRK_PIPEB_FORCE (1<<4)
1224
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1225

1226
struct intel_fbdev;
1227
struct intel_fbc_work;
1228

1229 1230
struct intel_gmbus {
	struct i2c_adapter adapter;
1231
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1232
	u32 force_bit;
1233
	u32 reg0;
1234
	i915_reg_t gpio_reg;
1235
	struct i2c_algo_bit_data bit_algo;
1236 1237 1238
	struct drm_i915_private *dev_priv;
};

1239
struct i915_suspend_saved_registers {
1240
	u32 saveDSPARB;
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Jesse Barnes 已提交
1241
	u32 saveFBC_CONTROL;
1242 1243
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
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Jesse Barnes 已提交
1244 1245
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1246
	u32 saveSWF3[3];
1247
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1248
	u32 savePCH_PORT_HOTPLUG;
1249
	u16 saveGCDGMBUS;
1250
};
1251

1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1310
	u32 pcbr;
1311 1312 1313
	u32 clock_gate_dis2;
};

1314 1315 1316 1317
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1318 1319
};

1320
struct intel_gen6_power_mgmt {
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Imre Deak 已提交
1321 1322 1323 1324
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1325
	struct work_struct work;
I
Imre Deak 已提交
1326
	bool interrupts_enabled;
1327
	u32 pm_iir;
1328

1329
	/* PM interrupt bits that should never be masked */
1330 1331
	u32 pm_intr_keep;

1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1347
	u8 boost_freq;		/* Frequency to request when wait boosting */
1348
	u8 idle_freq;		/* Frequency to request when we are idle */
1349 1350 1351
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1352
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1353

1354 1355 1356
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1357 1358 1359
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1360 1361 1362 1363
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1364
	bool enabled;
1365
	struct delayed_work autoenable_work;
1366
	unsigned boosts;
1367

1368 1369 1370
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1371 1372
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1373 1374 1375
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1376 1377
	 */
	struct mutex hw_lock;
1378 1379
};

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Daniel Vetter 已提交
1380 1381 1382
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1394
	u64 last_time2;
1395 1396 1397 1398 1399 1400 1401
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1432 1433
/* Power well structure for haswell */
struct i915_power_well {
1434
	const char *name;
1435
	bool always_on;
1436 1437
	/* power well enable/disable usage count */
	int count;
1438 1439
	/* cached hw enabled state */
	bool hw_enabled;
1440
	u64 domains;
1441 1442
	/* unique identifier for this power well */
	unsigned long id;
1443 1444 1445 1446 1447
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
	unsigned long data;
1448
	const struct i915_power_well_ops *ops;
1449 1450
};

1451
struct i915_power_domains {
1452 1453 1454 1455 1456
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1457
	bool initializing;
1458
	int power_well_count;
1459

1460
	struct mutex lock;
1461
	int domain_use_count[POWER_DOMAIN_NUM];
1462
	struct i915_power_well *power_wells;
1463 1464
};

1465
#define MAX_L3_SLICES 2
1466
struct intel_l3_parity {
1467
	u32 *remap_info[MAX_L3_SLICES];
1468
	struct work_struct error_work;
1469
	int which_slice;
1470 1471
};

1472 1473 1474
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1475 1476 1477 1478
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1479 1480 1481 1482 1483
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
1484 1485
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
1486 1487 1488
	 */
	struct list_head unbound_list;

1489 1490 1491 1492 1493
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

1494 1495 1496 1497 1498 1499
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;

1500
	/** Usable portion of the GTT for GEM */
1501
	dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1502 1503 1504 1505

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1506
	struct notifier_block oom_notifier;
1507
	struct notifier_block vmap_notifier;
1508
	struct shrinker shrinker;
1509 1510 1511 1512 1513 1514 1515 1516 1517 1518

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1519
	/* the indicator for dispatch video commands on two BSD rings */
1520
	atomic_t bsd_engine_dispatch_index;
1521

1522 1523 1524 1525 1526 1527
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1528
	spinlock_t object_stat_lock;
1529
	u64 object_memory;
1530 1531 1532
	u32 object_count;
};

1533
struct drm_i915_error_state_buf {
1534
	struct drm_i915_private *i915;
1535 1536 1537 1538 1539 1540 1541 1542
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1543 1544 1545
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

1546 1547 1548
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

1549 1550 1551 1552
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1553

1554
	struct delayed_work hangcheck_work;
1555 1556 1557 1558

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
1559
	struct i915_gpu_state *first_error;
1560 1561 1562

	unsigned long missed_irq_rings;

1563
	/**
M
Mika Kuoppala 已提交
1564
	 * State variable controlling the reset flow and count
1565
	 *
M
Mika Kuoppala 已提交
1566
	 * This is a counter which gets incremented when reset is triggered,
1567 1568 1569 1570
	 *
	 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
M
Mika Kuoppala 已提交
1571 1572 1573 1574 1575 1576 1577 1578 1579
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1580 1581 1582 1583
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1584
	 */
1585
	unsigned long reset_count;
1586

1587 1588 1589
	unsigned long flags;
#define I915_RESET_IN_PROGRESS	0
#define I915_WEDGED		(BITS_PER_LONG - 1)
1590

1591 1592 1593 1594 1595 1596
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1597 1598 1599 1600 1601
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1602

1603
	/* For missed irq/seqno simulation. */
1604
	unsigned long test_irq_rings;
1605 1606
};

1607 1608 1609 1610 1611 1612
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1613 1614 1615 1616 1617
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1618 1619 1620 1621
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1622
struct ddi_vbt_port_info {
1623 1624 1625 1626 1627 1628
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1629
	uint8_t hdmi_level_shift;
1630 1631 1632 1633

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1634
	uint8_t supports_edp:1;
1635 1636

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1637
	uint8_t alternate_ddc_pin;
1638 1639 1640

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1641 1642
};

R
Rodrigo Vivi 已提交
1643 1644 1645 1646 1647
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1648 1649
};

1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1662
	unsigned int panel_type:4;
1663 1664 1665
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1666 1667
	enum drrs_support_type drrs_type;

1668 1669 1670 1671 1672
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1673
		bool low_vswing;
1674 1675 1676 1677 1678
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1679

R
Rodrigo Vivi 已提交
1680 1681 1682 1683 1684 1685 1686 1687 1688
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1689 1690
	struct {
		u16 pwm_freq_hz;
1691
		bool present;
1692
		bool active_low_pwm;
1693
		u8 min_brightness;	/* min_brightness/255 of max */
1694
		u8 controller;		/* brightness controller number */
1695
		enum intel_backlight_type type;
1696 1697
	} backlight;

1698 1699 1700
	/* MIPI DSI */
	struct {
		u16 panel_id;
1701 1702 1703 1704 1705
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1706
		const u8 *sequence[MIPI_SEQ_MAX];
1707 1708
	} dsi;

1709 1710 1711
	int crt_ddc_pin;

	int child_dev_num;
1712
	union child_device_config *child_dev;
1713 1714

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1715
	struct sdvo_device_mapping sdvo_mappings[2];
1716 1717
};

1718 1719 1720 1721 1722
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1723 1724 1725 1726 1727 1728 1729 1730
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1731
struct ilk_wm_values {
1732 1733 1734 1735 1736 1737 1738 1739
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1740
struct vlv_pipe_wm {
1741
	uint16_t plane[I915_MAX_PLANES];
1742
};
1743

1744 1745
struct vlv_sr_wm {
	uint16_t plane;
1746 1747 1748 1749 1750
	uint16_t cursor;
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1751
};
1752

1753 1754 1755
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1756
	struct vlv_wm_ddl_values ddl[3];
1757 1758
	uint8_t level;
	bool cxsr;
1759 1760
};

1761
struct skl_ddb_entry {
1762
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1763 1764 1765 1766
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1767
	return entry->end - entry->start;
1768 1769
}

1770 1771 1772 1773 1774 1775 1776 1777 1778
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1779
struct skl_ddb_allocation {
1780
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1781
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1782 1783
};

1784
struct skl_wm_values {
1785
	unsigned dirty_pipes;
1786
	struct skl_ddb_allocation ddb;
1787 1788 1789
};

struct skl_wm_level {
L
Lyude 已提交
1790 1791 1792
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1793 1794
};

1795
/*
1796 1797 1798 1799
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1800
 *
1801 1802 1803
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1804
 *
1805 1806
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1807
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1808
 * it can be changed with the standard runtime PM files from sysfs.
1809 1810 1811 1812 1813
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1814
 * case it happens.
1815
 *
1816
 * For more, read the Documentation/power/runtime_pm.txt.
1817
 */
1818
struct i915_runtime_pm {
1819
	atomic_t wakeref_count;
1820
	bool suspended;
1821
	bool irqs_enabled;
1822 1823
};

1824 1825 1826 1827 1828
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1829
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1830 1831 1832 1833 1834
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1835
	INTEL_PIPE_CRC_SOURCE_AUTO,
1836 1837 1838
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1839
struct intel_pipe_crc_entry {
1840
	uint32_t frame;
1841 1842 1843
	uint32_t crc[5];
};

1844
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1845
struct intel_pipe_crc {
1846 1847
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1848
	struct intel_pipe_crc_entry *entries;
1849
	enum intel_pipe_crc_source source;
1850
	int head, tail;
1851
	wait_queue_head_t wq;
T
Tomeu Vizoso 已提交
1852
	int skipped;
1853 1854
};

1855
struct i915_frontbuffer_tracking {
1856
	spinlock_t lock;
1857 1858 1859 1860 1861 1862 1863 1864 1865

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1866
struct i915_wa_reg {
1867
	i915_reg_t addr;
1868 1869 1870 1871 1872
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1873 1874 1875 1876 1877 1878 1879
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1880 1881 1882 1883

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1884
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1885 1886
};

1887 1888 1889 1890
struct i915_virtual_gpu {
	bool active;
};

1891 1892 1893 1894 1895 1896 1897
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1898 1899 1900 1901 1902
struct i915_oa_format {
	u32 format;
	int size;
};

1903 1904 1905 1906 1907
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1908 1909
struct i915_perf_stream;

1910 1911 1912
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
1913
struct i915_perf_stream_ops {
1914 1915 1916 1917
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
1918 1919 1920
	 */
	void (*enable)(struct i915_perf_stream *stream);

1921 1922 1923 1924
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
1925 1926 1927
	 */
	void (*disable)(struct i915_perf_stream *stream);

1928 1929
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1930 1931 1932 1933 1934 1935
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

1936 1937 1938
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
1939
	 * wait queue that would be passed to poll_wait().
1940 1941 1942
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

1943 1944 1945 1946 1947 1948 1949
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
1950
	 *
1951 1952
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
1953
	 *
1954 1955
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
1956
	 *
1957 1958 1959
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
1960 1961 1962 1963 1964 1965
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

1966 1967
	/**
	 * @destroy: Cleanup any stream specific resources.
1968 1969 1970 1971 1972 1973
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

1974 1975 1976
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
1977
struct i915_perf_stream {
1978 1979 1980
	/**
	 * @dev_priv: i915 drm device
	 */
1981 1982
	struct drm_i915_private *dev_priv;

1983 1984 1985
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
1986 1987
	struct list_head link;

1988 1989 1990 1991 1992
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
1993
	u32 sample_flags;
1994 1995 1996 1997 1998 1999

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
2000
	int sample_size;
2001

2002 2003 2004 2005
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
2006
	struct i915_gem_context *ctx;
2007 2008 2009 2010 2011 2012

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
2013 2014
	bool enabled;

2015 2016 2017 2018
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
2019 2020 2021
	const struct i915_perf_stream_ops *ops;
};

2022 2023 2024
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
2025
struct i915_oa_ops {
2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040
	/**
	 * @init_oa_buffer: Resets the head and tail pointers of the
	 * circular buffer for periodic OA reports.
	 *
	 * Called when first opening a stream for OA metrics, but also may be
	 * called in response to an OA buffer overflow or other error
	 * condition.
	 *
	 * Note it may be necessary to clear the full OA buffer here as part of
	 * maintaining the invariable that new reports must be written to
	 * zeroed memory for us to be able to reliable detect if an expected
	 * report has not yet landed in memory.  (At least on Haswell the OA
	 * buffer tail pointer is not synchronized with reports being visible
	 * to the CPU)
	 */
2041
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2042 2043 2044 2045 2046 2047 2048

	/**
	 * @enable_metric_set: Applies any MUX configuration to set up the
	 * Boolean and Custom (B/C) counters that are part of the counter
	 * reports being sampled. May apply system constraints such as
	 * disabling EU clock gating as required.
	 */
2049
	int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2050 2051 2052 2053 2054

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
2055
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2056 2057 2058 2059

	/**
	 * @oa_enable: Enable periodic sampling
	 */
2060
	void (*oa_enable)(struct drm_i915_private *dev_priv);
2061 2062 2063 2064

	/**
	 * @oa_disable: Disable periodic sampling
	 */
2065
	void (*oa_disable)(struct drm_i915_private *dev_priv);
2066 2067 2068 2069 2070

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
2071 2072 2073 2074
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089

	/**
	 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
	 *
	 * This is either called via fops or the poll check hrtimer (atomic
	 * ctx) without any locks taken.
	 *
	 * It's safe to read OA config state here unlocked, assuming that this
	 * is only called while the stream is enabled, while the global OA
	 * configuration can't be modified.
	 *
	 * Efficiency is more important than avoiding some false positives
	 * here, which will be handled gracefully - likely resulting in an
	 * %EAGAIN error for userspace.
	 */
2090
	bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2091 2092
};

2093 2094 2095 2096
struct intel_cdclk_state {
	unsigned int cdclk, vco, ref;
};

2097
struct drm_i915_private {
2098 2099
	struct drm_device drm;

2100
	struct kmem_cache *objects;
2101
	struct kmem_cache *vmas;
2102
	struct kmem_cache *requests;
2103
	struct kmem_cache *dependencies;
2104

2105
	const struct intel_device_info info;
2106 2107 2108

	void __iomem *regs;

2109
	struct intel_uncore uncore;
2110

2111 2112
	struct i915_virtual_gpu vgpu;

2113
	struct intel_gvt *gvt;
2114

2115
	struct intel_huc huc;
2116 2117
	struct intel_guc guc;

2118 2119
	struct intel_csr csr;

2120
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2121

2122 2123 2124 2125 2126 2127 2128 2129 2130
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

2131 2132 2133
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

2134 2135
	uint32_t psr_mmio_base;

2136 2137
	uint32_t pps_mmio_base;

2138 2139
	wait_queue_head_t gmbus_wait_queue;

2140
	struct pci_dev *bridge_dev;
2141
	struct i915_gem_context *kernel_context;
2142
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
2143
	struct i915_vma *semaphore;
2144

2145
	struct drm_dma_handle *status_page_dmah;
2146 2147 2148 2149 2150
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

2151 2152 2153
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

2154 2155
	bool display_irqs_enabled;

2156 2157 2158
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
2159 2160
	/* Sideband mailbox protection */
	struct mutex sb_lock;
2161 2162

	/** Cached value of IMR to avoid reads in updating the bitfield */
2163 2164 2165 2166
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
2167
	u32 gt_irq_mask;
2168 2169
	u32 pm_imr;
	u32 pm_ier;
2170
	u32 pm_rps_events;
2171
	u32 pm_guc_events;
2172
	u32 pipestat_irq_mask[I915_MAX_PIPES];
2173

2174
	struct i915_hotplug hotplug;
2175
	struct intel_fbc fbc;
2176
	struct i915_drrs drrs;
2177
	struct intel_opregion opregion;
2178
	struct intel_vbt_data vbt;
2179

2180 2181
	bool preserve_bios_swizzle;

2182 2183 2184
	/* overlay */
	struct intel_overlay *overlay;

2185
	/* backlight registers and fields in struct intel_panel */
2186
	struct mutex backlight_lock;
2187

2188 2189 2190
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
2191 2192 2193
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

2194 2195 2196 2197
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
2198
	unsigned int skl_preferred_vco_freq;
2199
	unsigned int max_cdclk_freq;
2200

M
Mika Kahola 已提交
2201
	unsigned int max_dotclk_freq;
2202
	unsigned int rawclk_freq;
2203
	unsigned int hpll_freq;
2204
	unsigned int czclk_freq;
2205

2206
	struct {
2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220
		/*
		 * The current logical cdclk state.
		 * See intel_atomic_state.cdclk.logical
		 *
		 * For reading holding any crtc lock is sufficient,
		 * for writing must hold all of them.
		 */
		struct intel_cdclk_state logical;
		/*
		 * The current actual cdclk state.
		 * See intel_atomic_state.cdclk.actual
		 */
		struct intel_cdclk_state actual;
		/* The current hardware cdclk state */
2221 2222
		struct intel_cdclk_state hw;
	} cdclk;
2223

2224 2225 2226 2227 2228 2229 2230
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
2231 2232 2233 2234 2235 2236 2237
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
2238
	unsigned short pch_id;
2239 2240 2241

	unsigned long quirks;

2242 2243
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
2244
	struct drm_atomic_state *modeset_restore_state;
2245
	struct drm_modeset_acquire_ctx reset_ctx;
2246

2247
	struct list_head vm_list; /* Global list of all address spaces */
2248
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
2249

2250
	struct i915_gem_mm mm;
2251 2252
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
2253

2254 2255 2256 2257 2258 2259 2260
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

2261 2262
	/* Kernel Modesetting */

2263 2264
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2265 2266
	wait_queue_head_t pending_flip_queue;

2267 2268 2269 2270
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

2271
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
2272 2273
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2274
	const struct intel_dpll_mgr *dpll_mgr;
2275

2276 2277 2278 2279 2280 2281 2282
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

2283 2284 2285
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

2286
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2287

2288
	struct i915_workarounds workarounds;
2289

2290 2291
	struct i915_frontbuffer_tracking fb_tracking;

2292 2293 2294 2295 2296
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

2297
	u16 orig_clock;
2298

2299
	bool mchbar_need_disable;
2300

2301 2302
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
2303
	/* Cannot be determined by PCIID. You must always read a register. */
2304
	u32 edram_cap;
B
Ben Widawsky 已提交
2305

2306
	/* gen6+ rps state */
2307
	struct intel_gen6_power_mgmt rps;
2308

2309 2310
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
2311
	struct intel_ilk_power_mgmt ips;
2312

2313
	struct i915_power_domains power_domains;
2314

R
Rodrigo Vivi 已提交
2315
	struct i915_psr psr;
2316

2317
	struct i915_gpu_error gpu_error;
2318

2319 2320
	struct drm_i915_gem_object *vlv_pctx;

2321
#ifdef CONFIG_DRM_FBDEV_EMULATION
2322 2323
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
2324
	struct work_struct fbdev_suspend_work;
2325
#endif
2326 2327

	struct drm_property *broadcast_rgb_property;
2328
	struct drm_property *force_audio_property;
2329

I
Imre Deak 已提交
2330
	/* hda/i915 audio component */
2331
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
2332
	bool audio_component_registered;
2333 2334 2335 2336 2337
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
2338

2339
	uint32_t hw_context_size;
2340
	struct list_head context_list;
2341

2342
	u32 fdi_rx_config;
2343

2344
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2345
	u32 chv_phy_control;
2346 2347 2348 2349 2350 2351
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
2352
	u32 bxt_phy_grc;
2353

2354
	u32 suspend_count;
2355
	bool suspended_to_idle;
2356
	struct i915_suspend_saved_registers regfile;
2357
	struct vlv_s0ix_state vlv_s0ix_state;
2358

2359
	enum {
2360 2361 2362 2363 2364
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
2365

2366
	struct {
2367 2368 2369
		/* protects DSPARB registers on pre-g4x/vlv/chv */
		spinlock_t dsparb_lock;

2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2381 2382 2383 2384 2385 2386
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2387 2388

		/* current hardware state */
2389 2390 2391
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2392
			struct vlv_wm_values vlv;
2393
		};
2394 2395

		uint8_t max_level;
2396 2397 2398 2399 2400 2401 2402

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2403 2404 2405 2406 2407 2408 2409

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2410 2411
	} wm;

2412 2413
	struct i915_runtime_pm pm;

2414 2415
	struct {
		bool initialized;
2416

2417
		struct kobject *metrics_kobj;
2418
		struct ctl_table_header *sysctl_header;
2419

2420 2421
		struct mutex lock;
		struct list_head streams;
2422

2423 2424
		spinlock_t hook_lock;

2425
		struct {
2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

			bool periodic;
			int period_exponent;
			int timestamp_frequency;

			int tail_margin;

			int metrics_set;
2441 2442 2443 2444 2445

			const struct i915_oa_reg *mux_regs;
			int mux_regs_len;
			const struct i915_oa_reg *b_counter_regs;
			int b_counter_regs_len;
2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
				int format;
				int format_size;
			} oa_buffer;

			u32 gen7_latched_oastatus1;

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
			int n_builtin_sets;
2459
		} oa;
2460 2461
	} perf;

2462 2463
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2464
		void (*resume)(struct drm_i915_private *);
2465
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2466

2467 2468
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2469
		u32 active_requests;
2470

2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2497 2498

		ktime_t last_init_time;
2499 2500
	} gt;

2501 2502 2503
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2504 2505
	bool ipc_enabled;

2506 2507
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2508

2509 2510 2511 2512
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2513
};
L
Linus Torvalds 已提交
2514

2515 2516
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2517
	return container_of(dev, struct drm_i915_private, drm);
2518 2519
}

2520
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2521
{
2522
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2523 2524
}

2525 2526 2527 2528 2529
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

2530
/* Simple iterator over all initialised engines */
2531 2532 2533 2534 2535
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2536

2537 2538 2539 2540 2541 2542
#define __mask_next_bit(mask) ({					\
	int __idx = ffs(mask) - 1;					\
	mask &= ~BIT(__idx);						\
	__idx;								\
})

2543
/* Iterator over subset of engines selected by mask */
2544 2545
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
2546
	     tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2547

2548 2549 2550 2551 2552 2553 2554
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2555
#define I915_GTT_OFFSET_NONE ((u32)-1)
2556

2557 2558
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2559
 * considered to be the frontbuffer for the given plane interface-wise. This
2560 2561 2562 2563 2564
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2565 2566
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2567 2568 2569
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2570 2571 2572
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2573
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2574
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2575
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2576
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2577

2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2604 2605 2606 2607 2608 2609 2610 2611
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2626
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2627 2628
}

2629 2630 2631 2632 2633 2634 2635 2636 2637 2638
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2639
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2652
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2653

2654 2655 2656 2657 2658 2659 2660
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2661

2662
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2663
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2664

2665
#define REVID_FOREVER		0xff
2666
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2667 2668 2669 2670 2671 2672 2673

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2674
#define IS_GEN(dev_priv, s, e) ({ \
2675 2676 2677 2678 2679 2680 2681 2682 2683
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
2684
	!!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2685 2686
})

2687 2688 2689 2690 2691 2692 2693 2694
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2695 2696
#define IS_I830(dev_priv)	((dev_priv)->info.platform == INTEL_I830)
#define IS_I845G(dev_priv)	((dev_priv)->info.platform == INTEL_I845G)
2697
#define IS_I85X(dev_priv)	((dev_priv)->info.platform == INTEL_I85X)
2698
#define IS_I865G(dev_priv)	((dev_priv)->info.platform == INTEL_I865G)
2699
#define IS_I915G(dev_priv)	((dev_priv)->info.platform == INTEL_I915G)
2700 2701
#define IS_I915GM(dev_priv)	((dev_priv)->info.platform == INTEL_I915GM)
#define IS_I945G(dev_priv)	((dev_priv)->info.platform == INTEL_I945G)
2702
#define IS_I945GM(dev_priv)	((dev_priv)->info.platform == INTEL_I945GM)
2703 2704
#define IS_I965G(dev_priv)	((dev_priv)->info.platform == INTEL_I965G)
#define IS_I965GM(dev_priv)	((dev_priv)->info.platform == INTEL_I965GM)
2705 2706 2707
#define IS_G45(dev_priv)	((dev_priv)->info.platform == INTEL_G45)
#define IS_GM45(dev_priv)	((dev_priv)->info.platform == INTEL_GM45)
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2708 2709
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
2710
#define IS_PINEVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_PINEVIEW)
2711
#define IS_G33(dev_priv)	((dev_priv)->info.platform == INTEL_G33)
2712
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
2713
#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2714 2715 2716
#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
				 INTEL_DEVID(dev_priv) == 0x0152 || \
				 INTEL_DEVID(dev_priv) == 0x015a)
2717 2718 2719 2720 2721 2722 2723 2724
#define IS_VALLEYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	((dev_priv)->info.platform == INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	((dev_priv)->info.platform == INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
2725
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2726 2727 2728 2729 2730 2731
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2732
/* ULX machines are also considered ULT. */
2733 2734 2735 2736 2737 2738 2739 2740
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2741
/* ULX machines are also considered ULT. */
2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2764

2765
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2766

2767 2768 2769 2770 2771 2772
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2773 2774
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2775

2776 2777
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2778
#define BXT_REVID_A0		0x0
2779
#define BXT_REVID_A1		0x1
2780
#define BXT_REVID_B0		0x3
2781
#define BXT_REVID_B_LAST	0x8
2782
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2783

2784 2785
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2786

M
Mika Kuoppala 已提交
2787 2788
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2789 2790 2791
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2792

2793 2794
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2795

2796 2797 2798 2799 2800 2801
#define GLK_REVID_A0		0x0
#define GLK_REVID_A1		0x1

#define IS_GLK_REVID(dev_priv, since, until) \
	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

2802 2803 2804 2805 2806 2807
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2808 2809 2810 2811 2812 2813 2814 2815
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2816

2817
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
2818 2819
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2820

2821 2822 2823 2824 2825 2826 2827 2828 2829
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2830
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2831 2832 2833 2834 2835 2836

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2837 2838 2839
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2840 2841
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2842

2843
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2844

2845 2846 2847 2848 2849 2850 2851 2852 2853 2854
#define HAS_HW_CONTEXTS(dev_priv)	    ((dev_priv)->info.has_hw_contexts)
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2855

2856
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2857
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2858 2859

/* WaRsDisableCoarsePowerGating:skl,bxt */
2860
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2861
	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2862

2863 2864 2865 2866 2867 2868
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
2869 2870
#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2871

2872 2873 2874
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2875 2876 2877
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2878 2879
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2880

2881 2882 2883
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2884

2885
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2886

2887
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2888

2889 2890 2891 2892 2893
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
P
Paulo Zanoni 已提交
2894

2895
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2896

2897
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2898 2899
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2900 2901 2902 2903 2904
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2905 2906 2907
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2908
#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
2909

2910
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2911

2912
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2913

2914 2915 2916 2917 2918 2919
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2920 2921
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2922
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2923
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2924
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2925
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2926

2927 2928 2929 2930
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2931 2932 2933 2934
#define HAS_PCH_LPT_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2935 2936 2937 2938
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2939

2940
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2941

2942 2943
#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))

2944
/* DPF == dynamic parity feature */
2945
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2946 2947
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
2948

2949
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2950
#define GEN9_FREQ_SCALER 3
2951

2952 2953
#define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)

2954 2955
#include "i915_trace.h"

2956 2957 2958 2959 2960 2961 2962 2963 2964
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

2965
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2966
				int enable_ppgtt);
2967

2968 2969
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

2970
/* i915_drv.c */
2971 2972 2973 2974 2975 2976 2977
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2978
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2979 2980
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2981 2982
#else
#define i915_compat_ioctl NULL
2983
#endif
2984 2985 2986 2987 2988
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
2989 2990
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2991
extern void i915_reset(struct drm_i915_private *dev_priv);
2992
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2993
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2994
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2995 2996 2997 2998
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2999
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3000

3001 3002 3003
int intel_engines_init_early(struct drm_i915_private *dev_priv);
int intel_engines_init(struct drm_i915_private *dev_priv);

3004
/* intel_hotplug.c */
3005 3006
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
3007 3008 3009
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3010
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3011 3012
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3013

L
Linus Torvalds 已提交
3014
/* i915_irq.c */
3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

3032
__printf(3, 4)
3033 3034
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
3035
		       const char *fmt, ...);
L
Linus Torvalds 已提交
3036

3037
extern void intel_irq_init(struct drm_i915_private *dev_priv);
3038 3039
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3040

3041 3042
extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
3043
					bool restore_forcewake);
3044
extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3045
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3046
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3047 3048 3049
extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
					 bool restore);
3050
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3051
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3052
				enum forcewake_domains domains);
3053
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3054
				enum forcewake_domains domains);
3055 3056 3057 3058 3059 3060 3061
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
3062 3063
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

3064
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3065

3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076
int intel_wait_for_register(struct drm_i915_private *dev_priv,
			    i915_reg_t reg,
			    const u32 mask,
			    const u32 value,
			    const unsigned long timeout_ms);
int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
			       i915_reg_t reg,
			       const u32 mask,
			       const u32 value,
			       const unsigned long timeout_ms);

3077 3078
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
3079
	return dev_priv->gvt;
3080 3081
}

3082
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3083
{
3084
	return dev_priv->vgpu.active;
3085
}
3086

3087
void
3088
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3089
		     u32 status_mask);
3090 3091

void
3092
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3093
		      u32 status_mask);
3094

3095 3096
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3097 3098 3099
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
3127 3128 3129
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

3141 3142 3143 3144 3145 3146 3147 3148 3149
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3150 3151
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3152 3153 3154 3155 3156 3157
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3158 3159
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3160 3161
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3162 3163 3164 3165
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3166 3167
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3168 3169
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3170 3171 3172 3173
int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
3174
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3175 3176
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3177 3178
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3179 3180
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3181
void i915_gem_sanitize(struct drm_i915_private *i915);
3182 3183
int i915_gem_load_init(struct drm_i915_private *dev_priv);
void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3184
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3185
int i915_gem_freeze(struct drm_i915_private *dev_priv);
3186 3187
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3188
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3189
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3190 3191
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3192 3193 3194 3195 3196
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
3197
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3198
void i915_gem_free_object(struct drm_gem_object *obj);
3199

3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
	/* A single pass should suffice to release all the freed objects (along
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
	do {
		rcu_barrier();
	} while (flush_work(&i915->mm.free_work));
}

C
Chris Wilson 已提交
3213
struct i915_vma * __must_check
3214 3215
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3216
			 u64 size,
3217 3218
			 u64 alignment,
			 u64 flags);
3219

3220
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3221
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3222

3223 3224
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
3225
static inline int __sg_page_count(const struct scatterlist *sg)
3226
{
3227 3228
	return sg->length >> PAGE_SHIFT;
}
3229

3230 3231 3232
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
3233

3234 3235 3236
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
3237

3238 3239 3240
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
3241

3242 3243 3244
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
3245

3246 3247
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
				 struct sg_table *pages);
C
Chris Wilson 已提交
3248 3249 3250 3251 3252
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
3253
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
3254

3255
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
3256 3257 3258 3259 3260 3261 3262
		return 0;

	return __i915_gem_object_get_pages(obj);
}

static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3263
{
C
Chris Wilson 已提交
3264 3265
	GEM_BUG_ON(!obj->mm.pages);

3266
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3267 3268 3269 3270 3271
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3272
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3273 3274 3275 3276 3277 3278 3279 3280
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
	GEM_BUG_ON(!obj->mm.pages);

3281
	atomic_dec(&obj->mm.pages_pin_count);
3282
}
3283

3284 3285
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3286
{
C
Chris Wilson 已提交
3287
	__i915_gem_object_unpin_pages(obj);
3288 3289
}

3290 3291 3292 3293 3294 3295 3296
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3297
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3298

3299 3300 3301 3302 3303
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
};

3304 3305
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3306 3307
 * @obj: the object to map into kernel address space
 * @type: the type of mapping, used to select pgprot_t
3308 3309 3310
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3311 3312
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3313
 *
3314 3315
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3316
 *
3317 3318
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3319
 */
3320 3321
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3322 3323 3324

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
3325
 * @obj: the object to unmap
3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
#define CLFLUSH_BEFORE 0x1
#define CLFLUSH_AFTER 0x2
#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3351
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3352
void i915_vma_move_to_active(struct i915_vma *vma,
3353 3354
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3355 3356 3357
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3358 3359
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3360
int i915_gem_mmap_gtt_version(void);
3361 3362 3363 3364 3365

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3366
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3367

3368
struct drm_i915_gem_request *
3369
i915_gem_find_active_request(struct intel_engine_cs *engine);
3370

3371
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3372

3373 3374
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
3375
	return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3376 3377
}

3378
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3379
{
3380
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3381 3382
}

3383
static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3384
{
3385
	return i915_reset_in_progress(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3386 3387 3388 3389
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3390
	return READ_ONCE(error->reset_count);
3391
}
3392

3393
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3394
void i915_gem_reset(struct drm_i915_private *dev_priv);
3395
void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3396
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3397

3398
void i915_gem_init_mmio(struct drm_i915_private *i915);
3399 3400
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3401
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3402
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3403 3404
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
			   unsigned int flags);
3405 3406
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3407
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3408 3409 3410 3411
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3412 3413 3414 3415 3416
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3417
int __must_check
3418 3419 3420
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3421
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3422
struct i915_vma * __must_check
3423 3424
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3425
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3426
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3427
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3428
				int align);
3429
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3430
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3431

3432 3433 3434
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3435 3436 3437 3438 3439 3440
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3441 3442 3443 3444 3445 3446
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

J
Joonas Lahtinen 已提交
3447
/* i915_gem_fence_reg.c */
3448 3449 3450
int __must_check i915_vma_get_fence(struct i915_vma *vma);
int __must_check i915_vma_put_fence(struct i915_vma *vma);

3451
void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3452
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3453

3454
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3455 3456 3457 3458
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3459

3460 3461 3462 3463 3464
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3465
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3466 3467 3468 3469 3470 3471 3472 3473

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3474 3475
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3476
{
3477
	kref_get(&ctx->ref);
3478
	return ctx;
3479 3480
}

3481
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3482
{
3483
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3484
	kref_put(&ctx->ref, i915_gem_context_free);
3485 3486
}

3487 3488
static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
{
3489 3490 3491 3492
	struct mutex *lock = &ctx->i915->drm.struct_mutex;

	if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
		mutex_unlock(lock);
3493 3494
}

C
Chris Wilson 已提交
3495 3496 3497 3498 3499 3500 3501 3502 3503 3504
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3505 3506 3507
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);

3508
/* i915_gem_evict.c */
3509
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3510
					  u64 min_size, u64 alignment,
3511
					  unsigned cache_level,
3512
					  u64 start, u64 end,
3513
					  unsigned flags);
3514 3515 3516
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
3517
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3518

3519
/* belongs in i915_gem_gtt.h */
3520
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3521
{
3522
	wmb();
3523
	if (INTEL_GEN(dev_priv) < 6)
3524 3525
		intel_gtt_chipset_flush();
}
3526

3527
/* i915_gem_stolen.c */
3528 3529 3530
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3531 3532 3533 3534
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3535 3536
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3537
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3538
void i915_gem_cleanup_stolen(struct drm_device *dev);
3539
struct drm_i915_gem_object *
3540
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3541
struct drm_i915_gem_object *
3542
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3543 3544 3545
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3546

3547 3548 3549
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3550
				phys_addr_t size);
3551

3552 3553
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3554
			      unsigned long target,
3555 3556 3557 3558
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3559
#define I915_SHRINK_ACTIVE 0x8
3560
#define I915_SHRINK_VMAPS 0x10
3561 3562
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3563
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3564 3565


3566
/* i915_gem_tiling.c */
3567
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3568
{
3569
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3570 3571

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3572
		i915_gem_object_is_tiled(obj);
3573 3574
}

3575 3576 3577 3578 3579
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

3580
/* i915_debugfs.c */
3581
#ifdef CONFIG_DEBUG_FS
3582 3583
int i915_debugfs_register(struct drm_i915_private *dev_priv);
void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3584
int i915_debugfs_connector_add(struct drm_connector *connector);
3585
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3586
#else
3587 3588
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3589 3590
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3591
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3592
#endif
3593 3594

/* i915_gpu_error.c */
3595 3596
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

3597 3598
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3599
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3600
			    const struct i915_gpu_state *gpu);
3601
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3602
			      struct drm_i915_private *i915,
3603 3604 3605 3606 3607 3608
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3609 3610

struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3611 3612
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3613
			      const char *error_msg);
3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630

static inline struct i915_gpu_state *
i915_gpu_state_get(struct i915_gpu_state *gpu)
{
	kref_get(&gpu->ref);
	return gpu;
}

void __i915_gpu_state_free(struct kref *kref);
static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
{
	if (gpu)
		kref_put(&gpu->ref, __i915_gpu_state_free);
}

struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
void i915_reset_error_state(struct drm_i915_private *i915);
3631

3632 3633 3634 3635 3636 3637 3638 3639
#else

static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
					    u32 engine_mask,
					    const char *error_msg)
{
}

3640 3641 3642 3643 3644 3645 3646
static inline struct i915_gpu_state *
i915_first_error_state(struct drm_i915_private *i915)
{
	return NULL;
}

static inline void i915_reset_error_state(struct drm_i915_private *i915)
3647 3648 3649 3650 3651
{
}

#endif

3652
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3653

3654
/* i915_cmd_parser.c */
3655
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3656
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3657 3658 3659 3660 3661 3662 3663
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3664

3665 3666 3667
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3668 3669
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3670

3671
/* i915_suspend.c */
3672 3673
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3674

B
Ben Widawsky 已提交
3675
/* i915_sysfs.c */
D
David Weinehall 已提交
3676 3677
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3678

3679
/* intel_i2c.c */
3680 3681
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3682 3683
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3684

3685 3686
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3687 3688
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3689
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3690 3691 3692
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3693
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3694

3695
/* intel_bios.c */
3696
int intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3697
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3698
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3699
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3700
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3701
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3702
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3703
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3704 3705
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3706 3707 3708
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

3709

3710
/* intel_opregion.c */
3711
#ifdef CONFIG_ACPI
3712
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3713 3714
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3715
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3716 3717
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3718
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3719
					 pci_power_t state);
3720
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3721
#else
3722
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3723 3724
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3725 3726 3727
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3728 3729 3730 3731 3732
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3733
static inline int
3734
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3735 3736 3737
{
	return 0;
}
3738
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3739 3740 3741
{
	return -ENODEV;
}
3742
#endif
3743

J
Jesse Barnes 已提交
3744 3745 3746 3747 3748 3749 3750 3751 3752
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3753 3754 3755 3756 3757 3758 3759
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

3760
const char *intel_platform_name(enum intel_platform platform);
3761 3762 3763
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3764
/* modesetting */
3765
extern void intel_modeset_init_hw(struct drm_device *dev);
3766
extern int intel_modeset_init(struct drm_device *dev);
3767
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3768
extern void intel_modeset_cleanup(struct drm_device *dev);
3769
extern int intel_connector_register(struct drm_connector *);
3770
extern void intel_connector_unregister(struct drm_connector *);
3771 3772
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
3773
extern void intel_display_resume(struct drm_device *dev);
3774 3775
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3776
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3777
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3778
extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3779
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3780
				  bool enable);
3781

B
Ben Widawsky 已提交
3782 3783
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3784

3785
/* overlay */
3786 3787
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3788 3789
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3790

3791 3792
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3793
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3794
					    struct intel_display_error_state *error);
3795

3796 3797
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3798 3799
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms);
3800 3801

/* intel_sideband.c */
3802
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3803
int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3804
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3805 3806
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3807 3808 3809 3810
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3811 3812
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3813 3814
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3815 3816 3817 3818
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3819 3820
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3821

3822
/* intel_dpio_phy.c */
3823
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3824
			     enum dpio_phy *phy, enum dpio_channel *ch);
3825 3826 3827
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
					     uint8_t lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3840 3841 3842
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3843 3844
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3845
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3846 3847
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3848
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3849

3850 3851 3852
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3853
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3854
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3855
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3856

3857 3858
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3859

3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3873 3874 3875 3876
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3877 3878 3879 3880 3881 3882 3883 3884 3885
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3886
 */
3887
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3888

3889
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3890 3891
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3892
	do {								\
3893
		old_upper = upper;					\
3894
		lower = I915_READ(lower_reg);				\
3895 3896
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3897
	(u64)upper << 32 | lower; })
3898

3899 3900 3901
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3902 3903
#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3904
					     i915_reg_t reg) \
3905
{ \
3906
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3907 3908 3909 3910
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3911
				       i915_reg_t reg, uint##x##_t val) \
3912
{ \
3913
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3928
/* These are untraced mmio-accessors that are only valid to be used inside
3929
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3930
 * controlled.
3931
 *
3932
 * Think twice, and think again, before using these.
3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
3953
 */
3954 3955
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3956
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3957 3958
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3959 3960 3961 3962
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3963

3964
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3965
{
3966
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3967
		return VLV_VGACNTRL;
3968
	else if (INTEL_GEN(dev_priv) >= 5)
3969
		return CPU_VGACNTRL;
3970 3971 3972 3973
	else
		return VGACNTRL;
}

3974 3975 3976 3977 3978 3979 3980
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3981 3982 3983 3984 3985
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3986 3987 3988 3989 3990 3991 3992 3993
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3994 3995 3996 3997 3998 3999 4000 4001 4002
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
4003
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4004 4005 4006 4007 4008 4009 4010 4011 4012 4013

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
4014 4015 4016 4017
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
4018 4019
	}
}
4020 4021

static inline bool
4022
__i915_request_irq_complete(const struct drm_i915_gem_request *req)
4023
{
4024
	struct intel_engine_cs *engine = req->engine;
4025
	u32 seqno;
4026

4027 4028 4029 4030 4031 4032 4033 4034 4035
	/* Note that the engine may have wrapped around the seqno, and
	 * so our request->global_seqno will be ahead of the hardware,
	 * even though it completed the request before wrapping. We catch
	 * this by kicking all the waiters before resetting the seqno
	 * in hardware, and also signal the fence.
	 */
	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
		return true;

4036 4037 4038 4039 4040 4041 4042 4043 4044 4045
	/* The request was dequeued before we were awoken. We check after
	 * inspecting the hw to confirm that this was the same request
	 * that generated the HWS update. The memory barriers within
	 * the request execution are sufficient to ensure that a check
	 * after reading the value from hw matches this request.
	 */
	seqno = i915_gem_request_global_seqno(req);
	if (!seqno)
		return false;

4046 4047 4048
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
4049
	if (__i915_gem_request_completed(req, seqno))
4050 4051
		return true;

4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
4063
	if (engine->irq_seqno_barrier &&
4064
	    test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4065 4066
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
		unsigned long flags;
4067

4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
4080
		engine->irq_seqno_barrier(engine);
4081 4082 4083 4084 4085 4086 4087

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
4088 4089
		spin_lock_irqsave(&b->lock, flags);
		if (b->first_wait && b->first_wait->tsk != current)
4090 4091 4092 4093 4094 4095
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
4096 4097
			wake_up_process(b->first_wait->tsk);
		spin_unlock_irqrestore(&b->lock, flags);
4098

4099
		if (__i915_gem_request_completed(req, seqno))
4100 4101
			return true;
	}
4102 4103 4104 4105

	return false;
}

4106 4107 4108
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124
/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
 * perform the operation. To check beforehand, pass in the parameters to
 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
 * you only need to pass in the minor offsets, page-aligned pointers are
 * always valid.
 *
 * For just checking for SSE4.1, in the foreknowledge that the future use
 * will be correctly aligned, just use i915_has_memcpy_from_wc().
 */
#define i915_can_memcpy_from_wc(dst, src, len) \
	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)

#define i915_has_memcpy_from_wc() \
	i915_memcpy_from_wc(NULL, NULL, 0)

4125 4126 4127 4128 4129
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

4130 4131 4132 4133 4134 4135
static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
{
	return (obj->cache_level != I915_CACHE_NONE ||
		HAS_LLC(to_i915(obj->base.dev)));
}

L
Linus Torvalds 已提交
4136
#endif