intel_lrc.c 82.3 KB
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/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky <ben@bwidawsk.net>
 *    Michel Thierry <michel.thierry@intel.com>
 *    Thomas Daniel <thomas.daniel@intel.com>
 *    Oscar Mateo <oscar.mateo@intel.com>
 *
 */

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/**
 * DOC: Logical Rings, Logical Ring Contexts and Execlists
 *
 * Motivation:
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 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
 * These expanded contexts enable a number of new abilities, especially
 * "Execlists" (also implemented in this file).
 *
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 * One of the main differences with the legacy HW contexts is that logical
 * ring contexts incorporate many more things to the context's state, like
 * PDPs or ringbuffer control registers:
 *
 * The reason why PDPs are included in the context is straightforward: as
 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
 * instead, the GPU will do it for you on the context switch.
 *
 * But, what about the ringbuffer control registers (head, tail, etc..)?
 * shouldn't we just need a set of those per engine command streamer? This is
 * where the name "Logical Rings" starts to make sense: by virtualizing the
 * rings, the engine cs shifts to a new "ring buffer" with every context
 * switch. When you want to submit a workload to the GPU you: A) choose your
 * context, B) find its appropriate virtualized ring, C) write commands to it
 * and then, finally, D) tell the GPU to switch to that context.
 *
 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
 * to a contexts is via a context execution list, ergo "Execlists".
 *
 * LRC implementation:
 * Regarding the creation of contexts, we have:
 *
 * - One global default context.
 * - One local default context for each opened fd.
 * - One local extra context for each context create ioctl call.
 *
 * Now that ringbuffers belong per-context (and not per-engine, like before)
 * and that contexts are uniquely tied to a given engine (and not reusable,
 * like before) we need:
 *
 * - One ringbuffer per-engine inside each context.
 * - One backing object per-engine inside each context.
 *
 * The global default context starts its life with these new objects fully
 * allocated and populated. The local default context for each opened fd is
 * more complex, because we don't know at creation time which engine is going
 * to use them. To handle this, we have implemented a deferred creation of LR
 * contexts:
 *
 * The local context starts its life as a hollow or blank holder, that only
 * gets populated for a given engine once we receive an execbuffer. If later
 * on we receive another execbuffer ioctl for the same context but a different
 * engine, we allocate/populate a new ringbuffer and context backing object and
 * so on.
 *
 * Finally, regarding local contexts created using the ioctl call: as they are
 * only allowed with the render ring, we can allocate & populate them right
 * away (no need to defer anything, at least for now).
 *
 * Execlists implementation:
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 * Execlists are the new method by which, on gen8+ hardware, workloads are
 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
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 * This method works as follows:
 *
 * When a request is committed, its commands (the BB start and any leading or
 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
 * for the appropriate context. The tail pointer in the hardware context is not
 * updated at this time, but instead, kept by the driver in the ringbuffer
 * structure. A structure representing this request is added to a request queue
 * for the appropriate engine: this structure contains a copy of the context's
 * tail after the request was written to the ring buffer and a pointer to the
 * context itself.
 *
 * If the engine's request queue was empty before the request was added, the
 * queue is processed immediately. Otherwise the queue will be processed during
 * a context switch interrupt. In any case, elements on the queue will get sent
 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 * globally unique 20-bits submission ID.
 *
 * When execution of a request completes, the GPU updates the context status
 * buffer with a context complete event and generates a context switch interrupt.
 * During the interrupt handling, the driver examines the events in the buffer:
 * for each context complete event, if the announced ID matches that on the head
 * of the request queue, then that request is retired and removed from the queue.
 *
 * After processing, if any requests were retired and the queue is not empty
 * then a new execution list can be submitted. The two requests at the front of
 * the queue are next to be submitted but since a context may not occur twice in
 * an execution list, if subsequent requests have the same ID as the first then
 * the two requests must be combined. This is done simply by discarding requests
 * at the head of the queue until either only one requests is left (in which case
 * we use a NULL second context) or the first two requests have unique IDs.
 *
 * By always executing the first two requests in the queue the driver ensures
 * that the GPU is kept as busy as possible. In the case where a single context
 * completes but a second context is still executing, the request for this second
 * context will be at the head of the queue when we remove the first one. This
 * request will then be resubmitted along with a new request for a different context,
 * which will cause the hardware to continue executing the second request and queue
 * the new request (the GPU detects the condition of a context getting preempted
 * with the same context and optimizes the context switch flow by not doing
 * preemption, but just sampling the new tail pointer).
 *
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 */
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#include <linux/interrupt.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
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#include "intel_mocs.h"
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#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
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#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)

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#define RING_EXECLIST_QFULL		(1 << 0x2)
#define RING_EXECLIST1_VALID		(1 << 0x3)
#define RING_EXECLIST0_VALID		(1 << 0x4)
#define RING_EXECLIST_ACTIVE_STATUS	(3 << 0xE)
#define RING_EXECLIST1_ACTIVE		(1 << 0x11)
#define RING_EXECLIST0_ACTIVE		(1 << 0x12)

#define GEN8_CTX_STATUS_IDLE_ACTIVE	(1 << 0)
#define GEN8_CTX_STATUS_PREEMPTED	(1 << 1)
#define GEN8_CTX_STATUS_ELEMENT_SWITCH	(1 << 2)
#define GEN8_CTX_STATUS_ACTIVE_IDLE	(1 << 3)
#define GEN8_CTX_STATUS_COMPLETE	(1 << 4)
#define GEN8_CTX_STATUS_LITE_RESTORE	(1 << 15)
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#define CTX_LRI_HEADER_0		0x01
#define CTX_CONTEXT_CONTROL		0x02
#define CTX_RING_HEAD			0x04
#define CTX_RING_TAIL			0x06
#define CTX_RING_BUFFER_START		0x08
#define CTX_RING_BUFFER_CONTROL		0x0a
#define CTX_BB_HEAD_U			0x0c
#define CTX_BB_HEAD_L			0x0e
#define CTX_BB_STATE			0x10
#define CTX_SECOND_BB_HEAD_U		0x12
#define CTX_SECOND_BB_HEAD_L		0x14
#define CTX_SECOND_BB_STATE		0x16
#define CTX_BB_PER_CTX_PTR		0x18
#define CTX_RCS_INDIRECT_CTX		0x1a
#define CTX_RCS_INDIRECT_CTX_OFFSET	0x1c
#define CTX_LRI_HEADER_1		0x21
#define CTX_CTX_TIMESTAMP		0x22
#define CTX_PDP3_UDW			0x24
#define CTX_PDP3_LDW			0x26
#define CTX_PDP2_UDW			0x28
#define CTX_PDP2_LDW			0x2a
#define CTX_PDP1_UDW			0x2c
#define CTX_PDP1_LDW			0x2e
#define CTX_PDP0_UDW			0x30
#define CTX_PDP0_LDW			0x32
#define CTX_LRI_HEADER_2		0x41
#define CTX_R_PWR_CLK_STATE		0x42
#define CTX_GPGPU_CSR_BASE_ADDRESS	0x44

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#define GEN8_CTX_VALID (1<<0)
#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
#define GEN8_CTX_FORCE_RESTORE (1<<2)
#define GEN8_CTX_L3LLC_COHERENT (1<<5)
#define GEN8_CTX_PRIVILEGE (1<<8)
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#define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
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	(reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
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	(reg_state)[(pos)+1] = (val); \
} while (0)

#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {		\
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	const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n));	\
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	reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
	reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
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} while (0)
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#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
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	reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
	reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
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} while (0)
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enum {
	ADVANCED_CONTEXT = 0,
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	LEGACY_32B_CONTEXT,
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	ADVANCED_AD_CONTEXT,
	LEGACY_64B_CONTEXT
};
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#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
#define GEN8_CTX_ADDRESSING_MODE(dev)  (USES_FULL_48BIT_PPGTT(dev) ?\
		LEGACY_64B_CONTEXT :\
		LEGACY_32B_CONTEXT)
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enum {
	FAULT_AND_HANG = 0,
	FAULT_AND_HALT, /* Debug only */
	FAULT_AND_STREAM,
	FAULT_AND_CONTINUE /* Unsupported */
};
#define GEN8_CTX_ID_SHIFT 32
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#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
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static int intel_lr_context_pin(struct intel_context *ctx,
				struct intel_engine_cs *engine);
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/**
 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 * @dev: DRM device.
 * @enable_execlists: value of i915.enable_execlists module parameter.
 *
 * Only certain platforms support Execlists (the prerequisites being
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 * support for Logical Ring Contexts and Aliasing PPGTT or better).
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 *
 * Return: 1 if Execlists is supported and has to be enabled.
 */
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int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
{
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	WARN_ON(i915.enable_ppgtt == -1);

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	/* On platforms with execlist available, vGPU will only
	 * support execlist mode, no ring buffer mode.
	 */
	if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
		return 1;

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	if (INTEL_INFO(dev)->gen >= 9)
		return 1;

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	if (enable_execlists == 0)
		return 0;

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	if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
	    i915.use_mmio_flip >= 0)
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		return 1;

	return 0;
}
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static void
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logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
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{
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	struct drm_device *dev = engine->dev;
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	if (IS_GEN8(dev) || IS_GEN9(dev))
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		engine->idle_lite_restore_wa = ~0;
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	engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
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					IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
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					(engine->id == VCS || engine->id == VCS2);
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	engine->ctx_desc_template = GEN8_CTX_VALID;
	engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
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				   GEN8_CTX_ADDRESSING_MODE_SHIFT;
	if (IS_GEN8(dev))
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		engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
	engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
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	/* TODO: WaDisableLiteRestore when we start using semaphore
	 * signalling between Command Streamers */
	/* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */

	/* WaEnableForceRestoreInCtxtDescForVCS:skl */
	/* WaEnableForceRestoreInCtxtDescForVCS:bxt */
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	if (engine->disable_lite_restore_wa)
		engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
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}

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/**
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 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
 * 					  descriptor for a pinned context
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 *
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 * @ctx: Context to work on
 * @ring: Engine the descriptor will be used with
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 *
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 * The context descriptor encodes various attributes of a context,
 * including its GTT address and some flags. Because it's fairly
 * expensive to calculate, we'll just do it once and cache the result,
 * which remains valid until the context is unpinned.
 *
 * This is what a descriptor looks like, from LSB to MSB:
 *    bits 0-11:    flags, GEN8_CTX_* (cached in ctx_desc_template)
 *    bits 12-31:    LRCA, GTT address of (the HWSP of) this context
 *    bits 32-51:    ctx ID, a globally unique tag (the LRCA again!)
 *    bits 52-63:    reserved, may encode the engine ID (for GuC)
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 */
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static void
intel_lr_context_descriptor_update(struct intel_context *ctx,
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				   struct intel_engine_cs *engine)
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{
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	uint64_t lrca, desc;
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	lrca = ctx->engine[engine->id].lrc_vma->node.start +
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	       LRC_PPHWSP_PN * PAGE_SIZE;
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	desc = engine->ctx_desc_template;			   /* bits  0-11 */
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	desc |= lrca;					   /* bits 12-31 */
	desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */
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	ctx->engine[engine->id].lrc_desc = desc;
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}

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uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
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				     struct intel_engine_cs *engine)
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{
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	return ctx->engine[engine->id].lrc_desc;
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}
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/**
 * intel_execlists_ctx_id() - get the Execlists Context ID
 * @ctx: Context to get the ID for
 * @ring: Engine to get the ID for
 *
 * Do not confuse with ctx->id! Unfortunately we have a name overload
 * here: the old context ID we pass to userspace as a handler so that
 * they can refer to a context, and the new context ID we pass to the
 * ELSP so that the GPU can inform us of the context status via
 * interrupts.
 *
 * The context ID is a portion of the context descriptor, so we can
 * just extract the required part from the cached descriptor.
 *
 * Return: 20-bits globally unique context ID.
 */
u32 intel_execlists_ctx_id(struct intel_context *ctx,
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			   struct intel_engine_cs *engine)
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{
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	return intel_lr_context_descriptor(ctx, engine) >> GEN8_CTX_ID_SHIFT;
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}

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static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
				 struct drm_i915_gem_request *rq1)
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{
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	struct intel_engine_cs *engine = rq0->engine;
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	struct drm_device *dev = engine->dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	uint64_t desc[2];
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	if (rq1) {
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		desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
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		rq1->elsp_submitted++;
	} else {
		desc[1] = 0;
	}
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	desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);
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	rq0->elsp_submitted++;
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	/* You must always write both descriptors in the order below. */
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	I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
	I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
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	I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
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	/* The context is automatically loaded after the following */
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	I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
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	/* ELSP is a wo register, use another nearby reg for posting */
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	POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine));
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}

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static void
execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
{
	ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
}

static void execlists_update_context(struct drm_i915_gem_request *rq)
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{
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	struct intel_engine_cs *engine = rq->engine;
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	struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
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	uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
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	reg_state[CTX_RING_TAIL+1] = rq->tail;
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	/* True 32b PPGTT with dynamic page allocation: update PDP
	 * registers and point the unallocated PDPs to scratch page.
	 * PML4 is allocated during ppgtt init, so this is not needed
	 * in 48-bit mode.
	 */
	if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
		execlists_update_context_pdps(ppgtt, reg_state);
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}

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static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
				      struct drm_i915_gem_request *rq1)
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{
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	struct drm_i915_private *dev_priv = rq0->i915;
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	unsigned int fw_domains = rq0->engine->fw_domains;
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	execlists_update_context(rq0);
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	if (rq1)
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		execlists_update_context(rq1);
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	spin_lock_irq(&dev_priv->uncore.lock);
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	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
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	execlists_elsp_write(rq0, rq1);
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	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
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	spin_unlock_irq(&dev_priv->uncore.lock);
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}

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static void execlists_context_unqueue(struct intel_engine_cs *engine)
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{
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	struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
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	struct drm_i915_gem_request *cursor, *tmp;
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	assert_spin_locked(&engine->execlist_lock);
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	/*
	 * If irqs are not active generate a warning as batches that finish
	 * without the irqs may get lost and a GPU Hang may occur.
	 */
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	WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
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	/* Try to read in pairs */
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	list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
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				 execlist_link) {
		if (!req0) {
			req0 = cursor;
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		} else if (req0->ctx == cursor->ctx) {
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			/* Same ctx: ignore first request, as second request
			 * will update tail past first request's workload */
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			cursor->elsp_submitted = req0->elsp_submitted;
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			list_move_tail(&req0->execlist_link,
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				       &engine->execlist_retired_req_list);
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			req0 = cursor;
		} else {
			req1 = cursor;
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			WARN_ON(req1->elsp_submitted);
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			break;
		}
	}

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	if (unlikely(!req0))
		return;

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	if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
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		/*
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		 * WaIdleLiteRestore: make sure we never cause a lite restore
		 * with HEAD==TAIL.
		 *
		 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
		 * resubmit the request. See gen8_emit_request() for where we
		 * prepare the padding after the end of the request.
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		 */
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		struct intel_ringbuffer *ringbuf;
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		ringbuf = req0->ctx->engine[engine->id].ringbuf;
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		req0->tail += 8;
		req0->tail &= ringbuf->size - 1;
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	}

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	execlists_submit_requests(req0, req1);
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}

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static unsigned int
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execlists_check_remove_request(struct intel_engine_cs *engine, u32 request_id)
490
{
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	struct drm_i915_gem_request *head_req;
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	assert_spin_locked(&engine->execlist_lock);
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	head_req = list_first_entry_or_null(&engine->execlist_queue,
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					    struct drm_i915_gem_request,
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					    execlist_link);

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	if (!head_req)
		return 0;
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	if (unlikely(intel_execlists_ctx_id(head_req->ctx, engine) != request_id))
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		return 0;

	WARN(head_req->elsp_submitted == 0, "Never submitted head request\n");

	if (--head_req->elsp_submitted > 0)
		return 0;

	list_move_tail(&head_req->execlist_link,
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		       &engine->execlist_retired_req_list);
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	return 1;
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}

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static u32
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get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
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		   u32 *context_id)
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Ben Widawsky 已提交
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{
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	struct drm_i915_private *dev_priv = engine->dev->dev_private;
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	u32 status;
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Ben Widawsky 已提交
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	read_pointer %= GEN8_CSB_ENTRIES;

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	status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer));
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	if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
		return 0;
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Ben Widawsky 已提交
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	*context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine,
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							      read_pointer));

	return status;
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Ben Widawsky 已提交
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}

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/**
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 * intel_lrc_irq_handler() - handle Context Switch interrupts
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 * @engine: Engine Command Streamer to handle.
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 *
 * Check the unread Context Status Buffers and manage the submission of new
 * contexts to the ELSP accordingly.
 */
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static void intel_lrc_irq_handler(unsigned long data)
544
{
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	struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
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	struct drm_i915_private *dev_priv = engine->dev->dev_private;
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	u32 status_pointer;
548
	unsigned int read_pointer, write_pointer;
549 550
	u32 csb[GEN8_CSB_ENTRIES][2];
	unsigned int csb_read = 0, i;
551 552
	unsigned int submit_contexts = 0;

553
	intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
554

555
	status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine));
556

557
	read_pointer = engine->next_context_status_buffer;
558
	write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
559
	if (read_pointer > write_pointer)
560
		write_pointer += GEN8_CSB_ENTRIES;
561 562

	while (read_pointer < write_pointer) {
563 564 565 566 567 568
		if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES))
			break;
		csb[csb_read][0] = get_context_status(engine, ++read_pointer,
						      &csb[csb_read][1]);
		csb_read++;
	}
B
Ben Widawsky 已提交
569

570 571 572 573 574 575 576 577
	engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;

	/* Update the read pointer to the old write pointer. Manual ringbuffer
	 * management ftw </sarcasm> */
	I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine),
		      _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
				    engine->next_context_status_buffer << 8));

578
	intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
579 580 581 582 583 584 585

	spin_lock(&engine->execlist_lock);

	for (i = 0; i < csb_read; i++) {
		if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) {
			if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) {
				if (execlists_check_remove_request(engine, csb[i][1]))
586 587 588 589 590
					WARN(1, "Lite Restored request removed from queue\n");
			} else
				WARN(1, "Preemption without Lite Restore\n");
		}

591
		if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE |
592 593
		    GEN8_CTX_STATUS_ELEMENT_SWITCH))
			submit_contexts +=
594
				execlists_check_remove_request(engine, csb[i][1]);
595 596
	}

597
	if (submit_contexts) {
598
		if (!engine->disable_lite_restore_wa ||
599 600
		    (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
			execlists_context_unqueue(engine);
601
	}
602

603
	spin_unlock(&engine->execlist_lock);
604 605 606

	if (unlikely(submit_contexts > 2))
		DRM_ERROR("More than two context complete events?\n");
607 608
}

609
static void execlists_context_queue(struct drm_i915_gem_request *request)
610
{
611
	struct intel_engine_cs *engine = request->engine;
612
	struct drm_i915_gem_request *cursor;
613
	int num_elements = 0;
614

615
	if (request->ctx != request->i915->kernel_context)
616
		intel_lr_context_pin(request->ctx, engine);
617

618 619
	i915_gem_request_reference(request);

620
	spin_lock_bh(&engine->execlist_lock);
621

622
	list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
623 624 625 626
		if (++num_elements > 2)
			break;

	if (num_elements > 2) {
627
		struct drm_i915_gem_request *tail_req;
628

629
		tail_req = list_last_entry(&engine->execlist_queue,
630
					   struct drm_i915_gem_request,
631 632
					   execlist_link);

633
		if (request->ctx == tail_req->ctx) {
634
			WARN(tail_req->elsp_submitted != 0,
635
				"More than 2 already-submitted reqs queued\n");
636
			list_move_tail(&tail_req->execlist_link,
637
				       &engine->execlist_retired_req_list);
638 639 640
		}
	}

641
	list_add_tail(&request->execlist_link, &engine->execlist_queue);
642
	if (num_elements == 0)
643
		execlists_context_unqueue(engine);
644

645
	spin_unlock_bh(&engine->execlist_lock);
646 647
}

648
static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
649
{
650
	struct intel_engine_cs *engine = req->engine;
651 652 653 654
	uint32_t flush_domains;
	int ret;

	flush_domains = 0;
655
	if (engine->gpu_caches_dirty)
656 657
		flush_domains = I915_GEM_GPU_DOMAINS;

658
	ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
659 660 661
	if (ret)
		return ret;

662
	engine->gpu_caches_dirty = false;
663 664 665
	return 0;
}

666
static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
667 668
				 struct list_head *vmas)
{
669
	const unsigned other_rings = ~intel_engine_flag(req->engine);
670 671 672 673 674 675 676 677
	struct i915_vma *vma;
	uint32_t flush_domains = 0;
	bool flush_chipset = false;
	int ret;

	list_for_each_entry(vma, vmas, exec_list) {
		struct drm_i915_gem_object *obj = vma->obj;

678
		if (obj->active & other_rings) {
679
			ret = i915_gem_object_sync(obj, req->engine, &req);
680 681 682
			if (ret)
				return ret;
		}
683 684 685 686 687 688 689 690 691 692 693 694 695

		if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
			flush_chipset |= i915_gem_clflush_object(obj, false);

		flush_domains |= obj->base.write_domain;
	}

	if (flush_domains & I915_GEM_DOMAIN_GTT)
		wmb();

	/* Unconditionally invalidate gpu caches and ensure that we do flush
	 * any residual writes from the previous batch.
	 */
696
	return logical_ring_invalidate_all_caches(req);
697 698
}

699
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
700
{
D
Dave Gordon 已提交
701
	int ret = 0;
702

703
	request->ringbuf = request->ctx->engine[request->engine->id].ringbuf;
704

705 706 707 708 709 710 711 712 713 714 715 716 717
	if (i915.enable_guc_submission) {
		/*
		 * Check that the GuC has space for the request before
		 * going any further, as the i915_add_request() call
		 * later on mustn't fail ...
		 */
		struct intel_guc *guc = &request->i915->guc;

		ret = i915_guc_wq_check_space(guc->execbuf_client);
		if (ret)
			return ret;
	}

D
Dave Gordon 已提交
718
	if (request->ctx != request->i915->kernel_context)
719
		ret = intel_lr_context_pin(request->ctx, request->engine);
D
Dave Gordon 已提交
720 721

	return ret;
722 723
}

724
static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
725
				       int bytes)
726
{
727
	struct intel_ringbuffer *ringbuf = req->ringbuf;
728
	struct intel_engine_cs *engine = req->engine;
729
	struct drm_i915_gem_request *target;
730 731
	unsigned space;
	int ret;
732 733 734 735

	if (intel_ring_space(ringbuf) >= bytes)
		return 0;

736 737 738
	/* The whole point of reserving space is to not wait! */
	WARN_ON(ringbuf->reserved_in_use);

739
	list_for_each_entry(target, &engine->request_list, list) {
740 741 742 743 744
		/*
		 * The request queue is per-engine, so can contain requests
		 * from multiple ringbuffers. Here, we must ignore any that
		 * aren't from the ringbuffer we're considering.
		 */
745
		if (target->ringbuf != ringbuf)
746 747 748
			continue;

		/* Would completion of this request free enough space? */
749
		space = __intel_ring_space(target->postfix, ringbuf->tail,
750 751
					   ringbuf->size);
		if (space >= bytes)
752 753 754
			break;
	}

755
	if (WARN_ON(&target->list == &engine->request_list))
756 757
		return -ENOSPC;

758
	ret = i915_wait_request(target);
759 760 761
	if (ret)
		return ret;

762 763
	ringbuf->space = space;
	return 0;
764 765 766 767
}

/*
 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
768
 * @request: Request to advance the logical ringbuffer of.
769 770 771 772 773 774
 *
 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 * really happens during submission is that the context and current tail will be placed
 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 * point, the tail *inside* the context is updated and the ELSP written to.
 */
775
static int
776
intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
777
{
778
	struct intel_ringbuffer *ringbuf = request->ringbuf;
779
	struct drm_i915_private *dev_priv = request->i915;
780
	struct intel_engine_cs *engine = request->engine;
781

782 783
	intel_logical_ring_advance(ringbuf);
	request->tail = ringbuf->tail;
784

785 786 787 788 789 790 791 792 793
	/*
	 * Here we add two extra NOOPs as padding to avoid
	 * lite restore of a context with HEAD==TAIL.
	 *
	 * Caller must reserve WA_TAIL_DWORDS for us!
	 */
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);
794

795
	if (intel_engine_stopped(engine))
796
		return 0;
797

798 799 800 801 802 803 804 805 806 807 808
	if (engine->last_context != request->ctx) {
		if (engine->last_context)
			intel_lr_context_unpin(engine->last_context, engine);
		if (request->ctx != request->i915->kernel_context) {
			intel_lr_context_pin(request->ctx, engine);
			engine->last_context = request->ctx;
		} else {
			engine->last_context = NULL;
		}
	}

809 810 811 812
	if (dev_priv->guc.execbuf_client)
		i915_guc_submit(dev_priv->guc.execbuf_client, request);
	else
		execlists_context_queue(request);
813 814

	return 0;
815 816
}

817
static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
818 819 820 821 822 823 824 825 826 827 828 829 830
{
	uint32_t __iomem *virt;
	int rem = ringbuf->size - ringbuf->tail;

	virt = ringbuf->virtual_start + ringbuf->tail;
	rem /= 4;
	while (rem--)
		iowrite32(MI_NOOP, virt++);

	ringbuf->tail = 0;
	intel_ring_update_space(ringbuf);
}

831
static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
832
{
833
	struct intel_ringbuffer *ringbuf = req->ringbuf;
834 835 836 837
	int remain_usable = ringbuf->effective_size - ringbuf->tail;
	int remain_actual = ringbuf->size - ringbuf->tail;
	int ret, total_bytes, wait_bytes = 0;
	bool need_wrap = false;
838

839 840 841 842
	if (ringbuf->reserved_in_use)
		total_bytes = bytes;
	else
		total_bytes = bytes + ringbuf->reserved_size;
843

844 845 846 847 848 849 850 851 852 853 854
	if (unlikely(bytes > remain_usable)) {
		/*
		 * Not enough space for the basic request. So need to flush
		 * out the remainder and then wait for base + reserved.
		 */
		wait_bytes = remain_actual + total_bytes;
		need_wrap = true;
	} else {
		if (unlikely(total_bytes > remain_usable)) {
			/*
			 * The base request will fit but the reserved space
855 856 857
			 * falls off the end. So don't need an immediate wrap
			 * and only need to effectively wait for the reserved
			 * size space from the start of ringbuffer.
858 859 860 861 862
			 */
			wait_bytes = remain_actual + ringbuf->reserved_size;
		} else if (total_bytes > ringbuf->space) {
			/* No wrapping required, just waiting. */
			wait_bytes = total_bytes;
863
		}
864 865
	}

866 867
	if (wait_bytes) {
		ret = logical_ring_wait_for_space(req, wait_bytes);
868 869
		if (unlikely(ret))
			return ret;
870 871 872

		if (need_wrap)
			__wrap_ring_buffer(ringbuf);
873 874 875 876 877 878 879 880
	}

	return 0;
}

/**
 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
 *
881
 * @req: The request to start some new work for
882 883 884 885 886 887 888 889 890
 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
 *
 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
 * and also preallocates a request (every workload submission is still mediated through
 * requests, same as it did with legacy ringbuffer submission).
 *
 * Return: non-zero if the ringbuffer is not ready to be written to.
 */
891
int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
892 893 894
{
	int ret;

895
	ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
896 897 898
	if (ret)
		return ret;

899
	req->ringbuf->space -= num_dwords * sizeof(uint32_t);
900 901 902
	return 0;
}

903 904 905 906 907 908 909 910 911 912 913 914 915 916 917
int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
{
	/*
	 * The first call merely notes the reserve request and is common for
	 * all back ends. The subsequent localised _begin() call actually
	 * ensures that the reservation is available. Without the begin, if
	 * the request creator immediately submitted the request without
	 * adding any commands to it then there might not actually be
	 * sufficient room for the submission commands.
	 */
	intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);

	return intel_logical_ring_begin(request, 0);
}

918 919 920 921 922 923 924 925 926 927
/**
 * execlists_submission() - submit a batchbuffer for execution, Execlists style
 * @dev: DRM device.
 * @file: DRM file.
 * @ring: Engine Command Streamer to submit to.
 * @ctx: Context to employ for this submission.
 * @args: execbuffer call arguments.
 * @vmas: list of vmas.
 * @batch_obj: the batchbuffer to submit.
 * @exec_start: batchbuffer start virtual address pointer.
928
 * @dispatch_flags: translated execbuffer call flags.
929 930 931 932 933 934
 *
 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 * away the submission details of the execbuffer ioctl call.
 *
 * Return: non-zero if the submission fails.
 */
935
int intel_execlists_submission(struct i915_execbuffer_params *params,
936
			       struct drm_i915_gem_execbuffer2 *args,
937
			       struct list_head *vmas)
938
{
939
	struct drm_device       *dev = params->dev;
940
	struct intel_engine_cs *engine = params->engine;
941
	struct drm_i915_private *dev_priv = dev->dev_private;
942
	struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf;
943
	u64 exec_start;
944 945 946 947 948 949 950 951 952 953
	int instp_mode;
	u32 instp_mask;
	int ret;

	instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
	instp_mask = I915_EXEC_CONSTANTS_MASK;
	switch (instp_mode) {
	case I915_EXEC_CONSTANTS_REL_GENERAL:
	case I915_EXEC_CONSTANTS_ABSOLUTE:
	case I915_EXEC_CONSTANTS_REL_SURFACE:
954
		if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) {
955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978
			DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
			return -EINVAL;
		}

		if (instp_mode != dev_priv->relative_constants_mode) {
			if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
				DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
				return -EINVAL;
			}

			/* The HW changed the meaning on this bit on gen6 */
			instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
		}
		break;
	default:
		DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
		return -EINVAL;
	}

	if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
		DRM_DEBUG("sol reset is gen7 only\n");
		return -EINVAL;
	}

979
	ret = execlists_move_to_gpu(params->request, vmas);
980 981 982
	if (ret)
		return ret;

983
	if (engine == &dev_priv->engine[RCS] &&
984
	    instp_mode != dev_priv->relative_constants_mode) {
985
		ret = intel_logical_ring_begin(params->request, 4);
986 987 988 989 990
		if (ret)
			return ret;

		intel_logical_ring_emit(ringbuf, MI_NOOP);
		intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
991
		intel_logical_ring_emit_reg(ringbuf, INSTPM);
992 993 994 995 996 997
		intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
		intel_logical_ring_advance(ringbuf);

		dev_priv->relative_constants_mode = instp_mode;
	}

998 999 1000
	exec_start = params->batch_obj_vm_offset +
		     args->batch_start_offset;

1001
	ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags);
1002 1003 1004
	if (ret)
		return ret;

1005
	trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1006

1007
	i915_gem_execbuffer_move_to_active(vmas, params->request);
1008

1009 1010 1011
	return 0;
}

1012
void intel_execlists_retire_requests(struct intel_engine_cs *engine)
1013
{
1014
	struct drm_i915_gem_request *req, *tmp;
1015 1016
	struct list_head retired_list;

1017 1018
	WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
	if (list_empty(&engine->execlist_retired_req_list))
1019 1020 1021
		return;

	INIT_LIST_HEAD(&retired_list);
1022
	spin_lock_bh(&engine->execlist_lock);
1023
	list_replace_init(&engine->execlist_retired_req_list, &retired_list);
1024
	spin_unlock_bh(&engine->execlist_lock);
1025 1026

	list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
1027 1028
		struct intel_context *ctx = req->ctx;
		struct drm_i915_gem_object *ctx_obj =
1029
				ctx->engine[engine->id].state;
1030

1031
		if (ctx_obj && (ctx != req->i915->kernel_context))
1032
			intel_lr_context_unpin(ctx, engine);
1033

1034
		list_del(&req->execlist_link);
1035
		i915_gem_request_unreference(req);
1036 1037 1038
	}
}

1039
void intel_logical_ring_stop(struct intel_engine_cs *engine)
1040
{
1041
	struct drm_i915_private *dev_priv = engine->dev->dev_private;
1042 1043
	int ret;

1044
	if (!intel_engine_initialized(engine))
1045 1046
		return;

1047
	ret = intel_engine_idle(engine);
1048
	if (ret)
1049
		DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1050
			  engine->name, ret);
1051 1052

	/* TODO: Is this correct with Execlists enabled? */
1053 1054 1055
	I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
	if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
		DRM_ERROR("%s :timed out trying to stop ring\n", engine->name);
1056 1057
		return;
	}
1058
	I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
1059 1060
}

1061
int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
1062
{
1063
	struct intel_engine_cs *engine = req->engine;
1064 1065
	int ret;

1066
	if (!engine->gpu_caches_dirty)
1067 1068
		return 0;

1069
	ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1070 1071 1072
	if (ret)
		return ret;

1073
	engine->gpu_caches_dirty = false;
1074 1075 1076
	return 0;
}

1077
static int intel_lr_context_do_pin(struct intel_context *ctx,
1078
				   struct intel_engine_cs *engine)
1079
{
1080
	struct drm_device *dev = engine->dev;
1081
	struct drm_i915_private *dev_priv = dev->dev_private;
1082 1083
	struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
	struct intel_ringbuffer *ringbuf = ctx->engine[engine->id].ringbuf;
1084 1085
	void *vaddr;
	u32 *lrc_reg_state;
1086
	int ret;
1087

1088
	WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
1089

1090 1091 1092 1093
	ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
			PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
	if (ret)
		return ret;
1094

1095 1096 1097
	vaddr = i915_gem_object_pin_map(ctx_obj);
	if (IS_ERR(vaddr)) {
		ret = PTR_ERR(vaddr);
1098 1099 1100
		goto unpin_ctx_obj;
	}

1101 1102
	lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;

1103
	ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf);
1104
	if (ret)
1105
		goto unpin_map;
1106

1107 1108
	ctx->engine[engine->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj);
	intel_lr_context_descriptor_update(ctx, engine);
1109
	lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start;
1110
	ctx->engine[engine->id].lrc_reg_state = lrc_reg_state;
1111
	ctx_obj->dirty = true;
1112

1113 1114 1115
	/* Invalidate GuC TLB. */
	if (i915.enable_guc_submission)
		I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
1116

1117 1118
	return ret;

1119 1120
unpin_map:
	i915_gem_object_unpin_map(ctx_obj);
1121 1122
unpin_ctx_obj:
	i915_gem_object_ggtt_unpin(ctx_obj);
1123 1124 1125 1126

	return ret;
}

1127 1128
static int intel_lr_context_pin(struct intel_context *ctx,
				struct intel_engine_cs *engine)
1129 1130 1131
{
	int ret = 0;

1132 1133
	if (ctx->engine[engine->id].pin_count++ == 0) {
		ret = intel_lr_context_do_pin(ctx, engine);
1134 1135
		if (ret)
			goto reset_pin_count;
1136 1137

		i915_gem_context_reference(ctx);
1138 1139 1140
	}
	return ret;

1141
reset_pin_count:
1142
	ctx->engine[engine->id].pin_count = 0;
1143 1144 1145
	return ret;
}

1146 1147
void intel_lr_context_unpin(struct intel_context *ctx,
			    struct intel_engine_cs *engine)
1148
{
1149
	struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
1150

1151
	WARN_ON(!mutex_is_locked(&ctx->i915->dev->struct_mutex));
1152
	if (--ctx->engine[engine->id].pin_count == 0) {
1153
		i915_gem_object_unpin_map(ctx_obj);
1154
		intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf);
1155
		i915_gem_object_ggtt_unpin(ctx_obj);
1156 1157 1158
		ctx->engine[engine->id].lrc_vma = NULL;
		ctx->engine[engine->id].lrc_desc = 0;
		ctx->engine[engine->id].lrc_reg_state = NULL;
1159 1160

		i915_gem_context_unreference(ctx);
1161 1162 1163
	}
}

1164
static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1165 1166
{
	int ret, i;
1167
	struct intel_engine_cs *engine = req->engine;
1168
	struct intel_ringbuffer *ringbuf = req->ringbuf;
1169
	struct drm_device *dev = engine->dev;
1170 1171 1172
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_workarounds *w = &dev_priv->workarounds;

1173
	if (w->count == 0)
1174 1175
		return 0;

1176
	engine->gpu_caches_dirty = true;
1177
	ret = logical_ring_flush_all_caches(req);
1178 1179 1180
	if (ret)
		return ret;

1181
	ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1182 1183 1184 1185 1186
	if (ret)
		return ret;

	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
	for (i = 0; i < w->count; i++) {
1187
		intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
1188 1189 1190 1191 1192 1193
		intel_logical_ring_emit(ringbuf, w->reg[i].value);
	}
	intel_logical_ring_emit(ringbuf, MI_NOOP);

	intel_logical_ring_advance(ringbuf);

1194
	engine->gpu_caches_dirty = true;
1195
	ret = logical_ring_flush_all_caches(req);
1196 1197 1198 1199 1200 1201
	if (ret)
		return ret;

	return 0;
}

1202
#define wa_ctx_emit(batch, index, cmd)					\
1203
	do {								\
1204 1205
		int __index = (index)++;				\
		if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1206 1207
			return -ENOSPC;					\
		}							\
1208
		batch[__index] = (cmd);					\
1209 1210
	} while (0)

V
Ville Syrjälä 已提交
1211
#define wa_ctx_emit_reg(batch, index, reg) \
1212
	wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229

/*
 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
 * but there is a slight complication as this is applied in WA batch where the
 * values are only initialized once so we cannot take register value at the
 * beginning and reuse it further; hence we save its value to memory, upload a
 * constant value with bit21 set and then we restore it back with the saved value.
 * To simplify the WA, a constant value is formed by using the default value
 * of this register. This shouldn't be a problem because we are only modifying
 * it for a short period and this batch in non-premptible. We can ofcourse
 * use additional instructions that read the actual value of the register
 * at that time and set our bit of interest but it makes the WA complicated.
 *
 * This WA is also required for Gen9 so extracting as a function avoids
 * code duplication.
 */
1230
static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
1231 1232 1233 1234 1235
						uint32_t *const batch,
						uint32_t index)
{
	uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);

1236 1237 1238 1239 1240 1241
	/*
	 * WaDisableLSQCROPERFforOCL:skl
	 * This WA is implemented in skl_init_clock_gating() but since
	 * this batch updates GEN8_L3SQCREG4 with default value we need to
	 * set this bit here to retain the WA during flush.
	 */
1242
	if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
1243 1244
		l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;

1245
	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1246
				   MI_SRM_LRM_GLOBAL_GTT));
V
Ville Syrjälä 已提交
1247
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1248
	wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1249 1250 1251
	wa_ctx_emit(batch, index, 0);

	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
V
Ville Syrjälä 已提交
1252
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1253 1254 1255 1256 1257 1258 1259 1260 1261 1262
	wa_ctx_emit(batch, index, l3sqc4_flush);

	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_DC_FLUSH_ENABLE));
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);

1263
	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1264
				   MI_SRM_LRM_GLOBAL_GTT));
V
Ville Syrjälä 已提交
1265
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1266
	wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1267
	wa_ctx_emit(batch, index, 0);
1268 1269 1270 1271

	return index;
}

1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309
static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t offset,
				    uint32_t start_alignment)
{
	return wa_ctx->offset = ALIGN(offset, start_alignment);
}

static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
			     uint32_t offset,
			     uint32_t size_alignment)
{
	wa_ctx->size = offset - wa_ctx->offset;

	WARN(wa_ctx->size % size_alignment,
	     "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
	     wa_ctx->size, size_alignment);
	return 0;
}

/**
 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
 *
 * @ring: only applicable for RCS
 * @wa_ctx: structure representing wa_ctx
 *  offset: specifies start of the batch, should be cache-aligned. This is updated
 *    with the offset value received as input.
 *  size: size of the batch in DWORDS but HW expects in terms of cachelines
 * @batch: page in which WA are loaded
 * @offset: This field specifies the start of the batch, it should be
 *  cache-aligned otherwise it is adjusted accordingly.
 *  Typically we only have one indirect_ctx and per_ctx batch buffer which are
 *  initialized at the beginning and shared across all contexts but this field
 *  helps us to have multiple batches at different offsets and select them based
 *  on a criteria. At the moment this batch always start at the beginning of the page
 *  and at this point we don't have multiple wa_ctx batch buffers.
 *
 *  The number of WA applied are not known at the beginning; we use this field
 *  to return the no of DWORDS written.
1310
 *
1311 1312 1313 1314 1315 1316 1317 1318
 *  It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
 *  so it adds NOOPs as padding to make it cacheline aligned.
 *  MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
 *  makes a complete batch buffer.
 *
 * Return: non-zero if we exceed the PAGE_SIZE limit.
 */

1319
static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
1320 1321 1322 1323
				    struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t *const batch,
				    uint32_t *offset)
{
1324
	uint32_t scratch_addr;
1325 1326
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1327
	/* WaDisableCtxRestoreArbitration:bdw,chv */
1328
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1329

1330
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1331 1332
	if (IS_BROADWELL(engine->dev)) {
		int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1333 1334 1335
		if (rc < 0)
			return rc;
		index = rc;
1336 1337
	}

1338 1339
	/* WaClearSlmSpaceAtContextSwitch:bdw,chv */
	/* Actual scratch location is at 128 bytes offset */
1340
	scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1341

1342 1343 1344 1345 1346 1347 1348 1349 1350
	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
				   PIPE_CONTROL_GLOBAL_GTT_IVB |
				   PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_QW_WRITE));
	wa_ctx_emit(batch, index, scratch_addr);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
1351

1352 1353
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
1354
		wa_ctx_emit(batch, index, MI_NOOP);
1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371

	/*
	 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
	 * execution depends on the length specified in terms of cache lines
	 * in the register CTX_RCS_INDIRECT_CTX
	 */

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

/**
 * gen8_init_perctx_bb() - initialize per ctx batch with WA
 *
 * @ring: only applicable for RCS
 * @wa_ctx: structure representing wa_ctx
 *  offset: specifies start of the batch, should be cache-aligned.
 *  size: size of the batch in DWORDS but HW expects in terms of cachelines
1372
 * @batch: page in which WA are loaded
1373 1374 1375 1376 1377 1378 1379 1380 1381
 * @offset: This field specifies the start of this batch.
 *   This batch is started immediately after indirect_ctx batch. Since we ensure
 *   that indirect_ctx ends on a cacheline this batch is aligned automatically.
 *
 *   The number of DWORDS written are returned using this field.
 *
 *  This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
 *  to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
 */
1382
static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1383 1384 1385 1386 1387 1388
			       struct i915_wa_ctx_bb *wa_ctx,
			       uint32_t *const batch,
			       uint32_t *offset)
{
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1389
	/* WaDisableCtxRestoreArbitration:bdw,chv */
1390
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1391

1392
	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1393 1394 1395 1396

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1397
static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1398 1399 1400 1401
				    struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t *const batch,
				    uint32_t *offset)
{
1402
	int ret;
1403
	struct drm_device *dev = engine->dev;
1404 1405
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1406
	/* WaDisableCtxRestoreArbitration:skl,bxt */
1407
	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
T
Tim Gore 已提交
1408
	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1409
		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1410

1411
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1412
	ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1413 1414 1415 1416
	if (ret < 0)
		return ret;
	index = ret;

1417 1418 1419 1420 1421 1422 1423
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
		wa_ctx_emit(batch, index, MI_NOOP);

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

1424
static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1425 1426 1427 1428
			       struct i915_wa_ctx_bb *wa_ctx,
			       uint32_t *const batch,
			       uint32_t *offset)
{
1429
	struct drm_device *dev = engine->dev;
1430 1431
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1432
	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1433
	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
T
Tim Gore 已提交
1434
	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1435
		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
V
Ville Syrjälä 已提交
1436
		wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1437 1438 1439 1440 1441
		wa_ctx_emit(batch, index,
			    _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
		wa_ctx_emit(batch, index, MI_NOOP);
	}

1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460
	/* WaClearTdlStateAckDirtyBits:bxt */
	if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));

		wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));

		wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1);
		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));

		wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2);
		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));

		wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2);
		/* dummy write to CS, mask bits are 0 to ensure the register is not modified */
		wa_ctx_emit(batch, index, 0x0);
		wa_ctx_emit(batch, index, MI_NOOP);
	}

1461
	/* WaDisableCtxRestoreArbitration:skl,bxt */
1462
	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
T
Tim Gore 已提交
1463
	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1464 1465
		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);

1466 1467 1468 1469 1470
	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1471
static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1472 1473 1474
{
	int ret;

1475
	engine->wa_ctx.obj = i915_gem_object_create(engine->dev,
1476
						   PAGE_ALIGN(size));
1477
	if (IS_ERR(engine->wa_ctx.obj)) {
1478
		DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1479 1480 1481
		ret = PTR_ERR(engine->wa_ctx.obj);
		engine->wa_ctx.obj = NULL;
		return ret;
1482 1483
	}

1484
	ret = i915_gem_obj_ggtt_pin(engine->wa_ctx.obj, PAGE_SIZE, 0);
1485 1486 1487
	if (ret) {
		DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
				 ret);
1488
		drm_gem_object_unreference(&engine->wa_ctx.obj->base);
1489 1490 1491 1492 1493 1494
		return ret;
	}

	return 0;
}

1495
static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1496
{
1497 1498 1499 1500
	if (engine->wa_ctx.obj) {
		i915_gem_object_ggtt_unpin(engine->wa_ctx.obj);
		drm_gem_object_unreference(&engine->wa_ctx.obj->base);
		engine->wa_ctx.obj = NULL;
1501 1502 1503
	}
}

1504
static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1505 1506 1507 1508 1509
{
	int ret;
	uint32_t *batch;
	uint32_t offset;
	struct page *page;
1510
	struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1511

1512
	WARN_ON(engine->id != RCS);
1513

1514
	/* update this when WA for higher Gen are added */
1515
	if (INTEL_INFO(engine->dev)->gen > 9) {
1516
		DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1517
			  INTEL_INFO(engine->dev)->gen);
1518
		return 0;
1519
	}
1520

1521
	/* some WA perform writes to scratch page, ensure it is valid */
1522 1523
	if (engine->scratch.obj == NULL) {
		DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1524 1525 1526
		return -EINVAL;
	}

1527
	ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1528 1529 1530 1531 1532
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
		return ret;
	}

1533
	page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0);
1534 1535 1536
	batch = kmap_atomic(page);
	offset = 0;

1537 1538
	if (INTEL_INFO(engine->dev)->gen == 8) {
		ret = gen8_init_indirectctx_bb(engine,
1539 1540 1541 1542 1543 1544
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

1545
		ret = gen8_init_perctx_bb(engine,
1546 1547 1548 1549 1550
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1551 1552
	} else if (INTEL_INFO(engine->dev)->gen == 9) {
		ret = gen9_init_indirectctx_bb(engine,
1553 1554 1555 1556 1557 1558
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

1559
		ret = gen9_init_perctx_bb(engine,
1560 1561 1562 1563 1564
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1565 1566 1567 1568 1569
	}

out:
	kunmap_atomic(batch);
	if (ret)
1570
		lrc_destroy_wa_ctx_obj(engine);
1571 1572 1573 1574

	return ret;
}

1575 1576 1577 1578 1579 1580 1581 1582 1583
static void lrc_init_hws(struct intel_engine_cs *engine)
{
	struct drm_i915_private *dev_priv = engine->dev->dev_private;

	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
		   (u32)engine->status_page.gfx_addr);
	POSTING_READ(RING_HWS_PGA(engine->mmio_base));
}

1584
static int gen8_init_common_ring(struct intel_engine_cs *engine)
1585
{
1586
	struct drm_device *dev = engine->dev;
1587
	struct drm_i915_private *dev_priv = dev->dev_private;
1588
	unsigned int next_context_status_buffer_hw;
1589

1590
	lrc_init_hws(engine);
1591

1592 1593 1594
	I915_WRITE_IMR(engine,
		       ~(engine->irq_enable_mask | engine->irq_keep_mask));
	I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1595

1596
	I915_WRITE(RING_MODE_GEN7(engine),
1597 1598
		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1599
	POSTING_READ(RING_MODE_GEN7(engine));
1600 1601 1602 1603 1604 1605 1606 1607 1608 1609

	/*
	 * Instead of resetting the Context Status Buffer (CSB) read pointer to
	 * zero, we need to read the write pointer from hardware and use its
	 * value because "this register is power context save restored".
	 * Effectively, these states have been observed:
	 *
	 *      | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
	 * BDW  | CSB regs not reset       | CSB regs reset       |
	 * CHT  | CSB regs not reset       | CSB regs not reset   |
1610 1611
	 * SKL  |         ?                |         ?            |
	 * BXT  |         ?                |         ?            |
1612
	 */
1613
	next_context_status_buffer_hw =
1614
		GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine)));
1615 1616 1617 1618 1619 1620 1621 1622 1623

	/*
	 * When the CSB registers are reset (also after power-up / gpu reset),
	 * CSB write pointer is set to all 1's, which is not valid, use '5' in
	 * this special case, so the first element read is CSB[0].
	 */
	if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
		next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);

1624 1625
	engine->next_context_status_buffer = next_context_status_buffer_hw;
	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1626

1627
	intel_engine_init_hangcheck(engine);
1628

1629
	return intel_mocs_init_engine(engine);
1630 1631
}

1632
static int gen8_init_render_ring(struct intel_engine_cs *engine)
1633
{
1634
	struct drm_device *dev = engine->dev;
1635 1636 1637
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

1638
	ret = gen8_init_common_ring(engine);
1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651
	if (ret)
		return ret;

	/* We need to disable the AsyncFlip performance optimisations in order
	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
	 * programmed to '1' on all products.
	 *
	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
	 */
	I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));

	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));

1652
	return init_workarounds_ring(engine);
1653 1654
}

1655
static int gen9_init_render_ring(struct intel_engine_cs *engine)
1656 1657 1658
{
	int ret;

1659
	ret = gen8_init_common_ring(engine);
1660 1661 1662
	if (ret)
		return ret;

1663
	return init_workarounds_ring(engine);
1664 1665
}

1666 1667 1668
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
	struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1669
	struct intel_engine_cs *engine = req->engine;
1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681
	struct intel_ringbuffer *ringbuf = req->ringbuf;
	const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
	int i, ret;

	ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
	if (ret)
		return ret;

	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);

1682 1683
		intel_logical_ring_emit_reg(ringbuf,
					    GEN8_RING_PDP_UDW(engine, i));
1684
		intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1685 1686
		intel_logical_ring_emit_reg(ringbuf,
					    GEN8_RING_PDP_LDW(engine, i));
1687 1688 1689 1690 1691 1692 1693 1694 1695
		intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
	}

	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1696
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1697
			      u64 offset, unsigned dispatch_flags)
1698
{
1699
	struct intel_ringbuffer *ringbuf = req->ringbuf;
1700
	bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1701 1702
	int ret;

1703 1704 1705 1706
	/* Don't rely in hw updating PDPs, specially in lite-restore.
	 * Ideally, we should set Force PD Restore in ctx descriptor,
	 * but we can't. Force Restore would be a second option, but
	 * it is unsafe in case of lite-restore (because the ctx is
1707 1708
	 * not idle). PML4 is allocated during ppgtt init so this is
	 * not needed in 48-bit.*/
1709
	if (req->ctx->ppgtt &&
1710
	    (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1711 1712
		if (!USES_FULL_48BIT_PPGTT(req->i915) &&
		    !intel_vgpu_active(req->i915->dev)) {
1713 1714 1715 1716
			ret = intel_logical_ring_emit_pdps(req);
			if (ret)
				return ret;
		}
1717

1718
		req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1719 1720
	}

1721
	ret = intel_logical_ring_begin(req, 4);
1722 1723 1724 1725
	if (ret)
		return ret;

	/* FIXME(BDW): Address space and security selectors. */
1726 1727 1728 1729
	intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
				(ppgtt<<8) |
				(dispatch_flags & I915_DISPATCH_RS ?
				 MI_BATCH_RESOURCE_STREAMER : 0));
1730 1731 1732 1733 1734 1735 1736 1737
	intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
	intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1738
static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
1739
{
1740
	struct drm_device *dev = engine->dev;
1741 1742 1743
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long flags;

1744
	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1745 1746 1747
		return false;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
1748 1749 1750 1751
	if (engine->irq_refcount++ == 0) {
		I915_WRITE_IMR(engine,
			       ~(engine->irq_enable_mask | engine->irq_keep_mask));
		POSTING_READ(RING_IMR(engine->mmio_base));
1752 1753 1754 1755 1756 1757
	}
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	return true;
}

1758
static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
1759
{
1760
	struct drm_device *dev = engine->dev;
1761 1762 1763 1764
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
1765 1766 1767
	if (--engine->irq_refcount == 0) {
		I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
		POSTING_READ(RING_IMR(engine->mmio_base));
1768 1769 1770 1771
	}
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
}

1772
static int gen8_emit_flush(struct drm_i915_gem_request *request,
1773 1774 1775
			   u32 invalidate_domains,
			   u32 unused)
{
1776
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1777
	struct intel_engine_cs *engine = ringbuf->engine;
1778
	struct drm_device *dev = engine->dev;
1779 1780 1781 1782
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t cmd;
	int ret;

1783
	ret = intel_logical_ring_begin(request, 4);
1784 1785 1786 1787 1788
	if (ret)
		return ret;

	cmd = MI_FLUSH_DW + 1;

1789 1790 1791 1792 1793 1794 1795 1796 1797
	/* We always require a command barrier so that subsequent
	 * commands, such as breadcrumb interrupts, are strictly ordered
	 * wrt the contents of the write cache being flushed to memory
	 * (and thus being coherent from the CPU).
	 */
	cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;

	if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
		cmd |= MI_INVALIDATE_TLB;
1798
		if (engine == &dev_priv->engine[VCS])
1799
			cmd |= MI_INVALIDATE_BSD;
1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812
	}

	intel_logical_ring_emit(ringbuf, cmd);
	intel_logical_ring_emit(ringbuf,
				I915_GEM_HWS_SCRATCH_ADDR |
				MI_FLUSH_DW_USE_GTT);
	intel_logical_ring_emit(ringbuf, 0); /* upper addr */
	intel_logical_ring_emit(ringbuf, 0); /* value */
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1813
static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1814 1815 1816
				  u32 invalidate_domains,
				  u32 flush_domains)
{
1817
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1818
	struct intel_engine_cs *engine = ringbuf->engine;
1819
	u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1820
	bool vf_flush_wa = false;
1821 1822 1823 1824 1825 1826 1827 1828
	u32 flags = 0;
	int ret;

	flags |= PIPE_CONTROL_CS_STALL;

	if (flush_domains) {
		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1829
		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1830
		flags |= PIPE_CONTROL_FLUSH_ENABLE;
1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842
	}

	if (invalidate_domains) {
		flags |= PIPE_CONTROL_TLB_INVALIDATE;
		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_QW_WRITE;
		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;

1843 1844 1845 1846
		/*
		 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
		 * pipe control.
		 */
1847
		if (IS_GEN9(engine->dev))
1848 1849
			vf_flush_wa = true;
	}
1850

1851
	ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1852 1853 1854
	if (ret)
		return ret;

1855 1856 1857 1858 1859 1860 1861 1862 1863
	if (vf_flush_wa) {
		intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
	}

1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874
	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
	intel_logical_ring_emit(ringbuf, flags);
	intel_logical_ring_emit(ringbuf, scratch_addr);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1875
static u32 gen8_get_seqno(struct intel_engine_cs *engine)
1876
{
1877
	return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1878 1879
}

1880
static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1881
{
1882
	intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1883 1884
}

1885
static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896
{
	/*
	 * On BXT A steppings there is a HW coherency issue whereby the
	 * MI_STORE_DATA_IMM storing the completed request's seqno
	 * occasionally doesn't invalidate the CPU cache. Work around this by
	 * clflushing the corresponding cacheline whenever the caller wants
	 * the coherency to be guaranteed. Note that this cacheline is known
	 * to be clean at this point, since we only write it in
	 * bxt_a_set_seqno(), where we also do a clflush after the write. So
	 * this clflush in practice becomes an invalidate operation.
	 */
1897
	intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1898 1899
}

1900
static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1901
{
1902
	intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1903 1904

	/* See bxt_a_get_seqno() explaining the reason for the clflush. */
1905
	intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1906 1907
}

1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919
/*
 * Reserve space for 2 NOOPs at the end of each request to be
 * used as a workaround for not being allowed to do lite
 * restore with HEAD==TAIL (WaIdleLiteRestore).
 */
#define WA_TAIL_DWORDS 2

static inline u32 hws_seqno_address(struct intel_engine_cs *engine)
{
	return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR;
}

1920
static int gen8_emit_request(struct drm_i915_gem_request *request)
1921
{
1922
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1923 1924
	int ret;

1925
	ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
1926 1927 1928
	if (ret)
		return ret;

1929 1930
	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
	BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1931 1932

	intel_logical_ring_emit(ringbuf,
1933 1934
				(MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
	intel_logical_ring_emit(ringbuf,
1935
				hws_seqno_address(request->engine) |
1936
				MI_FLUSH_DW_USE_GTT);
1937
	intel_logical_ring_emit(ringbuf, 0);
1938
	intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1939 1940
	intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
	intel_logical_ring_emit(ringbuf, MI_NOOP);
1941 1942
	return intel_logical_ring_advance_and_submit(request);
}
1943

1944 1945 1946 1947
static int gen8_emit_request_render(struct drm_i915_gem_request *request)
{
	struct intel_ringbuffer *ringbuf = request->ringbuf;
	int ret;
1948

1949
	ret = intel_logical_ring_begin(request, 8 + WA_TAIL_DWORDS);
1950 1951 1952
	if (ret)
		return ret;

1953 1954 1955
	/* We're using qword write, seqno should be aligned to 8 bytes. */
	BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);

1956 1957 1958 1959
	/* w/a for post sync ops following a GPGPU operation we
	 * need a prior CS_STALL, which is emitted by the flush
	 * following the batch.
	 */
1960
	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1961 1962 1963 1964
	intel_logical_ring_emit(ringbuf,
				(PIPE_CONTROL_GLOBAL_GTT_IVB |
				 PIPE_CONTROL_CS_STALL |
				 PIPE_CONTROL_QW_WRITE));
1965
	intel_logical_ring_emit(ringbuf, hws_seqno_address(request->engine));
1966 1967
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1968 1969
	/* We're thrashing one dword of HWS. */
	intel_logical_ring_emit(ringbuf, 0);
1970
	intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1971
	intel_logical_ring_emit(ringbuf, MI_NOOP);
1972
	return intel_logical_ring_advance_and_submit(request);
1973 1974
}

1975
static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1976 1977 1978 1979
{
	struct render_state so;
	int ret;

1980
	ret = i915_gem_render_state_prepare(req->engine, &so);
1981 1982 1983 1984 1985 1986
	if (ret)
		return ret;

	if (so.rodata == NULL)
		return 0;

1987
	ret = req->engine->emit_bb_start(req, so.ggtt_offset,
1988
				       I915_DISPATCH_SECURE);
1989 1990 1991
	if (ret)
		goto out;

1992
	ret = req->engine->emit_bb_start(req,
1993 1994 1995 1996 1997
				       (so.ggtt_offset + so.aux_batch_offset),
				       I915_DISPATCH_SECURE);
	if (ret)
		goto out;

1998
	i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1999 2000 2001 2002 2003 2004

out:
	i915_gem_render_state_fini(&so);
	return ret;
}

2005
static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
2006 2007 2008
{
	int ret;

2009
	ret = intel_logical_ring_workarounds_emit(req);
2010 2011 2012
	if (ret)
		return ret;

2013 2014 2015 2016 2017 2018 2019 2020
	ret = intel_rcs_context_init_mocs(req);
	/*
	 * Failing to program the MOCS is non-fatal.The system will not
	 * run at peak performance. So generate an error and carry on.
	 */
	if (ret)
		DRM_ERROR("MOCS failed to program: expect performance issues.\n");

2021
	return intel_lr_context_render_state_init(req);
2022 2023
}

2024 2025 2026 2027 2028 2029
/**
 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
 *
 * @ring: Engine Command Streamer.
 *
 */
2030
void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
2031
{
2032
	struct drm_i915_private *dev_priv;
2033

2034
	if (!intel_engine_initialized(engine))
2035 2036
		return;

2037 2038 2039 2040 2041 2042 2043
	/*
	 * Tasklet cannot be active at this point due intel_mark_active/idle
	 * so this is just for documentation.
	 */
	if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
		tasklet_kill(&engine->irq_tasklet);

2044
	dev_priv = engine->dev->dev_private;
2045

2046 2047 2048
	if (engine->buffer) {
		intel_logical_ring_stop(engine);
		WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
2049
	}
2050

2051 2052
	if (engine->cleanup)
		engine->cleanup(engine);
2053

2054 2055
	i915_cmd_parser_fini_ring(engine);
	i915_gem_batch_pool_fini(&engine->batch_pool);
2056

2057
	if (engine->status_page.obj) {
2058
		i915_gem_object_unpin_map(engine->status_page.obj);
2059
		engine->status_page.obj = NULL;
2060
	}
2061

2062 2063 2064
	engine->idle_lite_restore_wa = 0;
	engine->disable_lite_restore_wa = false;
	engine->ctx_desc_template = 0;
2065

2066 2067
	lrc_destroy_wa_ctx_obj(engine);
	engine->dev = NULL;
2068 2069
}

2070 2071
static void
logical_ring_default_vfuncs(struct drm_device *dev,
2072
			    struct intel_engine_cs *engine)
2073 2074
{
	/* Default vfuncs which can be overriden by each engine. */
2075 2076 2077 2078 2079 2080
	engine->init_hw = gen8_init_common_ring;
	engine->emit_request = gen8_emit_request;
	engine->emit_flush = gen8_emit_flush;
	engine->irq_get = gen8_logical_ring_get_irq;
	engine->irq_put = gen8_logical_ring_put_irq;
	engine->emit_bb_start = gen8_emit_bb_start;
2081 2082
	engine->get_seqno = gen8_get_seqno;
	engine->set_seqno = gen8_set_seqno;
2083
	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2084
		engine->irq_seqno_barrier = bxt_a_seqno_barrier;
2085
		engine->set_seqno = bxt_a_set_seqno;
2086 2087 2088
	}
}

2089
static inline void
2090
logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
2091
{
2092 2093
	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2094 2095
}

2096
static int
2097 2098 2099
lrc_setup_hws(struct intel_engine_cs *engine,
	      struct drm_i915_gem_object *dctx_obj)
{
2100
	void *hws;
2101 2102 2103 2104

	/* The HWSP is part of the default context object in LRC mode. */
	engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj) +
				       LRC_PPHWSP_PN * PAGE_SIZE;
2105 2106 2107 2108
	hws = i915_gem_object_pin_map(dctx_obj);
	if (IS_ERR(hws))
		return PTR_ERR(hws);
	engine->status_page.page_addr = hws + LRC_PPHWSP_PN * PAGE_SIZE;
2109
	engine->status_page.obj = dctx_obj;
2110 2111

	return 0;
2112 2113
}

2114
static int
2115
logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
2116
{
2117 2118 2119
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_context *dctx = dev_priv->kernel_context;
	enum forcewake_domains fw_domains;
2120 2121 2122
	int ret;

	/* Intentionally left blank. */
2123
	engine->buffer = NULL;
2124

2125 2126 2127 2128 2129
	engine->dev = dev;
	INIT_LIST_HEAD(&engine->active_list);
	INIT_LIST_HEAD(&engine->request_list);
	i915_gem_batch_pool_init(dev, &engine->batch_pool);
	init_waitqueue_head(&engine->irq_queue);
2130

2131 2132 2133 2134
	INIT_LIST_HEAD(&engine->buffers);
	INIT_LIST_HEAD(&engine->execlist_queue);
	INIT_LIST_HEAD(&engine->execlist_retired_req_list);
	spin_lock_init(&engine->execlist_lock);
2135

2136 2137 2138
	tasklet_init(&engine->irq_tasklet,
		     intel_lrc_irq_handler, (unsigned long)engine);

2139
	logical_ring_init_platform_invariants(engine);
2140

2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154
	fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
						    RING_ELSP(engine),
						    FW_REG_WRITE);

	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
						     RING_CONTEXT_STATUS_PTR(engine),
						     FW_REG_READ | FW_REG_WRITE);

	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
						     RING_CONTEXT_STATUS_BUF_BASE(engine),
						     FW_REG_READ);

	engine->fw_domains = fw_domains;

2155
	ret = i915_cmd_parser_init_ring(engine);
2156
	if (ret)
2157
		goto error;
2158

2159
	ret = intel_lr_context_deferred_alloc(dctx, engine);
2160
	if (ret)
2161
		goto error;
2162 2163

	/* As this is the default context, always pin it */
2164
	ret = intel_lr_context_do_pin(dctx, engine);
2165 2166 2167
	if (ret) {
		DRM_ERROR(
			"Failed to pin and map ringbuffer %s: %d\n",
2168
			engine->name, ret);
2169
		goto error;
2170
	}
2171

2172
	/* And setup the hardware status page. */
2173 2174 2175 2176 2177
	ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
	if (ret) {
		DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
		goto error;
	}
2178

2179 2180 2181
	return 0;

error:
2182
	intel_logical_ring_cleanup(engine);
2183
	return ret;
2184 2185 2186 2187 2188
}

static int logical_render_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2189
	struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2190
	int ret;
2191

2192 2193 2194 2195 2196
	engine->name = "render ring";
	engine->id = RCS;
	engine->exec_id = I915_EXEC_RENDER;
	engine->guc_id = GUC_RENDER_ENGINE;
	engine->mmio_base = RENDER_RING_BASE;
2197

2198
	logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT);
2199
	if (HAS_L3_DPF(dev))
2200
		engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2201

2202
	logical_ring_default_vfuncs(dev, engine);
2203 2204

	/* Override some for render ring. */
2205
	if (INTEL_INFO(dev)->gen >= 9)
2206
		engine->init_hw = gen9_init_render_ring;
2207
	else
2208 2209 2210 2211 2212
		engine->init_hw = gen8_init_render_ring;
	engine->init_context = gen8_init_rcs_context;
	engine->cleanup = intel_fini_pipe_control;
	engine->emit_flush = gen8_emit_flush_render;
	engine->emit_request = gen8_emit_request_render;
2213

2214
	engine->dev = dev;
2215

2216
	ret = intel_init_pipe_control(engine);
2217 2218 2219
	if (ret)
		return ret;

2220
	ret = intel_init_workaround_bb(engine);
2221 2222 2223 2224 2225 2226 2227 2228 2229 2230
	if (ret) {
		/*
		 * We continue even if we fail to initialize WA batch
		 * because we only expect rare glitches but nothing
		 * critical to prevent us from using GPU
		 */
		DRM_ERROR("WA batch buffer initialization failed: %d\n",
			  ret);
	}

2231
	ret = logical_ring_init(dev, engine);
2232
	if (ret) {
2233
		lrc_destroy_wa_ctx_obj(engine);
2234
	}
2235 2236

	return ret;
2237 2238 2239 2240 2241
}

static int logical_bsd_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2242
	struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2243

2244 2245 2246 2247 2248
	engine->name = "bsd ring";
	engine->id = VCS;
	engine->exec_id = I915_EXEC_BSD;
	engine->guc_id = GUC_VIDEO_ENGINE;
	engine->mmio_base = GEN6_BSD_RING_BASE;
2249

2250 2251
	logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT);
	logical_ring_default_vfuncs(dev, engine);
2252

2253
	return logical_ring_init(dev, engine);
2254 2255 2256 2257 2258
}

static int logical_bsd2_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2259
	struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2260

2261 2262 2263 2264 2265
	engine->name = "bsd2 ring";
	engine->id = VCS2;
	engine->exec_id = I915_EXEC_BSD;
	engine->guc_id = GUC_VIDEO_ENGINE2;
	engine->mmio_base = GEN8_BSD2_RING_BASE;
2266

2267 2268
	logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT);
	logical_ring_default_vfuncs(dev, engine);
2269

2270
	return logical_ring_init(dev, engine);
2271 2272 2273 2274 2275
}

static int logical_blt_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2276
	struct intel_engine_cs *engine = &dev_priv->engine[BCS];
2277

2278 2279 2280 2281 2282
	engine->name = "blitter ring";
	engine->id = BCS;
	engine->exec_id = I915_EXEC_BLT;
	engine->guc_id = GUC_BLITTER_ENGINE;
	engine->mmio_base = BLT_RING_BASE;
2283

2284 2285
	logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT);
	logical_ring_default_vfuncs(dev, engine);
2286

2287
	return logical_ring_init(dev, engine);
2288 2289 2290 2291 2292
}

static int logical_vebox_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2293
	struct intel_engine_cs *engine = &dev_priv->engine[VECS];
2294

2295 2296 2297 2298 2299
	engine->name = "video enhancement ring";
	engine->id = VECS;
	engine->exec_id = I915_EXEC_VEBOX;
	engine->guc_id = GUC_VIDEOENHANCE_ENGINE;
	engine->mmio_base = VEBOX_RING_BASE;
2300

2301 2302
	logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT);
	logical_ring_default_vfuncs(dev, engine);
2303

2304
	return logical_ring_init(dev, engine);
2305 2306
}

2307 2308 2309 2310 2311
/**
 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
 * @dev: DRM device.
 *
 * This function inits the engines for an Execlists submission style (the equivalent in the
2312
 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2313 2314 2315 2316
 * those engines that are present in the hardware.
 *
 * Return: non-zero if the initialization failed.
 */
2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352
int intel_logical_rings_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = logical_render_ring_init(dev);
	if (ret)
		return ret;

	if (HAS_BSD(dev)) {
		ret = logical_bsd_ring_init(dev);
		if (ret)
			goto cleanup_render_ring;
	}

	if (HAS_BLT(dev)) {
		ret = logical_blt_ring_init(dev);
		if (ret)
			goto cleanup_bsd_ring;
	}

	if (HAS_VEBOX(dev)) {
		ret = logical_vebox_ring_init(dev);
		if (ret)
			goto cleanup_blt_ring;
	}

	if (HAS_BSD2(dev)) {
		ret = logical_bsd2_ring_init(dev);
		if (ret)
			goto cleanup_vebox_ring;
	}

	return 0;

cleanup_vebox_ring:
2353
	intel_logical_ring_cleanup(&dev_priv->engine[VECS]);
2354
cleanup_blt_ring:
2355
	intel_logical_ring_cleanup(&dev_priv->engine[BCS]);
2356
cleanup_bsd_ring:
2357
	intel_logical_ring_cleanup(&dev_priv->engine[VCS]);
2358
cleanup_render_ring:
2359
	intel_logical_ring_cleanup(&dev_priv->engine[RCS]);
2360 2361 2362 2363

	return ret;
}

2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406
static u32
make_rpcs(struct drm_device *dev)
{
	u32 rpcs = 0;

	/*
	 * No explicit RPCS request is needed to ensure full
	 * slice/subslice/EU enablement prior to Gen9.
	*/
	if (INTEL_INFO(dev)->gen < 9)
		return 0;

	/*
	 * Starting in Gen9, render power gating can leave
	 * slice/subslice/EU in a partially enabled state. We
	 * must make an explicit request through RPCS for full
	 * enablement.
	*/
	if (INTEL_INFO(dev)->has_slice_pg) {
		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
		rpcs |= INTEL_INFO(dev)->slice_total <<
			GEN8_RPCS_S_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	if (INTEL_INFO(dev)->has_subslice_pg) {
		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
		rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
			GEN8_RPCS_SS_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	if (INTEL_INFO(dev)->has_eu_pg) {
		rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
			GEN8_RPCS_EU_MIN_SHIFT;
		rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
			GEN8_RPCS_EU_MAX_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	return rpcs;
}

2407
static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2408 2409 2410
{
	u32 indirect_ctx_offset;

2411
	switch (INTEL_INFO(engine->dev)->gen) {
2412
	default:
2413
		MISSING_CASE(INTEL_INFO(engine->dev)->gen);
2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427
		/* fall through */
	case 9:
		indirect_ctx_offset =
			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
		break;
	case 8:
		indirect_ctx_offset =
			GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
		break;
	}

	return indirect_ctx_offset;
}

2428
static int
2429 2430
populate_lr_context(struct intel_context *ctx,
		    struct drm_i915_gem_object *ctx_obj,
2431 2432
		    struct intel_engine_cs *engine,
		    struct intel_ringbuffer *ringbuf)
2433
{
2434
	struct drm_device *dev = engine->dev;
2435
	struct drm_i915_private *dev_priv = dev->dev_private;
2436
	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2437 2438
	void *vaddr;
	u32 *reg_state;
2439 2440
	int ret;

2441 2442 2443
	if (!ppgtt)
		ppgtt = dev_priv->mm.aliasing_ppgtt;

2444 2445 2446 2447 2448 2449
	ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
	if (ret) {
		DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
		return ret;
	}

2450 2451 2452 2453
	vaddr = i915_gem_object_pin_map(ctx_obj);
	if (IS_ERR(vaddr)) {
		ret = PTR_ERR(vaddr);
		DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2454 2455
		return ret;
	}
2456
	ctx_obj->dirty = true;
2457 2458 2459

	/* The second page of the context object contains some fields which must
	 * be set up prior to the first execution. */
2460
	reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
2461 2462 2463 2464 2465 2466

	/* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
	 * commands followed by (reg, value) pairs. The values we are setting here are
	 * only for the first context restore: on a subsequent save, the GPU will
	 * recreate this batchbuffer with new values (including all the missing
	 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2467
	reg_state[CTX_LRI_HEADER_0] =
2468 2469 2470
		MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
	ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
		       RING_CONTEXT_CONTROL(engine),
2471 2472
		       _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
					  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2473 2474
					  (HAS_RESOURCE_STREAMER(dev) ?
					    CTX_CTRL_RS_CTX_ENABLE : 0)));
2475 2476 2477 2478
	ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
		       0);
2479 2480 2481
	/* Ring buffer start address is not known until the buffer is pinned.
	 * It is written to the context image in execlists_update_context()
	 */
2482 2483 2484 2485
	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
		       RING_START(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
		       RING_CTL(engine->mmio_base),
2486
		       ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
2487 2488 2489 2490 2491 2492
	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
		       RING_BBADDR_UDW(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
		       RING_BBADDR(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
		       RING_BBSTATE(engine->mmio_base),
2493
		       RING_BB_PPGTT);
2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
		       RING_SBBADDR_UDW(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
		       RING_SBBADDR(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
		       RING_SBBSTATE(engine->mmio_base), 0);
	if (engine->id == RCS) {
		ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
			       RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
			       RING_INDIRECT_CTX(engine->mmio_base), 0);
		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
			       RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
		if (engine->wa_ctx.obj) {
			struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2509 2510 2511 2512 2513 2514 2515
			uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);

			reg_state[CTX_RCS_INDIRECT_CTX+1] =
				(ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
				(wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);

			reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2516
				intel_lr_indirect_ctx_offset(engine) << 6;
2517 2518 2519 2520 2521

			reg_state[CTX_BB_PER_CTX_PTR+1] =
				(ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
				0x01;
		}
2522
	}
2523
	reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2524 2525
	ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
		       RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2526
	/* PDP values well be assigned later if needed */
2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542
	ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
		       0);
2543

2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555
	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
		/* 64b PPGTT (48bit canonical)
		 * PDP0_DESCRIPTOR contains the base address to PML4 and
		 * other PDP Descriptors are ignored.
		 */
		ASSIGN_CTX_PML4(ppgtt, reg_state);
	} else {
		/* 32b PPGTT
		 * PDP*_DESCRIPTOR contains the base address of space supported.
		 * With dynamic page allocation, PDPs may not be allocated at
		 * this point. Point the unallocated PDPs to the scratch page
		 */
2556
		execlists_update_context_pdps(ppgtt, reg_state);
2557 2558
	}

2559
	if (engine->id == RCS) {
2560
		reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2561 2562
		ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
			       make_rpcs(dev));
2563 2564
	}

2565
	i915_gem_object_unpin_map(ctx_obj);
2566 2567 2568 2569

	return 0;
}

2570 2571 2572 2573 2574 2575 2576 2577
/**
 * intel_lr_context_free() - free the LRC specific bits of a context
 * @ctx: the LR context to free.
 *
 * The real context freeing is done in i915_gem_context_free: this only
 * takes care of the bits that are LRC related: the per-engine backing
 * objects and the logical ringbuffer.
 */
2578 2579
void intel_lr_context_free(struct intel_context *ctx)
{
2580 2581
	int i;

2582
	for (i = I915_NUM_ENGINES; --i >= 0; ) {
D
Dave Gordon 已提交
2583
		struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
2584
		struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2585

D
Dave Gordon 已提交
2586 2587
		if (!ctx_obj)
			continue;
2588

D
Dave Gordon 已提交
2589 2590 2591
		if (ctx == ctx->i915->kernel_context) {
			intel_unpin_ringbuffer_obj(ringbuf);
			i915_gem_object_ggtt_unpin(ctx_obj);
2592
			i915_gem_object_unpin_map(ctx_obj);
2593
		}
D
Dave Gordon 已提交
2594 2595 2596 2597

		WARN_ON(ctx->engine[i].pin_count);
		intel_ringbuffer_free(ringbuf);
		drm_gem_object_unreference(&ctx_obj->base);
2598 2599 2600
	}
}

2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614
/**
 * intel_lr_context_size() - return the size of the context for an engine
 * @ring: which engine to find the context size for
 *
 * Each engine may require a different amount of space for a context image,
 * so when allocating (or copying) an image, this function can be used to
 * find the right size for the specific engine.
 *
 * Return: size (in bytes) of an engine-specific context image
 *
 * Note: this size includes the HWSP, which is part of the context image
 * in LRC mode, but does not include the "shared data page" used with
 * GuC submission. The caller should account for this if using the GuC.
 */
2615
uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2616 2617 2618
{
	int ret = 0;

2619
	WARN_ON(INTEL_INFO(engine->dev)->gen < 8);
2620

2621
	switch (engine->id) {
2622
	case RCS:
2623
		if (INTEL_INFO(engine->dev)->gen >= 9)
2624 2625 2626
			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
		else
			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2627 2628 2629 2630 2631 2632 2633 2634 2635 2636
		break;
	case VCS:
	case BCS:
	case VECS:
	case VCS2:
		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
		break;
	}

	return ret;
2637 2638
}

2639
/**
2640
 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2641 2642 2643 2644 2645 2646 2647 2648 2649
 * @ctx: LR context to create.
 * @ring: engine to be used with the context.
 *
 * This function can be called more than once, with different engines, if we plan
 * to use the context with them. The context backing objects and the ringbuffers
 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
 * the creation is a deferred call: it's better to make sure first that we need to use
 * a given ring with the context.
 *
2650
 * Return: non-zero on error.
2651
 */
2652 2653

int intel_lr_context_deferred_alloc(struct intel_context *ctx,
2654
				    struct intel_engine_cs *engine)
2655
{
2656
	struct drm_device *dev = engine->dev;
2657 2658
	struct drm_i915_gem_object *ctx_obj;
	uint32_t context_size;
2659
	struct intel_ringbuffer *ringbuf;
2660 2661
	int ret;

2662
	WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2663
	WARN_ON(ctx->engine[engine->id].state);
2664

2665
	context_size = round_up(intel_lr_context_size(engine), 4096);
2666

2667 2668 2669
	/* One extra page as the sharing data between driver and GuC */
	context_size += PAGE_SIZE * LRC_PPHWSP_PN;

2670
	ctx_obj = i915_gem_object_create(dev, context_size);
2671
	if (IS_ERR(ctx_obj)) {
2672
		DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2673
		return PTR_ERR(ctx_obj);
2674 2675
	}

2676
	ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE);
2677 2678
	if (IS_ERR(ringbuf)) {
		ret = PTR_ERR(ringbuf);
2679
		goto error_deref_obj;
2680 2681
	}

2682
	ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf);
2683 2684
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2685
		goto error_ringbuf;
2686 2687
	}

2688 2689
	ctx->engine[engine->id].ringbuf = ringbuf;
	ctx->engine[engine->id].state = ctx_obj;
2690

2691
	if (ctx != ctx->i915->kernel_context && engine->init_context) {
2692
		struct drm_i915_gem_request *req;
2693

2694
		req = i915_gem_request_alloc(engine, ctx);
2695 2696 2697
		if (IS_ERR(req)) {
			ret = PTR_ERR(req);
			DRM_ERROR("ring create req: %d\n", ret);
2698
			goto error_ringbuf;
2699 2700
		}

2701
		ret = engine->init_context(req);
2702
		i915_add_request_no_flush(req);
2703 2704 2705 2706 2707
		if (ret) {
			DRM_ERROR("ring init context: %d\n",
				ret);
			goto error_ringbuf;
		}
2708
	}
2709
	return 0;
2710

2711 2712
error_ringbuf:
	intel_ringbuffer_free(ringbuf);
2713
error_deref_obj:
2714
	drm_gem_object_unreference(&ctx_obj->base);
2715 2716
	ctx->engine[engine->id].ringbuf = NULL;
	ctx->engine[engine->id].state = NULL;
2717
	return ret;
2718
}
2719

2720 2721
void intel_lr_context_reset(struct drm_i915_private *dev_priv,
			    struct intel_context *ctx)
2722
{
2723
	struct intel_engine_cs *engine;
2724

2725
	for_each_engine(engine, dev_priv) {
2726
		struct drm_i915_gem_object *ctx_obj =
2727
				ctx->engine[engine->id].state;
2728
		struct intel_ringbuffer *ringbuf =
2729
				ctx->engine[engine->id].ringbuf;
2730
		void *vaddr;
2731 2732 2733 2734 2735
		uint32_t *reg_state;

		if (!ctx_obj)
			continue;

2736 2737
		vaddr = i915_gem_object_pin_map(ctx_obj);
		if (WARN_ON(IS_ERR(vaddr)))
2738
			continue;
2739 2740 2741

		reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
		ctx_obj->dirty = true;
2742 2743 2744 2745

		reg_state[CTX_RING_HEAD+1] = 0;
		reg_state[CTX_RING_TAIL+1] = 0;

2746
		i915_gem_object_unpin_map(ctx_obj);
2747 2748 2749 2750 2751

		ringbuf->head = 0;
		ringbuf->tail = 0;
	}
}