intel_lrc.c 80.9 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky <ben@bwidawsk.net>
 *    Michel Thierry <michel.thierry@intel.com>
 *    Thomas Daniel <thomas.daniel@intel.com>
 *    Oscar Mateo <oscar.mateo@intel.com>
 *
 */

31 32 33 34
/**
 * DOC: Logical Rings, Logical Ring Contexts and Execlists
 *
 * Motivation:
35 36 37 38
 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
 * These expanded contexts enable a number of new abilities, especially
 * "Execlists" (also implemented in this file).
 *
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
 * One of the main differences with the legacy HW contexts is that logical
 * ring contexts incorporate many more things to the context's state, like
 * PDPs or ringbuffer control registers:
 *
 * The reason why PDPs are included in the context is straightforward: as
 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
 * instead, the GPU will do it for you on the context switch.
 *
 * But, what about the ringbuffer control registers (head, tail, etc..)?
 * shouldn't we just need a set of those per engine command streamer? This is
 * where the name "Logical Rings" starts to make sense: by virtualizing the
 * rings, the engine cs shifts to a new "ring buffer" with every context
 * switch. When you want to submit a workload to the GPU you: A) choose your
 * context, B) find its appropriate virtualized ring, C) write commands to it
 * and then, finally, D) tell the GPU to switch to that context.
 *
 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
 * to a contexts is via a context execution list, ergo "Execlists".
 *
 * LRC implementation:
 * Regarding the creation of contexts, we have:
 *
 * - One global default context.
 * - One local default context for each opened fd.
 * - One local extra context for each context create ioctl call.
 *
 * Now that ringbuffers belong per-context (and not per-engine, like before)
 * and that contexts are uniquely tied to a given engine (and not reusable,
 * like before) we need:
 *
 * - One ringbuffer per-engine inside each context.
 * - One backing object per-engine inside each context.
 *
 * The global default context starts its life with these new objects fully
 * allocated and populated. The local default context for each opened fd is
 * more complex, because we don't know at creation time which engine is going
 * to use them. To handle this, we have implemented a deferred creation of LR
 * contexts:
 *
 * The local context starts its life as a hollow or blank holder, that only
 * gets populated for a given engine once we receive an execbuffer. If later
 * on we receive another execbuffer ioctl for the same context but a different
 * engine, we allocate/populate a new ringbuffer and context backing object and
 * so on.
 *
 * Finally, regarding local contexts created using the ioctl call: as they are
 * only allowed with the render ring, we can allocate & populate them right
 * away (no need to defer anything, at least for now).
 *
 * Execlists implementation:
90 91
 * Execlists are the new method by which, on gen8+ hardware, workloads are
 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
 * This method works as follows:
 *
 * When a request is committed, its commands (the BB start and any leading or
 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
 * for the appropriate context. The tail pointer in the hardware context is not
 * updated at this time, but instead, kept by the driver in the ringbuffer
 * structure. A structure representing this request is added to a request queue
 * for the appropriate engine: this structure contains a copy of the context's
 * tail after the request was written to the ring buffer and a pointer to the
 * context itself.
 *
 * If the engine's request queue was empty before the request was added, the
 * queue is processed immediately. Otherwise the queue will be processed during
 * a context switch interrupt. In any case, elements on the queue will get sent
 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 * globally unique 20-bits submission ID.
 *
 * When execution of a request completes, the GPU updates the context status
 * buffer with a context complete event and generates a context switch interrupt.
 * During the interrupt handling, the driver examines the events in the buffer:
 * for each context complete event, if the announced ID matches that on the head
 * of the request queue, then that request is retired and removed from the queue.
 *
 * After processing, if any requests were retired and the queue is not empty
 * then a new execution list can be submitted. The two requests at the front of
 * the queue are next to be submitted but since a context may not occur twice in
 * an execution list, if subsequent requests have the same ID as the first then
 * the two requests must be combined. This is done simply by discarding requests
 * at the head of the queue until either only one requests is left (in which case
 * we use a NULL second context) or the first two requests have unique IDs.
 *
 * By always executing the first two requests in the queue the driver ensures
 * that the GPU is kept as busy as possible. In the case where a single context
 * completes but a second context is still executing, the request for this second
 * context will be at the head of the queue when we remove the first one. This
 * request will then be resubmitted along with a new request for a different context,
 * which will cause the hardware to continue executing the second request and queue
 * the new request (the GPU detects the condition of a context getting preempted
 * with the same context and optimizes the context switch flow by not doing
 * preemption, but just sampling the new tail pointer).
 *
133 134 135 136 137
 */

#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
138
#include "intel_mocs.h"
139

140
#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 142 143
#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)

144 145 146 147 148 149 150 151 152 153 154 155 156
#define RING_EXECLIST_QFULL		(1 << 0x2)
#define RING_EXECLIST1_VALID		(1 << 0x3)
#define RING_EXECLIST0_VALID		(1 << 0x4)
#define RING_EXECLIST_ACTIVE_STATUS	(3 << 0xE)
#define RING_EXECLIST1_ACTIVE		(1 << 0x11)
#define RING_EXECLIST0_ACTIVE		(1 << 0x12)

#define GEN8_CTX_STATUS_IDLE_ACTIVE	(1 << 0)
#define GEN8_CTX_STATUS_PREEMPTED	(1 << 1)
#define GEN8_CTX_STATUS_ELEMENT_SWITCH	(1 << 2)
#define GEN8_CTX_STATUS_ACTIVE_IDLE	(1 << 3)
#define GEN8_CTX_STATUS_COMPLETE	(1 << 4)
#define GEN8_CTX_STATUS_LITE_RESTORE	(1 << 15)
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186

#define CTX_LRI_HEADER_0		0x01
#define CTX_CONTEXT_CONTROL		0x02
#define CTX_RING_HEAD			0x04
#define CTX_RING_TAIL			0x06
#define CTX_RING_BUFFER_START		0x08
#define CTX_RING_BUFFER_CONTROL		0x0a
#define CTX_BB_HEAD_U			0x0c
#define CTX_BB_HEAD_L			0x0e
#define CTX_BB_STATE			0x10
#define CTX_SECOND_BB_HEAD_U		0x12
#define CTX_SECOND_BB_HEAD_L		0x14
#define CTX_SECOND_BB_STATE		0x16
#define CTX_BB_PER_CTX_PTR		0x18
#define CTX_RCS_INDIRECT_CTX		0x1a
#define CTX_RCS_INDIRECT_CTX_OFFSET	0x1c
#define CTX_LRI_HEADER_1		0x21
#define CTX_CTX_TIMESTAMP		0x22
#define CTX_PDP3_UDW			0x24
#define CTX_PDP3_LDW			0x26
#define CTX_PDP2_UDW			0x28
#define CTX_PDP2_LDW			0x2a
#define CTX_PDP1_UDW			0x2c
#define CTX_PDP1_LDW			0x2e
#define CTX_PDP0_UDW			0x30
#define CTX_PDP0_LDW			0x32
#define CTX_LRI_HEADER_2		0x41
#define CTX_R_PWR_CLK_STATE		0x42
#define CTX_GPGPU_CSR_BASE_ADDRESS	0x44

187 188 189 190 191
#define GEN8_CTX_VALID (1<<0)
#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
#define GEN8_CTX_FORCE_RESTORE (1<<2)
#define GEN8_CTX_L3LLC_COHERENT (1<<5)
#define GEN8_CTX_PRIVILEGE (1<<8)
192

193
#define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
194
	(reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
195 196 197 198
	(reg_state)[(pos)+1] = (val); \
} while (0)

#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {		\
199
	const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n));	\
200 201
	reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
	reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
202
} while (0)
203

204
#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
205 206
	reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
	reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
207
} while (0)
208

209 210
enum {
	ADVANCED_CONTEXT = 0,
211
	LEGACY_32B_CONTEXT,
212 213 214
	ADVANCED_AD_CONTEXT,
	LEGACY_64B_CONTEXT
};
215 216 217 218
#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
#define GEN8_CTX_ADDRESSING_MODE(dev)  (USES_FULL_48BIT_PPGTT(dev) ?\
		LEGACY_64B_CONTEXT :\
		LEGACY_32B_CONTEXT)
219 220 221 222 223 224 225
enum {
	FAULT_AND_HANG = 0,
	FAULT_AND_HALT, /* Debug only */
	FAULT_AND_STREAM,
	FAULT_AND_CONTINUE /* Unsupported */
};
#define GEN8_CTX_ID_SHIFT 32
226 227
#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
228

229 230
static int intel_lr_context_pin(struct intel_context *ctx,
				struct intel_engine_cs *engine);
231 232
static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine,
					   struct drm_i915_gem_object *default_ctx_obj);
233

234

235 236 237 238 239 240
/**
 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 * @dev: DRM device.
 * @enable_execlists: value of i915.enable_execlists module parameter.
 *
 * Only certain platforms support Execlists (the prerequisites being
241
 * support for Logical Ring Contexts and Aliasing PPGTT or better).
242 243 244
 *
 * Return: 1 if Execlists is supported and has to be enabled.
 */
245 246
int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
{
247 248
	WARN_ON(i915.enable_ppgtt == -1);

249 250 251 252 253 254
	/* On platforms with execlist available, vGPU will only
	 * support execlist mode, no ring buffer mode.
	 */
	if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
		return 1;

255 256 257
	if (INTEL_INFO(dev)->gen >= 9)
		return 1;

258 259 260
	if (enable_execlists == 0)
		return 0;

261 262
	if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
	    i915.use_mmio_flip >= 0)
263 264 265 266
		return 1;

	return 0;
}
267

268
static void
269
logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
270
{
271
	struct drm_device *dev = engine->dev;
272

273
	if (IS_GEN8(dev) || IS_GEN9(dev))
274
		engine->idle_lite_restore_wa = ~0;
275

276
	engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
277
					IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
278
					(engine->id == VCS || engine->id == VCS2);
279

280 281
	engine->ctx_desc_template = GEN8_CTX_VALID;
	engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
282 283
				   GEN8_CTX_ADDRESSING_MODE_SHIFT;
	if (IS_GEN8(dev))
284 285
		engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
	engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
286 287 288 289 290 291 292

	/* TODO: WaDisableLiteRestore when we start using semaphore
	 * signalling between Command Streamers */
	/* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */

	/* WaEnableForceRestoreInCtxtDescForVCS:skl */
	/* WaEnableForceRestoreInCtxtDescForVCS:bxt */
293 294
	if (engine->disable_lite_restore_wa)
		engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
295 296
}

297
/**
298 299
 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
 * 					  descriptor for a pinned context
300
 *
301 302
 * @ctx: Context to work on
 * @ring: Engine the descriptor will be used with
303
 *
304 305 306 307 308 309 310 311 312 313
 * The context descriptor encodes various attributes of a context,
 * including its GTT address and some flags. Because it's fairly
 * expensive to calculate, we'll just do it once and cache the result,
 * which remains valid until the context is unpinned.
 *
 * This is what a descriptor looks like, from LSB to MSB:
 *    bits 0-11:    flags, GEN8_CTX_* (cached in ctx_desc_template)
 *    bits 12-31:    LRCA, GTT address of (the HWSP of) this context
 *    bits 32-51:    ctx ID, a globally unique tag (the LRCA again!)
 *    bits 52-63:    reserved, may encode the engine ID (for GuC)
314
 */
315 316
static void
intel_lr_context_descriptor_update(struct intel_context *ctx,
317
				   struct intel_engine_cs *engine)
318
{
319
	uint64_t lrca, desc;
320

321
	lrca = ctx->engine[engine->id].lrc_vma->node.start +
322
	       LRC_PPHWSP_PN * PAGE_SIZE;
323

324
	desc = engine->ctx_desc_template;			   /* bits  0-11 */
325 326
	desc |= lrca;					   /* bits 12-31 */
	desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */
327

328
	ctx->engine[engine->id].lrc_desc = desc;
329 330
}

331
uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
332
				     struct intel_engine_cs *engine)
333
{
334
	return ctx->engine[engine->id].lrc_desc;
335
}
336

337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353
/**
 * intel_execlists_ctx_id() - get the Execlists Context ID
 * @ctx: Context to get the ID for
 * @ring: Engine to get the ID for
 *
 * Do not confuse with ctx->id! Unfortunately we have a name overload
 * here: the old context ID we pass to userspace as a handler so that
 * they can refer to a context, and the new context ID we pass to the
 * ELSP so that the GPU can inform us of the context status via
 * interrupts.
 *
 * The context ID is a portion of the context descriptor, so we can
 * just extract the required part from the cached descriptor.
 *
 * Return: 20-bits globally unique context ID.
 */
u32 intel_execlists_ctx_id(struct intel_context *ctx,
354
			   struct intel_engine_cs *engine)
355
{
356
	return intel_lr_context_descriptor(ctx, engine) >> GEN8_CTX_ID_SHIFT;
357 358
}

359 360
static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
				 struct drm_i915_gem_request *rq1)
361
{
362

363
	struct intel_engine_cs *engine = rq0->engine;
364
	struct drm_device *dev = engine->dev;
365
	struct drm_i915_private *dev_priv = dev->dev_private;
366
	uint64_t desc[2];
367

368
	if (rq1) {
369
		desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
370 371 372 373
		rq1->elsp_submitted++;
	} else {
		desc[1] = 0;
	}
374

375
	desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);
376
	rq0->elsp_submitted++;
377

378
	/* You must always write both descriptors in the order below. */
379 380
	I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
	I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
381

382
	I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
383
	/* The context is automatically loaded after the following */
384
	I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
385

386
	/* ELSP is a wo register, use another nearby reg for posting */
387
	POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine));
388 389
}

390 391 392 393 394 395 396 397 398 399
static void
execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
{
	ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
}

static void execlists_update_context(struct drm_i915_gem_request *rq)
400
{
401
	struct intel_engine_cs *engine = rq->engine;
402
	struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
403
	uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
404

405
	reg_state[CTX_RING_TAIL+1] = rq->tail;
406

407 408 409 410 411 412 413
	/* True 32b PPGTT with dynamic page allocation: update PDP
	 * registers and point the unallocated PDPs to scratch page.
	 * PML4 is allocated during ppgtt init, so this is not needed
	 * in 48-bit mode.
	 */
	if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
		execlists_update_context_pdps(ppgtt, reg_state);
414 415
}

416 417
static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
				      struct drm_i915_gem_request *rq1)
418
{
419 420 421 422
	struct drm_i915_private *dev_priv = rq0->i915;

	/* BUG_ON(!irqs_disabled());  */

423
	execlists_update_context(rq0);
424

425
	if (rq1)
426
		execlists_update_context(rq1);
427

428 429 430
	spin_lock(&dev_priv->uncore.lock);
	intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);

431
	execlists_elsp_write(rq0, rq1);
432 433 434

	intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
	spin_unlock(&dev_priv->uncore.lock);
435 436
}

437
static void execlists_context_unqueue(struct intel_engine_cs *engine)
438
{
439
	struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
440
	struct drm_i915_gem_request *cursor, *tmp;
441

442
	assert_spin_locked(&engine->execlist_lock);
443

444 445 446 447
	/*
	 * If irqs are not active generate a warning as batches that finish
	 * without the irqs may get lost and a GPU Hang may occur.
	 */
448
	WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
449

450
	/* Try to read in pairs */
451
	list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
452 453 454
				 execlist_link) {
		if (!req0) {
			req0 = cursor;
455
		} else if (req0->ctx == cursor->ctx) {
456 457
			/* Same ctx: ignore first request, as second request
			 * will update tail past first request's workload */
458
			cursor->elsp_submitted = req0->elsp_submitted;
459
			list_move_tail(&req0->execlist_link,
460
				       &engine->execlist_retired_req_list);
461 462 463
			req0 = cursor;
		} else {
			req1 = cursor;
464
			WARN_ON(req1->elsp_submitted);
465 466 467 468
			break;
		}
	}

469 470 471
	if (unlikely(!req0))
		return;

472
	if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
473
		/*
474 475 476 477 478 479
		 * WaIdleLiteRestore: make sure we never cause a lite restore
		 * with HEAD==TAIL.
		 *
		 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
		 * resubmit the request. See gen8_emit_request() for where we
		 * prepare the padding after the end of the request.
480
		 */
481
		struct intel_ringbuffer *ringbuf;
482

483
		ringbuf = req0->ctx->engine[engine->id].ringbuf;
484 485
		req0->tail += 8;
		req0->tail &= ringbuf->size - 1;
486 487
	}

488
	execlists_submit_requests(req0, req1);
489 490
}

491
static unsigned int
492
execlists_check_remove_request(struct intel_engine_cs *engine, u32 request_id)
493
{
494
	struct drm_i915_gem_request *head_req;
495

496
	assert_spin_locked(&engine->execlist_lock);
497

498
	head_req = list_first_entry_or_null(&engine->execlist_queue,
499
					    struct drm_i915_gem_request,
500 501
					    execlist_link);

502 503
	if (!head_req)
		return 0;
504

505
	if (unlikely(intel_execlists_ctx_id(head_req->ctx, engine) != request_id))
506 507 508 509 510 511 512 513
		return 0;

	WARN(head_req->elsp_submitted == 0, "Never submitted head request\n");

	if (--head_req->elsp_submitted > 0)
		return 0;

	list_move_tail(&head_req->execlist_link,
514
		       &engine->execlist_retired_req_list);
515

516
	return 1;
517 518
}

519
static u32
520
get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
521
		   u32 *context_id)
B
Ben Widawsky 已提交
522
{
523
	struct drm_i915_private *dev_priv = engine->dev->dev_private;
524
	u32 status;
B
Ben Widawsky 已提交
525

526 527
	read_pointer %= GEN8_CSB_ENTRIES;

528
	status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer));
529 530 531

	if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
		return 0;
B
Ben Widawsky 已提交
532

533
	*context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine,
534 535 536
							      read_pointer));

	return status;
B
Ben Widawsky 已提交
537 538
}

539
/**
540
 * intel_lrc_irq_handler() - handle Context Switch interrupts
541 542 543 544 545
 * @ring: Engine Command Streamer to handle.
 *
 * Check the unread Context Status Buffers and manage the submission of new
 * contexts to the ELSP accordingly.
 */
546
void intel_lrc_irq_handler(struct intel_engine_cs *engine)
547
{
548
	struct drm_i915_private *dev_priv = engine->dev->dev_private;
549
	u32 status_pointer;
550
	unsigned int read_pointer, write_pointer;
551 552
	u32 csb[GEN8_CSB_ENTRIES][2];
	unsigned int csb_read = 0, i;
553 554 555 556 557
	unsigned int submit_contexts = 0;

	spin_lock(&dev_priv->uncore.lock);
	intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);

558
	status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine));
559

560
	read_pointer = engine->next_context_status_buffer;
561
	write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
562
	if (read_pointer > write_pointer)
563
		write_pointer += GEN8_CSB_ENTRIES;
564 565

	while (read_pointer < write_pointer) {
566 567 568 569 570 571
		if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES))
			break;
		csb[csb_read][0] = get_context_status(engine, ++read_pointer,
						      &csb[csb_read][1]);
		csb_read++;
	}
B
Ben Widawsky 已提交
572

573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589
	engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;

	/* Update the read pointer to the old write pointer. Manual ringbuffer
	 * management ftw </sarcasm> */
	I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine),
		      _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
				    engine->next_context_status_buffer << 8));

	intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
	spin_unlock(&dev_priv->uncore.lock);

	spin_lock(&engine->execlist_lock);

	for (i = 0; i < csb_read; i++) {
		if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) {
			if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) {
				if (execlists_check_remove_request(engine, csb[i][1]))
590 591 592 593 594
					WARN(1, "Lite Restored request removed from queue\n");
			} else
				WARN(1, "Preemption without Lite Restore\n");
		}

595
		if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE |
596 597
		    GEN8_CTX_STATUS_ELEMENT_SWITCH))
			submit_contexts +=
598
				execlists_check_remove_request(engine, csb[i][1]);
599 600
	}

601
	if (submit_contexts) {
602
		if (!engine->disable_lite_restore_wa ||
603 604
		    (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
			execlists_context_unqueue(engine);
605
	}
606

607
	spin_unlock(&engine->execlist_lock);
608 609 610

	if (unlikely(submit_contexts > 2))
		DRM_ERROR("More than two context complete events?\n");
611 612
}

613
static void execlists_context_queue(struct drm_i915_gem_request *request)
614
{
615
	struct intel_engine_cs *engine = request->engine;
616
	struct drm_i915_gem_request *cursor;
617
	int num_elements = 0;
618

619
	if (request->ctx != request->i915->kernel_context)
620
		intel_lr_context_pin(request->ctx, engine);
621

622 623
	i915_gem_request_reference(request);

624
	spin_lock_irq(&engine->execlist_lock);
625

626
	list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
627 628 629 630
		if (++num_elements > 2)
			break;

	if (num_elements > 2) {
631
		struct drm_i915_gem_request *tail_req;
632

633
		tail_req = list_last_entry(&engine->execlist_queue,
634
					   struct drm_i915_gem_request,
635 636
					   execlist_link);

637
		if (request->ctx == tail_req->ctx) {
638
			WARN(tail_req->elsp_submitted != 0,
639
				"More than 2 already-submitted reqs queued\n");
640
			list_move_tail(&tail_req->execlist_link,
641
				       &engine->execlist_retired_req_list);
642 643 644
		}
	}

645
	list_add_tail(&request->execlist_link, &engine->execlist_queue);
646
	if (num_elements == 0)
647
		execlists_context_unqueue(engine);
648

649
	spin_unlock_irq(&engine->execlist_lock);
650 651
}

652
static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
653
{
654
	struct intel_engine_cs *engine = req->engine;
655 656 657 658
	uint32_t flush_domains;
	int ret;

	flush_domains = 0;
659
	if (engine->gpu_caches_dirty)
660 661
		flush_domains = I915_GEM_GPU_DOMAINS;

662
	ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
663 664 665
	if (ret)
		return ret;

666
	engine->gpu_caches_dirty = false;
667 668 669
	return 0;
}

670
static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
671 672
				 struct list_head *vmas)
{
673
	const unsigned other_rings = ~intel_engine_flag(req->engine);
674 675 676 677 678 679 680 681
	struct i915_vma *vma;
	uint32_t flush_domains = 0;
	bool flush_chipset = false;
	int ret;

	list_for_each_entry(vma, vmas, exec_list) {
		struct drm_i915_gem_object *obj = vma->obj;

682
		if (obj->active & other_rings) {
683
			ret = i915_gem_object_sync(obj, req->engine, &req);
684 685 686
			if (ret)
				return ret;
		}
687 688 689 690 691 692 693 694 695 696 697 698 699

		if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
			flush_chipset |= i915_gem_clflush_object(obj, false);

		flush_domains |= obj->base.write_domain;
	}

	if (flush_domains & I915_GEM_DOMAIN_GTT)
		wmb();

	/* Unconditionally invalidate gpu caches and ensure that we do flush
	 * any residual writes from the previous batch.
	 */
700
	return logical_ring_invalidate_all_caches(req);
701 702
}

703
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
704
{
D
Dave Gordon 已提交
705
	int ret = 0;
706

707
	request->ringbuf = request->ctx->engine[request->engine->id].ringbuf;
708

709 710 711 712 713 714 715 716 717 718 719 720 721
	if (i915.enable_guc_submission) {
		/*
		 * Check that the GuC has space for the request before
		 * going any further, as the i915_add_request() call
		 * later on mustn't fail ...
		 */
		struct intel_guc *guc = &request->i915->guc;

		ret = i915_guc_wq_check_space(guc->execbuf_client);
		if (ret)
			return ret;
	}

D
Dave Gordon 已提交
722
	if (request->ctx != request->i915->kernel_context)
723
		ret = intel_lr_context_pin(request->ctx, request->engine);
D
Dave Gordon 已提交
724 725

	return ret;
726 727
}

728
static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
729
				       int bytes)
730
{
731
	struct intel_ringbuffer *ringbuf = req->ringbuf;
732
	struct intel_engine_cs *engine = req->engine;
733
	struct drm_i915_gem_request *target;
734 735
	unsigned space;
	int ret;
736 737 738 739

	if (intel_ring_space(ringbuf) >= bytes)
		return 0;

740 741 742
	/* The whole point of reserving space is to not wait! */
	WARN_ON(ringbuf->reserved_in_use);

743
	list_for_each_entry(target, &engine->request_list, list) {
744 745 746 747 748
		/*
		 * The request queue is per-engine, so can contain requests
		 * from multiple ringbuffers. Here, we must ignore any that
		 * aren't from the ringbuffer we're considering.
		 */
749
		if (target->ringbuf != ringbuf)
750 751 752
			continue;

		/* Would completion of this request free enough space? */
753
		space = __intel_ring_space(target->postfix, ringbuf->tail,
754 755
					   ringbuf->size);
		if (space >= bytes)
756 757 758
			break;
	}

759
	if (WARN_ON(&target->list == &engine->request_list))
760 761
		return -ENOSPC;

762
	ret = i915_wait_request(target);
763 764 765
	if (ret)
		return ret;

766 767
	ringbuf->space = space;
	return 0;
768 769 770 771
}

/*
 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
772
 * @request: Request to advance the logical ringbuffer of.
773 774 775 776 777 778
 *
 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 * really happens during submission is that the context and current tail will be placed
 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 * point, the tail *inside* the context is updated and the ELSP written to.
 */
779
static int
780
intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
781
{
782
	struct intel_ringbuffer *ringbuf = request->ringbuf;
783
	struct drm_i915_private *dev_priv = request->i915;
784
	struct intel_engine_cs *engine = request->engine;
785

786 787
	intel_logical_ring_advance(ringbuf);
	request->tail = ringbuf->tail;
788

789 790 791 792 793 794 795 796 797
	/*
	 * Here we add two extra NOOPs as padding to avoid
	 * lite restore of a context with HEAD==TAIL.
	 *
	 * Caller must reserve WA_TAIL_DWORDS for us!
	 */
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);
798

799
	if (intel_engine_stopped(engine))
800
		return 0;
801

802 803 804 805 806 807 808 809 810 811 812
	if (engine->last_context != request->ctx) {
		if (engine->last_context)
			intel_lr_context_unpin(engine->last_context, engine);
		if (request->ctx != request->i915->kernel_context) {
			intel_lr_context_pin(request->ctx, engine);
			engine->last_context = request->ctx;
		} else {
			engine->last_context = NULL;
		}
	}

813 814 815 816
	if (dev_priv->guc.execbuf_client)
		i915_guc_submit(dev_priv->guc.execbuf_client, request);
	else
		execlists_context_queue(request);
817 818

	return 0;
819 820
}

821
static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
822 823 824 825 826 827 828 829 830 831 832 833 834
{
	uint32_t __iomem *virt;
	int rem = ringbuf->size - ringbuf->tail;

	virt = ringbuf->virtual_start + ringbuf->tail;
	rem /= 4;
	while (rem--)
		iowrite32(MI_NOOP, virt++);

	ringbuf->tail = 0;
	intel_ring_update_space(ringbuf);
}

835
static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
836
{
837
	struct intel_ringbuffer *ringbuf = req->ringbuf;
838 839 840 841
	int remain_usable = ringbuf->effective_size - ringbuf->tail;
	int remain_actual = ringbuf->size - ringbuf->tail;
	int ret, total_bytes, wait_bytes = 0;
	bool need_wrap = false;
842

843 844 845 846
	if (ringbuf->reserved_in_use)
		total_bytes = bytes;
	else
		total_bytes = bytes + ringbuf->reserved_size;
847

848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866
	if (unlikely(bytes > remain_usable)) {
		/*
		 * Not enough space for the basic request. So need to flush
		 * out the remainder and then wait for base + reserved.
		 */
		wait_bytes = remain_actual + total_bytes;
		need_wrap = true;
	} else {
		if (unlikely(total_bytes > remain_usable)) {
			/*
			 * The base request will fit but the reserved space
			 * falls off the end. So only need to to wait for the
			 * reserved size after flushing out the remainder.
			 */
			wait_bytes = remain_actual + ringbuf->reserved_size;
			need_wrap = true;
		} else if (total_bytes > ringbuf->space) {
			/* No wrapping required, just waiting. */
			wait_bytes = total_bytes;
867
		}
868 869
	}

870 871
	if (wait_bytes) {
		ret = logical_ring_wait_for_space(req, wait_bytes);
872 873
		if (unlikely(ret))
			return ret;
874 875 876

		if (need_wrap)
			__wrap_ring_buffer(ringbuf);
877 878 879 880 881 882 883 884
	}

	return 0;
}

/**
 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
 *
885
 * @req: The request to start some new work for
886 887 888 889 890 891 892 893 894
 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
 *
 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
 * and also preallocates a request (every workload submission is still mediated through
 * requests, same as it did with legacy ringbuffer submission).
 *
 * Return: non-zero if the ringbuffer is not ready to be written to.
 */
895
int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
896
{
897
	struct drm_i915_private *dev_priv;
898 899
	int ret;

900
	WARN_ON(req == NULL);
901
	dev_priv = req->i915;
902

903 904 905 906 907
	ret = i915_gem_check_wedge(&dev_priv->gpu_error,
				   dev_priv->mm.interruptible);
	if (ret)
		return ret;

908
	ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
909 910 911
	if (ret)
		return ret;

912
	req->ringbuf->space -= num_dwords * sizeof(uint32_t);
913 914 915
	return 0;
}

916 917 918 919 920 921 922 923 924 925 926 927 928 929 930
int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
{
	/*
	 * The first call merely notes the reserve request and is common for
	 * all back ends. The subsequent localised _begin() call actually
	 * ensures that the reservation is available. Without the begin, if
	 * the request creator immediately submitted the request without
	 * adding any commands to it then there might not actually be
	 * sufficient room for the submission commands.
	 */
	intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);

	return intel_logical_ring_begin(request, 0);
}

931 932 933 934 935 936 937 938 939 940
/**
 * execlists_submission() - submit a batchbuffer for execution, Execlists style
 * @dev: DRM device.
 * @file: DRM file.
 * @ring: Engine Command Streamer to submit to.
 * @ctx: Context to employ for this submission.
 * @args: execbuffer call arguments.
 * @vmas: list of vmas.
 * @batch_obj: the batchbuffer to submit.
 * @exec_start: batchbuffer start virtual address pointer.
941
 * @dispatch_flags: translated execbuffer call flags.
942 943 944 945 946 947
 *
 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 * away the submission details of the execbuffer ioctl call.
 *
 * Return: non-zero if the submission fails.
 */
948
int intel_execlists_submission(struct i915_execbuffer_params *params,
949
			       struct drm_i915_gem_execbuffer2 *args,
950
			       struct list_head *vmas)
951
{
952
	struct drm_device       *dev = params->dev;
953
	struct intel_engine_cs *engine = params->engine;
954
	struct drm_i915_private *dev_priv = dev->dev_private;
955
	struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf;
956
	u64 exec_start;
957 958 959 960 961 962 963 964 965 966
	int instp_mode;
	u32 instp_mask;
	int ret;

	instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
	instp_mask = I915_EXEC_CONSTANTS_MASK;
	switch (instp_mode) {
	case I915_EXEC_CONSTANTS_REL_GENERAL:
	case I915_EXEC_CONSTANTS_ABSOLUTE:
	case I915_EXEC_CONSTANTS_REL_SURFACE:
967
		if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) {
968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991
			DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
			return -EINVAL;
		}

		if (instp_mode != dev_priv->relative_constants_mode) {
			if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
				DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
				return -EINVAL;
			}

			/* The HW changed the meaning on this bit on gen6 */
			instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
		}
		break;
	default:
		DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
		return -EINVAL;
	}

	if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
		DRM_DEBUG("sol reset is gen7 only\n");
		return -EINVAL;
	}

992
	ret = execlists_move_to_gpu(params->request, vmas);
993 994 995
	if (ret)
		return ret;

996
	if (engine == &dev_priv->engine[RCS] &&
997
	    instp_mode != dev_priv->relative_constants_mode) {
998
		ret = intel_logical_ring_begin(params->request, 4);
999 1000 1001 1002 1003
		if (ret)
			return ret;

		intel_logical_ring_emit(ringbuf, MI_NOOP);
		intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
1004
		intel_logical_ring_emit_reg(ringbuf, INSTPM);
1005 1006 1007 1008 1009 1010
		intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
		intel_logical_ring_advance(ringbuf);

		dev_priv->relative_constants_mode = instp_mode;
	}

1011 1012 1013
	exec_start = params->batch_obj_vm_offset +
		     args->batch_start_offset;

1014
	ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags);
1015 1016 1017
	if (ret)
		return ret;

1018
	trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1019

1020
	i915_gem_execbuffer_move_to_active(vmas, params->request);
1021
	i915_gem_execbuffer_retire_commands(params);
1022

1023 1024 1025
	return 0;
}

1026
void intel_execlists_retire_requests(struct intel_engine_cs *engine)
1027
{
1028
	struct drm_i915_gem_request *req, *tmp;
1029 1030
	struct list_head retired_list;

1031 1032
	WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
	if (list_empty(&engine->execlist_retired_req_list))
1033 1034 1035
		return;

	INIT_LIST_HEAD(&retired_list);
1036 1037 1038
	spin_lock_irq(&engine->execlist_lock);
	list_replace_init(&engine->execlist_retired_req_list, &retired_list);
	spin_unlock_irq(&engine->execlist_lock);
1039 1040

	list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
1041 1042
		struct intel_context *ctx = req->ctx;
		struct drm_i915_gem_object *ctx_obj =
1043
				ctx->engine[engine->id].state;
1044

1045
		if (ctx_obj && (ctx != req->i915->kernel_context))
1046
			intel_lr_context_unpin(ctx, engine);
1047

1048
		list_del(&req->execlist_link);
1049
		i915_gem_request_unreference(req);
1050 1051 1052
	}
}

1053
void intel_logical_ring_stop(struct intel_engine_cs *engine)
1054
{
1055
	struct drm_i915_private *dev_priv = engine->dev->dev_private;
1056 1057
	int ret;

1058
	if (!intel_engine_initialized(engine))
1059 1060
		return;

1061
	ret = intel_engine_idle(engine);
1062
	if (ret && !i915_reset_in_progress(&to_i915(engine->dev)->gpu_error))
1063
		DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1064
			  engine->name, ret);
1065 1066

	/* TODO: Is this correct with Execlists enabled? */
1067 1068 1069
	I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
	if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
		DRM_ERROR("%s :timed out trying to stop ring\n", engine->name);
1070 1071
		return;
	}
1072
	I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
1073 1074
}

1075
int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
1076
{
1077
	struct intel_engine_cs *engine = req->engine;
1078 1079
	int ret;

1080
	if (!engine->gpu_caches_dirty)
1081 1082
		return 0;

1083
	ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1084 1085 1086
	if (ret)
		return ret;

1087
	engine->gpu_caches_dirty = false;
1088 1089 1090
	return 0;
}

1091
static int intel_lr_context_do_pin(struct intel_context *ctx,
1092
				   struct intel_engine_cs *engine)
1093
{
1094
	struct drm_device *dev = engine->dev;
1095
	struct drm_i915_private *dev_priv = dev->dev_private;
1096 1097
	struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
	struct intel_ringbuffer *ringbuf = ctx->engine[engine->id].ringbuf;
1098
	struct page *lrc_state_page;
1099
	uint32_t *lrc_reg_state;
1100
	int ret;
1101

1102
	WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex));
1103

1104 1105 1106 1107
	ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
			PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
	if (ret)
		return ret;
1108

1109 1110 1111 1112 1113 1114
	lrc_state_page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
	if (WARN_ON(!lrc_state_page)) {
		ret = -ENODEV;
		goto unpin_ctx_obj;
	}

1115
	ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf);
1116 1117
	if (ret)
		goto unpin_ctx_obj;
1118

1119 1120
	ctx->engine[engine->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj);
	intel_lr_context_descriptor_update(ctx, engine);
1121 1122
	lrc_reg_state = kmap(lrc_state_page);
	lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start;
1123
	ctx->engine[engine->id].lrc_reg_state = lrc_reg_state;
1124
	ctx_obj->dirty = true;
1125

1126 1127 1128
	/* Invalidate GuC TLB. */
	if (i915.enable_guc_submission)
		I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
1129

1130 1131 1132 1133
	return ret;

unpin_ctx_obj:
	i915_gem_object_ggtt_unpin(ctx_obj);
1134 1135 1136 1137

	return ret;
}

1138 1139
static int intel_lr_context_pin(struct intel_context *ctx,
				struct intel_engine_cs *engine)
1140 1141 1142
{
	int ret = 0;

1143 1144
	if (ctx->engine[engine->id].pin_count++ == 0) {
		ret = intel_lr_context_do_pin(ctx, engine);
1145 1146
		if (ret)
			goto reset_pin_count;
1147 1148

		i915_gem_context_reference(ctx);
1149 1150 1151
	}
	return ret;

1152
reset_pin_count:
1153
	ctx->engine[engine->id].pin_count = 0;
1154 1155 1156
	return ret;
}

1157 1158
void intel_lr_context_unpin(struct intel_context *ctx,
			    struct intel_engine_cs *engine)
1159
{
1160
	struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
1161

1162
	WARN_ON(!mutex_is_locked(&ctx->i915->dev->struct_mutex));
1163 1164 1165
	if (--ctx->engine[engine->id].pin_count == 0) {
		kunmap(kmap_to_page(ctx->engine[engine->id].lrc_reg_state));
		intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf);
1166
		i915_gem_object_ggtt_unpin(ctx_obj);
1167 1168 1169
		ctx->engine[engine->id].lrc_vma = NULL;
		ctx->engine[engine->id].lrc_desc = 0;
		ctx->engine[engine->id].lrc_reg_state = NULL;
1170 1171

		i915_gem_context_unreference(ctx);
1172 1173 1174
	}
}

1175
static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1176 1177
{
	int ret, i;
1178
	struct intel_engine_cs *engine = req->engine;
1179
	struct intel_ringbuffer *ringbuf = req->ringbuf;
1180
	struct drm_device *dev = engine->dev;
1181 1182 1183
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_workarounds *w = &dev_priv->workarounds;

1184
	if (w->count == 0)
1185 1186
		return 0;

1187
	engine->gpu_caches_dirty = true;
1188
	ret = logical_ring_flush_all_caches(req);
1189 1190 1191
	if (ret)
		return ret;

1192
	ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1193 1194 1195 1196 1197
	if (ret)
		return ret;

	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
	for (i = 0; i < w->count; i++) {
1198
		intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
1199 1200 1201 1202 1203 1204
		intel_logical_ring_emit(ringbuf, w->reg[i].value);
	}
	intel_logical_ring_emit(ringbuf, MI_NOOP);

	intel_logical_ring_advance(ringbuf);

1205
	engine->gpu_caches_dirty = true;
1206
	ret = logical_ring_flush_all_caches(req);
1207 1208 1209 1210 1211 1212
	if (ret)
		return ret;

	return 0;
}

1213
#define wa_ctx_emit(batch, index, cmd)					\
1214
	do {								\
1215 1216
		int __index = (index)++;				\
		if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1217 1218
			return -ENOSPC;					\
		}							\
1219
		batch[__index] = (cmd);					\
1220 1221
	} while (0)

V
Ville Syrjälä 已提交
1222
#define wa_ctx_emit_reg(batch, index, reg) \
1223
	wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240

/*
 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
 * but there is a slight complication as this is applied in WA batch where the
 * values are only initialized once so we cannot take register value at the
 * beginning and reuse it further; hence we save its value to memory, upload a
 * constant value with bit21 set and then we restore it back with the saved value.
 * To simplify the WA, a constant value is formed by using the default value
 * of this register. This shouldn't be a problem because we are only modifying
 * it for a short period and this batch in non-premptible. We can ofcourse
 * use additional instructions that read the actual value of the register
 * at that time and set our bit of interest but it makes the WA complicated.
 *
 * This WA is also required for Gen9 so extracting as a function avoids
 * code duplication.
 */
1241
static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
1242 1243 1244 1245 1246
						uint32_t *const batch,
						uint32_t index)
{
	uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);

1247 1248 1249 1250 1251 1252
	/*
	 * WaDisableLSQCROPERFforOCL:skl
	 * This WA is implemented in skl_init_clock_gating() but since
	 * this batch updates GEN8_L3SQCREG4 with default value we need to
	 * set this bit here to retain the WA during flush.
	 */
1253
	if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
1254 1255
		l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;

1256
	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1257
				   MI_SRM_LRM_GLOBAL_GTT));
V
Ville Syrjälä 已提交
1258
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1259
	wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1260 1261 1262
	wa_ctx_emit(batch, index, 0);

	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
V
Ville Syrjälä 已提交
1263
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1264 1265 1266 1267 1268 1269 1270 1271 1272 1273
	wa_ctx_emit(batch, index, l3sqc4_flush);

	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_DC_FLUSH_ENABLE));
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);

1274
	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1275
				   MI_SRM_LRM_GLOBAL_GTT));
V
Ville Syrjälä 已提交
1276
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1277
	wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
1278
	wa_ctx_emit(batch, index, 0);
1279 1280 1281 1282

	return index;
}

1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320
static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t offset,
				    uint32_t start_alignment)
{
	return wa_ctx->offset = ALIGN(offset, start_alignment);
}

static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
			     uint32_t offset,
			     uint32_t size_alignment)
{
	wa_ctx->size = offset - wa_ctx->offset;

	WARN(wa_ctx->size % size_alignment,
	     "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
	     wa_ctx->size, size_alignment);
	return 0;
}

/**
 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
 *
 * @ring: only applicable for RCS
 * @wa_ctx: structure representing wa_ctx
 *  offset: specifies start of the batch, should be cache-aligned. This is updated
 *    with the offset value received as input.
 *  size: size of the batch in DWORDS but HW expects in terms of cachelines
 * @batch: page in which WA are loaded
 * @offset: This field specifies the start of the batch, it should be
 *  cache-aligned otherwise it is adjusted accordingly.
 *  Typically we only have one indirect_ctx and per_ctx batch buffer which are
 *  initialized at the beginning and shared across all contexts but this field
 *  helps us to have multiple batches at different offsets and select them based
 *  on a criteria. At the moment this batch always start at the beginning of the page
 *  and at this point we don't have multiple wa_ctx batch buffers.
 *
 *  The number of WA applied are not known at the beginning; we use this field
 *  to return the no of DWORDS written.
1321
 *
1322 1323 1324 1325 1326 1327 1328 1329
 *  It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
 *  so it adds NOOPs as padding to make it cacheline aligned.
 *  MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
 *  makes a complete batch buffer.
 *
 * Return: non-zero if we exceed the PAGE_SIZE limit.
 */

1330
static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
1331 1332 1333 1334
				    struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t *const batch,
				    uint32_t *offset)
{
1335
	uint32_t scratch_addr;
1336 1337
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1338
	/* WaDisableCtxRestoreArbitration:bdw,chv */
1339
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1340

1341
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1342 1343
	if (IS_BROADWELL(engine->dev)) {
		int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1344 1345 1346
		if (rc < 0)
			return rc;
		index = rc;
1347 1348
	}

1349 1350
	/* WaClearSlmSpaceAtContextSwitch:bdw,chv */
	/* Actual scratch location is at 128 bytes offset */
1351
	scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1352

1353 1354 1355 1356 1357 1358 1359 1360 1361
	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
				   PIPE_CONTROL_GLOBAL_GTT_IVB |
				   PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_QW_WRITE));
	wa_ctx_emit(batch, index, scratch_addr);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
1362

1363 1364
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
1365
		wa_ctx_emit(batch, index, MI_NOOP);
1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382

	/*
	 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
	 * execution depends on the length specified in terms of cache lines
	 * in the register CTX_RCS_INDIRECT_CTX
	 */

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

/**
 * gen8_init_perctx_bb() - initialize per ctx batch with WA
 *
 * @ring: only applicable for RCS
 * @wa_ctx: structure representing wa_ctx
 *  offset: specifies start of the batch, should be cache-aligned.
 *  size: size of the batch in DWORDS but HW expects in terms of cachelines
1383
 * @batch: page in which WA are loaded
1384 1385 1386 1387 1388 1389 1390 1391 1392
 * @offset: This field specifies the start of this batch.
 *   This batch is started immediately after indirect_ctx batch. Since we ensure
 *   that indirect_ctx ends on a cacheline this batch is aligned automatically.
 *
 *   The number of DWORDS written are returned using this field.
 *
 *  This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
 *  to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
 */
1393
static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1394 1395 1396 1397 1398 1399
			       struct i915_wa_ctx_bb *wa_ctx,
			       uint32_t *const batch,
			       uint32_t *offset)
{
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1400
	/* WaDisableCtxRestoreArbitration:bdw,chv */
1401
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1402

1403
	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1404 1405 1406 1407

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1408
static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1409 1410 1411 1412
				    struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t *const batch,
				    uint32_t *offset)
{
1413
	int ret;
1414
	struct drm_device *dev = engine->dev;
1415 1416
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1417
	/* WaDisableCtxRestoreArbitration:skl,bxt */
1418
	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
T
Tim Gore 已提交
1419
	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1420
		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1421

1422
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1423
	ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1424 1425 1426 1427
	if (ret < 0)
		return ret;
	index = ret;

1428 1429 1430 1431 1432 1433 1434
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
		wa_ctx_emit(batch, index, MI_NOOP);

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

1435
static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1436 1437 1438 1439
			       struct i915_wa_ctx_bb *wa_ctx,
			       uint32_t *const batch,
			       uint32_t *offset)
{
1440
	struct drm_device *dev = engine->dev;
1441 1442
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1443
	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1444
	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
T
Tim Gore 已提交
1445
	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1446
		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
V
Ville Syrjälä 已提交
1447
		wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1448 1449 1450 1451 1452
		wa_ctx_emit(batch, index,
			    _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
		wa_ctx_emit(batch, index, MI_NOOP);
	}

1453
	/* WaDisableCtxRestoreArbitration:skl,bxt */
1454
	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
T
Tim Gore 已提交
1455
	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1456 1457
		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);

1458 1459 1460 1461 1462
	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1463
static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1464 1465 1466
{
	int ret;

1467 1468 1469
	engine->wa_ctx.obj = i915_gem_alloc_object(engine->dev,
						   PAGE_ALIGN(size));
	if (!engine->wa_ctx.obj) {
1470 1471 1472 1473
		DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
		return -ENOMEM;
	}

1474
	ret = i915_gem_obj_ggtt_pin(engine->wa_ctx.obj, PAGE_SIZE, 0);
1475 1476 1477
	if (ret) {
		DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
				 ret);
1478
		drm_gem_object_unreference(&engine->wa_ctx.obj->base);
1479 1480 1481 1482 1483 1484
		return ret;
	}

	return 0;
}

1485
static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1486
{
1487 1488 1489 1490
	if (engine->wa_ctx.obj) {
		i915_gem_object_ggtt_unpin(engine->wa_ctx.obj);
		drm_gem_object_unreference(&engine->wa_ctx.obj->base);
		engine->wa_ctx.obj = NULL;
1491 1492 1493
	}
}

1494
static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1495 1496 1497 1498 1499
{
	int ret;
	uint32_t *batch;
	uint32_t offset;
	struct page *page;
1500
	struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1501

1502
	WARN_ON(engine->id != RCS);
1503

1504
	/* update this when WA for higher Gen are added */
1505
	if (INTEL_INFO(engine->dev)->gen > 9) {
1506
		DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1507
			  INTEL_INFO(engine->dev)->gen);
1508
		return 0;
1509
	}
1510

1511
	/* some WA perform writes to scratch page, ensure it is valid */
1512 1513
	if (engine->scratch.obj == NULL) {
		DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1514 1515 1516
		return -EINVAL;
	}

1517
	ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1518 1519 1520 1521 1522
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
		return ret;
	}

1523
	page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0);
1524 1525 1526
	batch = kmap_atomic(page);
	offset = 0;

1527 1528
	if (INTEL_INFO(engine->dev)->gen == 8) {
		ret = gen8_init_indirectctx_bb(engine,
1529 1530 1531 1532 1533 1534
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

1535
		ret = gen8_init_perctx_bb(engine,
1536 1537 1538 1539 1540
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1541 1542
	} else if (INTEL_INFO(engine->dev)->gen == 9) {
		ret = gen9_init_indirectctx_bb(engine,
1543 1544 1545 1546 1547 1548
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

1549
		ret = gen9_init_perctx_bb(engine,
1550 1551 1552 1553 1554
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1555 1556 1557 1558 1559
	}

out:
	kunmap_atomic(batch);
	if (ret)
1560
		lrc_destroy_wa_ctx_obj(engine);
1561 1562 1563 1564

	return ret;
}

1565
static int gen8_init_common_ring(struct intel_engine_cs *engine)
1566
{
1567
	struct drm_device *dev = engine->dev;
1568
	struct drm_i915_private *dev_priv = dev->dev_private;
1569
	unsigned int next_context_status_buffer_hw;
1570

1571 1572
	lrc_setup_hardware_status_page(engine,
				       dev_priv->kernel_context->engine[engine->id].state);
1573

1574 1575 1576
	I915_WRITE_IMR(engine,
		       ~(engine->irq_enable_mask | engine->irq_keep_mask));
	I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1577

1578
	I915_WRITE(RING_MODE_GEN7(engine),
1579 1580
		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1581
	POSTING_READ(RING_MODE_GEN7(engine));
1582 1583 1584 1585 1586 1587 1588 1589 1590 1591

	/*
	 * Instead of resetting the Context Status Buffer (CSB) read pointer to
	 * zero, we need to read the write pointer from hardware and use its
	 * value because "this register is power context save restored".
	 * Effectively, these states have been observed:
	 *
	 *      | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
	 * BDW  | CSB regs not reset       | CSB regs reset       |
	 * CHT  | CSB regs not reset       | CSB regs not reset   |
1592 1593
	 * SKL  |         ?                |         ?            |
	 * BXT  |         ?                |         ?            |
1594
	 */
1595
	next_context_status_buffer_hw =
1596
		GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine)));
1597 1598 1599 1600 1601 1602 1603 1604 1605

	/*
	 * When the CSB registers are reset (also after power-up / gpu reset),
	 * CSB write pointer is set to all 1's, which is not valid, use '5' in
	 * this special case, so the first element read is CSB[0].
	 */
	if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
		next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);

1606 1607
	engine->next_context_status_buffer = next_context_status_buffer_hw;
	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1608

1609
	memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
1610 1611 1612 1613

	return 0;
}

1614
static int gen8_init_render_ring(struct intel_engine_cs *engine)
1615
{
1616
	struct drm_device *dev = engine->dev;
1617 1618 1619
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

1620
	ret = gen8_init_common_ring(engine);
1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633
	if (ret)
		return ret;

	/* We need to disable the AsyncFlip performance optimisations in order
	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
	 * programmed to '1' on all products.
	 *
	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
	 */
	I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));

	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));

1634
	return init_workarounds_ring(engine);
1635 1636
}

1637
static int gen9_init_render_ring(struct intel_engine_cs *engine)
1638 1639 1640
{
	int ret;

1641
	ret = gen8_init_common_ring(engine);
1642 1643 1644
	if (ret)
		return ret;

1645
	return init_workarounds_ring(engine);
1646 1647
}

1648 1649 1650
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
	struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1651
	struct intel_engine_cs *engine = req->engine;
1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663
	struct intel_ringbuffer *ringbuf = req->ringbuf;
	const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
	int i, ret;

	ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
	if (ret)
		return ret;

	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);

1664 1665
		intel_logical_ring_emit_reg(ringbuf,
					    GEN8_RING_PDP_UDW(engine, i));
1666
		intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1667 1668
		intel_logical_ring_emit_reg(ringbuf,
					    GEN8_RING_PDP_LDW(engine, i));
1669 1670 1671 1672 1673 1674 1675 1676 1677
		intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
	}

	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1678
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1679
			      u64 offset, unsigned dispatch_flags)
1680
{
1681
	struct intel_ringbuffer *ringbuf = req->ringbuf;
1682
	bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1683 1684
	int ret;

1685 1686 1687 1688
	/* Don't rely in hw updating PDPs, specially in lite-restore.
	 * Ideally, we should set Force PD Restore in ctx descriptor,
	 * but we can't. Force Restore would be a second option, but
	 * it is unsafe in case of lite-restore (because the ctx is
1689 1690
	 * not idle). PML4 is allocated during ppgtt init so this is
	 * not needed in 48-bit.*/
1691
	if (req->ctx->ppgtt &&
1692
	    (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1693 1694
		if (!USES_FULL_48BIT_PPGTT(req->i915) &&
		    !intel_vgpu_active(req->i915->dev)) {
1695 1696 1697 1698
			ret = intel_logical_ring_emit_pdps(req);
			if (ret)
				return ret;
		}
1699

1700
		req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1701 1702
	}

1703
	ret = intel_logical_ring_begin(req, 4);
1704 1705 1706 1707
	if (ret)
		return ret;

	/* FIXME(BDW): Address space and security selectors. */
1708 1709 1710 1711
	intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
				(ppgtt<<8) |
				(dispatch_flags & I915_DISPATCH_RS ?
				 MI_BATCH_RESOURCE_STREAMER : 0));
1712 1713 1714 1715 1716 1717 1718 1719
	intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
	intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1720
static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
1721
{
1722
	struct drm_device *dev = engine->dev;
1723 1724 1725
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long flags;

1726
	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1727 1728 1729
		return false;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
1730 1731 1732 1733
	if (engine->irq_refcount++ == 0) {
		I915_WRITE_IMR(engine,
			       ~(engine->irq_enable_mask | engine->irq_keep_mask));
		POSTING_READ(RING_IMR(engine->mmio_base));
1734 1735 1736 1737 1738 1739
	}
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	return true;
}

1740
static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
1741
{
1742
	struct drm_device *dev = engine->dev;
1743 1744 1745 1746
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
1747 1748 1749
	if (--engine->irq_refcount == 0) {
		I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
		POSTING_READ(RING_IMR(engine->mmio_base));
1750 1751 1752 1753
	}
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
}

1754
static int gen8_emit_flush(struct drm_i915_gem_request *request,
1755 1756 1757
			   u32 invalidate_domains,
			   u32 unused)
{
1758
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1759
	struct intel_engine_cs *engine = ringbuf->engine;
1760
	struct drm_device *dev = engine->dev;
1761 1762 1763 1764
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t cmd;
	int ret;

1765
	ret = intel_logical_ring_begin(request, 4);
1766 1767 1768 1769 1770
	if (ret)
		return ret;

	cmd = MI_FLUSH_DW + 1;

1771 1772 1773 1774 1775 1776 1777 1778 1779
	/* We always require a command barrier so that subsequent
	 * commands, such as breadcrumb interrupts, are strictly ordered
	 * wrt the contents of the write cache being flushed to memory
	 * (and thus being coherent from the CPU).
	 */
	cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;

	if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
		cmd |= MI_INVALIDATE_TLB;
1780
		if (engine == &dev_priv->engine[VCS])
1781
			cmd |= MI_INVALIDATE_BSD;
1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794
	}

	intel_logical_ring_emit(ringbuf, cmd);
	intel_logical_ring_emit(ringbuf,
				I915_GEM_HWS_SCRATCH_ADDR |
				MI_FLUSH_DW_USE_GTT);
	intel_logical_ring_emit(ringbuf, 0); /* upper addr */
	intel_logical_ring_emit(ringbuf, 0); /* value */
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1795
static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1796 1797 1798
				  u32 invalidate_domains,
				  u32 flush_domains)
{
1799
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1800
	struct intel_engine_cs *engine = ringbuf->engine;
1801
	u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1802
	bool vf_flush_wa = false;
1803 1804 1805 1806 1807 1808 1809 1810
	u32 flags = 0;
	int ret;

	flags |= PIPE_CONTROL_CS_STALL;

	if (flush_domains) {
		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1811
		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1812
		flags |= PIPE_CONTROL_FLUSH_ENABLE;
1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824
	}

	if (invalidate_domains) {
		flags |= PIPE_CONTROL_TLB_INVALIDATE;
		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_QW_WRITE;
		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;

1825 1826 1827 1828
		/*
		 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
		 * pipe control.
		 */
1829
		if (IS_GEN9(engine->dev))
1830 1831
			vf_flush_wa = true;
	}
1832

1833
	ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1834 1835 1836
	if (ret)
		return ret;

1837 1838 1839 1840 1841 1842 1843 1844 1845
	if (vf_flush_wa) {
		intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
	}

1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856
	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
	intel_logical_ring_emit(ringbuf, flags);
	intel_logical_ring_emit(ringbuf, scratch_addr);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1857
static u32 gen8_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
1858
{
1859
	return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1860 1861
}

1862
static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1863
{
1864
	intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1865 1866
}

1867 1868
static u32 bxt_a_get_seqno(struct intel_engine_cs *engine,
			   bool lazy_coherency)
1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882
{

	/*
	 * On BXT A steppings there is a HW coherency issue whereby the
	 * MI_STORE_DATA_IMM storing the completed request's seqno
	 * occasionally doesn't invalidate the CPU cache. Work around this by
	 * clflushing the corresponding cacheline whenever the caller wants
	 * the coherency to be guaranteed. Note that this cacheline is known
	 * to be clean at this point, since we only write it in
	 * bxt_a_set_seqno(), where we also do a clflush after the write. So
	 * this clflush in practice becomes an invalidate operation.
	 */

	if (!lazy_coherency)
1883
		intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1884

1885
	return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1886 1887
}

1888
static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1889
{
1890
	intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1891 1892

	/* See bxt_a_get_seqno() explaining the reason for the clflush. */
1893
	intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1894 1895
}

1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907
/*
 * Reserve space for 2 NOOPs at the end of each request to be
 * used as a workaround for not being allowed to do lite
 * restore with HEAD==TAIL (WaIdleLiteRestore).
 */
#define WA_TAIL_DWORDS 2

static inline u32 hws_seqno_address(struct intel_engine_cs *engine)
{
	return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR;
}

1908
static int gen8_emit_request(struct drm_i915_gem_request *request)
1909
{
1910
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1911 1912
	int ret;

1913
	ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
1914 1915 1916
	if (ret)
		return ret;

1917 1918
	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
	BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1919 1920

	intel_logical_ring_emit(ringbuf,
1921 1922
				(MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
	intel_logical_ring_emit(ringbuf,
1923
				hws_seqno_address(request->engine) |
1924
				MI_FLUSH_DW_USE_GTT);
1925
	intel_logical_ring_emit(ringbuf, 0);
1926
	intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1927 1928
	intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
	intel_logical_ring_emit(ringbuf, MI_NOOP);
1929 1930
	return intel_logical_ring_advance_and_submit(request);
}
1931

1932 1933 1934 1935
static int gen8_emit_request_render(struct drm_i915_gem_request *request)
{
	struct intel_ringbuffer *ringbuf = request->ringbuf;
	int ret;
1936

1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949
	ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
	if (ret)
		return ret;

	/* w/a for post sync ops following a GPGPU operation we
	 * need a prior CS_STALL, which is emitted by the flush
	 * following the batch.
	 */
	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
	intel_logical_ring_emit(ringbuf,
				(PIPE_CONTROL_GLOBAL_GTT_IVB |
				 PIPE_CONTROL_CS_STALL |
				 PIPE_CONTROL_QW_WRITE));
1950
	intel_logical_ring_emit(ringbuf, hws_seqno_address(request->engine));
1951 1952 1953 1954
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
	intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
	return intel_logical_ring_advance_and_submit(request);
1955 1956
}

1957
static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1958 1959 1960 1961
{
	struct render_state so;
	int ret;

1962
	ret = i915_gem_render_state_prepare(req->engine, &so);
1963 1964 1965 1966 1967 1968
	if (ret)
		return ret;

	if (so.rodata == NULL)
		return 0;

1969
	ret = req->engine->emit_bb_start(req, so.ggtt_offset,
1970
				       I915_DISPATCH_SECURE);
1971 1972 1973
	if (ret)
		goto out;

1974
	ret = req->engine->emit_bb_start(req,
1975 1976 1977 1978 1979
				       (so.ggtt_offset + so.aux_batch_offset),
				       I915_DISPATCH_SECURE);
	if (ret)
		goto out;

1980
	i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1981 1982 1983 1984 1985 1986

out:
	i915_gem_render_state_fini(&so);
	return ret;
}

1987
static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1988 1989 1990
{
	int ret;

1991
	ret = intel_logical_ring_workarounds_emit(req);
1992 1993 1994
	if (ret)
		return ret;

1995 1996 1997 1998 1999 2000 2001 2002
	ret = intel_rcs_context_init_mocs(req);
	/*
	 * Failing to program the MOCS is non-fatal.The system will not
	 * run at peak performance. So generate an error and carry on.
	 */
	if (ret)
		DRM_ERROR("MOCS failed to program: expect performance issues.\n");

2003
	return intel_lr_context_render_state_init(req);
2004 2005
}

2006 2007 2008 2009 2010 2011
/**
 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
 *
 * @ring: Engine Command Streamer.
 *
 */
2012
void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
2013
{
2014
	struct drm_i915_private *dev_priv;
2015

2016
	if (!intel_engine_initialized(engine))
2017 2018
		return;

2019
	dev_priv = engine->dev->dev_private;
2020

2021 2022 2023
	if (engine->buffer) {
		intel_logical_ring_stop(engine);
		WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
2024
	}
2025

2026 2027
	if (engine->cleanup)
		engine->cleanup(engine);
2028

2029 2030
	i915_cmd_parser_fini_ring(engine);
	i915_gem_batch_pool_fini(&engine->batch_pool);
2031

2032 2033 2034
	if (engine->status_page.obj) {
		kunmap(sg_page(engine->status_page.obj->pages->sgl));
		engine->status_page.obj = NULL;
2035
	}
2036

2037 2038 2039
	engine->idle_lite_restore_wa = 0;
	engine->disable_lite_restore_wa = false;
	engine->ctx_desc_template = 0;
2040

2041 2042
	lrc_destroy_wa_ctx_obj(engine);
	engine->dev = NULL;
2043 2044
}

2045 2046
static void
logical_ring_default_vfuncs(struct drm_device *dev,
2047
			    struct intel_engine_cs *engine)
2048 2049
{
	/* Default vfuncs which can be overriden by each engine. */
2050 2051 2052 2053 2054 2055
	engine->init_hw = gen8_init_common_ring;
	engine->emit_request = gen8_emit_request;
	engine->emit_flush = gen8_emit_flush;
	engine->irq_get = gen8_logical_ring_get_irq;
	engine->irq_put = gen8_logical_ring_put_irq;
	engine->emit_bb_start = gen8_emit_bb_start;
2056
	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2057 2058
		engine->get_seqno = bxt_a_get_seqno;
		engine->set_seqno = bxt_a_set_seqno;
2059
	} else {
2060 2061
		engine->get_seqno = gen8_get_seqno;
		engine->set_seqno = gen8_set_seqno;
2062 2063 2064
	}
}

2065
static inline void
2066
logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
2067
{
2068 2069
	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2070 2071
}

2072
static int
2073
logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
2074
{
2075
	struct intel_context *dctx = to_i915(dev)->kernel_context;
2076 2077 2078
	int ret;

	/* Intentionally left blank. */
2079
	engine->buffer = NULL;
2080

2081 2082 2083 2084 2085
	engine->dev = dev;
	INIT_LIST_HEAD(&engine->active_list);
	INIT_LIST_HEAD(&engine->request_list);
	i915_gem_batch_pool_init(dev, &engine->batch_pool);
	init_waitqueue_head(&engine->irq_queue);
2086

2087 2088 2089 2090
	INIT_LIST_HEAD(&engine->buffers);
	INIT_LIST_HEAD(&engine->execlist_queue);
	INIT_LIST_HEAD(&engine->execlist_retired_req_list);
	spin_lock_init(&engine->execlist_lock);
2091

2092
	logical_ring_init_platform_invariants(engine);
2093

2094
	ret = i915_cmd_parser_init_ring(engine);
2095
	if (ret)
2096
		goto error;
2097

2098
	ret = intel_lr_context_deferred_alloc(dctx, engine);
2099
	if (ret)
2100
		goto error;
2101 2102

	/* As this is the default context, always pin it */
2103
	ret = intel_lr_context_do_pin(dctx, engine);
2104 2105 2106
	if (ret) {
		DRM_ERROR(
			"Failed to pin and map ringbuffer %s: %d\n",
2107
			engine->name, ret);
2108
		goto error;
2109
	}
2110

2111 2112 2113
	return 0;

error:
2114
	intel_logical_ring_cleanup(engine);
2115
	return ret;
2116 2117 2118 2119 2120
}

static int logical_render_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2121
	struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2122
	int ret;
2123

2124 2125 2126 2127 2128
	engine->name = "render ring";
	engine->id = RCS;
	engine->exec_id = I915_EXEC_RENDER;
	engine->guc_id = GUC_RENDER_ENGINE;
	engine->mmio_base = RENDER_RING_BASE;
2129

2130
	logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT);
2131
	if (HAS_L3_DPF(dev))
2132
		engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2133

2134
	logical_ring_default_vfuncs(dev, engine);
2135 2136

	/* Override some for render ring. */
2137
	if (INTEL_INFO(dev)->gen >= 9)
2138
		engine->init_hw = gen9_init_render_ring;
2139
	else
2140 2141 2142 2143 2144
		engine->init_hw = gen8_init_render_ring;
	engine->init_context = gen8_init_rcs_context;
	engine->cleanup = intel_fini_pipe_control;
	engine->emit_flush = gen8_emit_flush_render;
	engine->emit_request = gen8_emit_request_render;
2145

2146
	engine->dev = dev;
2147

2148
	ret = intel_init_pipe_control(engine);
2149 2150 2151
	if (ret)
		return ret;

2152
	ret = intel_init_workaround_bb(engine);
2153 2154 2155 2156 2157 2158 2159 2160 2161 2162
	if (ret) {
		/*
		 * We continue even if we fail to initialize WA batch
		 * because we only expect rare glitches but nothing
		 * critical to prevent us from using GPU
		 */
		DRM_ERROR("WA batch buffer initialization failed: %d\n",
			  ret);
	}

2163
	ret = logical_ring_init(dev, engine);
2164
	if (ret) {
2165
		lrc_destroy_wa_ctx_obj(engine);
2166
	}
2167 2168

	return ret;
2169 2170 2171 2172 2173
}

static int logical_bsd_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2174
	struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2175

2176 2177 2178 2179 2180
	engine->name = "bsd ring";
	engine->id = VCS;
	engine->exec_id = I915_EXEC_BSD;
	engine->guc_id = GUC_VIDEO_ENGINE;
	engine->mmio_base = GEN6_BSD_RING_BASE;
2181

2182 2183
	logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT);
	logical_ring_default_vfuncs(dev, engine);
2184

2185
	return logical_ring_init(dev, engine);
2186 2187 2188 2189 2190
}

static int logical_bsd2_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2191
	struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2192

2193 2194 2195 2196 2197
	engine->name = "bsd2 ring";
	engine->id = VCS2;
	engine->exec_id = I915_EXEC_BSD;
	engine->guc_id = GUC_VIDEO_ENGINE2;
	engine->mmio_base = GEN8_BSD2_RING_BASE;
2198

2199 2200
	logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT);
	logical_ring_default_vfuncs(dev, engine);
2201

2202
	return logical_ring_init(dev, engine);
2203 2204 2205 2206 2207
}

static int logical_blt_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2208
	struct intel_engine_cs *engine = &dev_priv->engine[BCS];
2209

2210 2211 2212 2213 2214
	engine->name = "blitter ring";
	engine->id = BCS;
	engine->exec_id = I915_EXEC_BLT;
	engine->guc_id = GUC_BLITTER_ENGINE;
	engine->mmio_base = BLT_RING_BASE;
2215

2216 2217
	logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT);
	logical_ring_default_vfuncs(dev, engine);
2218

2219
	return logical_ring_init(dev, engine);
2220 2221 2222 2223 2224
}

static int logical_vebox_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2225
	struct intel_engine_cs *engine = &dev_priv->engine[VECS];
2226

2227 2228 2229 2230 2231
	engine->name = "video enhancement ring";
	engine->id = VECS;
	engine->exec_id = I915_EXEC_VEBOX;
	engine->guc_id = GUC_VIDEOENHANCE_ENGINE;
	engine->mmio_base = VEBOX_RING_BASE;
2232

2233 2234
	logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT);
	logical_ring_default_vfuncs(dev, engine);
2235

2236
	return logical_ring_init(dev, engine);
2237 2238
}

2239 2240 2241 2242 2243
/**
 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
 * @dev: DRM device.
 *
 * This function inits the engines for an Execlists submission style (the equivalent in the
2244
 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2245 2246 2247 2248
 * those engines that are present in the hardware.
 *
 * Return: non-zero if the initialization failed.
 */
2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284
int intel_logical_rings_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = logical_render_ring_init(dev);
	if (ret)
		return ret;

	if (HAS_BSD(dev)) {
		ret = logical_bsd_ring_init(dev);
		if (ret)
			goto cleanup_render_ring;
	}

	if (HAS_BLT(dev)) {
		ret = logical_blt_ring_init(dev);
		if (ret)
			goto cleanup_bsd_ring;
	}

	if (HAS_VEBOX(dev)) {
		ret = logical_vebox_ring_init(dev);
		if (ret)
			goto cleanup_blt_ring;
	}

	if (HAS_BSD2(dev)) {
		ret = logical_bsd2_ring_init(dev);
		if (ret)
			goto cleanup_vebox_ring;
	}

	return 0;

cleanup_vebox_ring:
2285
	intel_logical_ring_cleanup(&dev_priv->engine[VECS]);
2286
cleanup_blt_ring:
2287
	intel_logical_ring_cleanup(&dev_priv->engine[BCS]);
2288
cleanup_bsd_ring:
2289
	intel_logical_ring_cleanup(&dev_priv->engine[VCS]);
2290
cleanup_render_ring:
2291
	intel_logical_ring_cleanup(&dev_priv->engine[RCS]);
2292 2293 2294 2295

	return ret;
}

2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338
static u32
make_rpcs(struct drm_device *dev)
{
	u32 rpcs = 0;

	/*
	 * No explicit RPCS request is needed to ensure full
	 * slice/subslice/EU enablement prior to Gen9.
	*/
	if (INTEL_INFO(dev)->gen < 9)
		return 0;

	/*
	 * Starting in Gen9, render power gating can leave
	 * slice/subslice/EU in a partially enabled state. We
	 * must make an explicit request through RPCS for full
	 * enablement.
	*/
	if (INTEL_INFO(dev)->has_slice_pg) {
		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
		rpcs |= INTEL_INFO(dev)->slice_total <<
			GEN8_RPCS_S_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	if (INTEL_INFO(dev)->has_subslice_pg) {
		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
		rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
			GEN8_RPCS_SS_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	if (INTEL_INFO(dev)->has_eu_pg) {
		rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
			GEN8_RPCS_EU_MIN_SHIFT;
		rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
			GEN8_RPCS_EU_MAX_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	return rpcs;
}

2339
static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2340 2341 2342
{
	u32 indirect_ctx_offset;

2343
	switch (INTEL_INFO(engine->dev)->gen) {
2344
	default:
2345
		MISSING_CASE(INTEL_INFO(engine->dev)->gen);
2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359
		/* fall through */
	case 9:
		indirect_ctx_offset =
			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
		break;
	case 8:
		indirect_ctx_offset =
			GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
		break;
	}

	return indirect_ctx_offset;
}

2360 2361
static int
populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
2362 2363
		    struct intel_engine_cs *engine,
		    struct intel_ringbuffer *ringbuf)
2364
{
2365
	struct drm_device *dev = engine->dev;
2366
	struct drm_i915_private *dev_priv = dev->dev_private;
2367
	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2368 2369 2370 2371
	struct page *page;
	uint32_t *reg_state;
	int ret;

2372 2373 2374
	if (!ppgtt)
		ppgtt = dev_priv->mm.aliasing_ppgtt;

2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390
	ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
	if (ret) {
		DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
		return ret;
	}

	ret = i915_gem_object_get_pages(ctx_obj);
	if (ret) {
		DRM_DEBUG_DRIVER("Could not get object pages\n");
		return ret;
	}

	i915_gem_object_pin_pages(ctx_obj);

	/* The second page of the context object contains some fields which must
	 * be set up prior to the first execution. */
2391
	page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2392 2393 2394 2395 2396 2397 2398
	reg_state = kmap_atomic(page);

	/* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
	 * commands followed by (reg, value) pairs. The values we are setting here are
	 * only for the first context restore: on a subsequent save, the GPU will
	 * recreate this batchbuffer with new values (including all the missing
	 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2399
	reg_state[CTX_LRI_HEADER_0] =
2400 2401 2402
		MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
	ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
		       RING_CONTEXT_CONTROL(engine),
2403 2404
		       _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
					  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2405 2406
					  (HAS_RESOURCE_STREAMER(dev) ?
					    CTX_CTRL_RS_CTX_ENABLE : 0)));
2407 2408 2409 2410
	ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
		       0);
2411 2412 2413
	/* Ring buffer start address is not known until the buffer is pinned.
	 * It is written to the context image in execlists_update_context()
	 */
2414 2415 2416 2417
	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
		       RING_START(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
		       RING_CTL(engine->mmio_base),
2418
		       ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
2419 2420 2421 2422 2423 2424
	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
		       RING_BBADDR_UDW(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
		       RING_BBADDR(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
		       RING_BBSTATE(engine->mmio_base),
2425
		       RING_BB_PPGTT);
2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
		       RING_SBBADDR_UDW(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
		       RING_SBBADDR(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
		       RING_SBBSTATE(engine->mmio_base), 0);
	if (engine->id == RCS) {
		ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
			       RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
			       RING_INDIRECT_CTX(engine->mmio_base), 0);
		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
			       RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
		if (engine->wa_ctx.obj) {
			struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2441 2442 2443 2444 2445 2446 2447
			uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);

			reg_state[CTX_RCS_INDIRECT_CTX+1] =
				(ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
				(wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);

			reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2448
				intel_lr_indirect_ctx_offset(engine) << 6;
2449 2450 2451 2452 2453

			reg_state[CTX_BB_PER_CTX_PTR+1] =
				(ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
				0x01;
		}
2454
	}
2455
	reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2456 2457
	ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
		       RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2458
	/* PDP values well be assigned later if needed */
2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474
	ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
		       0);
2475

2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487
	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
		/* 64b PPGTT (48bit canonical)
		 * PDP0_DESCRIPTOR contains the base address to PML4 and
		 * other PDP Descriptors are ignored.
		 */
		ASSIGN_CTX_PML4(ppgtt, reg_state);
	} else {
		/* 32b PPGTT
		 * PDP*_DESCRIPTOR contains the base address of space supported.
		 * With dynamic page allocation, PDPs may not be allocated at
		 * this point. Point the unallocated PDPs to the scratch page
		 */
2488
		execlists_update_context_pdps(ppgtt, reg_state);
2489 2490
	}

2491
	if (engine->id == RCS) {
2492
		reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2493 2494
		ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
			       make_rpcs(dev));
2495 2496 2497 2498 2499 2500 2501 2502
	}

	kunmap_atomic(reg_state);
	i915_gem_object_unpin_pages(ctx_obj);

	return 0;
}

2503 2504 2505 2506 2507 2508 2509 2510
/**
 * intel_lr_context_free() - free the LRC specific bits of a context
 * @ctx: the LR context to free.
 *
 * The real context freeing is done in i915_gem_context_free: this only
 * takes care of the bits that are LRC related: the per-engine backing
 * objects and the logical ringbuffer.
 */
2511 2512
void intel_lr_context_free(struct intel_context *ctx)
{
2513 2514
	int i;

2515
	for (i = I915_NUM_ENGINES; --i >= 0; ) {
D
Dave Gordon 已提交
2516
		struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
2517
		struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2518

D
Dave Gordon 已提交
2519 2520
		if (!ctx_obj)
			continue;
2521

D
Dave Gordon 已提交
2522 2523 2524
		if (ctx == ctx->i915->kernel_context) {
			intel_unpin_ringbuffer_obj(ringbuf);
			i915_gem_object_ggtt_unpin(ctx_obj);
2525
		}
D
Dave Gordon 已提交
2526 2527 2528 2529

		WARN_ON(ctx->engine[i].pin_count);
		intel_ringbuffer_free(ringbuf);
		drm_gem_object_unreference(&ctx_obj->base);
2530 2531 2532
	}
}

2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546
/**
 * intel_lr_context_size() - return the size of the context for an engine
 * @ring: which engine to find the context size for
 *
 * Each engine may require a different amount of space for a context image,
 * so when allocating (or copying) an image, this function can be used to
 * find the right size for the specific engine.
 *
 * Return: size (in bytes) of an engine-specific context image
 *
 * Note: this size includes the HWSP, which is part of the context image
 * in LRC mode, but does not include the "shared data page" used with
 * GuC submission. The caller should account for this if using the GuC.
 */
2547
uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2548 2549 2550
{
	int ret = 0;

2551
	WARN_ON(INTEL_INFO(engine->dev)->gen < 8);
2552

2553
	switch (engine->id) {
2554
	case RCS:
2555
		if (INTEL_INFO(engine->dev)->gen >= 9)
2556 2557 2558
			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
		else
			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2559 2560 2561 2562 2563 2564 2565 2566 2567 2568
		break;
	case VCS:
	case BCS:
	case VECS:
	case VCS2:
		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
		break;
	}

	return ret;
2569 2570
}

2571 2572
static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine,
					   struct drm_i915_gem_object *default_ctx_obj)
2573
{
2574
	struct drm_i915_private *dev_priv = engine->dev->dev_private;
2575
	struct page *page;
2576

2577
	/* The HWSP is part of the default context object in LRC mode. */
2578
	engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj)
2579 2580
			+ LRC_PPHWSP_PN * PAGE_SIZE;
	page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN);
2581 2582
	engine->status_page.page_addr = kmap(page);
	engine->status_page.obj = default_ctx_obj;
2583

2584 2585 2586
	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
			(u32)engine->status_page.gfx_addr);
	POSTING_READ(RING_HWS_PGA(engine->mmio_base));
2587 2588
}

2589
/**
2590
 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2591 2592 2593 2594 2595 2596 2597 2598 2599
 * @ctx: LR context to create.
 * @ring: engine to be used with the context.
 *
 * This function can be called more than once, with different engines, if we plan
 * to use the context with them. The context backing objects and the ringbuffers
 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
 * the creation is a deferred call: it's better to make sure first that we need to use
 * a given ring with the context.
 *
2600
 * Return: non-zero on error.
2601
 */
2602 2603

int intel_lr_context_deferred_alloc(struct intel_context *ctx,
2604
				    struct intel_engine_cs *engine)
2605
{
2606
	struct drm_device *dev = engine->dev;
2607 2608
	struct drm_i915_gem_object *ctx_obj;
	uint32_t context_size;
2609
	struct intel_ringbuffer *ringbuf;
2610 2611
	int ret;

2612
	WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2613
	WARN_ON(ctx->engine[engine->id].state);
2614

2615
	context_size = round_up(intel_lr_context_size(engine), 4096);
2616

2617 2618 2619
	/* One extra page as the sharing data between driver and GuC */
	context_size += PAGE_SIZE * LRC_PPHWSP_PN;

2620
	ctx_obj = i915_gem_alloc_object(dev, context_size);
2621 2622 2623
	if (!ctx_obj) {
		DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
		return -ENOMEM;
2624 2625
	}

2626
	ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE);
2627 2628
	if (IS_ERR(ringbuf)) {
		ret = PTR_ERR(ringbuf);
2629
		goto error_deref_obj;
2630 2631
	}

2632
	ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf);
2633 2634
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2635
		goto error_ringbuf;
2636 2637
	}

2638 2639
	ctx->engine[engine->id].ringbuf = ringbuf;
	ctx->engine[engine->id].state = ctx_obj;
2640

2641
	if (ctx != ctx->i915->kernel_context && engine->init_context) {
2642
		struct drm_i915_gem_request *req;
2643

2644
		req = i915_gem_request_alloc(engine, ctx);
2645 2646 2647
		if (IS_ERR(req)) {
			ret = PTR_ERR(req);
			DRM_ERROR("ring create req: %d\n", ret);
2648
			goto error_ringbuf;
2649 2650
		}

2651
		ret = engine->init_context(req);
2652 2653 2654 2655 2656 2657 2658
		if (ret) {
			DRM_ERROR("ring init context: %d\n",
				ret);
			i915_gem_request_cancel(req);
			goto error_ringbuf;
		}
		i915_add_request_no_flush(req);
2659
	}
2660
	return 0;
2661

2662 2663
error_ringbuf:
	intel_ringbuffer_free(ringbuf);
2664
error_deref_obj:
2665
	drm_gem_object_unreference(&ctx_obj->base);
2666 2667
	ctx->engine[engine->id].ringbuf = NULL;
	ctx->engine[engine->id].state = NULL;
2668
	return ret;
2669
}
2670 2671 2672 2673 2674

void intel_lr_context_reset(struct drm_device *dev,
			struct intel_context *ctx)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2675
	struct intel_engine_cs *engine;
2676 2677
	int i;

2678
	for_each_engine(engine, dev_priv, i) {
2679
		struct drm_i915_gem_object *ctx_obj =
2680
				ctx->engine[engine->id].state;
2681
		struct intel_ringbuffer *ringbuf =
2682
				ctx->engine[engine->id].ringbuf;
2683 2684 2685 2686 2687 2688 2689 2690 2691 2692
		uint32_t *reg_state;
		struct page *page;

		if (!ctx_obj)
			continue;

		if (i915_gem_object_get_pages(ctx_obj)) {
			WARN(1, "Failed get_pages for context obj\n");
			continue;
		}
2693
		page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704
		reg_state = kmap_atomic(page);

		reg_state[CTX_RING_HEAD+1] = 0;
		reg_state[CTX_RING_TAIL+1] = 0;

		kunmap_atomic(reg_state);

		ringbuf->head = 0;
		ringbuf->tail = 0;
	}
}