intel_lrc.c 79.0 KB
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/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky <ben@bwidawsk.net>
 *    Michel Thierry <michel.thierry@intel.com>
 *    Thomas Daniel <thomas.daniel@intel.com>
 *    Oscar Mateo <oscar.mateo@intel.com>
 *
 */

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/**
 * DOC: Logical Rings, Logical Ring Contexts and Execlists
 *
 * Motivation:
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 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
 * These expanded contexts enable a number of new abilities, especially
 * "Execlists" (also implemented in this file).
 *
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 * One of the main differences with the legacy HW contexts is that logical
 * ring contexts incorporate many more things to the context's state, like
 * PDPs or ringbuffer control registers:
 *
 * The reason why PDPs are included in the context is straightforward: as
 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
 * instead, the GPU will do it for you on the context switch.
 *
 * But, what about the ringbuffer control registers (head, tail, etc..)?
 * shouldn't we just need a set of those per engine command streamer? This is
 * where the name "Logical Rings" starts to make sense: by virtualizing the
 * rings, the engine cs shifts to a new "ring buffer" with every context
 * switch. When you want to submit a workload to the GPU you: A) choose your
 * context, B) find its appropriate virtualized ring, C) write commands to it
 * and then, finally, D) tell the GPU to switch to that context.
 *
 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
 * to a contexts is via a context execution list, ergo "Execlists".
 *
 * LRC implementation:
 * Regarding the creation of contexts, we have:
 *
 * - One global default context.
 * - One local default context for each opened fd.
 * - One local extra context for each context create ioctl call.
 *
 * Now that ringbuffers belong per-context (and not per-engine, like before)
 * and that contexts are uniquely tied to a given engine (and not reusable,
 * like before) we need:
 *
 * - One ringbuffer per-engine inside each context.
 * - One backing object per-engine inside each context.
 *
 * The global default context starts its life with these new objects fully
 * allocated and populated. The local default context for each opened fd is
 * more complex, because we don't know at creation time which engine is going
 * to use them. To handle this, we have implemented a deferred creation of LR
 * contexts:
 *
 * The local context starts its life as a hollow or blank holder, that only
 * gets populated for a given engine once we receive an execbuffer. If later
 * on we receive another execbuffer ioctl for the same context but a different
 * engine, we allocate/populate a new ringbuffer and context backing object and
 * so on.
 *
 * Finally, regarding local contexts created using the ioctl call: as they are
 * only allowed with the render ring, we can allocate & populate them right
 * away (no need to defer anything, at least for now).
 *
 * Execlists implementation:
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 * Execlists are the new method by which, on gen8+ hardware, workloads are
 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
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 * This method works as follows:
 *
 * When a request is committed, its commands (the BB start and any leading or
 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
 * for the appropriate context. The tail pointer in the hardware context is not
 * updated at this time, but instead, kept by the driver in the ringbuffer
 * structure. A structure representing this request is added to a request queue
 * for the appropriate engine: this structure contains a copy of the context's
 * tail after the request was written to the ring buffer and a pointer to the
 * context itself.
 *
 * If the engine's request queue was empty before the request was added, the
 * queue is processed immediately. Otherwise the queue will be processed during
 * a context switch interrupt. In any case, elements on the queue will get sent
 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 * globally unique 20-bits submission ID.
 *
 * When execution of a request completes, the GPU updates the context status
 * buffer with a context complete event and generates a context switch interrupt.
 * During the interrupt handling, the driver examines the events in the buffer:
 * for each context complete event, if the announced ID matches that on the head
 * of the request queue, then that request is retired and removed from the queue.
 *
 * After processing, if any requests were retired and the queue is not empty
 * then a new execution list can be submitted. The two requests at the front of
 * the queue are next to be submitted but since a context may not occur twice in
 * an execution list, if subsequent requests have the same ID as the first then
 * the two requests must be combined. This is done simply by discarding requests
 * at the head of the queue until either only one requests is left (in which case
 * we use a NULL second context) or the first two requests have unique IDs.
 *
 * By always executing the first two requests in the queue the driver ensures
 * that the GPU is kept as busy as possible. In the case where a single context
 * completes but a second context is still executing, the request for this second
 * context will be at the head of the queue when we remove the first one. This
 * request will then be resubmitted along with a new request for a different context,
 * which will cause the hardware to continue executing the second request and queue
 * the new request (the GPU detects the condition of a context getting preempted
 * with the same context and optimizes the context switch flow by not doing
 * preemption, but just sampling the new tail pointer).
 *
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 */

#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
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#include "intel_mocs.h"
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#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
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#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)

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#define RING_EXECLIST_QFULL		(1 << 0x2)
#define RING_EXECLIST1_VALID		(1 << 0x3)
#define RING_EXECLIST0_VALID		(1 << 0x4)
#define RING_EXECLIST_ACTIVE_STATUS	(3 << 0xE)
#define RING_EXECLIST1_ACTIVE		(1 << 0x11)
#define RING_EXECLIST0_ACTIVE		(1 << 0x12)

#define GEN8_CTX_STATUS_IDLE_ACTIVE	(1 << 0)
#define GEN8_CTX_STATUS_PREEMPTED	(1 << 1)
#define GEN8_CTX_STATUS_ELEMENT_SWITCH	(1 << 2)
#define GEN8_CTX_STATUS_ACTIVE_IDLE	(1 << 3)
#define GEN8_CTX_STATUS_COMPLETE	(1 << 4)
#define GEN8_CTX_STATUS_LITE_RESTORE	(1 << 15)
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#define CTX_LRI_HEADER_0		0x01
#define CTX_CONTEXT_CONTROL		0x02
#define CTX_RING_HEAD			0x04
#define CTX_RING_TAIL			0x06
#define CTX_RING_BUFFER_START		0x08
#define CTX_RING_BUFFER_CONTROL		0x0a
#define CTX_BB_HEAD_U			0x0c
#define CTX_BB_HEAD_L			0x0e
#define CTX_BB_STATE			0x10
#define CTX_SECOND_BB_HEAD_U		0x12
#define CTX_SECOND_BB_HEAD_L		0x14
#define CTX_SECOND_BB_STATE		0x16
#define CTX_BB_PER_CTX_PTR		0x18
#define CTX_RCS_INDIRECT_CTX		0x1a
#define CTX_RCS_INDIRECT_CTX_OFFSET	0x1c
#define CTX_LRI_HEADER_1		0x21
#define CTX_CTX_TIMESTAMP		0x22
#define CTX_PDP3_UDW			0x24
#define CTX_PDP3_LDW			0x26
#define CTX_PDP2_UDW			0x28
#define CTX_PDP2_LDW			0x2a
#define CTX_PDP1_UDW			0x2c
#define CTX_PDP1_LDW			0x2e
#define CTX_PDP0_UDW			0x30
#define CTX_PDP0_LDW			0x32
#define CTX_LRI_HEADER_2		0x41
#define CTX_R_PWR_CLK_STATE		0x42
#define CTX_GPGPU_CSR_BASE_ADDRESS	0x44

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#define GEN8_CTX_VALID (1<<0)
#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
#define GEN8_CTX_FORCE_RESTORE (1<<2)
#define GEN8_CTX_L3LLC_COHERENT (1<<5)
#define GEN8_CTX_PRIVILEGE (1<<8)
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#define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
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	(reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
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	(reg_state)[(pos)+1] = (val); \
} while (0)

#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {		\
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	const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n));	\
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	reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
	reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
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} while (0)
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#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
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	reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
	reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
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} while (0)
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enum {
	ADVANCED_CONTEXT = 0,
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	LEGACY_32B_CONTEXT,
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	ADVANCED_AD_CONTEXT,
	LEGACY_64B_CONTEXT
};
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#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
#define GEN8_CTX_ADDRESSING_MODE(dev)  (USES_FULL_48BIT_PPGTT(dev) ?\
		LEGACY_64B_CONTEXT :\
		LEGACY_32B_CONTEXT)
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enum {
	FAULT_AND_HANG = 0,
	FAULT_AND_HALT, /* Debug only */
	FAULT_AND_STREAM,
	FAULT_AND_CONTINUE /* Unsupported */
};
#define GEN8_CTX_ID_SHIFT 32
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#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT  0x17
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static int intel_lr_context_pin(struct intel_context *ctx,
				struct intel_engine_cs *engine);
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static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
		struct drm_i915_gem_object *default_ctx_obj);

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/**
 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 * @dev: DRM device.
 * @enable_execlists: value of i915.enable_execlists module parameter.
 *
 * Only certain platforms support Execlists (the prerequisites being
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 * support for Logical Ring Contexts and Aliasing PPGTT or better).
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 *
 * Return: 1 if Execlists is supported and has to be enabled.
 */
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int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
{
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	WARN_ON(i915.enable_ppgtt == -1);

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	/* On platforms with execlist available, vGPU will only
	 * support execlist mode, no ring buffer mode.
	 */
	if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
		return 1;

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	if (INTEL_INFO(dev)->gen >= 9)
		return 1;

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	if (enable_execlists == 0)
		return 0;

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	if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
	    i915.use_mmio_flip >= 0)
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		return 1;

	return 0;
}
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static void
logical_ring_init_platform_invariants(struct intel_engine_cs *ring)
{
	struct drm_device *dev = ring->dev;

	ring->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
					IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
					(ring->id == VCS || ring->id == VCS2);

	ring->ctx_desc_template = GEN8_CTX_VALID;
	ring->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
				   GEN8_CTX_ADDRESSING_MODE_SHIFT;
	if (IS_GEN8(dev))
		ring->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
	ring->ctx_desc_template |= GEN8_CTX_PRIVILEGE;

	/* TODO: WaDisableLiteRestore when we start using semaphore
	 * signalling between Command Streamers */
	/* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */

	/* WaEnableForceRestoreInCtxtDescForVCS:skl */
	/* WaEnableForceRestoreInCtxtDescForVCS:bxt */
	if (ring->disable_lite_restore_wa)
		ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
}

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/**
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 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
 * 					  descriptor for a pinned context
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 *
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 * @ctx: Context to work on
 * @ring: Engine the descriptor will be used with
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 *
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 * The context descriptor encodes various attributes of a context,
 * including its GTT address and some flags. Because it's fairly
 * expensive to calculate, we'll just do it once and cache the result,
 * which remains valid until the context is unpinned.
 *
 * This is what a descriptor looks like, from LSB to MSB:
 *    bits 0-11:    flags, GEN8_CTX_* (cached in ctx_desc_template)
 *    bits 12-31:    LRCA, GTT address of (the HWSP of) this context
 *    bits 32-51:    ctx ID, a globally unique tag (the LRCA again!)
 *    bits 52-63:    reserved, may encode the engine ID (for GuC)
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 */
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static void
intel_lr_context_descriptor_update(struct intel_context *ctx,
				   struct intel_engine_cs *ring)
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{
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	uint64_t lrca, desc;
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	lrca = ctx->engine[ring->id].lrc_vma->node.start +
	       LRC_PPHWSP_PN * PAGE_SIZE;
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	desc = ring->ctx_desc_template;			   /* bits  0-11 */
	desc |= lrca;					   /* bits 12-31 */
	desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */
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	ctx->engine[ring->id].lrc_desc = desc;
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}

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uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
				     struct intel_engine_cs *ring)
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{
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	return ctx->engine[ring->id].lrc_desc;
}
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/**
 * intel_execlists_ctx_id() - get the Execlists Context ID
 * @ctx: Context to get the ID for
 * @ring: Engine to get the ID for
 *
 * Do not confuse with ctx->id! Unfortunately we have a name overload
 * here: the old context ID we pass to userspace as a handler so that
 * they can refer to a context, and the new context ID we pass to the
 * ELSP so that the GPU can inform us of the context status via
 * interrupts.
 *
 * The context ID is a portion of the context descriptor, so we can
 * just extract the required part from the cached descriptor.
 *
 * Return: 20-bits globally unique context ID.
 */
u32 intel_execlists_ctx_id(struct intel_context *ctx,
			   struct intel_engine_cs *ring)
{
	return intel_lr_context_descriptor(ctx, ring) >> GEN8_CTX_ID_SHIFT;
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}

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static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
				 struct drm_i915_gem_request *rq1)
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{
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	struct intel_engine_cs *ring = rq0->ring;
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	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	uint64_t desc[2];
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	if (rq1) {
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		desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring);
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		rq1->elsp_submitted++;
	} else {
		desc[1] = 0;
	}
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	desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring);
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	rq0->elsp_submitted++;
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	/* You must always write both descriptors in the order below. */
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	spin_lock(&dev_priv->uncore.lock);
	intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
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	I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
	I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
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	I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));
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	/* The context is automatically loaded after the following */
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	I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
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	/* ELSP is a wo register, use another nearby reg for posting */
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	POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));
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	intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
	spin_unlock(&dev_priv->uncore.lock);
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}

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static int execlists_update_context(struct drm_i915_gem_request *rq)
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{
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	struct intel_engine_cs *ring = rq->ring;
	struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
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	uint32_t *reg_state = rq->ctx->engine[ring->id].lrc_reg_state;
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	reg_state[CTX_RING_TAIL+1] = rq->tail;
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	if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
		/* True 32b PPGTT with dynamic page allocation: update PDP
		 * registers and point the unallocated PDPs to scratch page.
		 * PML4 is allocated during ppgtt init, so this is not needed
		 * in 48-bit mode.
		 */
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		ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
	}

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	return 0;
}

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static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
				      struct drm_i915_gem_request *rq1)
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{
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	execlists_update_context(rq0);
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	if (rq1)
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		execlists_update_context(rq1);
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	execlists_elsp_write(rq0, rq1);
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}

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static void execlists_context_unqueue(struct intel_engine_cs *ring)
{
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	struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
	struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
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	assert_spin_locked(&ring->execlist_lock);
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	/*
	 * If irqs are not active generate a warning as batches that finish
	 * without the irqs may get lost and a GPU Hang may occur.
	 */
	WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));

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	if (list_empty(&ring->execlist_queue))
		return;

	/* Try to read in pairs */
	list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
				 execlist_link) {
		if (!req0) {
			req0 = cursor;
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		} else if (req0->ctx == cursor->ctx) {
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			/* Same ctx: ignore first request, as second request
			 * will update tail past first request's workload */
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			cursor->elsp_submitted = req0->elsp_submitted;
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			list_move_tail(&req0->execlist_link,
				       &ring->execlist_retired_req_list);
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			req0 = cursor;
		} else {
			req1 = cursor;
			break;
		}
	}

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	if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
		/*
		 * WaIdleLiteRestore: make sure we never cause a lite
		 * restore with HEAD==TAIL
		 */
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		if (req0->elsp_submitted) {
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			/*
			 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
			 * as we resubmit the request. See gen8_emit_request()
			 * for where we prepare the padding after the end of the
			 * request.
			 */
			struct intel_ringbuffer *ringbuf;

			ringbuf = req0->ctx->engine[ring->id].ringbuf;
			req0->tail += 8;
			req0->tail &= ringbuf->size - 1;
		}
	}

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	WARN_ON(req1 && req1->elsp_submitted);

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	execlists_submit_requests(req0, req1);
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}

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static bool execlists_check_remove_request(struct intel_engine_cs *ring,
					   u32 request_id)
{
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	struct drm_i915_gem_request *head_req;
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	assert_spin_locked(&ring->execlist_lock);

	head_req = list_first_entry_or_null(&ring->execlist_queue,
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					    struct drm_i915_gem_request,
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					    execlist_link);

	if (head_req != NULL) {
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		if (intel_execlists_ctx_id(head_req->ctx, ring) == request_id) {
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			WARN(head_req->elsp_submitted == 0,
			     "Never submitted head request\n");

			if (--head_req->elsp_submitted <= 0) {
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				list_move_tail(&head_req->execlist_link,
					       &ring->execlist_retired_req_list);
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				return true;
			}
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		}
	}

	return false;
}

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Ben Widawsky 已提交
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static void get_context_status(struct intel_engine_cs *ring,
			       u8 read_pointer,
			       u32 *status, u32 *context_id)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;

	if (WARN_ON(read_pointer >= GEN8_CSB_ENTRIES))
		return;

	*status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer));
	*context_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer));
}

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/**
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 * intel_lrc_irq_handler() - handle Context Switch interrupts
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 * @ring: Engine Command Streamer to handle.
 *
 * Check the unread Context Status Buffers and manage the submission of new
 * contexts to the ELSP accordingly.
 */
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void intel_lrc_irq_handler(struct intel_engine_cs *ring)
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{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	u32 status_pointer;
	u8 read_pointer;
	u8 write_pointer;
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	u32 status = 0;
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	u32 status_id;
	u32 submit_contexts = 0;

	status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));

	read_pointer = ring->next_context_status_buffer;
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	write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
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	if (read_pointer > write_pointer)
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		write_pointer += GEN8_CSB_ENTRIES;
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	spin_lock(&ring->execlist_lock);

	while (read_pointer < write_pointer) {
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Ben Widawsky 已提交
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		get_context_status(ring, ++read_pointer % GEN8_CSB_ENTRIES,
				   &status, &status_id);
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		if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
			continue;

557 558 559 560 561 562 563 564
		if (status & GEN8_CTX_STATUS_PREEMPTED) {
			if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
				if (execlists_check_remove_request(ring, status_id))
					WARN(1, "Lite Restored request removed from queue\n");
			} else
				WARN(1, "Preemption without Lite Restore\n");
		}

B
Ben Widawsky 已提交
565 566
		if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
		    (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
567 568 569 570 571
			if (execlists_check_remove_request(ring, status_id))
				submit_contexts++;
		}
	}

572
	if (ring->disable_lite_restore_wa) {
573 574 575 576 577
		/* Prevent a ctx to preempt itself */
		if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) &&
		    (submit_contexts != 0))
			execlists_context_unqueue(ring);
	} else if (submit_contexts != 0) {
578
		execlists_context_unqueue(ring);
579
	}
580 581 582

	spin_unlock(&ring->execlist_lock);

583 584 585
	if (unlikely(submit_contexts > 2))
		DRM_ERROR("More than two context complete events?\n");

586
	ring->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;
587

588 589
	/* Update the read pointer to the old write pointer. Manual ringbuffer
	 * management ftw </sarcasm> */
590
	I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
591 592
		   _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
				 ring->next_context_status_buffer << 8));
593 594
}

595
static int execlists_context_queue(struct drm_i915_gem_request *request)
596
{
597
	struct intel_engine_cs *ring = request->ring;
598
	struct drm_i915_gem_request *cursor;
599
	int num_elements = 0;
600

601
	if (request->ctx != request->i915->kernel_context)
602
		intel_lr_context_pin(request->ctx, ring);
603

604 605
	i915_gem_request_reference(request);

606
	spin_lock_irq(&ring->execlist_lock);
607

608 609 610 611 612
	list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
		if (++num_elements > 2)
			break;

	if (num_elements > 2) {
613
		struct drm_i915_gem_request *tail_req;
614 615

		tail_req = list_last_entry(&ring->execlist_queue,
616
					   struct drm_i915_gem_request,
617 618
					   execlist_link);

619
		if (request->ctx == tail_req->ctx) {
620
			WARN(tail_req->elsp_submitted != 0,
621
				"More than 2 already-submitted reqs queued\n");
622 623
			list_move_tail(&tail_req->execlist_link,
				       &ring->execlist_retired_req_list);
624 625 626
		}
	}

627
	list_add_tail(&request->execlist_link, &ring->execlist_queue);
628
	if (num_elements == 0)
629 630
		execlists_context_unqueue(ring);

631
	spin_unlock_irq(&ring->execlist_lock);
632 633 634 635

	return 0;
}

636
static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
637
{
638
	struct intel_engine_cs *ring = req->ring;
639 640 641 642 643 644 645
	uint32_t flush_domains;
	int ret;

	flush_domains = 0;
	if (ring->gpu_caches_dirty)
		flush_domains = I915_GEM_GPU_DOMAINS;

646
	ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
647 648 649 650 651 652 653
	if (ret)
		return ret;

	ring->gpu_caches_dirty = false;
	return 0;
}

654
static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
655 656
				 struct list_head *vmas)
{
657
	const unsigned other_rings = ~intel_ring_flag(req->ring);
658 659 660 661 662 663 664 665
	struct i915_vma *vma;
	uint32_t flush_domains = 0;
	bool flush_chipset = false;
	int ret;

	list_for_each_entry(vma, vmas, exec_list) {
		struct drm_i915_gem_object *obj = vma->obj;

666
		if (obj->active & other_rings) {
667
			ret = i915_gem_object_sync(obj, req->ring, &req);
668 669 670
			if (ret)
				return ret;
		}
671 672 673 674 675 676 677 678 679 680 681 682 683

		if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
			flush_chipset |= i915_gem_clflush_object(obj, false);

		flush_domains |= obj->base.write_domain;
	}

	if (flush_domains & I915_GEM_DOMAIN_GTT)
		wmb();

	/* Unconditionally invalidate gpu caches and ensure that we do flush
	 * any residual writes from the previous batch.
	 */
684
	return logical_ring_invalidate_all_caches(req);
685 686
}

687
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
688
{
D
Dave Gordon 已提交
689
	int ret = 0;
690

691 692
	request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;

693 694 695 696 697 698 699 700 701 702 703 704 705
	if (i915.enable_guc_submission) {
		/*
		 * Check that the GuC has space for the request before
		 * going any further, as the i915_add_request() call
		 * later on mustn't fail ...
		 */
		struct intel_guc *guc = &request->i915->guc;

		ret = i915_guc_wq_check_space(guc->execbuf_client);
		if (ret)
			return ret;
	}

D
Dave Gordon 已提交
706
	if (request->ctx != request->i915->kernel_context)
707
		ret = intel_lr_context_pin(request->ctx, request->ring);
D
Dave Gordon 已提交
708 709

	return ret;
710 711
}

712
static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
713
				       int bytes)
714
{
715 716 717
	struct intel_ringbuffer *ringbuf = req->ringbuf;
	struct intel_engine_cs *ring = req->ring;
	struct drm_i915_gem_request *target;
718 719
	unsigned space;
	int ret;
720 721 722 723

	if (intel_ring_space(ringbuf) >= bytes)
		return 0;

724 725 726
	/* The whole point of reserving space is to not wait! */
	WARN_ON(ringbuf->reserved_in_use);

727
	list_for_each_entry(target, &ring->request_list, list) {
728 729 730 731 732
		/*
		 * The request queue is per-engine, so can contain requests
		 * from multiple ringbuffers. Here, we must ignore any that
		 * aren't from the ringbuffer we're considering.
		 */
733
		if (target->ringbuf != ringbuf)
734 735 736
			continue;

		/* Would completion of this request free enough space? */
737
		space = __intel_ring_space(target->postfix, ringbuf->tail,
738 739
					   ringbuf->size);
		if (space >= bytes)
740 741 742
			break;
	}

743
	if (WARN_ON(&target->list == &ring->request_list))
744 745
		return -ENOSPC;

746
	ret = i915_wait_request(target);
747 748 749
	if (ret)
		return ret;

750 751
	ringbuf->space = space;
	return 0;
752 753 754 755
}

/*
 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
756
 * @request: Request to advance the logical ringbuffer of.
757 758 759 760 761 762
 *
 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 * really happens during submission is that the context and current tail will be placed
 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 * point, the tail *inside* the context is updated and the ELSP written to.
 */
763
static int
764
intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
765
{
766
	struct intel_ringbuffer *ringbuf = request->ringbuf;
767
	struct drm_i915_private *dev_priv = request->i915;
768
	struct intel_engine_cs *engine = request->ring;
769

770 771
	intel_logical_ring_advance(ringbuf);
	request->tail = ringbuf->tail;
772

773 774 775 776 777 778 779 780 781
	/*
	 * Here we add two extra NOOPs as padding to avoid
	 * lite restore of a context with HEAD==TAIL.
	 *
	 * Caller must reserve WA_TAIL_DWORDS for us!
	 */
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);
782

783
	if (intel_ring_stopped(engine))
784
		return 0;
785

786 787 788 789 790 791 792 793 794 795 796
	if (engine->last_context != request->ctx) {
		if (engine->last_context)
			intel_lr_context_unpin(engine->last_context, engine);
		if (request->ctx != request->i915->kernel_context) {
			intel_lr_context_pin(request->ctx, engine);
			engine->last_context = request->ctx;
		} else {
			engine->last_context = NULL;
		}
	}

797 798 799 800
	if (dev_priv->guc.execbuf_client)
		i915_guc_submit(dev_priv->guc.execbuf_client, request);
	else
		execlists_context_queue(request);
801 802

	return 0;
803 804
}

805
static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
806 807 808 809 810 811 812 813 814 815 816 817 818
{
	uint32_t __iomem *virt;
	int rem = ringbuf->size - ringbuf->tail;

	virt = ringbuf->virtual_start + ringbuf->tail;
	rem /= 4;
	while (rem--)
		iowrite32(MI_NOOP, virt++);

	ringbuf->tail = 0;
	intel_ring_update_space(ringbuf);
}

819
static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
820
{
821
	struct intel_ringbuffer *ringbuf = req->ringbuf;
822 823 824 825
	int remain_usable = ringbuf->effective_size - ringbuf->tail;
	int remain_actual = ringbuf->size - ringbuf->tail;
	int ret, total_bytes, wait_bytes = 0;
	bool need_wrap = false;
826

827 828 829 830
	if (ringbuf->reserved_in_use)
		total_bytes = bytes;
	else
		total_bytes = bytes + ringbuf->reserved_size;
831

832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850
	if (unlikely(bytes > remain_usable)) {
		/*
		 * Not enough space for the basic request. So need to flush
		 * out the remainder and then wait for base + reserved.
		 */
		wait_bytes = remain_actual + total_bytes;
		need_wrap = true;
	} else {
		if (unlikely(total_bytes > remain_usable)) {
			/*
			 * The base request will fit but the reserved space
			 * falls off the end. So only need to to wait for the
			 * reserved size after flushing out the remainder.
			 */
			wait_bytes = remain_actual + ringbuf->reserved_size;
			need_wrap = true;
		} else if (total_bytes > ringbuf->space) {
			/* No wrapping required, just waiting. */
			wait_bytes = total_bytes;
851
		}
852 853
	}

854 855
	if (wait_bytes) {
		ret = logical_ring_wait_for_space(req, wait_bytes);
856 857
		if (unlikely(ret))
			return ret;
858 859 860

		if (need_wrap)
			__wrap_ring_buffer(ringbuf);
861 862 863 864 865 866 867 868
	}

	return 0;
}

/**
 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
 *
869
 * @req: The request to start some new work for
870 871 872 873 874 875 876 877 878
 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
 *
 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
 * and also preallocates a request (every workload submission is still mediated through
 * requests, same as it did with legacy ringbuffer submission).
 *
 * Return: non-zero if the ringbuffer is not ready to be written to.
 */
879
int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
880
{
881
	struct drm_i915_private *dev_priv;
882 883
	int ret;

884 885 886
	WARN_ON(req == NULL);
	dev_priv = req->ring->dev->dev_private;

887 888 889 890 891
	ret = i915_gem_check_wedge(&dev_priv->gpu_error,
				   dev_priv->mm.interruptible);
	if (ret)
		return ret;

892
	ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
893 894 895
	if (ret)
		return ret;

896
	req->ringbuf->space -= num_dwords * sizeof(uint32_t);
897 898 899
	return 0;
}

900 901 902 903 904 905 906 907 908 909 910 911 912 913 914
int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
{
	/*
	 * The first call merely notes the reserve request and is common for
	 * all back ends. The subsequent localised _begin() call actually
	 * ensures that the reservation is available. Without the begin, if
	 * the request creator immediately submitted the request without
	 * adding any commands to it then there might not actually be
	 * sufficient room for the submission commands.
	 */
	intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);

	return intel_logical_ring_begin(request, 0);
}

915 916 917 918 919 920 921 922 923 924
/**
 * execlists_submission() - submit a batchbuffer for execution, Execlists style
 * @dev: DRM device.
 * @file: DRM file.
 * @ring: Engine Command Streamer to submit to.
 * @ctx: Context to employ for this submission.
 * @args: execbuffer call arguments.
 * @vmas: list of vmas.
 * @batch_obj: the batchbuffer to submit.
 * @exec_start: batchbuffer start virtual address pointer.
925
 * @dispatch_flags: translated execbuffer call flags.
926 927 928 929 930 931
 *
 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 * away the submission details of the execbuffer ioctl call.
 *
 * Return: non-zero if the submission fails.
 */
932
int intel_execlists_submission(struct i915_execbuffer_params *params,
933
			       struct drm_i915_gem_execbuffer2 *args,
934
			       struct list_head *vmas)
935
{
936 937
	struct drm_device       *dev = params->dev;
	struct intel_engine_cs  *ring = params->ring;
938
	struct drm_i915_private *dev_priv = dev->dev_private;
939 940
	struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
	u64 exec_start;
941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975
	int instp_mode;
	u32 instp_mask;
	int ret;

	instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
	instp_mask = I915_EXEC_CONSTANTS_MASK;
	switch (instp_mode) {
	case I915_EXEC_CONSTANTS_REL_GENERAL:
	case I915_EXEC_CONSTANTS_ABSOLUTE:
	case I915_EXEC_CONSTANTS_REL_SURFACE:
		if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
			DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
			return -EINVAL;
		}

		if (instp_mode != dev_priv->relative_constants_mode) {
			if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
				DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
				return -EINVAL;
			}

			/* The HW changed the meaning on this bit on gen6 */
			instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
		}
		break;
	default:
		DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
		return -EINVAL;
	}

	if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
		DRM_DEBUG("sol reset is gen7 only\n");
		return -EINVAL;
	}

976
	ret = execlists_move_to_gpu(params->request, vmas);
977 978 979 980 981
	if (ret)
		return ret;

	if (ring == &dev_priv->ring[RCS] &&
	    instp_mode != dev_priv->relative_constants_mode) {
982
		ret = intel_logical_ring_begin(params->request, 4);
983 984 985 986 987
		if (ret)
			return ret;

		intel_logical_ring_emit(ringbuf, MI_NOOP);
		intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
988
		intel_logical_ring_emit_reg(ringbuf, INSTPM);
989 990 991 992 993 994
		intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
		intel_logical_ring_advance(ringbuf);

		dev_priv->relative_constants_mode = instp_mode;
	}

995 996 997
	exec_start = params->batch_obj_vm_offset +
		     args->batch_start_offset;

998
	ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);
999 1000 1001
	if (ret)
		return ret;

1002
	trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1003

1004
	i915_gem_execbuffer_move_to_active(vmas, params->request);
1005
	i915_gem_execbuffer_retire_commands(params);
1006

1007 1008 1009
	return 0;
}

1010 1011
void intel_execlists_retire_requests(struct intel_engine_cs *ring)
{
1012
	struct drm_i915_gem_request *req, *tmp;
1013 1014 1015 1016 1017 1018 1019
	struct list_head retired_list;

	WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
	if (list_empty(&ring->execlist_retired_req_list))
		return;

	INIT_LIST_HEAD(&retired_list);
1020
	spin_lock_irq(&ring->execlist_lock);
1021
	list_replace_init(&ring->execlist_retired_req_list, &retired_list);
1022
	spin_unlock_irq(&ring->execlist_lock);
1023 1024

	list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
1025 1026 1027 1028
		struct intel_context *ctx = req->ctx;
		struct drm_i915_gem_object *ctx_obj =
				ctx->engine[ring->id].state;

1029
		if (ctx_obj && (ctx != req->i915->kernel_context))
1030 1031
			intel_lr_context_unpin(ctx, ring);

1032
		list_del(&req->execlist_link);
1033
		i915_gem_request_unreference(req);
1034 1035 1036
	}
}

1037 1038
void intel_logical_ring_stop(struct intel_engine_cs *ring)
{
1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	int ret;

	if (!intel_ring_initialized(ring))
		return;

	ret = intel_ring_idle(ring);
	if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
		DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
			  ring->name, ret);

	/* TODO: Is this correct with Execlists enabled? */
	I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
	if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
		DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
		return;
	}
	I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
1057 1058
}

1059
int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
1060
{
1061
	struct intel_engine_cs *ring = req->ring;
1062 1063 1064 1065 1066
	int ret;

	if (!ring->gpu_caches_dirty)
		return 0;

1067
	ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1068 1069 1070 1071 1072 1073 1074
	if (ret)
		return ret;

	ring->gpu_caches_dirty = false;
	return 0;
}

1075 1076
static int intel_lr_context_do_pin(struct intel_context *ctx,
				   struct intel_engine_cs *ring)
1077
{
1078 1079
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1080 1081
	struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
	struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1082
	struct page *lrc_state_page;
1083
	uint32_t *lrc_reg_state;
1084
	int ret;
1085 1086

	WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1087

1088 1089 1090 1091
	ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
			PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
	if (ret)
		return ret;
1092

1093 1094 1095 1096 1097 1098
	lrc_state_page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
	if (WARN_ON(!lrc_state_page)) {
		ret = -ENODEV;
		goto unpin_ctx_obj;
	}

1099 1100 1101
	ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
	if (ret)
		goto unpin_ctx_obj;
1102

1103 1104
	ctx->engine[ring->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj);
	intel_lr_context_descriptor_update(ctx, ring);
1105 1106 1107
	lrc_reg_state = kmap(lrc_state_page);
	lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start;
	ctx->engine[ring->id].lrc_reg_state = lrc_reg_state;
1108
	ctx_obj->dirty = true;
1109

1110 1111 1112
	/* Invalidate GuC TLB. */
	if (i915.enable_guc_submission)
		I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
1113

1114 1115 1116 1117
	return ret;

unpin_ctx_obj:
	i915_gem_object_ggtt_unpin(ctx_obj);
1118 1119 1120 1121

	return ret;
}

1122 1123
static int intel_lr_context_pin(struct intel_context *ctx,
				struct intel_engine_cs *engine)
1124 1125 1126
{
	int ret = 0;

1127 1128
	if (ctx->engine[engine->id].pin_count++ == 0) {
		ret = intel_lr_context_do_pin(ctx, engine);
1129 1130
		if (ret)
			goto reset_pin_count;
1131 1132

		i915_gem_context_reference(ctx);
1133 1134 1135
	}
	return ret;

1136
reset_pin_count:
1137
	ctx->engine[engine->id].pin_count = 0;
1138 1139 1140
	return ret;
}

1141 1142
void intel_lr_context_unpin(struct intel_context *ctx,
			    struct intel_engine_cs *engine)
1143
{
1144
	struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
1145

1146
	WARN_ON(!mutex_is_locked(&ctx->i915->dev->struct_mutex));
1147

1148
	if (WARN_ON_ONCE(!ctx_obj))
1149 1150
		return;

1151 1152 1153
	if (--ctx->engine[engine->id].pin_count == 0) {
		kunmap(kmap_to_page(ctx->engine[engine->id].lrc_reg_state));
		intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf);
1154
		i915_gem_object_ggtt_unpin(ctx_obj);
1155 1156 1157
		ctx->engine[engine->id].lrc_vma = NULL;
		ctx->engine[engine->id].lrc_desc = 0;
		ctx->engine[engine->id].lrc_reg_state = NULL;
1158 1159

		i915_gem_context_unreference(ctx);
1160 1161 1162
	}
}

1163
static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1164 1165
{
	int ret, i;
1166 1167
	struct intel_engine_cs *ring = req->ring;
	struct intel_ringbuffer *ringbuf = req->ringbuf;
1168 1169 1170 1171
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_workarounds *w = &dev_priv->workarounds;

1172
	if (w->count == 0)
1173 1174 1175
		return 0;

	ring->gpu_caches_dirty = true;
1176
	ret = logical_ring_flush_all_caches(req);
1177 1178 1179
	if (ret)
		return ret;

1180
	ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1181 1182 1183 1184 1185
	if (ret)
		return ret;

	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
	for (i = 0; i < w->count; i++) {
1186
		intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr);
1187 1188 1189 1190 1191 1192 1193
		intel_logical_ring_emit(ringbuf, w->reg[i].value);
	}
	intel_logical_ring_emit(ringbuf, MI_NOOP);

	intel_logical_ring_advance(ringbuf);

	ring->gpu_caches_dirty = true;
1194
	ret = logical_ring_flush_all_caches(req);
1195 1196 1197 1198 1199 1200
	if (ret)
		return ret;

	return 0;
}

1201
#define wa_ctx_emit(batch, index, cmd)					\
1202
	do {								\
1203 1204
		int __index = (index)++;				\
		if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1205 1206
			return -ENOSPC;					\
		}							\
1207
		batch[__index] = (cmd);					\
1208 1209
	} while (0)

V
Ville Syrjälä 已提交
1210
#define wa_ctx_emit_reg(batch, index, reg) \
1211
	wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234

/*
 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
 * but there is a slight complication as this is applied in WA batch where the
 * values are only initialized once so we cannot take register value at the
 * beginning and reuse it further; hence we save its value to memory, upload a
 * constant value with bit21 set and then we restore it back with the saved value.
 * To simplify the WA, a constant value is formed by using the default value
 * of this register. This shouldn't be a problem because we are only modifying
 * it for a short period and this batch in non-premptible. We can ofcourse
 * use additional instructions that read the actual value of the register
 * at that time and set our bit of interest but it makes the WA complicated.
 *
 * This WA is also required for Gen9 so extracting as a function avoids
 * code duplication.
 */
static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
						uint32_t *const batch,
						uint32_t index)
{
	uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);

1235 1236 1237 1238 1239 1240
	/*
	 * WaDisableLSQCROPERFforOCL:skl
	 * This WA is implemented in skl_init_clock_gating() but since
	 * this batch updates GEN8_L3SQCREG4 with default value we need to
	 * set this bit here to retain the WA during flush.
	 */
1241
	if (IS_SKL_REVID(ring->dev, 0, SKL_REVID_E0))
1242 1243
		l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;

1244
	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1245
				   MI_SRM_LRM_GLOBAL_GTT));
V
Ville Syrjälä 已提交
1246
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1247 1248 1249 1250
	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
	wa_ctx_emit(batch, index, 0);

	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
V
Ville Syrjälä 已提交
1251
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1252 1253 1254 1255 1256 1257 1258 1259 1260 1261
	wa_ctx_emit(batch, index, l3sqc4_flush);

	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_DC_FLUSH_ENABLE));
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);

1262
	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1263
				   MI_SRM_LRM_GLOBAL_GTT));
V
Ville Syrjälä 已提交
1264
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1265 1266
	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
	wa_ctx_emit(batch, index, 0);
1267 1268 1269 1270

	return index;
}

1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308
static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t offset,
				    uint32_t start_alignment)
{
	return wa_ctx->offset = ALIGN(offset, start_alignment);
}

static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
			     uint32_t offset,
			     uint32_t size_alignment)
{
	wa_ctx->size = offset - wa_ctx->offset;

	WARN(wa_ctx->size % size_alignment,
	     "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
	     wa_ctx->size, size_alignment);
	return 0;
}

/**
 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
 *
 * @ring: only applicable for RCS
 * @wa_ctx: structure representing wa_ctx
 *  offset: specifies start of the batch, should be cache-aligned. This is updated
 *    with the offset value received as input.
 *  size: size of the batch in DWORDS but HW expects in terms of cachelines
 * @batch: page in which WA are loaded
 * @offset: This field specifies the start of the batch, it should be
 *  cache-aligned otherwise it is adjusted accordingly.
 *  Typically we only have one indirect_ctx and per_ctx batch buffer which are
 *  initialized at the beginning and shared across all contexts but this field
 *  helps us to have multiple batches at different offsets and select them based
 *  on a criteria. At the moment this batch always start at the beginning of the page
 *  and at this point we don't have multiple wa_ctx batch buffers.
 *
 *  The number of WA applied are not known at the beginning; we use this field
 *  to return the no of DWORDS written.
1309
 *
1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322
 *  It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
 *  so it adds NOOPs as padding to make it cacheline aligned.
 *  MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
 *  makes a complete batch buffer.
 *
 * Return: non-zero if we exceed the PAGE_SIZE limit.
 */

static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
				    struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t *const batch,
				    uint32_t *offset)
{
1323
	uint32_t scratch_addr;
1324 1325
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1326
	/* WaDisableCtxRestoreArbitration:bdw,chv */
1327
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1328

1329 1330
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
	if (IS_BROADWELL(ring->dev)) {
1331 1332 1333 1334
		int rc = gen8_emit_flush_coherentl3_wa(ring, batch, index);
		if (rc < 0)
			return rc;
		index = rc;
1335 1336
	}

1337 1338 1339 1340
	/* WaClearSlmSpaceAtContextSwitch:bdw,chv */
	/* Actual scratch location is at 128 bytes offset */
	scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES;

1341 1342 1343 1344 1345 1346 1347 1348 1349
	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
				   PIPE_CONTROL_GLOBAL_GTT_IVB |
				   PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_QW_WRITE));
	wa_ctx_emit(batch, index, scratch_addr);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
1350

1351 1352
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
1353
		wa_ctx_emit(batch, index, MI_NOOP);
1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370

	/*
	 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
	 * execution depends on the length specified in terms of cache lines
	 * in the register CTX_RCS_INDIRECT_CTX
	 */

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

/**
 * gen8_init_perctx_bb() - initialize per ctx batch with WA
 *
 * @ring: only applicable for RCS
 * @wa_ctx: structure representing wa_ctx
 *  offset: specifies start of the batch, should be cache-aligned.
 *  size: size of the batch in DWORDS but HW expects in terms of cachelines
1371
 * @batch: page in which WA are loaded
1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387
 * @offset: This field specifies the start of this batch.
 *   This batch is started immediately after indirect_ctx batch. Since we ensure
 *   that indirect_ctx ends on a cacheline this batch is aligned automatically.
 *
 *   The number of DWORDS written are returned using this field.
 *
 *  This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
 *  to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
 */
static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
			       struct i915_wa_ctx_bb *wa_ctx,
			       uint32_t *const batch,
			       uint32_t *offset)
{
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1388
	/* WaDisableCtxRestoreArbitration:bdw,chv */
1389
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1390

1391
	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1392 1393 1394 1395

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1396 1397 1398 1399 1400
static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
				    struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t *const batch,
				    uint32_t *offset)
{
1401
	int ret;
1402
	struct drm_device *dev = ring->dev;
1403 1404
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1405
	/* WaDisableCtxRestoreArbitration:skl,bxt */
1406
	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
T
Tim Gore 已提交
1407
	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1408
		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1409

1410 1411 1412 1413 1414 1415
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
	ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);
	if (ret < 0)
		return ret;
	index = ret;

1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
		wa_ctx_emit(batch, index, MI_NOOP);

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
			       struct i915_wa_ctx_bb *wa_ctx,
			       uint32_t *const batch,
			       uint32_t *offset)
{
1428
	struct drm_device *dev = ring->dev;
1429 1430
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1431
	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1432
	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
T
Tim Gore 已提交
1433
	    IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1434
		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
V
Ville Syrjälä 已提交
1435
		wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1436 1437 1438 1439 1440
		wa_ctx_emit(batch, index,
			    _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
		wa_ctx_emit(batch, index, MI_NOOP);
	}

1441
	/* WaDisableCtxRestoreArbitration:skl,bxt */
1442
	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
T
Tim Gore 已提交
1443
	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1444 1445
		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);

1446 1447 1448 1449 1450
	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490
static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
{
	int ret;

	ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size));
	if (!ring->wa_ctx.obj) {
		DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
		return -ENOMEM;
	}

	ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0);
	if (ret) {
		DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
				 ret);
		drm_gem_object_unreference(&ring->wa_ctx.obj->base);
		return ret;
	}

	return 0;
}

static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring)
{
	if (ring->wa_ctx.obj) {
		i915_gem_object_ggtt_unpin(ring->wa_ctx.obj);
		drm_gem_object_unreference(&ring->wa_ctx.obj->base);
		ring->wa_ctx.obj = NULL;
	}
}

static int intel_init_workaround_bb(struct intel_engine_cs *ring)
{
	int ret;
	uint32_t *batch;
	uint32_t offset;
	struct page *page;
	struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;

	WARN_ON(ring->id != RCS);

1491
	/* update this when WA for higher Gen are added */
1492 1493 1494
	if (INTEL_INFO(ring->dev)->gen > 9) {
		DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
			  INTEL_INFO(ring->dev)->gen);
1495
		return 0;
1496
	}
1497

1498 1499 1500 1501 1502 1503
	/* some WA perform writes to scratch page, ensure it is valid */
	if (ring->scratch.obj == NULL) {
		DRM_ERROR("scratch page not allocated for %s\n", ring->name);
		return -EINVAL;
	}

1504 1505 1506 1507 1508 1509
	ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
		return ret;
	}

1510
	page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0);
1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527
	batch = kmap_atomic(page);
	offset = 0;

	if (INTEL_INFO(ring->dev)->gen == 8) {
		ret = gen8_init_indirectctx_bb(ring,
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

		ret = gen8_init_perctx_bb(ring,
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541
	} else if (INTEL_INFO(ring->dev)->gen == 9) {
		ret = gen9_init_indirectctx_bb(ring,
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

		ret = gen9_init_perctx_bb(ring,
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1542 1543 1544 1545 1546 1547 1548 1549 1550 1551
	}

out:
	kunmap_atomic(batch);
	if (ret)
		lrc_destroy_wa_ctx_obj(ring);

	return ret;
}

1552 1553 1554 1555
static int gen8_init_common_ring(struct intel_engine_cs *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1556
	u8 next_context_status_buffer_hw;
1557

1558
	lrc_setup_hardware_status_page(ring,
1559
				dev_priv->kernel_context->engine[ring->id].state);
1560

1561 1562 1563
	I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
	I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);

1564 1565 1566 1567
	I915_WRITE(RING_MODE_GEN7(ring),
		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
	POSTING_READ(RING_MODE_GEN7(ring));
1568 1569 1570 1571 1572 1573 1574 1575 1576 1577

	/*
	 * Instead of resetting the Context Status Buffer (CSB) read pointer to
	 * zero, we need to read the write pointer from hardware and use its
	 * value because "this register is power context save restored".
	 * Effectively, these states have been observed:
	 *
	 *      | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
	 * BDW  | CSB regs not reset       | CSB regs reset       |
	 * CHT  | CSB regs not reset       | CSB regs not reset   |
1578 1579
	 * SKL  |         ?                |         ?            |
	 * BXT  |         ?                |         ?            |
1580
	 */
1581 1582
	next_context_status_buffer_hw =
		GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(ring)));
1583 1584 1585 1586 1587 1588 1589 1590 1591 1592

	/*
	 * When the CSB registers are reset (also after power-up / gpu reset),
	 * CSB write pointer is set to all 1's, which is not valid, use '5' in
	 * this special case, so the first element read is CSB[0].
	 */
	if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
		next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);

	ring->next_context_status_buffer = next_context_status_buffer_hw;
1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619
	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);

	memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));

	return 0;
}

static int gen8_init_render_ring(struct intel_engine_cs *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = gen8_init_common_ring(ring);
	if (ret)
		return ret;

	/* We need to disable the AsyncFlip performance optimisations in order
	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
	 * programmed to '1' on all products.
	 *
	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
	 */
	I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));

	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));

1620
	return init_workarounds_ring(ring);
1621 1622
}

1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633
static int gen9_init_render_ring(struct intel_engine_cs *ring)
{
	int ret;

	ret = gen8_init_common_ring(ring);
	if (ret)
		return ret;

	return init_workarounds_ring(ring);
}

1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
	struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
	struct intel_engine_cs *ring = req->ring;
	struct intel_ringbuffer *ringbuf = req->ringbuf;
	const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
	int i, ret;

	ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
	if (ret)
		return ret;

	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);

1650
		intel_logical_ring_emit_reg(ringbuf, GEN8_RING_PDP_UDW(ring, i));
1651
		intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1652
		intel_logical_ring_emit_reg(ringbuf, GEN8_RING_PDP_LDW(ring, i));
1653 1654 1655 1656 1657 1658 1659 1660 1661
		intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
	}

	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1662
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1663
			      u64 offset, unsigned dispatch_flags)
1664
{
1665
	struct intel_ringbuffer *ringbuf = req->ringbuf;
1666
	bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1667 1668
	int ret;

1669 1670 1671 1672
	/* Don't rely in hw updating PDPs, specially in lite-restore.
	 * Ideally, we should set Force PD Restore in ctx descriptor,
	 * but we can't. Force Restore would be a second option, but
	 * it is unsafe in case of lite-restore (because the ctx is
1673 1674
	 * not idle). PML4 is allocated during ppgtt init so this is
	 * not needed in 48-bit.*/
1675 1676
	if (req->ctx->ppgtt &&
	    (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
1677 1678
		if (!USES_FULL_48BIT_PPGTT(req->i915) &&
		    !intel_vgpu_active(req->i915->dev)) {
1679 1680 1681 1682
			ret = intel_logical_ring_emit_pdps(req);
			if (ret)
				return ret;
		}
1683 1684 1685 1686

		req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
	}

1687
	ret = intel_logical_ring_begin(req, 4);
1688 1689 1690 1691
	if (ret)
		return ret;

	/* FIXME(BDW): Address space and security selectors. */
1692 1693 1694 1695
	intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
				(ppgtt<<8) |
				(dispatch_flags & I915_DISPATCH_RS ?
				 MI_BATCH_RESOURCE_STREAMER : 0));
1696 1697 1698 1699 1700 1701 1702 1703
	intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
	intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1704 1705 1706 1707 1708 1709
static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long flags;

1710
	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736
		return false;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	if (ring->irq_refcount++ == 0) {
		I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
		POSTING_READ(RING_IMR(ring->mmio_base));
	}
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	return true;
}

static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	if (--ring->irq_refcount == 0) {
		I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
		POSTING_READ(RING_IMR(ring->mmio_base));
	}
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
}

1737
static int gen8_emit_flush(struct drm_i915_gem_request *request,
1738 1739 1740
			   u32 invalidate_domains,
			   u32 unused)
{
1741
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1742 1743 1744 1745 1746 1747
	struct intel_engine_cs *ring = ringbuf->ring;
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t cmd;
	int ret;

1748
	ret = intel_logical_ring_begin(request, 4);
1749 1750 1751 1752 1753
	if (ret)
		return ret;

	cmd = MI_FLUSH_DW + 1;

1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764
	/* We always require a command barrier so that subsequent
	 * commands, such as breadcrumb interrupts, are strictly ordered
	 * wrt the contents of the write cache being flushed to memory
	 * (and thus being coherent from the CPU).
	 */
	cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;

	if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
		cmd |= MI_INVALIDATE_TLB;
		if (ring == &dev_priv->ring[VCS])
			cmd |= MI_INVALIDATE_BSD;
1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777
	}

	intel_logical_ring_emit(ringbuf, cmd);
	intel_logical_ring_emit(ringbuf,
				I915_GEM_HWS_SCRATCH_ADDR |
				MI_FLUSH_DW_USE_GTT);
	intel_logical_ring_emit(ringbuf, 0); /* upper addr */
	intel_logical_ring_emit(ringbuf, 0); /* value */
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1778
static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1779 1780 1781
				  u32 invalidate_domains,
				  u32 flush_domains)
{
1782
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1783 1784
	struct intel_engine_cs *ring = ringbuf->ring;
	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1785
	bool vf_flush_wa = false;
1786 1787 1788 1789 1790 1791 1792 1793
	u32 flags = 0;
	int ret;

	flags |= PIPE_CONTROL_CS_STALL;

	if (flush_domains) {
		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1794
		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1795
		flags |= PIPE_CONTROL_FLUSH_ENABLE;
1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807
	}

	if (invalidate_domains) {
		flags |= PIPE_CONTROL_TLB_INVALIDATE;
		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_QW_WRITE;
		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;

1808 1809 1810 1811 1812 1813 1814
		/*
		 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
		 * pipe control.
		 */
		if (IS_GEN9(ring->dev))
			vf_flush_wa = true;
	}
1815

1816
	ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1817 1818 1819
	if (ret)
		return ret;

1820 1821 1822 1823 1824 1825 1826 1827 1828
	if (vf_flush_wa) {
		intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
	}

1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839
	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
	intel_logical_ring_emit(ringbuf, flags);
	intel_logical_ring_emit(ringbuf, scratch_addr);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1840 1841 1842 1843 1844 1845 1846 1847 1848 1849
static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
{
	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
}

static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
{
	intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
}

1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877
static u32 bxt_a_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
{

	/*
	 * On BXT A steppings there is a HW coherency issue whereby the
	 * MI_STORE_DATA_IMM storing the completed request's seqno
	 * occasionally doesn't invalidate the CPU cache. Work around this by
	 * clflushing the corresponding cacheline whenever the caller wants
	 * the coherency to be guaranteed. Note that this cacheline is known
	 * to be clean at this point, since we only write it in
	 * bxt_a_set_seqno(), where we also do a clflush after the write. So
	 * this clflush in practice becomes an invalidate operation.
	 */

	if (!lazy_coherency)
		intel_flush_status_page(ring, I915_GEM_HWS_INDEX);

	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
}

static void bxt_a_set_seqno(struct intel_engine_cs *ring, u32 seqno)
{
	intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);

	/* See bxt_a_get_seqno() explaining the reason for the clflush. */
	intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
}

1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889
/*
 * Reserve space for 2 NOOPs at the end of each request to be
 * used as a workaround for not being allowed to do lite
 * restore with HEAD==TAIL (WaIdleLiteRestore).
 */
#define WA_TAIL_DWORDS 2

static inline u32 hws_seqno_address(struct intel_engine_cs *engine)
{
	return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR;
}

1890
static int gen8_emit_request(struct drm_i915_gem_request *request)
1891
{
1892
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1893 1894
	int ret;

1895
	ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
1896 1897 1898
	if (ret)
		return ret;

1899 1900
	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
	BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1901 1902

	intel_logical_ring_emit(ringbuf,
1903 1904 1905 1906
				(MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
	intel_logical_ring_emit(ringbuf,
				hws_seqno_address(request->ring) |
				MI_FLUSH_DW_USE_GTT);
1907
	intel_logical_ring_emit(ringbuf, 0);
1908
	intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1909 1910
	intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
	intel_logical_ring_emit(ringbuf, MI_NOOP);
1911 1912
	return intel_logical_ring_advance_and_submit(request);
}
1913

1914 1915 1916 1917
static int gen8_emit_request_render(struct drm_i915_gem_request *request)
{
	struct intel_ringbuffer *ringbuf = request->ringbuf;
	int ret;
1918

1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936
	ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
	if (ret)
		return ret;

	/* w/a for post sync ops following a GPGPU operation we
	 * need a prior CS_STALL, which is emitted by the flush
	 * following the batch.
	 */
	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
	intel_logical_ring_emit(ringbuf,
				(PIPE_CONTROL_GLOBAL_GTT_IVB |
				 PIPE_CONTROL_CS_STALL |
				 PIPE_CONTROL_QW_WRITE));
	intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring));
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
	intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
	return intel_logical_ring_advance_and_submit(request);
1937 1938
}

1939
static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1940 1941 1942 1943
{
	struct render_state so;
	int ret;

1944
	ret = i915_gem_render_state_prepare(req->ring, &so);
1945 1946 1947 1948 1949 1950
	if (ret)
		return ret;

	if (so.rodata == NULL)
		return 0;

1951
	ret = req->ring->emit_bb_start(req, so.ggtt_offset,
1952
				       I915_DISPATCH_SECURE);
1953 1954 1955
	if (ret)
		goto out;

1956 1957 1958 1959 1960 1961
	ret = req->ring->emit_bb_start(req,
				       (so.ggtt_offset + so.aux_batch_offset),
				       I915_DISPATCH_SECURE);
	if (ret)
		goto out;

1962
	i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1963 1964 1965 1966 1967 1968

out:
	i915_gem_render_state_fini(&so);
	return ret;
}

1969
static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1970 1971 1972
{
	int ret;

1973
	ret = intel_logical_ring_workarounds_emit(req);
1974 1975 1976
	if (ret)
		return ret;

1977 1978 1979 1980 1981 1982 1983 1984
	ret = intel_rcs_context_init_mocs(req);
	/*
	 * Failing to program the MOCS is non-fatal.The system will not
	 * run at peak performance. So generate an error and carry on.
	 */
	if (ret)
		DRM_ERROR("MOCS failed to program: expect performance issues.\n");

1985
	return intel_lr_context_render_state_init(req);
1986 1987
}

1988 1989 1990 1991 1992 1993
/**
 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
 *
 * @ring: Engine Command Streamer.
 *
 */
1994 1995
void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
{
1996
	struct drm_i915_private *dev_priv;
1997

1998 1999 2000
	if (!intel_ring_initialized(ring))
		return;

2001 2002
	dev_priv = ring->dev->dev_private;

2003 2004 2005 2006
	if (ring->buffer) {
		intel_logical_ring_stop(ring);
		WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
	}
2007 2008 2009 2010 2011

	if (ring->cleanup)
		ring->cleanup(ring);

	i915_cmd_parser_fini_ring(ring);
2012
	i915_gem_batch_pool_fini(&ring->batch_pool);
2013 2014 2015 2016 2017

	if (ring->status_page.obj) {
		kunmap(sg_page(ring->status_page.obj->pages->sgl));
		ring->status_page.obj = NULL;
	}
2018

2019 2020 2021
	ring->disable_lite_restore_wa = false;
	ring->ctx_desc_template = 0;

2022
	lrc_destroy_wa_ctx_obj(ring);
2023
	ring->dev = NULL;
2024 2025
}

2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045
static void
logical_ring_default_vfuncs(struct drm_device *dev,
			    struct intel_engine_cs *ring)
{
	/* Default vfuncs which can be overriden by each engine. */
	ring->init_hw = gen8_init_common_ring;
	ring->emit_request = gen8_emit_request;
	ring->emit_flush = gen8_emit_flush;
	ring->irq_get = gen8_logical_ring_get_irq;
	ring->irq_put = gen8_logical_ring_put_irq;
	ring->emit_bb_start = gen8_emit_bb_start;
	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
		ring->get_seqno = bxt_a_get_seqno;
		ring->set_seqno = bxt_a_set_seqno;
	} else {
		ring->get_seqno = gen8_get_seqno;
		ring->set_seqno = gen8_set_seqno;
	}
}

2046 2047 2048 2049 2050 2051 2052
static inline void
logical_ring_default_irqs(struct intel_engine_cs *ring, unsigned shift)
{
	ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
	ring->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
}

2053 2054
static int
logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
2055
{
2056
	struct intel_context *dctx = to_i915(dev)->kernel_context;
2057 2058 2059 2060 2061 2062 2063 2064
	int ret;

	/* Intentionally left blank. */
	ring->buffer = NULL;

	ring->dev = dev;
	INIT_LIST_HEAD(&ring->active_list);
	INIT_LIST_HEAD(&ring->request_list);
2065
	i915_gem_batch_pool_init(dev, &ring->batch_pool);
2066 2067
	init_waitqueue_head(&ring->irq_queue);

2068
	INIT_LIST_HEAD(&ring->buffers);
2069
	INIT_LIST_HEAD(&ring->execlist_queue);
2070
	INIT_LIST_HEAD(&ring->execlist_retired_req_list);
2071 2072
	spin_lock_init(&ring->execlist_lock);

2073 2074
	logical_ring_init_platform_invariants(ring);

2075 2076
	ret = i915_cmd_parser_init_ring(ring);
	if (ret)
2077
		goto error;
2078

2079
	ret = intel_lr_context_deferred_alloc(dctx, ring);
2080
	if (ret)
2081
		goto error;
2082 2083

	/* As this is the default context, always pin it */
2084
	ret = intel_lr_context_do_pin(dctx, ring);
2085 2086 2087 2088
	if (ret) {
		DRM_ERROR(
			"Failed to pin and map ringbuffer %s: %d\n",
			ring->name, ret);
2089
		goto error;
2090
	}
2091

2092 2093 2094 2095
	return 0;

error:
	intel_logical_ring_cleanup(ring);
2096
	return ret;
2097 2098 2099 2100 2101 2102
}

static int logical_render_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2103
	int ret;
2104 2105 2106

	ring->name = "render ring";
	ring->id = RCS;
2107
	ring->exec_id = I915_EXEC_RENDER;
2108
	ring->guc_id = GUC_RENDER_ENGINE;
2109
	ring->mmio_base = RENDER_RING_BASE;
2110 2111

	logical_ring_default_irqs(ring, GEN8_RCS_IRQ_SHIFT);
2112 2113
	if (HAS_L3_DPF(dev))
		ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2114

2115 2116 2117
	logical_ring_default_vfuncs(dev, ring);

	/* Override some for render ring. */
2118 2119 2120 2121
	if (INTEL_INFO(dev)->gen >= 9)
		ring->init_hw = gen9_init_render_ring;
	else
		ring->init_hw = gen8_init_render_ring;
2122
	ring->init_context = gen8_init_rcs_context;
2123
	ring->cleanup = intel_fini_pipe_control;
2124
	ring->emit_flush = gen8_emit_flush_render;
2125
	ring->emit_request = gen8_emit_request_render;
2126

2127
	ring->dev = dev;
2128 2129

	ret = intel_init_pipe_control(ring);
2130 2131 2132
	if (ret)
		return ret;

2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143
	ret = intel_init_workaround_bb(ring);
	if (ret) {
		/*
		 * We continue even if we fail to initialize WA batch
		 * because we only expect rare glitches but nothing
		 * critical to prevent us from using GPU
		 */
		DRM_ERROR("WA batch buffer initialization failed: %d\n",
			  ret);
	}

2144 2145
	ret = logical_ring_init(dev, ring);
	if (ret) {
2146
		lrc_destroy_wa_ctx_obj(ring);
2147
	}
2148 2149

	return ret;
2150 2151 2152 2153 2154 2155 2156 2157 2158
}

static int logical_bsd_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring = &dev_priv->ring[VCS];

	ring->name = "bsd ring";
	ring->id = VCS;
2159
	ring->exec_id = I915_EXEC_BSD;
2160
	ring->guc_id = GUC_VIDEO_ENGINE;
2161 2162
	ring->mmio_base = GEN6_BSD_RING_BASE;

2163
	logical_ring_default_irqs(ring, GEN8_VCS1_IRQ_SHIFT);
2164
	logical_ring_default_vfuncs(dev, ring);
2165

2166 2167 2168 2169 2170 2171 2172 2173
	return logical_ring_init(dev, ring);
}

static int logical_bsd2_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring = &dev_priv->ring[VCS2];

T
Tvrtko Ursulin 已提交
2174
	ring->name = "bsd2 ring";
2175
	ring->id = VCS2;
2176
	ring->exec_id = I915_EXEC_BSD;
2177
	ring->guc_id = GUC_VIDEO_ENGINE2;
2178 2179
	ring->mmio_base = GEN8_BSD2_RING_BASE;

2180
	logical_ring_default_irqs(ring, GEN8_VCS2_IRQ_SHIFT);
2181
	logical_ring_default_vfuncs(dev, ring);
2182

2183 2184 2185 2186 2187 2188 2189 2190 2191 2192
	return logical_ring_init(dev, ring);
}

static int logical_blt_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring = &dev_priv->ring[BCS];

	ring->name = "blitter ring";
	ring->id = BCS;
2193
	ring->exec_id = I915_EXEC_BLT;
2194
	ring->guc_id = GUC_BLITTER_ENGINE;
2195 2196
	ring->mmio_base = BLT_RING_BASE;

2197
	logical_ring_default_irqs(ring, GEN8_BCS_IRQ_SHIFT);
2198
	logical_ring_default_vfuncs(dev, ring);
2199

2200 2201 2202 2203 2204 2205 2206 2207 2208 2209
	return logical_ring_init(dev, ring);
}

static int logical_vebox_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring = &dev_priv->ring[VECS];

	ring->name = "video enhancement ring";
	ring->id = VECS;
2210
	ring->exec_id = I915_EXEC_VEBOX;
2211
	ring->guc_id = GUC_VIDEOENHANCE_ENGINE;
2212 2213
	ring->mmio_base = VEBOX_RING_BASE;

2214
	logical_ring_default_irqs(ring, GEN8_VECS_IRQ_SHIFT);
2215
	logical_ring_default_vfuncs(dev, ring);
2216

2217 2218 2219
	return logical_ring_init(dev, ring);
}

2220 2221 2222 2223 2224 2225 2226 2227 2228 2229
/**
 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
 * @dev: DRM device.
 *
 * This function inits the engines for an Execlists submission style (the equivalent in the
 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
 * those engines that are present in the hardware.
 *
 * Return: non-zero if the initialization failed.
 */
2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276
int intel_logical_rings_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = logical_render_ring_init(dev);
	if (ret)
		return ret;

	if (HAS_BSD(dev)) {
		ret = logical_bsd_ring_init(dev);
		if (ret)
			goto cleanup_render_ring;
	}

	if (HAS_BLT(dev)) {
		ret = logical_blt_ring_init(dev);
		if (ret)
			goto cleanup_bsd_ring;
	}

	if (HAS_VEBOX(dev)) {
		ret = logical_vebox_ring_init(dev);
		if (ret)
			goto cleanup_blt_ring;
	}

	if (HAS_BSD2(dev)) {
		ret = logical_bsd2_ring_init(dev);
		if (ret)
			goto cleanup_vebox_ring;
	}

	return 0;

cleanup_vebox_ring:
	intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
cleanup_blt_ring:
	intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
cleanup_bsd_ring:
	intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
cleanup_render_ring:
	intel_logical_ring_cleanup(&dev_priv->ring[RCS]);

	return ret;
}

2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319
static u32
make_rpcs(struct drm_device *dev)
{
	u32 rpcs = 0;

	/*
	 * No explicit RPCS request is needed to ensure full
	 * slice/subslice/EU enablement prior to Gen9.
	*/
	if (INTEL_INFO(dev)->gen < 9)
		return 0;

	/*
	 * Starting in Gen9, render power gating can leave
	 * slice/subslice/EU in a partially enabled state. We
	 * must make an explicit request through RPCS for full
	 * enablement.
	*/
	if (INTEL_INFO(dev)->has_slice_pg) {
		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
		rpcs |= INTEL_INFO(dev)->slice_total <<
			GEN8_RPCS_S_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	if (INTEL_INFO(dev)->has_subslice_pg) {
		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
		rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
			GEN8_RPCS_SS_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	if (INTEL_INFO(dev)->has_eu_pg) {
		rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
			GEN8_RPCS_EU_MIN_SHIFT;
		rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
			GEN8_RPCS_EU_MAX_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	return rpcs;
}

2320 2321 2322 2323
static int
populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
		    struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
{
2324 2325
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2326
	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2327 2328 2329 2330
	struct page *page;
	uint32_t *reg_state;
	int ret;

2331 2332 2333
	if (!ppgtt)
		ppgtt = dev_priv->mm.aliasing_ppgtt;

2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349
	ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
	if (ret) {
		DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
		return ret;
	}

	ret = i915_gem_object_get_pages(ctx_obj);
	if (ret) {
		DRM_DEBUG_DRIVER("Could not get object pages\n");
		return ret;
	}

	i915_gem_object_pin_pages(ctx_obj);

	/* The second page of the context object contains some fields which must
	 * be set up prior to the first execution. */
2350
	page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2351 2352 2353 2354 2355 2356 2357
	reg_state = kmap_atomic(page);

	/* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
	 * commands followed by (reg, value) pairs. The values we are setting here are
	 * only for the first context restore: on a subsequent save, the GPU will
	 * recreate this batchbuffer with new values (including all the missing
	 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2358 2359 2360 2361 2362 2363 2364 2365
	reg_state[CTX_LRI_HEADER_0] =
		MI_LOAD_REGISTER_IMM(ring->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
	ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(ring),
		       _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
					  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
					  CTX_CTRL_RS_CTX_ENABLE));
	ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(ring->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(ring->mmio_base), 0);
2366 2367 2368
	/* Ring buffer start address is not known until the buffer is pinned.
	 * It is written to the context image in execlists_update_context()
	 */
2369 2370 2371 2372 2373 2374 2375 2376 2377 2378
	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, RING_START(ring->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, RING_CTL(ring->mmio_base),
		       ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, RING_BBADDR_UDW(ring->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, RING_BBADDR(ring->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, RING_BBSTATE(ring->mmio_base),
		       RING_BB_PPGTT);
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(ring->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(ring->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, RING_SBBSTATE(ring->mmio_base), 0);
2379
	if (ring->id == RCS) {
2380 2381 2382
		ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(ring->mmio_base), 0);
		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(ring->mmio_base), 0);
		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, RING_INDIRECT_CTX_OFFSET(ring->mmio_base), 0);
2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397
		if (ring->wa_ctx.obj) {
			struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
			uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);

			reg_state[CTX_RCS_INDIRECT_CTX+1] =
				(ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
				(wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);

			reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
				CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;

			reg_state[CTX_BB_PER_CTX_PTR+1] =
				(ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
				0x01;
		}
2398
	}
2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409
	reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
	ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(ring->mmio_base), 0);
	/* PDP values well be assigned later if needed */
	ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(ring, 3), 0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(ring, 3), 0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(ring, 2), 0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(ring, 2), 0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(ring, 1), 0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(ring, 1), 0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(ring, 0), 0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(ring, 0), 0);
2410

2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428
	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
		/* 64b PPGTT (48bit canonical)
		 * PDP0_DESCRIPTOR contains the base address to PML4 and
		 * other PDP Descriptors are ignored.
		 */
		ASSIGN_CTX_PML4(ppgtt, reg_state);
	} else {
		/* 32b PPGTT
		 * PDP*_DESCRIPTOR contains the base address of space supported.
		 * With dynamic page allocation, PDPs may not be allocated at
		 * this point. Point the unallocated PDPs to the scratch page
		 */
		ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
	}

2429 2430
	if (ring->id == RCS) {
		reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2431 2432
		ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
			       make_rpcs(dev));
2433 2434 2435 2436 2437 2438 2439 2440
	}

	kunmap_atomic(reg_state);
	i915_gem_object_unpin_pages(ctx_obj);

	return 0;
}

2441 2442 2443 2444 2445 2446 2447 2448
/**
 * intel_lr_context_free() - free the LRC specific bits of a context
 * @ctx: the LR context to free.
 *
 * The real context freeing is done in i915_gem_context_free: this only
 * takes care of the bits that are LRC related: the per-engine backing
 * objects and the logical ringbuffer.
 */
2449 2450
void intel_lr_context_free(struct intel_context *ctx)
{
2451 2452
	int i;

D
Dave Gordon 已提交
2453 2454
	for (i = I915_NUM_RINGS; --i >= 0; ) {
		struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
2455
		struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2456

D
Dave Gordon 已提交
2457 2458
		if (!ctx_obj)
			continue;
2459

D
Dave Gordon 已提交
2460 2461 2462
		if (ctx == ctx->i915->kernel_context) {
			intel_unpin_ringbuffer_obj(ringbuf);
			i915_gem_object_ggtt_unpin(ctx_obj);
2463
		}
D
Dave Gordon 已提交
2464 2465 2466 2467

		WARN_ON(ctx->engine[i].pin_count);
		intel_ringbuffer_free(ringbuf);
		drm_gem_object_unreference(&ctx_obj->base);
2468 2469 2470
	}
}

2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484
/**
 * intel_lr_context_size() - return the size of the context for an engine
 * @ring: which engine to find the context size for
 *
 * Each engine may require a different amount of space for a context image,
 * so when allocating (or copying) an image, this function can be used to
 * find the right size for the specific engine.
 *
 * Return: size (in bytes) of an engine-specific context image
 *
 * Note: this size includes the HWSP, which is part of the context image
 * in LRC mode, but does not include the "shared data page" used with
 * GuC submission. The caller should account for this if using the GuC.
 */
2485
uint32_t intel_lr_context_size(struct intel_engine_cs *ring)
2486 2487 2488
{
	int ret = 0;

2489
	WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
2490 2491 2492

	switch (ring->id) {
	case RCS:
2493 2494 2495 2496
		if (INTEL_INFO(ring->dev)->gen >= 9)
			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
		else
			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2497 2498 2499 2500 2501 2502 2503 2504 2505 2506
		break;
	case VCS:
	case BCS:
	case VECS:
	case VCS2:
		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
		break;
	}

	return ret;
2507 2508
}

2509
static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
2510 2511 2512
		struct drm_i915_gem_object *default_ctx_obj)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2513
	struct page *page;
2514

2515 2516 2517 2518 2519
	/* The HWSP is part of the default context object in LRC mode. */
	ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj)
			+ LRC_PPHWSP_PN * PAGE_SIZE;
	page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN);
	ring->status_page.page_addr = kmap(page);
2520 2521 2522 2523 2524 2525 2526
	ring->status_page.obj = default_ctx_obj;

	I915_WRITE(RING_HWS_PGA(ring->mmio_base),
			(u32)ring->status_page.gfx_addr);
	POSTING_READ(RING_HWS_PGA(ring->mmio_base));
}

2527
/**
2528
 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2529 2530 2531 2532 2533 2534 2535 2536 2537
 * @ctx: LR context to create.
 * @ring: engine to be used with the context.
 *
 * This function can be called more than once, with different engines, if we plan
 * to use the context with them. The context backing objects and the ringbuffers
 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
 * the creation is a deferred call: it's better to make sure first that we need to use
 * a given ring with the context.
 *
2538
 * Return: non-zero on error.
2539
 */
2540 2541

int intel_lr_context_deferred_alloc(struct intel_context *ctx,
D
Dave Gordon 已提交
2542
				    struct intel_engine_cs *ring)
2543
{
2544 2545 2546
	struct drm_device *dev = ring->dev;
	struct drm_i915_gem_object *ctx_obj;
	uint32_t context_size;
2547
	struct intel_ringbuffer *ringbuf;
2548 2549
	int ret;

2550
	WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2551
	WARN_ON(ctx->engine[ring->id].state);
2552

2553
	context_size = round_up(intel_lr_context_size(ring), 4096);
2554

2555 2556 2557
	/* One extra page as the sharing data between driver and GuC */
	context_size += PAGE_SIZE * LRC_PPHWSP_PN;

2558
	ctx_obj = i915_gem_alloc_object(dev, context_size);
2559 2560 2561
	if (!ctx_obj) {
		DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
		return -ENOMEM;
2562 2563
	}

2564 2565 2566
	ringbuf = intel_engine_create_ringbuffer(ring, 4 * PAGE_SIZE);
	if (IS_ERR(ringbuf)) {
		ret = PTR_ERR(ringbuf);
2567
		goto error_deref_obj;
2568 2569 2570 2571 2572
	}

	ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2573
		goto error_ringbuf;
2574 2575 2576
	}

	ctx->engine[ring->id].ringbuf = ringbuf;
2577
	ctx->engine[ring->id].state = ctx_obj;
2578

2579
	if (ctx != ctx->i915->kernel_context && ring->init_context) {
2580
		struct drm_i915_gem_request *req;
2581

2582 2583 2584 2585
		req = i915_gem_request_alloc(ring, ctx);
		if (IS_ERR(req)) {
			ret = PTR_ERR(req);
			DRM_ERROR("ring create req: %d\n", ret);
2586
			goto error_ringbuf;
2587 2588
		}

2589 2590 2591 2592 2593 2594 2595 2596
		ret = ring->init_context(req);
		if (ret) {
			DRM_ERROR("ring init context: %d\n",
				ret);
			i915_gem_request_cancel(req);
			goto error_ringbuf;
		}
		i915_add_request_no_flush(req);
2597
	}
2598
	return 0;
2599

2600 2601
error_ringbuf:
	intel_ringbuffer_free(ringbuf);
2602
error_deref_obj:
2603
	drm_gem_object_unreference(&ctx_obj->base);
2604 2605
	ctx->engine[ring->id].ringbuf = NULL;
	ctx->engine[ring->id].state = NULL;
2606
	return ret;
2607
}
2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630

void intel_lr_context_reset(struct drm_device *dev,
			struct intel_context *ctx)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring;
	int i;

	for_each_ring(ring, dev_priv, i) {
		struct drm_i915_gem_object *ctx_obj =
				ctx->engine[ring->id].state;
		struct intel_ringbuffer *ringbuf =
				ctx->engine[ring->id].ringbuf;
		uint32_t *reg_state;
		struct page *page;

		if (!ctx_obj)
			continue;

		if (i915_gem_object_get_pages(ctx_obj)) {
			WARN(1, "Failed get_pages for context obj\n");
			continue;
		}
2631
		page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642
		reg_state = kmap_atomic(page);

		reg_state[CTX_RING_HEAD+1] = 0;
		reg_state[CTX_RING_TAIL+1] = 0;

		kunmap_atomic(reg_state);

		ringbuf->head = 0;
		ringbuf->tail = 0;
	}
}