intel_lrc.c 75.3 KB
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/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky <ben@bwidawsk.net>
 *    Michel Thierry <michel.thierry@intel.com>
 *    Thomas Daniel <thomas.daniel@intel.com>
 *    Oscar Mateo <oscar.mateo@intel.com>
 *
 */

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/**
 * DOC: Logical Rings, Logical Ring Contexts and Execlists
 *
 * Motivation:
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 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
 * These expanded contexts enable a number of new abilities, especially
 * "Execlists" (also implemented in this file).
 *
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 * One of the main differences with the legacy HW contexts is that logical
 * ring contexts incorporate many more things to the context's state, like
 * PDPs or ringbuffer control registers:
 *
 * The reason why PDPs are included in the context is straightforward: as
 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
 * instead, the GPU will do it for you on the context switch.
 *
 * But, what about the ringbuffer control registers (head, tail, etc..)?
 * shouldn't we just need a set of those per engine command streamer? This is
 * where the name "Logical Rings" starts to make sense: by virtualizing the
 * rings, the engine cs shifts to a new "ring buffer" with every context
 * switch. When you want to submit a workload to the GPU you: A) choose your
 * context, B) find its appropriate virtualized ring, C) write commands to it
 * and then, finally, D) tell the GPU to switch to that context.
 *
 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
 * to a contexts is via a context execution list, ergo "Execlists".
 *
 * LRC implementation:
 * Regarding the creation of contexts, we have:
 *
 * - One global default context.
 * - One local default context for each opened fd.
 * - One local extra context for each context create ioctl call.
 *
 * Now that ringbuffers belong per-context (and not per-engine, like before)
 * and that contexts are uniquely tied to a given engine (and not reusable,
 * like before) we need:
 *
 * - One ringbuffer per-engine inside each context.
 * - One backing object per-engine inside each context.
 *
 * The global default context starts its life with these new objects fully
 * allocated and populated. The local default context for each opened fd is
 * more complex, because we don't know at creation time which engine is going
 * to use them. To handle this, we have implemented a deferred creation of LR
 * contexts:
 *
 * The local context starts its life as a hollow or blank holder, that only
 * gets populated for a given engine once we receive an execbuffer. If later
 * on we receive another execbuffer ioctl for the same context but a different
 * engine, we allocate/populate a new ringbuffer and context backing object and
 * so on.
 *
 * Finally, regarding local contexts created using the ioctl call: as they are
 * only allowed with the render ring, we can allocate & populate them right
 * away (no need to defer anything, at least for now).
 *
 * Execlists implementation:
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 * Execlists are the new method by which, on gen8+ hardware, workloads are
 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
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 * This method works as follows:
 *
 * When a request is committed, its commands (the BB start and any leading or
 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
 * for the appropriate context. The tail pointer in the hardware context is not
 * updated at this time, but instead, kept by the driver in the ringbuffer
 * structure. A structure representing this request is added to a request queue
 * for the appropriate engine: this structure contains a copy of the context's
 * tail after the request was written to the ring buffer and a pointer to the
 * context itself.
 *
 * If the engine's request queue was empty before the request was added, the
 * queue is processed immediately. Otherwise the queue will be processed during
 * a context switch interrupt. In any case, elements on the queue will get sent
 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 * globally unique 20-bits submission ID.
 *
 * When execution of a request completes, the GPU updates the context status
 * buffer with a context complete event and generates a context switch interrupt.
 * During the interrupt handling, the driver examines the events in the buffer:
 * for each context complete event, if the announced ID matches that on the head
 * of the request queue, then that request is retired and removed from the queue.
 *
 * After processing, if any requests were retired and the queue is not empty
 * then a new execution list can be submitted. The two requests at the front of
 * the queue are next to be submitted but since a context may not occur twice in
 * an execution list, if subsequent requests have the same ID as the first then
 * the two requests must be combined. This is done simply by discarding requests
 * at the head of the queue until either only one requests is left (in which case
 * we use a NULL second context) or the first two requests have unique IDs.
 *
 * By always executing the first two requests in the queue the driver ensures
 * that the GPU is kept as busy as possible. In the case where a single context
 * completes but a second context is still executing, the request for this second
 * context will be at the head of the queue when we remove the first one. This
 * request will then be resubmitted along with a new request for a different context,
 * which will cause the hardware to continue executing the second request and queue
 * the new request (the GPU detects the condition of a context getting preempted
 * with the same context and optimizes the context switch flow by not doing
 * preemption, but just sampling the new tail pointer).
 *
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 */

#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
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#include "intel_mocs.h"
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#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
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#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)

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#define RING_EXECLIST_QFULL		(1 << 0x2)
#define RING_EXECLIST1_VALID		(1 << 0x3)
#define RING_EXECLIST0_VALID		(1 << 0x4)
#define RING_EXECLIST_ACTIVE_STATUS	(3 << 0xE)
#define RING_EXECLIST1_ACTIVE		(1 << 0x11)
#define RING_EXECLIST0_ACTIVE		(1 << 0x12)

#define GEN8_CTX_STATUS_IDLE_ACTIVE	(1 << 0)
#define GEN8_CTX_STATUS_PREEMPTED	(1 << 1)
#define GEN8_CTX_STATUS_ELEMENT_SWITCH	(1 << 2)
#define GEN8_CTX_STATUS_ACTIVE_IDLE	(1 << 3)
#define GEN8_CTX_STATUS_COMPLETE	(1 << 4)
#define GEN8_CTX_STATUS_LITE_RESTORE	(1 << 15)
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#define CTX_LRI_HEADER_0		0x01
#define CTX_CONTEXT_CONTROL		0x02
#define CTX_RING_HEAD			0x04
#define CTX_RING_TAIL			0x06
#define CTX_RING_BUFFER_START		0x08
#define CTX_RING_BUFFER_CONTROL		0x0a
#define CTX_BB_HEAD_U			0x0c
#define CTX_BB_HEAD_L			0x0e
#define CTX_BB_STATE			0x10
#define CTX_SECOND_BB_HEAD_U		0x12
#define CTX_SECOND_BB_HEAD_L		0x14
#define CTX_SECOND_BB_STATE		0x16
#define CTX_BB_PER_CTX_PTR		0x18
#define CTX_RCS_INDIRECT_CTX		0x1a
#define CTX_RCS_INDIRECT_CTX_OFFSET	0x1c
#define CTX_LRI_HEADER_1		0x21
#define CTX_CTX_TIMESTAMP		0x22
#define CTX_PDP3_UDW			0x24
#define CTX_PDP3_LDW			0x26
#define CTX_PDP2_UDW			0x28
#define CTX_PDP2_LDW			0x2a
#define CTX_PDP1_UDW			0x2c
#define CTX_PDP1_LDW			0x2e
#define CTX_PDP0_UDW			0x30
#define CTX_PDP0_LDW			0x32
#define CTX_LRI_HEADER_2		0x41
#define CTX_R_PWR_CLK_STATE		0x42
#define CTX_GPGPU_CSR_BASE_ADDRESS	0x44

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#define GEN8_CTX_VALID (1<<0)
#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
#define GEN8_CTX_FORCE_RESTORE (1<<2)
#define GEN8_CTX_L3LLC_COHERENT (1<<5)
#define GEN8_CTX_PRIVILEGE (1<<8)
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#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
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	const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n));	\
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	reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
	reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
}

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#define ASSIGN_CTX_PML4(ppgtt, reg_state) { \
	reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
	reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
}

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enum {
	ADVANCED_CONTEXT = 0,
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	LEGACY_32B_CONTEXT,
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	ADVANCED_AD_CONTEXT,
	LEGACY_64B_CONTEXT
};
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#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
#define GEN8_CTX_ADDRESSING_MODE(dev)  (USES_FULL_48BIT_PPGTT(dev) ?\
		LEGACY_64B_CONTEXT :\
		LEGACY_32B_CONTEXT)
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enum {
	FAULT_AND_HANG = 0,
	FAULT_AND_HALT, /* Debug only */
	FAULT_AND_STREAM,
	FAULT_AND_CONTINUE /* Unsupported */
};
#define GEN8_CTX_ID_SHIFT 32
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#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT  0x17
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static int intel_lr_context_pin(struct drm_i915_gem_request *rq);
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static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
		struct drm_i915_gem_object *default_ctx_obj);

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/**
 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 * @dev: DRM device.
 * @enable_execlists: value of i915.enable_execlists module parameter.
 *
 * Only certain platforms support Execlists (the prerequisites being
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 * support for Logical Ring Contexts and Aliasing PPGTT or better).
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 *
 * Return: 1 if Execlists is supported and has to be enabled.
 */
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int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
{
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	WARN_ON(i915.enable_ppgtt == -1);

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	/* On platforms with execlist available, vGPU will only
	 * support execlist mode, no ring buffer mode.
	 */
	if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
		return 1;

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	if (INTEL_INFO(dev)->gen >= 9)
		return 1;

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	if (enable_execlists == 0)
		return 0;

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	if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
	    i915.use_mmio_flip >= 0)
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		return 1;

	return 0;
}
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/**
 * intel_execlists_ctx_id() - get the Execlists Context ID
 * @ctx_obj: Logical Ring Context backing object.
 *
 * Do not confuse with ctx->id! Unfortunately we have a name overload
 * here: the old context ID we pass to userspace as a handler so that
 * they can refer to a context, and the new context ID we pass to the
 * ELSP so that the GPU can inform us of the context status via
 * interrupts.
 *
 * Return: 20-bits globally unique context ID.
 */
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u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
{
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	u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj) +
			LRC_PPHWSP_PN * PAGE_SIZE;
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	/* LRCA is required to be 4K aligned so the more significant 20 bits
	 * are globally unique */
	return lrca >> 12;
}

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static bool disable_lite_restore_wa(struct intel_engine_cs *ring)
{
	struct drm_device *dev = ring->dev;

	return ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
		(IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) &&
	       (ring->id == VCS || ring->id == VCS2);
}

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uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
				     struct intel_engine_cs *ring)
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{
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	struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
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	uint64_t desc;
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	uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj) +
			LRC_PPHWSP_PN * PAGE_SIZE;
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	WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
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	desc = GEN8_CTX_VALID;
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	desc |= GEN8_CTX_ADDRESSING_MODE(dev) << GEN8_CTX_ADDRESSING_MODE_SHIFT;
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	if (IS_GEN8(ctx_obj->base.dev))
		desc |= GEN8_CTX_L3LLC_COHERENT;
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	desc |= GEN8_CTX_PRIVILEGE;
	desc |= lrca;
	desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;

	/* TODO: WaDisableLiteRestore when we start using semaphore
	 * signalling between Command Streamers */
	/* desc |= GEN8_CTX_FORCE_RESTORE; */

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	/* WaEnableForceRestoreInCtxtDescForVCS:skl */
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	/* WaEnableForceRestoreInCtxtDescForVCS:bxt */
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	if (disable_lite_restore_wa(ring))
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		desc |= GEN8_CTX_FORCE_RESTORE;

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	return desc;
}

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static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
				 struct drm_i915_gem_request *rq1)
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{
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	struct intel_engine_cs *ring = rq0->ring;
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	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	uint64_t desc[2];
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	if (rq1) {
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		desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring);
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		rq1->elsp_submitted++;
	} else {
		desc[1] = 0;
	}
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	desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring);
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	rq0->elsp_submitted++;
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	/* You must always write both descriptors in the order below. */
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	spin_lock(&dev_priv->uncore.lock);
	intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
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	I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
	I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
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	I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));
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	/* The context is automatically loaded after the following */
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	I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
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	/* ELSP is a wo register, use another nearby reg for posting */
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	POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
	intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
	spin_unlock(&dev_priv->uncore.lock);
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}

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static int execlists_update_context(struct drm_i915_gem_request *rq)
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{
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	struct intel_engine_cs *ring = rq->ring;
	struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
	struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
	struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
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	struct page *page;
	uint32_t *reg_state;

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	BUG_ON(!ctx_obj);
	WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
	WARN_ON(!i915_gem_obj_is_pinned(rb_obj));

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	page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
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	reg_state = kmap_atomic(page);

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	reg_state[CTX_RING_TAIL+1] = rq->tail;
	reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
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	if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
		/* True 32b PPGTT with dynamic page allocation: update PDP
		 * registers and point the unallocated PDPs to scratch page.
		 * PML4 is allocated during ppgtt init, so this is not needed
		 * in 48-bit mode.
		 */
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		ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
	}

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	kunmap_atomic(reg_state);

	return 0;
}

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static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
				      struct drm_i915_gem_request *rq1)
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{
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	execlists_update_context(rq0);
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	if (rq1)
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		execlists_update_context(rq1);
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	execlists_elsp_write(rq0, rq1);
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}

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static void execlists_context_unqueue(struct intel_engine_cs *ring)
{
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	struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
	struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
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	assert_spin_locked(&ring->execlist_lock);
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	/*
	 * If irqs are not active generate a warning as batches that finish
	 * without the irqs may get lost and a GPU Hang may occur.
	 */
	WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));

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	if (list_empty(&ring->execlist_queue))
		return;

	/* Try to read in pairs */
	list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
				 execlist_link) {
		if (!req0) {
			req0 = cursor;
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		} else if (req0->ctx == cursor->ctx) {
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			/* Same ctx: ignore first request, as second request
			 * will update tail past first request's workload */
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			cursor->elsp_submitted = req0->elsp_submitted;
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			list_del(&req0->execlist_link);
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			list_add_tail(&req0->execlist_link,
				&ring->execlist_retired_req_list);
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			req0 = cursor;
		} else {
			req1 = cursor;
			break;
		}
	}

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	if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
		/*
		 * WaIdleLiteRestore: make sure we never cause a lite
		 * restore with HEAD==TAIL
		 */
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		if (req0->elsp_submitted) {
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			/*
			 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
			 * as we resubmit the request. See gen8_emit_request()
			 * for where we prepare the padding after the end of the
			 * request.
			 */
			struct intel_ringbuffer *ringbuf;

			ringbuf = req0->ctx->engine[ring->id].ringbuf;
			req0->tail += 8;
			req0->tail &= ringbuf->size - 1;
		}
	}

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	WARN_ON(req1 && req1->elsp_submitted);

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	execlists_submit_requests(req0, req1);
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}

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static bool execlists_check_remove_request(struct intel_engine_cs *ring,
					   u32 request_id)
{
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	struct drm_i915_gem_request *head_req;
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	assert_spin_locked(&ring->execlist_lock);

	head_req = list_first_entry_or_null(&ring->execlist_queue,
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					    struct drm_i915_gem_request,
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					    execlist_link);

	if (head_req != NULL) {
		struct drm_i915_gem_object *ctx_obj =
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				head_req->ctx->engine[ring->id].state;
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		if (intel_execlists_ctx_id(ctx_obj) == request_id) {
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			WARN(head_req->elsp_submitted == 0,
			     "Never submitted head request\n");

			if (--head_req->elsp_submitted <= 0) {
				list_del(&head_req->execlist_link);
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				list_add_tail(&head_req->execlist_link,
					&ring->execlist_retired_req_list);
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				return true;
			}
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		}
	}

	return false;
}

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/**
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 * intel_lrc_irq_handler() - handle Context Switch interrupts
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 * @ring: Engine Command Streamer to handle.
 *
 * Check the unread Context Status Buffers and manage the submission of new
 * contexts to the ELSP accordingly.
 */
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void intel_lrc_irq_handler(struct intel_engine_cs *ring)
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{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	u32 status_pointer;
	u8 read_pointer;
	u8 write_pointer;
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	u32 status = 0;
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	u32 status_id;
	u32 submit_contexts = 0;

	status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));

	read_pointer = ring->next_context_status_buffer;
	write_pointer = status_pointer & 0x07;
	if (read_pointer > write_pointer)
		write_pointer += 6;

	spin_lock(&ring->execlist_lock);

	while (read_pointer < write_pointer) {
		read_pointer++;
		status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
				(read_pointer % 6) * 8);
		status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
				(read_pointer % 6) * 8 + 4);

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		if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
			continue;

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		if (status & GEN8_CTX_STATUS_PREEMPTED) {
			if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
				if (execlists_check_remove_request(ring, status_id))
					WARN(1, "Lite Restored request removed from queue\n");
			} else
				WARN(1, "Preemption without Lite Restore\n");
		}

		 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
		     (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
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			if (execlists_check_remove_request(ring, status_id))
				submit_contexts++;
		}
	}

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	if (disable_lite_restore_wa(ring)) {
		/* Prevent a ctx to preempt itself */
		if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) &&
		    (submit_contexts != 0))
			execlists_context_unqueue(ring);
	} else if (submit_contexts != 0) {
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		execlists_context_unqueue(ring);
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	}
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	spin_unlock(&ring->execlist_lock);

	WARN(submit_contexts > 2, "More than two context complete events?\n");
	ring->next_context_status_buffer = write_pointer % 6;

	I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
560
		   _MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8));
561 562
}

563
static int execlists_context_queue(struct drm_i915_gem_request *request)
564
{
565
	struct intel_engine_cs *ring = request->ring;
566
	struct drm_i915_gem_request *cursor;
567
	int num_elements = 0;
568

569
	if (request->ctx != ring->default_context)
570
		intel_lr_context_pin(request);
571 572 573

	i915_gem_request_reference(request);

574
	spin_lock_irq(&ring->execlist_lock);
575

576 577 578 579 580
	list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
		if (++num_elements > 2)
			break;

	if (num_elements > 2) {
581
		struct drm_i915_gem_request *tail_req;
582 583

		tail_req = list_last_entry(&ring->execlist_queue,
584
					   struct drm_i915_gem_request,
585 586
					   execlist_link);

587
		if (request->ctx == tail_req->ctx) {
588
			WARN(tail_req->elsp_submitted != 0,
589
				"More than 2 already-submitted reqs queued\n");
590
			list_del(&tail_req->execlist_link);
591 592
			list_add_tail(&tail_req->execlist_link,
				&ring->execlist_retired_req_list);
593 594 595
		}
	}

596
	list_add_tail(&request->execlist_link, &ring->execlist_queue);
597
	if (num_elements == 0)
598 599
		execlists_context_unqueue(ring);

600
	spin_unlock_irq(&ring->execlist_lock);
601 602 603 604

	return 0;
}

605
static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
606
{
607
	struct intel_engine_cs *ring = req->ring;
608 609 610 611 612 613 614
	uint32_t flush_domains;
	int ret;

	flush_domains = 0;
	if (ring->gpu_caches_dirty)
		flush_domains = I915_GEM_GPU_DOMAINS;

615
	ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
616 617 618 619 620 621 622
	if (ret)
		return ret;

	ring->gpu_caches_dirty = false;
	return 0;
}

623
static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
624 625
				 struct list_head *vmas)
{
626
	const unsigned other_rings = ~intel_ring_flag(req->ring);
627 628 629 630 631 632 633 634
	struct i915_vma *vma;
	uint32_t flush_domains = 0;
	bool flush_chipset = false;
	int ret;

	list_for_each_entry(vma, vmas, exec_list) {
		struct drm_i915_gem_object *obj = vma->obj;

635
		if (obj->active & other_rings) {
636
			ret = i915_gem_object_sync(obj, req->ring, &req);
637 638 639
			if (ret)
				return ret;
		}
640 641 642 643 644 645 646 647 648 649 650 651 652

		if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
			flush_chipset |= i915_gem_clflush_object(obj, false);

		flush_domains |= obj->base.write_domain;
	}

	if (flush_domains & I915_GEM_DOMAIN_GTT)
		wmb();

	/* Unconditionally invalidate gpu caches and ensure that we do flush
	 * any residual writes from the previous batch.
	 */
653
	return logical_ring_invalidate_all_caches(req);
654 655
}

656
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
657 658 659
{
	int ret;

660 661
	request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;

662
	if (request->ctx != request->ring->default_context) {
663
		ret = intel_lr_context_pin(request);
664
		if (ret)
665 666 667 668 669 670
			return ret;
	}

	return 0;
}

671
static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
672
				       int bytes)
673
{
674 675 676
	struct intel_ringbuffer *ringbuf = req->ringbuf;
	struct intel_engine_cs *ring = req->ring;
	struct drm_i915_gem_request *target;
677 678
	unsigned space;
	int ret;
679 680 681 682

	if (intel_ring_space(ringbuf) >= bytes)
		return 0;

683 684 685
	/* The whole point of reserving space is to not wait! */
	WARN_ON(ringbuf->reserved_in_use);

686
	list_for_each_entry(target, &ring->request_list, list) {
687 688 689 690 691
		/*
		 * The request queue is per-engine, so can contain requests
		 * from multiple ringbuffers. Here, we must ignore any that
		 * aren't from the ringbuffer we're considering.
		 */
692
		if (target->ringbuf != ringbuf)
693 694 695
			continue;

		/* Would completion of this request free enough space? */
696
		space = __intel_ring_space(target->postfix, ringbuf->tail,
697 698
					   ringbuf->size);
		if (space >= bytes)
699 700 701
			break;
	}

702
	if (WARN_ON(&target->list == &ring->request_list))
703 704
		return -ENOSPC;

705
	ret = i915_wait_request(target);
706 707 708
	if (ret)
		return ret;

709 710
	ringbuf->space = space;
	return 0;
711 712 713 714
}

/*
 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
715
 * @request: Request to advance the logical ringbuffer of.
716 717 718 719 720 721 722
 *
 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 * really happens during submission is that the context and current tail will be placed
 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 * point, the tail *inside* the context is updated and the ELSP written to.
 */
static void
723
intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
724
{
725
	struct intel_engine_cs *ring = request->ring;
726
	struct drm_i915_private *dev_priv = request->i915;
727

728
	intel_logical_ring_advance(request->ringbuf);
729

730 731
	request->tail = request->ringbuf->tail;

732 733 734
	if (intel_ring_stopped(ring))
		return;

735 736 737 738
	if (dev_priv->guc.execbuf_client)
		i915_guc_submit(dev_priv->guc.execbuf_client, request);
	else
		execlists_context_queue(request);
739 740
}

741
static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
742 743 744 745 746 747 748 749 750 751 752 753 754
{
	uint32_t __iomem *virt;
	int rem = ringbuf->size - ringbuf->tail;

	virt = ringbuf->virtual_start + ringbuf->tail;
	rem /= 4;
	while (rem--)
		iowrite32(MI_NOOP, virt++);

	ringbuf->tail = 0;
	intel_ring_update_space(ringbuf);
}

755
static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
756
{
757
	struct intel_ringbuffer *ringbuf = req->ringbuf;
758 759 760 761
	int remain_usable = ringbuf->effective_size - ringbuf->tail;
	int remain_actual = ringbuf->size - ringbuf->tail;
	int ret, total_bytes, wait_bytes = 0;
	bool need_wrap = false;
762

763 764 765 766
	if (ringbuf->reserved_in_use)
		total_bytes = bytes;
	else
		total_bytes = bytes + ringbuf->reserved_size;
767

768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786
	if (unlikely(bytes > remain_usable)) {
		/*
		 * Not enough space for the basic request. So need to flush
		 * out the remainder and then wait for base + reserved.
		 */
		wait_bytes = remain_actual + total_bytes;
		need_wrap = true;
	} else {
		if (unlikely(total_bytes > remain_usable)) {
			/*
			 * The base request will fit but the reserved space
			 * falls off the end. So only need to to wait for the
			 * reserved size after flushing out the remainder.
			 */
			wait_bytes = remain_actual + ringbuf->reserved_size;
			need_wrap = true;
		} else if (total_bytes > ringbuf->space) {
			/* No wrapping required, just waiting. */
			wait_bytes = total_bytes;
787
		}
788 789
	}

790 791
	if (wait_bytes) {
		ret = logical_ring_wait_for_space(req, wait_bytes);
792 793
		if (unlikely(ret))
			return ret;
794 795 796

		if (need_wrap)
			__wrap_ring_buffer(ringbuf);
797 798 799 800 801 802 803 804
	}

	return 0;
}

/**
 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
 *
805
 * @req: The request to start some new work for
806 807 808 809 810 811 812 813 814
 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
 *
 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
 * and also preallocates a request (every workload submission is still mediated through
 * requests, same as it did with legacy ringbuffer submission).
 *
 * Return: non-zero if the ringbuffer is not ready to be written to.
 */
815
int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
816
{
817
	struct drm_i915_private *dev_priv;
818 819
	int ret;

820 821 822
	WARN_ON(req == NULL);
	dev_priv = req->ring->dev->dev_private;

823 824 825 826 827
	ret = i915_gem_check_wedge(&dev_priv->gpu_error,
				   dev_priv->mm.interruptible);
	if (ret)
		return ret;

828
	ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
829 830 831
	if (ret)
		return ret;

832
	req->ringbuf->space -= num_dwords * sizeof(uint32_t);
833 834 835
	return 0;
}

836 837 838 839 840 841 842 843 844 845 846 847 848 849 850
int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
{
	/*
	 * The first call merely notes the reserve request and is common for
	 * all back ends. The subsequent localised _begin() call actually
	 * ensures that the reservation is available. Without the begin, if
	 * the request creator immediately submitted the request without
	 * adding any commands to it then there might not actually be
	 * sufficient room for the submission commands.
	 */
	intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);

	return intel_logical_ring_begin(request, 0);
}

851 852 853 854 855 856 857 858 859 860
/**
 * execlists_submission() - submit a batchbuffer for execution, Execlists style
 * @dev: DRM device.
 * @file: DRM file.
 * @ring: Engine Command Streamer to submit to.
 * @ctx: Context to employ for this submission.
 * @args: execbuffer call arguments.
 * @vmas: list of vmas.
 * @batch_obj: the batchbuffer to submit.
 * @exec_start: batchbuffer start virtual address pointer.
861
 * @dispatch_flags: translated execbuffer call flags.
862 863 864 865 866 867
 *
 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 * away the submission details of the execbuffer ioctl call.
 *
 * Return: non-zero if the submission fails.
 */
868
int intel_execlists_submission(struct i915_execbuffer_params *params,
869
			       struct drm_i915_gem_execbuffer2 *args,
870
			       struct list_head *vmas)
871
{
872 873
	struct drm_device       *dev = params->dev;
	struct intel_engine_cs  *ring = params->ring;
874
	struct drm_i915_private *dev_priv = dev->dev_private;
875 876
	struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
	u64 exec_start;
877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926
	int instp_mode;
	u32 instp_mask;
	int ret;

	instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
	instp_mask = I915_EXEC_CONSTANTS_MASK;
	switch (instp_mode) {
	case I915_EXEC_CONSTANTS_REL_GENERAL:
	case I915_EXEC_CONSTANTS_ABSOLUTE:
	case I915_EXEC_CONSTANTS_REL_SURFACE:
		if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
			DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
			return -EINVAL;
		}

		if (instp_mode != dev_priv->relative_constants_mode) {
			if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
				DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
				return -EINVAL;
			}

			/* The HW changed the meaning on this bit on gen6 */
			instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
		}
		break;
	default:
		DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
		return -EINVAL;
	}

	if (args->num_cliprects != 0) {
		DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
		return -EINVAL;
	} else {
		if (args->DR4 == 0xffffffff) {
			DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
			args->DR4 = 0;
		}

		if (args->DR1 || args->DR4 || args->cliprects_ptr) {
			DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
			return -EINVAL;
		}
	}

	if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
		DRM_DEBUG("sol reset is gen7 only\n");
		return -EINVAL;
	}

927
	ret = execlists_move_to_gpu(params->request, vmas);
928 929 930 931 932
	if (ret)
		return ret;

	if (ring == &dev_priv->ring[RCS] &&
	    instp_mode != dev_priv->relative_constants_mode) {
933
		ret = intel_logical_ring_begin(params->request, 4);
934 935 936 937 938 939 940 941 942 943 944 945
		if (ret)
			return ret;

		intel_logical_ring_emit(ringbuf, MI_NOOP);
		intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
		intel_logical_ring_emit(ringbuf, INSTPM);
		intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
		intel_logical_ring_advance(ringbuf);

		dev_priv->relative_constants_mode = instp_mode;
	}

946 947 948
	exec_start = params->batch_obj_vm_offset +
		     args->batch_start_offset;

949
	ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);
950 951 952
	if (ret)
		return ret;

953
	trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
954

955
	i915_gem_execbuffer_move_to_active(vmas, params->request);
956
	i915_gem_execbuffer_retire_commands(params);
957

958 959 960
	return 0;
}

961 962
void intel_execlists_retire_requests(struct intel_engine_cs *ring)
{
963
	struct drm_i915_gem_request *req, *tmp;
964 965 966 967 968 969 970
	struct list_head retired_list;

	WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
	if (list_empty(&ring->execlist_retired_req_list))
		return;

	INIT_LIST_HEAD(&retired_list);
971
	spin_lock_irq(&ring->execlist_lock);
972
	list_replace_init(&ring->execlist_retired_req_list, &retired_list);
973
	spin_unlock_irq(&ring->execlist_lock);
974 975

	list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
976
		struct intel_context *ctx = req->ctx;
977 978 979 980
		struct drm_i915_gem_object *ctx_obj =
				ctx->engine[ring->id].state;

		if (ctx_obj && (ctx != ring->default_context))
981
			intel_lr_context_unpin(req);
982
		list_del(&req->execlist_link);
983
		i915_gem_request_unreference(req);
984 985 986
	}
}

987 988
void intel_logical_ring_stop(struct intel_engine_cs *ring)
{
989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	int ret;

	if (!intel_ring_initialized(ring))
		return;

	ret = intel_ring_idle(ring);
	if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
		DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
			  ring->name, ret);

	/* TODO: Is this correct with Execlists enabled? */
	I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
	if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
		DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
		return;
	}
	I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
1007 1008
}

1009
int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
1010
{
1011
	struct intel_engine_cs *ring = req->ring;
1012 1013 1014 1015 1016
	int ret;

	if (!ring->gpu_caches_dirty)
		return 0;

1017
	ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
1018 1019 1020 1021 1022 1023 1024
	if (ret)
		return ret;

	ring->gpu_caches_dirty = false;
	return 0;
}

1025 1026 1027
static int intel_lr_context_do_pin(struct intel_engine_cs *ring,
		struct drm_i915_gem_object *ctx_obj,
		struct intel_ringbuffer *ringbuf)
1028
{
1029 1030
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1031 1032 1033
	int ret = 0;

	WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1034 1035 1036 1037
	ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,
			PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
	if (ret)
		return ret;
1038

1039 1040 1041
	ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
	if (ret)
		goto unpin_ctx_obj;
1042

1043
	ctx_obj->dirty = true;
1044

1045 1046 1047
	/* Invalidate GuC TLB. */
	if (i915.enable_guc_submission)
		I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
1048

1049 1050 1051 1052
	return ret;

unpin_ctx_obj:
	i915_gem_object_ggtt_unpin(ctx_obj);
1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070

	return ret;
}

static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
{
	int ret = 0;
	struct intel_engine_cs *ring = rq->ring;
	struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
	struct intel_ringbuffer *ringbuf = rq->ringbuf;

	if (rq->ctx->engine[ring->id].pin_count++ == 0) {
		ret = intel_lr_context_do_pin(ring, ctx_obj, ringbuf);
		if (ret)
			goto reset_pin_count;
	}
	return ret;

1071
reset_pin_count:
1072
	rq->ctx->engine[ring->id].pin_count = 0;
1073 1074 1075
	return ret;
}

1076
void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
1077
{
1078 1079 1080
	struct intel_engine_cs *ring = rq->ring;
	struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
	struct intel_ringbuffer *ringbuf = rq->ringbuf;
1081 1082 1083

	if (ctx_obj) {
		WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1084
		if (--rq->ctx->engine[ring->id].pin_count == 0) {
1085
			intel_unpin_ringbuffer_obj(ringbuf);
1086
			i915_gem_object_ggtt_unpin(ctx_obj);
1087
		}
1088 1089 1090
	}
}

1091
static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1092 1093
{
	int ret, i;
1094 1095
	struct intel_engine_cs *ring = req->ring;
	struct intel_ringbuffer *ringbuf = req->ringbuf;
1096 1097 1098 1099
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_workarounds *w = &dev_priv->workarounds;

1100
	if (WARN_ON_ONCE(w->count == 0))
1101 1102 1103
		return 0;

	ring->gpu_caches_dirty = true;
1104
	ret = logical_ring_flush_all_caches(req);
1105 1106 1107
	if (ret)
		return ret;

1108
	ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121
	if (ret)
		return ret;

	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
	for (i = 0; i < w->count; i++) {
		intel_logical_ring_emit(ringbuf, w->reg[i].addr);
		intel_logical_ring_emit(ringbuf, w->reg[i].value);
	}
	intel_logical_ring_emit(ringbuf, MI_NOOP);

	intel_logical_ring_advance(ringbuf);

	ring->gpu_caches_dirty = true;
1122
	ret = logical_ring_flush_all_caches(req);
1123 1124 1125 1126 1127 1128
	if (ret)
		return ret;

	return 0;
}

1129
#define wa_ctx_emit(batch, index, cmd)					\
1130
	do {								\
1131 1132
		int __index = (index)++;				\
		if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1133 1134
			return -ENOSPC;					\
		}							\
1135
		batch[__index] = (cmd);					\
1136 1137
	} while (0)

1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160

/*
 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
 * but there is a slight complication as this is applied in WA batch where the
 * values are only initialized once so we cannot take register value at the
 * beginning and reuse it further; hence we save its value to memory, upload a
 * constant value with bit21 set and then we restore it back with the saved value.
 * To simplify the WA, a constant value is formed by using the default value
 * of this register. This shouldn't be a problem because we are only modifying
 * it for a short period and this batch in non-premptible. We can ofcourse
 * use additional instructions that read the actual value of the register
 * at that time and set our bit of interest but it makes the WA complicated.
 *
 * This WA is also required for Gen9 so extracting as a function avoids
 * code duplication.
 */
static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
						uint32_t *const batch,
						uint32_t index)
{
	uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);

1161 1162 1163 1164 1165 1166 1167 1168 1169
	/*
	 * WaDisableLSQCROPERFforOCL:skl
	 * This WA is implemented in skl_init_clock_gating() but since
	 * this batch updates GEN8_L3SQCREG4 with default value we need to
	 * set this bit here to retain the WA during flush.
	 */
	if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0)
		l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;

1170
	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187
				   MI_SRM_LRM_GLOBAL_GTT));
	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
	wa_ctx_emit(batch, index, 0);

	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
	wa_ctx_emit(batch, index, l3sqc4_flush);

	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_DC_FLUSH_ENABLE));
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);

1188
	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1189 1190 1191 1192
				   MI_SRM_LRM_GLOBAL_GTT));
	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
	wa_ctx_emit(batch, index, 0);
1193 1194 1195 1196

	return index;
}

1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234
static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t offset,
				    uint32_t start_alignment)
{
	return wa_ctx->offset = ALIGN(offset, start_alignment);
}

static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
			     uint32_t offset,
			     uint32_t size_alignment)
{
	wa_ctx->size = offset - wa_ctx->offset;

	WARN(wa_ctx->size % size_alignment,
	     "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
	     wa_ctx->size, size_alignment);
	return 0;
}

/**
 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
 *
 * @ring: only applicable for RCS
 * @wa_ctx: structure representing wa_ctx
 *  offset: specifies start of the batch, should be cache-aligned. This is updated
 *    with the offset value received as input.
 *  size: size of the batch in DWORDS but HW expects in terms of cachelines
 * @batch: page in which WA are loaded
 * @offset: This field specifies the start of the batch, it should be
 *  cache-aligned otherwise it is adjusted accordingly.
 *  Typically we only have one indirect_ctx and per_ctx batch buffer which are
 *  initialized at the beginning and shared across all contexts but this field
 *  helps us to have multiple batches at different offsets and select them based
 *  on a criteria. At the moment this batch always start at the beginning of the page
 *  and at this point we don't have multiple wa_ctx batch buffers.
 *
 *  The number of WA applied are not known at the beginning; we use this field
 *  to return the no of DWORDS written.
1235
 *
1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248
 *  It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
 *  so it adds NOOPs as padding to make it cacheline aligned.
 *  MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
 *  makes a complete batch buffer.
 *
 * Return: non-zero if we exceed the PAGE_SIZE limit.
 */

static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
				    struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t *const batch,
				    uint32_t *offset)
{
1249
	uint32_t scratch_addr;
1250 1251
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1252
	/* WaDisableCtxRestoreArbitration:bdw,chv */
1253
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1254

1255 1256
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
	if (IS_BROADWELL(ring->dev)) {
1257 1258 1259
		index = gen8_emit_flush_coherentl3_wa(ring, batch, index);
		if (index < 0)
			return index;
1260 1261
	}

1262 1263 1264 1265
	/* WaClearSlmSpaceAtContextSwitch:bdw,chv */
	/* Actual scratch location is at 128 bytes offset */
	scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES;

1266 1267 1268 1269 1270 1271 1272 1273 1274
	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
				   PIPE_CONTROL_GLOBAL_GTT_IVB |
				   PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_QW_WRITE));
	wa_ctx_emit(batch, index, scratch_addr);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
1275

1276 1277
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
1278
		wa_ctx_emit(batch, index, MI_NOOP);
1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295

	/*
	 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
	 * execution depends on the length specified in terms of cache lines
	 * in the register CTX_RCS_INDIRECT_CTX
	 */

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

/**
 * gen8_init_perctx_bb() - initialize per ctx batch with WA
 *
 * @ring: only applicable for RCS
 * @wa_ctx: structure representing wa_ctx
 *  offset: specifies start of the batch, should be cache-aligned.
 *  size: size of the batch in DWORDS but HW expects in terms of cachelines
1296
 * @batch: page in which WA are loaded
1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312
 * @offset: This field specifies the start of this batch.
 *   This batch is started immediately after indirect_ctx batch. Since we ensure
 *   that indirect_ctx ends on a cacheline this batch is aligned automatically.
 *
 *   The number of DWORDS written are returned using this field.
 *
 *  This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
 *  to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
 */
static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
			       struct i915_wa_ctx_bb *wa_ctx,
			       uint32_t *const batch,
			       uint32_t *offset)
{
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1313
	/* WaDisableCtxRestoreArbitration:bdw,chv */
1314
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1315

1316
	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1317 1318 1319 1320

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1321 1322 1323 1324 1325
static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
				    struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t *const batch,
				    uint32_t *offset)
{
1326
	int ret;
1327
	struct drm_device *dev = ring->dev;
1328 1329
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1330 1331 1332 1333
	/* WaDisableCtxRestoreArbitration:skl,bxt */
	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1334

1335 1336 1337 1338 1339 1340
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
	ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);
	if (ret < 0)
		return ret;
	index = ret;

1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
		wa_ctx_emit(batch, index, MI_NOOP);

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
			       struct i915_wa_ctx_bb *wa_ctx,
			       uint32_t *const batch,
			       uint32_t *offset)
{
1353
	struct drm_device *dev = ring->dev;
1354 1355
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1356 1357 1358 1359 1360 1361 1362 1363 1364 1365
	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
		wa_ctx_emit(batch, index,
			    _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
		wa_ctx_emit(batch, index, MI_NOOP);
	}

1366 1367 1368 1369 1370
	/* WaDisableCtxRestoreArbitration:skl,bxt */
	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);

1371 1372 1373 1374 1375
	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415
static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
{
	int ret;

	ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size));
	if (!ring->wa_ctx.obj) {
		DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
		return -ENOMEM;
	}

	ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0);
	if (ret) {
		DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
				 ret);
		drm_gem_object_unreference(&ring->wa_ctx.obj->base);
		return ret;
	}

	return 0;
}

static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring)
{
	if (ring->wa_ctx.obj) {
		i915_gem_object_ggtt_unpin(ring->wa_ctx.obj);
		drm_gem_object_unreference(&ring->wa_ctx.obj->base);
		ring->wa_ctx.obj = NULL;
	}
}

static int intel_init_workaround_bb(struct intel_engine_cs *ring)
{
	int ret;
	uint32_t *batch;
	uint32_t offset;
	struct page *page;
	struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;

	WARN_ON(ring->id != RCS);

1416
	/* update this when WA for higher Gen are added */
1417 1418 1419
	if (INTEL_INFO(ring->dev)->gen > 9) {
		DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
			  INTEL_INFO(ring->dev)->gen);
1420
		return 0;
1421
	}
1422

1423 1424 1425 1426 1427 1428
	/* some WA perform writes to scratch page, ensure it is valid */
	if (ring->scratch.obj == NULL) {
		DRM_ERROR("scratch page not allocated for %s\n", ring->name);
		return -EINVAL;
	}

1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452
	ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
		return ret;
	}

	page = i915_gem_object_get_page(wa_ctx->obj, 0);
	batch = kmap_atomic(page);
	offset = 0;

	if (INTEL_INFO(ring->dev)->gen == 8) {
		ret = gen8_init_indirectctx_bb(ring,
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

		ret = gen8_init_perctx_bb(ring,
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466
	} else if (INTEL_INFO(ring->dev)->gen == 9) {
		ret = gen9_init_indirectctx_bb(ring,
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

		ret = gen9_init_perctx_bb(ring,
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1467 1468 1469 1470 1471 1472 1473 1474 1475 1476
	}

out:
	kunmap_atomic(batch);
	if (ret)
		lrc_destroy_wa_ctx_obj(ring);

	return ret;
}

1477 1478 1479 1480 1481
static int gen8_init_common_ring(struct intel_engine_cs *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

1482 1483 1484
	lrc_setup_hardware_status_page(ring,
				ring->default_context->engine[ring->id].state);

1485 1486 1487
	I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
	I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);

1488 1489 1490 1491 1492 1493
	if (ring->status_page.obj) {
		I915_WRITE(RING_HWS_PGA(ring->mmio_base),
			   (u32)ring->status_page.gfx_addr);
		POSTING_READ(RING_HWS_PGA(ring->mmio_base));
	}

1494 1495 1496 1497
	I915_WRITE(RING_MODE_GEN7(ring),
		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
	POSTING_READ(RING_MODE_GEN7(ring));
1498
	ring->next_context_status_buffer = 0;
1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525
	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);

	memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));

	return 0;
}

static int gen8_init_render_ring(struct intel_engine_cs *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = gen8_init_common_ring(ring);
	if (ret)
		return ret;

	/* We need to disable the AsyncFlip performance optimisations in order
	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
	 * programmed to '1' on all products.
	 *
	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
	 */
	I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));

	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));

1526
	return init_workarounds_ring(ring);
1527 1528
}

1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539
static int gen9_init_render_ring(struct intel_engine_cs *ring)
{
	int ret;

	ret = gen8_init_common_ring(ring);
	if (ret)
		return ret;

	return init_workarounds_ring(ring);
}

1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
	struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
	struct intel_engine_cs *ring = req->ring;
	struct intel_ringbuffer *ringbuf = req->ringbuf;
	const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
	int i, ret;

	ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
	if (ret)
		return ret;

	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);

		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
		intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
		intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
		intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
	}

	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1568
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1569
			      u64 offset, unsigned dispatch_flags)
1570
{
1571
	struct intel_ringbuffer *ringbuf = req->ringbuf;
1572
	bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1573 1574
	int ret;

1575 1576 1577 1578
	/* Don't rely in hw updating PDPs, specially in lite-restore.
	 * Ideally, we should set Force PD Restore in ctx descriptor,
	 * but we can't. Force Restore would be a second option, but
	 * it is unsafe in case of lite-restore (because the ctx is
1579 1580
	 * not idle). PML4 is allocated during ppgtt init so this is
	 * not needed in 48-bit.*/
1581 1582
	if (req->ctx->ppgtt &&
	    (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
1583 1584
		if (!USES_FULL_48BIT_PPGTT(req->i915) &&
		    !intel_vgpu_active(req->i915->dev)) {
1585 1586 1587 1588
			ret = intel_logical_ring_emit_pdps(req);
			if (ret)
				return ret;
		}
1589 1590 1591 1592

		req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
	}

1593
	ret = intel_logical_ring_begin(req, 4);
1594 1595 1596 1597
	if (ret)
		return ret;

	/* FIXME(BDW): Address space and security selectors. */
1598 1599 1600 1601
	intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
				(ppgtt<<8) |
				(dispatch_flags & I915_DISPATCH_RS ?
				 MI_BATCH_RESOURCE_STREAMER : 0));
1602 1603 1604 1605 1606 1607 1608 1609
	intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
	intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1610 1611 1612 1613 1614 1615
static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long flags;

1616
	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642
		return false;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	if (ring->irq_refcount++ == 0) {
		I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
		POSTING_READ(RING_IMR(ring->mmio_base));
	}
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	return true;
}

static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	if (--ring->irq_refcount == 0) {
		I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
		POSTING_READ(RING_IMR(ring->mmio_base));
	}
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
}

1643
static int gen8_emit_flush(struct drm_i915_gem_request *request,
1644 1645 1646
			   u32 invalidate_domains,
			   u32 unused)
{
1647
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1648 1649 1650 1651 1652 1653
	struct intel_engine_cs *ring = ringbuf->ring;
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t cmd;
	int ret;

1654
	ret = intel_logical_ring_begin(request, 4);
1655 1656 1657 1658 1659
	if (ret)
		return ret;

	cmd = MI_FLUSH_DW + 1;

1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670
	/* We always require a command barrier so that subsequent
	 * commands, such as breadcrumb interrupts, are strictly ordered
	 * wrt the contents of the write cache being flushed to memory
	 * (and thus being coherent from the CPU).
	 */
	cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;

	if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
		cmd |= MI_INVALIDATE_TLB;
		if (ring == &dev_priv->ring[VCS])
			cmd |= MI_INVALIDATE_BSD;
1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683
	}

	intel_logical_ring_emit(ringbuf, cmd);
	intel_logical_ring_emit(ringbuf,
				I915_GEM_HWS_SCRATCH_ADDR |
				MI_FLUSH_DW_USE_GTT);
	intel_logical_ring_emit(ringbuf, 0); /* upper addr */
	intel_logical_ring_emit(ringbuf, 0); /* value */
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1684
static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1685 1686 1687
				  u32 invalidate_domains,
				  u32 flush_domains)
{
1688
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1689 1690
	struct intel_engine_cs *ring = ringbuf->ring;
	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1691
	bool vf_flush_wa;
1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712
	u32 flags = 0;
	int ret;

	flags |= PIPE_CONTROL_CS_STALL;

	if (flush_domains) {
		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
	}

	if (invalidate_domains) {
		flags |= PIPE_CONTROL_TLB_INVALIDATE;
		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_QW_WRITE;
		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
	}

1713 1714 1715 1716 1717 1718 1719
	/*
	 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
	 * control.
	 */
	vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
		      flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;

1720
	ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1721 1722 1723
	if (ret)
		return ret;

1724 1725 1726 1727 1728 1729 1730 1731 1732
	if (vf_flush_wa) {
		intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
		intel_logical_ring_emit(ringbuf, 0);
	}

1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743
	intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
	intel_logical_ring_emit(ringbuf, flags);
	intel_logical_ring_emit(ringbuf, scratch_addr);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_emit(ringbuf, 0);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

1744 1745 1746 1747 1748 1749 1750 1751 1752 1753
static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
{
	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
}

static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
{
	intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
}

1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781
static u32 bxt_a_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
{

	/*
	 * On BXT A steppings there is a HW coherency issue whereby the
	 * MI_STORE_DATA_IMM storing the completed request's seqno
	 * occasionally doesn't invalidate the CPU cache. Work around this by
	 * clflushing the corresponding cacheline whenever the caller wants
	 * the coherency to be guaranteed. Note that this cacheline is known
	 * to be clean at this point, since we only write it in
	 * bxt_a_set_seqno(), where we also do a clflush after the write. So
	 * this clflush in practice becomes an invalidate operation.
	 */

	if (!lazy_coherency)
		intel_flush_status_page(ring, I915_GEM_HWS_INDEX);

	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
}

static void bxt_a_set_seqno(struct intel_engine_cs *ring, u32 seqno)
{
	intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);

	/* See bxt_a_get_seqno() explaining the reason for the clflush. */
	intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
}

1782
static int gen8_emit_request(struct drm_i915_gem_request *request)
1783
{
1784
	struct intel_ringbuffer *ringbuf = request->ringbuf;
1785 1786 1787 1788
	struct intel_engine_cs *ring = ringbuf->ring;
	u32 cmd;
	int ret;

1789 1790 1791 1792 1793
	/*
	 * Reserve space for 2 NOOPs at the end of each request to be
	 * used as a workaround for not being allowed to do lite
	 * restore with HEAD==TAIL (WaIdleLiteRestore).
	 */
1794
	ret = intel_logical_ring_begin(request, 8);
1795 1796 1797
	if (ret)
		return ret;

1798
	cmd = MI_STORE_DWORD_IMM_GEN4;
1799 1800 1801 1802 1803 1804 1805
	cmd |= MI_GLOBAL_GTT;

	intel_logical_ring_emit(ringbuf, cmd);
	intel_logical_ring_emit(ringbuf,
				(ring->status_page.gfx_addr +
				(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
	intel_logical_ring_emit(ringbuf, 0);
1806
	intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1807 1808
	intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
	intel_logical_ring_emit(ringbuf, MI_NOOP);
1809
	intel_logical_ring_advance_and_submit(request);
1810

1811 1812 1813 1814 1815 1816 1817 1818
	/*
	 * Here we add two extra NOOPs as padding to avoid
	 * lite restore of a context with HEAD==TAIL.
	 */
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);

1819 1820 1821
	return 0;
}

1822
static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1823 1824 1825 1826
{
	struct render_state so;
	int ret;

1827
	ret = i915_gem_render_state_prepare(req->ring, &so);
1828 1829 1830 1831 1832 1833
	if (ret)
		return ret;

	if (so.rodata == NULL)
		return 0;

1834
	ret = req->ring->emit_bb_start(req, so.ggtt_offset,
1835
				       I915_DISPATCH_SECURE);
1836 1837 1838
	if (ret)
		goto out;

1839 1840 1841 1842 1843 1844
	ret = req->ring->emit_bb_start(req,
				       (so.ggtt_offset + so.aux_batch_offset),
				       I915_DISPATCH_SECURE);
	if (ret)
		goto out;

1845
	i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1846 1847 1848 1849 1850 1851

out:
	i915_gem_render_state_fini(&so);
	return ret;
}

1852
static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1853 1854 1855
{
	int ret;

1856
	ret = intel_logical_ring_workarounds_emit(req);
1857 1858 1859
	if (ret)
		return ret;

1860 1861 1862 1863 1864 1865 1866 1867
	ret = intel_rcs_context_init_mocs(req);
	/*
	 * Failing to program the MOCS is non-fatal.The system will not
	 * run at peak performance. So generate an error and carry on.
	 */
	if (ret)
		DRM_ERROR("MOCS failed to program: expect performance issues.\n");

1868
	return intel_lr_context_render_state_init(req);
1869 1870
}

1871 1872 1873 1874 1875 1876
/**
 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
 *
 * @ring: Engine Command Streamer.
 *
 */
1877 1878
void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
{
1879
	struct drm_i915_private *dev_priv;
1880

1881 1882 1883
	if (!intel_ring_initialized(ring))
		return;

1884 1885
	dev_priv = ring->dev->dev_private;

1886 1887
	intel_logical_ring_stop(ring);
	WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1888 1889 1890 1891 1892

	if (ring->cleanup)
		ring->cleanup(ring);

	i915_cmd_parser_fini_ring(ring);
1893
	i915_gem_batch_pool_fini(&ring->batch_pool);
1894 1895 1896 1897 1898

	if (ring->status_page.obj) {
		kunmap(sg_page(ring->status_page.obj->pages->sgl));
		ring->status_page.obj = NULL;
	}
1899 1900

	lrc_destroy_wa_ctx_obj(ring);
1901 1902 1903 1904
}

static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
{
1905 1906 1907 1908 1909 1910 1911 1912
	int ret;

	/* Intentionally left blank. */
	ring->buffer = NULL;

	ring->dev = dev;
	INIT_LIST_HEAD(&ring->active_list);
	INIT_LIST_HEAD(&ring->request_list);
1913
	i915_gem_batch_pool_init(dev, &ring->batch_pool);
1914 1915
	init_waitqueue_head(&ring->irq_queue);

1916
	INIT_LIST_HEAD(&ring->execlist_queue);
1917
	INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1918 1919
	spin_lock_init(&ring->execlist_lock);

1920 1921 1922 1923
	ret = i915_cmd_parser_init_ring(ring);
	if (ret)
		return ret;

1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938
	ret = intel_lr_context_deferred_alloc(ring->default_context, ring);
	if (ret)
		return ret;

	/* As this is the default context, always pin it */
	ret = intel_lr_context_do_pin(
			ring,
			ring->default_context->engine[ring->id].state,
			ring->default_context->engine[ring->id].ringbuf);
	if (ret) {
		DRM_ERROR(
			"Failed to pin and map ringbuffer %s: %d\n",
			ring->name, ret);
		return ret;
	}
1939 1940

	return ret;
1941 1942 1943 1944 1945 1946
}

static int logical_render_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1947
	int ret;
1948 1949 1950 1951 1952 1953

	ring->name = "render ring";
	ring->id = RCS;
	ring->mmio_base = RENDER_RING_BASE;
	ring->irq_enable_mask =
		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1954 1955 1956 1957
	ring->irq_keep_mask =
		GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
	if (HAS_L3_DPF(dev))
		ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1958

1959 1960 1961 1962
	if (INTEL_INFO(dev)->gen >= 9)
		ring->init_hw = gen9_init_render_ring;
	else
		ring->init_hw = gen8_init_render_ring;
1963
	ring->init_context = gen8_init_rcs_context;
1964
	ring->cleanup = intel_fini_pipe_control;
1965 1966 1967 1968 1969 1970 1971
	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
		ring->get_seqno = bxt_a_get_seqno;
		ring->set_seqno = bxt_a_set_seqno;
	} else {
		ring->get_seqno = gen8_get_seqno;
		ring->set_seqno = gen8_set_seqno;
	}
1972
	ring->emit_request = gen8_emit_request;
1973
	ring->emit_flush = gen8_emit_flush_render;
1974 1975
	ring->irq_get = gen8_logical_ring_get_irq;
	ring->irq_put = gen8_logical_ring_put_irq;
1976
	ring->emit_bb_start = gen8_emit_bb_start;
1977

1978
	ring->dev = dev;
1979 1980

	ret = intel_init_pipe_control(ring);
1981 1982 1983
	if (ret)
		return ret;

1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994
	ret = intel_init_workaround_bb(ring);
	if (ret) {
		/*
		 * We continue even if we fail to initialize WA batch
		 * because we only expect rare glitches but nothing
		 * critical to prevent us from using GPU
		 */
		DRM_ERROR("WA batch buffer initialization failed: %d\n",
			  ret);
	}

1995 1996
	ret = logical_ring_init(dev, ring);
	if (ret) {
1997
		lrc_destroy_wa_ctx_obj(ring);
1998
	}
1999 2000

	return ret;
2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012
}

static int logical_bsd_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring = &dev_priv->ring[VCS];

	ring->name = "bsd ring";
	ring->id = VCS;
	ring->mmio_base = GEN6_BSD_RING_BASE;
	ring->irq_enable_mask =
		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2013 2014
	ring->irq_keep_mask =
		GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2015

2016
	ring->init_hw = gen8_init_common_ring;
2017 2018 2019 2020 2021 2022 2023
	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
		ring->get_seqno = bxt_a_get_seqno;
		ring->set_seqno = bxt_a_set_seqno;
	} else {
		ring->get_seqno = gen8_get_seqno;
		ring->set_seqno = gen8_set_seqno;
	}
2024
	ring->emit_request = gen8_emit_request;
2025
	ring->emit_flush = gen8_emit_flush;
2026 2027
	ring->irq_get = gen8_logical_ring_get_irq;
	ring->irq_put = gen8_logical_ring_put_irq;
2028
	ring->emit_bb_start = gen8_emit_bb_start;
2029

2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042
	return logical_ring_init(dev, ring);
}

static int logical_bsd2_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring = &dev_priv->ring[VCS2];

	ring->name = "bds2 ring";
	ring->id = VCS2;
	ring->mmio_base = GEN8_BSD2_RING_BASE;
	ring->irq_enable_mask =
		GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2043 2044
	ring->irq_keep_mask =
		GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2045

2046
	ring->init_hw = gen8_init_common_ring;
2047 2048
	ring->get_seqno = gen8_get_seqno;
	ring->set_seqno = gen8_set_seqno;
2049
	ring->emit_request = gen8_emit_request;
2050
	ring->emit_flush = gen8_emit_flush;
2051 2052
	ring->irq_get = gen8_logical_ring_get_irq;
	ring->irq_put = gen8_logical_ring_put_irq;
2053
	ring->emit_bb_start = gen8_emit_bb_start;
2054

2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067
	return logical_ring_init(dev, ring);
}

static int logical_blt_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring = &dev_priv->ring[BCS];

	ring->name = "blitter ring";
	ring->id = BCS;
	ring->mmio_base = BLT_RING_BASE;
	ring->irq_enable_mask =
		GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2068 2069
	ring->irq_keep_mask =
		GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2070

2071
	ring->init_hw = gen8_init_common_ring;
2072 2073 2074 2075 2076 2077 2078
	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
		ring->get_seqno = bxt_a_get_seqno;
		ring->set_seqno = bxt_a_set_seqno;
	} else {
		ring->get_seqno = gen8_get_seqno;
		ring->set_seqno = gen8_set_seqno;
	}
2079
	ring->emit_request = gen8_emit_request;
2080
	ring->emit_flush = gen8_emit_flush;
2081 2082
	ring->irq_get = gen8_logical_ring_get_irq;
	ring->irq_put = gen8_logical_ring_put_irq;
2083
	ring->emit_bb_start = gen8_emit_bb_start;
2084

2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097
	return logical_ring_init(dev, ring);
}

static int logical_vebox_ring_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring = &dev_priv->ring[VECS];

	ring->name = "video enhancement ring";
	ring->id = VECS;
	ring->mmio_base = VEBOX_RING_BASE;
	ring->irq_enable_mask =
		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2098 2099
	ring->irq_keep_mask =
		GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2100

2101
	ring->init_hw = gen8_init_common_ring;
2102 2103 2104 2105 2106 2107 2108
	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) {
		ring->get_seqno = bxt_a_get_seqno;
		ring->set_seqno = bxt_a_set_seqno;
	} else {
		ring->get_seqno = gen8_get_seqno;
		ring->set_seqno = gen8_set_seqno;
	}
2109
	ring->emit_request = gen8_emit_request;
2110
	ring->emit_flush = gen8_emit_flush;
2111 2112
	ring->irq_get = gen8_logical_ring_get_irq;
	ring->irq_put = gen8_logical_ring_put_irq;
2113
	ring->emit_bb_start = gen8_emit_bb_start;
2114

2115 2116 2117
	return logical_ring_init(dev, ring);
}

2118 2119 2120 2121 2122 2123 2124 2125 2126 2127
/**
 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
 * @dev: DRM device.
 *
 * This function inits the engines for an Execlists submission style (the equivalent in the
 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
 * those engines that are present in the hardware.
 *
 * Return: non-zero if the initialization failed.
 */
2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174
int intel_logical_rings_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = logical_render_ring_init(dev);
	if (ret)
		return ret;

	if (HAS_BSD(dev)) {
		ret = logical_bsd_ring_init(dev);
		if (ret)
			goto cleanup_render_ring;
	}

	if (HAS_BLT(dev)) {
		ret = logical_blt_ring_init(dev);
		if (ret)
			goto cleanup_bsd_ring;
	}

	if (HAS_VEBOX(dev)) {
		ret = logical_vebox_ring_init(dev);
		if (ret)
			goto cleanup_blt_ring;
	}

	if (HAS_BSD2(dev)) {
		ret = logical_bsd2_ring_init(dev);
		if (ret)
			goto cleanup_vebox_ring;
	}

	return 0;

cleanup_vebox_ring:
	intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
cleanup_blt_ring:
	intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
cleanup_bsd_ring:
	intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
cleanup_render_ring:
	intel_logical_ring_cleanup(&dev_priv->ring[RCS]);

	return ret;
}

2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217
static u32
make_rpcs(struct drm_device *dev)
{
	u32 rpcs = 0;

	/*
	 * No explicit RPCS request is needed to ensure full
	 * slice/subslice/EU enablement prior to Gen9.
	*/
	if (INTEL_INFO(dev)->gen < 9)
		return 0;

	/*
	 * Starting in Gen9, render power gating can leave
	 * slice/subslice/EU in a partially enabled state. We
	 * must make an explicit request through RPCS for full
	 * enablement.
	*/
	if (INTEL_INFO(dev)->has_slice_pg) {
		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
		rpcs |= INTEL_INFO(dev)->slice_total <<
			GEN8_RPCS_S_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	if (INTEL_INFO(dev)->has_subslice_pg) {
		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
		rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
			GEN8_RPCS_SS_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	if (INTEL_INFO(dev)->has_eu_pg) {
		rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
			GEN8_RPCS_EU_MIN_SHIFT;
		rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
			GEN8_RPCS_EU_MAX_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	return rpcs;
}

2218 2219 2220 2221
static int
populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
		    struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
{
2222 2223
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2224
	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2225 2226 2227 2228
	struct page *page;
	uint32_t *reg_state;
	int ret;

2229 2230 2231
	if (!ppgtt)
		ppgtt = dev_priv->mm.aliasing_ppgtt;

2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247
	ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
	if (ret) {
		DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
		return ret;
	}

	ret = i915_gem_object_get_pages(ctx_obj);
	if (ret) {
		DRM_DEBUG_DRIVER("Could not get object pages\n");
		return ret;
	}

	i915_gem_object_pin_pages(ctx_obj);

	/* The second page of the context object contains some fields which must
	 * be set up prior to the first execution. */
2248
	page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262
	reg_state = kmap_atomic(page);

	/* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
	 * commands followed by (reg, value) pairs. The values we are setting here are
	 * only for the first context restore: on a subsequent save, the GPU will
	 * recreate this batchbuffer with new values (including all the missing
	 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
	if (ring->id == RCS)
		reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
	else
		reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
	reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
	reg_state[CTX_CONTEXT_CONTROL+1] =
2263
		_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2264 2265
				   CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
				   CTX_CTRL_RS_CTX_ENABLE);
2266 2267 2268 2269 2270
	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
	reg_state[CTX_RING_HEAD+1] = 0;
	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
	reg_state[CTX_RING_TAIL+1] = 0;
	reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
2271 2272 2273
	/* Ring buffer start address is not known until the buffer is pinned.
	 * It is written to the context image in execlists_update_context()
	 */
2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295
	reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
	reg_state[CTX_RING_BUFFER_CONTROL+1] =
			((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
	reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
	reg_state[CTX_BB_HEAD_U+1] = 0;
	reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
	reg_state[CTX_BB_HEAD_L+1] = 0;
	reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
	reg_state[CTX_BB_STATE+1] = (1<<5);
	reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
	reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
	reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
	reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
	reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
	reg_state[CTX_SECOND_BB_STATE+1] = 0;
	if (ring->id == RCS) {
		reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
		reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
		reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
		reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
		reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
		reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310
		if (ring->wa_ctx.obj) {
			struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
			uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);

			reg_state[CTX_RCS_INDIRECT_CTX+1] =
				(ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
				(wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);

			reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
				CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;

			reg_state[CTX_BB_PER_CTX_PTR+1] =
				(ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
				0x01;
		}
2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323
	}
	reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
	reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
	reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
	reg_state[CTX_CTX_TIMESTAMP+1] = 0;
	reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
	reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
	reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
	reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
	reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
	reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
	reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
	reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
2324

2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342
	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
		/* 64b PPGTT (48bit canonical)
		 * PDP0_DESCRIPTOR contains the base address to PML4 and
		 * other PDP Descriptors are ignored.
		 */
		ASSIGN_CTX_PML4(ppgtt, reg_state);
	} else {
		/* 32b PPGTT
		 * PDP*_DESCRIPTOR contains the base address of space supported.
		 * With dynamic page allocation, PDPs may not be allocated at
		 * this point. Point the unallocated PDPs to the scratch page
		 */
		ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
		ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
	}

2343 2344
	if (ring->id == RCS) {
		reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2345 2346
		reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
		reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357
	}

	kunmap_atomic(reg_state);

	ctx_obj->dirty = 1;
	set_page_dirty(page);
	i915_gem_object_unpin_pages(ctx_obj);

	return 0;
}

2358 2359 2360 2361 2362 2363 2364 2365
/**
 * intel_lr_context_free() - free the LRC specific bits of a context
 * @ctx: the LR context to free.
 *
 * The real context freeing is done in i915_gem_context_free: this only
 * takes care of the bits that are LRC related: the per-engine backing
 * objects and the logical ringbuffer.
 */
2366 2367
void intel_lr_context_free(struct intel_context *ctx)
{
2368 2369 2370 2371
	int i;

	for (i = 0; i < I915_NUM_RINGS; i++) {
		struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2372

2373
		if (ctx_obj) {
2374 2375 2376 2377
			struct intel_ringbuffer *ringbuf =
					ctx->engine[i].ringbuf;
			struct intel_engine_cs *ring = ringbuf->ring;

2378 2379 2380 2381
			if (ctx == ring->default_context) {
				intel_unpin_ringbuffer_obj(ringbuf);
				i915_gem_object_ggtt_unpin(ctx_obj);
			}
2382
			WARN_ON(ctx->engine[ring->id].pin_count);
2383
			intel_ringbuffer_free(ringbuf);
2384 2385 2386 2387 2388 2389 2390 2391 2392
			drm_gem_object_unreference(&ctx_obj->base);
		}
	}
}

static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
{
	int ret = 0;

2393
	WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
2394 2395 2396

	switch (ring->id) {
	case RCS:
2397 2398 2399 2400
		if (INTEL_INFO(ring->dev)->gen >= 9)
			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
		else
			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2401 2402 2403 2404 2405 2406 2407 2408 2409 2410
		break;
	case VCS:
	case BCS:
	case VECS:
	case VCS2:
		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
		break;
	}

	return ret;
2411 2412
}

2413
static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
2414 2415 2416
		struct drm_i915_gem_object *default_ctx_obj)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2417
	struct page *page;
2418

2419 2420 2421 2422 2423
	/* The HWSP is part of the default context object in LRC mode. */
	ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj)
			+ LRC_PPHWSP_PN * PAGE_SIZE;
	page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN);
	ring->status_page.page_addr = kmap(page);
2424 2425 2426 2427 2428 2429 2430
	ring->status_page.obj = default_ctx_obj;

	I915_WRITE(RING_HWS_PGA(ring->mmio_base),
			(u32)ring->status_page.gfx_addr);
	POSTING_READ(RING_HWS_PGA(ring->mmio_base));
}

2431
/**
2432
 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2433 2434 2435 2436 2437 2438 2439 2440 2441
 * @ctx: LR context to create.
 * @ring: engine to be used with the context.
 *
 * This function can be called more than once, with different engines, if we plan
 * to use the context with them. The context backing objects and the ringbuffers
 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
 * the creation is a deferred call: it's better to make sure first that we need to use
 * a given ring with the context.
 *
2442
 * Return: non-zero on error.
2443
 */
2444 2445

int intel_lr_context_deferred_alloc(struct intel_context *ctx,
2446 2447
				     struct intel_engine_cs *ring)
{
2448 2449 2450
	struct drm_device *dev = ring->dev;
	struct drm_i915_gem_object *ctx_obj;
	uint32_t context_size;
2451
	struct intel_ringbuffer *ringbuf;
2452 2453
	int ret;

2454
	WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2455
	WARN_ON(ctx->engine[ring->id].state);
2456

2457 2458
	context_size = round_up(get_lr_context_size(ring), 4096);

2459 2460 2461
	/* One extra page as the sharing data between driver and GuC */
	context_size += PAGE_SIZE * LRC_PPHWSP_PN;

2462
	ctx_obj = i915_gem_alloc_object(dev, context_size);
2463 2464 2465
	if (!ctx_obj) {
		DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
		return -ENOMEM;
2466 2467
	}

2468 2469 2470
	ringbuf = intel_engine_create_ringbuffer(ring, 4 * PAGE_SIZE);
	if (IS_ERR(ringbuf)) {
		ret = PTR_ERR(ringbuf);
2471
		goto error_deref_obj;
2472 2473 2474 2475 2476
	}

	ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2477
		goto error_ringbuf;
2478 2479 2480
	}

	ctx->engine[ring->id].ringbuf = ringbuf;
2481
	ctx->engine[ring->id].state = ctx_obj;
2482

2483 2484
	if (ctx != ring->default_context && ring->init_context) {
		struct drm_i915_gem_request *req;
2485

2486 2487 2488 2489 2490 2491 2492
		ret = i915_gem_request_alloc(ring,
			ctx, &req);
		if (ret) {
			DRM_ERROR("ring create req: %d\n",
				ret);
			i915_gem_request_cancel(req);
			goto error_ringbuf;
2493 2494
		}

2495 2496 2497 2498 2499 2500 2501 2502
		ret = ring->init_context(req);
		if (ret) {
			DRM_ERROR("ring init context: %d\n",
				ret);
			i915_gem_request_cancel(req);
			goto error_ringbuf;
		}
		i915_add_request_no_flush(req);
2503
	}
2504
	return 0;
2505

2506 2507
error_ringbuf:
	intel_ringbuffer_free(ringbuf);
2508
error_deref_obj:
2509
	drm_gem_object_unreference(&ctx_obj->base);
2510 2511
	ctx->engine[ring->id].ringbuf = NULL;
	ctx->engine[ring->id].state = NULL;
2512
	return ret;
2513
}
2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536

void intel_lr_context_reset(struct drm_device *dev,
			struct intel_context *ctx)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_engine_cs *ring;
	int i;

	for_each_ring(ring, dev_priv, i) {
		struct drm_i915_gem_object *ctx_obj =
				ctx->engine[ring->id].state;
		struct intel_ringbuffer *ringbuf =
				ctx->engine[ring->id].ringbuf;
		uint32_t *reg_state;
		struct page *page;

		if (!ctx_obj)
			continue;

		if (i915_gem_object_get_pages(ctx_obj)) {
			WARN(1, "Failed get_pages for context obj\n");
			continue;
		}
2537
		page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548
		reg_state = kmap_atomic(page);

		reg_state[CTX_RING_HEAD+1] = 0;
		reg_state[CTX_RING_TAIL+1] = 0;

		kunmap_atomic(reg_state);

		ringbuf->head = 0;
		ringbuf->tail = 0;
	}
}