emulate.c 131.5 KB
Newer Older
A
Avi Kivity 已提交
1
/******************************************************************************
2
 * emulate.c
A
Avi Kivity 已提交
3 4 5 6 7 8
 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
 * Copyright (c) 2005 Keir Fraser
 *
 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9
 * privileged instructions:
A
Avi Kivity 已提交
10 11
 *
 * Copyright (C) 2006 Qumranet
N
Nicolas Kaiser 已提交
12
 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
A
Avi Kivity 已提交
13 14 15 16 17 18 19 20 21 22
 *
 *   Avi Kivity <avi@qumranet.com>
 *   Yaniv Kamay <yaniv@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
 */

23
#include <linux/kvm_host.h>
24
#include "kvm_cache_regs.h"
A
Avi Kivity 已提交
25
#include <linux/module.h>
26
#include <asm/kvm_emulate.h>
27
#include <linux/stringify.h>
A
Avi Kivity 已提交
28

29
#include "x86.h"
30
#include "tss.h"
31

32 33 34
/*
 * Operand types
 */
35 36 37 38 39 40 41 42 43
#define OpNone             0ull
#define OpImplicit         1ull  /* No generic decode */
#define OpReg              2ull  /* Register */
#define OpMem              3ull  /* Memory */
#define OpAcc              4ull  /* Accumulator: AL/AX/EAX/RAX */
#define OpDI               5ull  /* ES:DI/EDI/RDI */
#define OpMem64            6ull  /* Memory, 64-bit */
#define OpImmUByte         7ull  /* Zero-extended 8-bit immediate */
#define OpDX               8ull  /* DX register */
44 45 46
#define OpCL               9ull  /* CL register (for shifts) */
#define OpImmByte         10ull  /* 8-bit sign extended immediate */
#define OpOne             11ull  /* Implied 1 */
47
#define OpImm             12ull  /* Sign extended up to 32-bit immediate */
48 49 50 51 52 53 54
#define OpMem16           13ull  /* Memory operand (16-bit). */
#define OpMem32           14ull  /* Memory operand (32-bit). */
#define OpImmU            15ull  /* Immediate operand, zero extended */
#define OpSI              16ull  /* SI/ESI/RSI */
#define OpImmFAddr        17ull  /* Immediate far address */
#define OpMemFAddr        18ull  /* Far address in memory */
#define OpImmU16          19ull  /* Immediate operand, 16 bits, zero extended */
55 56 57 58 59 60
#define OpES              20ull  /* ES */
#define OpCS              21ull  /* CS */
#define OpSS              22ull  /* SS */
#define OpDS              23ull  /* DS */
#define OpFS              24ull  /* FS */
#define OpGS              25ull  /* GS */
61
#define OpMem8            26ull  /* 8-bit zero extended memory operand */
62
#define OpImm64           27ull  /* Sign extended 16/32/64-bit immediate */
P
Paolo Bonzini 已提交
63
#define OpXLat            28ull  /* memory at BX/EBX/RBX + zero-extended AL */
64 65
#define OpAccLo           29ull  /* Low part of extended acc (AX/AX/EAX/RAX) */
#define OpAccHi           30ull  /* High part of extended acc (-/DX/EDX/RDX) */
66 67

#define OpBits             5  /* Width of operand field */
68
#define OpMask             ((1ull << OpBits) - 1)
69

A
Avi Kivity 已提交
70 71 72 73 74 75 76 77 78 79
/*
 * Opcode effective-address decode tables.
 * Note that we only emulate instructions that have at least one memory
 * operand (excluding implicit stack references). We assume that stack
 * references and instruction fetches will never occur in special memory
 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
 * not be handled.
 */

/* Operand sizes: 8-bit operands or specified/overridden size. */
80
#define ByteOp      (1<<0)	/* 8-bit operands. */
A
Avi Kivity 已提交
81
/* Destination operand type. */
82 83 84 85 86 87 88
#define DstShift    1
#define ImplicitOps (OpImplicit << DstShift)
#define DstReg      (OpReg << DstShift)
#define DstMem      (OpMem << DstShift)
#define DstAcc      (OpAcc << DstShift)
#define DstDI       (OpDI << DstShift)
#define DstMem64    (OpMem64 << DstShift)
89
#define DstMem16    (OpMem16 << DstShift)
90 91
#define DstImmUByte (OpImmUByte << DstShift)
#define DstDX       (OpDX << DstShift)
92
#define DstAccLo    (OpAccLo << DstShift)
93
#define DstMask     (OpMask << DstShift)
A
Avi Kivity 已提交
94
/* Source operand type. */
95 96 97 98 99 100 101 102 103 104 105 106
#define SrcShift    6
#define SrcNone     (OpNone << SrcShift)
#define SrcReg      (OpReg << SrcShift)
#define SrcMem      (OpMem << SrcShift)
#define SrcMem16    (OpMem16 << SrcShift)
#define SrcMem32    (OpMem32 << SrcShift)
#define SrcImm      (OpImm << SrcShift)
#define SrcImmByte  (OpImmByte << SrcShift)
#define SrcOne      (OpOne << SrcShift)
#define SrcImmUByte (OpImmUByte << SrcShift)
#define SrcImmU     (OpImmU << SrcShift)
#define SrcSI       (OpSI << SrcShift)
P
Paolo Bonzini 已提交
107
#define SrcXLat     (OpXLat << SrcShift)
108 109 110 111
#define SrcImmFAddr (OpImmFAddr << SrcShift)
#define SrcMemFAddr (OpMemFAddr << SrcShift)
#define SrcAcc      (OpAcc << SrcShift)
#define SrcImmU16   (OpImmU16 << SrcShift)
112
#define SrcImm64    (OpImm64 << SrcShift)
113
#define SrcDX       (OpDX << SrcShift)
114
#define SrcMem8     (OpMem8 << SrcShift)
115
#define SrcAccHi    (OpAccHi << SrcShift)
116
#define SrcMask     (OpMask << SrcShift)
117 118 119 120 121 122 123 124 125
#define BitOp       (1<<11)
#define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
#define String      (1<<13)     /* String instruction (rep capable) */
#define Stack       (1<<14)     /* Stack instruction (push/pop) */
#define GroupMask   (7<<15)     /* Opcode uses one of the group mechanisms */
#define Group       (1<<15)     /* Bits 3:5 of modrm byte extend opcode */
#define GroupDual   (2<<15)     /* Alternate decoding of mod == 3 */
#define Prefix      (3<<15)     /* Instruction varies with 66/f2/f3 prefix */
#define RMExt       (4<<15)     /* Opcode extension in ModRM r/m if mod == 3 */
126
#define Escape      (5<<15)     /* Escape to coprocessor instruction */
127
#define InstrDual   (6<<15)     /* Alternate instruction decoding of mod == 3 */
128
#define Sse         (1<<18)     /* SSE Vector instruction */
129 130 131 132
/* Generic ModRM decode. */
#define ModRM       (1<<19)
/* Destination is only written; never read. */
#define Mov         (1<<20)
133
/* Misc flags */
134
#define Prot        (1<<21) /* instruction generates #UD if not in prot-mode */
135
#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
136
#define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
137
#define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
138
#define Undefined   (1<<25) /* No Such Instruction */
139
#define Lock        (1<<26) /* lock prefix is allowed for the instruction */
140
#define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
141
#define No64	    (1<<28)
142
#define PageTable   (1 << 29)   /* instruction used to write page table */
143
#define NotImpl     (1 << 30)   /* instruction is not implemented */
144
/* Source 2 operand type */
145
#define Src2Shift   (31)
146
#define Src2None    (OpNone << Src2Shift)
147
#define Src2Mem     (OpMem << Src2Shift)
148 149 150 151
#define Src2CL      (OpCL << Src2Shift)
#define Src2ImmByte (OpImmByte << Src2Shift)
#define Src2One     (OpOne << Src2Shift)
#define Src2Imm     (OpImm << Src2Shift)
152 153 154 155 156 157
#define Src2ES      (OpES << Src2Shift)
#define Src2CS      (OpCS << Src2Shift)
#define Src2SS      (OpSS << Src2Shift)
#define Src2DS      (OpDS << Src2Shift)
#define Src2FS      (OpFS << Src2Shift)
#define Src2GS      (OpGS << Src2Shift)
158
#define Src2Mask    (OpMask << Src2Shift)
A
Avi Kivity 已提交
159
#define Mmx         ((u64)1 << 40)  /* MMX Vector instruction */
160 161 162
#define Aligned     ((u64)1 << 41)  /* Explicitly aligned (e.g. MOVDQA) */
#define Unaligned   ((u64)1 << 42)  /* Explicitly unaligned (e.g. MOVDQU) */
#define Avx         ((u64)1 << 43)  /* Advanced Vector Extensions */
163
#define Fastop      ((u64)1 << 44)  /* Use opcode::u.fastop */
164
#define NoWrite     ((u64)1 << 45)  /* No writeback */
165
#define SrcWrite    ((u64)1 << 46)  /* Write back src operand */
166
#define NoMod	    ((u64)1 << 47)  /* Mod field is ignored */
167 168
#define Intercept   ((u64)1 << 48)  /* Has valid intercept field */
#define CheckPerm   ((u64)1 << 49)  /* Has valid check_perm field */
169
#define NoBigReal   ((u64)1 << 50)  /* No big real mode */
170
#define PrivUD      ((u64)1 << 51)  /* #UD instead of #GP on CPL > 0 */
171
#define NearBranch  ((u64)1 << 52)  /* Near branches */
172
#define No16	    ((u64)1 << 53)  /* No 16 bit operand */
173
#define IncSP       ((u64)1 << 54)  /* SP is incremented before ModRM calc */
A
Avi Kivity 已提交
174

175
#define DstXacc     (DstAccLo | SrcAccHi | SrcWrite)
A
Avi Kivity 已提交
176

177 178 179 180 181 182 183 184
#define X2(x...) x, x
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X5(x...) X4(x), x
#define X6(x...) X4(x), X2(x)
#define X7(x...) X4(x), X3(x)
#define X8(x...) X4(x), X4(x)
#define X16(x...) X8(x), X8(x)
185

186 187 188 189 190 191
#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
#define FASTOP_SIZE 8

/*
 * fastop functions have a special calling convention:
 *
192 193
 * dst:    rax        (in/out)
 * src:    rdx        (in/out)
194 195
 * src2:   rcx        (in)
 * flags:  rflags     (in/out)
196
 * ex:     rsi        (in:fastop pointer, out:zero if exception)
197 198 199 200 201 202 203 204 205 206 207
 *
 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
 * different operand sizes can be reached by calculation, rather than a jump
 * table (which would be bigger than the code).
 *
 * fastop functions are declared as taking a never-defined fastop parameter,
 * so they can't be called from C directly.
 */

struct fastop;

208
struct opcode {
209 210
	u64 flags : 56;
	u64 intercept : 8;
211
	union {
212
		int (*execute)(struct x86_emulate_ctxt *ctxt);
213 214 215
		const struct opcode *group;
		const struct group_dual *gdual;
		const struct gprefix *gprefix;
216
		const struct escape *esc;
217
		const struct instr_dual *idual;
218
		void (*fastop)(struct fastop *fake);
219
	} u;
220
	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
221 222 223 224 225
};

struct group_dual {
	struct opcode mod012[8];
	struct opcode mod3[8];
226 227
};

228 229 230 231 232 233 234
struct gprefix {
	struct opcode pfx_no;
	struct opcode pfx_66;
	struct opcode pfx_f2;
	struct opcode pfx_f3;
};

235 236 237 238 239
struct escape {
	struct opcode op[8];
	struct opcode high[64];
};

240 241 242 243 244
struct instr_dual {
	struct opcode mod012;
	struct opcode mod3;
};

A
Avi Kivity 已提交
245
/* EFLAGS bit definitions. */
246 247 248 249
#define EFLG_ID (1<<21)
#define EFLG_VIP (1<<20)
#define EFLG_VIF (1<<19)
#define EFLG_AC (1<<18)
250 251
#define EFLG_VM (1<<17)
#define EFLG_RF (1<<16)
252 253
#define EFLG_IOPL (3<<12)
#define EFLG_NT (1<<14)
A
Avi Kivity 已提交
254 255
#define EFLG_OF (1<<11)
#define EFLG_DF (1<<10)
256
#define EFLG_IF (1<<9)
257
#define EFLG_TF (1<<8)
A
Avi Kivity 已提交
258 259 260 261 262 263
#define EFLG_SF (1<<7)
#define EFLG_ZF (1<<6)
#define EFLG_AF (1<<4)
#define EFLG_PF (1<<2)
#define EFLG_CF (1<<0)

264 265 266
#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
#define EFLG_RESERVED_ONE_MASK 2

267 268 269 270 271 272 273
enum x86_transfer_type {
	X86_TRANSFER_NONE,
	X86_TRANSFER_CALL_JMP,
	X86_TRANSFER_RET,
	X86_TRANSFER_TASK_SWITCH,
};

274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309
static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	if (!(ctxt->regs_valid & (1 << nr))) {
		ctxt->regs_valid |= 1 << nr;
		ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
	}
	return ctxt->_regs[nr];
}

static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	ctxt->regs_valid |= 1 << nr;
	ctxt->regs_dirty |= 1 << nr;
	return &ctxt->_regs[nr];
}

static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	reg_read(ctxt, nr);
	return reg_write(ctxt, nr);
}

static void writeback_registers(struct x86_emulate_ctxt *ctxt)
{
	unsigned reg;

	for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
		ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
}

static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
{
	ctxt->regs_dirty = 0;
	ctxt->regs_valid = 0;
}

A
Avi Kivity 已提交
310 311 312 313 314 315
/*
 * These EFLAGS bits are restored from saved value during emulation, and
 * any changes are written back to the saved value after emulation.
 */
#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)

316 317 318 319 320 321
#ifdef CONFIG_X86_64
#define ON64(x) x
#else
#define ON64(x)
#endif

322 323
static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));

324 325 326 327 328 329 330 331 332 333 334 335 336
#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
#define FOP_RET   "ret \n\t"

#define FOP_START(op) \
	extern void em_##op(struct fastop *fake); \
	asm(".pushsection .text, \"ax\" \n\t" \
	    ".global em_" #op " \n\t" \
            FOP_ALIGN \
	    "em_" #op ": \n\t"

#define FOP_END \
	    ".popsection")

337 338
#define FOPNOP() FOP_ALIGN FOP_RET

339
#define FOP1E(op,  dst) \
340 341 342 343
	FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET

#define FOP1EEX(op,  dst) \
	FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
344 345 346 347 348 349 350 351 352

#define FASTOP1(op) \
	FOP_START(op) \
	FOP1E(op##b, al) \
	FOP1E(op##w, ax) \
	FOP1E(op##l, eax) \
	ON64(FOP1E(op##q, rax))	\
	FOP_END

353 354 355 356 357 358 359 360 361
/* 1-operand, using src2 (for MUL/DIV r/m) */
#define FASTOP1SRC2(op, name) \
	FOP_START(name) \
	FOP1E(op, cl) \
	FOP1E(op, cx) \
	FOP1E(op, ecx) \
	ON64(FOP1E(op, rcx)) \
	FOP_END

362 363 364 365 366 367 368 369 370
/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
#define FASTOP1SRC2EX(op, name) \
	FOP_START(name) \
	FOP1EEX(op, cl) \
	FOP1EEX(op, cx) \
	FOP1EEX(op, ecx) \
	ON64(FOP1EEX(op, rcx)) \
	FOP_END

371 372 373 374 375
#define FOP2E(op,  dst, src)	   \
	FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET

#define FASTOP2(op) \
	FOP_START(op) \
376 377 378 379
	FOP2E(op##b, al, dl) \
	FOP2E(op##w, ax, dx) \
	FOP2E(op##l, eax, edx) \
	ON64(FOP2E(op##q, rax, rdx)) \
380 381
	FOP_END

382 383 384 385
/* 2 operand, word only */
#define FASTOP2W(op) \
	FOP_START(op) \
	FOPNOP() \
386 387 388
	FOP2E(op##w, ax, dx) \
	FOP2E(op##l, eax, edx) \
	ON64(FOP2E(op##q, rax, rdx)) \
389 390
	FOP_END

391 392 393 394 395 396 397 398 399
/* 2 operand, src is CL */
#define FASTOP2CL(op) \
	FOP_START(op) \
	FOP2E(op##b, al, cl) \
	FOP2E(op##w, ax, cl) \
	FOP2E(op##l, eax, cl) \
	ON64(FOP2E(op##q, rax, cl)) \
	FOP_END

400 401 402 403 404 405 406 407 408
/* 2 operand, src and dest are reversed */
#define FASTOP2R(op, name) \
	FOP_START(name) \
	FOP2E(op##b, dl, al) \
	FOP2E(op##w, dx, ax) \
	FOP2E(op##l, edx, eax) \
	ON64(FOP2E(op##q, rdx, rax)) \
	FOP_END

409 410 411 412 413 414 415
#define FOP3E(op,  dst, src, src2) \
	FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET

/* 3-operand, word-only, src2=cl */
#define FASTOP3WCL(op) \
	FOP_START(op) \
	FOPNOP() \
416 417 418
	FOP3E(op##w, ax, dx, cl) \
	FOP3E(op##l, eax, edx, cl) \
	ON64(FOP3E(op##q, rax, rdx, cl)) \
419 420
	FOP_END

421 422 423
/* Special case for SETcc - 1 instruction per cc */
#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"

424 425 426
asm(".global kvm_fastop_exception \n"
    "kvm_fastop_exception: xor %esi, %esi; ret");

427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445
FOP_START(setcc)
FOP_SETCC(seto)
FOP_SETCC(setno)
FOP_SETCC(setc)
FOP_SETCC(setnc)
FOP_SETCC(setz)
FOP_SETCC(setnz)
FOP_SETCC(setbe)
FOP_SETCC(setnbe)
FOP_SETCC(sets)
FOP_SETCC(setns)
FOP_SETCC(setp)
FOP_SETCC(setnp)
FOP_SETCC(setl)
FOP_SETCC(setnl)
FOP_SETCC(setle)
FOP_SETCC(setnle)
FOP_END;

P
Paolo Bonzini 已提交
446 447 448
FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
FOP_END;

449 450 451 452 453 454
static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
				    enum x86_intercept intercept,
				    enum x86_intercept_stage stage)
{
	struct x86_instruction_info info = {
		.intercept  = intercept,
455 456 457 458 459
		.rep_prefix = ctxt->rep_prefix,
		.modrm_mod  = ctxt->modrm_mod,
		.modrm_reg  = ctxt->modrm_reg,
		.modrm_rm   = ctxt->modrm_rm,
		.src_val    = ctxt->src.val64,
460
		.dst_val    = ctxt->dst.val64,
461 462 463
		.src_bytes  = ctxt->src.bytes,
		.dst_bytes  = ctxt->dst.bytes,
		.ad_bytes   = ctxt->ad_bytes,
464 465 466
		.next_rip   = ctxt->eip,
	};

467
	return ctxt->ops->intercept(ctxt, &info, stage);
468 469
}

A
Avi Kivity 已提交
470 471 472 473 474
static void assign_masked(ulong *dest, ulong src, ulong mask)
{
	*dest = (*dest & ~mask) | (src & mask);
}

475
static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
476
{
477
	return (1UL << (ctxt->ad_bytes << 3)) - 1;
478 479
}

A
Avi Kivity 已提交
480 481 482 483 484 485 486 487 488 489 490
static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
{
	u16 sel;
	struct desc_struct ss;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return ~0UL;
	ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
	return ~0U >> ((ss.d ^ 1) * 16);  /* d=0: 0xffff; d=1: 0xffffffff */
}

A
Avi Kivity 已提交
491 492 493 494 495
static int stack_size(struct x86_emulate_ctxt *ctxt)
{
	return (__fls(stack_mask(ctxt)) + 1) >> 3;
}

A
Avi Kivity 已提交
496
/* Access/update address held in a register, based on addressing mode. */
497
static inline unsigned long
498
address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
499
{
500
	if (ctxt->ad_bytes == sizeof(unsigned long))
501 502
		return reg;
	else
503
		return reg & ad_mask(ctxt);
504 505 506
}

static inline unsigned long
507
register_address(struct x86_emulate_ctxt *ctxt, int reg)
508
{
509
	return address_mask(ctxt, reg_read(ctxt, reg));
510 511
}

512 513 514 515 516
static void masked_increment(ulong *reg, ulong mask, int inc)
{
	assign_masked(reg, *reg + inc, mask);
}

517
static inline void
518
register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
519
{
520 521
	ulong mask;

522
	if (ctxt->ad_bytes == sizeof(unsigned long))
523
		mask = ~0UL;
524
	else
525
		mask = ad_mask(ctxt);
526
	masked_increment(reg_rmw(ctxt, reg), mask, inc);
527 528 529 530
}

static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
{
531
	masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
532
}
A
Avi Kivity 已提交
533

534 535 536 537 538 539 540
static u32 desc_limit_scaled(struct desc_struct *desc)
{
	u32 limit = get_desc_limit(desc);

	return desc->g ? (limit << 12) | 0xfff : limit;
}

541
static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
542 543 544 545
{
	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
		return 0;

546
	return ctxt->ops->get_cached_segment_base(ctxt, seg);
547 548
}

549 550
static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
			     u32 error, bool valid)
551
{
552
	WARN_ON(vec > 0x1f);
553 554 555
	ctxt->exception.vector = vec;
	ctxt->exception.error_code = error;
	ctxt->exception.error_code_valid = valid;
556
	return X86EMUL_PROPAGATE_FAULT;
557 558
}

559 560 561 562 563
static int emulate_db(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, DB_VECTOR, 0, false);
}

564
static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
565
{
566
	return emulate_exception(ctxt, GP_VECTOR, err, true);
567 568
}

569 570 571 572 573
static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
{
	return emulate_exception(ctxt, SS_VECTOR, err, true);
}

574
static int emulate_ud(struct x86_emulate_ctxt *ctxt)
575
{
576
	return emulate_exception(ctxt, UD_VECTOR, 0, false);
577 578
}

579
static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
580
{
581
	return emulate_exception(ctxt, TS_VECTOR, err, true);
582 583
}

584 585
static int emulate_de(struct x86_emulate_ctxt *ctxt)
{
586
	return emulate_exception(ctxt, DE_VECTOR, 0, false);
587 588
}

A
Avi Kivity 已提交
589 590 591 592 593
static int emulate_nm(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, NM_VECTOR, 0, false);
}

594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613
static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
{
	u16 selector;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
	return selector;
}

static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
				 unsigned seg)
{
	u16 dummy;
	u32 base3;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
}

614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636
/*
 * x86 defines three classes of vector instructions: explicitly
 * aligned, explicitly unaligned, and the rest, which change behaviour
 * depending on whether they're AVX encoded or not.
 *
 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
 * subject to the same check.
 */
static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
{
	if (likely(size < 16))
		return false;

	if (ctxt->d & Aligned)
		return true;
	else if (ctxt->d & Unaligned)
		return false;
	else if (ctxt->d & Avx)
		return false;
	else
		return true;
}

637 638 639 640
static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
				       struct segmented_address addr,
				       unsigned *max_size, unsigned size,
				       bool write, bool fetch,
641
				       enum x86emul_mode mode, ulong *linear)
642
{
643 644
	struct desc_struct desc;
	bool usable;
645
	ulong la;
646
	u32 lim;
647
	u16 sel;
648

649
	la = seg_base(ctxt, addr.seg) + addr.ea;
650
	*max_size = 0;
651
	switch (mode) {
652
	case X86EMUL_MODE_PROT64:
653
		if (is_noncanonical_address(la))
654
			goto bad;
655 656 657 658

		*max_size = min_t(u64, ~0u, (1ull << 48) - la);
		if (size > *max_size)
			goto bad;
659 660
		break;
	default:
661 662
		usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
						addr.seg);
663 664
		if (!usable)
			goto bad;
665 666 667
		/* code segment in protected mode or read-only data segment */
		if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
					|| !(desc.type & 2)) && write)
668 669
			goto bad;
		/* unreadable code segment */
670
		if (!fetch && (desc.type & 8) && !(desc.type & 2))
671 672
			goto bad;
		lim = desc_limit_scaled(&desc);
673
		if (!(desc.type & 8) && (desc.type & 4)) {
G
Guo Chao 已提交
674
			/* expand-down segment */
675
			if (addr.ea <= lim)
676 677 678
				goto bad;
			lim = desc.d ? 0xffffffff : 0xffff;
		}
679 680 681
		if (addr.ea > lim)
			goto bad;
		*max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
682 683
		if (size > *max_size)
			goto bad;
684
		la &= (u32)-1;
685 686
		break;
	}
687 688
	if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
		return emulate_gp(ctxt, 0);
689 690
	*linear = la;
	return X86EMUL_CONTINUE;
691 692
bad:
	if (addr.seg == VCPU_SREG_SS)
693
		return emulate_ss(ctxt, 0);
694
	else
695
		return emulate_gp(ctxt, 0);
696 697
}

698 699 700 701 702
static int linearize(struct x86_emulate_ctxt *ctxt,
		     struct segmented_address addr,
		     unsigned size, bool write,
		     ulong *linear)
{
703
	unsigned max_size;
704 705
	return __linearize(ctxt, addr, &max_size, size, write, false,
			   ctxt->mode, linear);
706 707
}

708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727
static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
			     enum x86emul_mode mode)
{
	ulong linear;
	int rc;
	unsigned max_size;
	struct segmented_address addr = { .seg = VCPU_SREG_CS,
					   .ea = dst };

	if (ctxt->op_bytes != sizeof(unsigned long))
		addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
	rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
	if (rc == X86EMUL_CONTINUE)
		ctxt->_eip = addr.ea;
	return rc;
}

static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
{
	return assign_eip(ctxt, dst, ctxt->mode);
728 729
}

730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752
static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
			  const struct desc_struct *cs_desc)
{
	enum x86emul_mode mode = ctxt->mode;

#ifdef CONFIG_X86_64
	if (ctxt->mode >= X86EMUL_MODE_PROT32 && cs_desc->l) {
		u64 efer = 0;

		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (efer & EFER_LMA)
			mode = X86EMUL_MODE_PROT64;
	}
#endif
	if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
		mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
	return assign_eip(ctxt, dst, mode);
}

static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
{
	return assign_eip_near(ctxt, ctxt->_eip + rel);
}
753

754 755 756 757 758
static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
			      struct segmented_address addr,
			      void *data,
			      unsigned size)
{
759 760 761
	int rc;
	ulong linear;

762
	rc = linearize(ctxt, addr, size, false, &linear);
763 764
	if (rc != X86EMUL_CONTINUE)
		return rc;
765
	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
766 767
}

768
/*
769
 * Prefetch the remaining bytes of the instruction without crossing page
770 771
 * boundary if they are not in fetch_cache yet.
 */
772
static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
773 774
{
	int rc;
775
	unsigned size, max_size;
776
	unsigned long linear;
777
	int cur_size = ctxt->fetch.end - ctxt->fetch.data;
778
	struct segmented_address addr = { .seg = VCPU_SREG_CS,
779 780
					   .ea = ctxt->eip + cur_size };

781 782 783 784 785 786 787 788 789 790
	/*
	 * We do not know exactly how many bytes will be needed, and
	 * __linearize is expensive, so fetch as much as possible.  We
	 * just have to avoid going beyond the 15 byte limit, the end
	 * of the segment, or the end of the page.
	 *
	 * __linearize is called with size 0 so that it does not do any
	 * boundary check itself.  Instead, we use max_size to check
	 * against op_size.
	 */
791 792
	rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
			 &linear);
793 794 795
	if (unlikely(rc != X86EMUL_CONTINUE))
		return rc;

796
	size = min_t(unsigned, 15UL ^ cur_size, max_size);
797
	size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
798 799 800 801 802 803 804 805

	/*
	 * One instruction can only straddle two pages,
	 * and one has been loaded at the beginning of
	 * x86_decode_insn.  So, if not enough bytes
	 * still, we must have hit the 15-byte boundary.
	 */
	if (unlikely(size < op_size))
806 807
		return emulate_gp(ctxt, 0);

808
	rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
809 810 811
			      size, &ctxt->exception);
	if (unlikely(rc != X86EMUL_CONTINUE))
		return rc;
812
	ctxt->fetch.end += size;
813
	return X86EMUL_CONTINUE;
814 815
}

816 817
static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
					       unsigned size)
818
{
819 820 821 822
	unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;

	if (unlikely(done_size < size))
		return __do_insn_fetch_bytes(ctxt, size - done_size);
823 824
	else
		return X86EMUL_CONTINUE;
825 826
}

827
/* Fetch next part of the instruction being emulated. */
828
#define insn_fetch(_type, _ctxt)					\
829 830 831
({	_type _x;							\
									\
	rc = do_insn_fetch_bytes(_ctxt, sizeof(_type));			\
832 833
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
834
	ctxt->_eip += sizeof(_type);					\
835 836
	_x = *(_type __aligned(1) *) ctxt->fetch.ptr;			\
	ctxt->fetch.ptr += sizeof(_type);				\
837
	_x;								\
838 839
})

840
#define insn_fetch_arr(_arr, _size, _ctxt)				\
841 842
({									\
	rc = do_insn_fetch_bytes(_ctxt, _size);				\
843 844
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
845
	ctxt->_eip += (_size);						\
846 847
	memcpy(_arr, ctxt->fetch.ptr, _size);				\
	ctxt->fetch.ptr += (_size);					\
848 849
})

850 851 852 853 854
/*
 * Given the 'reg' portion of a ModRM byte, and a register block, return a
 * pointer into the block that addresses the relevant register.
 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 */
855
static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
856
			     int byteop)
A
Avi Kivity 已提交
857 858
{
	void *p;
859
	int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
A
Avi Kivity 已提交
860 861

	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
862 863 864
		p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
	else
		p = reg_rmw(ctxt, modrm_reg);
A
Avi Kivity 已提交
865 866 867 868
	return p;
}

static int read_descriptor(struct x86_emulate_ctxt *ctxt,
869
			   struct segmented_address addr,
A
Avi Kivity 已提交
870 871 872 873 874 875 876
			   u16 *size, unsigned long *address, int op_bytes)
{
	int rc;

	if (op_bytes == 2)
		op_bytes = 3;
	*address = 0;
877
	rc = segmented_read_std(ctxt, addr, size, 2);
878
	if (rc != X86EMUL_CONTINUE)
A
Avi Kivity 已提交
879
		return rc;
880
	addr.ea += 2;
881
	rc = segmented_read_std(ctxt, addr, address, op_bytes);
A
Avi Kivity 已提交
882 883 884
	return rc;
}

885 886 887 888 889 890 891 892 893 894
FASTOP2(add);
FASTOP2(or);
FASTOP2(adc);
FASTOP2(sbb);
FASTOP2(and);
FASTOP2(sub);
FASTOP2(xor);
FASTOP2(cmp);
FASTOP2(test);

895 896
FASTOP1SRC2(mul, mul_ex);
FASTOP1SRC2(imul, imul_ex);
897 898
FASTOP1SRC2EX(div, div_ex);
FASTOP1SRC2EX(idiv, idiv_ex);
899

900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924
FASTOP3WCL(shld);
FASTOP3WCL(shrd);

FASTOP2W(imul);

FASTOP1(not);
FASTOP1(neg);
FASTOP1(inc);
FASTOP1(dec);

FASTOP2CL(rol);
FASTOP2CL(ror);
FASTOP2CL(rcl);
FASTOP2CL(rcr);
FASTOP2CL(shl);
FASTOP2CL(shr);
FASTOP2CL(sar);

FASTOP2W(bsf);
FASTOP2W(bsr);
FASTOP2W(bt);
FASTOP2W(bts);
FASTOP2W(btr);
FASTOP2W(btc);

925 926
FASTOP2(xadd);

927 928
FASTOP2R(cmp, cmp_r);

929
static u8 test_cc(unsigned int condition, unsigned long flags)
930
{
931 932
	u8 rc;
	void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
933

934
	flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
935
	asm("push %[flags]; popf; call *%[fastop]"
936 937
	    : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
	return rc;
938 939
}

940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957
static void fetch_register_operand(struct operand *op)
{
	switch (op->bytes) {
	case 1:
		op->val = *(u8 *)op->addr.reg;
		break;
	case 2:
		op->val = *(u16 *)op->addr.reg;
		break;
	case 4:
		op->val = *(u32 *)op->addr.reg;
		break;
	case 8:
		op->val = *(u64 *)op->addr.reg;
		break;
	}
}

A
Avi Kivity 已提交
958 959 960 961
static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
962 963 964 965 966 967 968 969
	case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
	case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
	case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
	case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
	case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
	case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
	case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
	case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
A
Avi Kivity 已提交
970
#ifdef CONFIG_X86_64
971 972 973 974 975 976 977 978
	case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
	case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
	case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
	case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
	case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
	case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
	case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
	case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
A
Avi Kivity 已提交
979 980 981 982 983 984 985 986 987 988 989
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
			  int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
990 991 992 993 994 995 996 997
	case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
	case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
	case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
	case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
	case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
	case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
	case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
	case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
A
Avi Kivity 已提交
998
#ifdef CONFIG_X86_64
999 1000 1001 1002 1003 1004 1005 1006
	case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
	case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
	case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
	case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
	case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
	case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
	case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
	case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
A
Avi Kivity 已提交
1007 1008 1009 1010 1011 1012
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

A
Avi Kivity 已提交
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046
static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
	case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
	case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
	case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
	case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
	case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
	case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
	case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
	case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
	case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
	case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
	case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
	case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
	case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
	case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089
static int em_fninit(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	ctxt->ops->get_fpu(ctxt);
	asm volatile("fninit");
	ctxt->ops->put_fpu(ctxt);
	return X86EMUL_CONTINUE;
}

static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
{
	u16 fcw;

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	ctxt->ops->get_fpu(ctxt);
	asm volatile("fnstcw %0": "+m"(fcw));
	ctxt->ops->put_fpu(ctxt);

	ctxt->dst.val = fcw;

	return X86EMUL_CONTINUE;
}

static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
{
	u16 fsw;

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	ctxt->ops->get_fpu(ctxt);
	asm volatile("fnstsw %0": "+m"(fsw));
	ctxt->ops->put_fpu(ctxt);

	ctxt->dst.val = fsw;

	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
1090
static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1091
				    struct operand *op)
1092
{
1093
	unsigned reg = ctxt->modrm_reg;
1094

1095 1096
	if (!(ctxt->d & ModRM))
		reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
A
Avi Kivity 已提交
1097

1098
	if (ctxt->d & Sse) {
A
Avi Kivity 已提交
1099 1100 1101 1102 1103 1104
		op->type = OP_XMM;
		op->bytes = 16;
		op->addr.xmm = reg;
		read_sse_reg(ctxt, &op->vec_val, reg);
		return;
	}
A
Avi Kivity 已提交
1105 1106 1107 1108 1109 1110 1111
	if (ctxt->d & Mmx) {
		reg &= 7;
		op->type = OP_MM;
		op->bytes = 8;
		op->addr.mm = reg;
		return;
	}
A
Avi Kivity 已提交
1112

1113
	op->type = OP_REG;
1114 1115 1116
	op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
	op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);

1117
	fetch_register_operand(op);
1118 1119 1120
	op->orig_val = op->val;
}

1121 1122 1123 1124 1125 1126
static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
{
	if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
		ctxt->modrm_seg = VCPU_SREG_SS;
}

1127
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1128
			struct operand *op)
1129 1130
{
	u8 sib;
B
Bandan Das 已提交
1131
	int index_reg, base_reg, scale;
1132
	int rc = X86EMUL_CONTINUE;
1133
	ulong modrm_ea = 0;
1134

B
Bandan Das 已提交
1135 1136 1137
	ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
	index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
	base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1138

B
Bandan Das 已提交
1139
	ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
1140
	ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
B
Bandan Das 已提交
1141
	ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1142
	ctxt->modrm_seg = VCPU_SREG_DS;
1143

1144
	if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
1145
		op->type = OP_REG;
1146
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1147
		op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1148
				ctxt->d & ByteOp);
1149
		if (ctxt->d & Sse) {
A
Avi Kivity 已提交
1150 1151
			op->type = OP_XMM;
			op->bytes = 16;
1152 1153
			op->addr.xmm = ctxt->modrm_rm;
			read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
A
Avi Kivity 已提交
1154 1155
			return rc;
		}
A
Avi Kivity 已提交
1156 1157 1158
		if (ctxt->d & Mmx) {
			op->type = OP_MM;
			op->bytes = 8;
1159
			op->addr.mm = ctxt->modrm_rm & 7;
A
Avi Kivity 已提交
1160 1161
			return rc;
		}
1162
		fetch_register_operand(op);
1163 1164 1165
		return rc;
	}

1166 1167
	op->type = OP_MEM;

1168
	if (ctxt->ad_bytes == 2) {
1169 1170 1171 1172
		unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
		unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
		unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
		unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1173 1174

		/* 16-bit ModR/M decode. */
1175
		switch (ctxt->modrm_mod) {
1176
		case 0:
1177
			if (ctxt->modrm_rm == 6)
1178
				modrm_ea += insn_fetch(u16, ctxt);
1179 1180
			break;
		case 1:
1181
			modrm_ea += insn_fetch(s8, ctxt);
1182 1183
			break;
		case 2:
1184
			modrm_ea += insn_fetch(u16, ctxt);
1185 1186
			break;
		}
1187
		switch (ctxt->modrm_rm) {
1188
		case 0:
1189
			modrm_ea += bx + si;
1190 1191
			break;
		case 1:
1192
			modrm_ea += bx + di;
1193 1194
			break;
		case 2:
1195
			modrm_ea += bp + si;
1196 1197
			break;
		case 3:
1198
			modrm_ea += bp + di;
1199 1200
			break;
		case 4:
1201
			modrm_ea += si;
1202 1203
			break;
		case 5:
1204
			modrm_ea += di;
1205 1206
			break;
		case 6:
1207
			if (ctxt->modrm_mod != 0)
1208
				modrm_ea += bp;
1209 1210
			break;
		case 7:
1211
			modrm_ea += bx;
1212 1213
			break;
		}
1214 1215 1216
		if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
		    (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
			ctxt->modrm_seg = VCPU_SREG_SS;
1217
		modrm_ea = (u16)modrm_ea;
1218 1219
	} else {
		/* 32/64-bit ModR/M decode. */
1220
		if ((ctxt->modrm_rm & 7) == 4) {
1221
			sib = insn_fetch(u8, ctxt);
1222 1223 1224 1225
			index_reg |= (sib >> 3) & 7;
			base_reg |= sib & 7;
			scale = sib >> 6;

1226
			if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1227
				modrm_ea += insn_fetch(s32, ctxt);
1228
			else {
1229
				modrm_ea += reg_read(ctxt, base_reg);
1230
				adjust_modrm_seg(ctxt, base_reg);
1231 1232 1233 1234
				/* Increment ESP on POP [ESP] */
				if ((ctxt->d & IncSP) &&
				    base_reg == VCPU_REGS_RSP)
					modrm_ea += ctxt->op_bytes;
1235
			}
1236
			if (index_reg != 4)
1237
				modrm_ea += reg_read(ctxt, index_reg) << scale;
1238
		} else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1239
			modrm_ea += insn_fetch(s32, ctxt);
1240
			if (ctxt->mode == X86EMUL_MODE_PROT64)
1241
				ctxt->rip_relative = 1;
1242 1243
		} else {
			base_reg = ctxt->modrm_rm;
1244
			modrm_ea += reg_read(ctxt, base_reg);
1245 1246
			adjust_modrm_seg(ctxt, base_reg);
		}
1247
		switch (ctxt->modrm_mod) {
1248
		case 1:
1249
			modrm_ea += insn_fetch(s8, ctxt);
1250 1251
			break;
		case 2:
1252
			modrm_ea += insn_fetch(s32, ctxt);
1253 1254 1255
			break;
		}
	}
1256
	op->addr.mem.ea = modrm_ea;
1257 1258 1259
	if (ctxt->ad_bytes != 8)
		ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;

1260 1261 1262 1263 1264
done:
	return rc;
}

static int decode_abs(struct x86_emulate_ctxt *ctxt,
1265
		      struct operand *op)
1266
{
1267
	int rc = X86EMUL_CONTINUE;
1268

1269
	op->type = OP_MEM;
1270
	switch (ctxt->ad_bytes) {
1271
	case 2:
1272
		op->addr.mem.ea = insn_fetch(u16, ctxt);
1273 1274
		break;
	case 4:
1275
		op->addr.mem.ea = insn_fetch(u32, ctxt);
1276 1277
		break;
	case 8:
1278
		op->addr.mem.ea = insn_fetch(u64, ctxt);
1279 1280 1281 1282 1283 1284
		break;
	}
done:
	return rc;
}

1285
static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1286
{
1287
	long sv = 0, mask;
1288

1289
	if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1290
		mask = ~((long)ctxt->dst.bytes * 8 - 1);
1291

1292 1293 1294 1295
		if (ctxt->src.bytes == 2)
			sv = (s16)ctxt->src.val & (s16)mask;
		else if (ctxt->src.bytes == 4)
			sv = (s32)ctxt->src.val & (s32)mask;
1296 1297
		else
			sv = (s64)ctxt->src.val & (s64)mask;
1298

1299 1300
		ctxt->dst.addr.mem.ea = address_mask(ctxt,
					   ctxt->dst.addr.mem.ea + (sv >> 3));
1301
	}
1302 1303

	/* only subword offset */
1304
	ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1305 1306
}

1307 1308
static int read_emulated(struct x86_emulate_ctxt *ctxt,
			 unsigned long addr, void *dest, unsigned size)
A
Avi Kivity 已提交
1309
{
1310
	int rc;
1311
	struct read_cache *mc = &ctxt->mem_read;
A
Avi Kivity 已提交
1312

1313 1314
	if (mc->pos < mc->end)
		goto read_cached;
A
Avi Kivity 已提交
1315

1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327
	WARN_ON((mc->end + size) >= sizeof(mc->data));

	rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
				      &ctxt->exception);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	mc->end += size;

read_cached:
	memcpy(dest, mc->data + mc->pos, size);
	mc->pos += size;
1328 1329
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1330

1331 1332 1333 1334 1335
static int segmented_read(struct x86_emulate_ctxt *ctxt,
			  struct segmented_address addr,
			  void *data,
			  unsigned size)
{
1336 1337 1338
	int rc;
	ulong linear;

1339
	rc = linearize(ctxt, addr, size, false, &linear);
1340 1341
	if (rc != X86EMUL_CONTINUE)
		return rc;
1342
	return read_emulated(ctxt, linear, data, size);
1343 1344 1345 1346 1347 1348 1349
}

static int segmented_write(struct x86_emulate_ctxt *ctxt,
			   struct segmented_address addr,
			   const void *data,
			   unsigned size)
{
1350 1351 1352
	int rc;
	ulong linear;

1353
	rc = linearize(ctxt, addr, size, true, &linear);
1354 1355
	if (rc != X86EMUL_CONTINUE)
		return rc;
1356 1357
	return ctxt->ops->write_emulated(ctxt, linear, data, size,
					 &ctxt->exception);
1358 1359 1360 1361 1362 1363 1364
}

static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
			     struct segmented_address addr,
			     const void *orig_data, const void *data,
			     unsigned size)
{
1365 1366 1367
	int rc;
	ulong linear;

1368
	rc = linearize(ctxt, addr, size, true, &linear);
1369 1370
	if (rc != X86EMUL_CONTINUE)
		return rc;
1371 1372
	return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
					   size, &ctxt->exception);
1373 1374
}

1375 1376 1377 1378
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
			   unsigned int size, unsigned short port,
			   void *dest)
{
1379
	struct read_cache *rc = &ctxt->io_read;
1380

1381 1382
	if (rc->pos == rc->end) { /* refill pio read ahead */
		unsigned int in_page, n;
1383
		unsigned int count = ctxt->rep_prefix ?
1384
			address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1385
		in_page = (ctxt->eflags & EFLG_DF) ?
1386 1387
			offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
			PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1388
		n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
1389 1390 1391
		if (n == 0)
			n = 1;
		rc->pos = rc->end = 0;
1392
		if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1393 1394
			return 0;
		rc->end = n * size;
A
Avi Kivity 已提交
1395 1396
	}

1397 1398
	if (ctxt->rep_prefix && (ctxt->d & String) &&
	    !(ctxt->eflags & EFLG_DF)) {
1399 1400 1401 1402 1403 1404 1405 1406
		ctxt->dst.data = rc->data + rc->pos;
		ctxt->dst.type = OP_MEM_STR;
		ctxt->dst.count = (rc->end - rc->pos) / size;
		rc->pos = rc->end;
	} else {
		memcpy(dest, rc->data + rc->pos, size);
		rc->pos += size;
	}
1407 1408
	return 1;
}
A
Avi Kivity 已提交
1409

1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425
static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
				     u16 index, struct desc_struct *desc)
{
	struct desc_ptr dt;
	ulong addr;

	ctxt->ops->get_idt(ctxt, &dt);

	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, index << 3 | 0x2);

	addr = dt.address + index * 8;
	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
				   &ctxt->exception);
}

1426 1427 1428
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
				     u16 selector, struct desc_ptr *dt)
{
1429
	const struct x86_emulate_ops *ops = ctxt->ops;
1430
	u32 base3 = 0;
1431

1432 1433
	if (selector & 1 << 2) {
		struct desc_struct desc;
1434 1435
		u16 sel;

1436
		memset (dt, 0, sizeof *dt);
1437 1438
		if (!ops->get_segment(ctxt, &sel, &desc, &base3,
				      VCPU_SREG_LDTR))
1439
			return;
1440

1441
		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1442
		dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
1443
	} else
1444
		ops->get_gdt(ctxt, dt);
1445
}
1446

1447 1448
static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
			      u16 selector, ulong *desc_addr_p)
1449 1450 1451 1452
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
1453

1454
	get_descriptor_table_ptr(ctxt, selector, &dt);
1455

1456 1457
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
1458

1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486
	addr = dt.address + index * 8;

#ifdef CONFIG_X86_64
	if (addr >> 32 != 0) {
		u64 efer = 0;

		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (!(efer & EFER_LMA))
			addr &= (u32)-1;
	}
#endif

	*desc_addr_p = addr;
	return X86EMUL_CONTINUE;
}

/* allowed just for 8 bytes segments */
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, struct desc_struct *desc,
				   ulong *desc_addr_p)
{
	int rc;

	rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
1487
				   &ctxt->exception);
1488
}
1489

1490 1491 1492 1493
/* allowed just for 8 bytes segments */
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				    u16 selector, struct desc_struct *desc)
{
1494
	int rc;
1495
	ulong addr;
A
Avi Kivity 已提交
1496

1497 1498 1499
	rc = get_descriptor_ptr(ctxt, selector, &addr);
	if (rc != X86EMUL_CONTINUE)
		return rc;
A
Avi Kivity 已提交
1500

1501 1502
	return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
				    &ctxt->exception);
1503
}
1504

1505
/* Does not support long mode */
1506
static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1507
				     u16 selector, int seg, u8 cpl,
1508
				     enum x86_transfer_type transfer,
1509
				     struct desc_struct *desc)
1510
{
1511
	struct desc_struct seg_desc, old_desc;
1512
	u8 dpl, rpl;
1513 1514 1515
	unsigned err_vec = GP_VECTOR;
	u32 err_code = 0;
	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1516
	ulong desc_addr;
1517
	int ret;
1518
	u16 dummy;
1519
	u32 base3 = 0;
1520

1521
	memset(&seg_desc, 0, sizeof seg_desc);
1522

1523 1524 1525
	if (ctxt->mode == X86EMUL_MODE_REAL) {
		/* set real mode segment descriptor (keep limit etc. for
		 * unreal mode) */
1526
		ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1527 1528
		set_desc_base(&seg_desc, selector << 4);
		goto load;
1529 1530 1531 1532 1533 1534 1535 1536 1537
	} else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
		/* VM86 needs a clean new segment descriptor */
		set_desc_base(&seg_desc, selector << 4);
		set_desc_limit(&seg_desc, 0xffff);
		seg_desc.type = 3;
		seg_desc.p = 1;
		seg_desc.s = 1;
		seg_desc.dpl = 3;
		goto load;
1538 1539
	}

1540 1541 1542 1543 1544 1545 1546
	rpl = selector & 3;

	/* NULL selector is not valid for TR, CS and SS (except for long mode) */
	if ((seg == VCPU_SREG_CS
	     || (seg == VCPU_SREG_SS
		 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
	     || seg == VCPU_SREG_TR)
1547 1548 1549 1550 1551 1552 1553 1554 1555 1556
	    && null_selector)
		goto exception;

	/* TR should be in GDT only */
	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
		goto exception;

	if (null_selector) /* for NULL selector skip all following checks */
		goto load;

1557
	ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1558 1559 1560 1561
	if (ret != X86EMUL_CONTINUE)
		return ret;

	err_code = selector & 0xfffc;
1562 1563
	err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
							   GP_VECTOR;
1564

G
Guo Chao 已提交
1565
	/* can't load system descriptor into segment selector */
1566 1567 1568
	if (seg <= VCPU_SREG_GS && !seg_desc.s) {
		if (transfer == X86_TRANSFER_CALL_JMP)
			return X86EMUL_UNHANDLEABLE;
1569
		goto exception;
1570
	}
1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586

	if (!seg_desc.p) {
		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
		goto exception;
	}

	dpl = seg_desc.dpl;

	switch (seg) {
	case VCPU_SREG_SS:
		/*
		 * segment is not a writable data segment or segment
		 * selector's RPL != CPL or segment selector's RPL != CPL
		 */
		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
			goto exception;
A
Avi Kivity 已提交
1587
		break;
1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600
	case VCPU_SREG_CS:
		if (!(seg_desc.type & 8))
			goto exception;

		if (seg_desc.type & 4) {
			/* conforming */
			if (dpl > cpl)
				goto exception;
		} else {
			/* nonconforming */
			if (rpl > cpl || dpl != cpl)
				goto exception;
		}
1601 1602 1603 1604 1605 1606 1607 1608 1609
		/* in long-mode d/b must be clear if l is set */
		if (seg_desc.d && seg_desc.l) {
			u64 efer = 0;

			ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
			if (efer & EFER_LMA)
				goto exception;
		}

1610 1611
		/* CS(RPL) <- CPL */
		selector = (selector & 0xfffc) | cpl;
A
Avi Kivity 已提交
1612
		break;
1613 1614 1615
	case VCPU_SREG_TR:
		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
			goto exception;
1616 1617 1618 1619 1620 1621
		old_desc = seg_desc;
		seg_desc.type |= 2; /* busy */
		ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
						  sizeof(seg_desc), &ctxt->exception);
		if (ret != X86EMUL_CONTINUE)
			return ret;
1622 1623 1624 1625 1626 1627
		break;
	case VCPU_SREG_LDTR:
		if (seg_desc.s || seg_desc.type != 2)
			goto exception;
		break;
	default: /*  DS, ES, FS, or GS */
1628
		/*
1629 1630 1631
		 * segment is not a data or readable code segment or
		 * ((segment is a data or nonconforming code segment)
		 * and (both RPL and CPL > DPL))
1632
		 */
1633 1634 1635 1636
		if ((seg_desc.type & 0xa) == 0x8 ||
		    (((seg_desc.type & 0xc) != 0xc) &&
		     (rpl > dpl && cpl > dpl)))
			goto exception;
A
Avi Kivity 已提交
1637
		break;
1638 1639 1640 1641
	}

	if (seg_desc.s) {
		/* mark segment as accessed */
1642 1643 1644 1645 1646 1647 1648
		if (!(seg_desc.type & 1)) {
			seg_desc.type |= 1;
			ret = write_segment_descriptor(ctxt, selector,
						       &seg_desc);
			if (ret != X86EMUL_CONTINUE)
				return ret;
		}
1649 1650 1651 1652 1653
	} else if (ctxt->mode == X86EMUL_MODE_PROT64) {
		ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
				sizeof(base3), &ctxt->exception);
		if (ret != X86EMUL_CONTINUE)
			return ret;
1654 1655 1656
		if (is_noncanonical_address(get_desc_base(&seg_desc) |
					     ((u64)base3 << 32)))
			return emulate_gp(ctxt, 0);
1657 1658
	}
load:
1659
	ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1660 1661
	if (desc)
		*desc = seg_desc;
1662 1663
	return X86EMUL_CONTINUE;
exception:
1664
	return emulate_exception(ctxt, err_vec, err_code, true);
1665 1666
}

1667 1668 1669 1670
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, int seg)
{
	u8 cpl = ctxt->ops->cpl(ctxt);
1671 1672
	return __load_segment_descriptor(ctxt, selector, seg, cpl,
					 X86_TRANSFER_NONE, NULL);
1673 1674
}

1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693
static void write_register_operand(struct operand *op)
{
	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
	switch (op->bytes) {
	case 1:
		*(u8 *)op->addr.reg = (u8)op->val;
		break;
	case 2:
		*(u16 *)op->addr.reg = (u16)op->val;
		break;
	case 4:
		*op->addr.reg = (u32)op->val;
		break;	/* 64b: zero-extend */
	case 8:
		*op->addr.reg = op->val;
		break;
	}
}

1694
static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1695
{
1696
	switch (op->type) {
1697
	case OP_REG:
1698
		write_register_operand(op);
A
Avi Kivity 已提交
1699
		break;
1700
	case OP_MEM:
1701
		if (ctxt->lock_prefix)
P
Paolo Bonzini 已提交
1702 1703 1704 1705 1706 1707 1708
			return segmented_cmpxchg(ctxt,
						 op->addr.mem,
						 &op->orig_val,
						 &op->val,
						 op->bytes);
		else
			return segmented_write(ctxt,
1709 1710 1711
					       op->addr.mem,
					       &op->val,
					       op->bytes);
1712
		break;
1713
	case OP_MEM_STR:
P
Paolo Bonzini 已提交
1714 1715 1716 1717
		return segmented_write(ctxt,
				       op->addr.mem,
				       op->data,
				       op->bytes * op->count);
1718
		break;
A
Avi Kivity 已提交
1719
	case OP_XMM:
1720
		write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
A
Avi Kivity 已提交
1721
		break;
A
Avi Kivity 已提交
1722
	case OP_MM:
1723
		write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
A
Avi Kivity 已提交
1724
		break;
1725 1726
	case OP_NONE:
		/* no writeback */
1727
		break;
1728
	default:
1729
		break;
A
Avi Kivity 已提交
1730
	}
1731 1732
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1733

1734
static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1735
{
1736
	struct segmented_address addr;
1737

1738
	rsp_increment(ctxt, -bytes);
1739
	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1740 1741
	addr.seg = VCPU_SREG_SS;

1742 1743 1744 1745 1746
	return segmented_write(ctxt, addr, data, bytes);
}

static int em_push(struct x86_emulate_ctxt *ctxt)
{
1747
	/* Disable writeback. */
1748
	ctxt->dst.type = OP_NONE;
1749
	return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1750
}
1751

1752 1753 1754 1755
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
		       void *dest, int len)
{
	int rc;
1756
	struct segmented_address addr;
1757

1758
	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1759
	addr.seg = VCPU_SREG_SS;
1760
	rc = segmented_read(ctxt, addr, dest, len);
1761 1762 1763
	if (rc != X86EMUL_CONTINUE)
		return rc;

1764
	rsp_increment(ctxt, len);
1765
	return rc;
1766 1767
}

1768 1769
static int em_pop(struct x86_emulate_ctxt *ctxt)
{
1770
	return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1771 1772
}

1773
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1774
			void *dest, int len)
1775 1776
{
	int rc;
1777 1778
	unsigned long val, change_mask;
	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1779
	int cpl = ctxt->ops->cpl(ctxt);
1780

1781
	rc = emulate_pop(ctxt, &val, len);
1782 1783
	if (rc != X86EMUL_CONTINUE)
		return rc;
1784

1785
	change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1786
		| EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
1787

1788 1789 1790 1791 1792 1793 1794 1795 1796 1797
	switch(ctxt->mode) {
	case X86EMUL_MODE_PROT64:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT16:
		if (cpl == 0)
			change_mask |= EFLG_IOPL;
		if (cpl <= iopl)
			change_mask |= EFLG_IF;
		break;
	case X86EMUL_MODE_VM86:
1798 1799
		if (iopl < 3)
			return emulate_gp(ctxt, 0);
1800 1801 1802 1803 1804
		change_mask |= EFLG_IF;
		break;
	default: /* real mode */
		change_mask |= (EFLG_IOPL | EFLG_IF);
		break;
1805
	}
1806 1807 1808 1809 1810

	*(unsigned long *)dest =
		(ctxt->eflags & ~change_mask) | (val & change_mask);

	return rc;
1811 1812
}

1813 1814
static int em_popf(struct x86_emulate_ctxt *ctxt)
{
1815 1816 1817 1818
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->eflags;
	ctxt->dst.bytes = ctxt->op_bytes;
	return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1819 1820
}

A
Avi Kivity 已提交
1821 1822 1823 1824 1825
static int em_enter(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	unsigned frame_size = ctxt->src.val;
	unsigned nesting_level = ctxt->src2.val & 31;
1826
	ulong rbp;
A
Avi Kivity 已提交
1827 1828 1829 1830

	if (nesting_level)
		return X86EMUL_UNHANDLEABLE;

1831 1832
	rbp = reg_read(ctxt, VCPU_REGS_RBP);
	rc = push(ctxt, &rbp, stack_size(ctxt));
A
Avi Kivity 已提交
1833 1834
	if (rc != X86EMUL_CONTINUE)
		return rc;
1835
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
A
Avi Kivity 已提交
1836
		      stack_mask(ctxt));
1837 1838
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
		      reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
A
Avi Kivity 已提交
1839 1840 1841 1842
		      stack_mask(ctxt));
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
1843 1844
static int em_leave(struct x86_emulate_ctxt *ctxt)
{
1845
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
A
Avi Kivity 已提交
1846
		      stack_mask(ctxt));
1847
	return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
A
Avi Kivity 已提交
1848 1849
}

1850
static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1851
{
1852 1853
	int seg = ctxt->src2.val;

1854
	ctxt->src.val = get_segment_selector(ctxt, seg);
1855 1856 1857 1858
	if (ctxt->op_bytes == 4) {
		rsp_increment(ctxt, -2);
		ctxt->op_bytes = 2;
	}
1859

1860
	return em_push(ctxt);
1861 1862
}

1863
static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1864
{
1865
	int seg = ctxt->src2.val;
1866 1867
	unsigned long selector;
	int rc;
1868

1869
	rc = emulate_pop(ctxt, &selector, 2);
1870 1871 1872
	if (rc != X86EMUL_CONTINUE)
		return rc;

1873 1874
	if (ctxt->modrm_reg == VCPU_SREG_SS)
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1875 1876
	if (ctxt->op_bytes > 2)
		rsp_increment(ctxt, ctxt->op_bytes - 2);
1877

1878
	rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1879
	return rc;
1880 1881
}

1882
static int em_pusha(struct x86_emulate_ctxt *ctxt)
1883
{
1884
	unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1885 1886
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RAX;
1887

1888 1889
	while (reg <= VCPU_REGS_RDI) {
		(reg == VCPU_REGS_RSP) ?
1890
		(ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1891

1892
		rc = em_push(ctxt);
1893 1894
		if (rc != X86EMUL_CONTINUE)
			return rc;
1895

1896
		++reg;
1897 1898
	}

1899
	return rc;
1900 1901
}

1902 1903
static int em_pushf(struct x86_emulate_ctxt *ctxt)
{
1904
	ctxt->src.val = (unsigned long)ctxt->eflags & ~EFLG_VM;
1905 1906 1907
	return em_push(ctxt);
}

1908
static int em_popa(struct x86_emulate_ctxt *ctxt)
1909
{
1910 1911
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RDI;
1912

1913 1914
	while (reg >= VCPU_REGS_RAX) {
		if (reg == VCPU_REGS_RSP) {
1915
			rsp_increment(ctxt, ctxt->op_bytes);
1916 1917
			--reg;
		}
1918

1919
		rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
1920 1921 1922
		if (rc != X86EMUL_CONTINUE)
			break;
		--reg;
1923
	}
1924
	return rc;
1925 1926
}

1927
static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1928
{
1929
	const struct x86_emulate_ops *ops = ctxt->ops;
1930
	int rc;
1931 1932 1933 1934 1935 1936
	struct desc_ptr dt;
	gva_t cs_addr;
	gva_t eip_addr;
	u16 cs, eip;

	/* TODO: Add limit checks */
1937
	ctxt->src.val = ctxt->eflags;
1938
	rc = em_push(ctxt);
1939 1940
	if (rc != X86EMUL_CONTINUE)
		return rc;
1941 1942 1943

	ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);

1944
	ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1945
	rc = em_push(ctxt);
1946 1947
	if (rc != X86EMUL_CONTINUE)
		return rc;
1948

1949
	ctxt->src.val = ctxt->_eip;
1950
	rc = em_push(ctxt);
1951 1952 1953
	if (rc != X86EMUL_CONTINUE)
		return rc;

1954
	ops->get_idt(ctxt, &dt);
1955 1956 1957 1958

	eip_addr = dt.address + (irq << 2);
	cs_addr = dt.address + (irq << 2) + 2;

1959
	rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1960 1961 1962
	if (rc != X86EMUL_CONTINUE)
		return rc;

1963
	rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1964 1965 1966
	if (rc != X86EMUL_CONTINUE)
		return rc;

1967
	rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
1968 1969 1970
	if (rc != X86EMUL_CONTINUE)
		return rc;

1971
	ctxt->_eip = eip;
1972 1973 1974 1975

	return rc;
}

1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986
int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
{
	int rc;

	invalidate_registers(ctxt);
	rc = __emulate_int_real(ctxt, irq);
	if (rc == X86EMUL_CONTINUE)
		writeback_registers(ctxt);
	return rc;
}

1987
static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
1988 1989 1990
{
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1991
		return __emulate_int_real(ctxt, irq);
1992 1993 1994 1995 1996 1997 1998 1999 2000 2001
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
	default:
		/* Protected mode interrupts unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
	}
}

2002
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
2003
{
2004 2005 2006 2007 2008 2009 2010 2011
	int rc = X86EMUL_CONTINUE;
	unsigned long temp_eip = 0;
	unsigned long temp_eflags = 0;
	unsigned long cs = 0;
	unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
			     EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
			     EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
	unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
2012

2013
	/* TODO: Add stack limit check */
2014

2015
	rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
2016

2017 2018
	if (rc != X86EMUL_CONTINUE)
		return rc;
2019

2020 2021
	if (temp_eip & ~0xffff)
		return emulate_gp(ctxt, 0);
2022

2023
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2024

2025 2026
	if (rc != X86EMUL_CONTINUE)
		return rc;
2027

2028
	rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
2029

2030 2031
	if (rc != X86EMUL_CONTINUE)
		return rc;
2032

2033
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2034

2035 2036
	if (rc != X86EMUL_CONTINUE)
		return rc;
2037

2038
	ctxt->_eip = temp_eip;
2039 2040


2041
	if (ctxt->op_bytes == 4)
2042
		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
2043
	else if (ctxt->op_bytes == 2) {
2044 2045
		ctxt->eflags &= ~0xffff;
		ctxt->eflags |= temp_eflags;
2046
	}
2047 2048 2049 2050 2051

	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
	ctxt->eflags |= EFLG_RESERVED_ONE_MASK;

	return rc;
2052 2053
}

2054
static int em_iret(struct x86_emulate_ctxt *ctxt)
2055
{
2056 2057
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
2058
		return emulate_iret_real(ctxt);
2059 2060 2061 2062
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
2063
	default:
2064 2065
		/* iret from protected mode unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
2066 2067 2068
	}
}

2069 2070 2071
static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
{
	int rc;
2072 2073 2074 2075 2076 2077 2078 2079 2080
	unsigned short sel, old_sel;
	struct desc_struct old_desc, new_desc;
	const struct x86_emulate_ops *ops = ctxt->ops;
	u8 cpl = ctxt->ops->cpl(ctxt);

	/* Assignment of RIP may only fail in 64-bit mode */
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
				 VCPU_SREG_CS);
2081

2082
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2083

2084 2085
	rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
				       X86_TRANSFER_CALL_JMP,
2086
				       &new_desc);
2087 2088 2089
	if (rc != X86EMUL_CONTINUE)
		return rc;

2090
	rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
2091
	if (rc != X86EMUL_CONTINUE) {
2092
		WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2093 2094 2095 2096 2097
		/* assigning eip failed; restore the old cs */
		ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
		return rc;
	}
	return rc;
2098 2099
}

2100
static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
2101
{
2102 2103
	return assign_eip_near(ctxt, ctxt->src.val);
}
2104

2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115
static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	long int old_eip;

	old_eip = ctxt->_eip;
	rc = assign_eip_near(ctxt, ctxt->src.val);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->src.val = old_eip;
	rc = em_push(ctxt);
2116
	return rc;
2117 2118
}

2119
static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2120
{
2121
	u64 old = ctxt->dst.orig_val64;
2122

2123 2124 2125
	if (ctxt->dst.bytes == 16)
		return X86EMUL_UNHANDLEABLE;

2126 2127 2128 2129
	if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
	    ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
		*reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
		*reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2130
		ctxt->eflags &= ~EFLG_ZF;
2131
	} else {
2132 2133
		ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
			(u32) reg_read(ctxt, VCPU_REGS_RBX);
2134

2135
		ctxt->eflags |= EFLG_ZF;
2136
	}
2137
	return X86EMUL_CONTINUE;
2138 2139
}

2140 2141
static int em_ret(struct x86_emulate_ctxt *ctxt)
{
2142 2143 2144 2145 2146 2147 2148 2149
	int rc;
	unsigned long eip;

	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	return assign_eip_near(ctxt, eip);
2150 2151
}

2152
static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2153 2154
{
	int rc;
2155 2156
	unsigned long eip, cs;
	u16 old_cs;
2157
	int cpl = ctxt->ops->cpl(ctxt);
2158 2159 2160 2161 2162 2163
	struct desc_struct old_desc, new_desc;
	const struct x86_emulate_ops *ops = ctxt->ops;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
				 VCPU_SREG_CS);
2164

2165
	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2166
	if (rc != X86EMUL_CONTINUE)
2167
		return rc;
2168
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2169
	if (rc != X86EMUL_CONTINUE)
2170
		return rc;
2171 2172 2173
	/* Outer-privilege level return is not implemented */
	if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
		return X86EMUL_UNHANDLEABLE;
2174 2175
	rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
				       X86_TRANSFER_RET,
2176 2177 2178
				       &new_desc);
	if (rc != X86EMUL_CONTINUE)
		return rc;
2179
	rc = assign_eip_far(ctxt, eip, &new_desc);
2180
	if (rc != X86EMUL_CONTINUE) {
2181
		WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2182 2183
		ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
	}
2184 2185 2186
	return rc;
}

2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197
static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
{
        int rc;

        rc = em_ret_far(ctxt);
        if (rc != X86EMUL_CONTINUE)
                return rc;
        rsp_increment(ctxt, ctxt->src.val);
        return X86EMUL_CONTINUE;
}

2198 2199 2200
static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
{
	/* Save real source value, then compare EAX against destination. */
2201 2202
	ctxt->dst.orig_val = ctxt->dst.val;
	ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
2203
	ctxt->src.orig_val = ctxt->src.val;
2204
	ctxt->src.val = ctxt->dst.orig_val;
2205
	fastop(ctxt, em_cmp);
2206 2207 2208 2209 2210 2211 2212

	if (ctxt->eflags & EFLG_ZF) {
		/* Success: write back to memory. */
		ctxt->dst.val = ctxt->src.orig_val;
	} else {
		/* Failure: write the value we saw to EAX. */
		ctxt->dst.type = OP_REG;
2213
		ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2214
		ctxt->dst.val = ctxt->dst.orig_val;
2215 2216 2217 2218
	}
	return X86EMUL_CONTINUE;
}

2219
static int em_lseg(struct x86_emulate_ctxt *ctxt)
2220
{
2221
	int seg = ctxt->src2.val;
2222 2223 2224
	unsigned short sel;
	int rc;

2225
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2226

2227
	rc = load_segment_descriptor(ctxt, sel, seg);
2228 2229 2230
	if (rc != X86EMUL_CONTINUE)
		return rc;

2231
	ctxt->dst.val = ctxt->src.val;
2232 2233 2234
	return rc;
}

2235
static void
2236
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2237
			struct desc_struct *cs, struct desc_struct *ss)
2238 2239
{
	cs->l = 0;		/* will be adjusted later */
2240
	set_desc_base(cs, 0);	/* flat segment */
2241
	cs->g = 1;		/* 4kb granularity */
2242
	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
2243 2244 2245
	cs->type = 0x0b;	/* Read, Execute, Accessed */
	cs->s = 1;
	cs->dpl = 0;		/* will be adjusted later */
2246 2247
	cs->p = 1;
	cs->d = 1;
2248
	cs->avl = 0;
2249

2250 2251
	set_desc_base(ss, 0);	/* flat segment */
	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
2252 2253 2254
	ss->g = 1;		/* 4kb granularity */
	ss->s = 1;
	ss->type = 0x03;	/* Read/Write, Accessed */
2255
	ss->d = 1;		/* 32bit stack segment */
2256
	ss->dpl = 0;
2257
	ss->p = 1;
2258 2259
	ss->l = 0;
	ss->avl = 0;
2260 2261
}

2262 2263 2264 2265 2266
static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

	eax = ecx = 0;
2267 2268
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2269 2270 2271 2272
		&& ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
		&& edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
}

2273 2274
static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
{
2275
	const struct x86_emulate_ops *ops = ctxt->ops;
2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286
	u32 eax, ebx, ecx, edx;

	/*
	 * syscall should always be enabled in longmode - so only become
	 * vendor specific (cpuid) if other modes are active...
	 */
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return true;

	eax = 0x00000000;
	ecx = 0x00000000;
2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311
	ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	/*
	 * Intel ("GenuineIntel")
	 * remark: Intel CPUs only support "syscall" in 64bit
	 * longmode. Also an 64bit guest with a
	 * 32bit compat-app running will #UD !! While this
	 * behaviour can be fixed (by emulating) into AMD
	 * response - CPUs of AMD can't behave like Intel.
	 */
	if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
		return false;

	/* AMD ("AuthenticAMD") */
	if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
		return true;

	/* AMD ("AMDisbetter!") */
	if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
		return true;
2312 2313 2314 2315 2316

	/* default: (not Intel, not AMD), apply Intel's stricter rules... */
	return false;
}

2317
static int em_syscall(struct x86_emulate_ctxt *ctxt)
2318
{
2319
	const struct x86_emulate_ops *ops = ctxt->ops;
2320
	struct desc_struct cs, ss;
2321
	u64 msr_data;
2322
	u16 cs_sel, ss_sel;
2323
	u64 efer = 0;
2324 2325

	/* syscall is not available in real mode */
2326
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2327 2328
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_ud(ctxt);
2329

2330 2331 2332
	if (!(em_syscall_is_enabled(ctxt)))
		return emulate_ud(ctxt);

2333
	ops->get_msr(ctxt, MSR_EFER, &efer);
2334
	setup_syscalls_segments(ctxt, &cs, &ss);
2335

2336 2337 2338
	if (!(efer & EFER_SCE))
		return emulate_ud(ctxt);

2339
	ops->get_msr(ctxt, MSR_STAR, &msr_data);
2340
	msr_data >>= 32;
2341 2342
	cs_sel = (u16)(msr_data & 0xfffc);
	ss_sel = (u16)(msr_data + 8);
2343

2344
	if (efer & EFER_LMA) {
2345
		cs.d = 0;
2346 2347
		cs.l = 1;
	}
2348 2349
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2350

2351
	*reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2352
	if (efer & EFER_LMA) {
2353
#ifdef CONFIG_X86_64
2354
		*reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
2355

2356
		ops->get_msr(ctxt,
2357 2358
			     ctxt->mode == X86EMUL_MODE_PROT64 ?
			     MSR_LSTAR : MSR_CSTAR, &msr_data);
2359
		ctxt->_eip = msr_data;
2360

2361
		ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2362
		ctxt->eflags &= ~msr_data;
2363
		ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2364 2365 2366
#endif
	} else {
		/* legacy mode */
2367
		ops->get_msr(ctxt, MSR_STAR, &msr_data);
2368
		ctxt->_eip = (u32)msr_data;
2369

2370
		ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
2371 2372
	}

2373
	return X86EMUL_CONTINUE;
2374 2375
}

2376
static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2377
{
2378
	const struct x86_emulate_ops *ops = ctxt->ops;
2379
	struct desc_struct cs, ss;
2380
	u64 msr_data;
2381
	u16 cs_sel, ss_sel;
2382
	u64 efer = 0;
2383

2384
	ops->get_msr(ctxt, MSR_EFER, &efer);
2385
	/* inject #GP if in real mode */
2386 2387
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return emulate_gp(ctxt, 0);
2388

2389 2390 2391 2392 2393 2394 2395 2396
	/*
	 * Not recognized on AMD in compat mode (but is recognized in legacy
	 * mode).
	 */
	if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
	    && !vendor_intel(ctxt))
		return emulate_ud(ctxt);

2397
	/* sysenter/sysexit have not been tested in 64bit mode. */
2398
	if (ctxt->mode == X86EMUL_MODE_PROT64)
2399
		return X86EMUL_UNHANDLEABLE;
2400

2401
	setup_syscalls_segments(ctxt, &cs, &ss);
2402

2403
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2404 2405
	switch (ctxt->mode) {
	case X86EMUL_MODE_PROT32:
2406 2407
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2408 2409
		break;
	case X86EMUL_MODE_PROT64:
2410 2411
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2412
		break;
2413 2414
	default:
		break;
2415 2416
	}

2417
	ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
2418 2419 2420 2421
	cs_sel = (u16)msr_data;
	cs_sel &= ~SELECTOR_RPL_MASK;
	ss_sel = cs_sel + 8;
	ss_sel &= ~SELECTOR_RPL_MASK;
2422
	if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
2423
		cs.d = 0;
2424 2425 2426
		cs.l = 1;
	}

2427 2428
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2429

2430
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2431
	ctxt->_eip = msr_data;
2432

2433
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2434
	*reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
2435

2436
	return X86EMUL_CONTINUE;
2437 2438
}

2439
static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2440
{
2441
	const struct x86_emulate_ops *ops = ctxt->ops;
2442
	struct desc_struct cs, ss;
2443
	u64 msr_data, rcx, rdx;
2444
	int usermode;
X
Xiao Guangrong 已提交
2445
	u16 cs_sel = 0, ss_sel = 0;
2446

2447 2448
	/* inject #GP if in real mode or Virtual 8086 mode */
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2449 2450
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_gp(ctxt, 0);
2451

2452
	setup_syscalls_segments(ctxt, &cs, &ss);
2453

2454
	if ((ctxt->rex_prefix & 0x8) != 0x0)
2455 2456 2457 2458
		usermode = X86EMUL_MODE_PROT64;
	else
		usermode = X86EMUL_MODE_PROT32;

2459 2460 2461
	rcx = reg_read(ctxt, VCPU_REGS_RCX);
	rdx = reg_read(ctxt, VCPU_REGS_RDX);

2462 2463
	cs.dpl = 3;
	ss.dpl = 3;
2464
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2465 2466
	switch (usermode) {
	case X86EMUL_MODE_PROT32:
2467
		cs_sel = (u16)(msr_data + 16);
2468 2469
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2470
		ss_sel = (u16)(msr_data + 24);
2471 2472
		rcx = (u32)rcx;
		rdx = (u32)rdx;
2473 2474
		break;
	case X86EMUL_MODE_PROT64:
2475
		cs_sel = (u16)(msr_data + 32);
2476 2477
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2478 2479
		ss_sel = cs_sel + 8;
		cs.d = 0;
2480
		cs.l = 1;
2481 2482 2483
		if (is_noncanonical_address(rcx) ||
		    is_noncanonical_address(rdx))
			return emulate_gp(ctxt, 0);
2484 2485
		break;
	}
2486 2487
	cs_sel |= SELECTOR_RPL_MASK;
	ss_sel |= SELECTOR_RPL_MASK;
2488

2489 2490
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2491

2492 2493
	ctxt->_eip = rdx;
	*reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2494

2495
	return X86EMUL_CONTINUE;
2496 2497
}

2498
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2499 2500 2501 2502 2503 2504 2505
{
	int iopl;
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return false;
	if (ctxt->mode == X86EMUL_MODE_VM86)
		return true;
	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2506
	return ctxt->ops->cpl(ctxt) > iopl;
2507 2508 2509 2510 2511
}

static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
					    u16 port, u16 len)
{
2512
	const struct x86_emulate_ops *ops = ctxt->ops;
2513
	struct desc_struct tr_seg;
2514
	u32 base3;
2515
	int r;
2516
	u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2517
	unsigned mask = (1 << len) - 1;
2518
	unsigned long base;
2519

2520
	ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2521
	if (!tr_seg.p)
2522
		return false;
2523
	if (desc_limit_scaled(&tr_seg) < 103)
2524
		return false;
2525 2526 2527 2528
	base = get_desc_base(&tr_seg);
#ifdef CONFIG_X86_64
	base |= ((u64)base3) << 32;
#endif
2529
	r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2530 2531
	if (r != X86EMUL_CONTINUE)
		return false;
2532
	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2533
		return false;
2534
	r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2535 2536 2537 2538 2539 2540 2541 2542 2543 2544
	if (r != X86EMUL_CONTINUE)
		return false;
	if ((perm >> bit_idx) & mask)
		return false;
	return true;
}

static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
				 u16 port, u16 len)
{
2545 2546 2547
	if (ctxt->perm_ok)
		return true;

2548 2549
	if (emulator_bad_iopl(ctxt))
		if (!emulator_io_port_access_allowed(ctxt, port, len))
2550
			return false;
2551 2552 2553

	ctxt->perm_ok = true;

2554 2555 2556
	return true;
}

2557 2558 2559
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_16 *tss)
{
2560
	tss->ip = ctxt->_eip;
2561
	tss->flag = ctxt->eflags;
2562 2563 2564 2565 2566 2567 2568 2569
	tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
	tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
	tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
	tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
	tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
	tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
	tss->si = reg_read(ctxt, VCPU_REGS_RSI);
	tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2570

2571 2572 2573 2574 2575
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2576 2577 2578 2579 2580 2581
}

static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_16 *tss)
{
	int ret;
2582
	u8 cpl;
2583

2584
	ctxt->_eip = tss->ip;
2585
	ctxt->eflags = tss->flag | 2;
2586 2587 2588 2589 2590 2591 2592 2593
	*reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
	*reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
	*reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
	*reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
	*reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
	*reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
	*reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
	*reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
2594 2595 2596 2597 2598

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2599 2600 2601 2602 2603
	set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2604

2605 2606
	cpl = tss->cs & 3;

2607
	/*
G
Guo Chao 已提交
2608
	 * Now load segment descriptors. If fault happens at this stage
2609 2610
	 * it is handled in a context of new task
	 */
2611
	ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2612
					X86_TRANSFER_TASK_SWITCH, NULL);
2613 2614
	if (ret != X86EMUL_CONTINUE)
		return ret;
2615
	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2616
					X86_TRANSFER_TASK_SWITCH, NULL);
2617 2618
	if (ret != X86EMUL_CONTINUE)
		return ret;
2619
	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2620
					X86_TRANSFER_TASK_SWITCH, NULL);
2621 2622
	if (ret != X86EMUL_CONTINUE)
		return ret;
2623
	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2624
					X86_TRANSFER_TASK_SWITCH, NULL);
2625 2626
	if (ret != X86EMUL_CONTINUE)
		return ret;
2627
	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2628
					X86_TRANSFER_TASK_SWITCH, NULL);
2629 2630 2631 2632 2633 2634 2635 2636 2637 2638
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_16(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2639
	const struct x86_emulate_ops *ops = ctxt->ops;
2640 2641
	struct tss_segment_16 tss_seg;
	int ret;
2642
	u32 new_tss_base = get_desc_base(new_desc);
2643

2644
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2645
			    &ctxt->exception);
2646
	if (ret != X86EMUL_CONTINUE)
2647 2648
		return ret;

2649
	save_state_to_tss16(ctxt, &tss_seg);
2650

2651
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2652
			     &ctxt->exception);
2653
	if (ret != X86EMUL_CONTINUE)
2654 2655
		return ret;

2656
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2657
			    &ctxt->exception);
2658
	if (ret != X86EMUL_CONTINUE)
2659 2660 2661 2662 2663
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2664
		ret = ops->write_std(ctxt, new_tss_base,
2665 2666
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2667
				     &ctxt->exception);
2668
		if (ret != X86EMUL_CONTINUE)
2669 2670 2671
			return ret;
	}

2672
	return load_state_from_tss16(ctxt, &tss_seg);
2673 2674 2675 2676 2677
}

static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_32 *tss)
{
2678
	/* CR3 and ldt selector are not saved intentionally */
2679
	tss->eip = ctxt->_eip;
2680
	tss->eflags = ctxt->eflags;
2681 2682 2683 2684 2685 2686 2687 2688
	tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
	tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
	tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
	tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
	tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
	tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
	tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
	tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
2689

2690 2691 2692 2693 2694 2695
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
	tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2696 2697 2698 2699 2700 2701
}

static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_32 *tss)
{
	int ret;
2702
	u8 cpl;
2703

2704
	if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2705
		return emulate_gp(ctxt, 0);
2706
	ctxt->_eip = tss->eip;
2707
	ctxt->eflags = tss->eflags | 2;
2708 2709

	/* General purpose registers */
2710 2711 2712 2713 2714 2715 2716 2717
	*reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
	*reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
	*reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
	*reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
	*reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
	*reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
	*reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
	*reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
2718 2719 2720

	/*
	 * SDM says that segment selectors are loaded before segment
2721 2722
	 * descriptors.  This is important because CPL checks will
	 * use CS.RPL.
2723
	 */
2724 2725 2726 2727 2728 2729 2730
	set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
	set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
	set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2731

2732 2733 2734 2735 2736
	/*
	 * If we're switching between Protected Mode and VM86, we need to make
	 * sure to update the mode before loading the segment descriptors so
	 * that the selectors are interpreted correctly.
	 */
2737
	if (ctxt->eflags & X86_EFLAGS_VM) {
2738
		ctxt->mode = X86EMUL_MODE_VM86;
2739 2740
		cpl = 3;
	} else {
2741
		ctxt->mode = X86EMUL_MODE_PROT32;
2742 2743
		cpl = tss->cs & 3;
	}
2744

2745 2746 2747 2748
	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
2749
	ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2750
					cpl, X86_TRANSFER_TASK_SWITCH, NULL);
2751 2752
	if (ret != X86EMUL_CONTINUE)
		return ret;
2753
	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2754
					X86_TRANSFER_TASK_SWITCH, NULL);
2755 2756
	if (ret != X86EMUL_CONTINUE)
		return ret;
2757
	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2758
					X86_TRANSFER_TASK_SWITCH, NULL);
2759 2760
	if (ret != X86EMUL_CONTINUE)
		return ret;
2761
	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2762
					X86_TRANSFER_TASK_SWITCH, NULL);
2763 2764
	if (ret != X86EMUL_CONTINUE)
		return ret;
2765
	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2766
					X86_TRANSFER_TASK_SWITCH, NULL);
2767 2768
	if (ret != X86EMUL_CONTINUE)
		return ret;
2769
	ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2770
					X86_TRANSFER_TASK_SWITCH, NULL);
2771 2772
	if (ret != X86EMUL_CONTINUE)
		return ret;
2773
	ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2774
					X86_TRANSFER_TASK_SWITCH, NULL);
2775 2776 2777 2778 2779 2780 2781 2782 2783 2784
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_32(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2785
	const struct x86_emulate_ops *ops = ctxt->ops;
2786 2787
	struct tss_segment_32 tss_seg;
	int ret;
2788
	u32 new_tss_base = get_desc_base(new_desc);
2789 2790
	u32 eip_offset = offsetof(struct tss_segment_32, eip);
	u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
2791

2792
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2793
			    &ctxt->exception);
2794
	if (ret != X86EMUL_CONTINUE)
2795 2796
		return ret;

2797
	save_state_to_tss32(ctxt, &tss_seg);
2798

2799 2800 2801
	/* Only GP registers and segment selectors are saved */
	ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
			     ldt_sel_offset - eip_offset, &ctxt->exception);
2802
	if (ret != X86EMUL_CONTINUE)
2803 2804
		return ret;

2805
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2806
			    &ctxt->exception);
2807
	if (ret != X86EMUL_CONTINUE)
2808 2809 2810 2811 2812
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2813
		ret = ops->write_std(ctxt, new_tss_base,
2814 2815
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2816
				     &ctxt->exception);
2817
		if (ret != X86EMUL_CONTINUE)
2818 2819 2820
			return ret;
	}

2821
	return load_state_from_tss32(ctxt, &tss_seg);
2822 2823 2824
}

static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2825
				   u16 tss_selector, int idt_index, int reason,
2826
				   bool has_error_code, u32 error_code)
2827
{
2828
	const struct x86_emulate_ops *ops = ctxt->ops;
2829 2830
	struct desc_struct curr_tss_desc, next_tss_desc;
	int ret;
2831
	u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2832
	ulong old_tss_base =
2833
		ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2834
	u32 desc_limit;
2835
	ulong desc_addr;
2836 2837 2838

	/* FIXME: old_tss_base == ~0 ? */

2839
	ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
2840 2841
	if (ret != X86EMUL_CONTINUE)
		return ret;
2842
	ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
2843 2844 2845 2846 2847
	if (ret != X86EMUL_CONTINUE)
		return ret;

	/* FIXME: check that next_tss_desc is tss */

2848 2849 2850 2851 2852
	/*
	 * Check privileges. The three cases are task switch caused by...
	 *
	 * 1. jmp/call/int to task gate: Check against DPL of the task gate
	 * 2. Exception/IRQ/iret: No check is performed
2853 2854
	 * 3. jmp/call to TSS/task-gate: No check is performed since the
	 *    hardware checks it before exiting.
2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870
	 */
	if (reason == TASK_SWITCH_GATE) {
		if (idt_index != -1) {
			/* Software interrupts */
			struct desc_struct task_gate_desc;
			int dpl;

			ret = read_interrupt_descriptor(ctxt, idt_index,
							&task_gate_desc);
			if (ret != X86EMUL_CONTINUE)
				return ret;

			dpl = task_gate_desc.dpl;
			if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
				return emulate_gp(ctxt, (idt_index << 3) | 0x2);
		}
2871 2872
	}

2873 2874 2875 2876
	desc_limit = desc_limit_scaled(&next_tss_desc);
	if (!next_tss_desc.p ||
	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
	     desc_limit < 0x2b)) {
2877
		return emulate_ts(ctxt, tss_selector & 0xfffc);
2878 2879 2880 2881
	}

	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2882
		write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2883 2884 2885 2886 2887 2888
	}

	if (reason == TASK_SWITCH_IRET)
		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;

	/* set back link to prev task only if NT bit is set in eflags
G
Guo Chao 已提交
2889
	   note that old_tss_sel is not used after this point */
2890 2891 2892 2893
	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
		old_tss_sel = 0xffff;

	if (next_tss_desc.type & 8)
2894
		ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2895 2896
				     old_tss_base, &next_tss_desc);
	else
2897
		ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2898
				     old_tss_base, &next_tss_desc);
2899 2900
	if (ret != X86EMUL_CONTINUE)
		return ret;
2901 2902 2903 2904 2905 2906

	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;

	if (reason != TASK_SWITCH_IRET) {
		next_tss_desc.type |= (1 << 1); /* set busy flag */
2907
		write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2908 2909
	}

2910
	ops->set_cr(ctxt, 0,  ops->get_cr(ctxt, 0) | X86_CR0_TS);
2911
	ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2912

2913
	if (has_error_code) {
2914 2915 2916
		ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
		ctxt->lock_prefix = 0;
		ctxt->src.val = (unsigned long) error_code;
2917
		ret = em_push(ctxt);
2918 2919
	}

2920 2921 2922 2923
	return ret;
}

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2924
			 u16 tss_selector, int idt_index, int reason,
2925
			 bool has_error_code, u32 error_code)
2926 2927 2928
{
	int rc;

2929
	invalidate_registers(ctxt);
2930 2931
	ctxt->_eip = ctxt->eip;
	ctxt->dst.type = OP_NONE;
2932

2933
	rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
2934
				     has_error_code, error_code);
2935

2936
	if (rc == X86EMUL_CONTINUE) {
2937
		ctxt->eip = ctxt->_eip;
2938 2939
		writeback_registers(ctxt);
	}
2940

2941
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2942 2943
}

2944 2945
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
		struct operand *op)
2946
{
2947
	int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
2948

2949 2950
	register_address_increment(ctxt, reg, df * op->bytes);
	op->addr.mem.ea = register_address(ctxt, reg);
2951 2952
}

2953 2954 2955 2956 2957 2958
static int em_das(struct x86_emulate_ctxt *ctxt)
{
	u8 al, old_al;
	bool af, cf, old_cf;

	cf = ctxt->eflags & X86_EFLAGS_CF;
2959
	al = ctxt->dst.val;
2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976

	old_al = al;
	old_cf = cf;
	cf = false;
	af = ctxt->eflags & X86_EFLAGS_AF;
	if ((al & 0x0f) > 9 || af) {
		al -= 6;
		cf = old_cf | (al >= 250);
		af = true;
	} else {
		af = false;
	}
	if (old_al > 0x99 || old_cf) {
		al -= 0x60;
		cf = true;
	}

2977
	ctxt->dst.val = al;
2978
	/* Set PF, ZF, SF */
2979 2980 2981
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
2982
	fastop(ctxt, em_or);
2983 2984 2985 2986 2987 2988 2989 2990
	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
	if (cf)
		ctxt->eflags |= X86_EFLAGS_CF;
	if (af)
		ctxt->eflags |= X86_EFLAGS_AF;
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012
static int em_aam(struct x86_emulate_ctxt *ctxt)
{
	u8 al, ah;

	if (ctxt->src.val == 0)
		return emulate_de(ctxt);

	al = ctxt->dst.val & 0xff;
	ah = al / ctxt->src.val;
	al %= ctxt->src.val;

	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);

	/* Set PF, ZF, SF */
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
	fastop(ctxt, em_or);

	return X86EMUL_CONTINUE;
}

3013 3014 3015 3016 3017 3018 3019 3020 3021
static int em_aad(struct x86_emulate_ctxt *ctxt)
{
	u8 al = ctxt->dst.val & 0xff;
	u8 ah = (ctxt->dst.val >> 8) & 0xff;

	al = (al + (ah * ctxt->src.val)) & 0xff;

	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;

3022 3023 3024 3025 3026
	/* Set PF, ZF, SF */
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
	fastop(ctxt, em_or);
3027 3028 3029 3030

	return X86EMUL_CONTINUE;
}

3031 3032
static int em_call(struct x86_emulate_ctxt *ctxt)
{
3033
	int rc;
3034 3035 3036
	long rel = ctxt->src.val;

	ctxt->src.val = (unsigned long)ctxt->_eip;
3037 3038 3039
	rc = jmp_rel(ctxt, rel);
	if (rc != X86EMUL_CONTINUE)
		return rc;
3040 3041 3042
	return em_push(ctxt);
}

3043 3044 3045 3046 3047
static int em_call_far(struct x86_emulate_ctxt *ctxt)
{
	u16 sel, old_cs;
	ulong old_eip;
	int rc;
3048 3049 3050
	struct desc_struct old_desc, new_desc;
	const struct x86_emulate_ops *ops = ctxt->ops;
	int cpl = ctxt->ops->cpl(ctxt);
3051

3052
	old_eip = ctxt->_eip;
3053
	ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
3054

3055
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3056 3057
	rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
				       X86_TRANSFER_CALL_JMP, &new_desc);
3058
	if (rc != X86EMUL_CONTINUE)
3059
		return rc;
3060

3061
	rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
3062 3063
	if (rc != X86EMUL_CONTINUE)
		goto fail;
3064

3065
	ctxt->src.val = old_cs;
3066
	rc = em_push(ctxt);
3067
	if (rc != X86EMUL_CONTINUE)
3068
		goto fail;
3069

3070
	ctxt->src.val = old_eip;
3071 3072 3073 3074 3075 3076 3077 3078 3079 3080
	rc = em_push(ctxt);
	/* If we failed, we tainted the memory, but the very least we should
	   restore cs */
	if (rc != X86EMUL_CONTINUE)
		goto fail;
	return rc;
fail:
	ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
	return rc;

3081 3082
}

3083 3084 3085
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
{
	int rc;
3086
	unsigned long eip;
3087

3088 3089 3090 3091
	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	rc = assign_eip_near(ctxt, eip);
3092 3093
	if (rc != X86EMUL_CONTINUE)
		return rc;
3094
	rsp_increment(ctxt, ctxt->src.val);
3095 3096 3097
	return X86EMUL_CONTINUE;
}

3098 3099 3100
static int em_xchg(struct x86_emulate_ctxt *ctxt)
{
	/* Write back the register source. */
3101 3102
	ctxt->src.val = ctxt->dst.val;
	write_register_operand(&ctxt->src);
3103 3104

	/* Write back the memory destination with implicit LOCK prefix. */
3105 3106
	ctxt->dst.val = ctxt->src.orig_val;
	ctxt->lock_prefix = 1;
3107 3108 3109
	return X86EMUL_CONTINUE;
}

3110 3111
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
{
3112
	ctxt->dst.val = ctxt->src2.val;
3113
	return fastop(ctxt, em_imul);
3114 3115
}

3116 3117
static int em_cwd(struct x86_emulate_ctxt *ctxt)
{
3118 3119
	ctxt->dst.type = OP_REG;
	ctxt->dst.bytes = ctxt->src.bytes;
3120
	ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3121
	ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3122 3123 3124 3125

	return X86EMUL_CONTINUE;
}

3126 3127 3128 3129
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
{
	u64 tsc = 0;

3130
	ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3131 3132
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
	*reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3133 3134 3135
	return X86EMUL_CONTINUE;
}

3136 3137 3138 3139
static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
{
	u64 pmc;

3140
	if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3141
		return emulate_gp(ctxt, 0);
3142 3143
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
	*reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3144 3145 3146
	return X86EMUL_CONTINUE;
}

3147 3148
static int em_mov(struct x86_emulate_ctxt *ctxt)
{
3149
	memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
3150 3151 3152
	return X86EMUL_CONTINUE;
}

B
Borislav Petkov 已提交
3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187
#define FFL(x) bit(X86_FEATURE_##x)

static int em_movbe(struct x86_emulate_ctxt *ctxt)
{
	u32 ebx, ecx, edx, eax = 1;
	u16 tmp;

	/*
	 * Check MOVBE is set in the guest-visible CPUID leaf.
	 */
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	if (!(ecx & FFL(MOVBE)))
		return emulate_ud(ctxt);

	switch (ctxt->op_bytes) {
	case 2:
		/*
		 * From MOVBE definition: "...When the operand size is 16 bits,
		 * the upper word of the destination register remains unchanged
		 * ..."
		 *
		 * Both casting ->valptr and ->val to u16 breaks strict aliasing
		 * rules so we have to do the operation almost per hand.
		 */
		tmp = (u16)ctxt->src.val;
		ctxt->dst.val &= ~0xffffUL;
		ctxt->dst.val |= (unsigned long)swab16(tmp);
		break;
	case 4:
		ctxt->dst.val = swab32((u32)ctxt->src.val);
		break;
	case 8:
		ctxt->dst.val = swab64(ctxt->src.val);
		break;
	default:
3188
		BUG();
B
Borislav Petkov 已提交
3189 3190 3191 3192
	}
	return X86EMUL_CONTINUE;
}

3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220
static int em_cr_write(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

static int em_dr_write(struct x86_emulate_ctxt *ctxt)
{
	unsigned long val;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		val = ctxt->src.val & ~0ULL;
	else
		val = ctxt->src.val & ~0U;

	/* #UD condition is already handled. */
	if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

3221 3222 3223 3224
static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

3225 3226 3227
	msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
		| ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
	if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3228 3229 3230 3231 3232 3233 3234 3235 3236
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

3237
	if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3238 3239
		return emulate_gp(ctxt, 0);

3240 3241
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
	*reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3242 3243 3244
	return X86EMUL_CONTINUE;
}

3245 3246
static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
{
3247
	if (ctxt->modrm_reg > VCPU_SREG_GS)
3248 3249
		return emulate_ud(ctxt);

3250
	ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
3251 3252
	if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
		ctxt->dst.bytes = 2;
3253 3254 3255 3256 3257
	return X86EMUL_CONTINUE;
}

static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
{
3258
	u16 sel = ctxt->src.val;
3259

3260
	if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3261 3262
		return emulate_ud(ctxt);

3263
	if (ctxt->modrm_reg == VCPU_SREG_SS)
3264 3265 3266
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;

	/* Disable writeback. */
3267 3268
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3269 3270
}

A
Avi Kivity 已提交
3271 3272 3273 3274 3275 3276 3277 3278 3279
static int em_lldt(struct x86_emulate_ctxt *ctxt)
{
	u16 sel = ctxt->src.val;

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
}

A
Avi Kivity 已提交
3280 3281 3282 3283 3284 3285 3286 3287 3288
static int em_ltr(struct x86_emulate_ctxt *ctxt)
{
	u16 sel = ctxt->src.val;

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
}

3289 3290
static int em_invlpg(struct x86_emulate_ctxt *ctxt)
{
3291 3292 3293
	int rc;
	ulong linear;

3294
	rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3295
	if (rc == X86EMUL_CONTINUE)
3296
		ctxt->ops->invlpg(ctxt, linear);
3297
	/* Disable writeback. */
3298
	ctxt->dst.type = OP_NONE;
3299 3300 3301
	return X86EMUL_CONTINUE;
}

3302 3303 3304 3305 3306 3307 3308 3309 3310 3311
static int em_clts(struct x86_emulate_ctxt *ctxt)
{
	ulong cr0;

	cr0 = ctxt->ops->get_cr(ctxt, 0);
	cr0 &= ~X86_CR0_TS;
	ctxt->ops->set_cr(ctxt, 0, cr0);
	return X86EMUL_CONTINUE;
}

3312 3313
static int em_vmcall(struct x86_emulate_ctxt *ctxt)
{
3314
	int rc = ctxt->ops->fix_hypercall(ctxt);
3315 3316 3317 3318 3319

	if (rc != X86EMUL_CONTINUE)
		return rc;

	/* Let the processor re-execute the fixed hypercall */
3320
	ctxt->_eip = ctxt->eip;
3321
	/* Disable writeback. */
3322
	ctxt->dst.type = OP_NONE;
3323 3324 3325
	return X86EMUL_CONTINUE;
}

3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354
static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
				  void (*get)(struct x86_emulate_ctxt *ctxt,
					      struct desc_ptr *ptr))
{
	struct desc_ptr desc_ptr;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
	get(ctxt, &desc_ptr);
	if (ctxt->op_bytes == 2) {
		ctxt->op_bytes = 4;
		desc_ptr.address &= 0x00ffffff;
	}
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return segmented_write(ctxt, ctxt->dst.addr.mem,
			       &desc_ptr, 2 + ctxt->op_bytes);
}

static int em_sgdt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
}

static int em_sidt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
}

3355
static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
3356 3357 3358 3359
{
	struct desc_ptr desc_ptr;
	int rc;

3360 3361
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
3362
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3363
			     &desc_ptr.size, &desc_ptr.address,
3364
			     ctxt->op_bytes);
3365 3366
	if (rc != X86EMUL_CONTINUE)
		return rc;
3367 3368 3369
	if (ctxt->mode == X86EMUL_MODE_PROT64 &&
	    is_noncanonical_address(desc_ptr.address))
		return emulate_gp(ctxt, 0);
3370 3371 3372 3373
	if (lgdt)
		ctxt->ops->set_gdt(ctxt, &desc_ptr);
	else
		ctxt->ops->set_idt(ctxt, &desc_ptr);
3374
	/* Disable writeback. */
3375
	ctxt->dst.type = OP_NONE;
3376 3377 3378
	return X86EMUL_CONTINUE;
}

3379 3380 3381 3382 3383
static int em_lgdt(struct x86_emulate_ctxt *ctxt)
{
	return em_lgdt_lidt(ctxt, true);
}

3384
static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
3385 3386 3387
{
	int rc;

3388 3389
	rc = ctxt->ops->fix_hypercall(ctxt);

3390
	/* Disable writeback. */
3391
	ctxt->dst.type = OP_NONE;
3392 3393 3394 3395 3396
	return rc;
}

static int em_lidt(struct x86_emulate_ctxt *ctxt)
{
3397
	return em_lgdt_lidt(ctxt, false);
3398 3399 3400 3401
}

static int em_smsw(struct x86_emulate_ctxt *ctxt)
{
3402 3403
	if (ctxt->dst.type == OP_MEM)
		ctxt->dst.bytes = 2;
3404
	ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3405 3406 3407 3408 3409 3410
	return X86EMUL_CONTINUE;
}

static int em_lmsw(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3411 3412
			  | (ctxt->src.val & 0x0f));
	ctxt->dst.type = OP_NONE;
3413 3414 3415
	return X86EMUL_CONTINUE;
}

3416 3417
static int em_loop(struct x86_emulate_ctxt *ctxt)
{
3418 3419
	int rc = X86EMUL_CONTINUE;

3420
	register_address_increment(ctxt, VCPU_REGS_RCX, -1);
3421
	if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3422
	    (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3423
		rc = jmp_rel(ctxt, ctxt->src.val);
3424

3425
	return rc;
3426 3427 3428 3429
}

static int em_jcxz(struct x86_emulate_ctxt *ctxt)
{
3430 3431
	int rc = X86EMUL_CONTINUE;

3432
	if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3433
		rc = jmp_rel(ctxt, ctxt->src.val);
3434

3435
	return rc;
3436 3437
}

3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455
static int em_in(struct x86_emulate_ctxt *ctxt)
{
	if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
			     &ctxt->dst.val))
		return X86EMUL_IO_NEEDED;

	return X86EMUL_CONTINUE;
}

static int em_out(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
				    &ctxt->src.val, 1);
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474
static int em_cli(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->eflags &= ~X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

static int em_sti(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
	ctxt->eflags |= X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3475 3476 3477 3478
static int em_cpuid(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

3479 3480
	eax = reg_read(ctxt, VCPU_REGS_RAX);
	ecx = reg_read(ctxt, VCPU_REGS_RCX);
A
Avi Kivity 已提交
3481
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3482 3483 3484 3485
	*reg_write(ctxt, VCPU_REGS_RAX) = eax;
	*reg_write(ctxt, VCPU_REGS_RBX) = ebx;
	*reg_write(ctxt, VCPU_REGS_RCX) = ecx;
	*reg_write(ctxt, VCPU_REGS_RDX) = edx;
A
Avi Kivity 已提交
3486 3487 3488
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500
static int em_sahf(struct x86_emulate_ctxt *ctxt)
{
	u32 flags;

	flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
	flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;

	ctxt->eflags &= ~0xffUL;
	ctxt->eflags |= flags | X86_EFLAGS_FIXED;
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3501 3502
static int em_lahf(struct x86_emulate_ctxt *ctxt)
{
3503 3504
	*reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
	*reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
A
Avi Kivity 已提交
3505 3506 3507
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522
static int em_bswap(struct x86_emulate_ctxt *ctxt)
{
	switch (ctxt->op_bytes) {
#ifdef CONFIG_X86_64
	case 8:
		asm("bswap %0" : "+r"(ctxt->dst.val));
		break;
#endif
	default:
		asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
		break;
	}
	return X86EMUL_CONTINUE;
}

3523 3524 3525 3526 3527 3528
static int em_clflush(struct x86_emulate_ctxt *ctxt)
{
	/* emulating clflush regardless of cpuid */
	return X86EMUL_CONTINUE;
}

3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542
static bool valid_cr(int nr)
{
	switch (nr) {
	case 0:
	case 2 ... 4:
	case 8:
		return true;
	default:
		return false;
	}
}

static int check_cr_read(struct x86_emulate_ctxt *ctxt)
{
3543
	if (!valid_cr(ctxt->modrm_reg))
3544 3545 3546 3547 3548 3549 3550
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_cr_write(struct x86_emulate_ctxt *ctxt)
{
3551 3552
	u64 new_val = ctxt->src.val64;
	int cr = ctxt->modrm_reg;
3553
	u64 efer = 0;
3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570

	static u64 cr_reserved_bits[] = {
		0xffffffff00000000ULL,
		0, 0, 0, /* CR3 checked later */
		CR4_RESERVED_BITS,
		0, 0, 0,
		CR8_RESERVED_BITS,
	};

	if (!valid_cr(cr))
		return emulate_ud(ctxt);

	if (new_val & cr_reserved_bits[cr])
		return emulate_gp(ctxt, 0);

	switch (cr) {
	case 0: {
3571
		u64 cr4;
3572 3573 3574 3575
		if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
		    ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
			return emulate_gp(ctxt, 0);

3576 3577
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3578 3579 3580 3581 3582 3583 3584 3585 3586 3587

		if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
		    !(cr4 & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	case 3: {
		u64 rsvd = 0;

3588 3589
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (efer & EFER_LMA)
N
Nadav Amit 已提交
3590
			rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
3591 3592 3593 3594 3595 3596 3597

		if (new_val & rsvd)
			return emulate_gp(ctxt, 0);

		break;
		}
	case 4: {
3598
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609

		if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	}

	return X86EMUL_CONTINUE;
}

3610 3611 3612 3613
static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
{
	unsigned long dr7;

3614
	ctxt->ops->get_dr(ctxt, 7, &dr7);
3615 3616 3617 3618 3619 3620 3621

	/* Check if DR7.Global_Enable is set */
	return dr7 & (1 << 13);
}

static int check_dr_read(struct x86_emulate_ctxt *ctxt)
{
3622
	int dr = ctxt->modrm_reg;
3623 3624 3625 3626 3627
	u64 cr4;

	if (dr > 7)
		return emulate_ud(ctxt);

3628
	cr4 = ctxt->ops->get_cr(ctxt, 4);
3629 3630 3631
	if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
		return emulate_ud(ctxt);

3632 3633 3634 3635 3636 3637 3638
	if (check_dr7_gd(ctxt)) {
		ulong dr6;

		ctxt->ops->get_dr(ctxt, 6, &dr6);
		dr6 &= ~15;
		dr6 |= DR6_BD | DR6_RTM;
		ctxt->ops->set_dr(ctxt, 6, dr6);
3639
		return emulate_db(ctxt);
3640
	}
3641 3642 3643 3644 3645 3646

	return X86EMUL_CONTINUE;
}

static int check_dr_write(struct x86_emulate_ctxt *ctxt)
{
3647 3648
	u64 new_val = ctxt->src.val64;
	int dr = ctxt->modrm_reg;
3649 3650 3651 3652 3653 3654 3655

	if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
		return emulate_gp(ctxt, 0);

	return check_dr_read(ctxt);
}

3656 3657 3658 3659
static int check_svme(struct x86_emulate_ctxt *ctxt)
{
	u64 efer;

3660
	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3661 3662 3663 3664 3665 3666 3667 3668 3669

	if (!(efer & EFER_SVME))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
{
3670
	u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
3671 3672

	/* Valid physical address? */
3673
	if (rax & 0xffff000000000000ULL)
3674 3675 3676 3677 3678
		return emulate_gp(ctxt, 0);

	return check_svme(ctxt);
}

3679 3680
static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
{
3681
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3682

3683
	if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
3684 3685 3686 3687 3688
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

3689 3690
static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
{
3691
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3692
	u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
3693

3694
	if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
3695
	    ctxt->ops->check_pmc(ctxt, rcx))
3696 3697 3698 3699 3700
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

3701 3702
static int check_perm_in(struct x86_emulate_ctxt *ctxt)
{
3703 3704
	ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
3705 3706 3707 3708 3709 3710 3711
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int check_perm_out(struct x86_emulate_ctxt *ctxt)
{
3712 3713
	ctxt->src.bytes = min(ctxt->src.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
3714 3715 3716 3717 3718
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

3719
#define D(_y) { .flags = (_y) }
3720 3721 3722
#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
		      .intercept = x86_intercept_##_i, .check_perm = (_p) }
3723
#define N    D(NotImpl)
3724
#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3725 3726
#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
3727
#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
3728
#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
3729
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3730
#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
3731
#define II(_f, _e, _i) \
3732
	{ .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
3733
#define IIP(_f, _e, _i, _p) \
3734 3735
	{ .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
	  .intercept = x86_intercept_##_i, .check_perm = (_p) }
3736
#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3737

3738
#define D2bv(_f)      D((_f) | ByteOp), D(_f)
3739
#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3740
#define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)
3741
#define F2bv(_f, _e)  F((_f) | ByteOp, _e), F(_f, _e)
3742 3743
#define I2bvIP(_f, _e, _i, _p) \
	IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
3744

3745 3746 3747
#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e),		\
		F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),	\
		F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3748

3749 3750 3751 3752 3753 3754
static const struct opcode group7_rm0[] = {
	N,
	I(SrcNone | Priv | EmulateOnUD,	em_vmcall),
	N, N, N, N, N, N,
};

3755
static const struct opcode group7_rm1[] = {
3756 3757
	DI(SrcNone | Priv, monitor),
	DI(SrcNone | Priv, mwait),
3758 3759 3760
	N, N, N, N, N, N,
};

3761
static const struct opcode group7_rm3[] = {
3762
	DIP(SrcNone | Prot | Priv,		vmrun,		check_svme_pa),
3763
	II(SrcNone  | Prot | EmulateOnUD,	em_vmmcall,	vmmcall),
3764 3765 3766 3767 3768 3769
	DIP(SrcNone | Prot | Priv,		vmload,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		vmsave,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		stgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		clgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		skinit,		check_svme),
	DIP(SrcNone | Prot | Priv,		invlpga,	check_svme),
3770
};
3771

3772
static const struct opcode group7_rm7[] = {
3773
	N,
3774
	DIP(SrcNone, rdtscp, check_rdtsc),
3775 3776
	N, N, N, N, N, N,
};
3777

3778
static const struct opcode group1[] = {
3779 3780 3781 3782 3783 3784 3785 3786
	F(Lock, em_add),
	F(Lock | PageTable, em_or),
	F(Lock, em_adc),
	F(Lock, em_sbb),
	F(Lock | PageTable, em_and),
	F(Lock, em_sub),
	F(Lock, em_xor),
	F(NoWrite, em_cmp),
3787 3788
};

3789
static const struct opcode group1A[] = {
3790
	I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
3791 3792
};

3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803
static const struct opcode group2[] = {
	F(DstMem | ModRM, em_rol),
	F(DstMem | ModRM, em_ror),
	F(DstMem | ModRM, em_rcl),
	F(DstMem | ModRM, em_rcr),
	F(DstMem | ModRM, em_shl),
	F(DstMem | ModRM, em_shr),
	F(DstMem | ModRM, em_shl),
	F(DstMem | ModRM, em_sar),
};

3804
static const struct opcode group3[] = {
3805 3806
	F(DstMem | SrcImm | NoWrite, em_test),
	F(DstMem | SrcImm | NoWrite, em_test),
3807 3808
	F(DstMem | SrcNone | Lock, em_not),
	F(DstMem | SrcNone | Lock, em_neg),
3809 3810
	F(DstXacc | Src2Mem, em_mul_ex),
	F(DstXacc | Src2Mem, em_imul_ex),
3811 3812
	F(DstXacc | Src2Mem, em_div_ex),
	F(DstXacc | Src2Mem, em_idiv_ex),
3813 3814
};

3815
static const struct opcode group4[] = {
3816 3817
	F(ByteOp | DstMem | SrcNone | Lock, em_inc),
	F(ByteOp | DstMem | SrcNone | Lock, em_dec),
3818 3819 3820
	N, N, N, N, N, N,
};

3821
static const struct opcode group5[] = {
3822 3823
	F(DstMem | SrcNone | Lock,		em_inc),
	F(DstMem | SrcNone | Lock,		em_dec),
3824
	I(SrcMem | NearBranch,			em_call_near_abs),
3825
	I(SrcMemFAddr | ImplicitOps | Stack,	em_call_far),
3826
	I(SrcMem | NearBranch,			em_jmp_abs),
3827 3828
	I(SrcMemFAddr | ImplicitOps,		em_jmp_far),
	I(SrcMem | Stack,			em_push), D(Undefined),
3829 3830
};

3831
static const struct opcode group6[] = {
3832 3833
	DI(Prot,	sldt),
	DI(Prot,	str),
A
Avi Kivity 已提交
3834
	II(Prot | Priv | SrcMem16, em_lldt, lldt),
A
Avi Kivity 已提交
3835
	II(Prot | Priv | SrcMem16, em_ltr, ltr),
3836 3837 3838
	N, N, N, N,
};

3839
static const struct group_dual group7 = { {
3840 3841
	II(Mov | DstMem,			em_sgdt, sgdt),
	II(Mov | DstMem,			em_sidt, sidt),
3842 3843 3844 3845 3846
	II(SrcMem | Priv,			em_lgdt, lgdt),
	II(SrcMem | Priv,			em_lidt, lidt),
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	II(SrcMem | ByteOp | Priv | NoAccess,	em_invlpg, invlpg),
3847
}, {
3848
	EXT(0, group7_rm0),
3849
	EXT(0, group7_rm1),
3850
	N, EXT(0, group7_rm3),
3851 3852 3853
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	EXT(0, group7_rm7),
3854 3855
} };

3856
static const struct opcode group8[] = {
3857
	N, N, N, N,
3858 3859 3860 3861
	F(DstMem | SrcImmByte | NoWrite,		em_bt),
	F(DstMem | SrcImmByte | Lock | PageTable,	em_bts),
	F(DstMem | SrcImmByte | Lock,			em_btr),
	F(DstMem | SrcImmByte | Lock | PageTable,	em_btc),
3862 3863
};

3864
static const struct group_dual group9 = { {
3865
	N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
3866 3867 3868 3869
}, {
	N, N, N, N, N, N, N, N,
} };

3870
static const struct opcode group11[] = {
3871
	I(DstMem | SrcImm | Mov | PageTable, em_mov),
3872
	X7(D(Undefined)),
3873 3874
};

3875
static const struct gprefix pfx_0f_ae_7 = {
3876
	I(SrcMem | ByteOp, em_clflush), N, N, N,
3877 3878 3879 3880 3881 3882 3883 3884
};

static const struct group_dual group15 = { {
	N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
}, {
	N, N, N, N, N, N, N, N,
} };

3885
static const struct gprefix pfx_0f_6f_0f_7f = {
3886
	I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
3887 3888
};

3889 3890 3891 3892
static const struct instr_dual instr_dual_0f_2b = {
	I(0, em_mov), N
};

3893
static const struct gprefix pfx_0f_2b = {
3894
	ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3895 3896
};

3897
static const struct gprefix pfx_0f_28_0f_29 = {
3898
	I(Aligned, em_mov), I(Aligned, em_mov), N, N,
3899 3900
};

3901 3902 3903 3904
static const struct gprefix pfx_0f_e7 = {
	N, I(Sse, em_mov), N, N,
};

3905
static const struct escape escape_d9 = { {
3906
	N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, N, N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

static const struct escape escape_db = { {
	N, N, N, N, N, N, N, N,
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

static const struct escape escape_dd = { {
3948
	N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, N, N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

3968 3969 3970 3971
static const struct instr_dual instr_dual_0f_c3 = {
	I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
};

3972
static const struct opcode opcode_table[256] = {
3973
	/* 0x00 - 0x07 */
3974
	F6ALU(Lock, em_add),
3975 3976
	I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
3977
	/* 0x08 - 0x0F */
3978
	F6ALU(Lock | PageTable, em_or),
3979 3980
	I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
	N,
3981
	/* 0x10 - 0x17 */
3982
	F6ALU(Lock, em_adc),
3983 3984
	I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
3985
	/* 0x18 - 0x1F */
3986
	F6ALU(Lock, em_sbb),
3987 3988
	I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
3989
	/* 0x20 - 0x27 */
3990
	F6ALU(Lock | PageTable, em_and), N, N,
3991
	/* 0x28 - 0x2F */
3992
	F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3993
	/* 0x30 - 0x37 */
3994
	F6ALU(Lock, em_xor), N, N,
3995
	/* 0x38 - 0x3F */
3996
	F6ALU(NoWrite, em_cmp), N, N,
3997
	/* 0x40 - 0x4F */
3998
	X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
3999
	/* 0x50 - 0x57 */
4000
	X8(I(SrcReg | Stack, em_push)),
4001
	/* 0x58 - 0x5F */
4002
	X8(I(DstReg | Stack, em_pop)),
4003
	/* 0x60 - 0x67 */
4004 4005
	I(ImplicitOps | Stack | No64, em_pusha),
	I(ImplicitOps | Stack | No64, em_popa),
4006 4007 4008
	N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
	N, N, N, N,
	/* 0x68 - 0x6F */
4009 4010
	I(SrcImm | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
4011 4012
	I(SrcImmByte | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
4013
	I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
4014
	I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
4015
	/* 0x70 - 0x7F */
4016
	X16(D(SrcImmByte | NearBranch)),
4017
	/* 0x80 - 0x87 */
4018 4019 4020 4021
	G(ByteOp | DstMem | SrcImm, group1),
	G(DstMem | SrcImm, group1),
	G(ByteOp | DstMem | SrcImm | No64, group1),
	G(DstMem | SrcImmByte, group1),
4022
	F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
4023
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
4024
	/* 0x88 - 0x8F */
4025
	I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
4026
	I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
4027
	I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
4028 4029 4030
	D(ModRM | SrcMem | NoAccess | DstReg),
	I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
	G(0, group1A),
4031
	/* 0x90 - 0x97 */
4032
	DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
4033
	/* 0x98 - 0x9F */
4034
	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
4035
	I(SrcImmFAddr | No64, em_call_far), N,
4036
	II(ImplicitOps | Stack, em_pushf, pushf),
P
Paolo Bonzini 已提交
4037 4038
	II(ImplicitOps | Stack, em_popf, popf),
	I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
4039
	/* 0xA0 - 0xA7 */
4040
	I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
4041
	I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
4042
	I2bv(SrcSI | DstDI | Mov | String, em_mov),
4043
	F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
4044
	/* 0xA8 - 0xAF */
4045
	F2bv(DstAcc | SrcImm | NoWrite, em_test),
4046 4047
	I2bv(SrcAcc | DstDI | Mov | String, em_mov),
	I2bv(SrcSI | DstAcc | Mov | String, em_mov),
4048
	F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
4049
	/* 0xB0 - 0xB7 */
4050
	X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
4051
	/* 0xB8 - 0xBF */
4052
	X8(I(DstReg | SrcImm64 | Mov, em_mov)),
4053
	/* 0xC0 - 0xC7 */
4054
	G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
4055 4056
	I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
	I(ImplicitOps | NearBranch, em_ret),
4057 4058
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
4059
	G(ByteOp, group11), G(0, group11),
4060
	/* 0xC8 - 0xCF */
A
Avi Kivity 已提交
4061
	I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
4062 4063
	I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
	I(ImplicitOps | Stack, em_ret_far),
4064
	D(ImplicitOps), DI(SrcImmByte, intn),
4065
	D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
4066
	/* 0xD0 - 0xD7 */
4067 4068
	G(Src2One | ByteOp, group2), G(Src2One, group2),
	G(Src2CL | ByteOp, group2), G(Src2CL, group2),
P
Paolo Bonzini 已提交
4069
	I(DstAcc | SrcImmUByte | No64, em_aam),
P
Paolo Bonzini 已提交
4070 4071
	I(DstAcc | SrcImmUByte | No64, em_aad),
	F(DstAcc | ByteOp | No64, em_salc),
P
Paolo Bonzini 已提交
4072
	I(DstAcc | SrcXLat | ByteOp, em_mov),
4073
	/* 0xD8 - 0xDF */
4074
	N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
4075
	/* 0xE0 - 0xE7 */
4076 4077
	X3(I(SrcImmByte | NearBranch, em_loop)),
	I(SrcImmByte | NearBranch, em_jcxz),
4078 4079
	I2bvIP(SrcImmUByte | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
4080
	/* 0xE8 - 0xEF */
4081 4082 4083
	I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
	I(SrcImmFAddr | No64, em_jmp_far),
	D(SrcImmByte | ImplicitOps | NearBranch),
4084 4085
	I2bvIP(SrcDX | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
4086
	/* 0xF0 - 0xF7 */
4087
	N, DI(ImplicitOps, icebp), N, N,
4088 4089
	DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
	G(ByteOp, group3), G(0, group3),
4090
	/* 0xF8 - 0xFF */
4091 4092
	D(ImplicitOps), D(ImplicitOps),
	I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
4093 4094 4095
	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
};

4096
static const struct opcode twobyte_table[256] = {
4097
	/* 0x00 - 0x0F */
4098
	G(0, group6), GD(0, &group7), N, N,
4099
	N, I(ImplicitOps | EmulateOnUD, em_syscall),
4100
	II(ImplicitOps | Priv, em_clts, clts), N,
4101
	DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
4102
	N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4103
	/* 0x10 - 0x1F */
P
Paolo Bonzini 已提交
4104
	N, N, N, N, N, N, N, N,
4105 4106
	D(ImplicitOps | ModRM | SrcMem | NoAccess),
	N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
4107
	/* 0x20 - 0x2F */
4108 4109 4110 4111 4112 4113
	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
						check_cr_write),
	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
						check_dr_write),
4114
	N, N, N, N,
4115 4116
	GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
	GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
4117
	N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
4118
	N, N, N, N,
4119
	/* 0x30 - 0x3F */
4120
	II(ImplicitOps | Priv, em_wrmsr, wrmsr),
4121
	IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
4122
	II(ImplicitOps | Priv, em_rdmsr, rdmsr),
4123
	IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
4124 4125
	I(ImplicitOps | EmulateOnUD, em_sysenter),
	I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
4126
	N, N,
4127 4128
	N, N, N, N, N, N, N, N,
	/* 0x40 - 0x4F */
4129
	X16(D(DstReg | SrcMem | ModRM)),
4130 4131 4132
	/* 0x50 - 0x5F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x60 - 0x6F */
4133 4134 4135 4136
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
4137
	/* 0x70 - 0x7F */
4138 4139 4140 4141
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
4142
	/* 0x80 - 0x8F */
4143
	X16(D(SrcImm | NearBranch)),
4144
	/* 0x90 - 0x9F */
4145
	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
4146
	/* 0xA0 - 0xA7 */
4147
	I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
4148 4149
	II(ImplicitOps, em_cpuid, cpuid),
	F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
4150 4151
	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
	F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
4152
	/* 0xA8 - 0xAF */
4153
	I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
4154
	DI(ImplicitOps, rsm),
4155
	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
4156 4157
	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
	F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4158
	GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
4159
	/* 0xB0 - 0xB7 */
4160
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
4161
	I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
4162
	F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
4163 4164
	I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
4165
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4166 4167
	/* 0xB8 - 0xBF */
	N, N,
4168
	G(BitOp, group8),
4169 4170
	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
	F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
4171
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
A
Avi Kivity 已提交
4172
	/* 0xC0 - 0xC7 */
4173
	F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
4174
	N, ID(0, &instr_dual_0f_c3),
4175
	N, N, N, GD(0, &group9),
A
Avi Kivity 已提交
4176 4177
	/* 0xC8 - 0xCF */
	X8(I(DstReg, em_bswap)),
4178 4179 4180
	/* 0xD0 - 0xDF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xEF */
4181 4182
	N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
	N, N, N, N, N, N, N, N,
4183 4184 4185 4186
	/* 0xF0 - 0xFF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
};

4187 4188 4189 4190 4191 4192 4193 4194
static const struct instr_dual instr_dual_0f_38_f0 = {
	I(DstReg | SrcMem | Mov, em_movbe), N
};

static const struct instr_dual instr_dual_0f_38_f1 = {
	I(DstMem | SrcReg | Mov, em_movbe), N
};

4195
static const struct gprefix three_byte_0f_38_f0 = {
4196
	ID(0, &instr_dual_0f_38_f0), N, N, N
4197 4198 4199
};

static const struct gprefix three_byte_0f_38_f1 = {
4200
	ID(0, &instr_dual_0f_38_f1), N, N, N
4201 4202 4203 4204 4205 4206 4207 4208 4209
};

/*
 * Insns below are selected by the prefix which indexed by the third opcode
 * byte.
 */
static const struct opcode opcode_map_0f_38[256] = {
	/* 0x00 - 0x7f */
	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
B
Borislav Petkov 已提交
4210 4211 4212
	/* 0x80 - 0xef */
	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
	/* 0xf0 - 0xf1 */
4213 4214
	GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
	GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
B
Borislav Petkov 已提交
4215 4216
	/* 0xf2 - 0xff */
	N, N, X4(N), X8(N)
4217 4218
};

4219 4220 4221 4222 4223
#undef D
#undef N
#undef G
#undef GD
#undef I
4224
#undef GP
4225
#undef EXT
4226

4227
#undef D2bv
4228
#undef D2bvIP
4229
#undef I2bv
4230
#undef I2bvIP
4231
#undef I6ALU
4232

4233
static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4234 4235 4236
{
	unsigned size;

4237
	size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249
	if (size == 8)
		size = 4;
	return size;
}

static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
		      unsigned size, bool sign_extension)
{
	int rc = X86EMUL_CONTINUE;

	op->type = OP_IMM;
	op->bytes = size;
4250
	op->addr.mem.ea = ctxt->_eip;
4251 4252 4253
	/* NB. Immediates are sign-extended as necessary. */
	switch (op->bytes) {
	case 1:
4254
		op->val = insn_fetch(s8, ctxt);
4255 4256
		break;
	case 2:
4257
		op->val = insn_fetch(s16, ctxt);
4258 4259
		break;
	case 4:
4260
		op->val = insn_fetch(s32, ctxt);
4261
		break;
4262 4263 4264
	case 8:
		op->val = insn_fetch(s64, ctxt);
		break;
4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282
	}
	if (!sign_extension) {
		switch (op->bytes) {
		case 1:
			op->val &= 0xff;
			break;
		case 2:
			op->val &= 0xffff;
			break;
		case 4:
			op->val &= 0xffffffff;
			break;
		}
	}
done:
	return rc;
}

4283 4284 4285 4286 4287 4288 4289
static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
			  unsigned d)
{
	int rc = X86EMUL_CONTINUE;

	switch (d) {
	case OpReg:
4290
		decode_register_operand(ctxt, op);
4291 4292
		break;
	case OpImmUByte:
4293
		rc = decode_imm(ctxt, op, 1, false);
4294 4295
		break;
	case OpMem:
4296
		ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4297 4298 4299
	mem_common:
		*op = ctxt->memop;
		ctxt->memopp = op;
4300
		if (ctxt->d & BitOp)
4301 4302 4303
			fetch_bit_operand(ctxt);
		op->orig_val = op->val;
		break;
4304
	case OpMem64:
4305
		ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
4306
		goto mem_common;
4307 4308 4309
	case OpAcc:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4310
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4311 4312 4313
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331
	case OpAccLo:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
	case OpAccHi:
		if (ctxt->d & ByteOp) {
			op->type = OP_NONE;
			break;
		}
		op->type = OP_REG;
		op->bytes = ctxt->op_bytes;
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
4332 4333 4334 4335
	case OpDI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
4336
			register_address(ctxt, VCPU_REGS_RDI);
4337 4338
		op->addr.mem.seg = VCPU_SREG_ES;
		op->val = 0;
4339
		op->count = 1;
4340 4341 4342 4343
		break;
	case OpDX:
		op->type = OP_REG;
		op->bytes = 2;
4344
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4345 4346
		fetch_register_operand(op);
		break;
4347
	case OpCL:
4348
		op->type = OP_IMM;
4349
		op->bytes = 1;
4350
		op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4351 4352 4353 4354 4355
		break;
	case OpImmByte:
		rc = decode_imm(ctxt, op, 1, true);
		break;
	case OpOne:
4356
		op->type = OP_IMM;
4357 4358 4359 4360 4361 4362
		op->bytes = 1;
		op->val = 1;
		break;
	case OpImm:
		rc = decode_imm(ctxt, op, imm_size(ctxt), true);
		break;
4363 4364 4365
	case OpImm64:
		rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
		break;
4366 4367
	case OpMem8:
		ctxt->memop.bytes = 1;
4368
		if (ctxt->memop.type == OP_REG) {
4369 4370
			ctxt->memop.addr.reg = decode_register(ctxt,
					ctxt->modrm_rm, true);
4371 4372
			fetch_register_operand(&ctxt->memop);
		}
4373
		goto mem_common;
4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389
	case OpMem16:
		ctxt->memop.bytes = 2;
		goto mem_common;
	case OpMem32:
		ctxt->memop.bytes = 4;
		goto mem_common;
	case OpImmU16:
		rc = decode_imm(ctxt, op, 2, false);
		break;
	case OpImmU:
		rc = decode_imm(ctxt, op, imm_size(ctxt), false);
		break;
	case OpSI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
4390
			register_address(ctxt, VCPU_REGS_RSI);
B
Bandan Das 已提交
4391
		op->addr.mem.seg = ctxt->seg_override;
4392
		op->val = 0;
4393
		op->count = 1;
4394
		break;
P
Paolo Bonzini 已提交
4395 4396 4397 4398
	case OpXLat:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
4399
			address_mask(ctxt,
P
Paolo Bonzini 已提交
4400 4401
				reg_read(ctxt, VCPU_REGS_RBX) +
				(reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
B
Bandan Das 已提交
4402
		op->addr.mem.seg = ctxt->seg_override;
P
Paolo Bonzini 已提交
4403 4404
		op->val = 0;
		break;
4405 4406 4407 4408 4409 4410 4411 4412 4413
	case OpImmFAddr:
		op->type = OP_IMM;
		op->addr.mem.ea = ctxt->_eip;
		op->bytes = ctxt->op_bytes + 2;
		insn_fetch_arr(op->valptr, op->bytes, ctxt);
		break;
	case OpMemFAddr:
		ctxt->memop.bytes = ctxt->op_bytes + 2;
		goto mem_common;
4414
	case OpES:
4415
		op->type = OP_IMM;
4416 4417 4418
		op->val = VCPU_SREG_ES;
		break;
	case OpCS:
4419
		op->type = OP_IMM;
4420 4421 4422
		op->val = VCPU_SREG_CS;
		break;
	case OpSS:
4423
		op->type = OP_IMM;
4424 4425 4426
		op->val = VCPU_SREG_SS;
		break;
	case OpDS:
4427
		op->type = OP_IMM;
4428 4429 4430
		op->val = VCPU_SREG_DS;
		break;
	case OpFS:
4431
		op->type = OP_IMM;
4432 4433 4434
		op->val = VCPU_SREG_FS;
		break;
	case OpGS:
4435
		op->type = OP_IMM;
4436 4437
		op->val = VCPU_SREG_GS;
		break;
4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448
	case OpImplicit:
		/* Special instructions do their own operand decoding. */
	default:
		op->type = OP_NONE; /* Disable writeback. */
		break;
	}

done:
	return rc;
}

4449
int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
4450 4451 4452
{
	int rc = X86EMUL_CONTINUE;
	int mode = ctxt->mode;
4453
	int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
4454
	bool op_prefix = false;
B
Bandan Das 已提交
4455
	bool has_seg_override = false;
4456
	struct opcode opcode;
4457

4458 4459
	ctxt->memop.type = OP_NONE;
	ctxt->memopp = NULL;
4460
	ctxt->_eip = ctxt->eip;
4461 4462
	ctxt->fetch.ptr = ctxt->fetch.data;
	ctxt->fetch.end = ctxt->fetch.data + insn_len;
B
Borislav Petkov 已提交
4463
	ctxt->opcode_len = 1;
4464
	if (insn_len > 0)
4465
		memcpy(ctxt->fetch.data, insn, insn_len);
4466
	else {
4467
		rc = __do_insn_fetch_bytes(ctxt, 1);
4468 4469 4470
		if (rc != X86EMUL_CONTINUE)
			return rc;
	}
4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487

	switch (mode) {
	case X86EMUL_MODE_REAL:
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
		def_op_bytes = def_ad_bytes = 2;
		break;
	case X86EMUL_MODE_PROT32:
		def_op_bytes = def_ad_bytes = 4;
		break;
#ifdef CONFIG_X86_64
	case X86EMUL_MODE_PROT64:
		def_op_bytes = 4;
		def_ad_bytes = 8;
		break;
#endif
	default:
4488
		return EMULATION_FAILED;
4489 4490
	}

4491 4492
	ctxt->op_bytes = def_op_bytes;
	ctxt->ad_bytes = def_ad_bytes;
4493 4494 4495

	/* Legacy prefixes. */
	for (;;) {
4496
		switch (ctxt->b = insn_fetch(u8, ctxt)) {
4497
		case 0x66:	/* operand-size override */
4498
			op_prefix = true;
4499
			/* switch between 2/4 bytes */
4500
			ctxt->op_bytes = def_op_bytes ^ 6;
4501 4502 4503 4504
			break;
		case 0x67:	/* address-size override */
			if (mode == X86EMUL_MODE_PROT64)
				/* switch between 4/8 bytes */
4505
				ctxt->ad_bytes = def_ad_bytes ^ 12;
4506 4507
			else
				/* switch between 2/4 bytes */
4508
				ctxt->ad_bytes = def_ad_bytes ^ 6;
4509 4510 4511 4512 4513
			break;
		case 0x26:	/* ES override */
		case 0x2e:	/* CS override */
		case 0x36:	/* SS override */
		case 0x3e:	/* DS override */
B
Bandan Das 已提交
4514 4515
			has_seg_override = true;
			ctxt->seg_override = (ctxt->b >> 3) & 3;
4516 4517 4518
			break;
		case 0x64:	/* FS override */
		case 0x65:	/* GS override */
B
Bandan Das 已提交
4519 4520
			has_seg_override = true;
			ctxt->seg_override = ctxt->b & 7;
4521 4522 4523 4524
			break;
		case 0x40 ... 0x4f: /* REX */
			if (mode != X86EMUL_MODE_PROT64)
				goto done_prefixes;
4525
			ctxt->rex_prefix = ctxt->b;
4526 4527
			continue;
		case 0xf0:	/* LOCK */
4528
			ctxt->lock_prefix = 1;
4529 4530 4531
			break;
		case 0xf2:	/* REPNE/REPNZ */
		case 0xf3:	/* REP/REPE/REPZ */
4532
			ctxt->rep_prefix = ctxt->b;
4533 4534 4535 4536 4537 4538 4539
			break;
		default:
			goto done_prefixes;
		}

		/* Any legacy prefix after a REX prefix nullifies its effect. */

4540
		ctxt->rex_prefix = 0;
4541 4542 4543 4544 4545
	}

done_prefixes:

	/* REX prefix. */
4546 4547
	if (ctxt->rex_prefix & 8)
		ctxt->op_bytes = 8;	/* REX.W */
4548 4549

	/* Opcode byte(s). */
4550
	opcode = opcode_table[ctxt->b];
4551
	/* Two-byte opcode? */
4552
	if (ctxt->b == 0x0f) {
B
Borislav Petkov 已提交
4553
		ctxt->opcode_len = 2;
4554
		ctxt->b = insn_fetch(u8, ctxt);
4555
		opcode = twobyte_table[ctxt->b];
4556 4557 4558 4559 4560 4561 4562

		/* 0F_38 opcode map */
		if (ctxt->b == 0x38) {
			ctxt->opcode_len = 3;
			ctxt->b = insn_fetch(u8, ctxt);
			opcode = opcode_map_0f_38[ctxt->b];
		}
4563
	}
4564
	ctxt->d = opcode.flags;
4565

4566 4567 4568
	if (ctxt->d & ModRM)
		ctxt->modrm = insn_fetch(u8, ctxt);

4569 4570
	/* vex-prefix instructions are not implemented */
	if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4571
	    (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
4572 4573 4574
		ctxt->d = NotImpl;
	}

4575 4576
	while (ctxt->d & GroupMask) {
		switch (ctxt->d & GroupMask) {
4577
		case Group:
4578
			goffset = (ctxt->modrm >> 3) & 7;
4579 4580 4581
			opcode = opcode.u.group[goffset];
			break;
		case GroupDual:
4582 4583
			goffset = (ctxt->modrm >> 3) & 7;
			if ((ctxt->modrm >> 6) == 3)
4584 4585 4586 4587 4588
				opcode = opcode.u.gdual->mod3[goffset];
			else
				opcode = opcode.u.gdual->mod012[goffset];
			break;
		case RMExt:
4589
			goffset = ctxt->modrm & 7;
4590
			opcode = opcode.u.group[goffset];
4591 4592
			break;
		case Prefix:
4593
			if (ctxt->rep_prefix && op_prefix)
4594
				return EMULATION_FAILED;
4595
			simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
4596 4597 4598 4599 4600 4601 4602
			switch (simd_prefix) {
			case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
			case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
			case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
			case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
			}
			break;
4603 4604 4605 4606 4607 4608
		case Escape:
			if (ctxt->modrm > 0xbf)
				opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
			else
				opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
			break;
4609 4610 4611 4612 4613 4614
		case InstrDual:
			if ((ctxt->modrm >> 6) == 3)
				opcode = opcode.u.idual->mod3;
			else
				opcode = opcode.u.idual->mod012;
			break;
4615
		default:
4616
			return EMULATION_FAILED;
4617
		}
4618

4619
		ctxt->d &= ~(u64)GroupMask;
4620
		ctxt->d |= opcode.flags;
4621 4622
	}

4623 4624 4625 4626
	/* Unrecognised? */
	if (ctxt->d == 0)
		return EMULATION_FAILED;

4627
	ctxt->execute = opcode.u.execute;
4628

4629 4630 4631
	if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
		return EMULATION_FAILED;

4632
	if (unlikely(ctxt->d &
4633 4634
	    (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
	     No16))) {
4635 4636 4637 4638 4639 4640
		/*
		 * These are copied unconditionally here, and checked unconditionally
		 * in x86_emulate_insn.
		 */
		ctxt->check_perm = opcode.check_perm;
		ctxt->intercept = opcode.intercept;
4641

4642 4643
		if (ctxt->d & NotImpl)
			return EMULATION_FAILED;
4644

4645 4646 4647 4648 4649 4650
		if (mode == X86EMUL_MODE_PROT64) {
			if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
				ctxt->op_bytes = 8;
			else if (ctxt->d & NearBranch)
				ctxt->op_bytes = 8;
		}
4651

4652 4653 4654 4655 4656 4657 4658
		if (ctxt->d & Op3264) {
			if (mode == X86EMUL_MODE_PROT64)
				ctxt->op_bytes = 8;
			else
				ctxt->op_bytes = 4;
		}

4659 4660 4661
		if ((ctxt->d & No16) && ctxt->op_bytes == 2)
			ctxt->op_bytes = 4;

4662 4663 4664 4665 4666
		if (ctxt->d & Sse)
			ctxt->op_bytes = 16;
		else if (ctxt->d & Mmx)
			ctxt->op_bytes = 8;
	}
A
Avi Kivity 已提交
4667

4668
	/* ModRM and SIB bytes. */
4669
	if (ctxt->d & ModRM) {
4670
		rc = decode_modrm(ctxt, &ctxt->memop);
B
Bandan Das 已提交
4671 4672 4673 4674
		if (!has_seg_override) {
			has_seg_override = true;
			ctxt->seg_override = ctxt->modrm_seg;
		}
4675
	} else if (ctxt->d & MemAbs)
4676
		rc = decode_abs(ctxt, &ctxt->memop);
4677 4678 4679
	if (rc != X86EMUL_CONTINUE)
		goto done;

B
Bandan Das 已提交
4680 4681
	if (!has_seg_override)
		ctxt->seg_override = VCPU_SREG_DS;
4682

B
Bandan Das 已提交
4683
	ctxt->memop.addr.mem.seg = ctxt->seg_override;
4684 4685 4686 4687 4688

	/*
	 * Decode and fetch the source operand: register, memory
	 * or immediate.
	 */
4689
	rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
4690 4691 4692
	if (rc != X86EMUL_CONTINUE)
		goto done;

4693 4694 4695 4696
	/*
	 * Decode and fetch the second source operand: register, memory
	 * or immediate.
	 */
4697
	rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
4698 4699 4700
	if (rc != X86EMUL_CONTINUE)
		goto done;

4701
	/* Decode and fetch the destination operand: register or memory. */
4702
	rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
4703

4704
	if (ctxt->rip_relative)
4705 4706
		ctxt->memopp->addr.mem.ea = address_mask(ctxt,
					ctxt->memopp->addr.mem.ea + ctxt->_eip);
4707

4708
done:
4709
	return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
4710 4711
}

4712 4713 4714 4715 4716
bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
{
	return ctxt->d & PageTable;
}

4717 4718 4719 4720 4721 4722 4723 4724 4725
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
{
	/* The second termination condition only applies for REPE
	 * and REPNE. Test if the repeat string operation prefix is
	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
	 * corresponding termination condition according to:
	 * 	- if REPE/REPZ and ZF = 0 then done
	 * 	- if REPNE/REPNZ and ZF = 1 then done
	 */
4726 4727 4728
	if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
	     (ctxt->b == 0xae) || (ctxt->b == 0xaf))
	    && (((ctxt->rep_prefix == REPE_PREFIX) &&
4729
		 ((ctxt->eflags & EFLG_ZF) == 0))
4730
		|| ((ctxt->rep_prefix == REPNE_PREFIX) &&
4731 4732 4733 4734 4735 4736
		    ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
		return true;

	return false;
}

A
Avi Kivity 已提交
4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749
static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
{
	bool fault = false;

	ctxt->ops->get_fpu(ctxt);
	asm volatile("1: fwait \n\t"
		     "2: \n\t"
		     ".pushsection .fixup,\"ax\" \n\t"
		     "3: \n\t"
		     "movb $1, %[fault] \n\t"
		     "jmp 2b \n\t"
		     ".popsection \n\t"
		     _ASM_EXTABLE(1b, 3b)
4750
		     : [fault]"+qm"(fault));
A
Avi Kivity 已提交
4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765
	ctxt->ops->put_fpu(ctxt);

	if (unlikely(fault))
		return emulate_exception(ctxt, MF_VECTOR, 0, false);

	return X86EMUL_CONTINUE;
}

static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
				       struct operand *op)
{
	if (op->type == OP_MM)
		read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
}

4766 4767 4768
static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
{
	ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4769 4770
	if (!(ctxt->d & ByteOp))
		fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4771
	asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4772 4773 4774
	    : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
	      [fastop]"+S"(fop)
	    : "c"(ctxt->src2.val));
4775
	ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4776 4777
	if (!fop) /* exception is returned in fop variable */
		return emulate_de(ctxt);
4778 4779
	return X86EMUL_CONTINUE;
}
4780

4781 4782
void init_decode_cache(struct x86_emulate_ctxt *ctxt)
{
B
Bandan Das 已提交
4783 4784
	memset(&ctxt->rip_relative, 0,
	       (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
4785 4786 4787 4788 4789 4790

	ctxt->io_read.pos = 0;
	ctxt->io_read.end = 0;
	ctxt->mem_read.end = 0;
}

4791
int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
4792
{
4793
	const struct x86_emulate_ops *ops = ctxt->ops;
4794
	int rc = X86EMUL_CONTINUE;
4795
	int saved_dst_type = ctxt->dst.type;
4796

4797
	ctxt->mem_read.pos = 0;
4798

4799 4800
	/* LOCK prefix is allowed only with some instructions */
	if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
4801
		rc = emulate_ud(ctxt);
4802 4803 4804
		goto done;
	}

4805
	if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
4806
		rc = emulate_ud(ctxt);
4807 4808 4809
		goto done;
	}

4810 4811 4812 4813 4814 4815 4816
	if (unlikely(ctxt->d &
		     (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
		if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
				(ctxt->d & Undefined)) {
			rc = emulate_ud(ctxt);
			goto done;
		}
A
Avi Kivity 已提交
4817

4818 4819 4820
		if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
		    || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
			rc = emulate_ud(ctxt);
A
Avi Kivity 已提交
4821
			goto done;
4822
		}
A
Avi Kivity 已提交
4823

4824 4825
		if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
			rc = emulate_nm(ctxt);
4826
			goto done;
4827
		}
4828

4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841
		if (ctxt->d & Mmx) {
			rc = flush_pending_x87_faults(ctxt);
			if (rc != X86EMUL_CONTINUE)
				goto done;
			/*
			 * Now that we know the fpu is exception safe, we can fetch
			 * operands from it.
			 */
			fetch_possible_mmx_operand(ctxt, &ctxt->src);
			fetch_possible_mmx_operand(ctxt, &ctxt->src2);
			if (!(ctxt->d & Mov))
				fetch_possible_mmx_operand(ctxt, &ctxt->dst);
		}
4842

4843
		if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4844 4845 4846 4847 4848
			rc = emulator_check_intercept(ctxt, ctxt->intercept,
						      X86_ICPT_PRE_EXCEPT);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}
4849

4850 4851 4852 4853 4854 4855
		/* Instruction can only be executed in protected mode */
		if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
			rc = emulate_ud(ctxt);
			goto done;
		}

4856 4857
		/* Privileged instruction can be executed only in CPL=0 */
		if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4858 4859 4860 4861
			if (ctxt->d & PrivUD)
				rc = emulate_ud(ctxt);
			else
				rc = emulate_gp(ctxt, 0);
4862
			goto done;
4863
		}
4864

4865
		/* Do instruction specific permission checks */
4866
		if (ctxt->d & CheckPerm) {
4867 4868 4869 4870 4871
			rc = ctxt->check_perm(ctxt);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}

4872
		if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4873 4874 4875 4876 4877 4878 4879 4880 4881 4882
			rc = emulator_check_intercept(ctxt, ctxt->intercept,
						      X86_ICPT_POST_EXCEPT);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}

		if (ctxt->rep_prefix && (ctxt->d & String)) {
			/* All REP prefixes have the same first termination condition */
			if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
				ctxt->eip = ctxt->_eip;
4883
				ctxt->eflags &= ~EFLG_RF;
4884 4885
				goto done;
			}
4886 4887 4888
		}
	}

4889 4890 4891
	if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
		rc = segmented_read(ctxt, ctxt->src.addr.mem,
				    ctxt->src.valptr, ctxt->src.bytes);
4892
		if (rc != X86EMUL_CONTINUE)
4893
			goto done;
4894
		ctxt->src.orig_val64 = ctxt->src.val64;
4895 4896
	}

4897 4898 4899
	if (ctxt->src2.type == OP_MEM) {
		rc = segmented_read(ctxt, ctxt->src2.addr.mem,
				    &ctxt->src2.val, ctxt->src2.bytes);
4900 4901 4902 4903
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

4904
	if ((ctxt->d & DstMask) == ImplicitOps)
4905 4906 4907
		goto special_insn;


4908
	if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
4909
		/* optimisation - avoid slow emulated read if Mov */
4910 4911
		rc = segmented_read(ctxt, ctxt->dst.addr.mem,
				   &ctxt->dst.val, ctxt->dst.bytes);
4912 4913
		if (rc != X86EMUL_CONTINUE)
			goto done;
4914
	}
4915
	ctxt->dst.orig_val = ctxt->dst.val;
4916

4917 4918
special_insn:

4919
	if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4920
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
4921
					      X86_ICPT_POST_MEMACCESS);
4922 4923 4924 4925
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

4926 4927 4928 4929
	if (ctxt->rep_prefix && (ctxt->d & String))
		ctxt->eflags |= EFLG_RF;
	else
		ctxt->eflags &= ~EFLG_RF;
4930

4931
	if (ctxt->execute) {
4932 4933 4934 4935 4936 4937 4938
		if (ctxt->d & Fastop) {
			void (*fop)(struct fastop *) = (void *)ctxt->execute;
			rc = fastop(ctxt, fop);
			if (rc != X86EMUL_CONTINUE)
				goto done;
			goto writeback;
		}
4939
		rc = ctxt->execute(ctxt);
4940 4941 4942 4943 4944
		if (rc != X86EMUL_CONTINUE)
			goto done;
		goto writeback;
	}

B
Borislav Petkov 已提交
4945
	if (ctxt->opcode_len == 2)
A
Avi Kivity 已提交
4946
		goto twobyte_insn;
4947 4948
	else if (ctxt->opcode_len == 3)
		goto threebyte_insn;
A
Avi Kivity 已提交
4949

4950
	switch (ctxt->b) {
A
Avi Kivity 已提交
4951
	case 0x63:		/* movsxd */
4952
		if (ctxt->mode != X86EMUL_MODE_PROT64)
A
Avi Kivity 已提交
4953
			goto cannot_emulate;
4954
		ctxt->dst.val = (s32) ctxt->src.val;
A
Avi Kivity 已提交
4955
		break;
4956
	case 0x70 ... 0x7f: /* jcc (short) */
4957
		if (test_cc(ctxt->b, ctxt->eflags))
4958
			rc = jmp_rel(ctxt, ctxt->src.val);
4959
		break;
N
Nitin A Kamble 已提交
4960
	case 0x8d: /* lea r16/r32, m */
4961
		ctxt->dst.val = ctxt->src.addr.mem.ea;
N
Nitin A Kamble 已提交
4962
		break;
4963
	case 0x90 ... 0x97: /* nop / xchg reg, rax */
4964
		if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
4965 4966 4967
			ctxt->dst.type = OP_NONE;
		else
			rc = em_xchg(ctxt);
4968
		break;
4969
	case 0x98: /* cbw/cwde/cdqe */
4970 4971 4972 4973
		switch (ctxt->op_bytes) {
		case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
		case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
		case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
4974 4975
		}
		break;
4976
	case 0xcc:		/* int3 */
4977 4978
		rc = emulate_int(ctxt, 3);
		break;
4979
	case 0xcd:		/* int n */
4980
		rc = emulate_int(ctxt, ctxt->src.val);
4981 4982
		break;
	case 0xce:		/* into */
4983 4984
		if (ctxt->eflags & EFLG_OF)
			rc = emulate_int(ctxt, 4);
4985
		break;
4986
	case 0xe9: /* jmp rel */
4987
	case 0xeb: /* jmp rel short */
4988
		rc = jmp_rel(ctxt, ctxt->src.val);
4989
		ctxt->dst.type = OP_NONE; /* Disable writeback. */
4990
		break;
4991
	case 0xf4:              /* hlt */
4992
		ctxt->ops->halt(ctxt);
4993
		break;
4994 4995 4996 4997 4998 4999 5000
	case 0xf5:	/* cmc */
		/* complement carry flag from eflags reg */
		ctxt->eflags ^= EFLG_CF;
		break;
	case 0xf8: /* clc */
		ctxt->eflags &= ~EFLG_CF;
		break;
5001 5002 5003
	case 0xf9: /* stc */
		ctxt->eflags |= EFLG_CF;
		break;
5004 5005 5006 5007 5008 5009
	case 0xfc: /* cld */
		ctxt->eflags &= ~EFLG_DF;
		break;
	case 0xfd: /* std */
		ctxt->eflags |= EFLG_DF;
		break;
5010 5011
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
5012
	}
5013

5014 5015 5016
	if (rc != X86EMUL_CONTINUE)
		goto done;

5017
writeback:
5018 5019 5020 5021 5022 5023
	if (ctxt->d & SrcWrite) {
		BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
		rc = writeback(ctxt, &ctxt->src);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}
5024 5025 5026 5027 5028
	if (!(ctxt->d & NoWrite)) {
		rc = writeback(ctxt, &ctxt->dst);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}
5029

5030 5031 5032 5033
	/*
	 * restore dst type in case the decoding will be reused
	 * (happens for string instruction )
	 */
5034
	ctxt->dst.type = saved_dst_type;
5035

5036
	if ((ctxt->d & SrcMask) == SrcSI)
5037
		string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
5038

5039
	if ((ctxt->d & DstMask) == DstDI)
5040
		string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
5041

5042
	if (ctxt->rep_prefix && (ctxt->d & String)) {
5043
		unsigned int count;
5044
		struct read_cache *r = &ctxt->io_read;
5045 5046 5047 5048
		if ((ctxt->d & SrcMask) == SrcSI)
			count = ctxt->src.count;
		else
			count = ctxt->dst.count;
5049
		register_address_increment(ctxt, VCPU_REGS_RCX, -count);
5050

5051 5052 5053 5054 5055
		if (!string_insn_completed(ctxt)) {
			/*
			 * Re-enter guest when pio read ahead buffer is empty
			 * or, if it is not used, after each 1024 iteration.
			 */
5056
			if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
5057 5058 5059 5060 5061 5062
			    (r->end == 0 || r->end != r->pos)) {
				/*
				 * Reset read cache. Usually happens before
				 * decode, but since instruction is restarted
				 * we have to do it here.
				 */
5063
				ctxt->mem_read.end = 0;
5064
				writeback_registers(ctxt);
5065 5066 5067
				return EMULATION_RESTART;
			}
			goto done; /* skip rip writeback */
5068
		}
5069
		ctxt->eflags &= ~EFLG_RF;
5070
	}
5071

5072
	ctxt->eip = ctxt->_eip;
5073 5074

done:
5075 5076
	if (rc == X86EMUL_PROPAGATE_FAULT) {
		WARN_ON(ctxt->exception.vector > 0x1f);
5077
		ctxt->have_exception = true;
5078
	}
5079 5080 5081
	if (rc == X86EMUL_INTERCEPTED)
		return EMULATION_INTERCEPTED;

5082 5083 5084
	if (rc == X86EMUL_CONTINUE)
		writeback_registers(ctxt);

5085
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
A
Avi Kivity 已提交
5086 5087

twobyte_insn:
5088
	switch (ctxt->b) {
5089
	case 0x09:		/* wbinvd */
5090
		(ctxt->ops->wbinvd)(ctxt);
5091 5092
		break;
	case 0x08:		/* invd */
5093 5094
	case 0x0d:		/* GrpP (prefetch) */
	case 0x18:		/* Grp16 (prefetch/nop) */
P
Paolo Bonzini 已提交
5095
	case 0x1f:		/* nop */
5096 5097
		break;
	case 0x20: /* mov cr, reg */
5098
		ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
5099
		break;
A
Avi Kivity 已提交
5100
	case 0x21: /* mov from dr to reg */
5101
		ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
A
Avi Kivity 已提交
5102 5103
		break;
	case 0x40 ... 0x4f:	/* cmov */
5104 5105 5106 5107
		if (test_cc(ctxt->b, ctxt->eflags))
			ctxt->dst.val = ctxt->src.val;
		else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
			 ctxt->op_bytes != 4)
5108
			ctxt->dst.type = OP_NONE; /* no writeback */
A
Avi Kivity 已提交
5109
		break;
5110
	case 0x80 ... 0x8f: /* jnz rel, etc*/
5111
		if (test_cc(ctxt->b, ctxt->eflags))
5112
			rc = jmp_rel(ctxt, ctxt->src.val);
5113
		break;
5114
	case 0x90 ... 0x9f:     /* setcc r/m8 */
5115
		ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
5116
		break;
A
Avi Kivity 已提交
5117
	case 0xb6 ... 0xb7:	/* movzx */
5118
		ctxt->dst.bytes = ctxt->op_bytes;
5119
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
5120
						       : (u16) ctxt->src.val;
A
Avi Kivity 已提交
5121 5122
		break;
	case 0xbe ... 0xbf:	/* movsx */
5123
		ctxt->dst.bytes = ctxt->op_bytes;
5124
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
5125
							(s16) ctxt->src.val;
A
Avi Kivity 已提交
5126
		break;
5127 5128
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
5129
	}
5130

5131 5132
threebyte_insn:

5133 5134 5135
	if (rc != X86EMUL_CONTINUE)
		goto done;

A
Avi Kivity 已提交
5136 5137 5138
	goto writeback;

cannot_emulate:
5139
	return EMULATION_FAILED;
A
Avi Kivity 已提交
5140
}
5141 5142 5143 5144 5145 5146 5147 5148 5149 5150

void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
{
	invalidate_registers(ctxt);
}

void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
{
	writeback_registers(ctxt);
}