davinci-mcasp.c 51.8 KB
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/*
 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
 *
 * Multi-channel Audio Serial Port Driver
 *
 * Author: Nirmal Pandey <n-pandey@ti.com>,
 *         Suresh Rajashekara <suresh.r@ti.com>
 *         Steve Chen <schen@.mvista.com>
 *
 * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
 * Copyright:   (C) 2009  Texas Instruments, India
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
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#include <linux/platform_data/davinci_asp.h>
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#include <linux/math64.h>
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#include <sound/asoundef.h>
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#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/omap-pcm.h>
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#include "edma-pcm.h"
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#include "davinci-mcasp.h"

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#define MCASP_MAX_AFIFO_DEPTH	64

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static u32 context_regs[] = {
	DAVINCI_MCASP_TXFMCTL_REG,
	DAVINCI_MCASP_RXFMCTL_REG,
	DAVINCI_MCASP_TXFMT_REG,
	DAVINCI_MCASP_RXFMT_REG,
	DAVINCI_MCASP_ACLKXCTL_REG,
	DAVINCI_MCASP_ACLKRCTL_REG,
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	DAVINCI_MCASP_AHCLKXCTL_REG,
	DAVINCI_MCASP_AHCLKRCTL_REG,
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	DAVINCI_MCASP_PDIR_REG,
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	DAVINCI_MCASP_RXMASK_REG,
	DAVINCI_MCASP_TXMASK_REG,
	DAVINCI_MCASP_RXTDM_REG,
	DAVINCI_MCASP_TXTDM_REG,
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};

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struct davinci_mcasp_context {
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	u32	config_regs[ARRAY_SIZE(context_regs)];
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	u32	afifo_regs[2]; /* for read/write fifo control registers */
	u32	*xrsr_regs; /* for serializer configuration */
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	bool	pm_state;
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};

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struct davinci_mcasp_ruledata {
	struct davinci_mcasp *mcasp;
	int serializers;
};

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struct davinci_mcasp {
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	struct snd_dmaengine_dai_dma_data dma_data[2];
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	void __iomem *base;
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	u32 fifo_base;
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	struct device *dev;
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	struct snd_pcm_substream *substreams[2];
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	/* McASP specific data */
	int	tdm_slots;
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	u32	tdm_mask[2];
	int	slot_width;
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	u8	op_mode;
	u8	num_serializer;
	u8	*serial_dir;
	u8	version;
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	u8	bclk_div;
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	int	streams;
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	u32	irq_request[2];
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	int	dma_request[2];
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	int	sysclk_freq;
	bool	bclk_master;

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	/* McASP FIFO related */
	u8	txnumevt;
	u8	rxnumevt;

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	bool	dat_port;

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	/* Used for comstraint setting on the second stream */
	u32	channels;

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#ifdef CONFIG_PM_SLEEP
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	struct davinci_mcasp_context context;
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#endif
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	struct davinci_mcasp_ruledata ruledata[2];
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	struct snd_pcm_hw_constraint_list chconstr[2];
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};

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static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
				  u32 val)
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{
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	void __iomem *reg = mcasp->base + offset;
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	__raw_writel(__raw_readl(reg) | val, reg);
}

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static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
				  u32 val)
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{
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	void __iomem *reg = mcasp->base + offset;
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	__raw_writel((__raw_readl(reg) & ~(val)), reg);
}

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static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
				  u32 val, u32 mask)
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{
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	void __iomem *reg = mcasp->base + offset;
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	__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
}

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static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
				 u32 val)
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{
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	__raw_writel(val, mcasp->base + offset);
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}

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static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
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{
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	return (u32)__raw_readl(mcasp->base + offset);
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}

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static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
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{
	int i = 0;

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	mcasp_set_bits(mcasp, ctl_reg, val);
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	/* programming GBLCTL needs to read back from GBLCTL and verfiy */
	/* loop count is to avoid the lock-up */
	for (i = 0; i < 1000; i++) {
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		if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
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			break;
	}

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	if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
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		printk(KERN_ERR "GBLCTL write error\n");
}

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static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
{
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	u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
	u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
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	return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
}

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static void mcasp_start_rx(struct davinci_mcasp *mcasp)
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{
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	if (mcasp->rxnumevt) {	/* enable FIFO */
		u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;

		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
		mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
	}

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	/* Start clocks */
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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
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	/*
	 * When ASYNC == 0 the transmit and receive sections operate
	 * synchronously from the transmit clock and frame sync. We need to make
	 * sure that the TX signlas are enabled when starting reception.
	 */
	if (mcasp_is_synchronous(mcasp)) {
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		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
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	}

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	/* Activate serializer(s) */
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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
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	/* Release RX state machine */
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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
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	/* Release Frame Sync generator */
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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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	if (mcasp_is_synchronous(mcasp))
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		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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	/* enable receive IRQs */
	mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
		       mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
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}

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static void mcasp_start_tx(struct davinci_mcasp *mcasp)
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{
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	u32 cnt;

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	if (mcasp->txnumevt) {	/* enable FIFO */
		u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;

		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
		mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
	}

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	/* Start clocks */
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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
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	/* Activate serializer(s) */
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	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
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	/* wait for XDATA to be cleared */
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	cnt = 0;
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	while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
	       (cnt < 100000))
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		cnt++;

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	/* Release TX state machine */
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
	/* Release Frame Sync generator */
	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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	/* enable transmit IRQs */
	mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
		       mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
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}

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static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
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{
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	mcasp->streams++;

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	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
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		mcasp_start_tx(mcasp);
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	else
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		mcasp_start_rx(mcasp);
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}

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static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
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{
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	/* disable IRQ sources */
	mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
		       mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);

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	/*
	 * In synchronous mode stop the TX clocks if no other stream is
	 * running
	 */
	if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
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		mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
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	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
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	if (mcasp->rxnumevt) {	/* disable FIFO */
		u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;

		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
	}
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}

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static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
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{
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	u32 val = 0;

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	/* disable IRQ sources */
	mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
		       mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);

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	/*
	 * In synchronous mode keep TX clocks running if the capture stream is
	 * still running.
	 */
	if (mcasp_is_synchronous(mcasp) && mcasp->streams)
		val =  TXHCLKRST | TXCLKRST | TXFSRST;

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	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
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	if (mcasp->txnumevt) {	/* disable FIFO */
		u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;

		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
	}
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}

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static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
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{
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	mcasp->streams--;

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	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
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		mcasp_stop_tx(mcasp);
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	else
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		mcasp_stop_rx(mcasp);
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}

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static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
{
	struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
	struct snd_pcm_substream *substream;
	u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
	u32 handled_mask = 0;
	u32 stat;

	stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
	if (stat & XUNDRN & irq_mask) {
		dev_warn(mcasp->dev, "Transmit buffer underflow\n");
		handled_mask |= XUNDRN;

		substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
		if (substream) {
			snd_pcm_stream_lock_irq(substream);
			if (snd_pcm_running(substream))
				snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
			snd_pcm_stream_unlock_irq(substream);
		}
	}

	if (!handled_mask)
		dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
			 stat);

	if (stat & XRERR)
		handled_mask |= XRERR;

	/* Ack the handled event only */
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);

	return IRQ_RETVAL(handled_mask);
}

static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
{
	struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
	struct snd_pcm_substream *substream;
	u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
	u32 handled_mask = 0;
	u32 stat;

	stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
	if (stat & ROVRN & irq_mask) {
		dev_warn(mcasp->dev, "Receive buffer overflow\n");
		handled_mask |= ROVRN;

		substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
		if (substream) {
			snd_pcm_stream_lock_irq(substream);
			if (snd_pcm_running(substream))
				snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
			snd_pcm_stream_unlock_irq(substream);
		}
	}

	if (!handled_mask)
		dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
			 stat);

	if (stat & XRERR)
		handled_mask |= XRERR;

	/* Ack the handled event only */
	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);

	return IRQ_RETVAL(handled_mask);
}

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static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
{
	struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
	irqreturn_t ret = IRQ_NONE;

	if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
		ret = davinci_mcasp_tx_irq_handler(irq, data);

	if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
		ret |= davinci_mcasp_rx_irq_handler(irq, data);

	return ret;
}

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static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
					 unsigned int fmt)
{
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	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
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	int ret = 0;
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	u32 data_delay;
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	bool fs_pol_rising;
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	bool inv_fs = false;
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401
	pm_runtime_get_sync(mcasp->dev);
402
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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	case SND_SOC_DAIFMT_DSP_A:
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
		/* 1st data bit occur one ACLK cycle after the frame sync */
		data_delay = 1;
		break;
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	case SND_SOC_DAIFMT_DSP_B:
	case SND_SOC_DAIFMT_AC97:
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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		/* No delay after FS */
		data_delay = 0;
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		break;
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	case SND_SOC_DAIFMT_I2S:
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		/* configure a full-word SYNC pulse (LRCLK) */
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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		/* 1st data bit occur one ACLK cycle after the frame sync */
		data_delay = 1;
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		/* FS need to be inverted */
		inv_fs = true;
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		break;
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	case SND_SOC_DAIFMT_LEFT_J:
		/* configure a full-word SYNC pulse (LRCLK) */
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
		/* No delay after FS */
		data_delay = 0;
		break;
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	default:
		ret = -EINVAL;
		goto out;
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	}

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	mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
		       FSXDLY(3));
	mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
		       FSRDLY(3));

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	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* codec is clock and frame slave */
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
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		mcasp->bclk_master = 1;
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		break;
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	case SND_SOC_DAIFMT_CBS_CFM:
		/* codec is clock slave and frame master */
		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);

		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);

		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
		mcasp->bclk_master = 1;
		break;
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	case SND_SOC_DAIFMT_CBM_CFS:
		/* codec is clock master and frame slave */
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
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		mcasp->bclk_master = 0;
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		break;
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	case SND_SOC_DAIFMT_CBM_CFM:
		/* codec is clock and frame master */
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
			       ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
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		mcasp->bclk_master = 0;
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		break;
	default:
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		ret = -EINVAL;
		goto out;
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	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_NF:
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
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		fs_pol_rising = true;
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		break;
	case SND_SOC_DAIFMT_NB_IF:
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
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		fs_pol_rising = false;
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		break;
	case SND_SOC_DAIFMT_IB_IF:
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
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		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
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		fs_pol_rising = false;
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		break;
	case SND_SOC_DAIFMT_NB_NF:
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		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
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		fs_pol_rising = true;
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		break;
	default:
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		ret = -EINVAL;
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		goto out;
	}

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	if (inv_fs)
		fs_pol_rising = !fs_pol_rising;

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	if (fs_pol_rising) {
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
	} else {
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
531
	}
532
out:
533
	pm_runtime_put(mcasp->dev);
534
	return ret;
535 536
}

537 538
static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
				      int div, bool explicit)
539
{
540
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
541

542
	pm_runtime_get_sync(mcasp->dev);
543 544
	switch (div_id) {
	case 0:		/* MCLK divider */
545
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
546
			       AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
547
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
548 549 550 551
			       AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
		break;

	case 1:		/* BCLK divider */
552
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
553
			       ACLKXDIV(div - 1), ACLKXDIV_MASK);
554
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
555
			       ACLKRDIV(div - 1), ACLKRDIV_MASK);
556 557
		if (explicit)
			mcasp->bclk_div = div;
558 559
		break;

560 561 562 563 564 565 566 567 568 569 570 571 572 573 574
	case 2:	/*
		 * BCLK/LRCLK ratio descries how many bit-clock cycles
		 * fit into one frame. The clock ratio is given for a
		 * full period of data (for I2S format both left and
		 * right channels), so it has to be divided by number
		 * of tdm-slots (for I2S - divided by 2).
		 * Instead of storing this ratio, we calculate a new
		 * tdm_slot width by dividing the the ratio by the
		 * number of configured tdm slots.
		 */
		mcasp->slot_width = div / mcasp->tdm_slots;
		if (div % mcasp->tdm_slots)
			dev_warn(mcasp->dev,
				 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
				 __func__, div, mcasp->tdm_slots);
575 576
		break;

577 578 579 580
	default:
		return -EINVAL;
	}

581
	pm_runtime_put(mcasp->dev);
582 583 584
	return 0;
}

585 586 587 588 589 590
static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
				    int div)
{
	return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
}

591 592 593
static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
				    unsigned int freq, int dir)
{
594
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
595

596
	pm_runtime_get_sync(mcasp->dev);
597
	if (dir == SND_SOC_CLOCK_OUT) {
598 599 600
		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
601
	} else {
602 603 604
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
605 606
	}

607 608
	mcasp->sysclk_freq = freq;

609
	pm_runtime_put(mcasp->dev);
610 611 612
	return 0;
}

613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683
/* All serializers must have equal number of channels */
static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
				       int serializers)
{
	struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
	unsigned int *list = (unsigned int *) cl->list;
	int slots = mcasp->tdm_slots;
	int i, count = 0;

	if (mcasp->tdm_mask[stream])
		slots = hweight32(mcasp->tdm_mask[stream]);

	for (i = 2; i <= slots; i++)
		list[count++] = i;

	for (i = 2; i <= serializers; i++)
		list[count++] = i*slots;

	cl->count = count;

	return 0;
}

static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
{
	int rx_serializers = 0, tx_serializers = 0, ret, i;

	for (i = 0; i < mcasp->num_serializer; i++)
		if (mcasp->serial_dir[i] == TX_MODE)
			tx_serializers++;
		else if (mcasp->serial_dir[i] == RX_MODE)
			rx_serializers++;

	ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
					  tx_serializers);
	if (ret)
		return ret;

	ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
					  rx_serializers);

	return ret;
}


static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
				      unsigned int tx_mask,
				      unsigned int rx_mask,
				      int slots, int slot_width)
{
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);

	dev_dbg(mcasp->dev,
		 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
		 __func__, tx_mask, rx_mask, slots, slot_width);

	if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
		dev_err(mcasp->dev,
			"Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
			tx_mask, rx_mask, slots);
		return -EINVAL;
	}

	if (slot_width &&
	    (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
		dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
			__func__, slot_width);
		return -EINVAL;
	}

	mcasp->tdm_slots = slots;
684 685
	mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
	mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
686 687 688 689 690
	mcasp->slot_width = slot_width;

	return davinci_mcasp_set_ch_constraints(mcasp);
}

691
static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
692
				       int sample_width)
693
{
694
	u32 fmt;
695 696 697 698
	u32 tx_rotate = (sample_width / 4) & 0x7;
	u32 mask = (1ULL << sample_width) - 1;
	u32 slot_width = sample_width;

699 700 701 702 703 704 705 706 707 708
	/*
	 * For captured data we should not rotate, inversion and masking is
	 * enoguh to get the data to the right position:
	 * Format	  data from bus		after reverse (XRBUF)
	 * S16_LE:	|LSB|MSB|xxx|xxx|	|xxx|xxx|MSB|LSB|
	 * S24_3LE:	|LSB|DAT|MSB|xxx|	|xxx|MSB|DAT|LSB|
	 * S24_LE:	|LSB|DAT|MSB|xxx|	|xxx|MSB|DAT|LSB|
	 * S32_LE:	|LSB|DAT|DAT|MSB|	|MSB|DAT|DAT|LSB|
	 */
	u32 rx_rotate = 0;
709

710
	/*
711 712 713 714
	 * Setting the tdm slot width either with set_clkdiv() or
	 * set_tdm_slot() allows us to for example send 32 bits per
	 * channel to the codec, while only 16 of them carry audio
	 * payload.
715
	 */
716
	if (mcasp->slot_width) {
717
		/*
718 719 720
		 * When we have more bclk then it is needed for the
		 * data, we need to use the rotation to move the
		 * received samples to have correct alignment.
721
		 */
722 723
		slot_width = mcasp->slot_width;
		rx_rotate = (slot_width - sample_width) / 4;
724
	}
725

726
	/* mapping of the XSSZ bit-field as described in the datasheet */
727
	fmt = (slot_width >> 1) - 1;
728

729
	if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
730 731 732 733 734 735 736 737 738
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
			       RXSSZ(0x0F));
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
			       TXSSZ(0x0F));
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
			       TXROT(7));
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
			       RXROT(7));
		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
739 740
	}

741
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
742

743 744 745
	return 0;
}

746
static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
747
				 int period_words, int channels)
748
{
749
	struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
750
	int i;
751 752
	u8 tx_ser = 0;
	u8 rx_ser = 0;
753
	u8 slots = mcasp->tdm_slots;
754
	u8 max_active_serializers = (channels + slots - 1) / slots;
755
	int active_serializers, numevt;
756
	u32 reg;
757
	/* Default configuration */
758
	if (mcasp->version < MCASP_VERSION_3)
759
		mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
760 761

	/* All PINS as McASP */
762
	mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
763 764

	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
765 766
		mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
767
	} else {
768 769
		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
		mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
770 771
	}

772
	for (i = 0; i < mcasp->num_serializer; i++) {
773 774
		mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
			       mcasp->serial_dir[i]);
775
		if (mcasp->serial_dir[i] == TX_MODE &&
776
					tx_ser < max_active_serializers) {
777
			mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
778 779
			mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
				       DISMOD_LOW, DISMOD_MASK);
780
			tx_ser++;
781
		} else if (mcasp->serial_dir[i] == RX_MODE &&
782
					rx_ser < max_active_serializers) {
783
			mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
784
			rx_ser++;
785
		} else {
786 787
			mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
				       SRMOD_INACTIVE, SRMOD_MASK);
788 789 790
		}
	}

791 792 793 794 795 796 797 798 799
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		active_serializers = tx_ser;
		numevt = mcasp->txnumevt;
		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
	} else {
		active_serializers = rx_ser;
		numevt = mcasp->rxnumevt;
		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
	}
800

801
	if (active_serializers < max_active_serializers) {
802
		dev_warn(mcasp->dev, "stream has more channels (%d) than are "
803 804
			 "enabled in mcasp (%d)\n", channels,
			 active_serializers * slots);
805 806 807
		return -EINVAL;
	}

808
	/* AFIFO is not in use */
809 810
	if (!numevt) {
		/* Configure the burst size for platform drivers */
811 812 813 814 815 816 817 818 819 820 821
		if (active_serializers > 1) {
			/*
			 * If more than one serializers are in use we have one
			 * DMA request to provide data for all serializers.
			 * For example if three serializers are enabled the DMA
			 * need to transfer three words per DMA request.
			 */
			dma_data->maxburst = active_serializers;
		} else {
			dma_data->maxburst = 0;
		}
822
		return 0;
823
	}
824

825 826 827 828 829 830 831 832 833 834 835 836
	if (period_words % active_serializers) {
		dev_err(mcasp->dev, "Invalid combination of period words and "
			"active serializers: %d, %d\n", period_words,
			active_serializers);
		return -EINVAL;
	}

	/*
	 * Calculate the optimal AFIFO depth for platform side:
	 * The number of words for numevt need to be in steps of active
	 * serializers.
	 */
837 838
	numevt = (numevt / active_serializers) * active_serializers;

839 840 841
	while (period_words % numevt && numevt > 0)
		numevt -= active_serializers;
	if (numevt <= 0)
842
		numevt = active_serializers;
843

844 845
	mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
	mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
846

847
	/* Configure the burst size for platform drivers */
848 849
	if (numevt == 1)
		numevt = 0;
850 851
	dma_data->maxburst = numevt;

852
	return 0;
853 854
}

855 856
static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
			      int channels)
857 858
{
	int i, active_slots;
859 860
	int total_slots;
	int active_serializers;
861
	u32 mask = 0;
862
	u32 busel = 0;
863

864 865 866 867
	total_slots = mcasp->tdm_slots;

	/*
	 * If more than one serializer is needed, then use them with
868 869 870
	 * all the specified tdm_slots. Otherwise, one serializer can
	 * cope with the transaction using just as many slots as there
	 * are channels in the stream.
871
	 */
872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891
	if (mcasp->tdm_mask[stream]) {
		active_slots = hweight32(mcasp->tdm_mask[stream]);
		active_serializers = (channels + active_slots - 1) /
			active_slots;
		if (active_serializers == 1) {
			active_slots = channels;
			for (i = 0; i < total_slots; i++) {
				if ((1 << i) & mcasp->tdm_mask[stream]) {
					mask |= (1 << i);
					if (--active_slots <= 0)
						break;
				}
			}
		}
	} else {
		active_serializers = (channels + total_slots - 1) / total_slots;
		if (active_serializers == 1)
			active_slots = channels;
		else
			active_slots = total_slots;
892

893 894 895
		for (i = 0; i < active_slots; i++)
			mask |= (1 << i);
	}
896
	mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
897

898 899 900
	if (!mcasp->dat_port)
		busel = TXSEL;

901 902 903 904 905 906 907 908 909 910
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
			       FSXMOD(total_slots), FSXMOD(0x1FF));
	} else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
			       FSRMOD(total_slots), FSRMOD(0x1FF));
911 912 913 914 915 916 917 918
		/*
		 * If McASP is set to be TX/RX synchronous and the playback is
		 * not running already we need to configure the TX slots in
		 * order to have correct FSX on the bus
		 */
		if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
			mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
				       FSXMOD(total_slots), FSXMOD(0x1FF));
919
	}
920 921

	return 0;
922 923 924
}

/* S/PDIF */
925 926
static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
			      unsigned int rate)
927
{
928 929 930
	u32 cs_value = 0;
	u8 *cs_bytes = (u8*) &cs_value;

931 932
	/* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
	   and LSB first */
933
	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
934 935

	/* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
936
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
937 938

	/* Set the TX tdm : for all the slots */
939
	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
940 941

	/* Set the TX clock controls : div = 1 and internal */
942
	mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
943

944
	mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
945 946

	/* Only 44100 and 48000 are valid, both have the same setting */
947
	mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
948 949

	/* Enable the DIT */
950
	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
951

952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991
	/* Set S/PDIF channel status bits */
	cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
	cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;

	switch (rate) {
	case 22050:
		cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
		break;
	case 24000:
		cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
		break;
	case 32000:
		cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
		break;
	case 44100:
		cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
		break;
	case 48000:
		cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
		break;
	case 88200:
		cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
		break;
	case 96000:
		cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
		break;
	case 176400:
		cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
		break;
	case 192000:
		cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
		break;
	default:
		printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
		return -EINVAL;
	}

	mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
	mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);

992
	return 0;
993 994
}

995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018
static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
				      unsigned int bclk_freq,
				      int *error_ppm)
{
	int div = mcasp->sysclk_freq / bclk_freq;
	int rem = mcasp->sysclk_freq % bclk_freq;

	if (rem != 0) {
		if (div == 0 ||
		    ((mcasp->sysclk_freq / div) - bclk_freq) >
		    (bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
			div++;
			rem = rem - bclk_freq;
		}
	}
	if (error_ppm)
		*error_ppm =
			(div*1000000 + (int)div64_long(1000000LL*rem,
						       (int)bclk_freq))
			/div - 1000000;

	return div;
}

1019 1020 1021 1022
static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
					struct snd_pcm_hw_params *params,
					struct snd_soc_dai *cpu_dai)
{
1023
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1024
	int word_length;
1025
	int channels = params_channels(params);
1026
	int period_size = params_period_size(params);
1027
	int ret;
1028

1029 1030 1031 1032 1033
	/*
	 * If mcasp is BCLK master, and a BCLK divider was not provided by
	 * the machine driver, we need to calculate the ratio.
	 */
	if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1034
		int slots = mcasp->tdm_slots;
1035 1036 1037 1038
		int rate = params_rate(params);
		int sbits = params_width(params);
		int ppm, div;

1039 1040 1041
		if (mcasp->slot_width)
			sbits = mcasp->slot_width;

1042
		div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots,
1043 1044 1045 1046 1047
						 &ppm);
		if (ppm)
			dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
				 ppm);

1048
		__davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
1049 1050
	}

1051 1052
	ret = mcasp_common_hw_param(mcasp, substream->stream,
				    period_size * channels, channels);
1053 1054 1055
	if (ret)
		return ret;

1056
	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1057
		ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1058
	else
1059 1060
		ret = mcasp_i2s_hw_param(mcasp, substream->stream,
					 channels);
1061 1062 1063

	if (ret)
		return ret;
1064 1065

	switch (params_format(params)) {
1066
	case SNDRV_PCM_FORMAT_U8:
1067
	case SNDRV_PCM_FORMAT_S8:
1068
		word_length = 8;
1069 1070
		break;

1071
	case SNDRV_PCM_FORMAT_U16_LE:
1072
	case SNDRV_PCM_FORMAT_S16_LE:
1073
		word_length = 16;
1074 1075
		break;

1076 1077
	case SNDRV_PCM_FORMAT_U24_3LE:
	case SNDRV_PCM_FORMAT_S24_3LE:
1078
		word_length = 24;
1079 1080
		break;

1081 1082
	case SNDRV_PCM_FORMAT_U24_LE:
	case SNDRV_PCM_FORMAT_S24_LE:
1083 1084 1085
		word_length = 24;
		break;

1086
	case SNDRV_PCM_FORMAT_U32_LE:
1087
	case SNDRV_PCM_FORMAT_S32_LE:
1088
		word_length = 32;
1089 1090 1091 1092 1093 1094
		break;

	default:
		printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
		return -EINVAL;
	}
1095

1096
	davinci_config_channel_size(mcasp, word_length);
1097

1098 1099 1100
	if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
		mcasp->channels = channels;

1101 1102 1103 1104 1105 1106
	return 0;
}

static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
				     int cmd, struct snd_soc_dai *cpu_dai)
{
1107
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1108 1109 1110 1111
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_RESUME:
1112 1113
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1114
		davinci_mcasp_start(mcasp, substream->stream);
1115 1116
		break;
	case SNDRV_PCM_TRIGGER_SUSPEND:
1117
	case SNDRV_PCM_TRIGGER_STOP:
1118
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1119
		davinci_mcasp_stop(mcasp, substream->stream);
1120 1121 1122 1123 1124 1125 1126 1127 1128
		break;

	default:
		ret = -EINVAL;
	}

	return ret;
}

1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142
static const unsigned int davinci_mcasp_dai_rates[] = {
	8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
	88200, 96000, 176400, 192000,
};

#define DAVINCI_MAX_RATE_ERROR_PPM 1000

static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
				      struct snd_pcm_hw_rule *rule)
{
	struct davinci_mcasp_ruledata *rd = rule->private;
	struct snd_interval *ri =
		hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
	int sbits = params_width(params);
1143
	int slots = rd->mcasp->tdm_slots;
1144 1145
	struct snd_interval range;
	int i;
1146

1147 1148 1149
	if (rd->mcasp->slot_width)
		sbits = rd->mcasp->slot_width;

1150 1151
	snd_interval_any(&range);
	range.empty = 1;
1152 1153

	for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1154
		if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1155
			uint bclk_freq = sbits*slots*
1156 1157 1158 1159
				davinci_mcasp_dai_rates[i];
			int ppm;

			davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1160 1161 1162 1163 1164 1165 1166
			if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
				if (range.empty) {
					range.min = davinci_mcasp_dai_rates[i];
					range.empty = 0;
				}
				range.max = davinci_mcasp_dai_rates[i];
			}
1167 1168
		}
	}
1169

1170
	dev_dbg(rd->mcasp->dev,
1171 1172
		"Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
		ri->min, ri->max, range.min, range.max, sbits, slots);
1173

1174 1175
	return snd_interval_refine(hw_param_interval(params, rule->var),
				   &range);
1176 1177 1178 1179 1180 1181 1182 1183 1184
}

static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
					struct snd_pcm_hw_rule *rule)
{
	struct davinci_mcasp_ruledata *rd = rule->private;
	struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
	struct snd_mask nfmt;
	int rate = params_rate(params);
1185
	int slots = rd->mcasp->tdm_slots;
1186 1187 1188 1189 1190 1191
	int i, count = 0;

	snd_mask_none(&nfmt);

	for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
		if (snd_mask_test(fmt, i)) {
1192
			uint sbits = snd_pcm_format_width(i);
1193 1194
			int ppm;

1195 1196 1197 1198 1199
			if (rd->mcasp->slot_width)
				sbits = rd->mcasp->slot_width;

			davinci_mcasp_calc_clk_div(rd->mcasp, sbits*slots*rate,
						   &ppm);
1200 1201 1202 1203 1204 1205 1206
			if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
				snd_mask_set(&nfmt, i);
				count++;
			}
		}
	}
	dev_dbg(rd->mcasp->dev,
1207 1208
		"%d possible sample format for %d Hz and %d tdm slots\n",
		count, rate, slots);
1209 1210 1211 1212

	return snd_mask_refine(fmt, &nfmt);
}

1213 1214 1215 1216
static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
				 struct snd_soc_dai *cpu_dai)
{
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1217 1218
	struct davinci_mcasp_ruledata *ruledata =
					&mcasp->ruledata[substream->stream];
1219 1220
	u32 max_channels = 0;
	int i, dir;
1221 1222 1223 1224
	int tdm_slots = mcasp->tdm_slots;

	if (mcasp->tdm_mask[substream->stream])
		tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1225

1226 1227
	mcasp->substreams[substream->stream] = substream;

1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243
	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
		return 0;

	/*
	 * Limit the maximum allowed channels for the first stream:
	 * number of serializers for the direction * tdm slots per serializer
	 */
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dir = TX_MODE;
	else
		dir = RX_MODE;

	for (i = 0; i < mcasp->num_serializer; i++) {
		if (mcasp->serial_dir[i] == dir)
			max_channels++;
	}
1244
	ruledata->serializers = max_channels;
1245
	max_channels *= tdm_slots;
1246 1247 1248 1249 1250 1251 1252 1253 1254
	/*
	 * If the already active stream has less channels than the calculated
	 * limnit based on the seirializers * tdm_slots, we need to use that as
	 * a constraint for the second stream.
	 * Otherwise (first stream or less allowed channels) we use the
	 * calculated constraint.
	 */
	if (mcasp->channels && mcasp->channels < max_channels)
		max_channels = mcasp->channels;
1255 1256 1257 1258 1259 1260
	/*
	 * But we can always allow channels upto the amount of
	 * the available tdm_slots.
	 */
	if (max_channels < tdm_slots)
		max_channels = tdm_slots;
1261 1262 1263 1264

	snd_pcm_hw_constraint_minmax(substream->runtime,
				     SNDRV_PCM_HW_PARAM_CHANNELS,
				     2, max_channels);
1265

1266 1267 1268 1269 1270 1271 1272 1273
	snd_pcm_hw_constraint_list(substream->runtime,
				   0, SNDRV_PCM_HW_PARAM_CHANNELS,
				   &mcasp->chconstr[substream->stream]);

	if (mcasp->slot_width)
		snd_pcm_hw_constraint_minmax(substream->runtime,
					     SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
					     8, mcasp->slot_width);
1274

1275 1276 1277 1278 1279 1280 1281
	/*
	 * If we rely on implicit BCLK divider setting we should
	 * set constraints based on what we can provide.
	 */
	if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
		int ret;

1282
		ruledata->mcasp = mcasp;
1283 1284 1285 1286

		ret = snd_pcm_hw_rule_add(substream->runtime, 0,
					  SNDRV_PCM_HW_PARAM_RATE,
					  davinci_mcasp_hw_rule_rate,
1287
					  ruledata,
1288
					  SNDRV_PCM_HW_PARAM_FORMAT, -1);
1289 1290 1291 1292 1293
		if (ret)
			return ret;
		ret = snd_pcm_hw_rule_add(substream->runtime, 0,
					  SNDRV_PCM_HW_PARAM_FORMAT,
					  davinci_mcasp_hw_rule_format,
1294
					  ruledata,
1295
					  SNDRV_PCM_HW_PARAM_RATE, -1);
1296 1297 1298 1299
		if (ret)
			return ret;
	}

1300 1301 1302 1303 1304 1305 1306 1307
	return 0;
}

static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
				   struct snd_soc_dai *cpu_dai)
{
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);

1308 1309
	mcasp->substreams[substream->stream] = NULL;

1310 1311 1312 1313 1314 1315 1316
	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
		return;

	if (!cpu_dai->active)
		mcasp->channels = 0;
}

1317
static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1318 1319
	.startup	= davinci_mcasp_startup,
	.shutdown	= davinci_mcasp_shutdown,
1320 1321 1322
	.trigger	= davinci_mcasp_trigger,
	.hw_params	= davinci_mcasp_hw_params,
	.set_fmt	= davinci_mcasp_set_dai_fmt,
1323
	.set_clkdiv	= davinci_mcasp_set_clkdiv,
1324
	.set_sysclk	= davinci_mcasp_set_sysclk,
1325
	.set_tdm_slot	= davinci_mcasp_set_tdm_slot,
1326 1327
};

1328 1329 1330 1331
static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
{
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);

1332 1333
	dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
	dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1334 1335 1336 1337

	return 0;
}

1338 1339 1340 1341
#ifdef CONFIG_PM_SLEEP
static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
{
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1342
	struct davinci_mcasp_context *context = &mcasp->context;
1343
	u32 reg;
1344
	int i;
1345

1346
	context->pm_state = pm_runtime_active(mcasp->dev);
1347 1348 1349
	if (!context->pm_state)
		pm_runtime_get_sync(mcasp->dev);

1350 1351
	for (i = 0; i < ARRAY_SIZE(context_regs); i++)
		context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1352

1353 1354 1355 1356 1357 1358 1359 1360
	if (mcasp->txnumevt) {
		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
		context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
	}
	if (mcasp->rxnumevt) {
		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
		context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
	}
1361

1362 1363 1364
	for (i = 0; i < mcasp->num_serializer; i++)
		context->xrsr_regs[i] = mcasp_get_reg(mcasp,
						DAVINCI_MCASP_XRSRCTL_REG(i));
1365

1366 1367
	pm_runtime_put_sync(mcasp->dev);

1368 1369 1370 1371 1372 1373
	return 0;
}

static int davinci_mcasp_resume(struct snd_soc_dai *dai)
{
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1374
	struct davinci_mcasp_context *context = &mcasp->context;
1375
	u32 reg;
1376
	int i;
1377

1378 1379
	pm_runtime_get_sync(mcasp->dev);

1380 1381
	for (i = 0; i < ARRAY_SIZE(context_regs); i++)
		mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1382

1383 1384 1385 1386 1387 1388 1389 1390
	if (mcasp->txnumevt) {
		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
		mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
	}
	if (mcasp->rxnumevt) {
		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
		mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
	}
1391

1392 1393 1394
	for (i = 0; i < mcasp->num_serializer; i++)
		mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
			      context->xrsr_regs[i]);
1395

1396 1397 1398
	if (!context->pm_state)
		pm_runtime_put_sync(mcasp->dev);

1399 1400 1401 1402 1403 1404 1405
	return 0;
}
#else
#define davinci_mcasp_suspend NULL
#define davinci_mcasp_resume NULL
#endif

1406 1407
#define DAVINCI_MCASP_RATES	SNDRV_PCM_RATE_8000_192000

1408 1409 1410 1411
#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
				SNDRV_PCM_FMTBIT_U8 | \
				SNDRV_PCM_FMTBIT_S16_LE | \
				SNDRV_PCM_FMTBIT_U16_LE | \
1412 1413 1414 1415
				SNDRV_PCM_FMTBIT_S24_LE | \
				SNDRV_PCM_FMTBIT_U24_LE | \
				SNDRV_PCM_FMTBIT_S24_3LE | \
				SNDRV_PCM_FMTBIT_U24_3LE | \
1416 1417 1418
				SNDRV_PCM_FMTBIT_S32_LE | \
				SNDRV_PCM_FMTBIT_U32_LE)

1419
static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1420
	{
1421
		.name		= "davinci-mcasp.0",
1422
		.probe		= davinci_mcasp_dai_probe,
1423 1424
		.suspend	= davinci_mcasp_suspend,
		.resume		= davinci_mcasp_resume,
1425 1426
		.playback	= {
			.channels_min	= 2,
1427
			.channels_max	= 32 * 16,
1428
			.rates 		= DAVINCI_MCASP_RATES,
1429
			.formats	= DAVINCI_MCASP_PCM_FMTS,
1430 1431 1432
		},
		.capture 	= {
			.channels_min 	= 2,
1433
			.channels_max	= 32 * 16,
1434
			.rates 		= DAVINCI_MCASP_RATES,
1435
			.formats	= DAVINCI_MCASP_PCM_FMTS,
1436 1437 1438
		},
		.ops 		= &davinci_mcasp_dai_ops,

1439
		.symmetric_samplebits	= 1,
1440
		.symmetric_rates	= 1,
1441 1442
	},
	{
1443
		.name		= "davinci-mcasp.1",
1444
		.probe		= davinci_mcasp_dai_probe,
1445 1446 1447 1448
		.playback 	= {
			.channels_min	= 1,
			.channels_max	= 384,
			.rates		= DAVINCI_MCASP_RATES,
1449
			.formats	= DAVINCI_MCASP_PCM_FMTS,
1450 1451 1452 1453 1454 1455
		},
		.ops 		= &davinci_mcasp_dai_ops,
	},

};

1456 1457 1458 1459
static const struct snd_soc_component_driver davinci_mcasp_component = {
	.name		= "davinci-mcasp",
};

1460
/* Some HW specific values and defaults. The rest is filled in from DT. */
1461
static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1462 1463 1464 1465 1466
	.tx_dma_offset = 0x400,
	.rx_dma_offset = 0x400,
	.version = MCASP_VERSION_1,
};

1467
static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1468 1469 1470 1471 1472
	.tx_dma_offset = 0x2000,
	.rx_dma_offset = 0x2000,
	.version = MCASP_VERSION_2,
};

1473
static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1474 1475 1476 1477 1478
	.tx_dma_offset = 0,
	.rx_dma_offset = 0,
	.version = MCASP_VERSION_3,
};

1479
static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1480 1481 1482 1483 1484
	.tx_dma_offset = 0x200,
	.rx_dma_offset = 0x284,
	.version = MCASP_VERSION_4,
};

1485 1486 1487
static const struct of_device_id mcasp_dt_ids[] = {
	{
		.compatible = "ti,dm646x-mcasp-audio",
1488
		.data = &dm646x_mcasp_pdata,
1489 1490 1491
	},
	{
		.compatible = "ti,da830-mcasp-audio",
1492
		.data = &da830_mcasp_pdata,
1493
	},
1494
	{
1495
		.compatible = "ti,am33xx-mcasp-audio",
1496
		.data = &am33xx_mcasp_pdata,
1497
	},
1498 1499 1500 1501
	{
		.compatible = "ti,dra7-mcasp-audio",
		.data = &dra7_mcasp_pdata,
	},
1502 1503 1504 1505
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mcasp_dt_ids);

1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545
static int mcasp_reparent_fck(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct clk *gfclk, *parent_clk;
	const char *parent_name;
	int ret;

	if (!node)
		return 0;

	parent_name = of_get_property(node, "fck_parent", NULL);
	if (!parent_name)
		return 0;

	gfclk = clk_get(&pdev->dev, "fck");
	if (IS_ERR(gfclk)) {
		dev_err(&pdev->dev, "failed to get fck\n");
		return PTR_ERR(gfclk);
	}

	parent_clk = clk_get(NULL, parent_name);
	if (IS_ERR(parent_clk)) {
		dev_err(&pdev->dev, "failed to get parent clock\n");
		ret = PTR_ERR(parent_clk);
		goto err1;
	}

	ret = clk_set_parent(gfclk, parent_clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to reparent fck\n");
		goto err2;
	}

err2:
	clk_put(parent_clk);
err1:
	clk_put(gfclk);
	return ret;
}

1546
static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1547 1548 1549
						struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
1550
	struct davinci_mcasp_pdata *pdata = NULL;
1551
	const struct of_device_id *match =
1552
			of_match_device(mcasp_dt_ids, &pdev->dev);
1553
	struct of_phandle_args dma_spec;
1554 1555 1556 1557 1558 1559 1560 1561 1562

	const u32 *of_serial_dir32;
	u32 val;
	int i, ret = 0;

	if (pdev->dev.platform_data) {
		pdata = pdev->dev.platform_data;
		return pdata;
	} else if (match) {
1563
		pdata = (struct davinci_mcasp_pdata*) match->data;
1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574
	} else {
		/* control shouldn't reach here. something is wrong */
		ret = -EINVAL;
		goto nodata;
	}

	ret = of_property_read_u32(np, "op-mode", &val);
	if (ret >= 0)
		pdata->op_mode = val;

	ret = of_property_read_u32(np, "tdm-slots", &val);
1575 1576 1577 1578 1579 1580 1581 1582
	if (ret >= 0) {
		if (val < 2 || val > 32) {
			dev_err(&pdev->dev,
				"tdm-slots must be in rage [2-32]\n");
			ret = -EINVAL;
			goto nodata;
		}

1583
		pdata->tdm_slots = val;
1584
	}
1585 1586 1587 1588

	of_serial_dir32 = of_get_property(np, "serial-dir", &val);
	val /= sizeof(u32);
	if (of_serial_dir32) {
1589 1590 1591
		u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
						 (sizeof(*of_serial_dir) * val),
						 GFP_KERNEL);
1592 1593 1594 1595 1596
		if (!of_serial_dir) {
			ret = -ENOMEM;
			goto nodata;
		}

1597
		for (i = 0; i < val; i++)
1598 1599
			of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);

1600
		pdata->num_serializer = val;
1601 1602 1603
		pdata->serial_dir = of_serial_dir;
	}

1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614
	ret = of_property_match_string(np, "dma-names", "tx");
	if (ret < 0)
		goto nodata;

	ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
					 &dma_spec);
	if (ret < 0)
		goto nodata;

	pdata->tx_dma_channel = dma_spec.args[0];

1615 1616 1617 1618 1619
	/* RX is not valid in DIT mode */
	if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
		ret = of_property_match_string(np, "dma-names", "rx");
		if (ret < 0)
			goto nodata;
1620

1621 1622 1623 1624
		ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
						 &dma_spec);
		if (ret < 0)
			goto nodata;
1625

1626 1627
		pdata->rx_dma_channel = dma_spec.args[0];
	}
1628

1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655
	ret = of_property_read_u32(np, "tx-num-evt", &val);
	if (ret >= 0)
		pdata->txnumevt = val;

	ret = of_property_read_u32(np, "rx-num-evt", &val);
	if (ret >= 0)
		pdata->rxnumevt = val;

	ret = of_property_read_u32(np, "sram-size-playback", &val);
	if (ret >= 0)
		pdata->sram_size_playback = val;

	ret = of_property_read_u32(np, "sram-size-capture", &val);
	if (ret >= 0)
		pdata->sram_size_capture = val;

	return  pdata;

nodata:
	if (ret < 0) {
		dev_err(&pdev->dev, "Error populating platform data, err %d\n",
			ret);
		pdata = NULL;
	}
	return  pdata;
}

1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698
enum {
	PCM_EDMA,
	PCM_SDMA,
};
static const char *sdma_prefix = "ti,omap";

static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
{
	struct dma_chan *chan;
	const char *tmp;
	int ret = PCM_EDMA;

	if (!mcasp->dev->of_node)
		return PCM_EDMA;

	tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
	chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
	if (IS_ERR(chan)) {
		if (PTR_ERR(chan) != -EPROBE_DEFER)
			dev_err(mcasp->dev,
				"Can't verify DMA configuration (%ld)\n",
				PTR_ERR(chan));
		return PTR_ERR(chan);
	}
	BUG_ON(!chan->device || !chan->device->dev);

	if (chan->device->dev->of_node)
		ret = of_property_read_string(chan->device->dev->of_node,
					      "compatible", &tmp);
	else
		dev_dbg(mcasp->dev, "DMA controller has no of-node\n");

	dma_release_channel(chan);
	if (ret)
		return ret;

	dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
	if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
		return PCM_SDMA;

	return PCM_EDMA;
}

1699 1700
static int davinci_mcasp_probe(struct platform_device *pdev)
{
1701
	struct snd_dmaengine_dai_dma_data *dma_data;
1702
	struct resource *mem, *res, *dat;
1703
	struct davinci_mcasp_pdata *pdata;
1704
	struct davinci_mcasp *mcasp;
1705
	char *irq_name;
1706
	int *dma;
1707
	int irq;
1708
	int ret;
1709

1710 1711 1712 1713 1714
	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
		dev_err(&pdev->dev, "No platform data supplied\n");
		return -EINVAL;
	}

1715
	mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1716
			   GFP_KERNEL);
1717
	if (!mcasp)
1718 1719
		return	-ENOMEM;

1720 1721 1722 1723 1724 1725
	pdata = davinci_mcasp_set_pdata_from_of(pdev);
	if (!pdata) {
		dev_err(&pdev->dev, "no platform data\n");
		return -EINVAL;
	}

1726
	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1727
	if (!mem) {
1728
		dev_warn(mcasp->dev,
1729 1730 1731 1732 1733 1734
			 "\"mpu\" mem resource not found, using index 0\n");
		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (!mem) {
			dev_err(&pdev->dev, "no mem resource?\n");
			return -ENODEV;
		}
1735 1736
	}

1737 1738 1739
	mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(mcasp->base))
		return PTR_ERR(mcasp->base);
1740

1741
	pm_runtime_enable(&pdev->dev);
1742

1743
	mcasp->op_mode = pdata->op_mode;
1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758
	/* sanity check for tdm slots parameter */
	if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
		if (pdata->tdm_slots < 2) {
			dev_err(&pdev->dev, "invalid tdm slots: %d\n",
				pdata->tdm_slots);
			mcasp->tdm_slots = 2;
		} else if (pdata->tdm_slots > 32) {
			dev_err(&pdev->dev, "invalid tdm slots: %d\n",
				pdata->tdm_slots);
			mcasp->tdm_slots = 32;
		} else {
			mcasp->tdm_slots = pdata->tdm_slots;
		}
	}

1759
	mcasp->num_serializer = pdata->num_serializer;
1760 1761 1762 1763 1764
#ifdef CONFIG_PM_SLEEP
	mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
					sizeof(u32) * mcasp->num_serializer,
					GFP_KERNEL);
#endif
1765 1766 1767 1768
	mcasp->serial_dir = pdata->serial_dir;
	mcasp->version = pdata->version;
	mcasp->txnumevt = pdata->txnumevt;
	mcasp->rxnumevt = pdata->rxnumevt;
1769

1770
	mcasp->dev = &pdev->dev;
1771

1772 1773
	irq = platform_get_irq_byname(pdev, "common");
	if (irq >= 0) {
1774
		irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1775 1776 1777
					  dev_name(&pdev->dev));
		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
						davinci_mcasp_common_irq_handler,
1778 1779
						IRQF_ONESHOT | IRQF_SHARED,
						irq_name, mcasp);
1780 1781 1782 1783 1784 1785 1786 1787 1788
		if (ret) {
			dev_err(&pdev->dev, "common IRQ request failed\n");
			goto err;
		}

		mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
		mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
	}

1789 1790
	irq = platform_get_irq_byname(pdev, "rx");
	if (irq >= 0) {
1791
		irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805
					  dev_name(&pdev->dev));
		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
						davinci_mcasp_rx_irq_handler,
						IRQF_ONESHOT, irq_name, mcasp);
		if (ret) {
			dev_err(&pdev->dev, "RX IRQ request failed\n");
			goto err;
		}

		mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
	}

	irq = platform_get_irq_byname(pdev, "tx");
	if (irq >= 0) {
1806
		irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818
					  dev_name(&pdev->dev));
		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
						davinci_mcasp_tx_irq_handler,
						IRQF_ONESHOT, irq_name, mcasp);
		if (ret) {
			dev_err(&pdev->dev, "TX IRQ request failed\n");
			goto err;
		}

		mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
	}

1819
	dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1820 1821
	if (dat)
		mcasp->dat_port = true;
1822

1823
	dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1824
	if (dat)
1825
		dma_data->addr = dat->start;
1826
	else
1827
		dma_data->addr = mem->start + pdata->tx_dma_offset;
1828

1829
	dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1830
	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1831
	if (res)
1832
		*dma = res->start;
1833
	else
1834
		*dma = pdata->tx_dma_channel;
1835

1836 1837 1838 1839
	/* dmaengine filter data for DT and non-DT boot */
	if (pdev->dev.of_node)
		dma_data->filter_data = "tx";
	else
1840
		dma_data->filter_data = dma;
1841

1842 1843 1844 1845
	/* RX is not valid in DIT mode */
	if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
		dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
		if (dat)
1846
			dma_data->addr = dat->start;
1847
		else
1848
			dma_data->addr = mem->start + pdata->rx_dma_offset;
1849

1850
		dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1851 1852
		res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
		if (res)
1853
			*dma = res->start;
1854
		else
1855
			*dma = pdata->rx_dma_channel;
1856 1857 1858 1859 1860

		/* dmaengine filter data for DT and non-DT boot */
		if (pdev->dev.of_node)
			dma_data->filter_data = "rx";
		else
1861
			dma_data->filter_data = dma;
1862
	}
1863

1864 1865
	if (mcasp->version < MCASP_VERSION_3) {
		mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1866
		/* dma_params->dma_addr is pointing to the data port address */
1867 1868 1869 1870
		mcasp->dat_port = true;
	} else {
		mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
	}
1871

1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893
	/* Allocate memory for long enough list for all possible
	 * scenarios. Maximum number tdm slots is 32 and there cannot
	 * be more serializers than given in the configuration.  The
	 * serializer directions could be taken into account, but it
	 * would make code much more complex and save only couple of
	 * bytes.
	 */
	mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
		devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
			     (32 + mcasp->num_serializer - 2),
			     GFP_KERNEL);

	mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
		devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
			     (32 + mcasp->num_serializer - 2),
			     GFP_KERNEL);

	if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
	    !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list)
		return -ENOMEM;

	ret = davinci_mcasp_set_ch_constraints(mcasp);
1894 1895 1896
	if (ret)
		goto err;

1897
	dev_set_drvdata(&pdev->dev, mcasp);
1898 1899 1900

	mcasp_reparent_fck(pdev);

1901 1902 1903
	ret = devm_snd_soc_register_component(&pdev->dev,
					&davinci_mcasp_component,
					&davinci_mcasp_dai[pdata->op_mode], 1);
1904 1905

	if (ret != 0)
1906
		goto err;
1907

1908 1909 1910
	ret = davinci_mcasp_get_dma_type(mcasp);
	switch (ret) {
	case PCM_EDMA:
1911 1912 1913 1914
#if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
	(IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
	 IS_MODULE(CONFIG_SND_EDMA_SOC))
		ret = edma_pcm_platform_register(&pdev->dev);
1915 1916 1917 1918
#else
		dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
		ret = -EINVAL;
		goto err;
1919
#endif
1920 1921
		break;
	case PCM_SDMA:
1922 1923 1924
#if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
	(IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
	 IS_MODULE(CONFIG_SND_OMAP_SOC))
1925
		ret = omap_pcm_platform_register(&pdev->dev);
1926 1927 1928 1929
#else
		dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
		ret = -EINVAL;
		goto err;
1930
#endif
1931
		break;
1932
	default:
1933 1934 1935
		dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
	case -EPROBE_DEFER:
		goto err;
1936 1937 1938 1939 1940
		break;
	}

	if (ret) {
		dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1941
		goto err;
1942 1943
	}

1944 1945
	return 0;

1946
err:
1947
	pm_runtime_disable(&pdev->dev);
1948 1949 1950 1951 1952
	return ret;
}

static int davinci_mcasp_remove(struct platform_device *pdev)
{
1953
	pm_runtime_disable(&pdev->dev);
1954 1955 1956 1957 1958 1959 1960 1961 1962

	return 0;
}

static struct platform_driver davinci_mcasp_driver = {
	.probe		= davinci_mcasp_probe,
	.remove		= davinci_mcasp_remove,
	.driver		= {
		.name	= "davinci-mcasp",
1963
		.of_match_table = mcasp_dt_ids,
1964 1965 1966
	},
};

1967
module_platform_driver(davinci_mcasp_driver);
1968 1969 1970 1971

MODULE_AUTHOR("Steve Chen");
MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
MODULE_LICENSE("GPL");