i915_drv.h 124.5 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include <drm/drm_cache.h>
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#include "i915_params.h"
#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_uc.h"
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#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_context.h"
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#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20170320"
#define DRIVER_TIMESTAMP	1489994464
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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typedef struct {
	uint32_t val;
} uint_fixed_16_16_t;

#define FP_16_16_MAX ({ \
	uint_fixed_16_16_t fp; \
	fp.val = UINT_MAX; \
	fp; \
})

static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
{
	uint_fixed_16_16_t fp;

	WARN_ON(val >> 16);

	fp.val = val << 16;
	return fp;
}

static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
{
	return DIV_ROUND_UP(fp.val, 1 << 16);
}

static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
{
	return fp.val >> 16;
}

static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
						 uint_fixed_16_16_t min2)
{
	uint_fixed_16_16_t min;

	min.val = min(min1.val, min2.val);
	return min;
}

static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
						 uint_fixed_16_16_t max2)
{
	uint_fixed_16_16_t max;

	max.val = max(max1.val, max2.val);
	return max;
}

static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
							  uint32_t d)
{
	uint_fixed_16_16_t fp, res;

	fp = u32_to_fixed_16_16(val);
	res.val = DIV_ROUND_UP(fp.val, d);
	return res;
}

static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
							      uint32_t d)
{
	uint_fixed_16_16_t res;
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
	WARN_ON(interm_val >> 32);
	res.val = (uint32_t) interm_val;

	return res;
}

static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
						     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;
	uint_fixed_16_16_t fp;

	intermediate_val = (uint64_t) val * mul.val;
	WARN_ON(intermediate_val >> 32);
	fp.val = (uint32_t) intermediate_val;
	return fp;
}

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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static inline const char *enableddisabled(bool v)
{
	return v ? "enabled" : "disabled";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * Global legacy plane identifier. Valid only for primary/sprite
 * planes on pre-g4x, and only for primary planes on g4x+.
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 */
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enum plane {
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	PLANE_A,
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	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
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/*
 * Per-pipe plane identifier.
 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
 *
 * This is expected to be passed to various register macros
 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 */
enum plane_id {
	PLANE_PRIMARY,
	PLANE_SPRITE0,
	PLANE_SPRITE1,
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	PLANE_SPRITE2,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
};

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#define for_each_plane_id_on_crtc(__crtc, __p) \
	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
		for_each_if ((__crtc)->plane_ids_mask & BIT(__p))

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enum port {
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	PORT_NONE = -1,
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	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
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	DPIO_PHY1,
	DPIO_PHY2,
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};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DDI_A_IO,
	POWER_DOMAIN_PORT_DDI_B_IO,
	POWER_DOMAIN_PORT_DDI_C_IO,
	POWER_DOMAIN_PORT_DDI_D_IO,
	POWER_DOMAIN_PORT_DDI_E_IO,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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#define HPD_STORM_DEFAULT_THRESHOLD 5

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	unsigned int hpd_storm_threshold;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_universal_plane(__dev_priv, __pipe, __p)		\
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	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector_iter(intel_connector, iter) \
	while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if (BIT_ULL(domain) & (mask))
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#define for_each_power_well(__dev_priv, __power_well)				\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells <	\
		(__dev_priv)->power_domains.power_well_count;		\
	     (__power_well)++)

#define for_each_power_well_rev(__dev_priv, __power_well)			\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells +		\
			      (__dev_priv)->power_domains.power_well_count - 1;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;	\
	     (__power_well)--)

#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)	\
	for_each_power_well(__dev_priv, __power_well)				\
		for_each_if ((__power_well)->domains & (__domain_mask))

#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
	for_each_power_well_rev(__dev_priv, __power_well)		        \
		for_each_if ((__power_well)->domains & (__domain_mask))

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#define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
	for ((__i) = 0; \
	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
		      (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
	     (__i)++) \
		for_each_if (plane_state)

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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	unsigned int bsd_engine;
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/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
	int context_bans;
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};

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
574 575
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
L
Linus Torvalds 已提交
576 577
 */
#define DRIVER_MAJOR		1
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
578
#define DRIVER_MINOR		6
L
Linus Torvalds 已提交
579 580
#define DRIVER_PATCHLEVEL	0

581 582 583 584 585
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

586
struct intel_opregion {
587 588 589
	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
J
Jani Nikula 已提交
590 591
	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
592
	struct opregion_asle *asle;
593
	void *rvda;
594
	const void *vbt;
595
	u32 vbt_size;
596
	u32 *lid_state;
597
	struct work_struct asle_work;
598
};
599
#define OPREGION_SIZE            (8*1024)
600

601 602 603
struct intel_overlay;
struct intel_overlay_error_state;

604
struct sdvo_device_mapping {
C
Chris Wilson 已提交
605
	u8 initialized;
606 607 608
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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Chris Wilson 已提交
609
	u8 i2c_pin;
610
	u8 ddc_pin;
611 612
};

613
struct intel_connector;
614
struct intel_encoder;
615
struct intel_atomic_state;
616
struct intel_crtc_state;
617
struct intel_initial_plane_config;
618
struct intel_crtc;
619 620
struct intel_limit;
struct dpll;
621
struct intel_cdclk_state;
622

623
struct drm_i915_display_funcs {
624 625
	void (*get_cdclk)(struct drm_i915_private *dev_priv,
			  struct intel_cdclk_state *cdclk_state);
626 627
	void (*set_cdclk)(struct drm_i915_private *dev_priv,
			  const struct intel_cdclk_state *cdclk_state);
628
	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
629
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
630 631 632
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
633 634 635 636 637 638
	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
639
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
640
	void (*update_wm)(struct intel_crtc *crtc);
641
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
642 643 644
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
645
				struct intel_crtc_state *);
646 647
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
648 649
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
650 651 652 653
	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
654 655
	void (*update_crtcs)(struct drm_atomic_state *state,
			     unsigned int *crtc_vblank_mask);
656 657
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
658
				   const struct drm_display_mode *adjusted_mode);
659
	void (*audio_codec_disable)(struct intel_encoder *encoder);
660 661
	void (*fdi_link_train)(struct intel_crtc *crtc,
			       const struct intel_crtc_state *crtc_state);
662
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
663 664 665 666 667
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
668
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
669 670 671 672 673
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
674

675 676
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
677 678
};

679 680 681 682 683 684 685 686 687
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
C
Chris Wilson 已提交
688 689 690
	FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= BIT(FW_DOMAIN_ID_MEDIA),
691 692 693 694 695
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

696 697 698
#define FW_REG_READ  (1)
#define FW_REG_WRITE (2)

699 700 701 702 703 704 705 706 707 708 709 710
enum decoupled_power_domain {
	GEN9_DECOUPLED_PD_BLITTER = 0,
	GEN9_DECOUPLED_PD_RENDER,
	GEN9_DECOUPLED_PD_MEDIA,
	GEN9_DECOUPLED_PD_ALL
};

enum decoupled_ops {
	GEN9_DECOUPLED_OP_WRITE = 0,
	GEN9_DECOUPLED_OP_READ
};

711 712 713 714
enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op);

715
struct intel_uncore_funcs {
716
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
717
			       enum forcewake_domains domains);
718
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735
			       enum forcewake_domains domains);

	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv,
			       i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv,
			       i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv,
			       i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv,
			       i915_reg_t r, bool trace);

	void (*mmio_writeb)(struct drm_i915_private *dev_priv,
			    i915_reg_t r, uint8_t val, bool trace);
	void (*mmio_writew)(struct drm_i915_private *dev_priv,
			    i915_reg_t r, uint16_t val, bool trace);
	void (*mmio_writel)(struct drm_i915_private *dev_priv,
			    i915_reg_t r, uint32_t val, bool trace);
736 737
};

738 739 740 741 742 743 744
struct intel_forcewake_range {
	u32 start;
	u32 end;

	enum forcewake_domains domains;
};

745 746 747
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

748 749 750
	const struct intel_forcewake_range *fw_domains_table;
	unsigned int fw_domains_table_entries;

751
	struct notifier_block pmic_bus_access_nb;
752 753 754
	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
755

756
	enum forcewake_domains fw_domains;
757
	enum forcewake_domains fw_domains_active;
758

759 760 761 762
	u32 fw_set;
	u32 fw_clear;
	u32 fw_reset;

763
	struct intel_uncore_forcewake_domain {
764
		enum forcewake_domain_id id;
765
		enum forcewake_domains mask;
766
		unsigned wake_count;
767
		struct hrtimer timer;
768 769
		i915_reg_t reg_set;
		i915_reg_t reg_ack;
770
	} fw_domain[FW_DOMAIN_ID_COUNT];
771 772

	int unclaimed_mmio_check;
773 774
};

C
Chris Wilson 已提交
775 776 777 778 779 780
#define __mask_next_bit(mask) ({					\
	int __idx = ffs(mask) - 1;					\
	mask &= ~BIT(__idx);						\
	__idx;								\
})

781
/* Iterate over initialised fw domains */
C
Chris Wilson 已提交
782 783 784
#define for_each_fw_domain_masked(domain__, mask__, dev_priv__, tmp__) \
	for (tmp__ = (mask__); \
	     tmp__ ? (domain__ = &(dev_priv__)->uncore.fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
785

C
Chris Wilson 已提交
786 787
#define for_each_fw_domain(domain__, dev_priv__, tmp__) \
	for_each_fw_domain_masked(domain__, (dev_priv__)->uncore.fw_domains, dev_priv__, tmp__)
788

789 790 791 792
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

793
struct intel_csr {
794
	struct work_struct work;
795
	const char *fw_path;
796
	uint32_t *dmc_payload;
797
	uint32_t dmc_fw_size;
798
	uint32_t version;
799
	uint32_t mmio_count;
800
	i915_reg_t mmioaddr[8];
801
	uint32_t mmiodata[8];
802
	uint32_t dc_state;
803
	uint32_t allowed_dc_mask;
804 805
};

806 807
#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
808
	func(is_lp); \
809
	func(is_alpha_support); \
810
	/* Keep has_* in alphabetical order */ \
811
	func(has_64bit_reloc); \
812
	func(has_aliasing_ppgtt); \
813
	func(has_csr); \
814
	func(has_ddi); \
815
	func(has_decoupled_mmio); \
816
	func(has_dp_mst); \
817 818
	func(has_fbc); \
	func(has_fpga_dbg); \
819 820
	func(has_full_ppgtt); \
	func(has_full_48bit_ppgtt); \
821 822 823 824
	func(has_gmbus_irq); \
	func(has_gmch_display); \
	func(has_guc); \
	func(has_hotplug); \
825 826
	func(has_hw_contexts); \
	func(has_l3_dpf); \
827
	func(has_llc); \
828 829 830 831 832 833 834 835 836
	func(has_logical_ring_contexts); \
	func(has_overlay); \
	func(has_pipe_cxsr); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
837
	func(has_snoop); \
838
	func(unfenced_needs_alignment); \
839 840 841
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
842
	func(supports_tv);
D
Daniel Vetter 已提交
843

844
struct sseu_dev_info {
845
	u8 slice_mask;
846
	u8 subslice_mask;
847 848
	u8 eu_total;
	u8 eu_per_subslice;
849 850 851 852 853 854
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
855 856
};

857 858 859 860 861
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

862 863 864 865 866 867 868 869 870 871 872 873 874
/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
875 876
	INTEL_I965G,
	INTEL_I965GM,
877 878
	INTEL_G45,
	INTEL_GM45,
879 880 881 882 883 884 885 886 887 888 889
	INTEL_IRONLAKE,
	INTEL_SANDYBRIDGE,
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
890
	INTEL_MAX_PLATFORMS
891 892
};

893
struct intel_device_info {
894
	u32 display_mmio_offset;
895
	u16 device_id;
896
	u8 num_pipes;
897
	u8 num_sprites[I915_MAX_PIPES];
898
	u8 num_scalers[I915_MAX_PIPES];
899
	u8 gen;
900
	u16 gen_mask;
901
	enum intel_platform platform;
902
	u8 ring_mask; /* Rings supported by the HW */
903
	u8 num_rings;
904 905 906
#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
907
	u16 ddb_size; /* in blocks */
908 909 910 911
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
912
	int cursor_offsets[I915_MAX_PIPES];
913 914

	/* Slice/subslice/EU info */
915
	struct sseu_dev_info sseu;
916 917 918 919 920

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
921 922
};

923 924
struct intel_display_error_state;

925
struct i915_gpu_state {
926 927
	struct kref ref;
	struct timeval time;
928 929
	struct timeval boottime;
	struct timeval uptime;
930

931 932
	struct drm_i915_private *i915;

933 934
	char error_msg[128];
	bool simulated;
935
	bool awake;
936 937
	bool wakelock;
	bool suspended;
938 939 940 941
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;
942
	struct i915_params params;
943 944 945 946 947

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
948
	u32 gtier[4], ngtier;
949 950 951 952 953 954 955 956 957 958 959 960
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
961

962
	u32 nfence;
963 964 965
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
966
	struct drm_i915_error_object *semaphore;
967
	struct drm_i915_error_object *guc_log;
968 969 970 971 972 973

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
974 975
		unsigned long hangcheck_timestamp;
		bool hangcheck_stalled;
976 977 978 979
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;

980 981 982
		/* position of active request inside the ring */
		u32 rq_head, rq_post, rq_tail;

983 984 985 986 987 988 989 990 991 992 993
		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
994
		u32 mode;
995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
1008
		struct intel_instdone instdone;
1009

1010 1011 1012 1013 1014 1015 1016 1017 1018 1019
		struct drm_i915_error_context {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 handle;
			u32 hw_id;
			int ban_score;
			int active;
			int guilty;
		} context;

1020 1021
		struct drm_i915_error_object {
			u64 gtt_offset;
1022
			u64 gtt_size;
1023 1024
			int page_count;
			int unused;
1025 1026 1027 1028 1029 1030 1031
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
1032
			pid_t pid;
1033
			u32 context;
1034
			int ban_score;
1035 1036 1037
			u32 seqno;
			u32 head;
			u32 tail;
1038
		} *requests, execlist[2];
1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

1074 1075
enum i915_cache_level {
	I915_CACHE_NONE = 0,
1076 1077 1078 1079 1080
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
1081
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1082 1083
};

1084 1085
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

1086 1087 1088 1089 1090
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
1091
	ORIGIN_DIRTYFB,
1092 1093
};

1094
struct intel_fbc {
P
Paulo Zanoni 已提交
1095 1096 1097
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
1098
	unsigned threshold;
1099 1100
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
1101
	unsigned int visible_pipes_mask;
1102
	struct intel_crtc *crtc;
1103

1104
	struct drm_mm_node compressed_fb;
1105 1106
	struct drm_mm_node *compressed_llb;

1107 1108
	bool false_color;

1109
	bool enabled;
1110
	bool active;
1111

1112 1113 1114
	bool underrun_detected;
	struct work_struct underrun_work;

1115
	struct intel_fbc_state_cache {
1116 1117
		struct i915_vma *vma;

1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
1131
			const struct drm_format_info *format;
1132 1133 1134 1135
			unsigned int stride;
		} fb;
	} state_cache;

1136
	struct intel_fbc_reg_params {
1137 1138
		struct i915_vma *vma;

1139 1140 1141 1142 1143 1144 1145
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
1146
			const struct drm_format_info *format;
1147 1148 1149 1150 1151 1152
			unsigned int stride;
		} fb;

		int cfb_size;
	} params;

1153
	struct intel_fbc_work {
1154
		bool scheduled;
1155
		u32 scheduled_vblank;
1156 1157
		struct work_struct work;
	} work;
1158

1159
	const char *no_fbc_reason;
1160 1161
};

1162
/*
1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1177 1178
};

1179
struct intel_dp;
1180 1181 1182 1183 1184 1185 1186 1187 1188
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

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Rodrigo Vivi 已提交
1189
struct i915_psr {
1190
	struct mutex lock;
R
Rodrigo Vivi 已提交
1191 1192
	bool sink_support;
	bool source_ok;
1193
	struct intel_dp *enabled;
1194 1195
	bool active;
	struct delayed_work work;
1196
	unsigned busy_frontbuffer_bits;
1197 1198
	bool psr2_support;
	bool aux_frame_sync;
1199
	bool link_standby;
1200 1201
	bool y_cord_support;
	bool colorimetry_support;
1202
	bool alpm;
1203
};
1204

1205
enum intel_pch {
1206
	PCH_NONE = 0,	/* No PCH present */
1207 1208
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1209
	PCH_LPT,	/* Lynxpoint PCH */
1210
	PCH_SPT,        /* Sunrisepoint PCH */
1211
	PCH_KBP,        /* Kabypoint PCH */
B
Ben Widawsky 已提交
1212
	PCH_NOP,
1213 1214
};

1215 1216 1217 1218 1219
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1220
#define QUIRK_PIPEA_FORCE (1<<0)
1221
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1222
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1223
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1224
#define QUIRK_PIPEB_FORCE (1<<4)
1225
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1226

1227
struct intel_fbdev;
1228
struct intel_fbc_work;
1229

1230 1231
struct intel_gmbus {
	struct i2c_adapter adapter;
1232
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1233
	u32 force_bit;
1234
	u32 reg0;
1235
	i915_reg_t gpio_reg;
1236
	struct i2c_algo_bit_data bit_algo;
1237 1238 1239
	struct drm_i915_private *dev_priv;
};

1240
struct i915_suspend_saved_registers {
1241
	u32 saveDSPARB;
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Jesse Barnes 已提交
1242
	u32 saveFBC_CONTROL;
1243 1244
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
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Jesse Barnes 已提交
1245 1246
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1247
	u32 saveSWF3[3];
1248
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1249
	u32 savePCH_PORT_HOTPLUG;
1250
	u16 saveGCDGMBUS;
1251
};
1252

1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1311
	u32 pcbr;
1312 1313 1314
	u32 clock_gate_dis2;
};

1315
struct intel_rps_ei {
1316
	ktime_t ktime;
1317 1318
	u32 render_c0;
	u32 media_c0;
1319 1320
};

1321
struct intel_gen6_power_mgmt {
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Imre Deak 已提交
1322 1323 1324 1325
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1326
	struct work_struct work;
I
Imre Deak 已提交
1327
	bool interrupts_enabled;
1328
	u32 pm_iir;
1329

1330
	/* PM interrupt bits that should never be masked */
1331
	u32 pm_intrmsk_mbz;
1332

1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1348
	u8 boost_freq;		/* Frequency to request when wait boosting */
1349
	u8 idle_freq;		/* Frequency to request when we are idle */
1350 1351 1352
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1353
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1354

1355 1356 1357
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1358 1359 1360
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1361 1362 1363 1364
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1365
	bool enabled;
1366
	struct delayed_work autoenable_work;
1367
	unsigned boosts;
1368

1369
	/* manual wa residency calculations */
1370
	struct intel_rps_ei ei;
1371

1372 1373
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1374 1375 1376
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1377 1378
	 */
	struct mutex hw_lock;
1379 1380
};

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Daniel Vetter 已提交
1381 1382 1383
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1395
	u64 last_time2;
1396 1397 1398 1399 1400 1401 1402
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1433 1434
/* Power well structure for haswell */
struct i915_power_well {
1435
	const char *name;
1436
	bool always_on;
1437 1438
	/* power well enable/disable usage count */
	int count;
1439 1440
	/* cached hw enabled state */
	bool hw_enabled;
1441
	u64 domains;
1442 1443
	/* unique identifier for this power well */
	unsigned long id;
1444 1445 1446 1447 1448
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
	unsigned long data;
1449
	const struct i915_power_well_ops *ops;
1450 1451
};

1452
struct i915_power_domains {
1453 1454 1455 1456 1457
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1458
	bool initializing;
1459
	int power_well_count;
1460

1461
	struct mutex lock;
1462
	int domain_use_count[POWER_DOMAIN_NUM];
1463
	struct i915_power_well *power_wells;
1464 1465
};

1466
#define MAX_L3_SLICES 2
1467
struct intel_l3_parity {
1468
	u32 *remap_info[MAX_L3_SLICES];
1469
	struct work_struct error_work;
1470
	int which_slice;
1471 1472
};

1473 1474 1475
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1476 1477 1478 1479
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1480 1481 1482 1483 1484
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
1485 1486
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
1487 1488 1489
	 */
	struct list_head unbound_list;

1490 1491 1492 1493 1494
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

1495 1496 1497 1498 1499 1500
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;

1501
	/** Usable portion of the GTT for GEM */
1502
	dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1503 1504 1505 1506

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1507
	struct notifier_block oom_notifier;
1508
	struct notifier_block vmap_notifier;
1509
	struct shrinker shrinker;
1510 1511 1512 1513 1514 1515 1516 1517 1518 1519

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1520
	/* the indicator for dispatch video commands on two BSD rings */
1521
	atomic_t bsd_engine_dispatch_index;
1522

1523 1524 1525 1526 1527 1528
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1529
	spinlock_t object_stat_lock;
1530
	u64 object_memory;
1531 1532 1533
	u32 object_count;
};

1534
struct drm_i915_error_state_buf {
1535
	struct drm_i915_private *i915;
1536 1537 1538 1539 1540 1541 1542 1543
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1544 1545 1546
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

1547 1548 1549
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

1550 1551 1552 1553
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1554

1555
	struct delayed_work hangcheck_work;
1556 1557 1558 1559

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
1560
	struct i915_gpu_state *first_error;
1561 1562 1563

	unsigned long missed_irq_rings;

1564
	/**
M
Mika Kuoppala 已提交
1565
	 * State variable controlling the reset flow and count
1566
	 *
M
Mika Kuoppala 已提交
1567
	 * This is a counter which gets incremented when reset is triggered,
1568 1569 1570 1571
	 *
	 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
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Mika Kuoppala 已提交
1572 1573 1574 1575 1576 1577 1578 1579 1580
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1581 1582 1583 1584
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1585
	 */
1586
	unsigned long reset_count;
1587

1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611
	/**
	 * flags: Control various stages of the GPU reset
	 *
	 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
	 * other users acquiring the struct_mutex. To do this we set the
	 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
	 * and then check for that bit before acquiring the struct_mutex (in
	 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
	 * secondary role in preventing two concurrent global reset attempts.
	 *
	 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
	 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
	 * but it may be held by some long running waiter (that we cannot
	 * interrupt without causing trouble). Once we are ready to do the GPU
	 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
	 * they already hold the struct_mutex and want to participate they can
	 * inspect the bit and do the reset directly, otherwise the worker
	 * waits for the struct_mutex.
	 *
	 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
	 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
	 * i915_gem_request_alloc(), this bit is checked and the sequence
	 * aborted (with -EIO reported to userspace) if set.
	 */
1612
	unsigned long flags;
1613 1614
#define I915_RESET_BACKOFF	0
#define I915_RESET_HANDOFF	1
1615
#define I915_WEDGED		(BITS_PER_LONG - 1)
1616

1617 1618 1619 1620 1621 1622
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1623 1624 1625 1626 1627
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1628

1629
	/* For missed irq/seqno simulation. */
1630
	unsigned long test_irq_rings;
1631 1632
};

1633 1634 1635 1636 1637 1638
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1639 1640 1641 1642 1643
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1644 1645 1646 1647
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1648
struct ddi_vbt_port_info {
1649 1650 1651 1652 1653 1654
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1655
	uint8_t hdmi_level_shift;
1656 1657 1658 1659

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1660
	uint8_t supports_edp:1;
1661 1662

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1663
	uint8_t alternate_ddc_pin;
1664 1665 1666

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1667 1668
};

R
Rodrigo Vivi 已提交
1669 1670 1671 1672 1673
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1674 1675
};

1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1688
	unsigned int panel_type:4;
1689 1690 1691
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1692 1693
	enum drrs_support_type drrs_type;

1694 1695 1696 1697 1698
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1699
		bool low_vswing;
1700 1701 1702 1703 1704
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1705

R
Rodrigo Vivi 已提交
1706 1707 1708 1709 1710 1711 1712 1713 1714
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1715 1716
	struct {
		u16 pwm_freq_hz;
1717
		bool present;
1718
		bool active_low_pwm;
1719
		u8 min_brightness;	/* min_brightness/255 of max */
1720
		u8 controller;		/* brightness controller number */
1721
		enum intel_backlight_type type;
1722 1723
	} backlight;

1724 1725 1726
	/* MIPI DSI */
	struct {
		u16 panel_id;
1727 1728 1729 1730 1731
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1732
		const u8 *sequence[MIPI_SEQ_MAX];
1733 1734
	} dsi;

1735 1736 1737
	int crt_ddc_pin;

	int child_dev_num;
1738
	union child_device_config *child_dev;
1739 1740

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1741
	struct sdvo_device_mapping sdvo_mappings[2];
1742 1743
};

1744 1745 1746 1747 1748
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1749 1750 1751 1752 1753 1754 1755 1756
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1757
struct ilk_wm_values {
1758 1759 1760 1761 1762 1763 1764 1765
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1766
struct vlv_pipe_wm {
1767
	uint16_t plane[I915_MAX_PLANES];
1768
};
1769

1770 1771
struct vlv_sr_wm {
	uint16_t plane;
1772 1773 1774 1775 1776
	uint16_t cursor;
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1777
};
1778

1779 1780 1781
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1782
	struct vlv_wm_ddl_values ddl[3];
1783 1784
	uint8_t level;
	bool cxsr;
1785 1786
};

1787
struct skl_ddb_entry {
1788
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1789 1790 1791 1792
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1793
	return entry->end - entry->start;
1794 1795
}

1796 1797 1798 1799 1800 1801 1802 1803 1804
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1805
struct skl_ddb_allocation {
1806
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1807
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1808 1809
};

1810
struct skl_wm_values {
1811
	unsigned dirty_pipes;
1812
	struct skl_ddb_allocation ddb;
1813 1814 1815
};

struct skl_wm_level {
L
Lyude 已提交
1816 1817 1818
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1819 1820
};

1821
/*
1822 1823 1824 1825
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1826
 *
1827 1828 1829
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1830
 *
1831 1832
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1833
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1834
 * it can be changed with the standard runtime PM files from sysfs.
1835 1836 1837 1838 1839
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1840
 * case it happens.
1841
 *
1842
 * For more, read the Documentation/power/runtime_pm.txt.
1843
 */
1844
struct i915_runtime_pm {
1845
	atomic_t wakeref_count;
1846
	bool suspended;
1847
	bool irqs_enabled;
1848 1849
};

1850 1851 1852 1853 1854
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1855
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1856 1857 1858 1859 1860
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1861
	INTEL_PIPE_CRC_SOURCE_AUTO,
1862 1863 1864
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1865
struct intel_pipe_crc_entry {
1866
	uint32_t frame;
1867 1868 1869
	uint32_t crc[5];
};

1870
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1871
struct intel_pipe_crc {
1872 1873
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1874
	struct intel_pipe_crc_entry *entries;
1875
	enum intel_pipe_crc_source source;
1876
	int head, tail;
1877
	wait_queue_head_t wq;
T
Tomeu Vizoso 已提交
1878
	int skipped;
1879 1880
};

1881
struct i915_frontbuffer_tracking {
1882
	spinlock_t lock;
1883 1884 1885 1886 1887 1888 1889 1890 1891

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1892
struct i915_wa_reg {
1893
	i915_reg_t addr;
1894 1895 1896 1897 1898
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1899 1900 1901 1902 1903 1904 1905
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1906 1907 1908 1909

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1910
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1911 1912
};

1913 1914 1915 1916
struct i915_virtual_gpu {
	bool active;
};

1917 1918 1919 1920 1921 1922 1923
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1924 1925 1926 1927 1928
struct i915_oa_format {
	u32 format;
	int size;
};

1929 1930 1931 1932 1933
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1934 1935
struct i915_perf_stream;

1936 1937 1938
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
1939
struct i915_perf_stream_ops {
1940 1941 1942 1943
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
1944 1945 1946
	 */
	void (*enable)(struct i915_perf_stream *stream);

1947 1948 1949 1950
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
1951 1952 1953
	 */
	void (*disable)(struct i915_perf_stream *stream);

1954 1955
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1956 1957 1958 1959 1960 1961
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

1962 1963 1964
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
1965
	 * wait queue that would be passed to poll_wait().
1966 1967 1968
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

1969 1970 1971 1972 1973 1974 1975
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
1976
	 *
1977 1978
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
1979
	 *
1980 1981
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
1982
	 *
1983 1984 1985
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
1986 1987 1988 1989 1990 1991
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

1992 1993
	/**
	 * @destroy: Cleanup any stream specific resources.
1994 1995 1996 1997 1998 1999
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

2000 2001 2002
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
2003
struct i915_perf_stream {
2004 2005 2006
	/**
	 * @dev_priv: i915 drm device
	 */
2007 2008
	struct drm_i915_private *dev_priv;

2009 2010 2011
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
2012 2013
	struct list_head link;

2014 2015 2016 2017 2018
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
2019
	u32 sample_flags;
2020 2021 2022 2023 2024 2025

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
2026
	int sample_size;
2027

2028 2029 2030 2031
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
2032
	struct i915_gem_context *ctx;
2033 2034 2035 2036 2037 2038

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
2039 2040
	bool enabled;

2041 2042 2043 2044
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
2045 2046 2047
	const struct i915_perf_stream_ops *ops;
};

2048 2049 2050
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
2051
struct i915_oa_ops {
2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066
	/**
	 * @init_oa_buffer: Resets the head and tail pointers of the
	 * circular buffer for periodic OA reports.
	 *
	 * Called when first opening a stream for OA metrics, but also may be
	 * called in response to an OA buffer overflow or other error
	 * condition.
	 *
	 * Note it may be necessary to clear the full OA buffer here as part of
	 * maintaining the invariable that new reports must be written to
	 * zeroed memory for us to be able to reliable detect if an expected
	 * report has not yet landed in memory.  (At least on Haswell the OA
	 * buffer tail pointer is not synchronized with reports being visible
	 * to the CPU)
	 */
2067
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2068 2069 2070 2071 2072 2073 2074

	/**
	 * @enable_metric_set: Applies any MUX configuration to set up the
	 * Boolean and Custom (B/C) counters that are part of the counter
	 * reports being sampled. May apply system constraints such as
	 * disabling EU clock gating as required.
	 */
2075
	int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2076 2077 2078 2079 2080

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
2081
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2082 2083 2084 2085

	/**
	 * @oa_enable: Enable periodic sampling
	 */
2086
	void (*oa_enable)(struct drm_i915_private *dev_priv);
2087 2088 2089 2090

	/**
	 * @oa_disable: Disable periodic sampling
	 */
2091
	void (*oa_disable)(struct drm_i915_private *dev_priv);
2092 2093 2094 2095 2096

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
2097 2098 2099 2100
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115

	/**
	 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
	 *
	 * This is either called via fops or the poll check hrtimer (atomic
	 * ctx) without any locks taken.
	 *
	 * It's safe to read OA config state here unlocked, assuming that this
	 * is only called while the stream is enabled, while the global OA
	 * configuration can't be modified.
	 *
	 * Efficiency is more important than avoiding some false positives
	 * here, which will be handled gracefully - likely resulting in an
	 * %EAGAIN error for userspace.
	 */
2116
	bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2117 2118
};

2119 2120 2121 2122
struct intel_cdclk_state {
	unsigned int cdclk, vco, ref;
};

2123
struct drm_i915_private {
2124 2125
	struct drm_device drm;

2126
	struct kmem_cache *objects;
2127
	struct kmem_cache *vmas;
2128
	struct kmem_cache *requests;
2129
	struct kmem_cache *dependencies;
2130

2131
	const struct intel_device_info info;
2132 2133 2134

	void __iomem *regs;

2135
	struct intel_uncore uncore;
2136

2137 2138
	struct i915_virtual_gpu vgpu;

2139
	struct intel_gvt *gvt;
2140

2141
	struct intel_huc huc;
2142 2143
	struct intel_guc guc;

2144 2145
	struct intel_csr csr;

2146
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2147

2148 2149 2150 2151 2152 2153 2154 2155 2156
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

2157 2158 2159
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

2160 2161
	uint32_t psr_mmio_base;

2162 2163
	uint32_t pps_mmio_base;

2164 2165
	wait_queue_head_t gmbus_wait_queue;

2166
	struct pci_dev *bridge_dev;
2167
	struct i915_gem_context *kernel_context;
2168
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
2169
	struct i915_vma *semaphore;
2170

2171
	struct drm_dma_handle *status_page_dmah;
2172 2173 2174 2175 2176
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

2177 2178 2179
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

2180 2181
	bool display_irqs_enabled;

2182 2183 2184
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
2185 2186
	/* Sideband mailbox protection */
	struct mutex sb_lock;
2187 2188

	/** Cached value of IMR to avoid reads in updating the bitfield */
2189 2190 2191 2192
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
2193
	u32 gt_irq_mask;
2194 2195
	u32 pm_imr;
	u32 pm_ier;
2196
	u32 pm_rps_events;
2197
	u32 pm_guc_events;
2198
	u32 pipestat_irq_mask[I915_MAX_PIPES];
2199

2200
	struct i915_hotplug hotplug;
2201
	struct intel_fbc fbc;
2202
	struct i915_drrs drrs;
2203
	struct intel_opregion opregion;
2204
	struct intel_vbt_data vbt;
2205

2206 2207
	bool preserve_bios_swizzle;

2208 2209 2210
	/* overlay */
	struct intel_overlay *overlay;

2211
	/* backlight registers and fields in struct intel_panel */
2212
	struct mutex backlight_lock;
2213

2214 2215 2216
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
2217 2218 2219
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

2220 2221 2222 2223
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
2224
	unsigned int skl_preferred_vco_freq;
2225
	unsigned int max_cdclk_freq;
2226

M
Mika Kahola 已提交
2227
	unsigned int max_dotclk_freq;
2228
	unsigned int rawclk_freq;
2229
	unsigned int hpll_freq;
2230
	unsigned int czclk_freq;
2231

2232
	struct {
2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246
		/*
		 * The current logical cdclk state.
		 * See intel_atomic_state.cdclk.logical
		 *
		 * For reading holding any crtc lock is sufficient,
		 * for writing must hold all of them.
		 */
		struct intel_cdclk_state logical;
		/*
		 * The current actual cdclk state.
		 * See intel_atomic_state.cdclk.actual
		 */
		struct intel_cdclk_state actual;
		/* The current hardware cdclk state */
2247 2248
		struct intel_cdclk_state hw;
	} cdclk;
2249

2250 2251 2252 2253 2254 2255 2256
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
2257 2258 2259 2260 2261 2262 2263
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
2264
	unsigned short pch_id;
2265 2266 2267

	unsigned long quirks;

2268 2269
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
2270
	struct drm_atomic_state *modeset_restore_state;
2271
	struct drm_modeset_acquire_ctx reset_ctx;
2272

2273
	struct list_head vm_list; /* Global list of all address spaces */
2274
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
2275

2276
	struct i915_gem_mm mm;
2277 2278
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
2279

2280 2281 2282 2283 2284 2285 2286
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

2287 2288
	/* Kernel Modesetting */

2289 2290
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2291 2292
	wait_queue_head_t pending_flip_queue;

2293 2294 2295 2296
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

2297
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
2298 2299
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2300
	const struct intel_dpll_mgr *dpll_mgr;
2301

2302 2303 2304 2305 2306 2307 2308
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

2309 2310 2311
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

2312
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2313

2314
	struct i915_workarounds workarounds;
2315

2316 2317
	struct i915_frontbuffer_tracking fb_tracking;

2318 2319 2320 2321 2322
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

2323
	u16 orig_clock;
2324

2325
	bool mchbar_need_disable;
2326

2327 2328
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
2329
	/* Cannot be determined by PCIID. You must always read a register. */
2330
	u32 edram_cap;
B
Ben Widawsky 已提交
2331

2332
	/* gen6+ rps state */
2333
	struct intel_gen6_power_mgmt rps;
2334

2335 2336
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
2337
	struct intel_ilk_power_mgmt ips;
2338

2339
	struct i915_power_domains power_domains;
2340

R
Rodrigo Vivi 已提交
2341
	struct i915_psr psr;
2342

2343
	struct i915_gpu_error gpu_error;
2344

2345 2346
	struct drm_i915_gem_object *vlv_pctx;

2347
#ifdef CONFIG_DRM_FBDEV_EMULATION
2348 2349
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
2350
	struct work_struct fbdev_suspend_work;
2351
#endif
2352 2353

	struct drm_property *broadcast_rgb_property;
2354
	struct drm_property *force_audio_property;
2355

I
Imre Deak 已提交
2356
	/* hda/i915 audio component */
2357
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
2358
	bool audio_component_registered;
2359 2360 2361 2362 2363
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
2364

2365
	uint32_t hw_context_size;
2366
	struct list_head context_list;
2367

2368
	u32 fdi_rx_config;
2369

2370
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2371
	u32 chv_phy_control;
2372 2373 2374 2375 2376 2377
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
2378
	u32 bxt_phy_grc;
2379

2380
	u32 suspend_count;
2381
	bool suspended_to_idle;
2382
	struct i915_suspend_saved_registers regfile;
2383
	struct vlv_s0ix_state vlv_s0ix_state;
2384

2385
	enum {
2386 2387 2388 2389 2390
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
2391

2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2404 2405 2406 2407 2408 2409
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2410 2411

		/* current hardware state */
2412 2413 2414
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2415
			struct vlv_wm_values vlv;
2416
		};
2417 2418

		uint8_t max_level;
2419 2420 2421 2422 2423 2424 2425

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2426 2427 2428 2429 2430 2431 2432

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2433 2434
	} wm;

2435 2436
	struct i915_runtime_pm pm;

2437 2438
	struct {
		bool initialized;
2439

2440
		struct kobject *metrics_kobj;
2441
		struct ctl_table_header *sysctl_header;
2442

2443 2444
		struct mutex lock;
		struct list_head streams;
2445

2446 2447
		spinlock_t hook_lock;

2448
		struct {
2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

			bool periodic;
			int period_exponent;
			int timestamp_frequency;

			int tail_margin;

			int metrics_set;
2464 2465 2466 2467 2468

			const struct i915_oa_reg *mux_regs;
			int mux_regs_len;
			const struct i915_oa_reg *b_counter_regs;
			int b_counter_regs_len;
2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
				int format;
				int format_size;
			} oa_buffer;

			u32 gen7_latched_oastatus1;

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
			int n_builtin_sets;
2482
		} oa;
2483 2484
	} perf;

2485 2486
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2487
		void (*resume)(struct drm_i915_private *);
2488
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2489

2490 2491
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2492
		u32 active_requests;
2493

2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2520 2521

		ktime_t last_init_time;
2522 2523
	} gt;

2524 2525 2526
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2527 2528
	bool ipc_enabled;

2529 2530
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2531

2532 2533 2534 2535 2536 2537
	/* necessary resource sharing with HDMI LPE audio driver. */
	struct {
		struct platform_device *platdev;
		int	irq;
	} lpe_audio;

2538 2539 2540 2541
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2542
};
L
Linus Torvalds 已提交
2543

2544 2545
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2546
	return container_of(dev, struct drm_i915_private, drm);
2547 2548
}

2549
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2550
{
2551
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2552 2553
}

2554 2555 2556 2557 2558
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

A
Arkadiusz Hiler 已提交
2559 2560 2561 2562 2563
static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
{
	return container_of(huc, struct drm_i915_private, huc);
}

2564
/* Simple iterator over all initialised engines */
2565 2566 2567 2568 2569
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2570 2571

/* Iterator over subset of engines selected by mask */
2572 2573
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
2574
	     tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2575

2576 2577 2578 2579 2580 2581 2582
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2583
#define I915_GTT_OFFSET_NONE ((u32)-1)
2584

2585 2586
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2587
 * considered to be the frontbuffer for the given plane interface-wise. This
2588 2589 2590 2591 2592
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2593 2594
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2595 2596 2597
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2598 2599 2600
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2601
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2602
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2603
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2604
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2605

2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2632 2633 2634 2635 2636 2637 2638 2639
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2654
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2655 2656
}

2657 2658 2659 2660 2661 2662 2663 2664 2665 2666
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2667
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2680
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2681

2682 2683 2684 2685 2686 2687 2688
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2689

2690
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2691
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2692

2693
#define REVID_FOREVER		0xff
2694
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2695 2696 2697 2698 2699 2700 2701

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2702
#define IS_GEN(dev_priv, s, e) ({ \
2703 2704 2705 2706 2707 2708 2709 2710 2711
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
2712
	!!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2713 2714
})

2715 2716 2717 2718 2719 2720 2721 2722
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2723 2724
#define IS_I830(dev_priv)	((dev_priv)->info.platform == INTEL_I830)
#define IS_I845G(dev_priv)	((dev_priv)->info.platform == INTEL_I845G)
2725
#define IS_I85X(dev_priv)	((dev_priv)->info.platform == INTEL_I85X)
2726
#define IS_I865G(dev_priv)	((dev_priv)->info.platform == INTEL_I865G)
2727
#define IS_I915G(dev_priv)	((dev_priv)->info.platform == INTEL_I915G)
2728 2729
#define IS_I915GM(dev_priv)	((dev_priv)->info.platform == INTEL_I915GM)
#define IS_I945G(dev_priv)	((dev_priv)->info.platform == INTEL_I945G)
2730
#define IS_I945GM(dev_priv)	((dev_priv)->info.platform == INTEL_I945GM)
2731 2732
#define IS_I965G(dev_priv)	((dev_priv)->info.platform == INTEL_I965G)
#define IS_I965GM(dev_priv)	((dev_priv)->info.platform == INTEL_I965GM)
2733 2734 2735
#define IS_G45(dev_priv)	((dev_priv)->info.platform == INTEL_G45)
#define IS_GM45(dev_priv)	((dev_priv)->info.platform == INTEL_GM45)
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2736 2737
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
2738
#define IS_PINEVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_PINEVIEW)
2739
#define IS_G33(dev_priv)	((dev_priv)->info.platform == INTEL_G33)
2740
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
2741
#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2742 2743 2744
#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
				 INTEL_DEVID(dev_priv) == 0x0152 || \
				 INTEL_DEVID(dev_priv) == 0x015a)
2745 2746 2747 2748 2749 2750 2751 2752
#define IS_VALLEYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	((dev_priv)->info.platform == INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	((dev_priv)->info.platform == INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
2753
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2754 2755 2756 2757 2758 2759
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2760
/* ULX machines are also considered ULT. */
2761 2762 2763 2764 2765 2766 2767 2768
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2769
/* ULX machines are also considered ULT. */
2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2792

2793
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2794

2795 2796 2797 2798 2799 2800
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2801 2802
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2803

2804 2805
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2806
#define BXT_REVID_A0		0x0
2807
#define BXT_REVID_A1		0x1
2808
#define BXT_REVID_B0		0x3
2809
#define BXT_REVID_B_LAST	0x8
2810
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2811

2812 2813
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2814

M
Mika Kuoppala 已提交
2815 2816
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2817 2818 2819
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2820

2821 2822
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2823

2824 2825 2826 2827 2828 2829
#define GLK_REVID_A0		0x0
#define GLK_REVID_A1		0x1

#define IS_GLK_REVID(dev_priv, since, until) \
	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

2830 2831 2832 2833 2834 2835
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2836 2837 2838 2839 2840 2841 2842 2843
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2844

2845
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
2846 2847
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2848

2849 2850 2851 2852 2853 2854 2855 2856 2857
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2858
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2859 2860 2861 2862 2863 2864

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2865 2866 2867
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2868 2869
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2870

2871
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2872

2873 2874 2875 2876 2877 2878 2879 2880 2881 2882
#define HAS_HW_CONTEXTS(dev_priv)	    ((dev_priv)->info.has_hw_contexts)
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2883

2884
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2885
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2886 2887

/* WaRsDisableCoarsePowerGating:skl,bxt */
2888
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2889
	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2890

2891 2892 2893 2894 2895 2896
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
2897 2898
#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2899

2900 2901 2902
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2903 2904 2905
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2906 2907
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2908

2909 2910 2911
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2912

2913
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2914

2915
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2916

2917 2918 2919 2920 2921
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
P
Paulo Zanoni 已提交
2922

2923
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2924

2925
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2926 2927
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2928 2929 2930 2931 2932
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2933 2934 2935
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2936
#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
2937

2938
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2939

2940
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2941

2942 2943 2944 2945 2946 2947
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2948 2949
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2950
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2951
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2952
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2953
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2954

2955 2956 2957 2958
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2959 2960 2961 2962
#define HAS_PCH_LPT_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2963 2964 2965 2966
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2967

2968
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2969

2970 2971
#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))

2972
/* DPF == dynamic parity feature */
2973
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2974 2975
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
2976

2977
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2978
#define GEN9_FREQ_SCALER 3
2979

2980 2981
#define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)

2982 2983
#include "i915_trace.h"

2984 2985 2986 2987 2988 2989 2990 2991 2992
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

2993
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2994
				int enable_ppgtt);
2995

2996 2997
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

2998
/* i915_drv.c */
2999 3000 3001 3002 3003 3004 3005
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

3006
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
3007 3008
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
3009 3010
#else
#define i915_compat_ioctl NULL
3011
#endif
3012 3013 3014 3015 3016
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
3017 3018
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3019
extern void i915_reset(struct drm_i915_private *dev_priv);
3020
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3021
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3022
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3023 3024 3025 3026
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3027
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3028

3029 3030 3031
int intel_engines_init_early(struct drm_i915_private *dev_priv);
int intel_engines_init(struct drm_i915_private *dev_priv);

3032
/* intel_hotplug.c */
3033 3034
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
3035 3036 3037
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3038
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3039 3040
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3041

L
Linus Torvalds 已提交
3042
/* i915_irq.c */
3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

3060
__printf(3, 4)
3061 3062
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
3063
		       const char *fmt, ...);
L
Linus Torvalds 已提交
3064

3065
extern void intel_irq_init(struct drm_i915_private *dev_priv);
3066 3067
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3068

3069 3070
extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3071
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3072
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3073
extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
3074 3075
extern void intel_uncore_suspend(struct drm_i915_private *dev_priv);
extern void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
3076
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3077
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3078
				enum forcewake_domains domains);
3079
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3080
				enum forcewake_domains domains);
3081 3082 3083 3084 3085 3086 3087
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
3088 3089
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

3090
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3091

3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102
int intel_wait_for_register(struct drm_i915_private *dev_priv,
			    i915_reg_t reg,
			    const u32 mask,
			    const u32 value,
			    const unsigned long timeout_ms);
int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
			       i915_reg_t reg,
			       const u32 mask,
			       const u32 value,
			       const unsigned long timeout_ms);

3103 3104
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
3105
	return dev_priv->gvt;
3106 3107
}

3108
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3109
{
3110
	return dev_priv->vgpu.active;
3111
}
3112

3113
void
3114
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3115
		     u32 status_mask);
3116 3117

void
3118
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3119
		      u32 status_mask);
3120

3121 3122
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3123 3124 3125
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
3153 3154 3155
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

3167 3168 3169 3170 3171 3172 3173 3174 3175
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3176 3177
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3178 3179 3180 3181 3182 3183
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3184 3185
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3186 3187
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3188 3189 3190 3191
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3192 3193
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3194 3195
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3196 3197 3198 3199
int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
3200
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3201 3202
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3203 3204
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3205 3206
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3207
void i915_gem_sanitize(struct drm_i915_private *i915);
3208 3209
int i915_gem_load_init(struct drm_i915_private *dev_priv);
void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3210
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3211
int i915_gem_freeze(struct drm_i915_private *dev_priv);
3212 3213
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3214
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3215
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3216 3217
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3218 3219 3220 3221 3222
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
3223
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3224
void i915_gem_free_object(struct drm_gem_object *obj);
3225

3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
	/* A single pass should suffice to release all the freed objects (along
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
	do {
		rcu_barrier();
	} while (flush_work(&i915->mm.free_work));
}

C
Chris Wilson 已提交
3239
struct i915_vma * __must_check
3240 3241
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3242
			 u64 size,
3243 3244
			 u64 alignment,
			 u64 flags);
3245

3246
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3247
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3248

3249 3250
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
3251
static inline int __sg_page_count(const struct scatterlist *sg)
3252
{
3253 3254
	return sg->length >> PAGE_SHIFT;
}
3255

3256 3257 3258
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
3259

3260 3261 3262
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
3263

3264 3265 3266
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
3267

3268 3269 3270
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
3271

3272 3273
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
				 struct sg_table *pages);
C
Chris Wilson 已提交
3274 3275 3276 3277 3278
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
3279
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
3280

3281
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
3282 3283 3284 3285 3286 3287 3288
		return 0;

	return __i915_gem_object_get_pages(obj);
}

static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3289
{
C
Chris Wilson 已提交
3290 3291
	GEM_BUG_ON(!obj->mm.pages);

3292
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3293 3294 3295 3296 3297
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3298
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3299 3300 3301 3302 3303 3304 3305 3306
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
	GEM_BUG_ON(!obj->mm.pages);

3307
	atomic_dec(&obj->mm.pages_pin_count);
3308
}
3309

3310 3311
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3312
{
C
Chris Wilson 已提交
3313
	__i915_gem_object_unpin_pages(obj);
3314 3315
}

3316 3317 3318 3319 3320 3321 3322
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3323
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3324

3325 3326 3327 3328 3329
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
};

3330 3331
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3332 3333
 * @obj: the object to map into kernel address space
 * @type: the type of mapping, used to select pgprot_t
3334 3335 3336
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3337 3338
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3339
 *
3340 3341
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3342
 *
3343 3344
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3345
 */
3346 3347
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3348 3349 3350

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
3351
 * @obj: the object to unmap
3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3363 3364 3365 3366
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
3367 3368 3369
#define CLFLUSH_BEFORE	BIT(0)
#define CLFLUSH_AFTER	BIT(1)
#define CLFLUSH_FLAGS	(CLFLUSH_BEFORE | CLFLUSH_AFTER)
3370 3371 3372 3373 3374 3375 3376

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3377
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3378
void i915_vma_move_to_active(struct i915_vma *vma,
3379 3380
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3381 3382 3383
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3384 3385
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3386
int i915_gem_mmap_gtt_version(void);
3387 3388 3389 3390 3391

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3392
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3393

3394
struct drm_i915_gem_request *
3395
i915_gem_find_active_request(struct intel_engine_cs *engine);
3396

3397
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3398

3399 3400 3401 3402 3403 3404
static inline bool i915_reset_backoff(struct i915_gpu_error *error)
{
	return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
}

static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3405
{
3406
	return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3407 3408
}

3409
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3410
{
3411
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3412 3413
}

3414
static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3415
{
3416
	return i915_reset_backoff(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3417 3418 3419 3420
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3421
	return READ_ONCE(error->reset_count);
3422
}
3423

3424
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3425
void i915_gem_reset(struct drm_i915_private *dev_priv);
3426
void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3427
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3428
bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3429

3430
void i915_gem_init_mmio(struct drm_i915_private *i915);
3431 3432
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3433
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3434
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3435 3436
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
			   unsigned int flags);
3437 3438
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3439
int i915_gem_fault(struct vm_fault *vmf);
3440 3441 3442 3443
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3444 3445 3446 3447 3448
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3449
int __must_check
3450 3451 3452
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3453
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3454
struct i915_vma * __must_check
3455 3456
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3457
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3458
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3459
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3460
				int align);
3461
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3462
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3463

3464 3465 3466
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3467 3468 3469 3470 3471 3472
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3473 3474 3475 3476 3477 3478
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

J
Joonas Lahtinen 已提交
3479
/* i915_gem_fence_reg.c */
3480 3481 3482
int __must_check i915_vma_get_fence(struct i915_vma *vma);
int __must_check i915_vma_put_fence(struct i915_vma *vma);

3483
void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3484
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3485

3486
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3487 3488 3489 3490
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3491

3492 3493 3494 3495 3496
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3497
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3498 3499 3500 3501 3502 3503 3504 3505

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3506 3507
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3508
{
3509
	kref_get(&ctx->ref);
3510
	return ctx;
3511 3512
}

3513
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3514
{
3515
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3516
	kref_put(&ctx->ref, i915_gem_context_free);
3517 3518
}

3519 3520
static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
{
3521 3522 3523 3524
	struct mutex *lock = &ctx->i915->drm.struct_mutex;

	if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
		mutex_unlock(lock);
3525 3526
}

C
Chris Wilson 已提交
3527 3528 3529 3530 3531 3532 3533 3534 3535 3536
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3537 3538 3539
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);

3540
/* i915_gem_evict.c */
3541
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3542
					  u64 min_size, u64 alignment,
3543
					  unsigned cache_level,
3544
					  u64 start, u64 end,
3545
					  unsigned flags);
3546 3547 3548
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
3549
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3550

3551
/* belongs in i915_gem_gtt.h */
3552
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3553
{
3554
	wmb();
3555
	if (INTEL_GEN(dev_priv) < 6)
3556 3557
		intel_gtt_chipset_flush();
}
3558

3559
/* i915_gem_stolen.c */
3560 3561 3562
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3563 3564 3565 3566
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3567 3568
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3569
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3570
void i915_gem_cleanup_stolen(struct drm_device *dev);
3571
struct drm_i915_gem_object *
3572
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3573
struct drm_i915_gem_object *
3574
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3575 3576 3577
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3578

3579 3580 3581
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3582
				phys_addr_t size);
3583

3584 3585
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3586
			      unsigned long target,
3587 3588 3589 3590
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3591
#define I915_SHRINK_ACTIVE 0x8
3592
#define I915_SHRINK_VMAPS 0x10
3593 3594
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3595
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3596 3597


3598
/* i915_gem_tiling.c */
3599
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3600
{
3601
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3602 3603

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3604
		i915_gem_object_is_tiled(obj);
3605 3606
}

3607 3608 3609 3610 3611
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

3612
/* i915_debugfs.c */
3613
#ifdef CONFIG_DEBUG_FS
3614
int i915_debugfs_register(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3615
int i915_debugfs_connector_add(struct drm_connector *connector);
3616
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3617
#else
3618
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3619 3620
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3621
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3622
#endif
3623 3624

/* i915_gpu_error.c */
3625 3626
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

3627 3628
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3629
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3630
			    const struct i915_gpu_state *gpu);
3631
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3632
			      struct drm_i915_private *i915,
3633 3634 3635 3636 3637 3638
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3639 3640

struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3641 3642
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3643
			      const char *error_msg);
3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660

static inline struct i915_gpu_state *
i915_gpu_state_get(struct i915_gpu_state *gpu)
{
	kref_get(&gpu->ref);
	return gpu;
}

void __i915_gpu_state_free(struct kref *kref);
static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
{
	if (gpu)
		kref_put(&gpu->ref, __i915_gpu_state_free);
}

struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
void i915_reset_error_state(struct drm_i915_private *i915);
3661

3662 3663 3664 3665 3666 3667 3668 3669
#else

static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
					    u32 engine_mask,
					    const char *error_msg)
{
}

3670 3671 3672 3673 3674 3675 3676
static inline struct i915_gpu_state *
i915_first_error_state(struct drm_i915_private *i915)
{
	return NULL;
}

static inline void i915_reset_error_state(struct drm_i915_private *i915)
3677 3678 3679 3680 3681
{
}

#endif

3682
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3683

3684
/* i915_cmd_parser.c */
3685
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3686
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3687 3688 3689 3690 3691 3692 3693
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3694

3695 3696 3697
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3698 3699
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3700

3701
/* i915_suspend.c */
3702 3703
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3704

B
Ben Widawsky 已提交
3705
/* i915_sysfs.c */
D
David Weinehall 已提交
3706 3707
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3708

3709 3710 3711 3712
/* intel_lpe_audio.c */
int  intel_lpe_audio_init(struct drm_i915_private *dev_priv);
void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3713
void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3714
			    void *eld, int port, int pipe, int tmds_clk_speed,
3715
			    bool dp_output, int link_rate);
3716

3717
/* intel_i2c.c */
3718 3719
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3720 3721
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3722

3723 3724
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3725 3726
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3727
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3728 3729 3730
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3731
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3732

3733
/* intel_bios.c */
3734
void intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3735
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3736
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3737
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3738
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3739
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3740
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3741
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3742 3743
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3744 3745 3746
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

3747

3748
/* intel_opregion.c */
3749
#ifdef CONFIG_ACPI
3750
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3751 3752
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3753
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3754 3755
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3756
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3757
					 pci_power_t state);
3758
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3759
#else
3760
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3761 3762
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3763 3764 3765
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3766 3767 3768 3769 3770
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3771
static inline int
3772
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3773 3774 3775
{
	return 0;
}
3776
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3777 3778 3779
{
	return -ENODEV;
}
3780
#endif
3781

J
Jesse Barnes 已提交
3782 3783 3784 3785 3786 3787 3788 3789 3790
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3791 3792 3793 3794 3795 3796 3797
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

3798
const char *intel_platform_name(enum intel_platform platform);
3799 3800 3801
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3802
/* modesetting */
3803
extern void intel_modeset_init_hw(struct drm_device *dev);
3804
extern int intel_modeset_init(struct drm_device *dev);
3805
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3806
extern void intel_modeset_cleanup(struct drm_device *dev);
3807
extern int intel_connector_register(struct drm_connector *);
3808
extern void intel_connector_unregister(struct drm_connector *);
3809 3810
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
3811
extern void intel_display_resume(struct drm_device *dev);
3812 3813
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3814
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3815
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3816
extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3817
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3818
				  bool enable);
3819

B
Ben Widawsky 已提交
3820 3821
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3822

3823
/* overlay */
3824 3825
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3826 3827
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3828

3829 3830
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3831
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3832
					    struct intel_display_error_state *error);
3833

3834 3835
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3836 3837
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms);
3838 3839

/* intel_sideband.c */
3840
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3841
int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3842
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3843 3844
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3845 3846 3847 3848
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3849 3850
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3851 3852
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3853 3854 3855 3856
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3857 3858
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3859

3860
/* intel_dpio_phy.c */
3861
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3862
			     enum dpio_phy *phy, enum dpio_channel *ch);
3863 3864 3865
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
					     uint8_t lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3878 3879 3880
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3881 3882
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3883
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3884 3885
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3886
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3887

3888 3889 3890
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3891
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3892
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3893
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3894

3895 3896
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3897 3898
u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
			   const i915_reg_t reg);
3899

3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3913 3914 3915 3916
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3917 3918 3919 3920 3921 3922 3923 3924 3925
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3926
 */
3927
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3928

3929
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3930 3931
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3932
	do {								\
3933
		old_upper = upper;					\
3934
		lower = I915_READ(lower_reg);				\
3935 3936
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3937
	(u64)upper << 32 | lower; })
3938

3939 3940 3941
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3942
#define __raw_read(x, s) \
3943
static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3944
					     i915_reg_t reg) \
3945
{ \
3946
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3947 3948 3949
}

#define __raw_write(x, s) \
3950
static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3951
				       i915_reg_t reg, uint##x##_t val) \
3952
{ \
3953
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3968
/* These are untraced mmio-accessors that are only valid to be used inside
3969
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3970
 * controlled.
3971
 *
3972
 * Think twice, and think again, before using these.
3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
3993
 */
3994 3995
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3996
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3997 3998
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3999 4000 4001 4002
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
4003

4004
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
4005
{
4006
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4007
		return VLV_VGACNTRL;
4008
	else if (INTEL_GEN(dev_priv) >= 5)
4009
		return CPU_VGACNTRL;
4010 4011 4012 4013
	else
		return VGACNTRL;
}

4014 4015 4016 4017 4018 4019 4020
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

4021 4022 4023 4024 4025
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

4026 4027 4028 4029 4030 4031 4032 4033
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

4034 4035 4036 4037 4038 4039 4040 4041 4042
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
4043
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4044 4045 4046 4047 4048 4049 4050 4051 4052 4053

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
4054 4055 4056 4057
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
4058 4059
	}
}
4060 4061

static inline bool
4062
__i915_request_irq_complete(const struct drm_i915_gem_request *req)
4063
{
4064
	struct intel_engine_cs *engine = req->engine;
4065
	u32 seqno;
4066

4067 4068 4069 4070 4071 4072 4073 4074 4075
	/* Note that the engine may have wrapped around the seqno, and
	 * so our request->global_seqno will be ahead of the hardware,
	 * even though it completed the request before wrapping. We catch
	 * this by kicking all the waiters before resetting the seqno
	 * in hardware, and also signal the fence.
	 */
	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
		return true;

4076 4077 4078 4079 4080 4081 4082 4083 4084 4085
	/* The request was dequeued before we were awoken. We check after
	 * inspecting the hw to confirm that this was the same request
	 * that generated the HWS update. The memory barriers within
	 * the request execution are sufficient to ensure that a check
	 * after reading the value from hw matches this request.
	 */
	seqno = i915_gem_request_global_seqno(req);
	if (!seqno)
		return false;

4086 4087 4088
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
4089
	if (__i915_gem_request_completed(req, seqno))
4090 4091
		return true;

4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
4103
	if (engine->irq_seqno_barrier &&
4104
	    test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4105
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
4106

4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
4119
		engine->irq_seqno_barrier(engine);
4120 4121 4122 4123 4124 4125 4126

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
4127
		spin_lock_irq(&b->irq_lock);
4128
		if (b->irq_wait && b->irq_wait->tsk != current)
4129 4130 4131 4132 4133 4134
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
4135
			wake_up_process(b->irq_wait->tsk);
4136
		spin_unlock_irq(&b->irq_lock);
4137

4138
		if (__i915_gem_request_completed(req, seqno))
4139 4140
			return true;
	}
4141 4142 4143 4144

	return false;
}

4145 4146 4147
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163
/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
 * perform the operation. To check beforehand, pass in the parameters to
 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
 * you only need to pass in the minor offsets, page-aligned pointers are
 * always valid.
 *
 * For just checking for SSE4.1, in the foreknowledge that the future use
 * will be correctly aligned, just use i915_has_memcpy_from_wc().
 */
#define i915_can_memcpy_from_wc(dst, src, len) \
	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)

#define i915_has_memcpy_from_wc() \
	i915_memcpy_from_wc(NULL, NULL, 0)

4164 4165 4166 4167 4168
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

4169 4170 4171 4172 4173 4174
static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
{
	return (obj->cache_level != I915_CACHE_NONE ||
		HAS_LLC(to_i915(obj->base.dev)));
}

L
Linus Torvalds 已提交
4175
#endif