i915_debugfs.c 146.9 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/seq_file.h>
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#include <linux/circ_buf.h>
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#include <linux/ctype.h>
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#include <linux/debugfs.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/list_sort.h>
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#include <asm/msr-index.h>
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include "intel_ringbuffer.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

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static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
	return to_i915(node->minor->dev);
}

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/* As the drm_debugfs_init() routines are called before dev->dev_private is
 * allocated we need to hook into the minor for release. */
static int
drm_add_fake_info_node(struct drm_minor *minor,
		       struct dentry *ent,
		       const void *key)
{
	struct drm_info_node *node;

	node = kmalloc(sizeof(*node), GFP_KERNEL);
	if (node == NULL) {
		debugfs_remove(ent);
		return -ENOMEM;
	}

	node->minor = minor;
	node->dent = ent;
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	node->info_ent = (void *)key;
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	mutex_lock(&minor->debugfs_lock);
	list_add(&node->list, &minor->debugfs_list);
	mutex_unlock(&minor->debugfs_lock);

	return 0;
}

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static int i915_capabilities(struct seq_file *m, void *data)
{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	const struct intel_device_info *info = INTEL_INFO(dev_priv);
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	seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
	seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
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#define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
#define SEP_SEMICOLON ;
	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
#undef PRINT_FLAG
#undef SEP_SEMICOLON
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	return 0;
}
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static char get_active_flag(struct drm_i915_gem_object *obj)
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{
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	return i915_gem_object_is_active(obj) ? '*' : ' ';
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}

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static char get_pin_flag(struct drm_i915_gem_object *obj)
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{
	return obj->pin_display ? 'p' : ' ';
}

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static char get_tiling_flag(struct drm_i915_gem_object *obj)
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{
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	switch (i915_gem_object_get_tiling(obj)) {
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	default:
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	case I915_TILING_NONE: return ' ';
	case I915_TILING_X: return 'X';
	case I915_TILING_Y: return 'Y';
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	}
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}

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static char get_global_flag(struct drm_i915_gem_object *obj)
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{
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	return i915_gem_object_to_ggtt(obj, NULL) ?  'g' : ' ';
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}

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static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
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{
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	return obj->mapping ? 'M' : ' ';
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}

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static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
{
	u64 size = 0;
	struct i915_vma *vma;

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	list_for_each_entry(vma, &obj->vma_list, obj_link) {
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		if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
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			size += vma->node.size;
	}

	return size;
}

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static void
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
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	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
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	struct intel_engine_cs *engine;
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	struct i915_vma *vma;
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	unsigned int frontbuffer_bits;
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	int pin_count = 0;
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	enum intel_engine_id id;
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	lockdep_assert_held(&obj->base.dev->struct_mutex);

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	seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
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		   &obj->base,
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		   get_active_flag(obj),
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		   get_pin_flag(obj),
		   get_tiling_flag(obj),
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		   get_global_flag(obj),
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		   get_pin_mapped_flag(obj),
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		   obj->base.size / 1024,
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		   obj->base.read_domains,
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		   obj->base.write_domain);
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	for_each_engine_id(engine, dev_priv, id)
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		seq_printf(m, "%x ",
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			   i915_gem_active_get_seqno(&obj->last_read[id],
						     &obj->base.dev->struct_mutex));
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	seq_printf(m, "] %x %s%s%s",
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		   i915_gem_active_get_seqno(&obj->last_write,
					     &obj->base.dev->struct_mutex),
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		   i915_cache_level_str(dev_priv, obj->cache_level),
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		   obj->dirty ? " dirty" : "",
		   obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
	if (obj->base.name)
		seq_printf(m, " (name: %d)", obj->base.name);
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	list_for_each_entry(vma, &obj->vma_list, obj_link) {
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		if (i915_vma_is_pinned(vma))
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			pin_count++;
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	}
	seq_printf(m, " (pinned x %d)", pin_count);
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	if (obj->pin_display)
		seq_printf(m, " (display)");
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	list_for_each_entry(vma, &obj->vma_list, obj_link) {
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		if (!drm_mm_node_allocated(&vma->node))
			continue;

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		seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
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			   i915_vma_is_ggtt(vma) ? "g" : "pp",
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			   vma->node.start, vma->node.size);
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		if (i915_vma_is_ggtt(vma))
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			seq_printf(m, ", type: %u", vma->ggtt_view.type);
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		if (vma->fence)
			seq_printf(m, " , fence: %d%s",
				   vma->fence->id,
				   i915_gem_active_isset(&vma->last_fence) ? "*" : "");
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		seq_puts(m, ")");
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	}
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	if (obj->stolen)
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		seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
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	if (obj->pin_display || obj->fault_mappable) {
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		char s[3], *t = s;
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		if (obj->pin_display)
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			*t++ = 'p';
		if (obj->fault_mappable)
			*t++ = 'f';
		*t = '\0';
		seq_printf(m, " (%s mappable)", s);
	}
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	engine = i915_gem_active_get_engine(&obj->last_write,
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					    &dev_priv->drm.struct_mutex);
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	if (engine)
		seq_printf(m, " (%s)", engine->name);

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	frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
	if (frontbuffer_bits)
		seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
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}

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static int obj_rank_by_stolen(void *priv,
			      struct list_head *A, struct list_head *B)
{
	struct drm_i915_gem_object *a =
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		container_of(A, struct drm_i915_gem_object, obj_exec_link);
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	struct drm_i915_gem_object *b =
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		container_of(B, struct drm_i915_gem_object, obj_exec_link);
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	if (a->stolen->start < b->stolen->start)
		return -1;
	if (a->stolen->start > b->stolen->start)
		return 1;
	return 0;
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}

static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
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	struct drm_i915_gem_object *obj;
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	u64 total_obj_size, total_gtt_size;
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	LIST_HEAD(stolen);
	int count, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	total_obj_size = total_gtt_size = count = 0;
	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
		if (obj->stolen == NULL)
			continue;

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		list_add(&obj->obj_exec_link, &stolen);
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		total_obj_size += obj->base.size;
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		total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
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		count++;
	}
	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
		if (obj->stolen == NULL)
			continue;

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		list_add(&obj->obj_exec_link, &stolen);
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		total_obj_size += obj->base.size;
		count++;
	}
	list_sort(NULL, &stolen, obj_rank_by_stolen);
	seq_puts(m, "Stolen:\n");
	while (!list_empty(&stolen)) {
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		obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
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		seq_puts(m, "   ");
		describe_obj(m, obj);
		seq_putc(m, '\n');
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		list_del_init(&obj->obj_exec_link);
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	}
	mutex_unlock(&dev->struct_mutex);

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	seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
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		   count, total_obj_size, total_gtt_size);
	return 0;
}

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struct file_stats {
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	struct drm_i915_file_private *file_priv;
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	unsigned long count;
	u64 total, unbound;
	u64 global, shared;
	u64 active, inactive;
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};

static int per_file_stats(int id, void *ptr, void *data)
{
	struct drm_i915_gem_object *obj = ptr;
	struct file_stats *stats = data;
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	struct i915_vma *vma;
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	stats->count++;
	stats->total += obj->base.size;
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	if (!obj->bind_count)
		stats->unbound += obj->base.size;
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	if (obj->base.name || obj->base.dma_buf)
		stats->shared += obj->base.size;

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	list_for_each_entry(vma, &obj->vma_list, obj_link) {
		if (!drm_mm_node_allocated(&vma->node))
			continue;
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		if (i915_vma_is_ggtt(vma)) {
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			stats->global += vma->node.size;
		} else {
			struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
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			if (ppgtt->base.file != stats->file_priv)
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				continue;
		}
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		if (i915_vma_is_active(vma))
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			stats->active += vma->node.size;
		else
			stats->inactive += vma->node.size;
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	}

	return 0;
}

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#define print_file_stats(m, name, stats) do { \
	if (stats.count) \
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		seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
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			   name, \
			   stats.count, \
			   stats.total, \
			   stats.active, \
			   stats.inactive, \
			   stats.global, \
			   stats.shared, \
			   stats.unbound); \
} while (0)
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static void print_batch_pool_stats(struct seq_file *m,
				   struct drm_i915_private *dev_priv)
{
	struct drm_i915_gem_object *obj;
	struct file_stats stats;
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	struct intel_engine_cs *engine;
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	int j;
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	memset(&stats, 0, sizeof(stats));

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	for_each_engine(engine, dev_priv) {
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		for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
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			list_for_each_entry(obj,
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					    &engine->batch_pool.cache_list[j],
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					    batch_pool_link)
				per_file_stats(0, obj, &stats);
		}
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	}
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	print_file_stats(m, "[k]batch pool", stats);
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}

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static int per_file_ctx_stats(int id, void *ptr, void *data)
{
	struct i915_gem_context *ctx = ptr;
	int n;

	for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
		if (ctx->engine[n].state)
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			per_file_stats(0, ctx->engine[n].state->obj, data);
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		if (ctx->engine[n].ring)
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			per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
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	}

	return 0;
}

static void print_context_stats(struct seq_file *m,
				struct drm_i915_private *dev_priv)
{
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	struct drm_device *dev = &dev_priv->drm;
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	struct file_stats stats;
	struct drm_file *file;

	memset(&stats, 0, sizeof(stats));

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	mutex_lock(&dev->struct_mutex);
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	if (dev_priv->kernel_context)
		per_file_ctx_stats(0, dev_priv->kernel_context, &stats);

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	list_for_each_entry(file, &dev->filelist, lhead) {
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		struct drm_i915_file_private *fpriv = file->driver_priv;
		idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
	}
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	mutex_unlock(&dev->struct_mutex);
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	print_file_stats(m, "[k]contexts", stats);
}

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static int i915_gem_object_info(struct seq_file *m, void *data)
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{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
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	struct i915_ggtt *ggtt = &dev_priv->ggtt;
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	u32 count, mapped_count, purgeable_count, dpy_count;
	u64 size, mapped_size, purgeable_size, dpy_size;
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	struct drm_i915_gem_object *obj;
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	struct drm_file *file;
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	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

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	seq_printf(m, "%u objects, %zu bytes\n",
		   dev_priv->mm.object_count,
		   dev_priv->mm.object_memory);

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	size = count = 0;
	mapped_size = mapped_count = 0;
	purgeable_size = purgeable_count = 0;
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	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
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		size += obj->base.size;
		++count;

		if (obj->madv == I915_MADV_DONTNEED) {
			purgeable_size += obj->base.size;
			++purgeable_count;
		}

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		if (obj->mapping) {
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			mapped_count++;
			mapped_size += obj->base.size;
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		}
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	}
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	seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
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	size = count = dpy_size = dpy_count = 0;
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	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
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		size += obj->base.size;
		++count;

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		if (obj->pin_display) {
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			dpy_size += obj->base.size;
			++dpy_count;
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		}
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		if (obj->madv == I915_MADV_DONTNEED) {
			purgeable_size += obj->base.size;
			++purgeable_count;
		}
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		if (obj->mapping) {
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			mapped_count++;
			mapped_size += obj->base.size;
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		}
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	}
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	seq_printf(m, "%u bound objects, %llu bytes\n",
		   count, size);
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	seq_printf(m, "%u purgeable objects, %llu bytes\n",
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		   purgeable_count, purgeable_size);
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	seq_printf(m, "%u mapped objects, %llu bytes\n",
		   mapped_count, mapped_size);
	seq_printf(m, "%u display objects (pinned), %llu bytes\n",
		   dpy_count, dpy_size);
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	seq_printf(m, "%llu [%llu] gtt total\n",
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		   ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
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	seq_putc(m, '\n');
	print_batch_pool_stats(m, dev_priv);
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	mutex_unlock(&dev->struct_mutex);

	mutex_lock(&dev->filelist_mutex);
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	print_context_stats(m, dev_priv);
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	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct file_stats stats;
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		struct drm_i915_file_private *file_priv = file->driver_priv;
		struct drm_i915_gem_request *request;
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		struct task_struct *task;
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		memset(&stats, 0, sizeof(stats));
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		stats.file_priv = file->driver_priv;
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		spin_lock(&file->table_lock);
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		idr_for_each(&file->object_idr, per_file_stats, &stats);
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		spin_unlock(&file->table_lock);
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		/*
		 * Although we have a valid reference on file->pid, that does
		 * not guarantee that the task_struct who called get_pid() is
		 * still alive (e.g. get_pid(current) => fork() => exit()).
		 * Therefore, we need to protect this ->comm access using RCU.
		 */
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		mutex_lock(&dev->struct_mutex);
		request = list_first_entry_or_null(&file_priv->mm.request_list,
						   struct drm_i915_gem_request,
						   client_list);
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		rcu_read_lock();
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		task = pid_task(request && request->ctx->pid ?
				request->ctx->pid : file->pid,
				PIDTYPE_PID);
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		print_file_stats(m, task ? task->comm : "<unknown>", stats);
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		rcu_read_unlock();
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		mutex_unlock(&dev->struct_mutex);
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	}
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	mutex_unlock(&dev->filelist_mutex);
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	return 0;
}

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static int i915_gem_gtt_info(struct seq_file *m, void *data)
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{
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	struct drm_info_node *node = m->private;
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	struct drm_i915_private *dev_priv = node_to_i915(node);
	struct drm_device *dev = &dev_priv->drm;
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	bool show_pin_display_only = !!node->info_ent->data;
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	struct drm_i915_gem_object *obj;
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	u64 total_obj_size, total_gtt_size;
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	int count, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	total_obj_size = total_gtt_size = count = 0;
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	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
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		if (show_pin_display_only && !obj->pin_display)
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			continue;

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		seq_puts(m, "   ");
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		describe_obj(m, obj);
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		seq_putc(m, '\n');
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		total_obj_size += obj->base.size;
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		total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
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		count++;
	}

	mutex_unlock(&dev->struct_mutex);

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	seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
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		   count, total_obj_size, total_gtt_size);

	return 0;
}

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static int i915_gem_pageflip_info(struct seq_file *m, void *data)
{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
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	struct intel_crtc *crtc;
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	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
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	for_each_intel_crtc(dev, crtc) {
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		const char pipe = pipe_name(crtc->pipe);
		const char plane = plane_name(crtc->plane);
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		struct intel_flip_work *work;
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		spin_lock_irq(&dev->event_lock);
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		work = crtc->flip_work;
		if (work == NULL) {
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			seq_printf(m, "No flip due on pipe %c (plane %c)\n",
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				   pipe, plane);
		} else {
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			u32 pending;
			u32 addr;

			pending = atomic_read(&work->pending);
			if (pending) {
				seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
					   pipe, plane);
			} else {
				seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
					   pipe, plane);
			}
			if (work->flip_queued_req) {
				struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);

				seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
					   engine->name,
					   i915_gem_request_get_seqno(work->flip_queued_req),
					   dev_priv->next_seqno,
575
					   intel_engine_get_seqno(engine),
576
					   i915_gem_request_completed(work->flip_queued_req));
577 578 579 580 581 582 583 584
			} else
				seq_printf(m, "Flip not associated with any ring\n");
			seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
				   work->flip_queued_vblank,
				   work->flip_ready_vblank,
				   intel_crtc_get_vblank_counter(crtc));
			seq_printf(m, "%d prepares\n", atomic_read(&work->pending));

585
			if (INTEL_GEN(dev_priv) >= 4)
586 587 588 589 590 591 592 593
				addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
			else
				addr = I915_READ(DSPADDR(crtc->plane));
			seq_printf(m, "Current scanout address 0x%08x\n", addr);

			if (work->pending_flip_obj) {
				seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
				seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
594 595
			}
		}
596
		spin_unlock_irq(&dev->event_lock);
597 598
	}

599 600
	mutex_unlock(&dev->struct_mutex);

601 602 603
	return 0;
}

604 605
static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
{
606 607
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
608
	struct drm_i915_gem_object *obj;
609
	struct intel_engine_cs *engine;
610
	int total = 0;
611
	int ret, j;
612 613 614 615 616

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

617
	for_each_engine(engine, dev_priv) {
618
		for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
619 620 621 622
			int count;

			count = 0;
			list_for_each_entry(obj,
623
					    &engine->batch_pool.cache_list[j],
624 625 626
					    batch_pool_link)
				count++;
			seq_printf(m, "%s cache[%d]: %d objects\n",
627
				   engine->name, j, count);
628 629

			list_for_each_entry(obj,
630
					    &engine->batch_pool.cache_list[j],
631 632 633 634 635 636 637
					    batch_pool_link) {
				seq_puts(m, "   ");
				describe_obj(m, obj);
				seq_putc(m, '\n');
			}

			total += count;
638
		}
639 640
	}

641
	seq_printf(m, "total: %d\n", total);
642 643 644 645 646 647

	mutex_unlock(&dev->struct_mutex);

	return 0;
}

648 649
static int i915_gem_request_info(struct seq_file *m, void *data)
{
650 651
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
652
	struct intel_engine_cs *engine;
D
Daniel Vetter 已提交
653
	struct drm_i915_gem_request *req;
654
	int ret, any;
655 656 657 658

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
659

660
	any = 0;
661
	for_each_engine(engine, dev_priv) {
662 663 664
		int count;

		count = 0;
665
		list_for_each_entry(req, &engine->request_list, link)
666 667
			count++;
		if (count == 0)
668 669
			continue;

670
		seq_printf(m, "%s requests: %d\n", engine->name, count);
671
		list_for_each_entry(req, &engine->request_list, link) {
672
			struct pid *pid = req->ctx->pid;
673 674 675
			struct task_struct *task;

			rcu_read_lock();
676
			task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
677
			seq_printf(m, "    %x @ %d: %s [%d]\n",
678
				   req->fence.seqno,
D
Daniel Vetter 已提交
679
				   (int) (jiffies - req->emitted_jiffies),
680 681 682
				   task ? task->comm : "<unknown>",
				   task ? task->pid : -1);
			rcu_read_unlock();
683
		}
684 685

		any++;
686
	}
687 688
	mutex_unlock(&dev->struct_mutex);

689
	if (any == 0)
690
		seq_puts(m, "No requests\n");
691

692 693 694
	return 0;
}

695
static void i915_ring_seqno_info(struct seq_file *m,
696
				 struct intel_engine_cs *engine)
697
{
698 699 700
	struct intel_breadcrumbs *b = &engine->breadcrumbs;
	struct rb_node *rb;

701
	seq_printf(m, "Current sequence (%s): %x\n",
702
		   engine->name, intel_engine_get_seqno(engine));
703 704 705 706 707 708 709 710 711

	spin_lock(&b->lock);
	for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
		struct intel_wait *w = container_of(rb, typeof(*w), node);

		seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
			   engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
	}
	spin_unlock(&b->lock);
712 713
}

714 715
static int i915_gem_seqno_info(struct seq_file *m, void *data)
{
716
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
717
	struct intel_engine_cs *engine;
718

719
	for_each_engine(engine, dev_priv)
720
		i915_ring_seqno_info(m, engine);
721

722 723 724 725 726 727
	return 0;
}


static int i915_interrupt_info(struct seq_file *m, void *data)
{
728
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
729
	struct intel_engine_cs *engine;
730
	int i, pipe;
731

732
	intel_runtime_pm_get(dev_priv);
733

734
	if (IS_CHERRYVIEW(dev_priv)) {
735 736 737 738 739 740 741 742 743 744 745
		seq_printf(m, "Master Interrupt Control:\t%08x\n",
			   I915_READ(GEN8_MASTER_IRQ));

		seq_printf(m, "Display IER:\t%08x\n",
			   I915_READ(VLV_IER));
		seq_printf(m, "Display IIR:\t%08x\n",
			   I915_READ(VLV_IIR));
		seq_printf(m, "Display IIR_RW:\t%08x\n",
			   I915_READ(VLV_IIR_RW));
		seq_printf(m, "Display IMR:\t%08x\n",
			   I915_READ(VLV_IMR));
746
		for_each_pipe(dev_priv, pipe)
747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772
			seq_printf(m, "Pipe %c stat:\t%08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));

		seq_printf(m, "Port hotplug:\t%08x\n",
			   I915_READ(PORT_HOTPLUG_EN));
		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
			   I915_READ(VLV_DPFLIPSTAT));
		seq_printf(m, "DPINVGTT:\t%08x\n",
			   I915_READ(DPINVGTT));

		for (i = 0; i < 4; i++) {
			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IMR(i)));
			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IIR(i)));
			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IER(i)));
		}

		seq_printf(m, "PCU interrupt mask:\t%08x\n",
			   I915_READ(GEN8_PCU_IMR));
		seq_printf(m, "PCU interrupt identity:\t%08x\n",
			   I915_READ(GEN8_PCU_IIR));
		seq_printf(m, "PCU interrupt enable:\t%08x\n",
			   I915_READ(GEN8_PCU_IER));
773
	} else if (INTEL_GEN(dev_priv) >= 8) {
774 775 776 777 778 779 780 781 782 783 784 785
		seq_printf(m, "Master Interrupt Control:\t%08x\n",
			   I915_READ(GEN8_MASTER_IRQ));

		for (i = 0; i < 4; i++) {
			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IMR(i)));
			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IIR(i)));
			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IER(i)));
		}

786
		for_each_pipe(dev_priv, pipe) {
787 788 789 790 791
			enum intel_display_power_domain power_domain;

			power_domain = POWER_DOMAIN_PIPE(pipe);
			if (!intel_display_power_get_if_enabled(dev_priv,
								power_domain)) {
792 793 794 795
				seq_printf(m, "Pipe %c power disabled\n",
					   pipe_name(pipe));
				continue;
			}
796
			seq_printf(m, "Pipe %c IMR:\t%08x\n",
797 798
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
799
			seq_printf(m, "Pipe %c IIR:\t%08x\n",
800 801
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
802
			seq_printf(m, "Pipe %c IER:\t%08x\n",
803 804
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IER(pipe)));
805 806

			intel_display_power_put(dev_priv, power_domain);
807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828
		}

		seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IMR));
		seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IIR));
		seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IER));

		seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IMR));
		seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IIR));
		seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IER));

		seq_printf(m, "PCU interrupt mask:\t%08x\n",
			   I915_READ(GEN8_PCU_IMR));
		seq_printf(m, "PCU interrupt identity:\t%08x\n",
			   I915_READ(GEN8_PCU_IIR));
		seq_printf(m, "PCU interrupt enable:\t%08x\n",
			   I915_READ(GEN8_PCU_IER));
829
	} else if (IS_VALLEYVIEW(dev_priv)) {
J
Jesse Barnes 已提交
830 831 832 833 834 835 836 837
		seq_printf(m, "Display IER:\t%08x\n",
			   I915_READ(VLV_IER));
		seq_printf(m, "Display IIR:\t%08x\n",
			   I915_READ(VLV_IIR));
		seq_printf(m, "Display IIR_RW:\t%08x\n",
			   I915_READ(VLV_IIR_RW));
		seq_printf(m, "Display IMR:\t%08x\n",
			   I915_READ(VLV_IMR));
838
		for_each_pipe(dev_priv, pipe)
J
Jesse Barnes 已提交
839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866
			seq_printf(m, "Pipe %c stat:\t%08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));

		seq_printf(m, "Master IER:\t%08x\n",
			   I915_READ(VLV_MASTER_IER));

		seq_printf(m, "Render IER:\t%08x\n",
			   I915_READ(GTIER));
		seq_printf(m, "Render IIR:\t%08x\n",
			   I915_READ(GTIIR));
		seq_printf(m, "Render IMR:\t%08x\n",
			   I915_READ(GTIMR));

		seq_printf(m, "PM IER:\t\t%08x\n",
			   I915_READ(GEN6_PMIER));
		seq_printf(m, "PM IIR:\t\t%08x\n",
			   I915_READ(GEN6_PMIIR));
		seq_printf(m, "PM IMR:\t\t%08x\n",
			   I915_READ(GEN6_PMIMR));

		seq_printf(m, "Port hotplug:\t%08x\n",
			   I915_READ(PORT_HOTPLUG_EN));
		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
			   I915_READ(VLV_DPFLIPSTAT));
		seq_printf(m, "DPINVGTT:\t%08x\n",
			   I915_READ(DPINVGTT));

867
	} else if (!HAS_PCH_SPLIT(dev_priv)) {
868 869 870 871 872 873
		seq_printf(m, "Interrupt enable:    %08x\n",
			   I915_READ(IER));
		seq_printf(m, "Interrupt identity:  %08x\n",
			   I915_READ(IIR));
		seq_printf(m, "Interrupt mask:      %08x\n",
			   I915_READ(IMR));
874
		for_each_pipe(dev_priv, pipe)
875 876 877
			seq_printf(m, "Pipe %c stat:         %08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));
878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897
	} else {
		seq_printf(m, "North Display Interrupt enable:		%08x\n",
			   I915_READ(DEIER));
		seq_printf(m, "North Display Interrupt identity:	%08x\n",
			   I915_READ(DEIIR));
		seq_printf(m, "North Display Interrupt mask:		%08x\n",
			   I915_READ(DEIMR));
		seq_printf(m, "South Display Interrupt enable:		%08x\n",
			   I915_READ(SDEIER));
		seq_printf(m, "South Display Interrupt identity:	%08x\n",
			   I915_READ(SDEIIR));
		seq_printf(m, "South Display Interrupt mask:		%08x\n",
			   I915_READ(SDEIMR));
		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
			   I915_READ(GTIER));
		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
			   I915_READ(GTIIR));
		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
			   I915_READ(GTIMR));
	}
898
	for_each_engine(engine, dev_priv) {
899
		if (INTEL_GEN(dev_priv) >= 6) {
900 901
			seq_printf(m,
				   "Graphics Interrupt mask (%s):	%08x\n",
902
				   engine->name, I915_READ_IMR(engine));
903
		}
904
		i915_ring_seqno_info(m, engine);
905
	}
906
	intel_runtime_pm_put(dev_priv);
907

908 909 910
	return 0;
}

911 912
static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
{
913 914
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
915 916 917 918 919
	int i, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
920 921 922

	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
	for (i = 0; i < dev_priv->num_fence_regs; i++) {
923
		struct i915_vma *vma = dev_priv->fence_regs[i].vma;
924

C
Chris Wilson 已提交
925 926
		seq_printf(m, "Fence %d, pin count = %d, object = ",
			   i, dev_priv->fence_regs[i].pin_count);
927
		if (!vma)
928
			seq_puts(m, "unused");
929
		else
930
			describe_obj(m, vma->obj);
931
		seq_putc(m, '\n');
932 933
	}

934
	mutex_unlock(&dev->struct_mutex);
935 936 937
	return 0;
}

938 939
static int i915_hws_info(struct seq_file *m, void *data)
{
940
	struct drm_info_node *node = m->private;
941
	struct drm_i915_private *dev_priv = node_to_i915(node);
942
	struct intel_engine_cs *engine;
D
Daniel Vetter 已提交
943
	const u32 *hws;
944 945
	int i;

946
	engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
947
	hws = engine->status_page.page_addr;
948 949 950 951 952 953 954 955 956 957 958
	if (hws == NULL)
		return 0;

	for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
		seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
			   i * 4,
			   hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
	}
	return 0;
}

959 960 961 962 963 964
static ssize_t
i915_error_state_write(struct file *filp,
		       const char __user *ubuf,
		       size_t cnt,
		       loff_t *ppos)
{
965
	struct i915_error_state_file_priv *error_priv = filp->private_data;
966 967

	DRM_DEBUG_DRIVER("Resetting error state\n");
968
	i915_destroy_error_state(error_priv->dev);
969 970 971 972 973 974

	return cnt;
}

static int i915_error_state_open(struct inode *inode, struct file *file)
{
975
	struct drm_i915_private *dev_priv = inode->i_private;
976 977 978 979 980 981
	struct i915_error_state_file_priv *error_priv;

	error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
	if (!error_priv)
		return -ENOMEM;

982
	error_priv->dev = &dev_priv->drm;
983

984
	i915_error_state_get(&dev_priv->drm, error_priv);
985

986 987 988
	file->private_data = error_priv;

	return 0;
989 990 991 992
}

static int i915_error_state_release(struct inode *inode, struct file *file)
{
993
	struct i915_error_state_file_priv *error_priv = file->private_data;
994

995
	i915_error_state_put(error_priv);
996 997
	kfree(error_priv);

998 999 1000
	return 0;
}

1001 1002 1003 1004 1005 1006 1007 1008 1009
static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
				     size_t count, loff_t *pos)
{
	struct i915_error_state_file_priv *error_priv = file->private_data;
	struct drm_i915_error_state_buf error_str;
	loff_t tmp_pos = 0;
	ssize_t ret_count = 0;
	int ret;

1010 1011
	ret = i915_error_state_buf_init(&error_str,
					to_i915(error_priv->dev), count, *pos);
1012 1013
	if (ret)
		return ret;
1014

1015
	ret = i915_error_state_to_str(&error_str, error_priv);
1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027
	if (ret)
		goto out;

	ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
					    error_str.buf,
					    error_str.bytes);

	if (ret_count < 0)
		ret = ret_count;
	else
		*pos = error_str.start + ret_count;
out:
1028
	i915_error_state_buf_release(&error_str);
1029
	return ret ?: ret_count;
1030 1031 1032 1033 1034
}

static const struct file_operations i915_error_state_fops = {
	.owner = THIS_MODULE,
	.open = i915_error_state_open,
1035
	.read = i915_error_state_read,
1036 1037 1038 1039 1040
	.write = i915_error_state_write,
	.llseek = default_llseek,
	.release = i915_error_state_release,
};

1041 1042
static int
i915_next_seqno_get(void *data, u64 *val)
1043
{
1044
	struct drm_i915_private *dev_priv = data;
1045 1046
	int ret;

1047
	ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
1048 1049 1050
	if (ret)
		return ret;

1051
	*val = dev_priv->next_seqno;
1052
	mutex_unlock(&dev_priv->drm.struct_mutex);
1053

1054
	return 0;
1055 1056
}

1057 1058 1059
static int
i915_next_seqno_set(void *data, u64 val)
{
1060 1061
	struct drm_i915_private *dev_priv = data;
	struct drm_device *dev = &dev_priv->drm;
1062 1063 1064 1065 1066 1067
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

1068
	ret = i915_gem_set_seqno(dev, val);
1069 1070
	mutex_unlock(&dev->struct_mutex);

1071
	return ret;
1072 1073
}

1074 1075
DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
			i915_next_seqno_get, i915_next_seqno_set,
1076
			"0x%llx\n");
1077

1078
static int i915_frequency_info(struct seq_file *m, void *unused)
1079
{
1080 1081
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1082 1083 1084
	int ret = 0;

	intel_runtime_pm_get(dev_priv);
1085

1086
	if (IS_GEN5(dev_priv)) {
1087 1088 1089 1090 1091 1092 1093 1094 1095
		u16 rgvswctl = I915_READ16(MEMSWCTL);
		u16 rgvstat = I915_READ16(MEMSTAT_ILK);

		seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
		seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
		seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
			   MEMSTAT_VID_SHIFT);
		seq_printf(m, "Current P-state: %d\n",
			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1096
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122
		u32 freq_sts;

		mutex_lock(&dev_priv->rps.hw_lock);
		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);

		seq_printf(m, "actual GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));

		seq_printf(m, "current GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));

		seq_printf(m, "max GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));

		seq_printf(m, "min GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));

		seq_printf(m, "idle GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));

		seq_printf(m,
			   "efficient (RPe) frequency: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
		mutex_unlock(&dev_priv->rps.hw_lock);
1123
	} else if (INTEL_GEN(dev_priv) >= 6) {
1124 1125 1126
		u32 rp_state_limits;
		u32 gt_perf_status;
		u32 rp_state_cap;
1127
		u32 rpmodectl, rpinclimit, rpdeclimit;
1128
		u32 rpstat, cagf, reqf;
1129 1130
		u32 rpupei, rpcurup, rpprevup;
		u32 rpdownei, rpcurdown, rpprevdown;
1131
		u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1132 1133
		int max_freq;

1134
		rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1135
		if (IS_BROXTON(dev_priv)) {
1136 1137 1138 1139 1140 1141 1142
			rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
			gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
		} else {
			rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
			gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
		}

1143
		/* RPSTAT1 is in the GT power well */
1144 1145
		ret = mutex_lock_interruptible(&dev->struct_mutex);
		if (ret)
1146
			goto out;
1147

1148
		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1149

1150
		reqf = I915_READ(GEN6_RPNSWREQ);
1151
		if (IS_GEN9(dev_priv))
1152 1153 1154
			reqf >>= 23;
		else {
			reqf &= ~GEN6_TURBO_DISABLE;
1155
			if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1156 1157 1158 1159
				reqf >>= 24;
			else
				reqf >>= 25;
		}
1160
		reqf = intel_gpu_freq(dev_priv, reqf);
1161

1162 1163 1164 1165
		rpmodectl = I915_READ(GEN6_RP_CONTROL);
		rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
		rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);

1166
		rpstat = I915_READ(GEN6_RPSTAT1);
1167 1168 1169 1170 1171 1172
		rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
		rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
		rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1173
		if (IS_GEN9(dev_priv))
1174
			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1175
		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
B
Ben Widawsky 已提交
1176 1177 1178
			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
		else
			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1179
		cagf = intel_gpu_freq(dev_priv, cagf);
1180

1181
		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1182 1183
		mutex_unlock(&dev->struct_mutex);

1184
		if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196
			pm_ier = I915_READ(GEN6_PMIER);
			pm_imr = I915_READ(GEN6_PMIMR);
			pm_isr = I915_READ(GEN6_PMISR);
			pm_iir = I915_READ(GEN6_PMIIR);
			pm_mask = I915_READ(GEN6_PMINTRMSK);
		} else {
			pm_ier = I915_READ(GEN8_GT_IER(2));
			pm_imr = I915_READ(GEN8_GT_IMR(2));
			pm_isr = I915_READ(GEN8_GT_ISR(2));
			pm_iir = I915_READ(GEN8_GT_IIR(2));
			pm_mask = I915_READ(GEN6_PMINTRMSK);
		}
1197
		seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1198
			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1199
		seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1200 1201
		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
		seq_printf(m, "Render p-state ratio: %d\n",
1202
			   (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1203 1204 1205 1206
		seq_printf(m, "Render p-state VID: %d\n",
			   gt_perf_status & 0xff);
		seq_printf(m, "Render p-state limit: %d\n",
			   rp_state_limits & 0xff);
1207 1208 1209 1210
		seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
		seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
		seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
		seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1211
		seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
B
Ben Widawsky 已提交
1212
		seq_printf(m, "CAGF: %dMHz\n", cagf);
1213 1214 1215 1216 1217 1218
		seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
			   rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
		seq_printf(m, "RP CUR UP: %d (%dus)\n",
			   rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
		seq_printf(m, "RP PREV UP: %d (%dus)\n",
			   rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1219 1220 1221
		seq_printf(m, "Up threshold: %d%%\n",
			   dev_priv->rps.up_threshold);

1222 1223 1224 1225 1226 1227
		seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
			   rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
		seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
			   rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
		seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
			   rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1228 1229
		seq_printf(m, "Down threshold: %d%%\n",
			   dev_priv->rps.down_threshold);
1230

1231
		max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1232
			    rp_state_cap >> 16) & 0xff;
1233
		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1234
			     GEN9_FREQ_SCALER : 1);
1235
		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1236
			   intel_gpu_freq(dev_priv, max_freq));
1237 1238

		max_freq = (rp_state_cap & 0xff00) >> 8;
1239
		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1240
			     GEN9_FREQ_SCALER : 1);
1241
		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1242
			   intel_gpu_freq(dev_priv, max_freq));
1243

1244
		max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1245
			    rp_state_cap >> 0) & 0xff;
1246
		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1247
			     GEN9_FREQ_SCALER : 1);
1248
		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1249
			   intel_gpu_freq(dev_priv, max_freq));
1250
		seq_printf(m, "Max overclocked frequency: %dMHz\n",
1251
			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1252

1253 1254 1255
		seq_printf(m, "Current freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
		seq_printf(m, "Actual freq: %d MHz\n", cagf);
1256 1257
		seq_printf(m, "Idle freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1258 1259
		seq_printf(m, "Min freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1260 1261
		seq_printf(m, "Boost freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1262 1263 1264 1265 1266
		seq_printf(m, "Max freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
		seq_printf(m,
			   "efficient (RPe) frequency: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1267
	} else {
1268
		seq_puts(m, "no P-state info available\n");
1269
	}
1270

1271 1272 1273 1274
	seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
	seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
	seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);

1275 1276 1277
out:
	intel_runtime_pm_put(dev_priv);
	return ret;
1278 1279
}

1280 1281
static int i915_hangcheck_info(struct seq_file *m, void *unused)
{
1282
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1283
	struct intel_engine_cs *engine;
1284 1285
	u64 acthd[I915_NUM_ENGINES];
	u32 seqno[I915_NUM_ENGINES];
1286
	u32 instdone[I915_NUM_INSTDONE_REG];
1287 1288
	enum intel_engine_id id;
	int j;
1289

1290 1291 1292 1293 1294 1295 1296 1297 1298
	if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
		seq_printf(m, "Wedged\n");
	if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
		seq_printf(m, "Reset in progress\n");
	if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
		seq_printf(m, "Waiter holding struct mutex\n");
	if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
		seq_printf(m, "struct_mutex blocked for reset\n");

1299 1300 1301 1302 1303
	if (!i915.enable_hangcheck) {
		seq_printf(m, "Hangcheck disabled\n");
		return 0;
	}

1304 1305
	intel_runtime_pm_get(dev_priv);

1306
	for_each_engine_id(engine, dev_priv, id) {
1307
		acthd[id] = intel_engine_get_active_head(engine);
1308
		seqno[id] = intel_engine_get_seqno(engine);
1309 1310
	}

1311
	i915_get_extra_instdone(dev_priv, instdone);
1312

1313 1314
	intel_runtime_pm_put(dev_priv);

1315 1316 1317 1318 1319 1320 1321
	if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
		seq_printf(m, "Hangcheck active, fires in %dms\n",
			   jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
					    jiffies));
	} else
		seq_printf(m, "Hangcheck inactive\n");

1322
	for_each_engine_id(engine, dev_priv, id) {
1323
		seq_printf(m, "%s:\n", engine->name);
1324 1325 1326 1327
		seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
			   engine->hangcheck.seqno,
			   seqno[id],
			   engine->last_submitted_seqno);
1328 1329 1330 1331
		seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
			   yesno(intel_engine_has_waiter(engine)),
			   yesno(test_bit(engine->id,
					  &dev_priv->gpu_error.missed_irq_rings)));
1332
		seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1333
			   (long long)engine->hangcheck.acthd,
1334
			   (long long)acthd[id]);
1335 1336
		seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
		seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1337

1338
		if (engine->id == RCS) {
1339 1340 1341 1342 1343 1344 1345 1346 1347
			seq_puts(m, "\tinstdone read =");

			for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
				seq_printf(m, " 0x%08x", instdone[j]);

			seq_puts(m, "\n\tinstdone accu =");

			for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
				seq_printf(m, " 0x%08x",
1348
					   engine->hangcheck.instdone[j]);
1349 1350 1351

			seq_puts(m, "\n");
		}
1352 1353 1354 1355 1356
	}

	return 0;
}

1357
static int ironlake_drpc_info(struct seq_file *m)
1358
{
1359 1360
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1361 1362 1363 1364 1365 1366 1367
	u32 rgvmodectl, rstdbyctl;
	u16 crstandvid;
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1368
	intel_runtime_pm_get(dev_priv);
1369 1370 1371 1372 1373

	rgvmodectl = I915_READ(MEMMODECTL);
	rstdbyctl = I915_READ(RSTDBYCTL);
	crstandvid = I915_READ16(CRSTANDVID);

1374
	intel_runtime_pm_put(dev_priv);
1375
	mutex_unlock(&dev->struct_mutex);
1376

1377
	seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1378 1379 1380 1381
	seq_printf(m, "Boost freq: %d\n",
		   (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
		   MEMMODE_BOOST_FREQ_SHIFT);
	seq_printf(m, "HW control enabled: %s\n",
1382
		   yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1383
	seq_printf(m, "SW control enabled: %s\n",
1384
		   yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1385
	seq_printf(m, "Gated voltage change: %s\n",
1386
		   yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1387 1388
	seq_printf(m, "Starting frequency: P%d\n",
		   (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1389
	seq_printf(m, "Max P-state: P%d\n",
1390
		   (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1391 1392 1393 1394
	seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
	seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
	seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
	seq_printf(m, "Render standby enabled: %s\n",
1395
		   yesno(!(rstdbyctl & RCX_SW_EXIT)));
1396
	seq_puts(m, "Current RS state: ");
1397 1398
	switch (rstdbyctl & RSX_STATUS_MASK) {
	case RSX_STATUS_ON:
1399
		seq_puts(m, "on\n");
1400 1401
		break;
	case RSX_STATUS_RC1:
1402
		seq_puts(m, "RC1\n");
1403 1404
		break;
	case RSX_STATUS_RC1E:
1405
		seq_puts(m, "RC1E\n");
1406 1407
		break;
	case RSX_STATUS_RS1:
1408
		seq_puts(m, "RS1\n");
1409 1410
		break;
	case RSX_STATUS_RS2:
1411
		seq_puts(m, "RS2 (RC6)\n");
1412 1413
		break;
	case RSX_STATUS_RS3:
1414
		seq_puts(m, "RC3 (RC6+)\n");
1415 1416
		break;
	default:
1417
		seq_puts(m, "unknown\n");
1418 1419
		break;
	}
1420 1421 1422 1423

	return 0;
}

1424
static int i915_forcewake_domains(struct seq_file *m, void *data)
1425
{
1426
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1427 1428 1429
	struct intel_uncore_forcewake_domain *fw_domain;

	spin_lock_irq(&dev_priv->uncore.lock);
1430
	for_each_fw_domain(fw_domain, dev_priv) {
1431
		seq_printf(m, "%s.wake_count = %u\n",
1432
			   intel_uncore_forcewake_domain_to_str(fw_domain->id),
1433 1434 1435
			   fw_domain->wake_count);
	}
	spin_unlock_irq(&dev_priv->uncore.lock);
1436

1437 1438 1439 1440 1441
	return 0;
}

static int vlv_drpc_info(struct seq_file *m)
{
1442
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1443
	u32 rpmodectl1, rcctl1, pw_status;
1444

1445 1446
	intel_runtime_pm_get(dev_priv);

1447
	pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1448 1449 1450
	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
	rcctl1 = I915_READ(GEN6_RC_CONTROL);

1451 1452
	intel_runtime_pm_put(dev_priv);

1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465
	seq_printf(m, "Video Turbo Mode: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
	seq_printf(m, "Turbo enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "HW control enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "SW control enabled: %s\n",
		   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
			  GEN6_RP_MEDIA_SW_MODE));
	seq_printf(m, "RC6 Enabled: %s\n",
		   yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
					GEN6_RC_CTL_EI_MODE(1))));
	seq_printf(m, "Render Power Well: %s\n",
1466
		   (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1467
	seq_printf(m, "Media Power Well: %s\n",
1468
		   (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1469

1470 1471 1472 1473 1474
	seq_printf(m, "Render RC6 residency since boot: %u\n",
		   I915_READ(VLV_GT_RENDER_RC6));
	seq_printf(m, "Media RC6 residency since boot: %u\n",
		   I915_READ(VLV_GT_MEDIA_RC6));

1475
	return i915_forcewake_domains(m, NULL);
1476 1477
}

1478 1479
static int gen6_drpc_info(struct seq_file *m)
{
1480 1481
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
B
Ben Widawsky 已提交
1482
	u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1483
	u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1484
	unsigned forcewake_count;
1485
	int count = 0, ret;
1486 1487 1488 1489

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1490
	intel_runtime_pm_get(dev_priv);
1491

1492
	spin_lock_irq(&dev_priv->uncore.lock);
1493
	forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1494
	spin_unlock_irq(&dev_priv->uncore.lock);
1495 1496

	if (forcewake_count) {
1497 1498
		seq_puts(m, "RC information inaccurate because somebody "
			    "holds a forcewake reference \n");
1499 1500 1501 1502 1503 1504 1505
	} else {
		/* NB: we cannot use forcewake, else we read the wrong values */
		while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
			udelay(10);
		seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
	}

1506
	gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1507
	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1508 1509 1510

	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
	rcctl1 = I915_READ(GEN6_RC_CONTROL);
1511
	if (INTEL_GEN(dev_priv) >= 9) {
1512 1513 1514
		gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
		gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
	}
1515
	mutex_unlock(&dev->struct_mutex);
1516 1517 1518
	mutex_lock(&dev_priv->rps.hw_lock);
	sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
	mutex_unlock(&dev_priv->rps.hw_lock);
1519

1520 1521
	intel_runtime_pm_put(dev_priv);

1522 1523 1524 1525 1526 1527 1528
	seq_printf(m, "Video Turbo Mode: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
	seq_printf(m, "HW control enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "SW control enabled: %s\n",
		   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
			  GEN6_RP_MEDIA_SW_MODE));
1529
	seq_printf(m, "RC1e Enabled: %s\n",
1530 1531 1532
		   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
	seq_printf(m, "RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1533
	if (INTEL_GEN(dev_priv) >= 9) {
1534 1535 1536 1537 1538
		seq_printf(m, "Render Well Gating Enabled: %s\n",
			yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
		seq_printf(m, "Media Well Gating Enabled: %s\n",
			yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
	}
1539 1540 1541 1542
	seq_printf(m, "Deep RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
	seq_printf(m, "Deepest RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1543
	seq_puts(m, "Current RC state: ");
1544 1545 1546
	switch (gt_core_status & GEN6_RCn_MASK) {
	case GEN6_RC0:
		if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1547
			seq_puts(m, "Core Power Down\n");
1548
		else
1549
			seq_puts(m, "on\n");
1550 1551
		break;
	case GEN6_RC3:
1552
		seq_puts(m, "RC3\n");
1553 1554
		break;
	case GEN6_RC6:
1555
		seq_puts(m, "RC6\n");
1556 1557
		break;
	case GEN6_RC7:
1558
		seq_puts(m, "RC7\n");
1559 1560
		break;
	default:
1561
		seq_puts(m, "Unknown\n");
1562 1563 1564 1565 1566
		break;
	}

	seq_printf(m, "Core Power Down: %s\n",
		   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1567
	if (INTEL_GEN(dev_priv) >= 9) {
1568 1569 1570 1571 1572 1573 1574
		seq_printf(m, "Render Power Well: %s\n",
			(gen9_powergate_status &
			 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
		seq_printf(m, "Media Power Well: %s\n",
			(gen9_powergate_status &
			 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
	}
1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585

	/* Not exactly sure what this is */
	seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6_LOCKED));
	seq_printf(m, "RC6 residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6));
	seq_printf(m, "RC6+ residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6p));
	seq_printf(m, "RC6++ residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6pp));

B
Ben Widawsky 已提交
1586 1587 1588 1589 1590 1591
	seq_printf(m, "RC6   voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
	seq_printf(m, "RC6+  voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
	seq_printf(m, "RC6++ voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1592
	return i915_forcewake_domains(m, NULL);
1593 1594 1595 1596
}

static int i915_drpc_info(struct seq_file *m, void *unused)
{
1597
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1598

1599
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1600
		return vlv_drpc_info(m);
1601
	else if (INTEL_GEN(dev_priv) >= 6)
1602 1603 1604 1605 1606
		return gen6_drpc_info(m);
	else
		return ironlake_drpc_info(m);
}

1607 1608
static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
{
1609
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1610 1611 1612 1613 1614 1615 1616 1617 1618 1619

	seq_printf(m, "FB tracking busy bits: 0x%08x\n",
		   dev_priv->fb_tracking.busy_bits);

	seq_printf(m, "FB tracking flip bits: 0x%08x\n",
		   dev_priv->fb_tracking.flip_bits);

	return 0;
}

1620 1621
static int i915_fbc_status(struct seq_file *m, void *unused)
{
1622
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1623

1624
	if (!HAS_FBC(dev_priv)) {
1625
		seq_puts(m, "FBC unsupported on this chipset\n");
1626 1627 1628
		return 0;
	}

1629
	intel_runtime_pm_get(dev_priv);
P
Paulo Zanoni 已提交
1630
	mutex_lock(&dev_priv->fbc.lock);
1631

1632
	if (intel_fbc_is_active(dev_priv))
1633
		seq_puts(m, "FBC enabled\n");
1634 1635
	else
		seq_printf(m, "FBC disabled: %s\n",
1636
			   dev_priv->fbc.no_fbc_reason);
1637

1638
	if (INTEL_GEN(dev_priv) >= 7)
1639 1640 1641 1642
		seq_printf(m, "Compressing: %s\n",
			   yesno(I915_READ(FBC_STATUS2) &
				 FBC_COMPRESSION_MASK));

P
Paulo Zanoni 已提交
1643
	mutex_unlock(&dev_priv->fbc.lock);
1644 1645
	intel_runtime_pm_put(dev_priv);

1646 1647 1648
	return 0;
}

1649 1650
static int i915_fbc_fc_get(void *data, u64 *val)
{
1651
	struct drm_i915_private *dev_priv = data;
1652

1653
	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1654 1655 1656 1657 1658 1659 1660 1661 1662
		return -ENODEV;

	*val = dev_priv->fbc.false_color;

	return 0;
}

static int i915_fbc_fc_set(void *data, u64 val)
{
1663
	struct drm_i915_private *dev_priv = data;
1664 1665
	u32 reg;

1666
	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1667 1668
		return -ENODEV;

P
Paulo Zanoni 已提交
1669
	mutex_lock(&dev_priv->fbc.lock);
1670 1671 1672 1673 1674 1675 1676 1677

	reg = I915_READ(ILK_DPFC_CONTROL);
	dev_priv->fbc.false_color = val;

	I915_WRITE(ILK_DPFC_CONTROL, val ?
		   (reg | FBC_CTL_FALSE_COLOR) :
		   (reg & ~FBC_CTL_FALSE_COLOR));

P
Paulo Zanoni 已提交
1678
	mutex_unlock(&dev_priv->fbc.lock);
1679 1680 1681 1682 1683 1684 1685
	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
			i915_fbc_fc_get, i915_fbc_fc_set,
			"%llu\n");

1686 1687
static int i915_ips_status(struct seq_file *m, void *unused)
{
1688
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1689

1690
	if (!HAS_IPS(dev_priv)) {
1691 1692 1693 1694
		seq_puts(m, "not supported\n");
		return 0;
	}

1695 1696
	intel_runtime_pm_get(dev_priv);

1697 1698 1699
	seq_printf(m, "Enabled by kernel parameter: %s\n",
		   yesno(i915.enable_ips));

1700
	if (INTEL_GEN(dev_priv) >= 8) {
1701 1702 1703 1704 1705 1706 1707
		seq_puts(m, "Currently: unknown\n");
	} else {
		if (I915_READ(IPS_CTL) & IPS_ENABLE)
			seq_puts(m, "Currently: enabled\n");
		else
			seq_puts(m, "Currently: disabled\n");
	}
1708

1709 1710
	intel_runtime_pm_put(dev_priv);

1711 1712 1713
	return 0;
}

1714 1715
static int i915_sr_status(struct seq_file *m, void *unused)
{
1716
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1717 1718
	bool sr_enabled = false;

1719 1720
	intel_runtime_pm_get(dev_priv);

1721
	if (HAS_PCH_SPLIT(dev_priv))
1722
		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1723 1724
	else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1725
		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1726
	else if (IS_I915GM(dev_priv))
1727
		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1728
	else if (IS_PINEVIEW(dev_priv))
1729
		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1730
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1731
		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1732

1733 1734
	intel_runtime_pm_put(dev_priv);

1735 1736
	seq_printf(m, "self-refresh: %s\n",
		   sr_enabled ? "enabled" : "disabled");
1737 1738 1739 1740

	return 0;
}

1741 1742
static int i915_emon_status(struct seq_file *m, void *unused)
{
1743 1744
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1745
	unsigned long temp, chipset, gfx;
1746 1747
	int ret;

1748
	if (!IS_GEN5(dev_priv))
1749 1750
		return -ENODEV;

1751 1752 1753
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1754 1755 1756 1757

	temp = i915_mch_val(dev_priv);
	chipset = i915_chipset_val(dev_priv);
	gfx = i915_gfx_val(dev_priv);
1758
	mutex_unlock(&dev->struct_mutex);
1759 1760 1761 1762 1763 1764 1765 1766 1767

	seq_printf(m, "GMCH temp: %ld\n", temp);
	seq_printf(m, "Chipset power: %ld\n", chipset);
	seq_printf(m, "GFX power: %ld\n", gfx);
	seq_printf(m, "Total power: %ld\n", chipset + gfx);

	return 0;
}

1768 1769
static int i915_ring_freq_table(struct seq_file *m, void *unused)
{
1770
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1771
	int ret = 0;
1772
	int gpu_freq, ia_freq;
1773
	unsigned int max_gpu_freq, min_gpu_freq;
1774

1775
	if (!HAS_LLC(dev_priv)) {
1776
		seq_puts(m, "unsupported on this chipset\n");
1777 1778 1779
		return 0;
	}

1780 1781
	intel_runtime_pm_get(dev_priv);

1782
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1783
	if (ret)
1784
		goto out;
1785

1786
	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1787 1788 1789 1790 1791 1792 1793 1794 1795 1796
		/* Convert GT frequency to 50 HZ units */
		min_gpu_freq =
			dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
		max_gpu_freq =
			dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
	} else {
		min_gpu_freq = dev_priv->rps.min_freq_softlimit;
		max_gpu_freq = dev_priv->rps.max_freq_softlimit;
	}

1797
	seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1798

1799
	for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
B
Ben Widawsky 已提交
1800 1801 1802 1803
		ia_freq = gpu_freq;
		sandybridge_pcode_read(dev_priv,
				       GEN6_PCODE_READ_MIN_FREQ_TABLE,
				       &ia_freq);
1804
		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1805
			   intel_gpu_freq(dev_priv, (gpu_freq *
1806
				(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1807
				 GEN9_FREQ_SCALER : 1))),
1808 1809
			   ((ia_freq >> 0) & 0xff) * 100,
			   ((ia_freq >> 8) & 0xff) * 100);
1810 1811
	}

1812
	mutex_unlock(&dev_priv->rps.hw_lock);
1813

1814 1815 1816
out:
	intel_runtime_pm_put(dev_priv);
	return ret;
1817 1818
}

1819 1820
static int i915_opregion(struct seq_file *m, void *unused)
{
1821 1822
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1823 1824 1825 1826 1827
	struct intel_opregion *opregion = &dev_priv->opregion;
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
1828
		goto out;
1829

1830 1831
	if (opregion->header)
		seq_write(m, opregion->header, OPREGION_SIZE);
1832 1833 1834

	mutex_unlock(&dev->struct_mutex);

1835
out:
1836 1837 1838
	return 0;
}

1839 1840
static int i915_vbt(struct seq_file *m, void *unused)
{
1841
	struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1842 1843 1844 1845 1846 1847 1848

	if (opregion->vbt)
		seq_write(m, opregion->vbt, opregion->vbt_size);

	return 0;
}

1849 1850
static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
{
1851 1852
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1853
	struct intel_framebuffer *fbdev_fb = NULL;
1854
	struct drm_framebuffer *drm_fb;
1855 1856 1857 1858 1859
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1860

1861
#ifdef CONFIG_DRM_FBDEV_EMULATION
1862 1863
	if (dev_priv->fbdev) {
		fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874

		seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
			   fbdev_fb->base.width,
			   fbdev_fb->base.height,
			   fbdev_fb->base.depth,
			   fbdev_fb->base.bits_per_pixel,
			   fbdev_fb->base.modifier[0],
			   drm_framebuffer_read_refcount(&fbdev_fb->base));
		describe_obj(m, fbdev_fb->obj);
		seq_putc(m, '\n');
	}
1875
#endif
1876

1877
	mutex_lock(&dev->mode_config.fb_lock);
1878
	drm_for_each_fb(drm_fb, dev) {
1879 1880
		struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
		if (fb == fbdev_fb)
1881 1882
			continue;

1883
		seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1884 1885 1886
			   fb->base.width,
			   fb->base.height,
			   fb->base.depth,
1887
			   fb->base.bits_per_pixel,
1888
			   fb->base.modifier[0],
1889
			   drm_framebuffer_read_refcount(&fb->base));
1890
		describe_obj(m, fb->obj);
1891
		seq_putc(m, '\n');
1892
	}
1893
	mutex_unlock(&dev->mode_config.fb_lock);
1894
	mutex_unlock(&dev->struct_mutex);
1895 1896 1897 1898

	return 0;
}

1899
static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1900 1901
{
	seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1902 1903
		   ring->space, ring->head, ring->tail,
		   ring->last_retired_head);
1904 1905
}

1906 1907
static int i915_context_status(struct seq_file *m, void *unused)
{
1908 1909
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1910
	struct intel_engine_cs *engine;
1911
	struct i915_gem_context *ctx;
1912
	int ret;
1913

1914
	ret = mutex_lock_interruptible(&dev->struct_mutex);
1915 1916 1917
	if (ret)
		return ret;

1918
	list_for_each_entry(ctx, &dev_priv->context_list, link) {
1919
		seq_printf(m, "HW context %u ", ctx->hw_id);
1920
		if (ctx->pid) {
1921 1922
			struct task_struct *task;

1923
			task = get_pid_task(ctx->pid, PIDTYPE_PID);
1924 1925 1926 1927 1928
			if (task) {
				seq_printf(m, "(%s [%d]) ",
					   task->comm, task->pid);
				put_task_struct(task);
			}
1929 1930
		} else if (IS_ERR(ctx->file_priv)) {
			seq_puts(m, "(deleted) ");
1931 1932 1933 1934
		} else {
			seq_puts(m, "(kernel) ");
		}

1935 1936
		seq_putc(m, ctx->remap_slice ? 'R' : 'r');
		seq_putc(m, '\n');
1937

1938 1939 1940 1941 1942 1943
		for_each_engine(engine, dev_priv) {
			struct intel_context *ce = &ctx->engine[engine->id];

			seq_printf(m, "%s: ", engine->name);
			seq_putc(m, ce->initialised ? 'I' : 'i');
			if (ce->state)
1944
				describe_obj(m, ce->state->obj);
1945
			if (ce->ring)
1946
				describe_ctx_ring(m, ce->ring);
1947 1948
			seq_putc(m, '\n');
		}
1949 1950

		seq_putc(m, '\n');
1951 1952
	}

1953
	mutex_unlock(&dev->struct_mutex);
1954 1955 1956 1957

	return 0;
}

1958
static void i915_dump_lrc_obj(struct seq_file *m,
1959
			      struct i915_gem_context *ctx,
1960
			      struct intel_engine_cs *engine)
1961
{
1962
	struct i915_vma *vma = ctx->engine[engine->id].state;
1963 1964 1965
	struct page *page;
	int j;

1966 1967
	seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);

1968 1969
	if (!vma) {
		seq_puts(m, "\tFake context\n");
1970 1971 1972
		return;
	}

1973 1974
	if (vma->flags & I915_VMA_GLOBAL_BIND)
		seq_printf(m, "\tBound in GGTT at 0x%08x\n",
1975
			   i915_ggtt_offset(vma));
1976

1977 1978
	if (i915_gem_object_get_pages(vma->obj)) {
		seq_puts(m, "\tFailed to get pages for context object\n\n");
1979 1980 1981
		return;
	}

1982 1983 1984
	page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
	if (page) {
		u32 *reg_state = kmap_atomic(page);
1985 1986

		for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1987 1988 1989
			seq_printf(m,
				   "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
				   j * 4,
1990 1991 1992 1993 1994 1995 1996 1997 1998
				   reg_state[j], reg_state[j + 1],
				   reg_state[j + 2], reg_state[j + 3]);
		}
		kunmap_atomic(reg_state);
	}

	seq_putc(m, '\n');
}

1999 2000
static int i915_dump_lrc(struct seq_file *m, void *unused)
{
2001 2002
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2003
	struct intel_engine_cs *engine;
2004
	struct i915_gem_context *ctx;
2005
	int ret;
2006 2007 2008 2009 2010 2011 2012 2013 2014 2015

	if (!i915.enable_execlists) {
		seq_printf(m, "Logical Ring Contexts are disabled\n");
		return 0;
	}

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

D
Dave Gordon 已提交
2016
	list_for_each_entry(ctx, &dev_priv->context_list, link)
2017 2018
		for_each_engine(engine, dev_priv)
			i915_dump_lrc_obj(m, ctx, engine);
2019 2020 2021 2022 2023 2024

	mutex_unlock(&dev->struct_mutex);

	return 0;
}

2025 2026
static int i915_execlists(struct seq_file *m, void *data)
{
2027 2028
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2029
	struct intel_engine_cs *engine;
2030 2031 2032 2033 2034 2035
	u32 status_pointer;
	u8 read_pointer;
	u8 write_pointer;
	u32 status;
	u32 ctx_id;
	struct list_head *cursor;
2036
	int i, ret;
2037 2038 2039 2040 2041 2042 2043 2044 2045 2046

	if (!i915.enable_execlists) {
		seq_puts(m, "Logical Ring Contexts are disabled\n");
		return 0;
	}

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

2047 2048
	intel_runtime_pm_get(dev_priv);

2049
	for_each_engine(engine, dev_priv) {
2050
		struct drm_i915_gem_request *head_req = NULL;
2051 2052
		int count = 0;

2053
		seq_printf(m, "%s\n", engine->name);
2054

2055 2056
		status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
		ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2057 2058 2059
		seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
			   status, ctx_id);

2060
		status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2061 2062
		seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);

2063
		read_pointer = GEN8_CSB_READ_PTR(status_pointer);
2064
		write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2065
		if (read_pointer > write_pointer)
2066
			write_pointer += GEN8_CSB_ENTRIES;
2067 2068 2069
		seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
			   read_pointer, write_pointer);

2070
		for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2071 2072
			status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
			ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2073 2074 2075 2076 2077

			seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
				   i, status, ctx_id);
		}

2078
		spin_lock_bh(&engine->execlist_lock);
2079
		list_for_each(cursor, &engine->execlist_queue)
2080
			count++;
2081 2082 2083
		head_req = list_first_entry_or_null(&engine->execlist_queue,
						    struct drm_i915_gem_request,
						    execlist_link);
2084
		spin_unlock_bh(&engine->execlist_lock);
2085 2086 2087

		seq_printf(m, "\t%d requests in queue\n", count);
		if (head_req) {
2088 2089
			seq_printf(m, "\tHead request context: %u\n",
				   head_req->ctx->hw_id);
2090
			seq_printf(m, "\tHead request tail: %u\n",
2091
				   head_req->tail);
2092 2093 2094 2095 2096
		}

		seq_putc(m, '\n');
	}

2097
	intel_runtime_pm_put(dev_priv);
2098 2099 2100 2101 2102
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

2103 2104
static const char *swizzle_string(unsigned swizzle)
{
2105
	switch (swizzle) {
2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120
	case I915_BIT_6_SWIZZLE_NONE:
		return "none";
	case I915_BIT_6_SWIZZLE_9:
		return "bit9";
	case I915_BIT_6_SWIZZLE_9_10:
		return "bit9/bit10";
	case I915_BIT_6_SWIZZLE_9_11:
		return "bit9/bit11";
	case I915_BIT_6_SWIZZLE_9_10_11:
		return "bit9/bit10/bit11";
	case I915_BIT_6_SWIZZLE_9_17:
		return "bit9/bit17";
	case I915_BIT_6_SWIZZLE_9_10_17:
		return "bit9/bit10/bit17";
	case I915_BIT_6_SWIZZLE_UNKNOWN:
2121
		return "unknown";
2122 2123 2124 2125 2126 2127 2128
	}

	return "bug";
}

static int i915_swizzle_info(struct seq_file *m, void *data)
{
2129 2130
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2131 2132 2133 2134 2135
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
2136
	intel_runtime_pm_get(dev_priv);
2137 2138 2139 2140 2141 2142

	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
		   swizzle_string(dev_priv->mm.bit_6_swizzle_x));
	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
		   swizzle_string(dev_priv->mm.bit_6_swizzle_y));

2143
	if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2144 2145
		seq_printf(m, "DDC = 0x%08x\n",
			   I915_READ(DCC));
2146 2147
		seq_printf(m, "DDC2 = 0x%08x\n",
			   I915_READ(DCC2));
2148 2149 2150 2151
		seq_printf(m, "C0DRB3 = 0x%04x\n",
			   I915_READ16(C0DRB3));
		seq_printf(m, "C1DRB3 = 0x%04x\n",
			   I915_READ16(C1DRB3));
2152
	} else if (INTEL_GEN(dev_priv) >= 6) {
2153 2154 2155 2156 2157 2158 2159 2160
		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C0));
		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C1));
		seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C2));
		seq_printf(m, "TILECTL = 0x%08x\n",
			   I915_READ(TILECTL));
2161
		if (INTEL_GEN(dev_priv) >= 8)
B
Ben Widawsky 已提交
2162 2163 2164 2165 2166
			seq_printf(m, "GAMTARBMODE = 0x%08x\n",
				   I915_READ(GAMTARBMODE));
		else
			seq_printf(m, "ARB_MODE = 0x%08x\n",
				   I915_READ(ARB_MODE));
2167 2168
		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
			   I915_READ(DISP_ARB_CTL));
2169
	}
2170 2171 2172 2173

	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
		seq_puts(m, "L-shaped memory detected\n");

2174
	intel_runtime_pm_put(dev_priv);
2175 2176 2177 2178 2179
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

B
Ben Widawsky 已提交
2180 2181
static int per_file_ctx(int id, void *ptr, void *data)
{
2182
	struct i915_gem_context *ctx = ptr;
B
Ben Widawsky 已提交
2183
	struct seq_file *m = data;
2184 2185 2186 2187 2188 2189 2190
	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;

	if (!ppgtt) {
		seq_printf(m, "  no ppgtt for context %d\n",
			   ctx->user_handle);
		return 0;
	}
B
Ben Widawsky 已提交
2191

2192 2193 2194
	if (i915_gem_context_is_default(ctx))
		seq_puts(m, "  default context:\n");
	else
2195
		seq_printf(m, "  context %d:\n", ctx->user_handle);
B
Ben Widawsky 已提交
2196 2197 2198 2199 2200
	ppgtt->debug_dump(ppgtt, m);

	return 0;
}

2201 2202
static void gen8_ppgtt_info(struct seq_file *m,
			    struct drm_i915_private *dev_priv)
D
Daniel Vetter 已提交
2203
{
2204
	struct intel_engine_cs *engine;
B
Ben Widawsky 已提交
2205
	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2206
	int i;
D
Daniel Vetter 已提交
2207

B
Ben Widawsky 已提交
2208 2209 2210
	if (!ppgtt)
		return;

2211
	for_each_engine(engine, dev_priv) {
2212
		seq_printf(m, "%s\n", engine->name);
B
Ben Widawsky 已提交
2213
		for (i = 0; i < 4; i++) {
2214
			u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
B
Ben Widawsky 已提交
2215
			pdp <<= 32;
2216
			pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2217
			seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
B
Ben Widawsky 已提交
2218 2219 2220 2221
		}
	}
}

2222 2223
static void gen6_ppgtt_info(struct seq_file *m,
			    struct drm_i915_private *dev_priv)
B
Ben Widawsky 已提交
2224
{
2225
	struct intel_engine_cs *engine;
D
Daniel Vetter 已提交
2226

2227
	if (IS_GEN6(dev_priv))
D
Daniel Vetter 已提交
2228 2229
		seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));

2230
	for_each_engine(engine, dev_priv) {
2231
		seq_printf(m, "%s\n", engine->name);
2232
		if (IS_GEN7(dev_priv))
2233 2234 2235 2236 2237 2238 2239 2240
			seq_printf(m, "GFX_MODE: 0x%08x\n",
				   I915_READ(RING_MODE_GEN7(engine)));
		seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
			   I915_READ(RING_PP_DIR_BASE(engine)));
		seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
			   I915_READ(RING_PP_DIR_BASE_READ(engine)));
		seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
			   I915_READ(RING_PP_DIR_DCLV(engine)));
D
Daniel Vetter 已提交
2241 2242 2243 2244
	}
	if (dev_priv->mm.aliasing_ppgtt) {
		struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;

2245
		seq_puts(m, "aliasing PPGTT:\n");
2246
		seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
B
Ben Widawsky 已提交
2247

B
Ben Widawsky 已提交
2248
		ppgtt->debug_dump(ppgtt, m);
2249
	}
B
Ben Widawsky 已提交
2250

D
Daniel Vetter 已提交
2251
	seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
B
Ben Widawsky 已提交
2252 2253 2254 2255
}

static int i915_ppgtt_info(struct seq_file *m, void *data)
{
2256 2257
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2258
	struct drm_file *file;
2259
	int ret;
B
Ben Widawsky 已提交
2260

2261 2262
	mutex_lock(&dev->filelist_mutex);
	ret = mutex_lock_interruptible(&dev->struct_mutex);
B
Ben Widawsky 已提交
2263
	if (ret)
2264 2265
		goto out_unlock;

2266
	intel_runtime_pm_get(dev_priv);
B
Ben Widawsky 已提交
2267

2268 2269 2270 2271
	if (INTEL_GEN(dev_priv) >= 8)
		gen8_ppgtt_info(m, dev_priv);
	else if (INTEL_GEN(dev_priv) >= 6)
		gen6_ppgtt_info(m, dev_priv);
B
Ben Widawsky 已提交
2272

2273 2274
	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct drm_i915_file_private *file_priv = file->driver_priv;
2275
		struct task_struct *task;
2276

2277
		task = get_pid_task(file->pid, PIDTYPE_PID);
2278 2279
		if (!task) {
			ret = -ESRCH;
2280
			goto out_rpm;
2281
		}
2282 2283
		seq_printf(m, "\nproc: %s\n", task->comm);
		put_task_struct(task);
2284 2285 2286 2287
		idr_for_each(&file_priv->context_idr, per_file_ctx,
			     (void *)(unsigned long)m);
	}

2288
out_rpm:
2289
	intel_runtime_pm_put(dev_priv);
D
Daniel Vetter 已提交
2290
	mutex_unlock(&dev->struct_mutex);
2291 2292
out_unlock:
	mutex_unlock(&dev->filelist_mutex);
2293
	return ret;
D
Daniel Vetter 已提交
2294 2295
}

2296 2297
static int count_irq_waiters(struct drm_i915_private *i915)
{
2298
	struct intel_engine_cs *engine;
2299 2300
	int count = 0;

2301
	for_each_engine(engine, i915)
2302
		count += intel_engine_has_waiter(engine);
2303 2304 2305 2306

	return count;
}

2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320
static const char *rps_power_to_str(unsigned int power)
{
	static const char * const strings[] = {
		[LOW_POWER] = "low power",
		[BETWEEN] = "mixed",
		[HIGH_POWER] = "high power",
	};

	if (power >= ARRAY_SIZE(strings) || !strings[power])
		return "unknown";

	return strings[power];
}

2321 2322
static int i915_rps_boost_info(struct seq_file *m, void *data)
{
2323 2324
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2325 2326
	struct drm_file *file;

2327
	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2328 2329
	seq_printf(m, "GPU busy? %s [%x]\n",
		   yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2330
	seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2331 2332 2333
	seq_printf(m, "Frequency requested %d\n",
		   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
	seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2334 2335 2336 2337
		   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
		   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
		   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
		   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2338 2339 2340 2341
	seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
		   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
		   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
		   intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2342 2343

	mutex_lock(&dev->filelist_mutex);
2344
	spin_lock(&dev_priv->rps.client_lock);
2345 2346 2347 2348 2349 2350 2351 2352 2353
	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct drm_i915_file_private *file_priv = file->driver_priv;
		struct task_struct *task;

		rcu_read_lock();
		task = pid_task(file->pid, PIDTYPE_PID);
		seq_printf(m, "%s [%d]: %d boosts%s\n",
			   task ? task->comm : "<unknown>",
			   task ? task->pid : -1,
2354 2355
			   file_priv->rps.boosts,
			   list_empty(&file_priv->rps.link) ? "" : ", active");
2356 2357
		rcu_read_unlock();
	}
2358
	seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2359
	spin_unlock(&dev_priv->rps.client_lock);
2360
	mutex_unlock(&dev->filelist_mutex);
2361

2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386
	if (INTEL_GEN(dev_priv) >= 6 &&
	    dev_priv->rps.enabled &&
	    dev_priv->gt.active_engines) {
		u32 rpup, rpupei;
		u32 rpdown, rpdownei;

		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
		rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
		rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
		rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
		rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

		seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
			   rps_power_to_str(dev_priv->rps.power));
		seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
			   100 * rpup / rpupei,
			   dev_priv->rps.up_threshold);
		seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
			   100 * rpdown / rpdownei,
			   dev_priv->rps.down_threshold);
	} else {
		seq_puts(m, "\nRPS Autotuning inactive\n");
	}

2387
	return 0;
2388 2389
}

2390 2391
static int i915_llc(struct seq_file *m, void *data)
{
2392
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2393
	const bool edram = INTEL_GEN(dev_priv) > 8;
2394

2395
	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2396 2397
	seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
		   intel_uncore_edram_size(dev_priv)/1024/1024);
2398 2399 2400 2401

	return 0;
}

2402 2403
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
2404
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2405 2406 2407
	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
	u32 tmp, i;

2408
	if (!HAS_GUC_UCODE(dev_priv))
2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421
		return 0;

	seq_printf(m, "GuC firmware status:\n");
	seq_printf(m, "\tpath: %s\n",
		guc_fw->guc_fw_path);
	seq_printf(m, "\tfetch: %s\n",
		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
	seq_printf(m, "\tload: %s\n",
		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
	seq_printf(m, "\tversion wanted: %d.%d\n",
		guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
	seq_printf(m, "\tversion found: %d.%d\n",
		guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
A
Alex Dai 已提交
2422 2423 2424 2425 2426 2427
	seq_printf(m, "\theader: offset is %d; size = %d\n",
		guc_fw->header_offset, guc_fw->header_size);
	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
		guc_fw->ucode_offset, guc_fw->ucode_size);
	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
		guc_fw->rsa_offset, guc_fw->rsa_size);
2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444

	tmp = I915_READ(GUC_STATUS);

	seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
	seq_printf(m, "\tBootrom status = 0x%x\n",
		(tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
	seq_printf(m, "\tuKernel status = 0x%x\n",
		(tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
	seq_printf(m, "\tMIA Core status = 0x%x\n",
		(tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
	seq_puts(m, "\nScratch registers:\n");
	for (i = 0; i < 16; i++)
		seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));

	return 0;
}

2445 2446 2447 2448
static void i915_guc_client_info(struct seq_file *m,
				 struct drm_i915_private *dev_priv,
				 struct i915_guc_client *client)
{
2449
	struct intel_engine_cs *engine;
2450
	enum intel_engine_id id;
2451 2452 2453 2454 2455 2456 2457 2458 2459
	uint64_t tot = 0;

	seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
		client->priority, client->ctx_index, client->proc_desc_offset);
	seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
		client->doorbell_id, client->doorbell_offset, client->cookie);
	seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
		client->wq_size, client->wq_offset, client->wq_tail);

2460
	seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2461 2462 2463
	seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
	seq_printf(m, "\tLast submission result: %d\n", client->retcode);

2464 2465 2466
	for_each_engine_id(engine, dev_priv, id) {
		u64 submissions = client->submissions[id];
		tot += submissions;
2467
		seq_printf(m, "\tSubmissions: %llu %s\n",
2468
				submissions, engine->name);
2469 2470 2471 2472 2473 2474
	}
	seq_printf(m, "\tTotal: %llu\n", tot);
}

static int i915_guc_info(struct seq_file *m, void *data)
{
2475 2476
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2477
	struct intel_guc guc;
2478
	struct i915_guc_client client = {};
2479
	struct intel_engine_cs *engine;
2480
	enum intel_engine_id id;
2481 2482
	u64 total = 0;

2483
	if (!HAS_GUC_SCHED(dev_priv))
2484 2485
		return 0;

A
Alex Dai 已提交
2486 2487 2488
	if (mutex_lock_interruptible(&dev->struct_mutex))
		return 0;

2489 2490
	/* Take a local copy of the GuC data, so we can dump it at leisure */
	guc = dev_priv->guc;
A
Alex Dai 已提交
2491
	if (guc.execbuf_client)
2492
		client = *guc.execbuf_client;
A
Alex Dai 已提交
2493 2494

	mutex_unlock(&dev->struct_mutex);
2495

2496 2497 2498 2499
	seq_printf(m, "Doorbell map:\n");
	seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
	seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);

2500 2501 2502 2503 2504 2505 2506
	seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
	seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
	seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
	seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
	seq_printf(m, "GuC last action error code: %d\n", guc.action_err);

	seq_printf(m, "\nGuC submissions:\n");
2507 2508 2509
	for_each_engine_id(engine, dev_priv, id) {
		u64 submissions = guc.submissions[id];
		total += submissions;
2510
		seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2511
			engine->name, submissions, guc.last_seqno[id]);
2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522
	}
	seq_printf(m, "\t%s: %llu\n", "Total", total);

	seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
	i915_guc_client_info(m, dev_priv, &client);

	/* Add more as required ... */

	return 0;
}

A
Alex Dai 已提交
2523 2524
static int i915_guc_log_dump(struct seq_file *m, void *data)
{
2525
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2526
	struct drm_i915_gem_object *obj;
A
Alex Dai 已提交
2527 2528
	int i = 0, pg;

2529
	if (!dev_priv->guc.log_vma)
A
Alex Dai 已提交
2530 2531
		return 0;

2532 2533 2534
	obj = dev_priv->guc.log_vma->obj;
	for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
		u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
A
Alex Dai 已提交
2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548

		for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
			seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
				   *(log + i), *(log + i + 1),
				   *(log + i + 2), *(log + i + 3));

		kunmap_atomic(log);
	}

	seq_putc(m, '\n');

	return 0;
}

2549 2550
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
2551
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
R
Rodrigo Vivi 已提交
2552
	u32 psrperf = 0;
R
Rodrigo Vivi 已提交
2553 2554
	u32 stat[3];
	enum pipe pipe;
R
Rodrigo Vivi 已提交
2555
	bool enabled = false;
2556

2557
	if (!HAS_PSR(dev_priv)) {
2558 2559 2560 2561
		seq_puts(m, "PSR not supported\n");
		return 0;
	}

2562 2563
	intel_runtime_pm_get(dev_priv);

2564
	mutex_lock(&dev_priv->psr.lock);
R
Rodrigo Vivi 已提交
2565 2566
	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
	seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2567
	seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2568
	seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2569 2570 2571 2572
	seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
		   dev_priv->psr.busy_frontbuffer_bits);
	seq_printf(m, "Re-enable work scheduled: %s\n",
		   yesno(work_busy(&dev_priv->psr.work.work)));
2573

2574
	if (HAS_DDI(dev_priv))
2575
		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2576 2577 2578 2579 2580 2581 2582
	else {
		for_each_pipe(dev_priv, pipe) {
			stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
				VLV_EDP_PSR_CURR_STATE_MASK;
			if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
			    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
				enabled = true;
R
Rodrigo Vivi 已提交
2583 2584
		}
	}
2585 2586 2587 2588

	seq_printf(m, "Main link in standby mode: %s\n",
		   yesno(dev_priv->psr.link_standby));

R
Rodrigo Vivi 已提交
2589 2590
	seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));

2591
	if (!HAS_DDI(dev_priv))
R
Rodrigo Vivi 已提交
2592 2593 2594 2595 2596 2597
		for_each_pipe(dev_priv, pipe) {
			if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
			    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
				seq_printf(m, " pipe %c", pipe_name(pipe));
		}
	seq_puts(m, "\n");
2598

2599 2600 2601 2602
	/*
	 * VLV/CHV PSR has no kind of performance counter
	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
	 */
2603
	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2604
		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
R
Rodrigo Vivi 已提交
2605
			EDP_PSR_PERF_CNT_MASK;
R
Rodrigo Vivi 已提交
2606 2607 2608

		seq_printf(m, "Performance_Counter: %u\n", psrperf);
	}
2609
	mutex_unlock(&dev_priv->psr.lock);
2610

2611
	intel_runtime_pm_put(dev_priv);
2612 2613 2614
	return 0;
}

2615 2616
static int i915_sink_crc(struct seq_file *m, void *data)
{
2617 2618
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2619 2620 2621 2622 2623 2624
	struct intel_connector *connector;
	struct intel_dp *intel_dp = NULL;
	int ret;
	u8 crc[6];

	drm_modeset_lock_all(dev);
2625
	for_each_intel_connector(dev, connector) {
2626
		struct drm_crtc *crtc;
2627

2628
		if (!connector->base.state->best_encoder)
2629 2630
			continue;

2631 2632
		crtc = connector->base.state->crtc;
		if (!crtc->state->active)
2633 2634
			continue;

2635
		if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2636 2637
			continue;

2638
		intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654

		ret = intel_dp_sink_crc(intel_dp, crc);
		if (ret)
			goto out;

		seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
			   crc[0], crc[1], crc[2],
			   crc[3], crc[4], crc[5]);
		goto out;
	}
	ret = -ENODEV;
out:
	drm_modeset_unlock_all(dev);
	return ret;
}

2655 2656
static int i915_energy_uJ(struct seq_file *m, void *data)
{
2657
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2658 2659 2660
	u64 power;
	u32 units;

2661
	if (INTEL_GEN(dev_priv) < 6)
2662 2663
		return -ENODEV;

2664 2665
	intel_runtime_pm_get(dev_priv);

2666 2667 2668 2669 2670 2671
	rdmsrl(MSR_RAPL_POWER_UNIT, power);
	power = (power & 0x1f00) >> 8;
	units = 1000000 / (1 << power); /* convert to uJ */
	power = I915_READ(MCH_SECP_NRG_STTS);
	power *= units;

2672 2673
	intel_runtime_pm_put(dev_priv);

2674
	seq_printf(m, "%llu", (long long unsigned)power);
2675 2676 2677 2678

	return 0;
}

2679
static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2680
{
2681
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
D
David Weinehall 已提交
2682
	struct pci_dev *pdev = dev_priv->drm.pdev;
2683

2684 2685
	if (!HAS_RUNTIME_PM(dev_priv))
		seq_puts(m, "Runtime power management not supported\n");
2686

2687
	seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2688
	seq_printf(m, "IRQs disabled: %s\n",
2689
		   yesno(!intel_irqs_enabled(dev_priv)));
2690
#ifdef CONFIG_PM
2691
	seq_printf(m, "Usage count: %d\n",
2692
		   atomic_read(&dev_priv->drm.dev->power.usage_count));
2693 2694 2695
#else
	seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
#endif
2696
	seq_printf(m, "PCI device power state: %s [%d]\n",
D
David Weinehall 已提交
2697 2698
		   pci_power_name(pdev->current_state),
		   pdev->current_state);
2699

2700 2701 2702
	return 0;
}

2703 2704
static int i915_power_domain_info(struct seq_file *m, void *unused)
{
2705
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725
	struct i915_power_domains *power_domains = &dev_priv->power_domains;
	int i;

	mutex_lock(&power_domains->lock);

	seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
	for (i = 0; i < power_domains->power_well_count; i++) {
		struct i915_power_well *power_well;
		enum intel_display_power_domain power_domain;

		power_well = &power_domains->power_wells[i];
		seq_printf(m, "%-25s %d\n", power_well->name,
			   power_well->count);

		for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
		     power_domain++) {
			if (!(BIT(power_domain) & power_well->domains))
				continue;

			seq_printf(m, "  %-23s %d\n",
2726
				 intel_display_power_domain_str(power_domain),
2727 2728 2729 2730 2731 2732 2733 2734 2735
				 power_domains->domain_use_count[power_domain]);
		}
	}

	mutex_unlock(&power_domains->lock);

	return 0;
}

2736 2737
static int i915_dmc_info(struct seq_file *m, void *unused)
{
2738
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2739 2740
	struct intel_csr *csr;

2741
	if (!HAS_CSR(dev_priv)) {
2742 2743 2744 2745 2746 2747
		seq_puts(m, "not supported\n");
		return 0;
	}

	csr = &dev_priv->csr;

2748 2749
	intel_runtime_pm_get(dev_priv);

2750 2751 2752 2753
	seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
	seq_printf(m, "path: %s\n", csr->fw_path);

	if (!csr->dmc_payload)
2754
		goto out;
2755 2756 2757 2758

	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
		   CSR_VERSION_MINOR(csr->version));

2759
	if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2760 2761 2762 2763
		seq_printf(m, "DC3 -> DC5 count: %d\n",
			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
		seq_printf(m, "DC5 -> DC6 count: %d\n",
			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
2764
	} else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2765 2766
		seq_printf(m, "DC3 -> DC5 count: %d\n",
			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
2767 2768
	}

2769 2770 2771 2772 2773
out:
	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));

2774 2775
	intel_runtime_pm_put(dev_priv);

2776 2777 2778
	return 0;
}

2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800
static void intel_seq_print_mode(struct seq_file *m, int tabs,
				 struct drm_display_mode *mode)
{
	int i;

	for (i = 0; i < tabs; i++)
		seq_putc(m, '\t');

	seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
		   mode->base.id, mode->name,
		   mode->vrefresh, mode->clock,
		   mode->hdisplay, mode->hsync_start,
		   mode->hsync_end, mode->htotal,
		   mode->vdisplay, mode->vsync_start,
		   mode->vsync_end, mode->vtotal,
		   mode->type, mode->flags);
}

static void intel_encoder_info(struct seq_file *m,
			       struct intel_crtc *intel_crtc,
			       struct intel_encoder *intel_encoder)
{
2801 2802
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2803 2804 2805 2806 2807 2808
	struct drm_crtc *crtc = &intel_crtc->base;
	struct intel_connector *intel_connector;
	struct drm_encoder *encoder;

	encoder = &intel_encoder->base;
	seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2809
		   encoder->base.id, encoder->name);
2810 2811 2812 2813
	for_each_connector_on_encoder(dev, encoder, intel_connector) {
		struct drm_connector *connector = &intel_connector->base;
		seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
			   connector->base.id,
2814
			   connector->name,
2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827
			   drm_get_connector_status_name(connector->status));
		if (connector->status == connector_status_connected) {
			struct drm_display_mode *mode = &crtc->mode;
			seq_printf(m, ", mode:\n");
			intel_seq_print_mode(m, 2, mode);
		} else {
			seq_putc(m, '\n');
		}
	}
}

static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
2828 2829
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2830 2831
	struct drm_crtc *crtc = &intel_crtc->base;
	struct intel_encoder *intel_encoder;
2832 2833
	struct drm_plane_state *plane_state = crtc->primary->state;
	struct drm_framebuffer *fb = plane_state->fb;
2834

2835
	if (fb)
2836
		seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2837 2838
			   fb->base.id, plane_state->src_x >> 16,
			   plane_state->src_y >> 16, fb->width, fb->height);
2839 2840
	else
		seq_puts(m, "\tprimary plane disabled\n");
2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859
	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		intel_encoder_info(m, intel_crtc, intel_encoder);
}

static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
{
	struct drm_display_mode *mode = panel->fixed_mode;

	seq_printf(m, "\tfixed mode:\n");
	intel_seq_print_mode(m, 2, mode);
}

static void intel_dp_info(struct seq_file *m,
			  struct intel_connector *intel_connector)
{
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2860
	seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2861
	if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2862
		intel_panel_info(m, &intel_connector->panel);
2863 2864 2865

	drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
				&intel_dp->aux);
2866 2867 2868 2869 2870 2871 2872 2873
}

static void intel_hdmi_info(struct seq_file *m,
			    struct intel_connector *intel_connector)
{
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);

2874
	seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887
}

static void intel_lvds_info(struct seq_file *m,
			    struct intel_connector *intel_connector)
{
	intel_panel_info(m, &intel_connector->panel);
}

static void intel_connector_info(struct seq_file *m,
				 struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct intel_encoder *intel_encoder = intel_connector->encoder;
2888
	struct drm_display_mode *mode;
2889 2890

	seq_printf(m, "connector %d: type %s, status: %s\n",
2891
		   connector->base.id, connector->name,
2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902
		   drm_get_connector_status_name(connector->status));
	if (connector->status == connector_status_connected) {
		seq_printf(m, "\tname: %s\n", connector->display_info.name);
		seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
			   connector->display_info.width_mm,
			   connector->display_info.height_mm);
		seq_printf(m, "\tsubpixel order: %s\n",
			   drm_get_subpixel_order_name(connector->display_info.subpixel_order));
		seq_printf(m, "\tCEA rev: %d\n",
			   connector->display_info.cea_rev);
	}
2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913

	if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
		return;

	switch (connector->connector_type) {
	case DRM_MODE_CONNECTOR_DisplayPort:
	case DRM_MODE_CONNECTOR_eDP:
		intel_dp_info(m, intel_connector);
		break;
	case DRM_MODE_CONNECTOR_LVDS:
		if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2914
			intel_lvds_info(m, intel_connector);
2915 2916 2917 2918 2919 2920 2921 2922
		break;
	case DRM_MODE_CONNECTOR_HDMIA:
		if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
		    intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
			intel_hdmi_info(m, intel_connector);
		break;
	default:
		break;
2923
	}
2924

2925 2926 2927
	seq_printf(m, "\tmodes:\n");
	list_for_each_entry(mode, &connector->modes, head)
		intel_seq_print_mode(m, 2, mode);
2928 2929
}

2930
static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2931 2932 2933
{
	u32 state;

2934
	if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2935
		state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2936
	else
2937
		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2938 2939 2940 2941

	return state;
}

2942 2943
static bool cursor_position(struct drm_i915_private *dev_priv,
			    int pipe, int *x, int *y)
2944 2945 2946
{
	u32 pos;

2947
	pos = I915_READ(CURPOS(pipe));
2948 2949 2950 2951 2952 2953 2954 2955 2956

	*x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
	if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
		*x = -*x;

	*y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
	if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
		*y = -*y;

2957
	return cursor_active(dev_priv, pipe);
2958 2959
}

2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986
static const char *plane_type(enum drm_plane_type type)
{
	switch (type) {
	case DRM_PLANE_TYPE_OVERLAY:
		return "OVL";
	case DRM_PLANE_TYPE_PRIMARY:
		return "PRI";
	case DRM_PLANE_TYPE_CURSOR:
		return "CUR";
	/*
	 * Deliberately omitting default: to generate compiler warnings
	 * when a new drm_plane_type gets added.
	 */
	}

	return "unknown";
}

static const char *plane_rotation(unsigned int rotation)
{
	static char buf[48];
	/*
	 * According to doc only one DRM_ROTATE_ is allowed but this
	 * will print them all to visualize if the values are misused
	 */
	snprintf(buf, sizeof(buf),
		 "%s%s%s%s%s%s(0x%08x)",
2987 2988 2989 2990 2991 2992
		 (rotation & DRM_ROTATE_0) ? "0 " : "",
		 (rotation & DRM_ROTATE_90) ? "90 " : "",
		 (rotation & DRM_ROTATE_180) ? "180 " : "",
		 (rotation & DRM_ROTATE_270) ? "270 " : "",
		 (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
		 (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
2993 2994 2995 2996 2997 2998 2999
		 rotation);

	return buf;
}

static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
3000 3001
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060
	struct intel_plane *intel_plane;

	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
		struct drm_plane_state *state;
		struct drm_plane *plane = &intel_plane->base;

		if (!plane->state) {
			seq_puts(m, "plane->state is NULL!\n");
			continue;
		}

		state = plane->state;

		seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
			   plane->base.id,
			   plane_type(intel_plane->base.type),
			   state->crtc_x, state->crtc_y,
			   state->crtc_w, state->crtc_h,
			   (state->src_x >> 16),
			   ((state->src_x & 0xffff) * 15625) >> 10,
			   (state->src_y >> 16),
			   ((state->src_y & 0xffff) * 15625) >> 10,
			   (state->src_w >> 16),
			   ((state->src_w & 0xffff) * 15625) >> 10,
			   (state->src_h >> 16),
			   ((state->src_h & 0xffff) * 15625) >> 10,
			   state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
			   plane_rotation(state->rotation));
	}
}

static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
	struct intel_crtc_state *pipe_config;
	int num_scalers = intel_crtc->num_scalers;
	int i;

	pipe_config = to_intel_crtc_state(intel_crtc->base.state);

	/* Not all platformas have a scaler */
	if (num_scalers) {
		seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
			   num_scalers,
			   pipe_config->scaler_state.scaler_users,
			   pipe_config->scaler_state.scaler_id);

		for (i = 0; i < SKL_NUM_SCALERS; i++) {
			struct intel_scaler *sc =
					&pipe_config->scaler_state.scalers[i];

			seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
				   i, yesno(sc->in_use), sc->mode);
		}
		seq_puts(m, "\n");
	} else {
		seq_puts(m, "\tNo scalers available on this platform\n");
	}
}

3061 3062
static int i915_display_info(struct seq_file *m, void *unused)
{
3063 3064
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3065
	struct intel_crtc *crtc;
3066 3067
	struct drm_connector *connector;

3068
	intel_runtime_pm_get(dev_priv);
3069 3070 3071
	drm_modeset_lock_all(dev);
	seq_printf(m, "CRTC info\n");
	seq_printf(m, "---------\n");
3072
	for_each_intel_crtc(dev, crtc) {
3073
		bool active;
3074
		struct intel_crtc_state *pipe_config;
3075
		int x, y;
3076

3077 3078
		pipe_config = to_intel_crtc_state(crtc->base.state);

3079
		seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3080
			   crtc->base.base.id, pipe_name(crtc->pipe),
3081
			   yesno(pipe_config->base.active),
3082 3083 3084
			   pipe_config->pipe_src_w, pipe_config->pipe_src_h,
			   yesno(pipe_config->dither), pipe_config->pipe_bpp);

3085
		if (pipe_config->base.active) {
3086 3087
			intel_crtc_info(m, crtc);

3088
			active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3089
			seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3090
				   yesno(crtc->cursor_base),
3091 3092
				   x, y, crtc->base.cursor->state->crtc_w,
				   crtc->base.cursor->state->crtc_h,
3093
				   crtc->cursor_addr, yesno(active));
3094 3095
			intel_scaler_info(m, crtc);
			intel_plane_info(m, crtc);
3096
		}
3097 3098 3099 3100

		seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
			   yesno(!crtc->cpu_fifo_underrun_disabled),
			   yesno(!crtc->pch_fifo_underrun_disabled));
3101 3102 3103 3104 3105 3106 3107 3108 3109
	}

	seq_printf(m, "\n");
	seq_printf(m, "Connector info\n");
	seq_printf(m, "--------------\n");
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		intel_connector_info(m, connector);
	}
	drm_modeset_unlock_all(dev);
3110
	intel_runtime_pm_put(dev_priv);
3111 3112 3113 3114

	return 0;
}

B
Ben Widawsky 已提交
3115 3116
static int i915_semaphore_status(struct seq_file *m, void *unused)
{
3117 3118
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3119
	struct intel_engine_cs *engine;
3120
	int num_rings = INTEL_INFO(dev_priv)->num_rings;
3121 3122
	enum intel_engine_id id;
	int j, ret;
B
Ben Widawsky 已提交
3123

3124
	if (!i915.semaphores) {
B
Ben Widawsky 已提交
3125 3126 3127 3128 3129 3130 3131
		seq_puts(m, "Semaphores are disabled\n");
		return 0;
	}

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
3132
	intel_runtime_pm_get(dev_priv);
B
Ben Widawsky 已提交
3133

3134
	if (IS_BROADWELL(dev_priv)) {
B
Ben Widawsky 已提交
3135 3136 3137
		struct page *page;
		uint64_t *seqno;

3138
		page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
B
Ben Widawsky 已提交
3139 3140

		seqno = (uint64_t *)kmap_atomic(page);
3141
		for_each_engine_id(engine, dev_priv, id) {
B
Ben Widawsky 已提交
3142 3143
			uint64_t offset;

3144
			seq_printf(m, "%s\n", engine->name);
B
Ben Widawsky 已提交
3145 3146 3147

			seq_puts(m, "  Last signal:");
			for (j = 0; j < num_rings; j++) {
3148
				offset = id * I915_NUM_ENGINES + j;
B
Ben Widawsky 已提交
3149 3150 3151 3152 3153 3154 3155
				seq_printf(m, "0x%08llx (0x%02llx) ",
					   seqno[offset], offset * 8);
			}
			seq_putc(m, '\n');

			seq_puts(m, "  Last wait:  ");
			for (j = 0; j < num_rings; j++) {
3156
				offset = id + (j * I915_NUM_ENGINES);
B
Ben Widawsky 已提交
3157 3158 3159 3160 3161 3162 3163 3164 3165
				seq_printf(m, "0x%08llx (0x%02llx) ",
					   seqno[offset], offset * 8);
			}
			seq_putc(m, '\n');

		}
		kunmap_atomic(seqno);
	} else {
		seq_puts(m, "  Last signal:");
3166
		for_each_engine(engine, dev_priv)
B
Ben Widawsky 已提交
3167 3168
			for (j = 0; j < num_rings; j++)
				seq_printf(m, "0x%08x\n",
3169
					   I915_READ(engine->semaphore.mbox.signal[j]));
B
Ben Widawsky 已提交
3170 3171 3172 3173
		seq_putc(m, '\n');
	}

	seq_puts(m, "\nSync seqno:\n");
3174 3175
	for_each_engine(engine, dev_priv) {
		for (j = 0; j < num_rings; j++)
3176 3177
			seq_printf(m, "  0x%08x ",
				   engine->semaphore.sync_seqno[j]);
B
Ben Widawsky 已提交
3178 3179 3180 3181
		seq_putc(m, '\n');
	}
	seq_putc(m, '\n');

3182
	intel_runtime_pm_put(dev_priv);
B
Ben Widawsky 已提交
3183 3184 3185 3186
	mutex_unlock(&dev->struct_mutex);
	return 0;
}

3187 3188
static int i915_shared_dplls_info(struct seq_file *m, void *unused)
{
3189 3190
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3191 3192 3193 3194 3195 3196 3197
	int i;

	drm_modeset_lock_all(dev);
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];

		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3198 3199
		seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
			   pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3200
		seq_printf(m, " tracked hardware state:\n");
3201 3202 3203 3204 3205 3206
		seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
		seq_printf(m, " dpll_md: 0x%08x\n",
			   pll->config.hw_state.dpll_md);
		seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
		seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
		seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3207 3208 3209 3210 3211 3212
	}
	drm_modeset_unlock_all(dev);

	return 0;
}

3213
static int i915_wa_registers(struct seq_file *m, void *unused)
3214 3215 3216
{
	int i;
	int ret;
3217
	struct intel_engine_cs *engine;
3218 3219
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3220
	struct i915_workarounds *workarounds = &dev_priv->workarounds;
3221
	enum intel_engine_id id;
3222 3223 3224 3225 3226 3227 3228

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	intel_runtime_pm_get(dev_priv);

3229
	seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3230
	for_each_engine_id(engine, dev_priv, id)
3231
		seq_printf(m, "HW whitelist count for %s: %d\n",
3232
			   engine->name, workarounds->hw_whitelist_count[id]);
3233
	for (i = 0; i < workarounds->count; ++i) {
3234 3235
		i915_reg_t addr;
		u32 mask, value, read;
3236
		bool ok;
3237

3238 3239 3240
		addr = workarounds->reg[i].addr;
		mask = workarounds->reg[i].mask;
		value = workarounds->reg[i].value;
3241 3242 3243
		read = I915_READ(addr);
		ok = (value & mask) == (read & mask);
		seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3244
			   i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3245 3246 3247 3248 3249 3250 3251 3252
	}

	intel_runtime_pm_put(dev_priv);
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

3253 3254
static int i915_ddb_info(struct seq_file *m, void *unused)
{
3255 3256
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3257 3258 3259 3260 3261
	struct skl_ddb_allocation *ddb;
	struct skl_ddb_entry *entry;
	enum pipe pipe;
	int plane;

3262
	if (INTEL_GEN(dev_priv) < 9)
3263 3264
		return 0;

3265 3266 3267 3268 3269 3270 3271 3272 3273
	drm_modeset_lock_all(dev);

	ddb = &dev_priv->wm.skl_hw.ddb;

	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");

	for_each_pipe(dev_priv, pipe) {
		seq_printf(m, "Pipe %c\n", pipe_name(pipe));

3274
		for_each_plane(dev_priv, pipe, plane) {
3275 3276 3277 3278 3279 3280
			entry = &ddb->plane[pipe][plane];
			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
				   entry->start, entry->end,
				   skl_ddb_entry_size(entry));
		}

3281
		entry = &ddb->plane[pipe][PLANE_CURSOR];
3282 3283 3284 3285 3286 3287 3288 3289 3290
		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
			   entry->end, skl_ddb_entry_size(entry));
	}

	drm_modeset_unlock_all(dev);

	return 0;
}

3291
static void drrs_status_per_crtc(struct seq_file *m,
3292 3293
				 struct drm_device *dev,
				 struct intel_crtc *intel_crtc)
3294
{
3295
	struct drm_i915_private *dev_priv = to_i915(dev);
3296 3297
	struct i915_drrs *drrs = &dev_priv->drrs;
	int vrefresh = 0;
3298
	struct drm_connector *connector;
3299

3300 3301 3302 3303 3304
	drm_for_each_connector(connector, dev) {
		if (connector->state->crtc != &intel_crtc->base)
			continue;

		seq_printf(m, "%s:\n", connector->name);
3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317
	}

	if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
		seq_puts(m, "\tVBT: DRRS_type: Static");
	else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
		seq_puts(m, "\tVBT: DRRS_type: Seamless");
	else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
		seq_puts(m, "\tVBT: DRRS_type: None");
	else
		seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");

	seq_puts(m, "\n\n");

3318
	if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361
		struct intel_panel *panel;

		mutex_lock(&drrs->mutex);
		/* DRRS Supported */
		seq_puts(m, "\tDRRS Supported: Yes\n");

		/* disable_drrs() will make drrs->dp NULL */
		if (!drrs->dp) {
			seq_puts(m, "Idleness DRRS: Disabled");
			mutex_unlock(&drrs->mutex);
			return;
		}

		panel = &drrs->dp->attached_connector->panel;
		seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
					drrs->busy_frontbuffer_bits);

		seq_puts(m, "\n\t\t");
		if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
			seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
			vrefresh = panel->fixed_mode->vrefresh;
		} else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
			seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
			vrefresh = panel->downclock_mode->vrefresh;
		} else {
			seq_printf(m, "DRRS_State: Unknown(%d)\n",
						drrs->refresh_rate_type);
			mutex_unlock(&drrs->mutex);
			return;
		}
		seq_printf(m, "\t\tVrefresh: %d", vrefresh);

		seq_puts(m, "\n\t\t");
		mutex_unlock(&drrs->mutex);
	} else {
		/* DRRS not supported. Print the VBT parameter*/
		seq_puts(m, "\tDRRS Supported : No");
	}
	seq_puts(m, "\n");
}

static int i915_drrs_status(struct seq_file *m, void *unused)
{
3362 3363
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3364 3365 3366
	struct intel_crtc *intel_crtc;
	int active_crtc_cnt = 0;

3367
	drm_modeset_lock_all(dev);
3368
	for_each_intel_crtc(dev, intel_crtc) {
3369
		if (intel_crtc->base.state->active) {
3370 3371 3372 3373 3374 3375
			active_crtc_cnt++;
			seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);

			drrs_status_per_crtc(m, dev, intel_crtc);
		}
	}
3376
	drm_modeset_unlock_all(dev);
3377 3378 3379 3380 3381 3382 3383

	if (!active_crtc_cnt)
		seq_puts(m, "No active crtc found\n");

	return 0;
}

3384 3385
struct pipe_crc_info {
	const char *name;
3386
	struct drm_i915_private *dev_priv;
3387 3388 3389
	enum pipe pipe;
};

3390 3391
static int i915_dp_mst_info(struct seq_file *m, void *unused)
{
3392 3393
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3394 3395
	struct intel_encoder *intel_encoder;
	struct intel_digital_port *intel_dig_port;
3396 3397
	struct drm_connector *connector;

3398
	drm_modeset_lock_all(dev);
3399 3400
	drm_for_each_connector(connector, dev) {
		if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3401
			continue;
3402 3403 3404 3405 3406 3407

		intel_encoder = intel_attached_encoder(connector);
		if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
			continue;

		intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3408 3409
		if (!intel_dig_port->dp.can_mst)
			continue;
3410

3411 3412
		seq_printf(m, "MST Source Port %c\n",
			   port_name(intel_dig_port->port));
3413 3414 3415 3416 3417 3418
		drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
	}
	drm_modeset_unlock_all(dev);
	return 0;
}

3419 3420
static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
{
3421
	struct pipe_crc_info *info = inode->i_private;
3422
	struct drm_i915_private *dev_priv = info->dev_priv;
3423 3424
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];

3425
	if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3426 3427
		return -ENODEV;

3428 3429 3430 3431
	spin_lock_irq(&pipe_crc->lock);

	if (pipe_crc->opened) {
		spin_unlock_irq(&pipe_crc->lock);
3432 3433 3434
		return -EBUSY; /* already open */
	}

3435
	pipe_crc->opened = true;
3436 3437
	filep->private_data = inode->i_private;

3438 3439
	spin_unlock_irq(&pipe_crc->lock);

3440 3441 3442 3443 3444
	return 0;
}

static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
{
3445
	struct pipe_crc_info *info = inode->i_private;
3446
	struct drm_i915_private *dev_priv = info->dev_priv;
3447 3448
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];

3449 3450 3451
	spin_lock_irq(&pipe_crc->lock);
	pipe_crc->opened = false;
	spin_unlock_irq(&pipe_crc->lock);
3452

3453 3454 3455 3456 3457 3458 3459 3460 3461
	return 0;
}

/* (6 fields, 8 chars each, space separated (5) + '\n') */
#define PIPE_CRC_LINE_LEN	(6 * 8 + 5 + 1)
/* account for \'0' */
#define PIPE_CRC_BUFFER_LEN	(PIPE_CRC_LINE_LEN + 1)

static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3462
{
3463 3464 3465
	assert_spin_locked(&pipe_crc->lock);
	return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
			INTEL_PIPE_CRC_ENTRIES_NR);
3466 3467 3468 3469 3470 3471 3472
}

static ssize_t
i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
		   loff_t *pos)
{
	struct pipe_crc_info *info = filep->private_data;
3473
	struct drm_i915_private *dev_priv = info->dev_priv;
3474 3475
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
	char buf[PIPE_CRC_BUFFER_LEN];
3476
	int n_entries;
3477 3478 3479 3480 3481 3482 3483 3484 3485 3486
	ssize_t bytes_read;

	/*
	 * Don't allow user space to provide buffers not big enough to hold
	 * a line of data.
	 */
	if (count < PIPE_CRC_LINE_LEN)
		return -EINVAL;

	if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3487
		return 0;
3488 3489

	/* nothing to read */
3490
	spin_lock_irq(&pipe_crc->lock);
3491
	while (pipe_crc_data_count(pipe_crc) == 0) {
3492 3493 3494 3495
		int ret;

		if (filep->f_flags & O_NONBLOCK) {
			spin_unlock_irq(&pipe_crc->lock);
3496
			return -EAGAIN;
3497
		}
3498

3499 3500 3501 3502 3503 3504
		ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
				pipe_crc_data_count(pipe_crc), pipe_crc->lock);
		if (ret) {
			spin_unlock_irq(&pipe_crc->lock);
			return ret;
		}
3505 3506
	}

3507
	/* We now have one or more entries to read */
3508
	n_entries = count / PIPE_CRC_LINE_LEN;
3509

3510
	bytes_read = 0;
3511 3512 3513
	while (n_entries > 0) {
		struct intel_pipe_crc_entry *entry =
			&pipe_crc->entries[pipe_crc->tail];
3514

3515 3516 3517 3518 3519 3520 3521
		if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
			     INTEL_PIPE_CRC_ENTRIES_NR) < 1)
			break;

		BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
		pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);

3522 3523 3524 3525 3526 3527
		bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
				       "%8u %8x %8x %8x %8x %8x\n",
				       entry->frame, entry->crc[0],
				       entry->crc[1], entry->crc[2],
				       entry->crc[3], entry->crc[4]);

3528 3529
		spin_unlock_irq(&pipe_crc->lock);

3530
		if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3531
			return -EFAULT;
3532

3533 3534 3535 3536 3537
		user_buf += PIPE_CRC_LINE_LEN;
		n_entries--;

		spin_lock_irq(&pipe_crc->lock);
	}
3538

3539 3540
	spin_unlock_irq(&pipe_crc->lock);

3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568
	return bytes_read;
}

static const struct file_operations i915_pipe_crc_fops = {
	.owner = THIS_MODULE,
	.open = i915_pipe_crc_open,
	.read = i915_pipe_crc_read,
	.release = i915_pipe_crc_release,
};

static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
	{
		.name = "i915_pipe_A_crc",
		.pipe = PIPE_A,
	},
	{
		.name = "i915_pipe_B_crc",
		.pipe = PIPE_B,
	},
	{
		.name = "i915_pipe_C_crc",
		.pipe = PIPE_C,
	},
};

static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
				enum pipe pipe)
{
3569
	struct drm_i915_private *dev_priv = to_i915(minor->dev);
3570 3571 3572
	struct dentry *ent;
	struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];

3573
	info->dev_priv = dev_priv;
3574 3575
	ent = debugfs_create_file(info->name, S_IRUGO, root, info,
				  &i915_pipe_crc_fops);
3576 3577
	if (!ent)
		return -ENOMEM;
3578 3579

	return drm_add_fake_info_node(minor, ent, info);
3580 3581
}

D
Daniel Vetter 已提交
3582
static const char * const pipe_crc_sources[] = {
3583 3584 3585 3586
	"none",
	"plane1",
	"plane2",
	"pf",
3587
	"pipe",
D
Daniel Vetter 已提交
3588 3589 3590 3591
	"TV",
	"DP-B",
	"DP-C",
	"DP-D",
3592
	"auto",
3593 3594 3595 3596 3597 3598 3599 3600
};

static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
{
	BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
	return pipe_crc_sources[source];
}

3601
static int display_crc_ctl_show(struct seq_file *m, void *data)
3602
{
3603
	struct drm_i915_private *dev_priv = m->private;
3604 3605 3606 3607 3608 3609 3610 3611 3612
	int i;

	for (i = 0; i < I915_MAX_PIPES; i++)
		seq_printf(m, "%c %s\n", pipe_name(i),
			   pipe_crc_source_name(dev_priv->pipe_crc[i].source));

	return 0;
}

3613
static int display_crc_ctl_open(struct inode *inode, struct file *file)
3614
{
3615
	return single_open(file, display_crc_ctl_show, inode->i_private);
3616 3617
}

3618
static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
D
Daniel Vetter 已提交
3619 3620
				 uint32_t *val)
{
3621 3622 3623 3624
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PIPE;

	switch (*source) {
D
Daniel Vetter 已提交
3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
		break;
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

3638 3639
static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
				     enum pipe pipe,
3640 3641
				     enum intel_pipe_crc_source *source)
{
3642
	struct drm_device *dev = &dev_priv->drm;
3643 3644
	struct intel_encoder *encoder;
	struct intel_crtc *crtc;
3645
	struct intel_digital_port *dig_port;
3646 3647 3648 3649
	int ret = 0;

	*source = INTEL_PIPE_CRC_SOURCE_PIPE;

3650
	drm_modeset_lock_all(dev);
3651
	for_each_intel_encoder(dev, encoder) {
3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663
		if (!encoder->base.crtc)
			continue;

		crtc = to_intel_crtc(encoder->base.crtc);

		if (crtc->pipe != pipe)
			continue;

		switch (encoder->type) {
		case INTEL_OUTPUT_TVOUT:
			*source = INTEL_PIPE_CRC_SOURCE_TV;
			break;
3664
		case INTEL_OUTPUT_DP:
3665
		case INTEL_OUTPUT_EDP:
3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681
			dig_port = enc_to_dig_port(&encoder->base);
			switch (dig_port->port) {
			case PORT_B:
				*source = INTEL_PIPE_CRC_SOURCE_DP_B;
				break;
			case PORT_C:
				*source = INTEL_PIPE_CRC_SOURCE_DP_C;
				break;
			case PORT_D:
				*source = INTEL_PIPE_CRC_SOURCE_DP_D;
				break;
			default:
				WARN(1, "nonexisting DP port %c\n",
				     port_name(dig_port->port));
				break;
			}
3682
			break;
3683 3684
		default:
			break;
3685 3686
		}
	}
3687
	drm_modeset_unlock_all(dev);
3688 3689 3690 3691

	return ret;
}

3692
static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3693 3694
				enum pipe pipe,
				enum intel_pipe_crc_source *source,
D
Daniel Vetter 已提交
3695 3696
				uint32_t *val)
{
3697 3698
	bool need_stable_symbols = false;

3699
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3700
		int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3701 3702 3703 3704 3705
		if (ret)
			return ret;
	}

	switch (*source) {
D
Daniel Vetter 已提交
3706 3707 3708 3709 3710
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_B:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3711
		need_stable_symbols = true;
D
Daniel Vetter 已提交
3712 3713 3714
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_C:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3715
		need_stable_symbols = true;
D
Daniel Vetter 已提交
3716
		break;
3717
	case INTEL_PIPE_CRC_SOURCE_DP_D:
3718
		if (!IS_CHERRYVIEW(dev_priv))
3719 3720 3721 3722
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
		need_stable_symbols = true;
		break;
D
Daniel Vetter 已提交
3723 3724 3725 3726 3727 3728 3729
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742
	/*
	 * When the pipe CRC tap point is after the transcoders we need
	 * to tweak symbol-level features to produce a deterministic series of
	 * symbols for a given frame. We need to reset those features only once
	 * a frame (instead of every nth symbol):
	 *   - DC-balance: used to ensure a better clock recovery from the data
	 *     link (SDVO)
	 *   - DisplayPort scrambling: used for EMI reduction
	 */
	if (need_stable_symbols) {
		uint32_t tmp = I915_READ(PORT_DFT2_G4X);

		tmp |= DC_BALANCE_RESET_VLV;
3743 3744
		switch (pipe) {
		case PIPE_A:
3745
			tmp |= PIPE_A_SCRAMBLE_RESET;
3746 3747
			break;
		case PIPE_B:
3748
			tmp |= PIPE_B_SCRAMBLE_RESET;
3749 3750 3751 3752 3753 3754 3755
			break;
		case PIPE_C:
			tmp |= PIPE_C_SCRAMBLE_RESET;
			break;
		default:
			return -EINVAL;
		}
3756 3757 3758
		I915_WRITE(PORT_DFT2_G4X, tmp);
	}

D
Daniel Vetter 已提交
3759 3760 3761
	return 0;
}

3762
static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3763 3764
				 enum pipe pipe,
				 enum intel_pipe_crc_source *source,
3765 3766
				 uint32_t *val)
{
3767 3768
	bool need_stable_symbols = false;

3769
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3770
		int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3771 3772 3773 3774 3775
		if (ret)
			return ret;
	}

	switch (*source) {
3776 3777 3778 3779
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
		break;
	case INTEL_PIPE_CRC_SOURCE_TV:
3780
		if (!SUPPORTS_TV(dev_priv))
3781 3782 3783 3784
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_B:
3785
		if (!IS_G4X(dev_priv))
3786 3787
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3788
		need_stable_symbols = true;
3789 3790
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_C:
3791
		if (!IS_G4X(dev_priv))
3792 3793
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3794
		need_stable_symbols = true;
3795 3796
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_D:
3797
		if (!IS_G4X(dev_priv))
3798 3799
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3800
		need_stable_symbols = true;
3801 3802 3803 3804 3805 3806 3807 3808
		break;
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820
	/*
	 * When the pipe CRC tap point is after the transcoders we need
	 * to tweak symbol-level features to produce a deterministic series of
	 * symbols for a given frame. We need to reset those features only once
	 * a frame (instead of every nth symbol):
	 *   - DC-balance: used to ensure a better clock recovery from the data
	 *     link (SDVO)
	 *   - DisplayPort scrambling: used for EMI reduction
	 */
	if (need_stable_symbols) {
		uint32_t tmp = I915_READ(PORT_DFT2_G4X);

3821
		WARN_ON(!IS_G4X(dev_priv));
3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833

		I915_WRITE(PORT_DFT_I9XX,
			   I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);

		if (pipe == PIPE_A)
			tmp |= PIPE_A_SCRAMBLE_RESET;
		else
			tmp |= PIPE_B_SCRAMBLE_RESET;

		I915_WRITE(PORT_DFT2_G4X, tmp);
	}

3834 3835 3836
	return 0;
}

3837
static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3838 3839 3840 3841
					 enum pipe pipe)
{
	uint32_t tmp = I915_READ(PORT_DFT2_G4X);

3842 3843
	switch (pipe) {
	case PIPE_A:
3844
		tmp &= ~PIPE_A_SCRAMBLE_RESET;
3845 3846
		break;
	case PIPE_B:
3847
		tmp &= ~PIPE_B_SCRAMBLE_RESET;
3848 3849 3850 3851 3852 3853 3854
		break;
	case PIPE_C:
		tmp &= ~PIPE_C_SCRAMBLE_RESET;
		break;
	default:
		return;
	}
3855 3856 3857 3858 3859 3860
	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
		tmp &= ~DC_BALANCE_RESET_VLV;
	I915_WRITE(PORT_DFT2_G4X, tmp);

}

3861
static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877
					 enum pipe pipe)
{
	uint32_t tmp = I915_READ(PORT_DFT2_G4X);

	if (pipe == PIPE_A)
		tmp &= ~PIPE_A_SCRAMBLE_RESET;
	else
		tmp &= ~PIPE_B_SCRAMBLE_RESET;
	I915_WRITE(PORT_DFT2_G4X, tmp);

	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
		I915_WRITE(PORT_DFT_I9XX,
			   I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
	}
}

3878
static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3879 3880
				uint32_t *val)
{
3881 3882 3883 3884
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PIPE;

	switch (*source) {
3885 3886 3887 3888 3889 3890 3891 3892 3893
	case INTEL_PIPE_CRC_SOURCE_PLANE1:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
		break;
	case INTEL_PIPE_CRC_SOURCE_PLANE2:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
		break;
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
		break;
D
Daniel Vetter 已提交
3894
	case INTEL_PIPE_CRC_SOURCE_NONE:
3895 3896
		*val = 0;
		break;
D
Daniel Vetter 已提交
3897 3898
	default:
		return -EINVAL;
3899 3900 3901 3902 3903
	}

	return 0;
}

3904 3905
static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
					bool enable)
3906
{
3907
	struct drm_device *dev = &dev_priv->drm;
3908 3909
	struct intel_crtc *crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3910
	struct intel_crtc_state *pipe_config;
3911 3912
	struct drm_atomic_state *state;
	int ret = 0;
3913 3914

	drm_modeset_lock_all(dev);
3915 3916 3917 3918
	state = drm_atomic_state_alloc(dev);
	if (!state) {
		ret = -ENOMEM;
		goto out;
3919 3920
	}

3921 3922 3923 3924 3925 3926
	state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
	pipe_config = intel_atomic_get_crtc_state(state, crtc);
	if (IS_ERR(pipe_config)) {
		ret = PTR_ERR(pipe_config);
		goto out;
	}
3927

3928 3929 3930 3931
	pipe_config->pch_pfit.force_thru = enable;
	if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
	    pipe_config->pch_pfit.enabled != enable)
		pipe_config->base.connectors_changed = true;
3932

3933 3934
	ret = drm_atomic_commit(state);
out:
3935
	drm_modeset_unlock_all(dev);
3936 3937 3938
	WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
	if (ret)
		drm_atomic_state_free(state);
3939 3940
}

3941
static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3942 3943
				enum pipe pipe,
				enum intel_pipe_crc_source *source,
3944 3945
				uint32_t *val)
{
3946 3947 3948 3949
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PF;

	switch (*source) {
3950 3951 3952 3953 3954 3955 3956
	case INTEL_PIPE_CRC_SOURCE_PLANE1:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
		break;
	case INTEL_PIPE_CRC_SOURCE_PLANE2:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
		break;
	case INTEL_PIPE_CRC_SOURCE_PF:
3957 3958
		if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
			hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
3959

3960 3961
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
		break;
D
Daniel Vetter 已提交
3962
	case INTEL_PIPE_CRC_SOURCE_NONE:
3963 3964
		*val = 0;
		break;
D
Daniel Vetter 已提交
3965 3966
	default:
		return -EINVAL;
3967 3968 3969 3970 3971
	}

	return 0;
}

3972 3973
static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
			       enum pipe pipe,
3974 3975
			       enum intel_pipe_crc_source source)
{
3976
	struct drm_device *dev = &dev_priv->drm;
3977
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3978 3979
	struct intel_crtc *crtc =
			to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
3980
	enum intel_display_power_domain power_domain;
3981
	u32 val = 0; /* shut up gcc */
3982
	int ret;
3983

3984 3985 3986
	if (pipe_crc->source == source)
		return 0;

3987 3988 3989 3990
	/* forbid changing the source without going back to 'none' */
	if (pipe_crc->source && source)
		return -EINVAL;

3991 3992
	power_domain = POWER_DOMAIN_PIPE(pipe);
	if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
3993 3994 3995 3996
		DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
		return -EIO;
	}

3997
	if (IS_GEN2(dev_priv))
3998
		ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3999 4000 4001 4002 4003
	else if (INTEL_GEN(dev_priv) < 5)
		ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
	else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4004
		ret = ilk_pipe_crc_ctl_reg(&source, &val);
4005
	else
4006
		ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4007 4008

	if (ret != 0)
4009
		goto out;
4010

4011 4012
	/* none -> real source transition */
	if (source) {
4013 4014
		struct intel_pipe_crc_entry *entries;

4015 4016 4017
		DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
				 pipe_name(pipe), pipe_crc_source_name(source));

4018 4019
		entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
				  sizeof(pipe_crc->entries[0]),
4020
				  GFP_KERNEL);
4021 4022 4023 4024
		if (!entries) {
			ret = -ENOMEM;
			goto out;
		}
4025

4026 4027 4028 4029 4030 4031 4032 4033
		/*
		 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
		 * enabled and disabled dynamically based on package C states,
		 * user space can't make reliable use of the CRCs, so let's just
		 * completely disable it.
		 */
		hsw_disable_ips(crtc);

4034
		spin_lock_irq(&pipe_crc->lock);
4035
		kfree(pipe_crc->entries);
4036
		pipe_crc->entries = entries;
4037 4038 4039
		pipe_crc->head = 0;
		pipe_crc->tail = 0;
		spin_unlock_irq(&pipe_crc->lock);
4040 4041
	}

4042
	pipe_crc->source = source;
4043 4044 4045 4046

	I915_WRITE(PIPE_CRC_CTL(pipe), val);
	POSTING_READ(PIPE_CRC_CTL(pipe));

4047 4048
	/* real source -> none transition */
	if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4049
		struct intel_pipe_crc_entry *entries;
4050 4051
		struct intel_crtc *crtc =
			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4052

4053 4054 4055
		DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
				 pipe_name(pipe));

4056
		drm_modeset_lock(&crtc->base.mutex, NULL);
4057
		if (crtc->base.state->active)
4058 4059
			intel_wait_for_vblank(dev, pipe);
		drm_modeset_unlock(&crtc->base.mutex);
4060

4061 4062
		spin_lock_irq(&pipe_crc->lock);
		entries = pipe_crc->entries;
4063
		pipe_crc->entries = NULL;
4064 4065
		pipe_crc->head = 0;
		pipe_crc->tail = 0;
4066 4067 4068
		spin_unlock_irq(&pipe_crc->lock);

		kfree(entries);
4069

4070 4071 4072 4073 4074 4075
		if (IS_G4X(dev_priv))
			g4x_undo_pipe_scramble_reset(dev_priv, pipe);
		else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
			vlv_undo_pipe_scramble_reset(dev_priv, pipe);
		else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
			hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4076 4077

		hsw_enable_ips(crtc);
4078 4079
	}

4080 4081 4082 4083 4084 4085
	ret = 0;

out:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
4086 4087 4088 4089
}

/*
 * Parse pipe CRC command strings:
4090 4091 4092
 *   command: wsp* object wsp+ name wsp+ source wsp*
 *   object: 'pipe'
 *   name: (A | B | C)
4093 4094 4095 4096
 *   source: (none | plane1 | plane2 | pf)
 *   wsp: (#0x20 | #0x9 | #0xA)+
 *
 * eg.:
4097 4098
 *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
 *  "pipe A none"    ->  Stop CRC
4099
 */
4100
static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130
{
	int n_words = 0;

	while (*buf) {
		char *end;

		/* skip leading white space */
		buf = skip_spaces(buf);
		if (!*buf)
			break;	/* end of buffer */

		/* find end of word */
		for (end = buf; *end && !isspace(*end); end++)
			;

		if (n_words == max_words) {
			DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
					 max_words);
			return -EINVAL;	/* ran out of words[] before bytes */
		}

		if (*end)
			*end++ = '\0';
		words[n_words++] = buf;
		buf = end;
	}

	return n_words;
}

4131 4132 4133 4134
enum intel_pipe_crc_object {
	PIPE_CRC_OBJECT_PIPE,
};

D
Daniel Vetter 已提交
4135
static const char * const pipe_crc_objects[] = {
4136 4137 4138 4139
	"pipe",
};

static int
4140
display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4141 4142 4143 4144 4145
{
	int i;

	for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
		if (!strcmp(buf, pipe_crc_objects[i])) {
4146
			*o = i;
4147 4148 4149 4150 4151 4152
			return 0;
		    }

	return -EINVAL;
}

4153
static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165
{
	const char name = buf[0];

	if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
		return -EINVAL;

	*pipe = name - 'A';

	return 0;
}

static int
4166
display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4167 4168 4169 4170 4171
{
	int i;

	for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
		if (!strcmp(buf, pipe_crc_sources[i])) {
4172
			*s = i;
4173 4174 4175 4176 4177 4178
			return 0;
		    }

	return -EINVAL;
}

4179 4180
static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
				 char *buf, size_t len)
4181
{
4182
#define N_WORDS 3
4183
	int n_words;
4184
	char *words[N_WORDS];
4185
	enum pipe pipe;
4186
	enum intel_pipe_crc_object object;
4187 4188
	enum intel_pipe_crc_source source;

4189
	n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4190 4191 4192 4193 4194 4195
	if (n_words != N_WORDS) {
		DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
				 N_WORDS);
		return -EINVAL;
	}

4196
	if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4197
		DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4198 4199 4200
		return -EINVAL;
	}

4201
	if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4202
		DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4203 4204 4205
		return -EINVAL;
	}

4206
	if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4207
		DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4208 4209 4210
		return -EINVAL;
	}

4211
	return pipe_crc_set_source(dev_priv, pipe, source);
4212 4213
}

4214 4215
static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
				     size_t len, loff_t *offp)
4216 4217
{
	struct seq_file *m = file->private_data;
4218
	struct drm_i915_private *dev_priv = m->private;
4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240
	char *tmpbuf;
	int ret;

	if (len == 0)
		return 0;

	if (len > PAGE_SIZE - 1) {
		DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
				 PAGE_SIZE);
		return -E2BIG;
	}

	tmpbuf = kmalloc(len + 1, GFP_KERNEL);
	if (!tmpbuf)
		return -ENOMEM;

	if (copy_from_user(tmpbuf, ubuf, len)) {
		ret = -EFAULT;
		goto out;
	}
	tmpbuf[len] = '\0';

4241
	ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4242 4243 4244 4245 4246 4247 4248 4249 4250 4251

out:
	kfree(tmpbuf);
	if (ret < 0)
		return ret;

	*offp += len;
	return len;
}

4252
static const struct file_operations i915_display_crc_ctl_fops = {
4253
	.owner = THIS_MODULE,
4254
	.open = display_crc_ctl_open,
4255 4256 4257
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
4258
	.write = display_crc_ctl_write
4259 4260
};

4261
static ssize_t i915_displayport_test_active_write(struct file *file,
4262 4263
						  const char __user *ubuf,
						  size_t len, loff_t *offp)
4264 4265 4266 4267 4268 4269 4270 4271 4272
{
	char *input_buffer;
	int status = 0;
	struct drm_device *dev;
	struct drm_connector *connector;
	struct list_head *connector_list;
	struct intel_dp *intel_dp;
	int val = 0;

4273
	dev = ((struct seq_file *)file->private_data)->private;
4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296

	connector_list = &dev->mode_config.connector_list;

	if (len == 0)
		return 0;

	input_buffer = kmalloc(len + 1, GFP_KERNEL);
	if (!input_buffer)
		return -ENOMEM;

	if (copy_from_user(input_buffer, ubuf, len)) {
		status = -EFAULT;
		goto out;
	}

	input_buffer[len] = '\0';
	DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);

	list_for_each_entry(connector, connector_list, head) {
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

4297
		if (connector->status == connector_status_connected &&
4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			status = kstrtoint(input_buffer, 10, &val);
			if (status < 0)
				goto out;
			DRM_DEBUG_DRIVER("Got %d for test active\n", val);
			/* To prevent erroneous activation of the compliance
			 * testing code, only accept an actual value of 1 here
			 */
			if (val == 1)
				intel_dp->compliance_test_active = 1;
			else
				intel_dp->compliance_test_active = 0;
		}
	}
out:
	kfree(input_buffer);
	if (status < 0)
		return status;

	*offp += len;
	return len;
}

static int i915_displayport_test_active_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
	struct drm_connector *connector;
	struct list_head *connector_list = &dev->mode_config.connector_list;
	struct intel_dp *intel_dp;

	list_for_each_entry(connector, connector_list, head) {
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

		if (connector->status == connector_status_connected &&
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			if (intel_dp->compliance_test_active)
				seq_puts(m, "1");
			else
				seq_puts(m, "0");
		} else
			seq_puts(m, "0");
	}

	return 0;
}

static int i915_displayport_test_active_open(struct inode *inode,
4349
					     struct file *file)
4350
{
4351
	struct drm_i915_private *dev_priv = inode->i_private;
4352

4353 4354
	return single_open(file, i915_displayport_test_active_show,
			   &dev_priv->drm);
4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388
}

static const struct file_operations i915_displayport_test_active_fops = {
	.owner = THIS_MODULE,
	.open = i915_displayport_test_active_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = i915_displayport_test_active_write
};

static int i915_displayport_test_data_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
	struct drm_connector *connector;
	struct list_head *connector_list = &dev->mode_config.connector_list;
	struct intel_dp *intel_dp;

	list_for_each_entry(connector, connector_list, head) {
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

		if (connector->status == connector_status_connected &&
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			seq_printf(m, "%lx", intel_dp->compliance_test_data);
		} else
			seq_puts(m, "0");
	}

	return 0;
}
static int i915_displayport_test_data_open(struct inode *inode,
4389
					   struct file *file)
4390
{
4391
	struct drm_i915_private *dev_priv = inode->i_private;
4392

4393 4394
	return single_open(file, i915_displayport_test_data_show,
			   &dev_priv->drm);
4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430
}

static const struct file_operations i915_displayport_test_data_fops = {
	.owner = THIS_MODULE,
	.open = i915_displayport_test_data_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release
};

static int i915_displayport_test_type_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
	struct drm_connector *connector;
	struct list_head *connector_list = &dev->mode_config.connector_list;
	struct intel_dp *intel_dp;

	list_for_each_entry(connector, connector_list, head) {
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

		if (connector->status == connector_status_connected &&
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			seq_printf(m, "%02lx", intel_dp->compliance_test_type);
		} else
			seq_puts(m, "0");
	}

	return 0;
}

static int i915_displayport_test_type_open(struct inode *inode,
				       struct file *file)
{
4431
	struct drm_i915_private *dev_priv = inode->i_private;
4432

4433 4434
	return single_open(file, i915_displayport_test_type_show,
			   &dev_priv->drm);
4435 4436 4437 4438 4439 4440 4441 4442 4443 4444
}

static const struct file_operations i915_displayport_test_type_fops = {
	.owner = THIS_MODULE,
	.open = i915_displayport_test_type_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release
};

4445
static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4446
{
4447 4448
	struct drm_i915_private *dev_priv = m->private;
	struct drm_device *dev = &dev_priv->drm;
4449
	int level;
4450 4451
	int num_levels;

4452
	if (IS_CHERRYVIEW(dev_priv))
4453
		num_levels = 3;
4454
	else if (IS_VALLEYVIEW(dev_priv))
4455 4456 4457
		num_levels = 1;
	else
		num_levels = ilk_wm_max_level(dev) + 1;
4458 4459 4460 4461 4462 4463

	drm_modeset_lock_all(dev);

	for (level = 0; level < num_levels; level++) {
		unsigned int latency = wm[level];

4464 4465
		/*
		 * - WM1+ latency values in 0.5us units
4466
		 * - latencies are in us on gen9/vlv/chv
4467
		 */
4468 4469
		if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
		    IS_CHERRYVIEW(dev_priv))
4470 4471
			latency *= 10;
		else if (level > 0)
4472 4473 4474
			latency *= 5;

		seq_printf(m, "WM%d %u (%u.%u usec)\n",
4475
			   level, wm[level], latency / 10, latency % 10);
4476 4477 4478 4479 4480 4481 4482
	}

	drm_modeset_unlock_all(dev);
}

static int pri_wm_latency_show(struct seq_file *m, void *data)
{
4483
	struct drm_i915_private *dev_priv = m->private;
4484 4485
	const uint16_t *latencies;

4486
	if (INTEL_GEN(dev_priv) >= 9)
4487 4488
		latencies = dev_priv->wm.skl_latency;
	else
4489
		latencies = dev_priv->wm.pri_latency;
4490

4491
	wm_latency_show(m, latencies);
4492 4493 4494 4495 4496 4497

	return 0;
}

static int spr_wm_latency_show(struct seq_file *m, void *data)
{
4498
	struct drm_i915_private *dev_priv = m->private;
4499 4500
	const uint16_t *latencies;

4501
	if (INTEL_GEN(dev_priv) >= 9)
4502 4503
		latencies = dev_priv->wm.skl_latency;
	else
4504
		latencies = dev_priv->wm.spr_latency;
4505

4506
	wm_latency_show(m, latencies);
4507 4508 4509 4510 4511 4512

	return 0;
}

static int cur_wm_latency_show(struct seq_file *m, void *data)
{
4513
	struct drm_i915_private *dev_priv = m->private;
4514 4515
	const uint16_t *latencies;

4516
	if (INTEL_GEN(dev_priv) >= 9)
4517 4518
		latencies = dev_priv->wm.skl_latency;
	else
4519
		latencies = dev_priv->wm.cur_latency;
4520

4521
	wm_latency_show(m, latencies);
4522 4523 4524 4525 4526 4527

	return 0;
}

static int pri_wm_latency_open(struct inode *inode, struct file *file)
{
4528
	struct drm_i915_private *dev_priv = inode->i_private;
4529

4530
	if (INTEL_GEN(dev_priv) < 5)
4531 4532
		return -ENODEV;

4533
	return single_open(file, pri_wm_latency_show, dev_priv);
4534 4535 4536 4537
}

static int spr_wm_latency_open(struct inode *inode, struct file *file)
{
4538
	struct drm_i915_private *dev_priv = inode->i_private;
4539

4540
	if (HAS_GMCH_DISPLAY(dev_priv))
4541 4542
		return -ENODEV;

4543
	return single_open(file, spr_wm_latency_show, dev_priv);
4544 4545 4546 4547
}

static int cur_wm_latency_open(struct inode *inode, struct file *file)
{
4548
	struct drm_i915_private *dev_priv = inode->i_private;
4549

4550
	if (HAS_GMCH_DISPLAY(dev_priv))
4551 4552
		return -ENODEV;

4553
	return single_open(file, cur_wm_latency_show, dev_priv);
4554 4555 4556
}

static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4557
				size_t len, loff_t *offp, uint16_t wm[8])
4558 4559
{
	struct seq_file *m = file->private_data;
4560 4561
	struct drm_i915_private *dev_priv = m->private;
	struct drm_device *dev = &dev_priv->drm;
4562
	uint16_t new[8] = { 0 };
4563
	int num_levels;
4564 4565 4566 4567
	int level;
	int ret;
	char tmp[32];

4568
	if (IS_CHERRYVIEW(dev_priv))
4569
		num_levels = 3;
4570
	else if (IS_VALLEYVIEW(dev_priv))
4571 4572 4573 4574
		num_levels = 1;
	else
		num_levels = ilk_wm_max_level(dev) + 1;

4575 4576 4577 4578 4579 4580 4581 4582
	if (len >= sizeof(tmp))
		return -EINVAL;

	if (copy_from_user(tmp, ubuf, len))
		return -EFAULT;

	tmp[len] = '\0';

4583 4584 4585
	ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
		     &new[0], &new[1], &new[2], &new[3],
		     &new[4], &new[5], &new[6], &new[7]);
4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603
	if (ret != num_levels)
		return -EINVAL;

	drm_modeset_lock_all(dev);

	for (level = 0; level < num_levels; level++)
		wm[level] = new[level];

	drm_modeset_unlock_all(dev);

	return len;
}


static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
4604
	struct drm_i915_private *dev_priv = m->private;
4605
	uint16_t *latencies;
4606

4607
	if (INTEL_GEN(dev_priv) >= 9)
4608 4609
		latencies = dev_priv->wm.skl_latency;
	else
4610
		latencies = dev_priv->wm.pri_latency;
4611 4612

	return wm_latency_write(file, ubuf, len, offp, latencies);
4613 4614 4615 4616 4617 4618
}

static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
4619
	struct drm_i915_private *dev_priv = m->private;
4620
	uint16_t *latencies;
4621

4622
	if (INTEL_GEN(dev_priv) >= 9)
4623 4624
		latencies = dev_priv->wm.skl_latency;
	else
4625
		latencies = dev_priv->wm.spr_latency;
4626 4627

	return wm_latency_write(file, ubuf, len, offp, latencies);
4628 4629 4630 4631 4632 4633
}

static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
4634
	struct drm_i915_private *dev_priv = m->private;
4635 4636
	uint16_t *latencies;

4637
	if (INTEL_GEN(dev_priv) >= 9)
4638 4639
		latencies = dev_priv->wm.skl_latency;
	else
4640
		latencies = dev_priv->wm.cur_latency;
4641

4642
	return wm_latency_write(file, ubuf, len, offp, latencies);
4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671
}

static const struct file_operations i915_pri_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = pri_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = pri_wm_latency_write
};

static const struct file_operations i915_spr_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = spr_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = spr_wm_latency_write
};

static const struct file_operations i915_cur_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = cur_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = cur_wm_latency_write
};

4672 4673
static int
i915_wedged_get(void *data, u64 *val)
4674
{
4675
	struct drm_i915_private *dev_priv = data;
4676

4677
	*val = i915_terminally_wedged(&dev_priv->gpu_error);
4678

4679
	return 0;
4680 4681
}

4682 4683
static int
i915_wedged_set(void *data, u64 val)
4684
{
4685
	struct drm_i915_private *dev_priv = data;
4686

4687 4688 4689 4690 4691 4692 4693 4694
	/*
	 * There is no safeguard against this debugfs entry colliding
	 * with the hangcheck calling same i915_handle_error() in
	 * parallel, causing an explosion. For now we assume that the
	 * test harness is responsible enough not to inject gpu hangs
	 * while it is writing to 'i915_wedged'
	 */

4695
	if (i915_reset_in_progress(&dev_priv->gpu_error))
4696 4697
		return -EAGAIN;

4698
	intel_runtime_pm_get(dev_priv);
4699

4700
	i915_handle_error(dev_priv, val,
4701
			  "Manually setting wedged to %llu", val);
4702 4703 4704

	intel_runtime_pm_put(dev_priv);

4705
	return 0;
4706 4707
}

4708 4709
DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
			i915_wedged_get, i915_wedged_set,
4710
			"%llu\n");
4711

4712 4713 4714
static int
i915_ring_missed_irq_get(void *data, u64 *val)
{
4715
	struct drm_i915_private *dev_priv = data;
4716 4717 4718 4719 4720 4721 4722 4723

	*val = dev_priv->gpu_error.missed_irq_rings;
	return 0;
}

static int
i915_ring_missed_irq_set(void *data, u64 val)
{
4724 4725
	struct drm_i915_private *dev_priv = data;
	struct drm_device *dev = &dev_priv->drm;
4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744
	int ret;

	/* Lock against concurrent debugfs callers */
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
	dev_priv->gpu_error.missed_irq_rings = val;
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
			i915_ring_missed_irq_get, i915_ring_missed_irq_set,
			"0x%08llx\n");

static int
i915_ring_test_irq_get(void *data, u64 *val)
{
4745
	struct drm_i915_private *dev_priv = data;
4746 4747 4748 4749 4750 4751 4752 4753 4754

	*val = dev_priv->gpu_error.test_irq_rings;

	return 0;
}

static int
i915_ring_test_irq_set(void *data, u64 val)
{
4755
	struct drm_i915_private *dev_priv = data;
4756

4757
	val &= INTEL_INFO(dev_priv)->ring_mask;
4758 4759 4760 4761 4762 4763 4764 4765 4766 4767
	DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
	dev_priv->gpu_error.test_irq_rings = val;

	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
			i915_ring_test_irq_get, i915_ring_test_irq_set,
			"0x%08llx\n");

4768 4769 4770 4771 4772 4773 4774 4775
#define DROP_UNBOUND 0x1
#define DROP_BOUND 0x2
#define DROP_RETIRE 0x4
#define DROP_ACTIVE 0x8
#define DROP_ALL (DROP_UNBOUND | \
		  DROP_BOUND | \
		  DROP_RETIRE | \
		  DROP_ACTIVE)
4776 4777
static int
i915_drop_caches_get(void *data, u64 *val)
4778
{
4779
	*val = DROP_ALL;
4780

4781
	return 0;
4782 4783
}

4784 4785
static int
i915_drop_caches_set(void *data, u64 val)
4786
{
4787 4788
	struct drm_i915_private *dev_priv = data;
	struct drm_device *dev = &dev_priv->drm;
4789
	int ret;
4790

4791
	DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4792 4793 4794 4795 4796 4797 4798 4799

	/* No need to check and wait for gpu resets, only libdrm auto-restarts
	 * on ioctls on -EAGAIN. */
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	if (val & DROP_ACTIVE) {
4800 4801 4802
		ret = i915_gem_wait_for_idle(dev_priv,
					     I915_WAIT_INTERRUPTIBLE |
					     I915_WAIT_LOCKED);
4803 4804 4805 4806 4807
		if (ret)
			goto unlock;
	}

	if (val & (DROP_RETIRE | DROP_ACTIVE))
4808
		i915_gem_retire_requests(dev_priv);
4809

4810 4811
	if (val & DROP_BOUND)
		i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4812

4813 4814
	if (val & DROP_UNBOUND)
		i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4815 4816 4817 4818

unlock:
	mutex_unlock(&dev->struct_mutex);

4819
	return ret;
4820 4821
}

4822 4823 4824
DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
			i915_drop_caches_get, i915_drop_caches_set,
			"0x%08llx\n");
4825

4826 4827
static int
i915_max_freq_get(void *data, u64 *val)
4828
{
4829
	struct drm_i915_private *dev_priv = data;
4830

4831
	if (INTEL_GEN(dev_priv) < 6)
4832 4833
		return -ENODEV;

4834
	*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4835
	return 0;
4836 4837
}

4838 4839
static int
i915_max_freq_set(void *data, u64 val)
4840
{
4841
	struct drm_i915_private *dev_priv = data;
4842
	u32 hw_max, hw_min;
4843
	int ret;
4844

4845
	if (INTEL_GEN(dev_priv) < 6)
4846
		return -ENODEV;
4847

4848
	DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4849

4850
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4851 4852 4853
	if (ret)
		return ret;

4854 4855 4856
	/*
	 * Turbo will still be enabled, but won't go above the set value.
	 */
4857
	val = intel_freq_opcode(dev_priv, val);
J
Jeff McGee 已提交
4858

4859 4860
	hw_max = dev_priv->rps.max_freq;
	hw_min = dev_priv->rps.min_freq;
J
Jeff McGee 已提交
4861

4862
	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
J
Jeff McGee 已提交
4863 4864
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
4865 4866
	}

4867
	dev_priv->rps.max_freq_softlimit = val;
J
Jeff McGee 已提交
4868

4869
	intel_set_rps(dev_priv, val);
J
Jeff McGee 已提交
4870

4871
	mutex_unlock(&dev_priv->rps.hw_lock);
4872

4873
	return 0;
4874 4875
}

4876 4877
DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
			i915_max_freq_get, i915_max_freq_set,
4878
			"%llu\n");
4879

4880 4881
static int
i915_min_freq_get(void *data, u64 *val)
4882
{
4883
	struct drm_i915_private *dev_priv = data;
4884

4885
	if (INTEL_GEN(dev_priv) < 6)
4886 4887
		return -ENODEV;

4888
	*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4889
	return 0;
4890 4891
}

4892 4893
static int
i915_min_freq_set(void *data, u64 val)
4894
{
4895
	struct drm_i915_private *dev_priv = data;
4896
	u32 hw_max, hw_min;
4897
	int ret;
4898

4899
	if (INTEL_GEN(dev_priv) < 6)
4900
		return -ENODEV;
4901

4902
	DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4903

4904
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4905 4906 4907
	if (ret)
		return ret;

4908 4909 4910
	/*
	 * Turbo will still be enabled, but won't go below the set value.
	 */
4911
	val = intel_freq_opcode(dev_priv, val);
J
Jeff McGee 已提交
4912

4913 4914
	hw_max = dev_priv->rps.max_freq;
	hw_min = dev_priv->rps.min_freq;
J
Jeff McGee 已提交
4915

4916 4917
	if (val < hw_min ||
	    val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
J
Jeff McGee 已提交
4918 4919
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
4920
	}
J
Jeff McGee 已提交
4921

4922
	dev_priv->rps.min_freq_softlimit = val;
J
Jeff McGee 已提交
4923

4924
	intel_set_rps(dev_priv, val);
J
Jeff McGee 已提交
4925

4926
	mutex_unlock(&dev_priv->rps.hw_lock);
4927

4928
	return 0;
4929 4930
}

4931 4932
DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
			i915_min_freq_get, i915_min_freq_set,
4933
			"%llu\n");
4934

4935 4936
static int
i915_cache_sharing_get(void *data, u64 *val)
4937
{
4938 4939
	struct drm_i915_private *dev_priv = data;
	struct drm_device *dev = &dev_priv->drm;
4940
	u32 snpcr;
4941
	int ret;
4942

4943
	if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4944 4945
		return -ENODEV;

4946 4947 4948
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
4949
	intel_runtime_pm_get(dev_priv);
4950

4951
	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4952 4953

	intel_runtime_pm_put(dev_priv);
4954
	mutex_unlock(&dev->struct_mutex);
4955

4956
	*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4957

4958
	return 0;
4959 4960
}

4961 4962
static int
i915_cache_sharing_set(void *data, u64 val)
4963
{
4964
	struct drm_i915_private *dev_priv = data;
4965 4966
	u32 snpcr;

4967
	if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4968 4969
		return -ENODEV;

4970
	if (val > 3)
4971 4972
		return -EINVAL;

4973
	intel_runtime_pm_get(dev_priv);
4974
	DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4975 4976 4977 4978 4979 4980 4981

	/* Update the cache sharing policy here as well */
	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
	snpcr &= ~GEN6_MBC_SNPCR_MASK;
	snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);

4982
	intel_runtime_pm_put(dev_priv);
4983
	return 0;
4984 4985
}

4986 4987 4988
DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
			i915_cache_sharing_get, i915_cache_sharing_set,
			"%llu\n");
4989

4990
static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4991
					  struct sseu_dev_info *sseu)
4992
{
4993
	int ss_max = 2;
4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008
	int ss;
	u32 sig1[ss_max], sig2[ss_max];

	sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
	sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
	sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
	sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);

	for (ss = 0; ss < ss_max; ss++) {
		unsigned int eu_cnt;

		if (sig1[ss] & CHV_SS_PG_ENABLE)
			/* skip disabled subslice */
			continue;

5009
		sseu->slice_mask = BIT(0);
5010
		sseu->subslice_mask |= BIT(ss);
5011 5012 5013 5014
		eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
			 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
			 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
			 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5015 5016 5017
		sseu->eu_total += eu_cnt;
		sseu->eu_per_subslice = max_t(unsigned int,
					      sseu->eu_per_subslice, eu_cnt);
5018 5019 5020
	}
}

5021
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5022
				    struct sseu_dev_info *sseu)
5023
{
5024
	int s_max = 3, ss_max = 4;
5025 5026 5027
	int s, ss;
	u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];

5028
	/* BXT has a single slice and at most 3 subslices. */
5029
	if (IS_BROXTON(dev_priv)) {
5030 5031 5032 5033 5034 5035 5036 5037 5038 5039
		s_max = 1;
		ss_max = 3;
	}

	for (s = 0; s < s_max; s++) {
		s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
		eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
		eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
	}

5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053
	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
		     GEN9_PGCTL_SSA_EU19_ACK |
		     GEN9_PGCTL_SSA_EU210_ACK |
		     GEN9_PGCTL_SSA_EU311_ACK;
	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
		     GEN9_PGCTL_SSB_EU19_ACK |
		     GEN9_PGCTL_SSB_EU210_ACK |
		     GEN9_PGCTL_SSB_EU311_ACK;

	for (s = 0; s < s_max; s++) {
		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
			/* skip disabled slice */
			continue;

5054
		sseu->slice_mask |= BIT(s);
5055

5056
		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5057 5058
			sseu->subslice_mask =
				INTEL_INFO(dev_priv)->sseu.subslice_mask;
5059

5060 5061 5062
		for (ss = 0; ss < ss_max; ss++) {
			unsigned int eu_cnt;

5063 5064 5065 5066
			if (IS_BROXTON(dev_priv)) {
				if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
					/* skip disabled subslice */
					continue;
5067

5068 5069
				sseu->subslice_mask |= BIT(ss);
			}
5070

5071 5072
			eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
					       eu_mask[ss%2]);
5073 5074 5075 5076
			sseu->eu_total += eu_cnt;
			sseu->eu_per_subslice = max_t(unsigned int,
						      sseu->eu_per_subslice,
						      eu_cnt);
5077 5078 5079 5080
		}
	}
}

5081
static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5082
					 struct sseu_dev_info *sseu)
5083 5084
{
	u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5085
	int s;
5086

5087
	sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5088

5089
	if (sseu->slice_mask) {
5090
		sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5091 5092
		sseu->eu_per_subslice =
				INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5093 5094
		sseu->eu_total = sseu->eu_per_subslice *
				 sseu_subslice_total(sseu);
5095 5096

		/* subtract fused off EU(s) from enabled slice(s) */
5097
		for (s = 0; s < fls(sseu->slice_mask); s++) {
5098 5099
			u8 subslice_7eu =
				INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5100

5101
			sseu->eu_total -= hweight8(subslice_7eu);
5102 5103 5104 5105
		}
	}
}

5106 5107 5108 5109 5110 5111
static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
				 const struct sseu_dev_info *sseu)
{
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	const char *type = is_available_info ? "Available" : "Enabled";

5112 5113
	seq_printf(m, "  %s Slice Mask: %04x\n", type,
		   sseu->slice_mask);
5114
	seq_printf(m, "  %s Slice Total: %u\n", type,
5115
		   hweight8(sseu->slice_mask));
5116
	seq_printf(m, "  %s Subslice Total: %u\n", type,
5117
		   sseu_subslice_total(sseu));
5118 5119
	seq_printf(m, "  %s Subslice Mask: %04x\n", type,
		   sseu->subslice_mask);
5120
	seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5121
		   hweight8(sseu->subslice_mask));
5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141
	seq_printf(m, "  %s EU Total: %u\n", type,
		   sseu->eu_total);
	seq_printf(m, "  %s EU Per Subslice: %u\n", type,
		   sseu->eu_per_subslice);

	if (!is_available_info)
		return;

	seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
	if (HAS_POOLED_EU(dev_priv))
		seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);

	seq_printf(m, "  Has Slice Power Gating: %s\n",
		   yesno(sseu->has_slice_pg));
	seq_printf(m, "  Has Subslice Power Gating: %s\n",
		   yesno(sseu->has_subslice_pg));
	seq_printf(m, "  Has EU Power Gating: %s\n",
		   yesno(sseu->has_eu_pg));
}

5142 5143
static int i915_sseu_status(struct seq_file *m, void *unused)
{
5144
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
5145
	struct sseu_dev_info sseu;
5146

5147
	if (INTEL_GEN(dev_priv) < 8)
5148 5149 5150
		return -ENODEV;

	seq_puts(m, "SSEU Device Info\n");
5151
	i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5152

5153
	seq_puts(m, "SSEU Device Status\n");
5154
	memset(&sseu, 0, sizeof(sseu));
5155 5156 5157

	intel_runtime_pm_get(dev_priv);

5158
	if (IS_CHERRYVIEW(dev_priv)) {
5159
		cherryview_sseu_device_status(dev_priv, &sseu);
5160
	} else if (IS_BROADWELL(dev_priv)) {
5161
		broadwell_sseu_device_status(dev_priv, &sseu);
5162
	} else if (INTEL_GEN(dev_priv) >= 9) {
5163
		gen9_sseu_device_status(dev_priv, &sseu);
5164
	}
5165 5166 5167

	intel_runtime_pm_put(dev_priv);

5168
	i915_print_sseu_info(m, false, &sseu);
5169

5170 5171 5172
	return 0;
}

5173 5174
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
5175
	struct drm_i915_private *dev_priv = inode->i_private;
5176

5177
	if (INTEL_GEN(dev_priv) < 6)
5178 5179
		return 0;

5180
	intel_runtime_pm_get(dev_priv);
5181
	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5182 5183 5184 5185

	return 0;
}

5186
static int i915_forcewake_release(struct inode *inode, struct file *file)
5187
{
5188
	struct drm_i915_private *dev_priv = inode->i_private;
5189

5190
	if (INTEL_GEN(dev_priv) < 6)
5191 5192
		return 0;

5193
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5194
	intel_runtime_pm_put(dev_priv);
5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209

	return 0;
}

static const struct file_operations i915_forcewake_fops = {
	.owner = THIS_MODULE,
	.open = i915_forcewake_open,
	.release = i915_forcewake_release,
};

static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
{
	struct dentry *ent;

	ent = debugfs_create_file("i915_forcewake_user",
B
Ben Widawsky 已提交
5210
				  S_IRUSR,
5211
				  root, to_i915(minor->dev),
5212
				  &i915_forcewake_fops);
5213 5214
	if (!ent)
		return -ENOMEM;
5215

B
Ben Widawsky 已提交
5216
	return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5217 5218
}

5219 5220 5221 5222
static int i915_debugfs_create(struct dentry *root,
			       struct drm_minor *minor,
			       const char *name,
			       const struct file_operations *fops)
5223 5224 5225
{
	struct dentry *ent;

5226
	ent = debugfs_create_file(name,
5227
				  S_IRUGO | S_IWUSR,
5228
				  root, to_i915(minor->dev),
5229
				  fops);
5230 5231
	if (!ent)
		return -ENOMEM;
5232

5233
	return drm_add_fake_info_node(minor, ent, fops);
5234 5235
}

5236
static const struct drm_info_list i915_debugfs_list[] = {
C
Chris Wilson 已提交
5237
	{"i915_capabilities", i915_capabilities, 0},
5238
	{"i915_gem_objects", i915_gem_object_info, 0},
5239
	{"i915_gem_gtt", i915_gem_gtt_info, 0},
5240
	{"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5241
	{"i915_gem_stolen", i915_gem_stolen_list_info },
5242
	{"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5243 5244
	{"i915_gem_request", i915_gem_request_info, 0},
	{"i915_gem_seqno", i915_gem_seqno_info, 0},
5245
	{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5246
	{"i915_gem_interrupt", i915_interrupt_info, 0},
5247 5248 5249
	{"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
	{"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
	{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
X
Xiang, Haihao 已提交
5250
	{"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5251
	{"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5252
	{"i915_guc_info", i915_guc_info, 0},
5253
	{"i915_guc_load_status", i915_guc_load_status_info, 0},
A
Alex Dai 已提交
5254
	{"i915_guc_log_dump", i915_guc_log_dump, 0},
5255
	{"i915_frequency_info", i915_frequency_info, 0},
5256
	{"i915_hangcheck_info", i915_hangcheck_info, 0},
5257
	{"i915_drpc_info", i915_drpc_info, 0},
5258
	{"i915_emon_status", i915_emon_status, 0},
5259
	{"i915_ring_freq_table", i915_ring_freq_table, 0},
5260
	{"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5261
	{"i915_fbc_status", i915_fbc_status, 0},
5262
	{"i915_ips_status", i915_ips_status, 0},
5263
	{"i915_sr_status", i915_sr_status, 0},
5264
	{"i915_opregion", i915_opregion, 0},
5265
	{"i915_vbt", i915_vbt, 0},
5266
	{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5267
	{"i915_context_status", i915_context_status, 0},
5268
	{"i915_dump_lrc", i915_dump_lrc, 0},
5269
	{"i915_execlists", i915_execlists, 0},
5270
	{"i915_forcewake_domains", i915_forcewake_domains, 0},
5271
	{"i915_swizzle_info", i915_swizzle_info, 0},
D
Daniel Vetter 已提交
5272
	{"i915_ppgtt_info", i915_ppgtt_info, 0},
5273
	{"i915_llc", i915_llc, 0},
5274
	{"i915_edp_psr_status", i915_edp_psr_status, 0},
5275
	{"i915_sink_crc_eDP1", i915_sink_crc, 0},
5276
	{"i915_energy_uJ", i915_energy_uJ, 0},
5277
	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5278
	{"i915_power_domain_info", i915_power_domain_info, 0},
5279
	{"i915_dmc_info", i915_dmc_info, 0},
5280
	{"i915_display_info", i915_display_info, 0},
B
Ben Widawsky 已提交
5281
	{"i915_semaphore_status", i915_semaphore_status, 0},
5282
	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5283
	{"i915_dp_mst_info", i915_dp_mst_info, 0},
5284
	{"i915_wa_registers", i915_wa_registers, 0},
5285
	{"i915_ddb_info", i915_ddb_info, 0},
5286
	{"i915_sseu_status", i915_sseu_status, 0},
5287
	{"i915_drrs_status", i915_drrs_status, 0},
5288
	{"i915_rps_boost_info", i915_rps_boost_info, 0},
5289
};
5290
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5291

5292
static const struct i915_debugfs_files {
5293 5294 5295 5296 5297 5298 5299
	const char *name;
	const struct file_operations *fops;
} i915_debugfs_files[] = {
	{"i915_wedged", &i915_wedged_fops},
	{"i915_max_freq", &i915_max_freq_fops},
	{"i915_min_freq", &i915_min_freq_fops},
	{"i915_cache_sharing", &i915_cache_sharing_fops},
5300 5301
	{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
	{"i915_ring_test_irq", &i915_ring_test_irq_fops},
5302 5303 5304
	{"i915_gem_drop_caches", &i915_drop_caches_fops},
	{"i915_error_state", &i915_error_state_fops},
	{"i915_next_seqno", &i915_next_seqno_fops},
5305
	{"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5306 5307 5308
	{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
	{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
	{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5309
	{"i915_fbc_false_color", &i915_fbc_fc_fops},
5310 5311 5312
	{"i915_dp_test_data", &i915_displayport_test_data_fops},
	{"i915_dp_test_type", &i915_displayport_test_type_fops},
	{"i915_dp_test_active", &i915_displayport_test_active_fops}
5313 5314
};

5315
void intel_display_crc_init(struct drm_i915_private *dev_priv)
5316
{
5317
	enum pipe pipe;
5318

5319
	for_each_pipe(dev_priv, pipe) {
5320
		struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5321

5322 5323
		pipe_crc->opened = false;
		spin_lock_init(&pipe_crc->lock);
5324 5325 5326 5327
		init_waitqueue_head(&pipe_crc->wq);
	}
}

5328
int i915_debugfs_register(struct drm_i915_private *dev_priv)
5329
{
5330
	struct drm_minor *minor = dev_priv->drm.primary;
5331
	int ret, i;
5332

5333
	ret = i915_forcewake_create(minor->debugfs_root, minor);
5334 5335
	if (ret)
		return ret;
5336

5337 5338 5339 5340 5341 5342
	for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
		ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
		if (ret)
			return ret;
	}

5343 5344 5345 5346 5347 5348 5349
	for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
		ret = i915_debugfs_create(minor->debugfs_root, minor,
					  i915_debugfs_files[i].name,
					  i915_debugfs_files[i].fops);
		if (ret)
			return ret;
	}
5350

5351 5352
	return drm_debugfs_create_files(i915_debugfs_list,
					I915_DEBUGFS_ENTRIES,
5353 5354 5355
					minor->debugfs_root, minor);
}

5356
void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5357
{
5358
	struct drm_minor *minor = dev_priv->drm.primary;
5359 5360
	int i;

5361 5362
	drm_debugfs_remove_files(i915_debugfs_list,
				 I915_DEBUGFS_ENTRIES, minor);
5363

5364
	drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5365
				 1, minor);
5366

D
Daniel Vetter 已提交
5367
	for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5368 5369 5370 5371 5372 5373
		struct drm_info_list *info_list =
			(struct drm_info_list *)&i915_pipe_crc_data[i];

		drm_debugfs_remove_files(info_list, 1, minor);
	}

5374 5375
	for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
		struct drm_info_list *info_list =
5376
			(struct drm_info_list *)i915_debugfs_files[i].fops;
5377 5378 5379

		drm_debugfs_remove_files(info_list, 1, minor);
	}
5380
}
5381 5382 5383 5384 5385 5386 5387 5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414

struct dpcd_block {
	/* DPCD dump start address. */
	unsigned int offset;
	/* DPCD dump end address, inclusive. If unset, .size will be used. */
	unsigned int end;
	/* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
	size_t size;
	/* Only valid for eDP. */
	bool edp;
};

static const struct dpcd_block i915_dpcd_debug[] = {
	{ .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
	{ .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
	{ .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
	{ .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
	{ .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
	{ .offset = DP_SET_POWER },
	{ .offset = DP_EDP_DPCD_REV },
	{ .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
	{ .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
	{ .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
};

static int i915_dpcd_show(struct seq_file *m, void *data)
{
	struct drm_connector *connector = m->private;
	struct intel_dp *intel_dp =
		enc_to_intel_dp(&intel_attached_encoder(connector)->base);
	uint8_t buf[16];
	ssize_t err;
	int i;

5415 5416 5417
	if (connector->status != connector_status_connected)
		return -ENODEV;

5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435 5436 5437
	for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
		const struct dpcd_block *b = &i915_dpcd_debug[i];
		size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);

		if (b->edp &&
		    connector->connector_type != DRM_MODE_CONNECTOR_eDP)
			continue;

		/* low tech for now */
		if (WARN_ON(size > sizeof(buf)))
			continue;

		err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
		if (err <= 0) {
			DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
				  size, b->offset, err);
			continue;
		}

		seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5438
	}
5439 5440 5441 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455

	return 0;
}

static int i915_dpcd_open(struct inode *inode, struct file *file)
{
	return single_open(file, i915_dpcd_show, inode->i_private);
}

static const struct file_operations i915_dpcd_fops = {
	.owner = THIS_MODULE,
	.open = i915_dpcd_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
};

5456 5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489
static int i915_panel_show(struct seq_file *m, void *data)
{
	struct drm_connector *connector = m->private;
	struct intel_dp *intel_dp =
		enc_to_intel_dp(&intel_attached_encoder(connector)->base);

	if (connector->status != connector_status_connected)
		return -ENODEV;

	seq_printf(m, "Panel power up delay: %d\n",
		   intel_dp->panel_power_up_delay);
	seq_printf(m, "Panel power down delay: %d\n",
		   intel_dp->panel_power_down_delay);
	seq_printf(m, "Backlight on delay: %d\n",
		   intel_dp->backlight_on_delay);
	seq_printf(m, "Backlight off delay: %d\n",
		   intel_dp->backlight_off_delay);

	return 0;
}

static int i915_panel_open(struct inode *inode, struct file *file)
{
	return single_open(file, i915_panel_show, inode->i_private);
}

static const struct file_operations i915_panel_fops = {
	.owner = THIS_MODULE,
	.open = i915_panel_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
};

5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508
/**
 * i915_debugfs_connector_add - add i915 specific connector debugfs files
 * @connector: pointer to a registered drm_connector
 *
 * Cleanup will be done by drm_connector_unregister() through a call to
 * drm_debugfs_connector_remove().
 *
 * Returns 0 on success, negative error codes on error.
 */
int i915_debugfs_connector_add(struct drm_connector *connector)
{
	struct dentry *root = connector->debugfs_entry;

	/* The connector must have been registered beforehands. */
	if (!root)
		return -ENODEV;

	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
	    connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5509 5510 5511 5512 5513 5514
		debugfs_create_file("i915_dpcd", S_IRUGO, root,
				    connector, &i915_dpcd_fops);

	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
		debugfs_create_file("i915_panel_timings", S_IRUGO, root,
				    connector, &i915_panel_fops);
5515 5516 5517

	return 0;
}