i915_debugfs.c 150.7 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/seq_file.h>
30
#include <linux/circ_buf.h>
31
#include <linux/ctype.h>
32
#include <linux/debugfs.h>
33
#include <linux/slab.h>
34
#include <linux/export.h>
35
#include <linux/list_sort.h>
36
#include <asm/msr-index.h>
37
#include <drm/drmP.h>
38
#include "intel_drv.h"
39
#include "intel_ringbuffer.h"
40
#include <drm/i915_drm.h>
41 42
#include "i915_drv.h"

C
Chris Wilson 已提交
43
enum {
44
	ACTIVE_LIST,
C
Chris Wilson 已提交
45
	INACTIVE_LIST,
46
	PINNED_LIST,
C
Chris Wilson 已提交
47
};
48

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
/* As the drm_debugfs_init() routines are called before dev->dev_private is
 * allocated we need to hook into the minor for release. */
static int
drm_add_fake_info_node(struct drm_minor *minor,
		       struct dentry *ent,
		       const void *key)
{
	struct drm_info_node *node;

	node = kmalloc(sizeof(*node), GFP_KERNEL);
	if (node == NULL) {
		debugfs_remove(ent);
		return -ENOMEM;
	}

	node->minor = minor;
	node->dent = ent;
	node->info_ent = (void *) key;

	mutex_lock(&minor->debugfs_lock);
	list_add(&node->list, &minor->debugfs_list);
	mutex_unlock(&minor->debugfs_lock);

	return 0;
}

75 76
static int i915_capabilities(struct seq_file *m, void *data)
{
77
	struct drm_info_node *node = m->private;
78 79 80 81
	struct drm_device *dev = node->minor->dev;
	const struct intel_device_info *info = INTEL_INFO(dev);

	seq_printf(m, "gen: %d\n", info->gen);
82
	seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 84 85 86 87
#define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
#define SEP_SEMICOLON ;
	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
#undef PRINT_FLAG
#undef SEP_SEMICOLON
88 89 90

	return 0;
}
91

92
static char get_active_flag(struct drm_i915_gem_object *obj)
93
{
94
	return obj->active ? '*' : ' ';
95 96
}

97
static char get_pin_flag(struct drm_i915_gem_object *obj)
98 99 100 101
{
	return obj->pin_display ? 'p' : ' ';
}

102
static char get_tiling_flag(struct drm_i915_gem_object *obj)
103
{
104 105
	switch (obj->tiling_mode) {
	default:
106 107 108
	case I915_TILING_NONE: return ' ';
	case I915_TILING_X: return 'X';
	case I915_TILING_Y: return 'Y';
109
	}
110 111
}

112
static char get_global_flag(struct drm_i915_gem_object *obj)
113 114 115 116
{
	return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
}

117
static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
B
Ben Widawsky 已提交
118
{
119
	return obj->mapping ? 'M' : ' ';
B
Ben Widawsky 已提交
120 121
}

122 123 124 125 126
static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
{
	u64 size = 0;
	struct i915_vma *vma;

127
	list_for_each_entry(vma, &obj->vma_list, obj_link) {
128
		if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
129 130 131 132 133 134
			size += vma->node.size;
	}

	return size;
}

135 136 137
static void
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
138
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
139
	struct intel_engine_cs *engine;
B
Ben Widawsky 已提交
140
	struct i915_vma *vma;
B
Ben Widawsky 已提交
141
	int pin_count = 0;
142
	enum intel_engine_id id;
B
Ben Widawsky 已提交
143

144 145
	lockdep_assert_held(&obj->base.dev->struct_mutex);

146
	seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
147
		   &obj->base,
148
		   get_active_flag(obj),
149 150
		   get_pin_flag(obj),
		   get_tiling_flag(obj),
B
Ben Widawsky 已提交
151
		   get_global_flag(obj),
152
		   get_pin_mapped_flag(obj),
153
		   obj->base.size / 1024,
154
		   obj->base.read_domains,
155
		   obj->base.write_domain);
156
	for_each_engine_id(engine, dev_priv, id)
157
		seq_printf(m, "%x ",
158
				i915_gem_request_get_seqno(obj->last_read_req[id]));
159
	seq_printf(m, "] %x %x%s%s%s",
160 161
		   i915_gem_request_get_seqno(obj->last_write_req),
		   i915_gem_request_get_seqno(obj->last_fenced_req),
162
		   i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
163 164 165 166
		   obj->dirty ? " dirty" : "",
		   obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
	if (obj->base.name)
		seq_printf(m, " (name: %d)", obj->base.name);
167
	list_for_each_entry(vma, &obj->vma_list, obj_link) {
B
Ben Widawsky 已提交
168 169
		if (vma->pin_count > 0)
			pin_count++;
D
Dan Carpenter 已提交
170 171
	}
	seq_printf(m, " (pinned x %d)", pin_count);
172 173
	if (obj->pin_display)
		seq_printf(m, " (display)");
174 175
	if (obj->fence_reg != I915_FENCE_REG_NONE)
		seq_printf(m, " (fence: %d)", obj->fence_reg);
176
	list_for_each_entry(vma, &obj->vma_list, obj_link) {
177
		seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
178
			   vma->is_ggtt ? "g" : "pp",
179
			   vma->node.start, vma->node.size);
180 181 182
		if (vma->is_ggtt)
			seq_printf(m, ", type: %u", vma->ggtt_view.type);
		seq_puts(m, ")");
B
Ben Widawsky 已提交
183
	}
184
	if (obj->stolen)
185
		seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
186
	if (obj->pin_display || obj->fault_mappable) {
187
		char s[3], *t = s;
188
		if (obj->pin_display)
189 190 191 192 193 194
			*t++ = 'p';
		if (obj->fault_mappable)
			*t++ = 'f';
		*t = '\0';
		seq_printf(m, " (%s mappable)", s);
	}
195
	if (obj->last_write_req != NULL)
196
		seq_printf(m, " (%s)",
197
			   i915_gem_request_get_engine(obj->last_write_req)->name);
198 199
	if (obj->frontbuffer_bits)
		seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
200 201
}

202
static int i915_gem_object_list_info(struct seq_file *m, void *data)
203
{
204
	struct drm_info_node *node = m->private;
205 206
	uintptr_t list = (uintptr_t) node->info_ent->data;
	struct list_head *head;
207
	struct drm_device *dev = node->minor->dev;
208 209
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
B
Ben Widawsky 已提交
210
	struct i915_vma *vma;
211
	u64 total_obj_size, total_gtt_size;
212
	int count, ret;
213 214 215 216

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
217

B
Ben Widawsky 已提交
218
	/* FIXME: the user of this interface might want more than just GGTT */
219 220
	switch (list) {
	case ACTIVE_LIST:
221
		seq_puts(m, "Active:\n");
222
		head = &ggtt->base.active_list;
223 224
		break;
	case INACTIVE_LIST:
225
		seq_puts(m, "Inactive:\n");
226
		head = &ggtt->base.inactive_list;
227 228
		break;
	default:
229 230
		mutex_unlock(&dev->struct_mutex);
		return -EINVAL;
231 232
	}

233
	total_obj_size = total_gtt_size = count = 0;
234
	list_for_each_entry(vma, head, vm_link) {
B
Ben Widawsky 已提交
235 236 237 238 239
		seq_printf(m, "   ");
		describe_obj(m, vma->obj);
		seq_printf(m, "\n");
		total_obj_size += vma->obj->base.size;
		total_gtt_size += vma->node.size;
240
		count++;
241
	}
242
	mutex_unlock(&dev->struct_mutex);
243

244
	seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
245
		   count, total_obj_size, total_gtt_size);
246 247 248
	return 0;
}

249 250 251 252
static int obj_rank_by_stolen(void *priv,
			      struct list_head *A, struct list_head *B)
{
	struct drm_i915_gem_object *a =
253
		container_of(A, struct drm_i915_gem_object, obj_exec_link);
254
	struct drm_i915_gem_object *b =
255
		container_of(B, struct drm_i915_gem_object, obj_exec_link);
256

R
Rasmus Villemoes 已提交
257 258 259 260 261
	if (a->stolen->start < b->stolen->start)
		return -1;
	if (a->stolen->start > b->stolen->start)
		return 1;
	return 0;
262 263 264 265
}

static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
{
266
	struct drm_info_node *node = m->private;
267 268 269
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
270
	u64 total_obj_size, total_gtt_size;
271 272 273 274 275 276 277 278 279 280 281 282
	LIST_HEAD(stolen);
	int count, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	total_obj_size = total_gtt_size = count = 0;
	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
		if (obj->stolen == NULL)
			continue;

283
		list_add(&obj->obj_exec_link, &stolen);
284 285

		total_obj_size += obj->base.size;
286
		total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
287 288 289 290 291 292
		count++;
	}
	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
		if (obj->stolen == NULL)
			continue;

293
		list_add(&obj->obj_exec_link, &stolen);
294 295 296 297 298 299 300

		total_obj_size += obj->base.size;
		count++;
	}
	list_sort(NULL, &stolen, obj_rank_by_stolen);
	seq_puts(m, "Stolen:\n");
	while (!list_empty(&stolen)) {
301
		obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
302 303 304
		seq_puts(m, "   ");
		describe_obj(m, obj);
		seq_putc(m, '\n');
305
		list_del_init(&obj->obj_exec_link);
306 307 308
	}
	mutex_unlock(&dev->struct_mutex);

309
	seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
310 311 312 313
		   count, total_obj_size, total_gtt_size);
	return 0;
}

314 315
#define count_objects(list, member) do { \
	list_for_each_entry(obj, list, member) { \
316
		size += i915_gem_obj_total_ggtt_size(obj); \
317 318
		++count; \
		if (obj->map_and_fenceable) { \
319
			mappable_size += i915_gem_obj_ggtt_size(obj); \
320 321 322
			++mappable_count; \
		} \
	} \
323
} while (0)
324

325
struct file_stats {
326
	struct drm_i915_file_private *file_priv;
327 328 329 330
	unsigned long count;
	u64 total, unbound;
	u64 global, shared;
	u64 active, inactive;
331 332 333 334 335 336
};

static int per_file_stats(int id, void *ptr, void *data)
{
	struct drm_i915_gem_object *obj = ptr;
	struct file_stats *stats = data;
337
	struct i915_vma *vma;
338 339 340 341

	stats->count++;
	stats->total += obj->base.size;

342 343 344
	if (obj->base.name || obj->base.dma_buf)
		stats->shared += obj->base.size;

345
	if (USES_FULL_PPGTT(obj->base.dev)) {
346
		list_for_each_entry(vma, &obj->vma_list, obj_link) {
347 348 349 350 351
			struct i915_hw_ppgtt *ppgtt;

			if (!drm_mm_node_allocated(&vma->node))
				continue;

352
			if (vma->is_ggtt) {
353 354 355 356 357
				stats->global += obj->base.size;
				continue;
			}

			ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
358
			if (ppgtt->file_priv != stats->file_priv)
359 360
				continue;

361
			if (obj->active) /* XXX per-vma statistic */
362 363 364 365 366 367
				stats->active += obj->base.size;
			else
				stats->inactive += obj->base.size;

			return 0;
		}
368
	} else {
369 370
		if (i915_gem_obj_ggtt_bound(obj)) {
			stats->global += obj->base.size;
371
			if (obj->active)
372 373 374 375 376
				stats->active += obj->base.size;
			else
				stats->inactive += obj->base.size;
			return 0;
		}
377 378
	}

379 380 381
	if (!list_empty(&obj->global_list))
		stats->unbound += obj->base.size;

382 383 384
	return 0;
}

385 386
#define print_file_stats(m, name, stats) do { \
	if (stats.count) \
387
		seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
388 389 390 391 392 393 394 395 396
			   name, \
			   stats.count, \
			   stats.total, \
			   stats.active, \
			   stats.inactive, \
			   stats.global, \
			   stats.shared, \
			   stats.unbound); \
} while (0)
397 398 399 400 401 402

static void print_batch_pool_stats(struct seq_file *m,
				   struct drm_i915_private *dev_priv)
{
	struct drm_i915_gem_object *obj;
	struct file_stats stats;
403
	struct intel_engine_cs *engine;
404
	int j;
405 406 407

	memset(&stats, 0, sizeof(stats));

408
	for_each_engine(engine, dev_priv) {
409
		for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
410
			list_for_each_entry(obj,
411
					    &engine->batch_pool.cache_list[j],
412 413 414
					    batch_pool_link)
				per_file_stats(0, obj, &stats);
		}
415
	}
416

417
	print_file_stats(m, "[k]batch pool", stats);
418 419
}

420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455
static int per_file_ctx_stats(int id, void *ptr, void *data)
{
	struct i915_gem_context *ctx = ptr;
	int n;

	for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
		if (ctx->engine[n].state)
			per_file_stats(0, ctx->engine[n].state, data);
		if (ctx->engine[n].ringbuf)
			per_file_stats(0, ctx->engine[n].ringbuf->obj, data);
	}

	return 0;
}

static void print_context_stats(struct seq_file *m,
				struct drm_i915_private *dev_priv)
{
	struct file_stats stats;
	struct drm_file *file;

	memset(&stats, 0, sizeof(stats));

	mutex_lock(&dev_priv->dev->struct_mutex);
	if (dev_priv->kernel_context)
		per_file_ctx_stats(0, dev_priv->kernel_context, &stats);

	list_for_each_entry(file, &dev_priv->dev->filelist, lhead) {
		struct drm_i915_file_private *fpriv = file->driver_priv;
		idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
	}
	mutex_unlock(&dev_priv->dev->struct_mutex);

	print_file_stats(m, "[k]contexts", stats);
}

B
Ben Widawsky 已提交
456 457
#define count_vmas(list, member) do { \
	list_for_each_entry(vma, list, member) { \
458
		size += i915_gem_obj_total_ggtt_size(vma->obj); \
B
Ben Widawsky 已提交
459 460 461 462 463 464 465 466 467
		++count; \
		if (vma->obj->map_and_fenceable) { \
			mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
			++mappable_count; \
		} \
	} \
} while (0)

static int i915_gem_object_info(struct seq_file *m, void* data)
468
{
469
	struct drm_info_node *node = m->private;
470
	struct drm_device *dev = node->minor->dev;
471 472
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
473
	u32 count, mappable_count, purgeable_count;
474
	u64 size, mappable_size, purgeable_size;
475 476
	unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
	u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
477
	struct drm_i915_gem_object *obj;
478
	struct drm_file *file;
B
Ben Widawsky 已提交
479
	struct i915_vma *vma;
480 481 482 483 484 485
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

486 487 488 489 490
	seq_printf(m, "%u objects, %zu bytes\n",
		   dev_priv->mm.object_count,
		   dev_priv->mm.object_memory);

	size = count = mappable_size = mappable_count = 0;
491
	count_objects(&dev_priv->mm.bound_list, global_list);
492
	seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
493 494 495
		   count, mappable_count, size, mappable_size);

	size = count = mappable_size = mappable_count = 0;
496
	count_vmas(&ggtt->base.active_list, vm_link);
497
	seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
498 499 500
		   count, mappable_count, size, mappable_size);

	size = count = mappable_size = mappable_count = 0;
501
	count_vmas(&ggtt->base.inactive_list, vm_link);
502
	seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
503 504
		   count, mappable_count, size, mappable_size);

505
	size = count = purgeable_size = purgeable_count = 0;
506
	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
C
Chris Wilson 已提交
507
		size += obj->base.size, ++count;
508 509
		if (obj->madv == I915_MADV_DONTNEED)
			purgeable_size += obj->base.size, ++purgeable_count;
510 511 512 513 514 515 516 517
		if (obj->mapping) {
			pin_mapped_count++;
			pin_mapped_size += obj->base.size;
			if (obj->pages_pin_count == 0) {
				pin_mapped_purgeable_count++;
				pin_mapped_purgeable_size += obj->base.size;
			}
		}
518
	}
519
	seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
C
Chris Wilson 已提交
520

521
	size = count = mappable_size = mappable_count = 0;
522
	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
523
		if (obj->fault_mappable) {
524
			size += i915_gem_obj_ggtt_size(obj);
525 526
			++count;
		}
527
		if (obj->pin_display) {
528
			mappable_size += i915_gem_obj_ggtt_size(obj);
529 530
			++mappable_count;
		}
531 532 533 534
		if (obj->madv == I915_MADV_DONTNEED) {
			purgeable_size += obj->base.size;
			++purgeable_count;
		}
535 536 537 538 539 540 541 542
		if (obj->mapping) {
			pin_mapped_count++;
			pin_mapped_size += obj->base.size;
			if (obj->pages_pin_count == 0) {
				pin_mapped_purgeable_count++;
				pin_mapped_purgeable_size += obj->base.size;
			}
		}
543
	}
544
	seq_printf(m, "%u purgeable objects, %llu bytes\n",
545
		   purgeable_count, purgeable_size);
546
	seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
547
		   mappable_count, mappable_size);
548
	seq_printf(m, "%u fault mappable objects, %llu bytes\n",
549
		   count, size);
550 551 552 553
	seq_printf(m,
		   "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
		   pin_mapped_count, pin_mapped_purgeable_count,
		   pin_mapped_size, pin_mapped_purgeable_size);
554

555
	seq_printf(m, "%llu [%llu] gtt total\n",
556
		   ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
557

558 559
	seq_putc(m, '\n');
	print_batch_pool_stats(m, dev_priv);
560 561 562
	mutex_unlock(&dev->struct_mutex);

	mutex_lock(&dev->filelist_mutex);
563
	print_context_stats(m, dev_priv);
564 565
	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct file_stats stats;
566
		struct task_struct *task;
567 568

		memset(&stats, 0, sizeof(stats));
569
		stats.file_priv = file->driver_priv;
570
		spin_lock(&file->table_lock);
571
		idr_for_each(&file->object_idr, per_file_stats, &stats);
572
		spin_unlock(&file->table_lock);
573 574 575 576 577 578 579 580
		/*
		 * Although we have a valid reference on file->pid, that does
		 * not guarantee that the task_struct who called get_pid() is
		 * still alive (e.g. get_pid(current) => fork() => exit()).
		 * Therefore, we need to protect this ->comm access using RCU.
		 */
		rcu_read_lock();
		task = pid_task(file->pid, PIDTYPE_PID);
581
		print_file_stats(m, task ? task->comm : "<unknown>", stats);
582
		rcu_read_unlock();
583
	}
584
	mutex_unlock(&dev->filelist_mutex);
585 586 587 588

	return 0;
}

589
static int i915_gem_gtt_info(struct seq_file *m, void *data)
590
{
591
	struct drm_info_node *node = m->private;
592
	struct drm_device *dev = node->minor->dev;
593
	uintptr_t list = (uintptr_t) node->info_ent->data;
594 595
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
596
	u64 total_obj_size, total_gtt_size;
597 598 599 600 601 602 603
	int count, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	total_obj_size = total_gtt_size = count = 0;
604
	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
B
Ben Widawsky 已提交
605
		if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
606 607
			continue;

608
		seq_puts(m, "   ");
609
		describe_obj(m, obj);
610
		seq_putc(m, '\n');
611
		total_obj_size += obj->base.size;
612
		total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
613 614 615 616 617
		count++;
	}

	mutex_unlock(&dev->struct_mutex);

618
	seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
619 620 621 622 623
		   count, total_obj_size, total_gtt_size);

	return 0;
}

624 625
static int i915_gem_pageflip_info(struct seq_file *m, void *data)
{
626
	struct drm_info_node *node = m->private;
627
	struct drm_device *dev = node->minor->dev;
628
	struct drm_i915_private *dev_priv = dev->dev_private;
629
	struct intel_crtc *crtc;
630 631 632 633 634
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
635

636
	for_each_intel_crtc(dev, crtc) {
637 638
		const char pipe = pipe_name(crtc->pipe);
		const char plane = plane_name(crtc->plane);
639
		struct intel_flip_work *work;
640

641
		spin_lock_irq(&dev->event_lock);
642 643
		work = crtc->flip_work;
		if (work == NULL) {
644
			seq_printf(m, "No flip due on pipe %c (plane %c)\n",
645 646
				   pipe, plane);
		} else {
647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683
			u32 pending;
			u32 addr;

			pending = atomic_read(&work->pending);
			if (pending) {
				seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
					   pipe, plane);
			} else {
				seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
					   pipe, plane);
			}
			if (work->flip_queued_req) {
				struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);

				seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
					   engine->name,
					   i915_gem_request_get_seqno(work->flip_queued_req),
					   dev_priv->next_seqno,
					   engine->get_seqno(engine),
					   i915_gem_request_completed(work->flip_queued_req, true));
			} else
				seq_printf(m, "Flip not associated with any ring\n");
			seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
				   work->flip_queued_vblank,
				   work->flip_ready_vblank,
				   intel_crtc_get_vblank_counter(crtc));
			seq_printf(m, "%d prepares\n", atomic_read(&work->pending));

			if (INTEL_INFO(dev)->gen >= 4)
				addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
			else
				addr = I915_READ(DSPADDR(crtc->plane));
			seq_printf(m, "Current scanout address 0x%08x\n", addr);

			if (work->pending_flip_obj) {
				seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
				seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
684 685
			}
		}
686
		spin_unlock_irq(&dev->event_lock);
687 688
	}

689 690
	mutex_unlock(&dev->struct_mutex);

691 692 693
	return 0;
}

694 695 696 697 698 699
static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
700
	struct intel_engine_cs *engine;
701
	int total = 0;
702
	int ret, j;
703 704 705 706 707

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

708
	for_each_engine(engine, dev_priv) {
709
		for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
710 711 712 713
			int count;

			count = 0;
			list_for_each_entry(obj,
714
					    &engine->batch_pool.cache_list[j],
715 716 717
					    batch_pool_link)
				count++;
			seq_printf(m, "%s cache[%d]: %d objects\n",
718
				   engine->name, j, count);
719 720

			list_for_each_entry(obj,
721
					    &engine->batch_pool.cache_list[j],
722 723 724 725 726 727 728
					    batch_pool_link) {
				seq_puts(m, "   ");
				describe_obj(m, obj);
				seq_putc(m, '\n');
			}

			total += count;
729
		}
730 731
	}

732
	seq_printf(m, "total: %d\n", total);
733 734 735 736 737 738

	mutex_unlock(&dev->struct_mutex);

	return 0;
}

739 740
static int i915_gem_request_info(struct seq_file *m, void *data)
{
741
	struct drm_info_node *node = m->private;
742
	struct drm_device *dev = node->minor->dev;
743
	struct drm_i915_private *dev_priv = dev->dev_private;
744
	struct intel_engine_cs *engine;
D
Daniel Vetter 已提交
745
	struct drm_i915_gem_request *req;
746
	int ret, any;
747 748 749 750

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
751

752
	any = 0;
753
	for_each_engine(engine, dev_priv) {
754 755 756
		int count;

		count = 0;
757
		list_for_each_entry(req, &engine->request_list, list)
758 759
			count++;
		if (count == 0)
760 761
			continue;

762 763
		seq_printf(m, "%s requests: %d\n", engine->name, count);
		list_for_each_entry(req, &engine->request_list, list) {
764 765 766 767
			struct task_struct *task;

			rcu_read_lock();
			task = NULL;
D
Daniel Vetter 已提交
768 769
			if (req->pid)
				task = pid_task(req->pid, PIDTYPE_PID);
770
			seq_printf(m, "    %x @ %d: %s [%d]\n",
D
Daniel Vetter 已提交
771 772
				   req->seqno,
				   (int) (jiffies - req->emitted_jiffies),
773 774 775
				   task ? task->comm : "<unknown>",
				   task ? task->pid : -1);
			rcu_read_unlock();
776
		}
777 778

		any++;
779
	}
780 781
	mutex_unlock(&dev->struct_mutex);

782
	if (any == 0)
783
		seq_puts(m, "No requests\n");
784

785 786 787
	return 0;
}

788
static void i915_ring_seqno_info(struct seq_file *m,
789
				 struct intel_engine_cs *engine)
790
{
791 792 793 794
	seq_printf(m, "Current sequence (%s): %x\n",
		   engine->name, engine->get_seqno(engine));
	seq_printf(m, "Current user interrupts (%s): %x\n",
		   engine->name, READ_ONCE(engine->user_interrupts));
795 796
}

797 798
static int i915_gem_seqno_info(struct seq_file *m, void *data)
{
799
	struct drm_info_node *node = m->private;
800
	struct drm_device *dev = node->minor->dev;
801
	struct drm_i915_private *dev_priv = dev->dev_private;
802
	struct intel_engine_cs *engine;
803
	int ret;
804 805 806 807

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
808
	intel_runtime_pm_get(dev_priv);
809

810
	for_each_engine(engine, dev_priv)
811
		i915_ring_seqno_info(m, engine);
812

813
	intel_runtime_pm_put(dev_priv);
814 815
	mutex_unlock(&dev->struct_mutex);

816 817 818 819 820 821
	return 0;
}


static int i915_interrupt_info(struct seq_file *m, void *data)
{
822
	struct drm_info_node *node = m->private;
823
	struct drm_device *dev = node->minor->dev;
824
	struct drm_i915_private *dev_priv = dev->dev_private;
825
	struct intel_engine_cs *engine;
826
	int ret, i, pipe;
827 828 829 830

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
831
	intel_runtime_pm_get(dev_priv);
832

833 834 835 836 837 838 839 840 841 842 843 844
	if (IS_CHERRYVIEW(dev)) {
		seq_printf(m, "Master Interrupt Control:\t%08x\n",
			   I915_READ(GEN8_MASTER_IRQ));

		seq_printf(m, "Display IER:\t%08x\n",
			   I915_READ(VLV_IER));
		seq_printf(m, "Display IIR:\t%08x\n",
			   I915_READ(VLV_IIR));
		seq_printf(m, "Display IIR_RW:\t%08x\n",
			   I915_READ(VLV_IIR_RW));
		seq_printf(m, "Display IMR:\t%08x\n",
			   I915_READ(VLV_IMR));
845
		for_each_pipe(dev_priv, pipe)
846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872
			seq_printf(m, "Pipe %c stat:\t%08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));

		seq_printf(m, "Port hotplug:\t%08x\n",
			   I915_READ(PORT_HOTPLUG_EN));
		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
			   I915_READ(VLV_DPFLIPSTAT));
		seq_printf(m, "DPINVGTT:\t%08x\n",
			   I915_READ(DPINVGTT));

		for (i = 0; i < 4; i++) {
			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IMR(i)));
			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IIR(i)));
			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IER(i)));
		}

		seq_printf(m, "PCU interrupt mask:\t%08x\n",
			   I915_READ(GEN8_PCU_IMR));
		seq_printf(m, "PCU interrupt identity:\t%08x\n",
			   I915_READ(GEN8_PCU_IIR));
		seq_printf(m, "PCU interrupt enable:\t%08x\n",
			   I915_READ(GEN8_PCU_IER));
	} else if (INTEL_INFO(dev)->gen >= 8) {
873 874 875 876 877 878 879 880 881 882 883 884
		seq_printf(m, "Master Interrupt Control:\t%08x\n",
			   I915_READ(GEN8_MASTER_IRQ));

		for (i = 0; i < 4; i++) {
			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IMR(i)));
			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IIR(i)));
			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IER(i)));
		}

885
		for_each_pipe(dev_priv, pipe) {
886 887 888 889 890
			enum intel_display_power_domain power_domain;

			power_domain = POWER_DOMAIN_PIPE(pipe);
			if (!intel_display_power_get_if_enabled(dev_priv,
								power_domain)) {
891 892 893 894
				seq_printf(m, "Pipe %c power disabled\n",
					   pipe_name(pipe));
				continue;
			}
895
			seq_printf(m, "Pipe %c IMR:\t%08x\n",
896 897
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
898
			seq_printf(m, "Pipe %c IIR:\t%08x\n",
899 900
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
901
			seq_printf(m, "Pipe %c IER:\t%08x\n",
902 903
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IER(pipe)));
904 905

			intel_display_power_put(dev_priv, power_domain);
906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928
		}

		seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IMR));
		seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IIR));
		seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IER));

		seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IMR));
		seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IIR));
		seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IER));

		seq_printf(m, "PCU interrupt mask:\t%08x\n",
			   I915_READ(GEN8_PCU_IMR));
		seq_printf(m, "PCU interrupt identity:\t%08x\n",
			   I915_READ(GEN8_PCU_IIR));
		seq_printf(m, "PCU interrupt enable:\t%08x\n",
			   I915_READ(GEN8_PCU_IER));
	} else if (IS_VALLEYVIEW(dev)) {
J
Jesse Barnes 已提交
929 930 931 932 933 934 935 936
		seq_printf(m, "Display IER:\t%08x\n",
			   I915_READ(VLV_IER));
		seq_printf(m, "Display IIR:\t%08x\n",
			   I915_READ(VLV_IIR));
		seq_printf(m, "Display IIR_RW:\t%08x\n",
			   I915_READ(VLV_IIR_RW));
		seq_printf(m, "Display IMR:\t%08x\n",
			   I915_READ(VLV_IMR));
937
		for_each_pipe(dev_priv, pipe)
J
Jesse Barnes 已提交
938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966
			seq_printf(m, "Pipe %c stat:\t%08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));

		seq_printf(m, "Master IER:\t%08x\n",
			   I915_READ(VLV_MASTER_IER));

		seq_printf(m, "Render IER:\t%08x\n",
			   I915_READ(GTIER));
		seq_printf(m, "Render IIR:\t%08x\n",
			   I915_READ(GTIIR));
		seq_printf(m, "Render IMR:\t%08x\n",
			   I915_READ(GTIMR));

		seq_printf(m, "PM IER:\t\t%08x\n",
			   I915_READ(GEN6_PMIER));
		seq_printf(m, "PM IIR:\t\t%08x\n",
			   I915_READ(GEN6_PMIIR));
		seq_printf(m, "PM IMR:\t\t%08x\n",
			   I915_READ(GEN6_PMIMR));

		seq_printf(m, "Port hotplug:\t%08x\n",
			   I915_READ(PORT_HOTPLUG_EN));
		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
			   I915_READ(VLV_DPFLIPSTAT));
		seq_printf(m, "DPINVGTT:\t%08x\n",
			   I915_READ(DPINVGTT));

	} else if (!HAS_PCH_SPLIT(dev)) {
967 968 969 970 971 972
		seq_printf(m, "Interrupt enable:    %08x\n",
			   I915_READ(IER));
		seq_printf(m, "Interrupt identity:  %08x\n",
			   I915_READ(IIR));
		seq_printf(m, "Interrupt mask:      %08x\n",
			   I915_READ(IMR));
973
		for_each_pipe(dev_priv, pipe)
974 975 976
			seq_printf(m, "Pipe %c stat:         %08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));
977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996
	} else {
		seq_printf(m, "North Display Interrupt enable:		%08x\n",
			   I915_READ(DEIER));
		seq_printf(m, "North Display Interrupt identity:	%08x\n",
			   I915_READ(DEIIR));
		seq_printf(m, "North Display Interrupt mask:		%08x\n",
			   I915_READ(DEIMR));
		seq_printf(m, "South Display Interrupt enable:		%08x\n",
			   I915_READ(SDEIER));
		seq_printf(m, "South Display Interrupt identity:	%08x\n",
			   I915_READ(SDEIIR));
		seq_printf(m, "South Display Interrupt mask:		%08x\n",
			   I915_READ(SDEIMR));
		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
			   I915_READ(GTIER));
		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
			   I915_READ(GTIIR));
		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
			   I915_READ(GTIMR));
	}
997
	for_each_engine(engine, dev_priv) {
998
		if (INTEL_INFO(dev)->gen >= 6) {
999 1000
			seq_printf(m,
				   "Graphics Interrupt mask (%s):	%08x\n",
1001
				   engine->name, I915_READ_IMR(engine));
1002
		}
1003
		i915_ring_seqno_info(m, engine);
1004
	}
1005
	intel_runtime_pm_put(dev_priv);
1006 1007
	mutex_unlock(&dev->struct_mutex);

1008 1009 1010
	return 0;
}

1011 1012
static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
{
1013
	struct drm_info_node *node = m->private;
1014
	struct drm_device *dev = node->minor->dev;
1015
	struct drm_i915_private *dev_priv = dev->dev_private;
1016 1017 1018 1019 1020
	int i, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1021 1022 1023

	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
	for (i = 0; i < dev_priv->num_fence_regs; i++) {
1024
		struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1025

C
Chris Wilson 已提交
1026 1027
		seq_printf(m, "Fence %d, pin count = %d, object = ",
			   i, dev_priv->fence_regs[i].pin_count);
1028
		if (obj == NULL)
1029
			seq_puts(m, "unused");
1030
		else
1031
			describe_obj(m, obj);
1032
		seq_putc(m, '\n');
1033 1034
	}

1035
	mutex_unlock(&dev->struct_mutex);
1036 1037 1038
	return 0;
}

1039 1040
static int i915_hws_info(struct seq_file *m, void *data)
{
1041
	struct drm_info_node *node = m->private;
1042
	struct drm_device *dev = node->minor->dev;
1043
	struct drm_i915_private *dev_priv = dev->dev_private;
1044
	struct intel_engine_cs *engine;
D
Daniel Vetter 已提交
1045
	const u32 *hws;
1046 1047
	int i;

1048
	engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1049
	hws = engine->status_page.page_addr;
1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060
	if (hws == NULL)
		return 0;

	for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
		seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
			   i * 4,
			   hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
	}
	return 0;
}

1061 1062 1063 1064 1065 1066
static ssize_t
i915_error_state_write(struct file *filp,
		       const char __user *ubuf,
		       size_t cnt,
		       loff_t *ppos)
{
1067
	struct i915_error_state_file_priv *error_priv = filp->private_data;
1068
	struct drm_device *dev = error_priv->dev;
1069
	int ret;
1070 1071 1072

	DRM_DEBUG_DRIVER("Resetting error state\n");

1073 1074 1075 1076
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093
	i915_destroy_error_state(dev);
	mutex_unlock(&dev->struct_mutex);

	return cnt;
}

static int i915_error_state_open(struct inode *inode, struct file *file)
{
	struct drm_device *dev = inode->i_private;
	struct i915_error_state_file_priv *error_priv;

	error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
	if (!error_priv)
		return -ENOMEM;

	error_priv->dev = dev;

1094
	i915_error_state_get(dev, error_priv);
1095

1096 1097 1098
	file->private_data = error_priv;

	return 0;
1099 1100 1101 1102
}

static int i915_error_state_release(struct inode *inode, struct file *file)
{
1103
	struct i915_error_state_file_priv *error_priv = file->private_data;
1104

1105
	i915_error_state_put(error_priv);
1106 1107
	kfree(error_priv);

1108 1109 1110
	return 0;
}

1111 1112 1113 1114 1115 1116 1117 1118 1119
static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
				     size_t count, loff_t *pos)
{
	struct i915_error_state_file_priv *error_priv = file->private_data;
	struct drm_i915_error_state_buf error_str;
	loff_t tmp_pos = 0;
	ssize_t ret_count = 0;
	int ret;

1120
	ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1121 1122
	if (ret)
		return ret;
1123

1124
	ret = i915_error_state_to_str(&error_str, error_priv);
1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136
	if (ret)
		goto out;

	ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
					    error_str.buf,
					    error_str.bytes);

	if (ret_count < 0)
		ret = ret_count;
	else
		*pos = error_str.start + ret_count;
out:
1137
	i915_error_state_buf_release(&error_str);
1138
	return ret ?: ret_count;
1139 1140 1141 1142 1143
}

static const struct file_operations i915_error_state_fops = {
	.owner = THIS_MODULE,
	.open = i915_error_state_open,
1144
	.read = i915_error_state_read,
1145 1146 1147 1148 1149
	.write = i915_error_state_write,
	.llseek = default_llseek,
	.release = i915_error_state_release,
};

1150 1151
static int
i915_next_seqno_get(void *data, u64 *val)
1152
{
1153
	struct drm_device *dev = data;
1154
	struct drm_i915_private *dev_priv = dev->dev_private;
1155 1156 1157 1158 1159 1160
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

1161
	*val = dev_priv->next_seqno;
1162 1163
	mutex_unlock(&dev->struct_mutex);

1164
	return 0;
1165 1166
}

1167 1168 1169 1170
static int
i915_next_seqno_set(void *data, u64 val)
{
	struct drm_device *dev = data;
1171 1172 1173 1174 1175 1176
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

1177
	ret = i915_gem_set_seqno(dev, val);
1178 1179
	mutex_unlock(&dev->struct_mutex);

1180
	return ret;
1181 1182
}

1183 1184
DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
			i915_next_seqno_get, i915_next_seqno_set,
1185
			"0x%llx\n");
1186

1187
static int i915_frequency_info(struct seq_file *m, void *unused)
1188
{
1189
	struct drm_info_node *node = m->private;
1190
	struct drm_device *dev = node->minor->dev;
1191
	struct drm_i915_private *dev_priv = dev->dev_private;
1192 1193 1194
	int ret = 0;

	intel_runtime_pm_get(dev_priv);
1195

1196 1197
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

1198 1199 1200 1201 1202 1203 1204 1205 1206 1207
	if (IS_GEN5(dev)) {
		u16 rgvswctl = I915_READ16(MEMSWCTL);
		u16 rgvstat = I915_READ16(MEMSTAT_ILK);

		seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
		seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
		seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
			   MEMSTAT_VID_SHIFT);
		seq_printf(m, "Current P-state: %d\n",
			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235
	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
		u32 freq_sts;

		mutex_lock(&dev_priv->rps.hw_lock);
		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);

		seq_printf(m, "actual GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));

		seq_printf(m, "current GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));

		seq_printf(m, "max GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));

		seq_printf(m, "min GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));

		seq_printf(m, "idle GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));

		seq_printf(m,
			   "efficient (RPe) frequency: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
		mutex_unlock(&dev_priv->rps.hw_lock);
	} else if (INTEL_INFO(dev)->gen >= 6) {
1236 1237 1238
		u32 rp_state_limits;
		u32 gt_perf_status;
		u32 rp_state_cap;
1239
		u32 rpmodectl, rpinclimit, rpdeclimit;
1240
		u32 rpstat, cagf, reqf;
1241 1242
		u32 rpupei, rpcurup, rpprevup;
		u32 rpdownei, rpcurdown, rpprevdown;
1243
		u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1244 1245
		int max_freq;

1246 1247 1248 1249 1250 1251 1252 1253 1254
		rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
		if (IS_BROXTON(dev)) {
			rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
			gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
		} else {
			rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
			gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
		}

1255
		/* RPSTAT1 is in the GT power well */
1256 1257
		ret = mutex_lock_interruptible(&dev->struct_mutex);
		if (ret)
1258
			goto out;
1259

1260
		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1261

1262
		reqf = I915_READ(GEN6_RPNSWREQ);
1263 1264 1265 1266 1267 1268 1269 1270 1271
		if (IS_GEN9(dev))
			reqf >>= 23;
		else {
			reqf &= ~GEN6_TURBO_DISABLE;
			if (IS_HASWELL(dev) || IS_BROADWELL(dev))
				reqf >>= 24;
			else
				reqf >>= 25;
		}
1272
		reqf = intel_gpu_freq(dev_priv, reqf);
1273

1274 1275 1276 1277
		rpmodectl = I915_READ(GEN6_RP_CONTROL);
		rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
		rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);

1278
		rpstat = I915_READ(GEN6_RPSTAT1);
1279 1280 1281 1282 1283 1284
		rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
		rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
		rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1285 1286 1287
		if (IS_GEN9(dev))
			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
B
Ben Widawsky 已提交
1288 1289 1290
			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
		else
			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1291
		cagf = intel_gpu_freq(dev_priv, cagf);
1292

1293
		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1294 1295
		mutex_unlock(&dev->struct_mutex);

1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308
		if (IS_GEN6(dev) || IS_GEN7(dev)) {
			pm_ier = I915_READ(GEN6_PMIER);
			pm_imr = I915_READ(GEN6_PMIMR);
			pm_isr = I915_READ(GEN6_PMISR);
			pm_iir = I915_READ(GEN6_PMIIR);
			pm_mask = I915_READ(GEN6_PMINTRMSK);
		} else {
			pm_ier = I915_READ(GEN8_GT_IER(2));
			pm_imr = I915_READ(GEN8_GT_IMR(2));
			pm_isr = I915_READ(GEN8_GT_ISR(2));
			pm_iir = I915_READ(GEN8_GT_IIR(2));
			pm_mask = I915_READ(GEN6_PMINTRMSK);
		}
1309
		seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1310
			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1311 1312
		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
		seq_printf(m, "Render p-state ratio: %d\n",
1313
			   (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1314 1315 1316 1317
		seq_printf(m, "Render p-state VID: %d\n",
			   gt_perf_status & 0xff);
		seq_printf(m, "Render p-state limit: %d\n",
			   rp_state_limits & 0xff);
1318 1319 1320 1321
		seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
		seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
		seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
		seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1322
		seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
B
Ben Widawsky 已提交
1323
		seq_printf(m, "CAGF: %dMHz\n", cagf);
1324 1325 1326 1327 1328 1329
		seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
			   rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
		seq_printf(m, "RP CUR UP: %d (%dus)\n",
			   rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
		seq_printf(m, "RP PREV UP: %d (%dus)\n",
			   rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1330 1331 1332
		seq_printf(m, "Up threshold: %d%%\n",
			   dev_priv->rps.up_threshold);

1333 1334 1335 1336 1337 1338
		seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
			   rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
		seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
			   rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
		seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
			   rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1339 1340
		seq_printf(m, "Down threshold: %d%%\n",
			   dev_priv->rps.down_threshold);
1341

1342 1343
		max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
			    rp_state_cap >> 16) & 0xff;
1344 1345
		max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
			     GEN9_FREQ_SCALER : 1);
1346
		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1347
			   intel_gpu_freq(dev_priv, max_freq));
1348 1349

		max_freq = (rp_state_cap & 0xff00) >> 8;
1350 1351
		max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
			     GEN9_FREQ_SCALER : 1);
1352
		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1353
			   intel_gpu_freq(dev_priv, max_freq));
1354

1355 1356
		max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
			    rp_state_cap >> 0) & 0xff;
1357 1358
		max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
			     GEN9_FREQ_SCALER : 1);
1359
		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1360
			   intel_gpu_freq(dev_priv, max_freq));
1361
		seq_printf(m, "Max overclocked frequency: %dMHz\n",
1362
			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1363

1364 1365 1366
		seq_printf(m, "Current freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
		seq_printf(m, "Actual freq: %d MHz\n", cagf);
1367 1368
		seq_printf(m, "Idle freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1369 1370 1371 1372 1373 1374 1375
		seq_printf(m, "Min freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
		seq_printf(m, "Max freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
		seq_printf(m,
			   "efficient (RPe) frequency: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1376
	} else {
1377
		seq_puts(m, "no P-state info available\n");
1378
	}
1379

1380 1381 1382 1383
	seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
	seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
	seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);

1384 1385 1386
out:
	intel_runtime_pm_put(dev_priv);
	return ret;
1387 1388
}

1389 1390 1391
static int i915_hangcheck_info(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = m->private;
1392 1393
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1394
	struct intel_engine_cs *engine;
1395 1396
	u64 acthd[I915_NUM_ENGINES];
	u32 seqno[I915_NUM_ENGINES];
1397
	u32 instdone[I915_NUM_INSTDONE_REG];
1398 1399
	enum intel_engine_id id;
	int j;
1400 1401 1402 1403 1404 1405

	if (!i915.enable_hangcheck) {
		seq_printf(m, "Hangcheck disabled\n");
		return 0;
	}

1406 1407
	intel_runtime_pm_get(dev_priv);

1408 1409
	for_each_engine_id(engine, dev_priv, id) {
		acthd[id] = intel_ring_get_active_head(engine);
1410
		seqno[id] = engine->get_seqno(engine);
1411 1412
	}

1413
	i915_get_extra_instdone(dev_priv, instdone);
1414

1415 1416
	intel_runtime_pm_put(dev_priv);

1417 1418 1419 1420 1421 1422 1423
	if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
		seq_printf(m, "Hangcheck active, fires in %dms\n",
			   jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
					    jiffies));
	} else
		seq_printf(m, "Hangcheck inactive\n");

1424
	for_each_engine_id(engine, dev_priv, id) {
1425
		seq_printf(m, "%s:\n", engine->name);
1426 1427 1428 1429
		seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
			   engine->hangcheck.seqno,
			   seqno[id],
			   engine->last_submitted_seqno);
1430 1431 1432
		seq_printf(m, "\tuser interrupts = %x [current %x]\n",
			   engine->hangcheck.user_interrupts,
			   READ_ONCE(engine->user_interrupts));
1433
		seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1434
			   (long long)engine->hangcheck.acthd,
1435
			   (long long)acthd[id]);
1436 1437
		seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
		seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1438

1439
		if (engine->id == RCS) {
1440 1441 1442 1443 1444 1445 1446 1447 1448
			seq_puts(m, "\tinstdone read =");

			for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
				seq_printf(m, " 0x%08x", instdone[j]);

			seq_puts(m, "\n\tinstdone accu =");

			for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
				seq_printf(m, " 0x%08x",
1449
					   engine->hangcheck.instdone[j]);
1450 1451 1452

			seq_puts(m, "\n");
		}
1453 1454 1455 1456 1457
	}

	return 0;
}

1458
static int ironlake_drpc_info(struct seq_file *m)
1459
{
1460
	struct drm_info_node *node = m->private;
1461
	struct drm_device *dev = node->minor->dev;
1462
	struct drm_i915_private *dev_priv = dev->dev_private;
1463 1464 1465 1466 1467 1468 1469
	u32 rgvmodectl, rstdbyctl;
	u16 crstandvid;
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1470
	intel_runtime_pm_get(dev_priv);
1471 1472 1473 1474 1475

	rgvmodectl = I915_READ(MEMMODECTL);
	rstdbyctl = I915_READ(RSTDBYCTL);
	crstandvid = I915_READ16(CRSTANDVID);

1476
	intel_runtime_pm_put(dev_priv);
1477
	mutex_unlock(&dev->struct_mutex);
1478

1479
	seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1480 1481 1482 1483
	seq_printf(m, "Boost freq: %d\n",
		   (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
		   MEMMODE_BOOST_FREQ_SHIFT);
	seq_printf(m, "HW control enabled: %s\n",
1484
		   yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1485
	seq_printf(m, "SW control enabled: %s\n",
1486
		   yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1487
	seq_printf(m, "Gated voltage change: %s\n",
1488
		   yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1489 1490
	seq_printf(m, "Starting frequency: P%d\n",
		   (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1491
	seq_printf(m, "Max P-state: P%d\n",
1492
		   (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1493 1494 1495 1496
	seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
	seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
	seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
	seq_printf(m, "Render standby enabled: %s\n",
1497
		   yesno(!(rstdbyctl & RCX_SW_EXIT)));
1498
	seq_puts(m, "Current RS state: ");
1499 1500
	switch (rstdbyctl & RSX_STATUS_MASK) {
	case RSX_STATUS_ON:
1501
		seq_puts(m, "on\n");
1502 1503
		break;
	case RSX_STATUS_RC1:
1504
		seq_puts(m, "RC1\n");
1505 1506
		break;
	case RSX_STATUS_RC1E:
1507
		seq_puts(m, "RC1E\n");
1508 1509
		break;
	case RSX_STATUS_RS1:
1510
		seq_puts(m, "RS1\n");
1511 1512
		break;
	case RSX_STATUS_RS2:
1513
		seq_puts(m, "RS2 (RC6)\n");
1514 1515
		break;
	case RSX_STATUS_RS3:
1516
		seq_puts(m, "RC3 (RC6+)\n");
1517 1518
		break;
	default:
1519
		seq_puts(m, "unknown\n");
1520 1521
		break;
	}
1522 1523 1524 1525

	return 0;
}

1526
static int i915_forcewake_domains(struct seq_file *m, void *data)
1527
{
1528 1529 1530 1531 1532 1533
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_uncore_forcewake_domain *fw_domain;

	spin_lock_irq(&dev_priv->uncore.lock);
1534
	for_each_fw_domain(fw_domain, dev_priv) {
1535
		seq_printf(m, "%s.wake_count = %u\n",
1536
			   intel_uncore_forcewake_domain_to_str(fw_domain->id),
1537 1538 1539
			   fw_domain->wake_count);
	}
	spin_unlock_irq(&dev_priv->uncore.lock);
1540

1541 1542 1543 1544 1545
	return 0;
}

static int vlv_drpc_info(struct seq_file *m)
{
1546
	struct drm_info_node *node = m->private;
1547 1548
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1549
	u32 rpmodectl1, rcctl1, pw_status;
1550

1551 1552
	intel_runtime_pm_get(dev_priv);

1553
	pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1554 1555 1556
	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
	rcctl1 = I915_READ(GEN6_RC_CONTROL);

1557 1558
	intel_runtime_pm_put(dev_priv);

1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571
	seq_printf(m, "Video Turbo Mode: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
	seq_printf(m, "Turbo enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "HW control enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "SW control enabled: %s\n",
		   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
			  GEN6_RP_MEDIA_SW_MODE));
	seq_printf(m, "RC6 Enabled: %s\n",
		   yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
					GEN6_RC_CTL_EI_MODE(1))));
	seq_printf(m, "Render Power Well: %s\n",
1572
		   (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1573
	seq_printf(m, "Media Power Well: %s\n",
1574
		   (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1575

1576 1577 1578 1579 1580
	seq_printf(m, "Render RC6 residency since boot: %u\n",
		   I915_READ(VLV_GT_RENDER_RC6));
	seq_printf(m, "Media RC6 residency since boot: %u\n",
		   I915_READ(VLV_GT_MEDIA_RC6));

1581
	return i915_forcewake_domains(m, NULL);
1582 1583
}

1584 1585
static int gen6_drpc_info(struct seq_file *m)
{
1586
	struct drm_info_node *node = m->private;
1587 1588
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
B
Ben Widawsky 已提交
1589
	u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1590
	unsigned forcewake_count;
1591
	int count = 0, ret;
1592 1593 1594 1595

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1596
	intel_runtime_pm_get(dev_priv);
1597

1598
	spin_lock_irq(&dev_priv->uncore.lock);
1599
	forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1600
	spin_unlock_irq(&dev_priv->uncore.lock);
1601 1602

	if (forcewake_count) {
1603 1604
		seq_puts(m, "RC information inaccurate because somebody "
			    "holds a forcewake reference \n");
1605 1606 1607 1608 1609 1610 1611
	} else {
		/* NB: we cannot use forcewake, else we read the wrong values */
		while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
			udelay(10);
		seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
	}

1612
	gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1613
	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1614 1615 1616 1617

	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
	rcctl1 = I915_READ(GEN6_RC_CONTROL);
	mutex_unlock(&dev->struct_mutex);
1618 1619 1620
	mutex_lock(&dev_priv->rps.hw_lock);
	sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
	mutex_unlock(&dev_priv->rps.hw_lock);
1621

1622 1623
	intel_runtime_pm_put(dev_priv);

1624 1625 1626 1627 1628 1629 1630
	seq_printf(m, "Video Turbo Mode: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
	seq_printf(m, "HW control enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "SW control enabled: %s\n",
		   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
			  GEN6_RP_MEDIA_SW_MODE));
1631
	seq_printf(m, "RC1e Enabled: %s\n",
1632 1633 1634 1635 1636 1637 1638
		   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
	seq_printf(m, "RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
	seq_printf(m, "Deep RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
	seq_printf(m, "Deepest RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1639
	seq_puts(m, "Current RC state: ");
1640 1641 1642
	switch (gt_core_status & GEN6_RCn_MASK) {
	case GEN6_RC0:
		if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1643
			seq_puts(m, "Core Power Down\n");
1644
		else
1645
			seq_puts(m, "on\n");
1646 1647
		break;
	case GEN6_RC3:
1648
		seq_puts(m, "RC3\n");
1649 1650
		break;
	case GEN6_RC6:
1651
		seq_puts(m, "RC6\n");
1652 1653
		break;
	case GEN6_RC7:
1654
		seq_puts(m, "RC7\n");
1655 1656
		break;
	default:
1657
		seq_puts(m, "Unknown\n");
1658 1659 1660 1661 1662
		break;
	}

	seq_printf(m, "Core Power Down: %s\n",
		   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673

	/* Not exactly sure what this is */
	seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6_LOCKED));
	seq_printf(m, "RC6 residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6));
	seq_printf(m, "RC6+ residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6p));
	seq_printf(m, "RC6++ residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6pp));

B
Ben Widawsky 已提交
1674 1675 1676 1677 1678 1679
	seq_printf(m, "RC6   voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
	seq_printf(m, "RC6+  voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
	seq_printf(m, "RC6++ voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1680 1681 1682 1683 1684
	return 0;
}

static int i915_drpc_info(struct seq_file *m, void *unused)
{
1685
	struct drm_info_node *node = m->private;
1686 1687
	struct drm_device *dev = node->minor->dev;

1688
	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1689
		return vlv_drpc_info(m);
1690
	else if (INTEL_INFO(dev)->gen >= 6)
1691 1692 1693 1694 1695
		return gen6_drpc_info(m);
	else
		return ironlake_drpc_info(m);
}

1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710
static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	seq_printf(m, "FB tracking busy bits: 0x%08x\n",
		   dev_priv->fb_tracking.busy_bits);

	seq_printf(m, "FB tracking flip bits: 0x%08x\n",
		   dev_priv->fb_tracking.flip_bits);

	return 0;
}

1711 1712
static int i915_fbc_status(struct seq_file *m, void *unused)
{
1713
	struct drm_info_node *node = m->private;
1714
	struct drm_device *dev = node->minor->dev;
1715
	struct drm_i915_private *dev_priv = dev->dev_private;
1716

1717
	if (!HAS_FBC(dev)) {
1718
		seq_puts(m, "FBC unsupported on this chipset\n");
1719 1720 1721
		return 0;
	}

1722
	intel_runtime_pm_get(dev_priv);
P
Paulo Zanoni 已提交
1723
	mutex_lock(&dev_priv->fbc.lock);
1724

1725
	if (intel_fbc_is_active(dev_priv))
1726
		seq_puts(m, "FBC enabled\n");
1727 1728
	else
		seq_printf(m, "FBC disabled: %s\n",
1729
			   dev_priv->fbc.no_fbc_reason);
1730

1731 1732 1733 1734 1735
	if (INTEL_INFO(dev_priv)->gen >= 7)
		seq_printf(m, "Compressing: %s\n",
			   yesno(I915_READ(FBC_STATUS2) &
				 FBC_COMPRESSION_MASK));

P
Paulo Zanoni 已提交
1736
	mutex_unlock(&dev_priv->fbc.lock);
1737 1738
	intel_runtime_pm_put(dev_priv);

1739 1740 1741
	return 0;
}

1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763
static int i915_fbc_fc_get(void *data, u64 *val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
		return -ENODEV;

	*val = dev_priv->fbc.false_color;

	return 0;
}

static int i915_fbc_fc_set(void *data, u64 val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 reg;

	if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
		return -ENODEV;

P
Paulo Zanoni 已提交
1764
	mutex_lock(&dev_priv->fbc.lock);
1765 1766 1767 1768 1769 1770 1771 1772

	reg = I915_READ(ILK_DPFC_CONTROL);
	dev_priv->fbc.false_color = val;

	I915_WRITE(ILK_DPFC_CONTROL, val ?
		   (reg | FBC_CTL_FALSE_COLOR) :
		   (reg & ~FBC_CTL_FALSE_COLOR));

P
Paulo Zanoni 已提交
1773
	mutex_unlock(&dev_priv->fbc.lock);
1774 1775 1776 1777 1778 1779 1780
	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
			i915_fbc_fc_get, i915_fbc_fc_set,
			"%llu\n");

1781 1782
static int i915_ips_status(struct seq_file *m, void *unused)
{
1783
	struct drm_info_node *node = m->private;
1784 1785 1786
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

1787
	if (!HAS_IPS(dev)) {
1788 1789 1790 1791
		seq_puts(m, "not supported\n");
		return 0;
	}

1792 1793
	intel_runtime_pm_get(dev_priv);

1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804
	seq_printf(m, "Enabled by kernel parameter: %s\n",
		   yesno(i915.enable_ips));

	if (INTEL_INFO(dev)->gen >= 8) {
		seq_puts(m, "Currently: unknown\n");
	} else {
		if (I915_READ(IPS_CTL) & IPS_ENABLE)
			seq_puts(m, "Currently: enabled\n");
		else
			seq_puts(m, "Currently: disabled\n");
	}
1805

1806 1807
	intel_runtime_pm_put(dev_priv);

1808 1809 1810
	return 0;
}

1811 1812
static int i915_sr_status(struct seq_file *m, void *unused)
{
1813
	struct drm_info_node *node = m->private;
1814
	struct drm_device *dev = node->minor->dev;
1815
	struct drm_i915_private *dev_priv = dev->dev_private;
1816 1817
	bool sr_enabled = false;

1818 1819
	intel_runtime_pm_get(dev_priv);

1820
	if (HAS_PCH_SPLIT(dev))
1821
		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1822 1823
	else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
		 IS_I945G(dev) || IS_I945GM(dev))
1824 1825 1826 1827 1828
		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
	else if (IS_I915GM(dev))
		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
	else if (IS_PINEVIEW(dev))
		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1829
	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1830
		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1831

1832 1833
	intel_runtime_pm_put(dev_priv);

1834 1835
	seq_printf(m, "self-refresh: %s\n",
		   sr_enabled ? "enabled" : "disabled");
1836 1837 1838 1839

	return 0;
}

1840 1841
static int i915_emon_status(struct seq_file *m, void *unused)
{
1842
	struct drm_info_node *node = m->private;
1843
	struct drm_device *dev = node->minor->dev;
1844
	struct drm_i915_private *dev_priv = dev->dev_private;
1845
	unsigned long temp, chipset, gfx;
1846 1847
	int ret;

1848 1849 1850
	if (!IS_GEN5(dev))
		return -ENODEV;

1851 1852 1853
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1854 1855 1856 1857

	temp = i915_mch_val(dev_priv);
	chipset = i915_chipset_val(dev_priv);
	gfx = i915_gfx_val(dev_priv);
1858
	mutex_unlock(&dev->struct_mutex);
1859 1860 1861 1862 1863 1864 1865 1866 1867

	seq_printf(m, "GMCH temp: %ld\n", temp);
	seq_printf(m, "Chipset power: %ld\n", chipset);
	seq_printf(m, "GFX power: %ld\n", gfx);
	seq_printf(m, "Total power: %ld\n", chipset + gfx);

	return 0;
}

1868 1869
static int i915_ring_freq_table(struct seq_file *m, void *unused)
{
1870
	struct drm_info_node *node = m->private;
1871
	struct drm_device *dev = node->minor->dev;
1872
	struct drm_i915_private *dev_priv = dev->dev_private;
1873
	int ret = 0;
1874
	int gpu_freq, ia_freq;
1875
	unsigned int max_gpu_freq, min_gpu_freq;
1876

1877
	if (!HAS_CORE_RING_FREQ(dev)) {
1878
		seq_puts(m, "unsupported on this chipset\n");
1879 1880 1881
		return 0;
	}

1882 1883
	intel_runtime_pm_get(dev_priv);

1884 1885
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

1886
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1887
	if (ret)
1888
		goto out;
1889

1890
	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1891 1892 1893 1894 1895 1896 1897 1898 1899 1900
		/* Convert GT frequency to 50 HZ units */
		min_gpu_freq =
			dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
		max_gpu_freq =
			dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
	} else {
		min_gpu_freq = dev_priv->rps.min_freq_softlimit;
		max_gpu_freq = dev_priv->rps.max_freq_softlimit;
	}

1901
	seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1902

1903
	for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
B
Ben Widawsky 已提交
1904 1905 1906 1907
		ia_freq = gpu_freq;
		sandybridge_pcode_read(dev_priv,
				       GEN6_PCODE_READ_MIN_FREQ_TABLE,
				       &ia_freq);
1908
		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1909
			   intel_gpu_freq(dev_priv, (gpu_freq *
1910 1911
				(IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
				 GEN9_FREQ_SCALER : 1))),
1912 1913
			   ((ia_freq >> 0) & 0xff) * 100,
			   ((ia_freq >> 8) & 0xff) * 100);
1914 1915
	}

1916
	mutex_unlock(&dev_priv->rps.hw_lock);
1917

1918 1919 1920
out:
	intel_runtime_pm_put(dev_priv);
	return ret;
1921 1922
}

1923 1924
static int i915_opregion(struct seq_file *m, void *unused)
{
1925
	struct drm_info_node *node = m->private;
1926
	struct drm_device *dev = node->minor->dev;
1927
	struct drm_i915_private *dev_priv = dev->dev_private;
1928 1929 1930 1931 1932
	struct intel_opregion *opregion = &dev_priv->opregion;
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
1933
		goto out;
1934

1935 1936
	if (opregion->header)
		seq_write(m, opregion->header, OPREGION_SIZE);
1937 1938 1939

	mutex_unlock(&dev->struct_mutex);

1940
out:
1941 1942 1943
	return 0;
}

1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956
static int i915_vbt(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_opregion *opregion = &dev_priv->opregion;

	if (opregion->vbt)
		seq_write(m, opregion->vbt, opregion->vbt_size);

	return 0;
}

1957 1958
static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
{
1959
	struct drm_info_node *node = m->private;
1960
	struct drm_device *dev = node->minor->dev;
1961
	struct intel_framebuffer *fbdev_fb = NULL;
1962
	struct drm_framebuffer *drm_fb;
1963 1964 1965 1966 1967
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1968

1969
#ifdef CONFIG_DRM_FBDEV_EMULATION
1970 1971 1972 1973 1974 1975 1976 1977 1978
       if (to_i915(dev)->fbdev) {
               fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);

               seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
                         fbdev_fb->base.width,
                         fbdev_fb->base.height,
                         fbdev_fb->base.depth,
                         fbdev_fb->base.bits_per_pixel,
                         fbdev_fb->base.modifier[0],
1979
                         drm_framebuffer_read_refcount(&fbdev_fb->base));
1980 1981 1982
               describe_obj(m, fbdev_fb->obj);
               seq_putc(m, '\n');
       }
1983
#endif
1984

1985
	mutex_lock(&dev->mode_config.fb_lock);
1986
	drm_for_each_fb(drm_fb, dev) {
1987 1988
		struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
		if (fb == fbdev_fb)
1989 1990
			continue;

1991
		seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1992 1993 1994
			   fb->base.width,
			   fb->base.height,
			   fb->base.depth,
1995
			   fb->base.bits_per_pixel,
1996
			   fb->base.modifier[0],
1997
			   drm_framebuffer_read_refcount(&fb->base));
1998
		describe_obj(m, fb->obj);
1999
		seq_putc(m, '\n');
2000
	}
2001
	mutex_unlock(&dev->mode_config.fb_lock);
2002
	mutex_unlock(&dev->struct_mutex);
2003 2004 2005 2006

	return 0;
}

2007 2008 2009 2010 2011 2012 2013 2014
static void describe_ctx_ringbuf(struct seq_file *m,
				 struct intel_ringbuffer *ringbuf)
{
	seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
		   ringbuf->space, ringbuf->head, ringbuf->tail,
		   ringbuf->last_retired_head);
}

2015 2016
static int i915_context_status(struct seq_file *m, void *unused)
{
2017
	struct drm_info_node *node = m->private;
2018
	struct drm_device *dev = node->minor->dev;
2019
	struct drm_i915_private *dev_priv = dev->dev_private;
2020
	struct intel_engine_cs *engine;
2021
	struct i915_gem_context *ctx;
2022
	int ret;
2023

2024
	ret = mutex_lock_interruptible(&dev->struct_mutex);
2025 2026 2027
	if (ret)
		return ret;

2028
	list_for_each_entry(ctx, &dev_priv->context_list, link) {
2029
		seq_printf(m, "HW context %u ", ctx->hw_id);
2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045
		if (IS_ERR(ctx->file_priv)) {
			seq_puts(m, "(deleted) ");
		} else if (ctx->file_priv) {
			struct pid *pid = ctx->file_priv->file->pid;
			struct task_struct *task;

			task = get_pid_task(pid, PIDTYPE_PID);
			if (task) {
				seq_printf(m, "(%s [%d]) ",
					   task->comm, task->pid);
				put_task_struct(task);
			}
		} else {
			seq_puts(m, "(kernel) ");
		}

2046 2047
		seq_putc(m, ctx->remap_slice ? 'R' : 'r');
		seq_putc(m, '\n');
2048

2049 2050 2051 2052 2053 2054 2055 2056 2057
		for_each_engine(engine, dev_priv) {
			struct intel_context *ce = &ctx->engine[engine->id];

			seq_printf(m, "%s: ", engine->name);
			seq_putc(m, ce->initialised ? 'I' : 'i');
			if (ce->state)
				describe_obj(m, ce->state);
			if (ce->ringbuf)
				describe_ctx_ringbuf(m, ce->ringbuf);
2058 2059
			seq_putc(m, '\n');
		}
2060 2061

		seq_putc(m, '\n');
2062 2063
	}

2064
	mutex_unlock(&dev->struct_mutex);
2065 2066 2067 2068

	return 0;
}

2069
static void i915_dump_lrc_obj(struct seq_file *m,
2070
			      struct i915_gem_context *ctx,
2071
			      struct intel_engine_cs *engine)
2072
{
2073
	struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2074 2075 2076 2077 2078
	struct page *page;
	uint32_t *reg_state;
	int j;
	unsigned long ggtt_offset = 0;

2079 2080
	seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);

2081
	if (ctx_obj == NULL) {
2082
		seq_puts(m, "\tNot allocated\n");
2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095
		return;
	}

	if (!i915_gem_obj_ggtt_bound(ctx_obj))
		seq_puts(m, "\tNot bound in GGTT\n");
	else
		ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);

	if (i915_gem_object_get_pages(ctx_obj)) {
		seq_puts(m, "\tFailed to get pages for context object\n");
		return;
	}

2096
	page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111
	if (!WARN_ON(page == NULL)) {
		reg_state = kmap_atomic(page);

		for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
			seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
				   ggtt_offset + 4096 + (j * 4),
				   reg_state[j], reg_state[j + 1],
				   reg_state[j + 2], reg_state[j + 3]);
		}
		kunmap_atomic(reg_state);
	}

	seq_putc(m, '\n');
}

2112 2113 2114 2115 2116
static int i915_dump_lrc(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2117
	struct intel_engine_cs *engine;
2118
	struct i915_gem_context *ctx;
2119
	int ret;
2120 2121 2122 2123 2124 2125 2126 2127 2128 2129

	if (!i915.enable_execlists) {
		seq_printf(m, "Logical Ring Contexts are disabled\n");
		return 0;
	}

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

D
Dave Gordon 已提交
2130
	list_for_each_entry(ctx, &dev_priv->context_list, link)
2131 2132
		for_each_engine(engine, dev_priv)
			i915_dump_lrc_obj(m, ctx, engine);
2133 2134 2135 2136 2137 2138

	mutex_unlock(&dev->struct_mutex);

	return 0;
}

2139 2140 2141 2142 2143
static int i915_execlists(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2144
	struct intel_engine_cs *engine;
2145 2146 2147 2148 2149 2150
	u32 status_pointer;
	u8 read_pointer;
	u8 write_pointer;
	u32 status;
	u32 ctx_id;
	struct list_head *cursor;
2151
	int i, ret;
2152 2153 2154 2155 2156 2157 2158 2159 2160 2161

	if (!i915.enable_execlists) {
		seq_puts(m, "Logical Ring Contexts are disabled\n");
		return 0;
	}

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

2162 2163
	intel_runtime_pm_get(dev_priv);

2164
	for_each_engine(engine, dev_priv) {
2165
		struct drm_i915_gem_request *head_req = NULL;
2166 2167
		int count = 0;

2168
		seq_printf(m, "%s\n", engine->name);
2169

2170 2171
		status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
		ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2172 2173 2174
		seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
			   status, ctx_id);

2175
		status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2176 2177
		seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);

2178
		read_pointer = engine->next_context_status_buffer;
2179
		write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2180
		if (read_pointer > write_pointer)
2181
			write_pointer += GEN8_CSB_ENTRIES;
2182 2183 2184
		seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
			   read_pointer, write_pointer);

2185
		for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2186 2187
			status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
			ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2188 2189 2190 2191 2192

			seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
				   i, status, ctx_id);
		}

2193
		spin_lock_bh(&engine->execlist_lock);
2194
		list_for_each(cursor, &engine->execlist_queue)
2195
			count++;
2196 2197 2198
		head_req = list_first_entry_or_null(&engine->execlist_queue,
						    struct drm_i915_gem_request,
						    execlist_link);
2199
		spin_unlock_bh(&engine->execlist_lock);
2200 2201 2202

		seq_printf(m, "\t%d requests in queue\n", count);
		if (head_req) {
2203 2204
			seq_printf(m, "\tHead request context: %u\n",
				   head_req->ctx->hw_id);
2205
			seq_printf(m, "\tHead request tail: %u\n",
2206
				   head_req->tail);
2207 2208 2209 2210 2211
		}

		seq_putc(m, '\n');
	}

2212
	intel_runtime_pm_put(dev_priv);
2213 2214 2215 2216 2217
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

2218 2219
static const char *swizzle_string(unsigned swizzle)
{
2220
	switch (swizzle) {
2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235
	case I915_BIT_6_SWIZZLE_NONE:
		return "none";
	case I915_BIT_6_SWIZZLE_9:
		return "bit9";
	case I915_BIT_6_SWIZZLE_9_10:
		return "bit9/bit10";
	case I915_BIT_6_SWIZZLE_9_11:
		return "bit9/bit11";
	case I915_BIT_6_SWIZZLE_9_10_11:
		return "bit9/bit10/bit11";
	case I915_BIT_6_SWIZZLE_9_17:
		return "bit9/bit17";
	case I915_BIT_6_SWIZZLE_9_10_17:
		return "bit9/bit10/bit17";
	case I915_BIT_6_SWIZZLE_UNKNOWN:
2236
		return "unknown";
2237 2238 2239 2240 2241 2242 2243
	}

	return "bug";
}

static int i915_swizzle_info(struct seq_file *m, void *data)
{
2244
	struct drm_info_node *node = m->private;
2245 2246
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2247 2248 2249 2250 2251
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
2252
	intel_runtime_pm_get(dev_priv);
2253 2254 2255 2256 2257 2258 2259 2260 2261

	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
		   swizzle_string(dev_priv->mm.bit_6_swizzle_x));
	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
		   swizzle_string(dev_priv->mm.bit_6_swizzle_y));

	if (IS_GEN3(dev) || IS_GEN4(dev)) {
		seq_printf(m, "DDC = 0x%08x\n",
			   I915_READ(DCC));
2262 2263
		seq_printf(m, "DDC2 = 0x%08x\n",
			   I915_READ(DCC2));
2264 2265 2266 2267
		seq_printf(m, "C0DRB3 = 0x%04x\n",
			   I915_READ16(C0DRB3));
		seq_printf(m, "C1DRB3 = 0x%04x\n",
			   I915_READ16(C1DRB3));
B
Ben Widawsky 已提交
2268
	} else if (INTEL_INFO(dev)->gen >= 6) {
2269 2270 2271 2272 2273 2274 2275 2276
		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C0));
		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C1));
		seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C2));
		seq_printf(m, "TILECTL = 0x%08x\n",
			   I915_READ(TILECTL));
2277
		if (INTEL_INFO(dev)->gen >= 8)
B
Ben Widawsky 已提交
2278 2279 2280 2281 2282
			seq_printf(m, "GAMTARBMODE = 0x%08x\n",
				   I915_READ(GAMTARBMODE));
		else
			seq_printf(m, "ARB_MODE = 0x%08x\n",
				   I915_READ(ARB_MODE));
2283 2284
		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
			   I915_READ(DISP_ARB_CTL));
2285
	}
2286 2287 2288 2289

	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
		seq_puts(m, "L-shaped memory detected\n");

2290
	intel_runtime_pm_put(dev_priv);
2291 2292 2293 2294 2295
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

B
Ben Widawsky 已提交
2296 2297
static int per_file_ctx(int id, void *ptr, void *data)
{
2298
	struct i915_gem_context *ctx = ptr;
B
Ben Widawsky 已提交
2299
	struct seq_file *m = data;
2300 2301 2302 2303 2304 2305 2306
	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;

	if (!ppgtt) {
		seq_printf(m, "  no ppgtt for context %d\n",
			   ctx->user_handle);
		return 0;
	}
B
Ben Widawsky 已提交
2307

2308 2309 2310
	if (i915_gem_context_is_default(ctx))
		seq_puts(m, "  default context:\n");
	else
2311
		seq_printf(m, "  context %d:\n", ctx->user_handle);
B
Ben Widawsky 已提交
2312 2313 2314 2315 2316
	ppgtt->debug_dump(ppgtt, m);

	return 0;
}

B
Ben Widawsky 已提交
2317
static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
D
Daniel Vetter 已提交
2318 2319
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2320
	struct intel_engine_cs *engine;
B
Ben Widawsky 已提交
2321
	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2322
	int i;
D
Daniel Vetter 已提交
2323

B
Ben Widawsky 已提交
2324 2325 2326
	if (!ppgtt)
		return;

2327
	for_each_engine(engine, dev_priv) {
2328
		seq_printf(m, "%s\n", engine->name);
B
Ben Widawsky 已提交
2329
		for (i = 0; i < 4; i++) {
2330
			u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
B
Ben Widawsky 已提交
2331
			pdp <<= 32;
2332
			pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2333
			seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
B
Ben Widawsky 已提交
2334 2335 2336 2337 2338 2339 2340
		}
	}
}

static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2341
	struct intel_engine_cs *engine;
D
Daniel Vetter 已提交
2342

2343
	if (IS_GEN6(dev_priv))
D
Daniel Vetter 已提交
2344 2345
		seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));

2346
	for_each_engine(engine, dev_priv) {
2347
		seq_printf(m, "%s\n", engine->name);
2348
		if (IS_GEN7(dev_priv))
2349 2350 2351 2352 2353 2354 2355 2356
			seq_printf(m, "GFX_MODE: 0x%08x\n",
				   I915_READ(RING_MODE_GEN7(engine)));
		seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
			   I915_READ(RING_PP_DIR_BASE(engine)));
		seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
			   I915_READ(RING_PP_DIR_BASE_READ(engine)));
		seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
			   I915_READ(RING_PP_DIR_DCLV(engine)));
D
Daniel Vetter 已提交
2357 2358 2359 2360
	}
	if (dev_priv->mm.aliasing_ppgtt) {
		struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;

2361
		seq_puts(m, "aliasing PPGTT:\n");
2362
		seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
B
Ben Widawsky 已提交
2363

B
Ben Widawsky 已提交
2364
		ppgtt->debug_dump(ppgtt, m);
2365
	}
B
Ben Widawsky 已提交
2366

D
Daniel Vetter 已提交
2367
	seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
B
Ben Widawsky 已提交
2368 2369 2370 2371
}

static int i915_ppgtt_info(struct seq_file *m, void *data)
{
2372
	struct drm_info_node *node = m->private;
B
Ben Widawsky 已提交
2373
	struct drm_device *dev = node->minor->dev;
2374
	struct drm_i915_private *dev_priv = dev->dev_private;
2375
	struct drm_file *file;
B
Ben Widawsky 已提交
2376 2377 2378 2379

	int ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
2380
	intel_runtime_pm_get(dev_priv);
B
Ben Widawsky 已提交
2381 2382 2383 2384 2385 2386

	if (INTEL_INFO(dev)->gen >= 8)
		gen8_ppgtt_info(m, dev);
	else if (INTEL_INFO(dev)->gen >= 6)
		gen6_ppgtt_info(m, dev);

2387
	mutex_lock(&dev->filelist_mutex);
2388 2389
	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct drm_i915_file_private *file_priv = file->driver_priv;
2390
		struct task_struct *task;
2391

2392
		task = get_pid_task(file->pid, PIDTYPE_PID);
2393 2394 2395 2396
		if (!task) {
			ret = -ESRCH;
			goto out_put;
		}
2397 2398
		seq_printf(m, "\nproc: %s\n", task->comm);
		put_task_struct(task);
2399 2400 2401
		idr_for_each(&file_priv->context_idr, per_file_ctx,
			     (void *)(unsigned long)m);
	}
2402
	mutex_unlock(&dev->filelist_mutex);
2403

2404
out_put:
2405
	intel_runtime_pm_put(dev_priv);
D
Daniel Vetter 已提交
2406 2407
	mutex_unlock(&dev->struct_mutex);

2408
	return ret;
D
Daniel Vetter 已提交
2409 2410
}

2411 2412
static int count_irq_waiters(struct drm_i915_private *i915)
{
2413
	struct intel_engine_cs *engine;
2414 2415
	int count = 0;

2416
	for_each_engine(engine, i915)
2417
		count += engine->irq_refcount;
2418 2419 2420 2421

	return count;
}

2422 2423 2424 2425 2426 2427 2428
static int i915_rps_boost_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_file *file;

2429 2430 2431 2432 2433 2434 2435 2436 2437
	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
	seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
	seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
	seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
		   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
		   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
		   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
		   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
		   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2438 2439

	mutex_lock(&dev->filelist_mutex);
2440
	spin_lock(&dev_priv->rps.client_lock);
2441 2442 2443 2444 2445 2446 2447 2448 2449
	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct drm_i915_file_private *file_priv = file->driver_priv;
		struct task_struct *task;

		rcu_read_lock();
		task = pid_task(file->pid, PIDTYPE_PID);
		seq_printf(m, "%s [%d]: %d boosts%s\n",
			   task ? task->comm : "<unknown>",
			   task ? task->pid : -1,
2450 2451
			   file_priv->rps.boosts,
			   list_empty(&file_priv->rps.link) ? "" : ", active");
2452 2453
		rcu_read_unlock();
	}
2454 2455 2456 2457 2458 2459
	seq_printf(m, "Semaphore boosts: %d%s\n",
		   dev_priv->rps.semaphores.boosts,
		   list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
	seq_printf(m, "MMIO flip boosts: %d%s\n",
		   dev_priv->rps.mmioflips.boosts,
		   list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2460
	seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2461
	spin_unlock(&dev_priv->rps.client_lock);
2462
	mutex_unlock(&dev->filelist_mutex);
2463

2464
	return 0;
2465 2466
}

2467 2468
static int i915_llc(struct seq_file *m, void *data)
{
2469
	struct drm_info_node *node = m->private;
2470 2471
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2472
	const bool edram = INTEL_GEN(dev_priv) > 8;
2473 2474

	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2475 2476
	seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
		   intel_uncore_edram_size(dev_priv)/1024/1024);
2477 2478 2479 2480

	return 0;
}

2481 2482 2483 2484 2485 2486 2487
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = m->private;
	struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
	u32 tmp, i;

2488
	if (!HAS_GUC_UCODE(dev_priv))
2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501
		return 0;

	seq_printf(m, "GuC firmware status:\n");
	seq_printf(m, "\tpath: %s\n",
		guc_fw->guc_fw_path);
	seq_printf(m, "\tfetch: %s\n",
		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
	seq_printf(m, "\tload: %s\n",
		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
	seq_printf(m, "\tversion wanted: %d.%d\n",
		guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
	seq_printf(m, "\tversion found: %d.%d\n",
		guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
A
Alex Dai 已提交
2502 2503 2504 2505 2506 2507
	seq_printf(m, "\theader: offset is %d; size = %d\n",
		guc_fw->header_offset, guc_fw->header_size);
	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
		guc_fw->ucode_offset, guc_fw->ucode_size);
	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
		guc_fw->rsa_offset, guc_fw->rsa_size);
2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524

	tmp = I915_READ(GUC_STATUS);

	seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
	seq_printf(m, "\tBootrom status = 0x%x\n",
		(tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
	seq_printf(m, "\tuKernel status = 0x%x\n",
		(tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
	seq_printf(m, "\tMIA Core status = 0x%x\n",
		(tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
	seq_puts(m, "\nScratch registers:\n");
	for (i = 0; i < 16; i++)
		seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));

	return 0;
}

2525 2526 2527 2528
static void i915_guc_client_info(struct seq_file *m,
				 struct drm_i915_private *dev_priv,
				 struct i915_guc_client *client)
{
2529
	struct intel_engine_cs *engine;
2530 2531 2532 2533 2534 2535 2536 2537 2538
	uint64_t tot = 0;

	seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
		client->priority, client->ctx_index, client->proc_desc_offset);
	seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
		client->doorbell_id, client->doorbell_offset, client->cookie);
	seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
		client->wq_size, client->wq_offset, client->wq_tail);

2539
	seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2540 2541 2542 2543
	seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
	seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
	seq_printf(m, "\tLast submission result: %d\n", client->retcode);

2544
	for_each_engine(engine, dev_priv) {
2545
		seq_printf(m, "\tSubmissions: %llu %s\n",
2546 2547 2548
				client->submissions[engine->guc_id],
				engine->name);
		tot += client->submissions[engine->guc_id];
2549 2550 2551 2552 2553 2554 2555 2556 2557 2558
	}
	seq_printf(m, "\tTotal: %llu\n", tot);
}

static int i915_guc_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_guc guc;
2559
	struct i915_guc_client client = {};
2560
	struct intel_engine_cs *engine;
2561 2562
	u64 total = 0;

2563
	if (!HAS_GUC_SCHED(dev_priv))
2564 2565
		return 0;

A
Alex Dai 已提交
2566 2567 2568
	if (mutex_lock_interruptible(&dev->struct_mutex))
		return 0;

2569 2570
	/* Take a local copy of the GuC data, so we can dump it at leisure */
	guc = dev_priv->guc;
A
Alex Dai 已提交
2571
	if (guc.execbuf_client)
2572
		client = *guc.execbuf_client;
A
Alex Dai 已提交
2573 2574

	mutex_unlock(&dev->struct_mutex);
2575 2576 2577 2578 2579 2580 2581 2582

	seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
	seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
	seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
	seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
	seq_printf(m, "GuC last action error code: %d\n", guc.action_err);

	seq_printf(m, "\nGuC submissions:\n");
2583
	for_each_engine(engine, dev_priv) {
2584
		seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2585 2586 2587
			engine->name, guc.submissions[engine->guc_id],
			guc.last_seqno[engine->guc_id]);
		total += guc.submissions[engine->guc_id];
2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598
	}
	seq_printf(m, "\t%s: %llu\n", "Total", total);

	seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
	i915_guc_client_info(m, dev_priv, &client);

	/* Add more as required ... */

	return 0;
}

A
Alex Dai 已提交
2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626
static int i915_guc_log_dump(struct seq_file *m, void *data)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
	u32 *log;
	int i = 0, pg;

	if (!log_obj)
		return 0;

	for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
		log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));

		for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
			seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
				   *(log + i), *(log + i + 1),
				   *(log + i + 2), *(log + i + 3));

		kunmap_atomic(log);
	}

	seq_putc(m, '\n');

	return 0;
}

2627 2628 2629 2630 2631
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
R
Rodrigo Vivi 已提交
2632
	u32 psrperf = 0;
R
Rodrigo Vivi 已提交
2633 2634
	u32 stat[3];
	enum pipe pipe;
R
Rodrigo Vivi 已提交
2635
	bool enabled = false;
2636

2637 2638 2639 2640 2641
	if (!HAS_PSR(dev)) {
		seq_puts(m, "PSR not supported\n");
		return 0;
	}

2642 2643
	intel_runtime_pm_get(dev_priv);

2644
	mutex_lock(&dev_priv->psr.lock);
R
Rodrigo Vivi 已提交
2645 2646
	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
	seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2647
	seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2648
	seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2649 2650 2651 2652
	seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
		   dev_priv->psr.busy_frontbuffer_bits);
	seq_printf(m, "Re-enable work scheduled: %s\n",
		   yesno(work_busy(&dev_priv->psr.work.work)));
2653

2654
	if (HAS_DDI(dev))
2655
		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2656 2657 2658 2659 2660 2661 2662
	else {
		for_each_pipe(dev_priv, pipe) {
			stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
				VLV_EDP_PSR_CURR_STATE_MASK;
			if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
			    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
				enabled = true;
R
Rodrigo Vivi 已提交
2663 2664
		}
	}
2665 2666 2667 2668

	seq_printf(m, "Main link in standby mode: %s\n",
		   yesno(dev_priv->psr.link_standby));

R
Rodrigo Vivi 已提交
2669 2670 2671 2672 2673 2674 2675 2676 2677
	seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));

	if (!HAS_DDI(dev))
		for_each_pipe(dev_priv, pipe) {
			if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
			    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
				seq_printf(m, " pipe %c", pipe_name(pipe));
		}
	seq_puts(m, "\n");
2678

2679 2680 2681 2682 2683
	/*
	 * VLV/CHV PSR has no kind of performance counter
	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
	 */
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2684
		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
R
Rodrigo Vivi 已提交
2685
			EDP_PSR_PERF_CNT_MASK;
R
Rodrigo Vivi 已提交
2686 2687 2688

		seq_printf(m, "Performance_Counter: %u\n", psrperf);
	}
2689
	mutex_unlock(&dev_priv->psr.lock);
2690

2691
	intel_runtime_pm_put(dev_priv);
2692 2693 2694
	return 0;
}

2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705
static int i915_sink_crc(struct seq_file *m, void *data)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct intel_encoder *encoder;
	struct intel_connector *connector;
	struct intel_dp *intel_dp = NULL;
	int ret;
	u8 crc[6];

	drm_modeset_lock_all(dev);
2706
	for_each_intel_connector(dev, connector) {
2707 2708 2709 2710

		if (connector->base.dpms != DRM_MODE_DPMS_ON)
			continue;

2711 2712 2713
		if (!connector->base.encoder)
			continue;

2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734
		encoder = to_intel_encoder(connector->base.encoder);
		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);

		ret = intel_dp_sink_crc(intel_dp, crc);
		if (ret)
			goto out;

		seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
			   crc[0], crc[1], crc[2],
			   crc[3], crc[4], crc[5]);
		goto out;
	}
	ret = -ENODEV;
out:
	drm_modeset_unlock_all(dev);
	return ret;
}

2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745
static int i915_energy_uJ(struct seq_file *m, void *data)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u64 power;
	u32 units;

	if (INTEL_INFO(dev)->gen < 6)
		return -ENODEV;

2746 2747
	intel_runtime_pm_get(dev_priv);

2748 2749 2750 2751 2752 2753
	rdmsrl(MSR_RAPL_POWER_UNIT, power);
	power = (power & 0x1f00) >> 8;
	units = 1000000 / (1 << power); /* convert to uJ */
	power = I915_READ(MCH_SECP_NRG_STTS);
	power *= units;

2754 2755
	intel_runtime_pm_put(dev_priv);

2756
	seq_printf(m, "%llu", (long long unsigned)power);
2757 2758 2759 2760

	return 0;
}

2761
static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2762
{
2763
	struct drm_info_node *node = m->private;
2764 2765 2766
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

2767 2768
	if (!HAS_RUNTIME_PM(dev_priv))
		seq_puts(m, "Runtime power management not supported\n");
2769

2770
	seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2771
	seq_printf(m, "IRQs disabled: %s\n",
2772
		   yesno(!intel_irqs_enabled(dev_priv)));
2773
#ifdef CONFIG_PM
2774 2775
	seq_printf(m, "Usage count: %d\n",
		   atomic_read(&dev->dev->power.usage_count));
2776 2777 2778
#else
	seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
#endif
2779 2780 2781
	seq_printf(m, "PCI device power state: %s [%d]\n",
		   pci_power_name(dev_priv->dev->pdev->current_state),
		   dev_priv->dev->pdev->current_state);
2782

2783 2784 2785
	return 0;
}

2786 2787
static int i915_power_domain_info(struct seq_file *m, void *unused)
{
2788
	struct drm_info_node *node = m->private;
2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_power_domains *power_domains = &dev_priv->power_domains;
	int i;

	mutex_lock(&power_domains->lock);

	seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
	for (i = 0; i < power_domains->power_well_count; i++) {
		struct i915_power_well *power_well;
		enum intel_display_power_domain power_domain;

		power_well = &power_domains->power_wells[i];
		seq_printf(m, "%-25s %d\n", power_well->name,
			   power_well->count);

		for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
		     power_domain++) {
			if (!(BIT(power_domain) & power_well->domains))
				continue;

			seq_printf(m, "  %-23s %d\n",
2811
				 intel_display_power_domain_str(power_domain),
2812 2813 2814 2815 2816 2817 2818 2819 2820
				 power_domains->domain_use_count[power_domain]);
		}
	}

	mutex_unlock(&power_domains->lock);

	return 0;
}

2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834
static int i915_dmc_info(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_csr *csr;

	if (!HAS_CSR(dev)) {
		seq_puts(m, "not supported\n");
		return 0;
	}

	csr = &dev_priv->csr;

2835 2836
	intel_runtime_pm_get(dev_priv);

2837 2838 2839 2840
	seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
	seq_printf(m, "path: %s\n", csr->fw_path);

	if (!csr->dmc_payload)
2841
		goto out;
2842 2843 2844 2845

	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
		   CSR_VERSION_MINOR(csr->version));

2846 2847 2848 2849 2850
	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
		seq_printf(m, "DC3 -> DC5 count: %d\n",
			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
		seq_printf(m, "DC5 -> DC6 count: %d\n",
			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
2851 2852 2853
	} else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
		seq_printf(m, "DC3 -> DC5 count: %d\n",
			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
2854 2855
	}

2856 2857 2858 2859 2860
out:
	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));

2861 2862
	intel_runtime_pm_put(dev_priv);

2863 2864 2865
	return 0;
}

2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887
static void intel_seq_print_mode(struct seq_file *m, int tabs,
				 struct drm_display_mode *mode)
{
	int i;

	for (i = 0; i < tabs; i++)
		seq_putc(m, '\t');

	seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
		   mode->base.id, mode->name,
		   mode->vrefresh, mode->clock,
		   mode->hdisplay, mode->hsync_start,
		   mode->hsync_end, mode->htotal,
		   mode->vdisplay, mode->vsync_start,
		   mode->vsync_end, mode->vtotal,
		   mode->type, mode->flags);
}

static void intel_encoder_info(struct seq_file *m,
			       struct intel_crtc *intel_crtc,
			       struct intel_encoder *intel_encoder)
{
2888
	struct drm_info_node *node = m->private;
2889 2890 2891 2892 2893 2894 2895
	struct drm_device *dev = node->minor->dev;
	struct drm_crtc *crtc = &intel_crtc->base;
	struct intel_connector *intel_connector;
	struct drm_encoder *encoder;

	encoder = &intel_encoder->base;
	seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2896
		   encoder->base.id, encoder->name);
2897 2898 2899 2900
	for_each_connector_on_encoder(dev, encoder, intel_connector) {
		struct drm_connector *connector = &intel_connector->base;
		seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
			   connector->base.id,
2901
			   connector->name,
2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914
			   drm_get_connector_status_name(connector->status));
		if (connector->status == connector_status_connected) {
			struct drm_display_mode *mode = &crtc->mode;
			seq_printf(m, ", mode:\n");
			intel_seq_print_mode(m, 2, mode);
		} else {
			seq_putc(m, '\n');
		}
	}
}

static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
2915
	struct drm_info_node *node = m->private;
2916 2917 2918
	struct drm_device *dev = node->minor->dev;
	struct drm_crtc *crtc = &intel_crtc->base;
	struct intel_encoder *intel_encoder;
2919 2920
	struct drm_plane_state *plane_state = crtc->primary->state;
	struct drm_framebuffer *fb = plane_state->fb;
2921

2922
	if (fb)
2923
		seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2924 2925
			   fb->base.id, plane_state->src_x >> 16,
			   plane_state->src_y >> 16, fb->width, fb->height);
2926 2927
	else
		seq_puts(m, "\tprimary plane disabled\n");
2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946
	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		intel_encoder_info(m, intel_crtc, intel_encoder);
}

static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
{
	struct drm_display_mode *mode = panel->fixed_mode;

	seq_printf(m, "\tfixed mode:\n");
	intel_seq_print_mode(m, 2, mode);
}

static void intel_dp_info(struct seq_file *m,
			  struct intel_connector *intel_connector)
{
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2947
	seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2948 2949 2950 2951 2952 2953 2954 2955 2956 2957
	if (intel_encoder->type == INTEL_OUTPUT_EDP)
		intel_panel_info(m, &intel_connector->panel);
}

static void intel_hdmi_info(struct seq_file *m,
			    struct intel_connector *intel_connector)
{
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);

2958
	seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971
}

static void intel_lvds_info(struct seq_file *m,
			    struct intel_connector *intel_connector)
{
	intel_panel_info(m, &intel_connector->panel);
}

static void intel_connector_info(struct seq_file *m,
				 struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct intel_encoder *intel_encoder = intel_connector->encoder;
2972
	struct drm_display_mode *mode;
2973 2974

	seq_printf(m, "connector %d: type %s, status: %s\n",
2975
		   connector->base.id, connector->name,
2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986
		   drm_get_connector_status_name(connector->status));
	if (connector->status == connector_status_connected) {
		seq_printf(m, "\tname: %s\n", connector->display_info.name);
		seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
			   connector->display_info.width_mm,
			   connector->display_info.height_mm);
		seq_printf(m, "\tsubpixel order: %s\n",
			   drm_get_subpixel_order_name(connector->display_info.subpixel_order));
		seq_printf(m, "\tCEA rev: %d\n",
			   connector->display_info.cea_rev);
	}
2987 2988 2989 2990 2991 2992 2993 2994 2995
	if (intel_encoder) {
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
			intel_dp_info(m, intel_connector);
		else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
			intel_hdmi_info(m, intel_connector);
		else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
			intel_lvds_info(m, intel_connector);
	}
2996

2997 2998 2999
	seq_printf(m, "\tmodes:\n");
	list_for_each_entry(mode, &connector->modes, head)
		intel_seq_print_mode(m, 2, mode);
3000 3001
}

3002 3003 3004 3005 3006 3007
static bool cursor_active(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 state;

	if (IS_845G(dev) || IS_I865G(dev))
3008
		state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3009
	else
3010
		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3011 3012 3013 3014 3015 3016 3017 3018 3019

	return state;
}

static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pos;

3020
	pos = I915_READ(CURPOS(pipe));
3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032

	*x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
	if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
		*x = -*x;

	*y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
	if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
		*y = -*y;

	return cursor_active(dev, pipe);
}

3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133
static const char *plane_type(enum drm_plane_type type)
{
	switch (type) {
	case DRM_PLANE_TYPE_OVERLAY:
		return "OVL";
	case DRM_PLANE_TYPE_PRIMARY:
		return "PRI";
	case DRM_PLANE_TYPE_CURSOR:
		return "CUR";
	/*
	 * Deliberately omitting default: to generate compiler warnings
	 * when a new drm_plane_type gets added.
	 */
	}

	return "unknown";
}

static const char *plane_rotation(unsigned int rotation)
{
	static char buf[48];
	/*
	 * According to doc only one DRM_ROTATE_ is allowed but this
	 * will print them all to visualize if the values are misused
	 */
	snprintf(buf, sizeof(buf),
		 "%s%s%s%s%s%s(0x%08x)",
		 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
		 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
		 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
		 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
		 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
		 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
		 rotation);

	return buf;
}

static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct intel_plane *intel_plane;

	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
		struct drm_plane_state *state;
		struct drm_plane *plane = &intel_plane->base;

		if (!plane->state) {
			seq_puts(m, "plane->state is NULL!\n");
			continue;
		}

		state = plane->state;

		seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
			   plane->base.id,
			   plane_type(intel_plane->base.type),
			   state->crtc_x, state->crtc_y,
			   state->crtc_w, state->crtc_h,
			   (state->src_x >> 16),
			   ((state->src_x & 0xffff) * 15625) >> 10,
			   (state->src_y >> 16),
			   ((state->src_y & 0xffff) * 15625) >> 10,
			   (state->src_w >> 16),
			   ((state->src_w & 0xffff) * 15625) >> 10,
			   (state->src_h >> 16),
			   ((state->src_h & 0xffff) * 15625) >> 10,
			   state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
			   plane_rotation(state->rotation));
	}
}

static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
	struct intel_crtc_state *pipe_config;
	int num_scalers = intel_crtc->num_scalers;
	int i;

	pipe_config = to_intel_crtc_state(intel_crtc->base.state);

	/* Not all platformas have a scaler */
	if (num_scalers) {
		seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
			   num_scalers,
			   pipe_config->scaler_state.scaler_users,
			   pipe_config->scaler_state.scaler_id);

		for (i = 0; i < SKL_NUM_SCALERS; i++) {
			struct intel_scaler *sc =
					&pipe_config->scaler_state.scalers[i];

			seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
				   i, yesno(sc->in_use), sc->mode);
		}
		seq_puts(m, "\n");
	} else {
		seq_puts(m, "\tNo scalers available on this platform\n");
	}
}

3134 3135
static int i915_display_info(struct seq_file *m, void *unused)
{
3136
	struct drm_info_node *node = m->private;
3137
	struct drm_device *dev = node->minor->dev;
3138
	struct drm_i915_private *dev_priv = dev->dev_private;
3139
	struct intel_crtc *crtc;
3140 3141
	struct drm_connector *connector;

3142
	intel_runtime_pm_get(dev_priv);
3143 3144 3145
	drm_modeset_lock_all(dev);
	seq_printf(m, "CRTC info\n");
	seq_printf(m, "---------\n");
3146
	for_each_intel_crtc(dev, crtc) {
3147
		bool active;
3148
		struct intel_crtc_state *pipe_config;
3149
		int x, y;
3150

3151 3152
		pipe_config = to_intel_crtc_state(crtc->base.state);

3153
		seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3154
			   crtc->base.base.id, pipe_name(crtc->pipe),
3155
			   yesno(pipe_config->base.active),
3156 3157 3158
			   pipe_config->pipe_src_w, pipe_config->pipe_src_h,
			   yesno(pipe_config->dither), pipe_config->pipe_bpp);

3159
		if (pipe_config->base.active) {
3160 3161
			intel_crtc_info(m, crtc);

3162
			active = cursor_position(dev, crtc->pipe, &x, &y);
3163
			seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3164
				   yesno(crtc->cursor_base),
3165 3166
				   x, y, crtc->base.cursor->state->crtc_w,
				   crtc->base.cursor->state->crtc_h,
3167
				   crtc->cursor_addr, yesno(active));
3168 3169
			intel_scaler_info(m, crtc);
			intel_plane_info(m, crtc);
3170
		}
3171 3172 3173 3174

		seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
			   yesno(!crtc->cpu_fifo_underrun_disabled),
			   yesno(!crtc->pch_fifo_underrun_disabled));
3175 3176 3177 3178 3179 3180 3181 3182 3183
	}

	seq_printf(m, "\n");
	seq_printf(m, "Connector info\n");
	seq_printf(m, "--------------\n");
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		intel_connector_info(m, connector);
	}
	drm_modeset_unlock_all(dev);
3184
	intel_runtime_pm_put(dev_priv);
3185 3186 3187 3188

	return 0;
}

B
Ben Widawsky 已提交
3189 3190 3191 3192 3193
static int i915_semaphore_status(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
3194
	struct intel_engine_cs *engine;
B
Ben Widawsky 已提交
3195
	int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3196 3197
	enum intel_engine_id id;
	int j, ret;
B
Ben Widawsky 已提交
3198

3199
	if (!i915_semaphore_is_enabled(dev_priv)) {
B
Ben Widawsky 已提交
3200 3201 3202 3203 3204 3205 3206
		seq_puts(m, "Semaphores are disabled\n");
		return 0;
	}

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
3207
	intel_runtime_pm_get(dev_priv);
B
Ben Widawsky 已提交
3208 3209 3210 3211 3212 3213 3214 3215

	if (IS_BROADWELL(dev)) {
		struct page *page;
		uint64_t *seqno;

		page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);

		seqno = (uint64_t *)kmap_atomic(page);
3216
		for_each_engine_id(engine, dev_priv, id) {
B
Ben Widawsky 已提交
3217 3218
			uint64_t offset;

3219
			seq_printf(m, "%s\n", engine->name);
B
Ben Widawsky 已提交
3220 3221 3222

			seq_puts(m, "  Last signal:");
			for (j = 0; j < num_rings; j++) {
3223
				offset = id * I915_NUM_ENGINES + j;
B
Ben Widawsky 已提交
3224 3225 3226 3227 3228 3229 3230
				seq_printf(m, "0x%08llx (0x%02llx) ",
					   seqno[offset], offset * 8);
			}
			seq_putc(m, '\n');

			seq_puts(m, "  Last wait:  ");
			for (j = 0; j < num_rings; j++) {
3231
				offset = id + (j * I915_NUM_ENGINES);
B
Ben Widawsky 已提交
3232 3233 3234 3235 3236 3237 3238 3239 3240
				seq_printf(m, "0x%08llx (0x%02llx) ",
					   seqno[offset], offset * 8);
			}
			seq_putc(m, '\n');

		}
		kunmap_atomic(seqno);
	} else {
		seq_puts(m, "  Last signal:");
3241
		for_each_engine(engine, dev_priv)
B
Ben Widawsky 已提交
3242 3243
			for (j = 0; j < num_rings; j++)
				seq_printf(m, "0x%08x\n",
3244
					   I915_READ(engine->semaphore.mbox.signal[j]));
B
Ben Widawsky 已提交
3245 3246 3247 3248
		seq_putc(m, '\n');
	}

	seq_puts(m, "\nSync seqno:\n");
3249 3250
	for_each_engine(engine, dev_priv) {
		for (j = 0; j < num_rings; j++)
3251 3252
			seq_printf(m, "  0x%08x ",
				   engine->semaphore.sync_seqno[j]);
B
Ben Widawsky 已提交
3253 3254 3255 3256
		seq_putc(m, '\n');
	}
	seq_putc(m, '\n');

3257
	intel_runtime_pm_put(dev_priv);
B
Ben Widawsky 已提交
3258 3259 3260 3261
	mutex_unlock(&dev->struct_mutex);
	return 0;
}

3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273
static int i915_shared_dplls_info(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	drm_modeset_lock_all(dev);
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];

		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3274 3275
		seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
			   pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3276
		seq_printf(m, " tracked hardware state:\n");
3277 3278 3279 3280 3281 3282
		seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
		seq_printf(m, " dpll_md: 0x%08x\n",
			   pll->config.hw_state.dpll_md);
		seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
		seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
		seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3283 3284 3285 3286 3287 3288
	}
	drm_modeset_unlock_all(dev);

	return 0;
}

3289
static int i915_wa_registers(struct seq_file *m, void *unused)
3290 3291 3292
{
	int i;
	int ret;
3293
	struct intel_engine_cs *engine;
3294 3295 3296
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
3297
	struct i915_workarounds *workarounds = &dev_priv->workarounds;
3298
	enum intel_engine_id id;
3299 3300 3301 3302 3303 3304 3305

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	intel_runtime_pm_get(dev_priv);

3306
	seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3307
	for_each_engine_id(engine, dev_priv, id)
3308
		seq_printf(m, "HW whitelist count for %s: %d\n",
3309
			   engine->name, workarounds->hw_whitelist_count[id]);
3310
	for (i = 0; i < workarounds->count; ++i) {
3311 3312
		i915_reg_t addr;
		u32 mask, value, read;
3313
		bool ok;
3314

3315 3316 3317
		addr = workarounds->reg[i].addr;
		mask = workarounds->reg[i].mask;
		value = workarounds->reg[i].value;
3318 3319 3320
		read = I915_READ(addr);
		ok = (value & mask) == (read & mask);
		seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3321
			   i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3322 3323 3324 3325 3326 3327 3328 3329
	}

	intel_runtime_pm_put(dev_priv);
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

3330 3331 3332 3333 3334 3335 3336 3337 3338 3339
static int i915_ddb_info(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct skl_ddb_allocation *ddb;
	struct skl_ddb_entry *entry;
	enum pipe pipe;
	int plane;

3340 3341 3342
	if (INTEL_INFO(dev)->gen < 9)
		return 0;

3343 3344 3345 3346 3347 3348 3349 3350 3351
	drm_modeset_lock_all(dev);

	ddb = &dev_priv->wm.skl_hw.ddb;

	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");

	for_each_pipe(dev_priv, pipe) {
		seq_printf(m, "Pipe %c\n", pipe_name(pipe));

3352
		for_each_plane(dev_priv, pipe, plane) {
3353 3354 3355 3356 3357 3358
			entry = &ddb->plane[pipe][plane];
			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
				   entry->start, entry->end,
				   skl_ddb_entry_size(entry));
		}

3359
		entry = &ddb->plane[pipe][PLANE_CURSOR];
3360 3361 3362 3363 3364 3365 3366 3367 3368
		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
			   entry->end, skl_ddb_entry_size(entry));
	}

	drm_modeset_unlock_all(dev);

	return 0;
}

3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409
static void drrs_status_per_crtc(struct seq_file *m,
		struct drm_device *dev, struct intel_crtc *intel_crtc)
{
	struct intel_encoder *intel_encoder;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_drrs *drrs = &dev_priv->drrs;
	int vrefresh = 0;

	for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
		/* Encoder connected on this CRTC */
		switch (intel_encoder->type) {
		case INTEL_OUTPUT_EDP:
			seq_puts(m, "eDP:\n");
			break;
		case INTEL_OUTPUT_DSI:
			seq_puts(m, "DSI:\n");
			break;
		case INTEL_OUTPUT_HDMI:
			seq_puts(m, "HDMI:\n");
			break;
		case INTEL_OUTPUT_DISPLAYPORT:
			seq_puts(m, "DP:\n");
			break;
		default:
			seq_printf(m, "Other encoder (id=%d).\n",
						intel_encoder->type);
			return;
		}
	}

	if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
		seq_puts(m, "\tVBT: DRRS_type: Static");
	else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
		seq_puts(m, "\tVBT: DRRS_type: Seamless");
	else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
		seq_puts(m, "\tVBT: DRRS_type: None");
	else
		seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");

	seq_puts(m, "\n\n");

3410
	if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461
		struct intel_panel *panel;

		mutex_lock(&drrs->mutex);
		/* DRRS Supported */
		seq_puts(m, "\tDRRS Supported: Yes\n");

		/* disable_drrs() will make drrs->dp NULL */
		if (!drrs->dp) {
			seq_puts(m, "Idleness DRRS: Disabled");
			mutex_unlock(&drrs->mutex);
			return;
		}

		panel = &drrs->dp->attached_connector->panel;
		seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
					drrs->busy_frontbuffer_bits);

		seq_puts(m, "\n\t\t");
		if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
			seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
			vrefresh = panel->fixed_mode->vrefresh;
		} else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
			seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
			vrefresh = panel->downclock_mode->vrefresh;
		} else {
			seq_printf(m, "DRRS_State: Unknown(%d)\n",
						drrs->refresh_rate_type);
			mutex_unlock(&drrs->mutex);
			return;
		}
		seq_printf(m, "\t\tVrefresh: %d", vrefresh);

		seq_puts(m, "\n\t\t");
		mutex_unlock(&drrs->mutex);
	} else {
		/* DRRS not supported. Print the VBT parameter*/
		seq_puts(m, "\tDRRS Supported : No");
	}
	seq_puts(m, "\n");
}

static int i915_drrs_status(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct intel_crtc *intel_crtc;
	int active_crtc_cnt = 0;

	for_each_intel_crtc(dev, intel_crtc) {
		drm_modeset_lock(&intel_crtc->base.mutex, NULL);

3462
		if (intel_crtc->base.state->active) {
3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477
			active_crtc_cnt++;
			seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);

			drrs_status_per_crtc(m, dev, intel_crtc);
		}

		drm_modeset_unlock(&intel_crtc->base.mutex);
	}

	if (!active_crtc_cnt)
		seq_puts(m, "No active crtc found\n");

	return 0;
}

3478 3479 3480 3481 3482 3483
struct pipe_crc_info {
	const char *name;
	struct drm_device *dev;
	enum pipe pipe;
};

3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498
static int i915_dp_mst_info(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_encoder *encoder;
	struct intel_encoder *intel_encoder;
	struct intel_digital_port *intel_dig_port;
	drm_modeset_lock_all(dev);
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		intel_encoder = to_intel_encoder(encoder);
		if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
			continue;
		intel_dig_port = enc_to_dig_port(encoder);
		if (!intel_dig_port->dp.can_mst)
			continue;
3499 3500
		seq_printf(m, "MST Source Port %c\n",
			   port_name(intel_dig_port->port));
3501 3502 3503 3504 3505 3506
		drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
	}
	drm_modeset_unlock_all(dev);
	return 0;
}

3507 3508
static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
{
3509 3510 3511 3512
	struct pipe_crc_info *info = inode->i_private;
	struct drm_i915_private *dev_priv = info->dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];

3513 3514 3515
	if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
		return -ENODEV;

3516 3517 3518 3519
	spin_lock_irq(&pipe_crc->lock);

	if (pipe_crc->opened) {
		spin_unlock_irq(&pipe_crc->lock);
3520 3521 3522
		return -EBUSY; /* already open */
	}

3523
	pipe_crc->opened = true;
3524 3525
	filep->private_data = inode->i_private;

3526 3527
	spin_unlock_irq(&pipe_crc->lock);

3528 3529 3530 3531 3532
	return 0;
}

static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
{
3533 3534 3535 3536
	struct pipe_crc_info *info = inode->i_private;
	struct drm_i915_private *dev_priv = info->dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];

3537 3538 3539
	spin_lock_irq(&pipe_crc->lock);
	pipe_crc->opened = false;
	spin_unlock_irq(&pipe_crc->lock);
3540

3541 3542 3543 3544 3545 3546 3547 3548 3549
	return 0;
}

/* (6 fields, 8 chars each, space separated (5) + '\n') */
#define PIPE_CRC_LINE_LEN	(6 * 8 + 5 + 1)
/* account for \'0' */
#define PIPE_CRC_BUFFER_LEN	(PIPE_CRC_LINE_LEN + 1)

static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3550
{
3551 3552 3553
	assert_spin_locked(&pipe_crc->lock);
	return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
			INTEL_PIPE_CRC_ENTRIES_NR);
3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564
}

static ssize_t
i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
		   loff_t *pos)
{
	struct pipe_crc_info *info = filep->private_data;
	struct drm_device *dev = info->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
	char buf[PIPE_CRC_BUFFER_LEN];
3565
	int n_entries;
3566 3567 3568 3569 3570 3571 3572 3573 3574 3575
	ssize_t bytes_read;

	/*
	 * Don't allow user space to provide buffers not big enough to hold
	 * a line of data.
	 */
	if (count < PIPE_CRC_LINE_LEN)
		return -EINVAL;

	if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3576
		return 0;
3577 3578

	/* nothing to read */
3579
	spin_lock_irq(&pipe_crc->lock);
3580
	while (pipe_crc_data_count(pipe_crc) == 0) {
3581 3582 3583 3584
		int ret;

		if (filep->f_flags & O_NONBLOCK) {
			spin_unlock_irq(&pipe_crc->lock);
3585
			return -EAGAIN;
3586
		}
3587

3588 3589 3590 3591 3592 3593
		ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
				pipe_crc_data_count(pipe_crc), pipe_crc->lock);
		if (ret) {
			spin_unlock_irq(&pipe_crc->lock);
			return ret;
		}
3594 3595
	}

3596
	/* We now have one or more entries to read */
3597
	n_entries = count / PIPE_CRC_LINE_LEN;
3598

3599
	bytes_read = 0;
3600 3601 3602
	while (n_entries > 0) {
		struct intel_pipe_crc_entry *entry =
			&pipe_crc->entries[pipe_crc->tail];
3603
		int ret;
3604

3605 3606 3607 3608 3609 3610 3611
		if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
			     INTEL_PIPE_CRC_ENTRIES_NR) < 1)
			break;

		BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
		pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);

3612 3613 3614 3615 3616 3617
		bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
				       "%8u %8x %8x %8x %8x %8x\n",
				       entry->frame, entry->crc[0],
				       entry->crc[1], entry->crc[2],
				       entry->crc[3], entry->crc[4]);

3618 3619 3620
		spin_unlock_irq(&pipe_crc->lock);

		ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3621 3622
		if (ret == PIPE_CRC_LINE_LEN)
			return -EFAULT;
3623

3624 3625 3626 3627 3628
		user_buf += PIPE_CRC_LINE_LEN;
		n_entries--;

		spin_lock_irq(&pipe_crc->lock);
	}
3629

3630 3631
	spin_unlock_irq(&pipe_crc->lock);

3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666
	return bytes_read;
}

static const struct file_operations i915_pipe_crc_fops = {
	.owner = THIS_MODULE,
	.open = i915_pipe_crc_open,
	.read = i915_pipe_crc_read,
	.release = i915_pipe_crc_release,
};

static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
	{
		.name = "i915_pipe_A_crc",
		.pipe = PIPE_A,
	},
	{
		.name = "i915_pipe_B_crc",
		.pipe = PIPE_B,
	},
	{
		.name = "i915_pipe_C_crc",
		.pipe = PIPE_C,
	},
};

static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
				enum pipe pipe)
{
	struct drm_device *dev = minor->dev;
	struct dentry *ent;
	struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];

	info->dev = dev;
	ent = debugfs_create_file(info->name, S_IRUGO, root, info,
				  &i915_pipe_crc_fops);
3667 3668
	if (!ent)
		return -ENOMEM;
3669 3670

	return drm_add_fake_info_node(minor, ent, info);
3671 3672
}

D
Daniel Vetter 已提交
3673
static const char * const pipe_crc_sources[] = {
3674 3675 3676 3677
	"none",
	"plane1",
	"plane2",
	"pf",
3678
	"pipe",
D
Daniel Vetter 已提交
3679 3680 3681 3682
	"TV",
	"DP-B",
	"DP-C",
	"DP-D",
3683
	"auto",
3684 3685 3686 3687 3688 3689 3690 3691
};

static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
{
	BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
	return pipe_crc_sources[source];
}

3692
static int display_crc_ctl_show(struct seq_file *m, void *data)
3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704
{
	struct drm_device *dev = m->private;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	for (i = 0; i < I915_MAX_PIPES; i++)
		seq_printf(m, "%c %s\n", pipe_name(i),
			   pipe_crc_source_name(dev_priv->pipe_crc[i].source));

	return 0;
}

3705
static int display_crc_ctl_open(struct inode *inode, struct file *file)
3706 3707 3708
{
	struct drm_device *dev = inode->i_private;

3709
	return single_open(file, display_crc_ctl_show, dev);
3710 3711
}

3712
static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
D
Daniel Vetter 已提交
3713 3714
				 uint32_t *val)
{
3715 3716 3717 3718
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PIPE;

	switch (*source) {
D
Daniel Vetter 已提交
3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
		break;
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

3732 3733 3734 3735 3736
static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
				     enum intel_pipe_crc_source *source)
{
	struct intel_encoder *encoder;
	struct intel_crtc *crtc;
3737
	struct intel_digital_port *dig_port;
3738 3739 3740 3741
	int ret = 0;

	*source = INTEL_PIPE_CRC_SOURCE_PIPE;

3742
	drm_modeset_lock_all(dev);
3743
	for_each_intel_encoder(dev, encoder) {
3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757
		if (!encoder->base.crtc)
			continue;

		crtc = to_intel_crtc(encoder->base.crtc);

		if (crtc->pipe != pipe)
			continue;

		switch (encoder->type) {
		case INTEL_OUTPUT_TVOUT:
			*source = INTEL_PIPE_CRC_SOURCE_TV;
			break;
		case INTEL_OUTPUT_DISPLAYPORT:
		case INTEL_OUTPUT_EDP:
3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773
			dig_port = enc_to_dig_port(&encoder->base);
			switch (dig_port->port) {
			case PORT_B:
				*source = INTEL_PIPE_CRC_SOURCE_DP_B;
				break;
			case PORT_C:
				*source = INTEL_PIPE_CRC_SOURCE_DP_C;
				break;
			case PORT_D:
				*source = INTEL_PIPE_CRC_SOURCE_DP_D;
				break;
			default:
				WARN(1, "nonexisting DP port %c\n",
				     port_name(dig_port->port));
				break;
			}
3774
			break;
3775 3776
		default:
			break;
3777 3778
		}
	}
3779
	drm_modeset_unlock_all(dev);
3780 3781 3782 3783 3784 3785 3786

	return ret;
}

static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
				enum pipe pipe,
				enum intel_pipe_crc_source *source,
D
Daniel Vetter 已提交
3787 3788
				uint32_t *val)
{
3789 3790 3791
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool need_stable_symbols = false;

3792 3793 3794 3795 3796 3797 3798
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
		int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
		if (ret)
			return ret;
	}

	switch (*source) {
D
Daniel Vetter 已提交
3799 3800 3801 3802 3803
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_B:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3804
		need_stable_symbols = true;
D
Daniel Vetter 已提交
3805 3806 3807
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_C:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3808
		need_stable_symbols = true;
D
Daniel Vetter 已提交
3809
		break;
3810 3811 3812 3813 3814 3815
	case INTEL_PIPE_CRC_SOURCE_DP_D:
		if (!IS_CHERRYVIEW(dev))
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
		need_stable_symbols = true;
		break;
D
Daniel Vetter 已提交
3816 3817 3818 3819 3820 3821 3822
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835
	/*
	 * When the pipe CRC tap point is after the transcoders we need
	 * to tweak symbol-level features to produce a deterministic series of
	 * symbols for a given frame. We need to reset those features only once
	 * a frame (instead of every nth symbol):
	 *   - DC-balance: used to ensure a better clock recovery from the data
	 *     link (SDVO)
	 *   - DisplayPort scrambling: used for EMI reduction
	 */
	if (need_stable_symbols) {
		uint32_t tmp = I915_READ(PORT_DFT2_G4X);

		tmp |= DC_BALANCE_RESET_VLV;
3836 3837
		switch (pipe) {
		case PIPE_A:
3838
			tmp |= PIPE_A_SCRAMBLE_RESET;
3839 3840
			break;
		case PIPE_B:
3841
			tmp |= PIPE_B_SCRAMBLE_RESET;
3842 3843 3844 3845 3846 3847 3848
			break;
		case PIPE_C:
			tmp |= PIPE_C_SCRAMBLE_RESET;
			break;
		default:
			return -EINVAL;
		}
3849 3850 3851
		I915_WRITE(PORT_DFT2_G4X, tmp);
	}

D
Daniel Vetter 已提交
3852 3853 3854
	return 0;
}

3855
static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3856 3857
				 enum pipe pipe,
				 enum intel_pipe_crc_source *source,
3858 3859
				 uint32_t *val)
{
3860 3861 3862
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool need_stable_symbols = false;

3863 3864 3865 3866 3867 3868 3869
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
		int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
		if (ret)
			return ret;
	}

	switch (*source) {
3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
		break;
	case INTEL_PIPE_CRC_SOURCE_TV:
		if (!SUPPORTS_TV(dev))
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_B:
		if (!IS_G4X(dev))
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3882
		need_stable_symbols = true;
3883 3884 3885 3886 3887
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_C:
		if (!IS_G4X(dev))
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3888
		need_stable_symbols = true;
3889 3890 3891 3892 3893
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_D:
		if (!IS_G4X(dev))
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3894
		need_stable_symbols = true;
3895 3896 3897 3898 3899 3900 3901 3902
		break;
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927
	/*
	 * When the pipe CRC tap point is after the transcoders we need
	 * to tweak symbol-level features to produce a deterministic series of
	 * symbols for a given frame. We need to reset those features only once
	 * a frame (instead of every nth symbol):
	 *   - DC-balance: used to ensure a better clock recovery from the data
	 *     link (SDVO)
	 *   - DisplayPort scrambling: used for EMI reduction
	 */
	if (need_stable_symbols) {
		uint32_t tmp = I915_READ(PORT_DFT2_G4X);

		WARN_ON(!IS_G4X(dev));

		I915_WRITE(PORT_DFT_I9XX,
			   I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);

		if (pipe == PIPE_A)
			tmp |= PIPE_A_SCRAMBLE_RESET;
		else
			tmp |= PIPE_B_SCRAMBLE_RESET;

		I915_WRITE(PORT_DFT2_G4X, tmp);
	}

3928 3929 3930
	return 0;
}

3931 3932 3933 3934 3935 3936
static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
					 enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp = I915_READ(PORT_DFT2_G4X);

3937 3938
	switch (pipe) {
	case PIPE_A:
3939
		tmp &= ~PIPE_A_SCRAMBLE_RESET;
3940 3941
		break;
	case PIPE_B:
3942
		tmp &= ~PIPE_B_SCRAMBLE_RESET;
3943 3944 3945 3946 3947 3948 3949
		break;
	case PIPE_C:
		tmp &= ~PIPE_C_SCRAMBLE_RESET;
		break;
	default:
		return;
	}
3950 3951 3952 3953 3954 3955
	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
		tmp &= ~DC_BALANCE_RESET_VLV;
	I915_WRITE(PORT_DFT2_G4X, tmp);

}

3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973
static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
					 enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp = I915_READ(PORT_DFT2_G4X);

	if (pipe == PIPE_A)
		tmp &= ~PIPE_A_SCRAMBLE_RESET;
	else
		tmp &= ~PIPE_B_SCRAMBLE_RESET;
	I915_WRITE(PORT_DFT2_G4X, tmp);

	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
		I915_WRITE(PORT_DFT_I9XX,
			   I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
	}
}

3974
static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3975 3976
				uint32_t *val)
{
3977 3978 3979 3980
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PIPE;

	switch (*source) {
3981 3982 3983 3984 3985 3986 3987 3988 3989
	case INTEL_PIPE_CRC_SOURCE_PLANE1:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
		break;
	case INTEL_PIPE_CRC_SOURCE_PLANE2:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
		break;
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
		break;
D
Daniel Vetter 已提交
3990
	case INTEL_PIPE_CRC_SOURCE_NONE:
3991 3992
		*val = 0;
		break;
D
Daniel Vetter 已提交
3993 3994
	default:
		return -EINVAL;
3995 3996 3997 3998 3999
	}

	return 0;
}

4000
static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
4001 4002 4003 4004
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4005
	struct intel_crtc_state *pipe_config;
4006 4007
	struct drm_atomic_state *state;
	int ret = 0;
4008 4009

	drm_modeset_lock_all(dev);
4010 4011 4012 4013
	state = drm_atomic_state_alloc(dev);
	if (!state) {
		ret = -ENOMEM;
		goto out;
4014 4015
	}

4016 4017 4018 4019 4020 4021
	state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
	pipe_config = intel_atomic_get_crtc_state(state, crtc);
	if (IS_ERR(pipe_config)) {
		ret = PTR_ERR(pipe_config);
		goto out;
	}
4022

4023 4024 4025 4026
	pipe_config->pch_pfit.force_thru = enable;
	if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
	    pipe_config->pch_pfit.enabled != enable)
		pipe_config->base.connectors_changed = true;
4027

4028 4029
	ret = drm_atomic_commit(state);
out:
4030
	drm_modeset_unlock_all(dev);
4031 4032 4033
	WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
	if (ret)
		drm_atomic_state_free(state);
4034 4035 4036 4037 4038
}

static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
				enum pipe pipe,
				enum intel_pipe_crc_source *source,
4039 4040
				uint32_t *val)
{
4041 4042 4043 4044
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PF;

	switch (*source) {
4045 4046 4047 4048 4049 4050 4051
	case INTEL_PIPE_CRC_SOURCE_PLANE1:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
		break;
	case INTEL_PIPE_CRC_SOURCE_PLANE2:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
		break;
	case INTEL_PIPE_CRC_SOURCE_PF:
4052
		if (IS_HASWELL(dev) && pipe == PIPE_A)
4053
			hsw_trans_edp_pipe_A_crc_wa(dev, true);
4054

4055 4056
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
		break;
D
Daniel Vetter 已提交
4057
	case INTEL_PIPE_CRC_SOURCE_NONE:
4058 4059
		*val = 0;
		break;
D
Daniel Vetter 已提交
4060 4061
	default:
		return -EINVAL;
4062 4063 4064 4065 4066
	}

	return 0;
}

4067 4068 4069 4070
static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
			       enum intel_pipe_crc_source source)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4071
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4072 4073
	struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
									pipe));
4074
	enum intel_display_power_domain power_domain;
4075
	u32 val = 0; /* shut up gcc */
4076
	int ret;
4077

4078 4079 4080
	if (pipe_crc->source == source)
		return 0;

4081 4082 4083 4084
	/* forbid changing the source without going back to 'none' */
	if (pipe_crc->source && source)
		return -EINVAL;

4085 4086
	power_domain = POWER_DOMAIN_PIPE(pipe);
	if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4087 4088 4089 4090
		DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
		return -EIO;
	}

D
Daniel Vetter 已提交
4091
	if (IS_GEN2(dev))
4092
		ret = i8xx_pipe_crc_ctl_reg(&source, &val);
D
Daniel Vetter 已提交
4093
	else if (INTEL_INFO(dev)->gen < 5)
4094
		ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4095
	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4096
		ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4097
	else if (IS_GEN5(dev) || IS_GEN6(dev))
4098
		ret = ilk_pipe_crc_ctl_reg(&source, &val);
4099
	else
4100
		ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4101 4102

	if (ret != 0)
4103
		goto out;
4104

4105 4106
	/* none -> real source transition */
	if (source) {
4107 4108
		struct intel_pipe_crc_entry *entries;

4109 4110 4111
		DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
				 pipe_name(pipe), pipe_crc_source_name(source));

4112 4113
		entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
				  sizeof(pipe_crc->entries[0]),
4114
				  GFP_KERNEL);
4115 4116 4117 4118
		if (!entries) {
			ret = -ENOMEM;
			goto out;
		}
4119

4120 4121 4122 4123 4124 4125 4126 4127
		/*
		 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
		 * enabled and disabled dynamically based on package C states,
		 * user space can't make reliable use of the CRCs, so let's just
		 * completely disable it.
		 */
		hsw_disable_ips(crtc);

4128
		spin_lock_irq(&pipe_crc->lock);
4129
		kfree(pipe_crc->entries);
4130
		pipe_crc->entries = entries;
4131 4132 4133
		pipe_crc->head = 0;
		pipe_crc->tail = 0;
		spin_unlock_irq(&pipe_crc->lock);
4134 4135
	}

4136
	pipe_crc->source = source;
4137 4138 4139 4140

	I915_WRITE(PIPE_CRC_CTL(pipe), val);
	POSTING_READ(PIPE_CRC_CTL(pipe));

4141 4142
	/* real source -> none transition */
	if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4143
		struct intel_pipe_crc_entry *entries;
4144 4145
		struct intel_crtc *crtc =
			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4146

4147 4148 4149
		DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
				 pipe_name(pipe));

4150
		drm_modeset_lock(&crtc->base.mutex, NULL);
4151
		if (crtc->base.state->active)
4152 4153
			intel_wait_for_vblank(dev, pipe);
		drm_modeset_unlock(&crtc->base.mutex);
4154

4155 4156
		spin_lock_irq(&pipe_crc->lock);
		entries = pipe_crc->entries;
4157
		pipe_crc->entries = NULL;
4158 4159
		pipe_crc->head = 0;
		pipe_crc->tail = 0;
4160 4161 4162
		spin_unlock_irq(&pipe_crc->lock);

		kfree(entries);
4163 4164 4165

		if (IS_G4X(dev))
			g4x_undo_pipe_scramble_reset(dev, pipe);
4166
		else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4167
			vlv_undo_pipe_scramble_reset(dev, pipe);
4168
		else if (IS_HASWELL(dev) && pipe == PIPE_A)
4169
			hsw_trans_edp_pipe_A_crc_wa(dev, false);
4170 4171

		hsw_enable_ips(crtc);
4172 4173
	}

4174 4175 4176 4177 4178 4179
	ret = 0;

out:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
4180 4181 4182 4183
}

/*
 * Parse pipe CRC command strings:
4184 4185 4186
 *   command: wsp* object wsp+ name wsp+ source wsp*
 *   object: 'pipe'
 *   name: (A | B | C)
4187 4188 4189 4190
 *   source: (none | plane1 | plane2 | pf)
 *   wsp: (#0x20 | #0x9 | #0xA)+
 *
 * eg.:
4191 4192
 *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
 *  "pipe A none"    ->  Stop CRC
4193
 */
4194
static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224
{
	int n_words = 0;

	while (*buf) {
		char *end;

		/* skip leading white space */
		buf = skip_spaces(buf);
		if (!*buf)
			break;	/* end of buffer */

		/* find end of word */
		for (end = buf; *end && !isspace(*end); end++)
			;

		if (n_words == max_words) {
			DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
					 max_words);
			return -EINVAL;	/* ran out of words[] before bytes */
		}

		if (*end)
			*end++ = '\0';
		words[n_words++] = buf;
		buf = end;
	}

	return n_words;
}

4225 4226 4227 4228
enum intel_pipe_crc_object {
	PIPE_CRC_OBJECT_PIPE,
};

D
Daniel Vetter 已提交
4229
static const char * const pipe_crc_objects[] = {
4230 4231 4232 4233
	"pipe",
};

static int
4234
display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4235 4236 4237 4238 4239
{
	int i;

	for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
		if (!strcmp(buf, pipe_crc_objects[i])) {
4240
			*o = i;
4241 4242 4243 4244 4245 4246
			return 0;
		    }

	return -EINVAL;
}

4247
static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259
{
	const char name = buf[0];

	if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
		return -EINVAL;

	*pipe = name - 'A';

	return 0;
}

static int
4260
display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4261 4262 4263 4264 4265
{
	int i;

	for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
		if (!strcmp(buf, pipe_crc_sources[i])) {
4266
			*s = i;
4267 4268 4269 4270 4271 4272
			return 0;
		    }

	return -EINVAL;
}

4273
static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4274
{
4275
#define N_WORDS 3
4276
	int n_words;
4277
	char *words[N_WORDS];
4278
	enum pipe pipe;
4279
	enum intel_pipe_crc_object object;
4280 4281
	enum intel_pipe_crc_source source;

4282
	n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4283 4284 4285 4286 4287 4288
	if (n_words != N_WORDS) {
		DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
				 N_WORDS);
		return -EINVAL;
	}

4289
	if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4290
		DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4291 4292 4293
		return -EINVAL;
	}

4294
	if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4295
		DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4296 4297 4298
		return -EINVAL;
	}

4299
	if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4300
		DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4301 4302 4303 4304 4305 4306
		return -EINVAL;
	}

	return pipe_crc_set_source(dev, pipe, source);
}

4307 4308
static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
				     size_t len, loff_t *offp)
4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333
{
	struct seq_file *m = file->private_data;
	struct drm_device *dev = m->private;
	char *tmpbuf;
	int ret;

	if (len == 0)
		return 0;

	if (len > PAGE_SIZE - 1) {
		DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
				 PAGE_SIZE);
		return -E2BIG;
	}

	tmpbuf = kmalloc(len + 1, GFP_KERNEL);
	if (!tmpbuf)
		return -ENOMEM;

	if (copy_from_user(tmpbuf, ubuf, len)) {
		ret = -EFAULT;
		goto out;
	}
	tmpbuf[len] = '\0';

4334
	ret = display_crc_ctl_parse(dev, tmpbuf, len);
4335 4336 4337 4338 4339 4340 4341 4342 4343 4344

out:
	kfree(tmpbuf);
	if (ret < 0)
		return ret;

	*offp += len;
	return len;
}

4345
static const struct file_operations i915_display_crc_ctl_fops = {
4346
	.owner = THIS_MODULE,
4347
	.open = display_crc_ctl_open,
4348 4349 4350
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
4351
	.write = display_crc_ctl_write
4352 4353
};

4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365
static ssize_t i915_displayport_test_active_write(struct file *file,
					    const char __user *ubuf,
					    size_t len, loff_t *offp)
{
	char *input_buffer;
	int status = 0;
	struct drm_device *dev;
	struct drm_connector *connector;
	struct list_head *connector_list;
	struct intel_dp *intel_dp;
	int val = 0;

4366
	dev = ((struct seq_file *)file->private_data)->private;
4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390

	connector_list = &dev->mode_config.connector_list;

	if (len == 0)
		return 0;

	input_buffer = kmalloc(len + 1, GFP_KERNEL);
	if (!input_buffer)
		return -ENOMEM;

	if (copy_from_user(input_buffer, ubuf, len)) {
		status = -EFAULT;
		goto out;
	}

	input_buffer[len] = '\0';
	DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);

	list_for_each_entry(connector, connector_list, head) {

		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

4391
		if (connector->status == connector_status_connected &&
4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			status = kstrtoint(input_buffer, 10, &val);
			if (status < 0)
				goto out;
			DRM_DEBUG_DRIVER("Got %d for test active\n", val);
			/* To prevent erroneous activation of the compliance
			 * testing code, only accept an actual value of 1 here
			 */
			if (val == 1)
				intel_dp->compliance_test_active = 1;
			else
				intel_dp->compliance_test_active = 0;
		}
	}
out:
	kfree(input_buffer);
	if (status < 0)
		return status;

	*offp += len;
	return len;
}

static int i915_displayport_test_active_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
	struct drm_connector *connector;
	struct list_head *connector_list = &dev->mode_config.connector_list;
	struct intel_dp *intel_dp;

	list_for_each_entry(connector, connector_list, head) {

		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

		if (connector->status == connector_status_connected &&
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			if (intel_dp->compliance_test_active)
				seq_puts(m, "1");
			else
				seq_puts(m, "0");
		} else
			seq_puts(m, "0");
	}

	return 0;
}

static int i915_displayport_test_active_open(struct inode *inode,
				       struct file *file)
{
	struct drm_device *dev = inode->i_private;

	return single_open(file, i915_displayport_test_active_show, dev);
}

static const struct file_operations i915_displayport_test_active_fops = {
	.owner = THIS_MODULE,
	.open = i915_displayport_test_active_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = i915_displayport_test_active_write
};

static int i915_displayport_test_data_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
	struct drm_connector *connector;
	struct list_head *connector_list = &dev->mode_config.connector_list;
	struct intel_dp *intel_dp;

	list_for_each_entry(connector, connector_list, head) {

		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

		if (connector->status == connector_status_connected &&
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			seq_printf(m, "%lx", intel_dp->compliance_test_data);
		} else
			seq_puts(m, "0");
	}

	return 0;
}
static int i915_displayport_test_data_open(struct inode *inode,
				       struct file *file)
{
	struct drm_device *dev = inode->i_private;

	return single_open(file, i915_displayport_test_data_show, dev);
}

static const struct file_operations i915_displayport_test_data_fops = {
	.owner = THIS_MODULE,
	.open = i915_displayport_test_data_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release
};

static int i915_displayport_test_type_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
	struct drm_connector *connector;
	struct list_head *connector_list = &dev->mode_config.connector_list;
	struct intel_dp *intel_dp;

	list_for_each_entry(connector, connector_list, head) {

		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

		if (connector->status == connector_status_connected &&
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			seq_printf(m, "%02lx", intel_dp->compliance_test_type);
		} else
			seq_puts(m, "0");
	}

	return 0;
}

static int i915_displayport_test_type_open(struct inode *inode,
				       struct file *file)
{
	struct drm_device *dev = inode->i_private;

	return single_open(file, i915_displayport_test_type_show, dev);
}

static const struct file_operations i915_displayport_test_type_fops = {
	.owner = THIS_MODULE,
	.open = i915_displayport_test_type_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release
};

4539
static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4540 4541 4542
{
	struct drm_device *dev = m->private;
	int level;
4543 4544 4545 4546 4547 4548 4549 4550
	int num_levels;

	if (IS_CHERRYVIEW(dev))
		num_levels = 3;
	else if (IS_VALLEYVIEW(dev))
		num_levels = 1;
	else
		num_levels = ilk_wm_max_level(dev) + 1;
4551 4552 4553 4554 4555 4556

	drm_modeset_lock_all(dev);

	for (level = 0; level < num_levels; level++) {
		unsigned int latency = wm[level];

4557 4558
		/*
		 * - WM1+ latency values in 0.5us units
4559
		 * - latencies are in us on gen9/vlv/chv
4560
		 */
4561 4562
		if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
		    IS_CHERRYVIEW(dev))
4563 4564
			latency *= 10;
		else if (level > 0)
4565 4566 4567
			latency *= 5;

		seq_printf(m, "WM%d %u (%u.%u usec)\n",
4568
			   level, wm[level], latency / 10, latency % 10);
4569 4570 4571 4572 4573 4574 4575 4576
	}

	drm_modeset_unlock_all(dev);
}

static int pri_wm_latency_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
4577 4578 4579 4580 4581 4582 4583
	struct drm_i915_private *dev_priv = dev->dev_private;
	const uint16_t *latencies;

	if (INTEL_INFO(dev)->gen >= 9)
		latencies = dev_priv->wm.skl_latency;
	else
		latencies = to_i915(dev)->wm.pri_latency;
4584

4585
	wm_latency_show(m, latencies);
4586 4587 4588 4589 4590 4591 4592

	return 0;
}

static int spr_wm_latency_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
4593 4594 4595 4596 4597 4598 4599
	struct drm_i915_private *dev_priv = dev->dev_private;
	const uint16_t *latencies;

	if (INTEL_INFO(dev)->gen >= 9)
		latencies = dev_priv->wm.skl_latency;
	else
		latencies = to_i915(dev)->wm.spr_latency;
4600

4601
	wm_latency_show(m, latencies);
4602 4603 4604 4605 4606 4607 4608

	return 0;
}

static int cur_wm_latency_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
4609 4610 4611 4612 4613 4614 4615
	struct drm_i915_private *dev_priv = dev->dev_private;
	const uint16_t *latencies;

	if (INTEL_INFO(dev)->gen >= 9)
		latencies = dev_priv->wm.skl_latency;
	else
		latencies = to_i915(dev)->wm.cur_latency;
4616

4617
	wm_latency_show(m, latencies);
4618 4619 4620 4621 4622 4623 4624 4625

	return 0;
}

static int pri_wm_latency_open(struct inode *inode, struct file *file)
{
	struct drm_device *dev = inode->i_private;

4626
	if (INTEL_INFO(dev)->gen < 5)
4627 4628 4629 4630 4631 4632 4633 4634 4635
		return -ENODEV;

	return single_open(file, pri_wm_latency_show, dev);
}

static int spr_wm_latency_open(struct inode *inode, struct file *file)
{
	struct drm_device *dev = inode->i_private;

4636
	if (HAS_GMCH_DISPLAY(dev))
4637 4638 4639 4640 4641 4642 4643 4644 4645
		return -ENODEV;

	return single_open(file, spr_wm_latency_show, dev);
}

static int cur_wm_latency_open(struct inode *inode, struct file *file)
{
	struct drm_device *dev = inode->i_private;

4646
	if (HAS_GMCH_DISPLAY(dev))
4647 4648 4649 4650 4651 4652
		return -ENODEV;

	return single_open(file, cur_wm_latency_show, dev);
}

static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4653
				size_t len, loff_t *offp, uint16_t wm[8])
4654 4655 4656
{
	struct seq_file *m = file->private_data;
	struct drm_device *dev = m->private;
4657
	uint16_t new[8] = { 0 };
4658
	int num_levels;
4659 4660 4661 4662
	int level;
	int ret;
	char tmp[32];

4663 4664 4665 4666 4667 4668 4669
	if (IS_CHERRYVIEW(dev))
		num_levels = 3;
	else if (IS_VALLEYVIEW(dev))
		num_levels = 1;
	else
		num_levels = ilk_wm_max_level(dev) + 1;

4670 4671 4672 4673 4674 4675 4676 4677
	if (len >= sizeof(tmp))
		return -EINVAL;

	if (copy_from_user(tmp, ubuf, len))
		return -EFAULT;

	tmp[len] = '\0';

4678 4679 4680
	ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
		     &new[0], &new[1], &new[2], &new[3],
		     &new[4], &new[5], &new[6], &new[7]);
4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699
	if (ret != num_levels)
		return -EINVAL;

	drm_modeset_lock_all(dev);

	for (level = 0; level < num_levels; level++)
		wm[level] = new[level];

	drm_modeset_unlock_all(dev);

	return len;
}


static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
	struct drm_device *dev = m->private;
4700 4701
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint16_t *latencies;
4702

4703 4704 4705 4706 4707 4708
	if (INTEL_INFO(dev)->gen >= 9)
		latencies = dev_priv->wm.skl_latency;
	else
		latencies = to_i915(dev)->wm.pri_latency;

	return wm_latency_write(file, ubuf, len, offp, latencies);
4709 4710 4711 4712 4713 4714 4715
}

static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
	struct drm_device *dev = m->private;
4716 4717
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint16_t *latencies;
4718

4719 4720 4721 4722 4723 4724
	if (INTEL_INFO(dev)->gen >= 9)
		latencies = dev_priv->wm.skl_latency;
	else
		latencies = to_i915(dev)->wm.spr_latency;

	return wm_latency_write(file, ubuf, len, offp, latencies);
4725 4726 4727 4728 4729 4730 4731
}

static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
	struct drm_device *dev = m->private;
4732 4733 4734 4735 4736 4737 4738
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint16_t *latencies;

	if (INTEL_INFO(dev)->gen >= 9)
		latencies = dev_priv->wm.skl_latency;
	else
		latencies = to_i915(dev)->wm.cur_latency;
4739

4740
	return wm_latency_write(file, ubuf, len, offp, latencies);
4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769
}

static const struct file_operations i915_pri_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = pri_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = pri_wm_latency_write
};

static const struct file_operations i915_spr_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = spr_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = spr_wm_latency_write
};

static const struct file_operations i915_cur_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = cur_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = cur_wm_latency_write
};

4770 4771
static int
i915_wedged_get(void *data, u64 *val)
4772
{
4773
	struct drm_device *dev = data;
4774
	struct drm_i915_private *dev_priv = dev->dev_private;
4775

4776
	*val = i915_terminally_wedged(&dev_priv->gpu_error);
4777

4778
	return 0;
4779 4780
}

4781 4782
static int
i915_wedged_set(void *data, u64 val)
4783
{
4784
	struct drm_device *dev = data;
4785 4786
	struct drm_i915_private *dev_priv = dev->dev_private;

4787 4788 4789 4790 4791 4792 4793 4794
	/*
	 * There is no safeguard against this debugfs entry colliding
	 * with the hangcheck calling same i915_handle_error() in
	 * parallel, causing an explosion. For now we assume that the
	 * test harness is responsible enough not to inject gpu hangs
	 * while it is writing to 'i915_wedged'
	 */

4795
	if (i915_reset_in_progress(&dev_priv->gpu_error))
4796 4797
		return -EAGAIN;

4798
	intel_runtime_pm_get(dev_priv);
4799

4800
	i915_handle_error(dev_priv, val,
4801
			  "Manually setting wedged to %llu", val);
4802 4803 4804

	intel_runtime_pm_put(dev_priv);

4805
	return 0;
4806 4807
}

4808 4809
DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
			i915_wedged_get, i915_wedged_set,
4810
			"%llu\n");
4811

4812 4813
static int
i915_ring_stop_get(void *data, u64 *val)
4814
{
4815
	struct drm_device *dev = data;
4816
	struct drm_i915_private *dev_priv = dev->dev_private;
4817

4818
	*val = dev_priv->gpu_error.stop_rings;
4819

4820
	return 0;
4821 4822
}

4823 4824
static int
i915_ring_stop_set(void *data, u64 val)
4825
{
4826
	struct drm_device *dev = data;
4827
	struct drm_i915_private *dev_priv = dev->dev_private;
4828
	int ret;
4829

4830
	DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4831

4832 4833 4834 4835
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

4836
	dev_priv->gpu_error.stop_rings = val;
4837 4838
	mutex_unlock(&dev->struct_mutex);

4839
	return 0;
4840 4841
}

4842 4843 4844
DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
			i915_ring_stop_get, i915_ring_stop_set,
			"0x%08llx\n");
4845

4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911
static int
i915_ring_missed_irq_get(void *data, u64 *val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = dev->dev_private;

	*val = dev_priv->gpu_error.missed_irq_rings;
	return 0;
}

static int
i915_ring_missed_irq_set(void *data, u64 val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	/* Lock against concurrent debugfs callers */
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
	dev_priv->gpu_error.missed_irq_rings = val;
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
			i915_ring_missed_irq_get, i915_ring_missed_irq_set,
			"0x%08llx\n");

static int
i915_ring_test_irq_get(void *data, u64 *val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = dev->dev_private;

	*val = dev_priv->gpu_error.test_irq_rings;

	return 0;
}

static int
i915_ring_test_irq_set(void *data, u64 val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);

	/* Lock against concurrent debugfs callers */
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	dev_priv->gpu_error.test_irq_rings = val;
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
			i915_ring_test_irq_get, i915_ring_test_irq_set,
			"0x%08llx\n");

4912 4913 4914 4915 4916 4917 4918 4919
#define DROP_UNBOUND 0x1
#define DROP_BOUND 0x2
#define DROP_RETIRE 0x4
#define DROP_ACTIVE 0x8
#define DROP_ALL (DROP_UNBOUND | \
		  DROP_BOUND | \
		  DROP_RETIRE | \
		  DROP_ACTIVE)
4920 4921
static int
i915_drop_caches_get(void *data, u64 *val)
4922
{
4923
	*val = DROP_ALL;
4924

4925
	return 0;
4926 4927
}

4928 4929
static int
i915_drop_caches_set(void *data, u64 val)
4930
{
4931
	struct drm_device *dev = data;
4932
	struct drm_i915_private *dev_priv = dev->dev_private;
4933
	int ret;
4934

4935
	DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949

	/* No need to check and wait for gpu resets, only libdrm auto-restarts
	 * on ioctls on -EAGAIN. */
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	if (val & DROP_ACTIVE) {
		ret = i915_gpu_idle(dev);
		if (ret)
			goto unlock;
	}

	if (val & (DROP_RETIRE | DROP_ACTIVE))
4950
		i915_gem_retire_requests(dev_priv);
4951

4952 4953
	if (val & DROP_BOUND)
		i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4954

4955 4956
	if (val & DROP_UNBOUND)
		i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4957 4958 4959 4960

unlock:
	mutex_unlock(&dev->struct_mutex);

4961
	return ret;
4962 4963
}

4964 4965 4966
DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
			i915_drop_caches_get, i915_drop_caches_set,
			"0x%08llx\n");
4967

4968 4969
static int
i915_max_freq_get(void *data, u64 *val)
4970
{
4971
	struct drm_device *dev = data;
4972
	struct drm_i915_private *dev_priv = dev->dev_private;
4973
	int ret;
4974

4975
	if (INTEL_INFO(dev)->gen < 6)
4976 4977
		return -ENODEV;

4978 4979
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

4980
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4981 4982
	if (ret)
		return ret;
4983

4984
	*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4985
	mutex_unlock(&dev_priv->rps.hw_lock);
4986

4987
	return 0;
4988 4989
}

4990 4991
static int
i915_max_freq_set(void *data, u64 val)
4992
{
4993
	struct drm_device *dev = data;
4994
	struct drm_i915_private *dev_priv = dev->dev_private;
4995
	u32 hw_max, hw_min;
4996
	int ret;
4997

4998
	if (INTEL_INFO(dev)->gen < 6)
4999
		return -ENODEV;
5000

5001 5002
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

5003
	DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
5004

5005
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5006 5007 5008
	if (ret)
		return ret;

5009 5010 5011
	/*
	 * Turbo will still be enabled, but won't go above the set value.
	 */
5012
	val = intel_freq_opcode(dev_priv, val);
J
Jeff McGee 已提交
5013

5014 5015
	hw_max = dev_priv->rps.max_freq;
	hw_min = dev_priv->rps.min_freq;
J
Jeff McGee 已提交
5016

5017
	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
J
Jeff McGee 已提交
5018 5019
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
5020 5021
	}

5022
	dev_priv->rps.max_freq_softlimit = val;
J
Jeff McGee 已提交
5023

5024
	intel_set_rps(dev_priv, val);
J
Jeff McGee 已提交
5025

5026
	mutex_unlock(&dev_priv->rps.hw_lock);
5027

5028
	return 0;
5029 5030
}

5031 5032
DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
			i915_max_freq_get, i915_max_freq_set,
5033
			"%llu\n");
5034

5035 5036
static int
i915_min_freq_get(void *data, u64 *val)
5037
{
5038
	struct drm_device *dev = data;
5039
	struct drm_i915_private *dev_priv = dev->dev_private;
5040
	int ret;
5041

5042
	if (INTEL_INFO(dev)->gen < 6)
5043 5044
		return -ENODEV;

5045 5046
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

5047
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5048 5049
	if (ret)
		return ret;
5050

5051
	*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5052
	mutex_unlock(&dev_priv->rps.hw_lock);
5053

5054
	return 0;
5055 5056
}

5057 5058
static int
i915_min_freq_set(void *data, u64 val)
5059
{
5060
	struct drm_device *dev = data;
5061
	struct drm_i915_private *dev_priv = dev->dev_private;
5062
	u32 hw_max, hw_min;
5063
	int ret;
5064

5065
	if (INTEL_INFO(dev)->gen < 6)
5066
		return -ENODEV;
5067

5068 5069
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

5070
	DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5071

5072
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5073 5074 5075
	if (ret)
		return ret;

5076 5077 5078
	/*
	 * Turbo will still be enabled, but won't go below the set value.
	 */
5079
	val = intel_freq_opcode(dev_priv, val);
J
Jeff McGee 已提交
5080

5081 5082
	hw_max = dev_priv->rps.max_freq;
	hw_min = dev_priv->rps.min_freq;
J
Jeff McGee 已提交
5083

5084
	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
J
Jeff McGee 已提交
5085 5086
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
5087
	}
J
Jeff McGee 已提交
5088

5089
	dev_priv->rps.min_freq_softlimit = val;
J
Jeff McGee 已提交
5090

5091
	intel_set_rps(dev_priv, val);
J
Jeff McGee 已提交
5092

5093
	mutex_unlock(&dev_priv->rps.hw_lock);
5094

5095
	return 0;
5096 5097
}

5098 5099
DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
			i915_min_freq_get, i915_min_freq_set,
5100
			"%llu\n");
5101

5102 5103
static int
i915_cache_sharing_get(void *data, u64 *val)
5104
{
5105
	struct drm_device *dev = data;
5106
	struct drm_i915_private *dev_priv = dev->dev_private;
5107
	u32 snpcr;
5108
	int ret;
5109

5110 5111 5112
	if (!(IS_GEN6(dev) || IS_GEN7(dev)))
		return -ENODEV;

5113 5114 5115
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
5116
	intel_runtime_pm_get(dev_priv);
5117

5118
	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5119 5120

	intel_runtime_pm_put(dev_priv);
5121 5122
	mutex_unlock(&dev_priv->dev->struct_mutex);

5123
	*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5124

5125
	return 0;
5126 5127
}

5128 5129
static int
i915_cache_sharing_set(void *data, u64 val)
5130
{
5131
	struct drm_device *dev = data;
5132 5133 5134
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 snpcr;

5135 5136 5137
	if (!(IS_GEN6(dev) || IS_GEN7(dev)))
		return -ENODEV;

5138
	if (val > 3)
5139 5140
		return -EINVAL;

5141
	intel_runtime_pm_get(dev_priv);
5142
	DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5143 5144 5145 5146 5147 5148 5149

	/* Update the cache sharing policy here as well */
	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
	snpcr &= ~GEN6_MBC_SNPCR_MASK;
	snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);

5150
	intel_runtime_pm_put(dev_priv);
5151
	return 0;
5152 5153
}

5154 5155 5156
DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
			i915_cache_sharing_get, i915_cache_sharing_set,
			"%llu\n");
5157

5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169
struct sseu_dev_status {
	unsigned int slice_total;
	unsigned int subslice_total;
	unsigned int subslice_per_slice;
	unsigned int eu_total;
	unsigned int eu_per_subslice;
};

static void cherryview_sseu_device_status(struct drm_device *dev,
					  struct sseu_dev_status *stat)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5170
	int ss_max = 2;
5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201
	int ss;
	u32 sig1[ss_max], sig2[ss_max];

	sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
	sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
	sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
	sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);

	for (ss = 0; ss < ss_max; ss++) {
		unsigned int eu_cnt;

		if (sig1[ss] & CHV_SS_PG_ENABLE)
			/* skip disabled subslice */
			continue;

		stat->slice_total = 1;
		stat->subslice_per_slice++;
		eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
			 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
			 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
			 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
		stat->eu_total += eu_cnt;
		stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
	}
	stat->subslice_total = stat->subslice_per_slice;
}

static void gen9_sseu_device_status(struct drm_device *dev,
				    struct sseu_dev_status *stat)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5202
	int s_max = 3, ss_max = 4;
5203 5204 5205
	int s, ss;
	u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];

5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217
	/* BXT has a single slice and at most 3 subslices. */
	if (IS_BROXTON(dev)) {
		s_max = 1;
		ss_max = 3;
	}

	for (s = 0; s < s_max; s++) {
		s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
		eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
		eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
	}

5218 5219 5220 5221 5222 5223 5224 5225 5226 5227
	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
		     GEN9_PGCTL_SSA_EU19_ACK |
		     GEN9_PGCTL_SSA_EU210_ACK |
		     GEN9_PGCTL_SSA_EU311_ACK;
	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
		     GEN9_PGCTL_SSB_EU19_ACK |
		     GEN9_PGCTL_SSB_EU210_ACK |
		     GEN9_PGCTL_SSB_EU311_ACK;

	for (s = 0; s < s_max; s++) {
5228 5229
		unsigned int ss_cnt = 0;

5230 5231 5232 5233 5234
		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
			/* skip disabled slice */
			continue;

		stat->slice_total++;
5235

5236
		if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5237 5238
			ss_cnt = INTEL_INFO(dev)->subslice_per_slice;

5239 5240 5241
		for (ss = 0; ss < ss_max; ss++) {
			unsigned int eu_cnt;

5242 5243 5244 5245 5246 5247 5248 5249
			if (IS_BROXTON(dev) &&
			    !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
				/* skip disabled subslice */
				continue;

			if (IS_BROXTON(dev))
				ss_cnt++;

5250 5251 5252 5253 5254 5255
			eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
					       eu_mask[ss%2]);
			stat->eu_total += eu_cnt;
			stat->eu_per_subslice = max(stat->eu_per_subslice,
						    eu_cnt);
		}
5256 5257 5258 5259

		stat->subslice_total += ss_cnt;
		stat->subslice_per_slice = max(stat->subslice_per_slice,
					       ss_cnt);
5260 5261 5262
	}
}

5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273 5274 5275 5276 5277 5278 5279 5280 5281 5282 5283 5284 5285 5286 5287
static void broadwell_sseu_device_status(struct drm_device *dev,
					 struct sseu_dev_status *stat)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int s;
	u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);

	stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);

	if (stat->slice_total) {
		stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
		stat->subslice_total = stat->slice_total *
				       stat->subslice_per_slice;
		stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
		stat->eu_total = stat->eu_per_subslice * stat->subslice_total;

		/* subtract fused off EU(s) from enabled slice(s) */
		for (s = 0; s < stat->slice_total; s++) {
			u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];

			stat->eu_total -= hweight8(subslice_7eu);
		}
	}
}

5288 5289 5290 5291
static int i915_sseu_status(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
5292
	struct sseu_dev_status stat;
5293

5294
	if (INTEL_INFO(dev)->gen < 8)
5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314
		return -ENODEV;

	seq_puts(m, "SSEU Device Info\n");
	seq_printf(m, "  Available Slice Total: %u\n",
		   INTEL_INFO(dev)->slice_total);
	seq_printf(m, "  Available Subslice Total: %u\n",
		   INTEL_INFO(dev)->subslice_total);
	seq_printf(m, "  Available Subslice Per Slice: %u\n",
		   INTEL_INFO(dev)->subslice_per_slice);
	seq_printf(m, "  Available EU Total: %u\n",
		   INTEL_INFO(dev)->eu_total);
	seq_printf(m, "  Available EU Per Subslice: %u\n",
		   INTEL_INFO(dev)->eu_per_subslice);
	seq_printf(m, "  Has Slice Power Gating: %s\n",
		   yesno(INTEL_INFO(dev)->has_slice_pg));
	seq_printf(m, "  Has Subslice Power Gating: %s\n",
		   yesno(INTEL_INFO(dev)->has_subslice_pg));
	seq_printf(m, "  Has EU Power Gating: %s\n",
		   yesno(INTEL_INFO(dev)->has_eu_pg));

5315
	seq_puts(m, "SSEU Device Status\n");
5316
	memset(&stat, 0, sizeof(stat));
5317
	if (IS_CHERRYVIEW(dev)) {
5318
		cherryview_sseu_device_status(dev, &stat);
5319 5320
	} else if (IS_BROADWELL(dev)) {
		broadwell_sseu_device_status(dev, &stat);
5321
	} else if (INTEL_INFO(dev)->gen >= 9) {
5322
		gen9_sseu_device_status(dev, &stat);
5323
	}
5324 5325 5326 5327 5328 5329 5330 5331 5332 5333
	seq_printf(m, "  Enabled Slice Total: %u\n",
		   stat.slice_total);
	seq_printf(m, "  Enabled Subslice Total: %u\n",
		   stat.subslice_total);
	seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
		   stat.subslice_per_slice);
	seq_printf(m, "  Enabled EU Total: %u\n",
		   stat.eu_total);
	seq_printf(m, "  Enabled EU Per Subslice: %u\n",
		   stat.eu_per_subslice);
5334

5335 5336 5337
	return 0;
}

5338 5339 5340 5341 5342
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
	struct drm_device *dev = inode->i_private;
	struct drm_i915_private *dev_priv = dev->dev_private;

5343
	if (INTEL_INFO(dev)->gen < 6)
5344 5345
		return 0;

5346
	intel_runtime_pm_get(dev_priv);
5347
	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5348 5349 5350 5351

	return 0;
}

5352
static int i915_forcewake_release(struct inode *inode, struct file *file)
5353 5354 5355 5356
{
	struct drm_device *dev = inode->i_private;
	struct drm_i915_private *dev_priv = dev->dev_private;

5357
	if (INTEL_INFO(dev)->gen < 6)
5358 5359
		return 0;

5360
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5361
	intel_runtime_pm_put(dev_priv);
5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377

	return 0;
}

static const struct file_operations i915_forcewake_fops = {
	.owner = THIS_MODULE,
	.open = i915_forcewake_open,
	.release = i915_forcewake_release,
};

static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
{
	struct drm_device *dev = minor->dev;
	struct dentry *ent;

	ent = debugfs_create_file("i915_forcewake_user",
B
Ben Widawsky 已提交
5378
				  S_IRUSR,
5379 5380
				  root, dev,
				  &i915_forcewake_fops);
5381 5382
	if (!ent)
		return -ENOMEM;
5383

B
Ben Widawsky 已提交
5384
	return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5385 5386
}

5387 5388 5389 5390
static int i915_debugfs_create(struct dentry *root,
			       struct drm_minor *minor,
			       const char *name,
			       const struct file_operations *fops)
5391 5392 5393 5394
{
	struct drm_device *dev = minor->dev;
	struct dentry *ent;

5395
	ent = debugfs_create_file(name,
5396 5397
				  S_IRUGO | S_IWUSR,
				  root, dev,
5398
				  fops);
5399 5400
	if (!ent)
		return -ENOMEM;
5401

5402
	return drm_add_fake_info_node(minor, ent, fops);
5403 5404
}

5405
static const struct drm_info_list i915_debugfs_list[] = {
C
Chris Wilson 已提交
5406
	{"i915_capabilities", i915_capabilities, 0},
5407
	{"i915_gem_objects", i915_gem_object_info, 0},
5408
	{"i915_gem_gtt", i915_gem_gtt_info, 0},
5409
	{"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5410 5411
	{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
	{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5412
	{"i915_gem_stolen", i915_gem_stolen_list_info },
5413
	{"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5414 5415
	{"i915_gem_request", i915_gem_request_info, 0},
	{"i915_gem_seqno", i915_gem_seqno_info, 0},
5416
	{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5417
	{"i915_gem_interrupt", i915_interrupt_info, 0},
5418 5419 5420
	{"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
	{"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
	{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
X
Xiang, Haihao 已提交
5421
	{"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5422
	{"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5423
	{"i915_guc_info", i915_guc_info, 0},
5424
	{"i915_guc_load_status", i915_guc_load_status_info, 0},
A
Alex Dai 已提交
5425
	{"i915_guc_log_dump", i915_guc_log_dump, 0},
5426
	{"i915_frequency_info", i915_frequency_info, 0},
5427
	{"i915_hangcheck_info", i915_hangcheck_info, 0},
5428
	{"i915_drpc_info", i915_drpc_info, 0},
5429
	{"i915_emon_status", i915_emon_status, 0},
5430
	{"i915_ring_freq_table", i915_ring_freq_table, 0},
5431
	{"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5432
	{"i915_fbc_status", i915_fbc_status, 0},
5433
	{"i915_ips_status", i915_ips_status, 0},
5434
	{"i915_sr_status", i915_sr_status, 0},
5435
	{"i915_opregion", i915_opregion, 0},
5436
	{"i915_vbt", i915_vbt, 0},
5437
	{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5438
	{"i915_context_status", i915_context_status, 0},
5439
	{"i915_dump_lrc", i915_dump_lrc, 0},
5440
	{"i915_execlists", i915_execlists, 0},
5441
	{"i915_forcewake_domains", i915_forcewake_domains, 0},
5442
	{"i915_swizzle_info", i915_swizzle_info, 0},
D
Daniel Vetter 已提交
5443
	{"i915_ppgtt_info", i915_ppgtt_info, 0},
5444
	{"i915_llc", i915_llc, 0},
5445
	{"i915_edp_psr_status", i915_edp_psr_status, 0},
5446
	{"i915_sink_crc_eDP1", i915_sink_crc, 0},
5447
	{"i915_energy_uJ", i915_energy_uJ, 0},
5448
	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5449
	{"i915_power_domain_info", i915_power_domain_info, 0},
5450
	{"i915_dmc_info", i915_dmc_info, 0},
5451
	{"i915_display_info", i915_display_info, 0},
B
Ben Widawsky 已提交
5452
	{"i915_semaphore_status", i915_semaphore_status, 0},
5453
	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5454
	{"i915_dp_mst_info", i915_dp_mst_info, 0},
5455
	{"i915_wa_registers", i915_wa_registers, 0},
5456
	{"i915_ddb_info", i915_ddb_info, 0},
5457
	{"i915_sseu_status", i915_sseu_status, 0},
5458
	{"i915_drrs_status", i915_drrs_status, 0},
5459
	{"i915_rps_boost_info", i915_rps_boost_info, 0},
5460
};
5461
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5462

5463
static const struct i915_debugfs_files {
5464 5465 5466 5467 5468 5469 5470 5471
	const char *name;
	const struct file_operations *fops;
} i915_debugfs_files[] = {
	{"i915_wedged", &i915_wedged_fops},
	{"i915_max_freq", &i915_max_freq_fops},
	{"i915_min_freq", &i915_min_freq_fops},
	{"i915_cache_sharing", &i915_cache_sharing_fops},
	{"i915_ring_stop", &i915_ring_stop_fops},
5472 5473
	{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
	{"i915_ring_test_irq", &i915_ring_test_irq_fops},
5474 5475 5476
	{"i915_gem_drop_caches", &i915_drop_caches_fops},
	{"i915_error_state", &i915_error_state_fops},
	{"i915_next_seqno", &i915_next_seqno_fops},
5477
	{"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5478 5479 5480
	{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
	{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
	{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5481
	{"i915_fbc_false_color", &i915_fbc_fc_fops},
5482 5483 5484
	{"i915_dp_test_data", &i915_displayport_test_data_fops},
	{"i915_dp_test_type", &i915_displayport_test_type_fops},
	{"i915_dp_test_active", &i915_displayport_test_active_fops}
5485 5486
};

5487 5488 5489
void intel_display_crc_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5490
	enum pipe pipe;
5491

5492
	for_each_pipe(dev_priv, pipe) {
5493
		struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5494

5495 5496
		pipe_crc->opened = false;
		spin_lock_init(&pipe_crc->lock);
5497 5498 5499 5500
		init_waitqueue_head(&pipe_crc->wq);
	}
}

5501
int i915_debugfs_init(struct drm_minor *minor)
5502
{
5503
	int ret, i;
5504

5505
	ret = i915_forcewake_create(minor->debugfs_root, minor);
5506 5507
	if (ret)
		return ret;
5508

5509 5510 5511 5512 5513 5514
	for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
		ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
		if (ret)
			return ret;
	}

5515 5516 5517 5518 5519 5520 5521
	for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
		ret = i915_debugfs_create(minor->debugfs_root, minor,
					  i915_debugfs_files[i].name,
					  i915_debugfs_files[i].fops);
		if (ret)
			return ret;
	}
5522

5523 5524
	return drm_debugfs_create_files(i915_debugfs_list,
					I915_DEBUGFS_ENTRIES,
5525 5526 5527
					minor->debugfs_root, minor);
}

5528
void i915_debugfs_cleanup(struct drm_minor *minor)
5529
{
5530 5531
	int i;

5532 5533
	drm_debugfs_remove_files(i915_debugfs_list,
				 I915_DEBUGFS_ENTRIES, minor);
5534

5535 5536
	drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
				 1, minor);
5537

D
Daniel Vetter 已提交
5538
	for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5539 5540 5541 5542 5543 5544
		struct drm_info_list *info_list =
			(struct drm_info_list *)&i915_pipe_crc_data[i];

		drm_debugfs_remove_files(info_list, 1, minor);
	}

5545 5546 5547 5548 5549 5550
	for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
		struct drm_info_list *info_list =
			(struct drm_info_list *) i915_debugfs_files[i].fops;

		drm_debugfs_remove_files(info_list, 1, minor);
	}
5551
}
5552 5553 5554 5555 5556 5557 5558 5559 5560 5561 5562 5563 5564 5565 5566 5567 5568 5569 5570 5571 5572 5573 5574 5575 5576 5577 5578 5579 5580 5581 5582 5583 5584 5585

struct dpcd_block {
	/* DPCD dump start address. */
	unsigned int offset;
	/* DPCD dump end address, inclusive. If unset, .size will be used. */
	unsigned int end;
	/* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
	size_t size;
	/* Only valid for eDP. */
	bool edp;
};

static const struct dpcd_block i915_dpcd_debug[] = {
	{ .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
	{ .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
	{ .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
	{ .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
	{ .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
	{ .offset = DP_SET_POWER },
	{ .offset = DP_EDP_DPCD_REV },
	{ .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
	{ .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
	{ .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
};

static int i915_dpcd_show(struct seq_file *m, void *data)
{
	struct drm_connector *connector = m->private;
	struct intel_dp *intel_dp =
		enc_to_intel_dp(&intel_attached_encoder(connector)->base);
	uint8_t buf[16];
	ssize_t err;
	int i;

5586 5587 5588
	if (connector->status != connector_status_connected)
		return -ENODEV;

5589 5590 5591 5592 5593 5594 5595 5596 5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608
	for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
		const struct dpcd_block *b = &i915_dpcd_debug[i];
		size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);

		if (b->edp &&
		    connector->connector_type != DRM_MODE_CONNECTOR_eDP)
			continue;

		/* low tech for now */
		if (WARN_ON(size > sizeof(buf)))
			continue;

		err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
		if (err <= 0) {
			DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
				  size, b->offset, err);
			continue;
		}

		seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5609
	}
5610 5611 5612 5613 5614 5615 5616 5617 5618 5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650

	return 0;
}

static int i915_dpcd_open(struct inode *inode, struct file *file)
{
	return single_open(file, i915_dpcd_show, inode->i_private);
}

static const struct file_operations i915_dpcd_fops = {
	.owner = THIS_MODULE,
	.open = i915_dpcd_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
};

/**
 * i915_debugfs_connector_add - add i915 specific connector debugfs files
 * @connector: pointer to a registered drm_connector
 *
 * Cleanup will be done by drm_connector_unregister() through a call to
 * drm_debugfs_connector_remove().
 *
 * Returns 0 on success, negative error codes on error.
 */
int i915_debugfs_connector_add(struct drm_connector *connector)
{
	struct dentry *root = connector->debugfs_entry;

	/* The connector must have been registered beforehands. */
	if (!root)
		return -ENODEV;

	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
	    connector->connector_type == DRM_MODE_CONNECTOR_eDP)
		debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
				    &i915_dpcd_fops);

	return 0;
}