i7core_edac.c 64.1 KB
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/* Intel i7 core/Nehalem Memory Controller kernel module
 *
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David Sterba 已提交
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 * This driver supports the memory controllers found on the Intel
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 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
 * and Westmere-EP.
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 *
 * This file may be distributed under the terms of the
 * GNU General Public License version 2 only.
 *
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 * Copyright (c) 2009-2010 by:
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 *	 Mauro Carvalho Chehab <mchehab@redhat.com>
 *
 * Red Hat Inc. http://www.redhat.com
 *
 * Forked and adapted from the i5400_edac driver
 *
 * Based on the following public Intel datasheets:
 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
 * Datasheet, Volume 2:
 *	http://download.intel.com/design/processor/datashts/320835.pdf
 * Intel Xeon Processor 5500 Series Datasheet Volume 2
 *	http://www.intel.com/Assets/PDF/datasheet/321322.pdf
 * also available at:
 * 	http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
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Randy Dunlap 已提交
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#include <linux/delay.h>
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Nils Carlson 已提交
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#include <linux/dmi.h>
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#include <linux/edac.h>
#include <linux/mmzone.h>
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#include <linux/smp.h>
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#include <asm/mce.h>
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#include <asm/processor.h>
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#include <asm/div64.h>
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#include "edac_core.h"

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/* Static vars */
static LIST_HEAD(i7core_edac_list);
static DEFINE_MUTEX(i7core_edac_lock);
static int probed;

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static int use_pci_fixup;
module_param(use_pci_fixup, int, 0444);
MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
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/*
 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
 * registers start at bus 255, and are not reported by BIOS.
 * We currently find devices with only 2 sockets. In order to support more QPI
 * Quick Path Interconnect, just increment this number.
 */
#define MAX_SOCKET_BUSES	2


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/*
 * Alter this version for the module when modifications are made
 */
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Michal Marek 已提交
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#define I7CORE_REVISION    " Ver: 1.0.0"
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#define EDAC_MOD_STR      "i7core_edac"

/*
 * Debug macros
 */
#define i7core_printk(level, fmt, arg...)			\
	edac_printk(level, "i7core", fmt, ##arg)

#define i7core_mc_printk(mci, level, fmt, arg...)		\
	edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)

/*
 * i7core Memory Controller Registers
 */

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	/* OFFSETS for Device 0 Function 0 */

#define MC_CFG_CONTROL	0x90
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  #define MC_CFG_UNLOCK		0x02
  #define MC_CFG_LOCK		0x00
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	/* OFFSETS for Device 3 Function 0 */

#define MC_CONTROL	0x48
#define MC_STATUS	0x4c
#define MC_MAX_DOD	0x64

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/*
 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#define MC_TEST_ERR_RCV1	0x60
  #define DIMM2_COR_ERR(r)			((r) & 0x7fff)

#define MC_TEST_ERR_RCV0	0x64
  #define DIMM1_COR_ERR(r)			(((r) >> 16) & 0x7fff)
  #define DIMM0_COR_ERR(r)			((r) & 0x7fff)

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/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
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#define MC_SSRCONTROL		0x48
  #define SSR_MODE_DISABLE	0x00
  #define SSR_MODE_ENABLE	0x01
  #define SSR_MODE_MASK		0x03

#define MC_SCRUB_CONTROL	0x4c
  #define STARTSCRUB		(1 << 24)
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  #define SCRUBINTERVAL_MASK    0xffffff
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#define MC_COR_ECC_CNT_0	0x80
#define MC_COR_ECC_CNT_1	0x84
#define MC_COR_ECC_CNT_2	0x88
#define MC_COR_ECC_CNT_3	0x8c
#define MC_COR_ECC_CNT_4	0x90
#define MC_COR_ECC_CNT_5	0x94

#define DIMM_TOP_COR_ERR(r)			(((r) >> 16) & 0x7fff)
#define DIMM_BOT_COR_ERR(r)			((r) & 0x7fff)


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	/* OFFSETS for Devices 4,5 and 6 Function 0 */

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#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
  #define THREE_DIMMS_PRESENT		(1 << 24)
  #define SINGLE_QUAD_RANK_PRESENT	(1 << 23)
  #define QUAD_RANK_PRESENT		(1 << 22)
  #define REGISTERED_DIMM		(1 << 15)

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#define MC_CHANNEL_MAPPER	0x60
  #define RDLCH(r, ch)		((((r) >> (3 + (ch * 6))) & 0x07) - 1)
  #define WRLCH(r, ch)		((((r) >> (ch * 6)) & 0x07) - 1)

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#define MC_CHANNEL_RANK_PRESENT 0x7c
  #define RANK_PRESENT_MASK		0xffff

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#define MC_CHANNEL_ADDR_MATCH	0xf0
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#define MC_CHANNEL_ERROR_MASK	0xf8
#define MC_CHANNEL_ERROR_INJECT	0xfc
  #define INJECT_ADDR_PARITY	0x10
  #define INJECT_ECC		0x08
  #define MASK_CACHELINE	0x06
  #define MASK_FULL_CACHELINE	0x06
  #define MASK_MSB32_CACHELINE	0x04
  #define MASK_LSB32_CACHELINE	0x02
  #define NO_MASK_CACHELINE	0x00
  #define REPEAT_EN		0x01
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	/* OFFSETS for Devices 4,5 and 6 Function 1 */
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#define MC_DOD_CH_DIMM0		0x48
#define MC_DOD_CH_DIMM1		0x4c
#define MC_DOD_CH_DIMM2		0x50
  #define RANKOFFSET_MASK	((1 << 12) | (1 << 11) | (1 << 10))
  #define RANKOFFSET(x)		((x & RANKOFFSET_MASK) >> 10)
  #define DIMM_PRESENT_MASK	(1 << 9)
  #define DIMM_PRESENT(x)	(((x) & DIMM_PRESENT_MASK) >> 9)
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  #define MC_DOD_NUMBANK_MASK		((1 << 8) | (1 << 7))
  #define MC_DOD_NUMBANK(x)		(((x) & MC_DOD_NUMBANK_MASK) >> 7)
  #define MC_DOD_NUMRANK_MASK		((1 << 6) | (1 << 5))
  #define MC_DOD_NUMRANK(x)		(((x) & MC_DOD_NUMRANK_MASK) >> 5)
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  #define MC_DOD_NUMROW_MASK		((1 << 4) | (1 << 3) | (1 << 2))
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  #define MC_DOD_NUMROW(x)		(((x) & MC_DOD_NUMROW_MASK) >> 2)
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  #define MC_DOD_NUMCOL_MASK		3
  #define MC_DOD_NUMCOL(x)		((x) & MC_DOD_NUMCOL_MASK)
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#define MC_RANK_PRESENT		0x7c

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#define MC_SAG_CH_0	0x80
#define MC_SAG_CH_1	0x84
#define MC_SAG_CH_2	0x88
#define MC_SAG_CH_3	0x8c
#define MC_SAG_CH_4	0x90
#define MC_SAG_CH_5	0x94
#define MC_SAG_CH_6	0x98
#define MC_SAG_CH_7	0x9c

#define MC_RIR_LIMIT_CH_0	0x40
#define MC_RIR_LIMIT_CH_1	0x44
#define MC_RIR_LIMIT_CH_2	0x48
#define MC_RIR_LIMIT_CH_3	0x4C
#define MC_RIR_LIMIT_CH_4	0x50
#define MC_RIR_LIMIT_CH_5	0x54
#define MC_RIR_LIMIT_CH_6	0x58
#define MC_RIR_LIMIT_CH_7	0x5C
#define MC_RIR_LIMIT_MASK	((1 << 10) - 1)

#define MC_RIR_WAY_CH		0x80
  #define MC_RIR_WAY_OFFSET_MASK	(((1 << 14) - 1) & ~0x7)
  #define MC_RIR_WAY_RANK_MASK		0x7

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/*
 * i7core structs
 */

#define NUM_CHANS 3
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#define MAX_DIMMS 3		/* Max DIMMS per channel */
#define MAX_MCR_FUNC  4
#define MAX_CHAN_FUNC 3
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struct i7core_info {
	u32	mc_control;
	u32	mc_status;
	u32	max_dod;
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	u32	ch_map;
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};

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struct i7core_inject {
	int	enable;

	u32	section;
	u32	type;
	u32	eccmask;

	/* Error address mask */
	int channel, dimm, rank, bank, page, col;
};

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struct i7core_channel {
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	u32		ranks;
	u32		dimms;
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};

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struct pci_id_descr {
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	int			dev;
	int			func;
	int 			dev_id;
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	int			optional;
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};

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struct pci_id_table {
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	const struct pci_id_descr	*descr;
	int				n_devs;
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};

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struct i7core_dev {
	struct list_head	list;
	u8			socket;
	struct pci_dev		**pdev;
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	int			n_devs;
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	struct mem_ctl_info	*mci;
};

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struct i7core_pvt {
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	struct pci_dev	*pci_noncore;
	struct pci_dev	*pci_mcr[MAX_MCR_FUNC + 1];
	struct pci_dev	*pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];

	struct i7core_dev *i7core_dev;
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	struct i7core_info	info;
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	struct i7core_inject	inject;
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	struct i7core_channel	channel[NUM_CHANS];
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	int		ce_count_available;
	int 		csrow_map[NUM_CHANS][MAX_DIMMS];
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			/* ECC corrected errors counts per udimm */
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	unsigned long	udimm_ce_count[MAX_DIMMS];
	int		udimm_last_ce_count[MAX_DIMMS];
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			/* ECC corrected errors counts per rdimm */
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	unsigned long	rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
	int		rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
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	bool		is_registered, enable_scrub;
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	/* Fifo double buffers */
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	struct mce		mce_entry[MCE_LOG_LEN];
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	struct mce		mce_outentry[MCE_LOG_LEN];

	/* Fifo in/out counters */
	unsigned		mce_in, mce_out;

	/* Count indicator to show errors not got */
	unsigned		mce_overrun;
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	/* DCLK Frequency used for computing scrub rate */
	int			dclk_freq;

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	/* Struct to control EDAC polling */
	struct edac_pci_ctl_info *i7core_pci;
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};

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#define PCI_DESCR(device, function, device_id)	\
	.dev = (device),			\
	.func = (function),			\
	.dev_id = (device_id)

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static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
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		/* Memory controller */
	{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR)     },
	{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD)  },
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			/* Exists only for RDIMM */
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	{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1  },
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	{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },

		/* Channel 0 */
	{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
	{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
	{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
	{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC)   },

		/* Channel 1 */
	{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
	{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
	{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
	{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC)   },

		/* Channel 2 */
	{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
	{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
	{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
	{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC)   },
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		/* Generic Non-core registers */
	/*
	 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
	 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
	 * the probing code needs to test for the other address in case of
	 * failure of this one
	 */
	{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE)  },

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};
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static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
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	{ PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR)         },
	{ PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD)      },
	{ PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST)     },

	{ PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
	{ PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
	{ PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
	{ PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC)   },

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	{ PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
	{ PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
	{ PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
	{ PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC)   },
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	/*
	 * This is the PCI device has an alternate address on some
	 * processors like Core i7 860
	 */
	{ PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE)     },
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};

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static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
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		/* Memory controller */
	{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2)     },
	{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2)  },
			/* Exists only for RDIMM */
	{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1  },
	{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },

		/* Channel 0 */
	{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
	{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
	{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
	{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2)   },

		/* Channel 1 */
	{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
	{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
	{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
	{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2)   },

		/* Channel 2 */
	{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
	{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
	{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
	{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2)   },
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		/* Generic Non-core registers */
	{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2)  },

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};

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#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
static const struct pci_id_table pci_dev_table[] = {
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	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
	PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
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	{0,}			/* 0 terminated list. */
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};

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/*
 *	pci_device_id	table for which devices we are looking for
 */
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static DEFINE_PCI_DEVICE_TABLE(i7core_pci_tbl) = {
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	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
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	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
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	{0,}			/* 0 terminated list. */
};

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/****************************************************************************
			Anciliary status routines
 ****************************************************************************/

	/* MC_CONTROL bits */
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#define CH_ACTIVE(pvt, ch)	((pvt)->info.mc_control & (1 << (8 + ch)))
#define ECCx8(pvt)		((pvt)->info.mc_control & (1 << 1))
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	/* MC_STATUS bits */
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#define ECC_ENABLED(pvt)	((pvt)->info.mc_status & (1 << 4))
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#define CH_DISABLED(pvt, ch)	((pvt)->info.mc_status & (1 << ch))
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	/* MC_MAX_DOD read functions */
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static inline int numdimms(u32 dimms)
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{
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	return (dimms & 0x3) + 1;
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}

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static inline int numrank(u32 rank)
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{
	static int ranks[4] = { 1, 2, 4, -EINVAL };

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	return ranks[rank & 0x3];
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}

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static inline int numbank(u32 bank)
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{
	static int banks[4] = { 4, 8, 16, -EINVAL };

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	return banks[bank & 0x3];
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}

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static inline int numrow(u32 row)
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{
	static int rows[8] = {
		1 << 12, 1 << 13, 1 << 14, 1 << 15,
		1 << 16, -EINVAL, -EINVAL, -EINVAL,
	};

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	return rows[row & 0x7];
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}

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static inline int numcol(u32 col)
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{
	static int cols[8] = {
		1 << 10, 1 << 11, 1 << 12, -EINVAL,
	};
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	return cols[col & 0x3];
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}

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static struct i7core_dev *get_i7core_dev(u8 socket)
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{
	struct i7core_dev *i7core_dev;

	list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
		if (i7core_dev->socket == socket)
			return i7core_dev;
	}

	return NULL;
}

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static struct i7core_dev *alloc_i7core_dev(u8 socket,
					   const struct pci_id_table *table)
{
	struct i7core_dev *i7core_dev;

	i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
	if (!i7core_dev)
		return NULL;

	i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
				   GFP_KERNEL);
	if (!i7core_dev->pdev) {
		kfree(i7core_dev);
		return NULL;
	}

	i7core_dev->socket = socket;
	i7core_dev->n_devs = table->n_devs;
	list_add_tail(&i7core_dev->list, &i7core_edac_list);

	return i7core_dev;
}

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static void free_i7core_dev(struct i7core_dev *i7core_dev)
{
	list_del(&i7core_dev->list);
	kfree(i7core_dev->pdev);
	kfree(i7core_dev);
}

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/****************************************************************************
			Memory check routines
 ****************************************************************************/
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static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
					  unsigned func)
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{
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	struct i7core_dev *i7core_dev = get_i7core_dev(socket);
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	int i;

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	if (!i7core_dev)
		return NULL;

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	for (i = 0; i < i7core_dev->n_devs; i++) {
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		if (!i7core_dev->pdev[i])
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			continue;

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		if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
		    PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
			return i7core_dev->pdev[i];
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		}
	}

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	return NULL;
}

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/**
 * i7core_get_active_channels() - gets the number of channels and csrows
 * @socket:	Quick Path Interconnect socket
 * @channels:	Number of channels that will be returned
 * @csrows:	Number of csrows found
 *
 * Since EDAC core needs to know in advance the number of available channels
 * and csrows, in order to allocate memory for csrows/channels, it is needed
 * to run two similar steps. At the first step, implemented on this function,
 * it checks the number of csrows/channels present at one socket.
 * this is used in order to properly allocate the size of mci components.
 *
 * It should be noticed that none of the current available datasheets explain
 * or even mention how csrows are seen by the memory controller. So, we need
 * to add a fake description for csrows.
 * So, this driver is attributing one DIMM memory for one csrow.
 */
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static int i7core_get_active_channels(const u8 socket, unsigned *channels,
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				      unsigned *csrows)
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{
	struct pci_dev *pdev = NULL;
	int i, j;
	u32 status, control;

	*channels = 0;
	*csrows = 0;

544
	pdev = get_pdev_slot_func(socket, 3, 0);
545
	if (!pdev) {
546 547
		i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
			      socket);
548
		return -ENODEV;
549
	}
550 551 552 553 554 555

	/* Device 3 function 0 reads */
	pci_read_config_dword(pdev, MC_STATUS, &status);
	pci_read_config_dword(pdev, MC_CONTROL, &control);

	for (i = 0; i < NUM_CHANS; i++) {
556
		u32 dimm_dod[3];
557 558 559 560 561
		/* Check if the channel is active */
		if (!(control & (1 << (8 + i))))
			continue;

		/* Check if the channel is disabled */
562
		if (status & (1 << i))
563 564
			continue;

565
		pdev = get_pdev_slot_func(socket, i + 4, 1);
566
		if (!pdev) {
567 568 569
			i7core_printk(KERN_ERR, "Couldn't find socket %d "
						"fn %d.%d!!!\n",
						socket, i + 4, 1);
570 571 572 573 574 575 576 577 578 579
			return -ENODEV;
		}
		/* Devices 4-6 function 1 */
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM0, &dimm_dod[0]);
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM1, &dimm_dod[1]);
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM2, &dimm_dod[2]);

580
		(*channels)++;
581 582 583 584 585 586

		for (j = 0; j < 3; j++) {
			if (!DIMM_PRESENT(dimm_dod[j]))
				continue;
			(*csrows)++;
		}
587 588
	}

589
	debugf0("Number of active channels on socket %d: %d\n",
590
		socket, *channels);
591

592 593 594
	return 0;
}

595
static int get_dimm_config(struct mem_ctl_info *mci)
596 597
{
	struct i7core_pvt *pvt = mci->pvt_info;
598
	struct csrow_info *csr;
599
	struct pci_dev *pdev;
600
	int i, j;
601
	int csrow = 0;
602
	unsigned long last_page = 0;
603
	enum edac_type mode;
604
	enum mem_type mtype;
605
	struct dimm_info *dimm;
606

607
	/* Get data from the MC register, function 0 */
608
	pdev = pvt->pci_mcr[0];
609
	if (!pdev)
610 611
		return -ENODEV;

612
	/* Device 3 function 0 reads */
613 614 615 616
	pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
	pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
	pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
	pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
617

618
	debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
619
		pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
620
		pvt->info.max_dod, pvt->info.ch_map);
621

622
	if (ECC_ENABLED(pvt)) {
623
		debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
624 625 626 627 628
		if (ECCx8(pvt))
			mode = EDAC_S8ECD8ED;
		else
			mode = EDAC_S4ECD4ED;
	} else {
629
		debugf0("ECC disabled\n");
630 631
		mode = EDAC_NONE;
	}
632 633

	/* FIXME: need to handle the error codes */
634 635
	debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
		"x%x x 0x%x\n",
636 637
		numdimms(pvt->info.max_dod),
		numrank(pvt->info.max_dod >> 2),
638
		numbank(pvt->info.max_dod >> 4),
639 640
		numrow(pvt->info.max_dod >> 6),
		numcol(pvt->info.max_dod >> 9));
641

642
	for (i = 0; i < NUM_CHANS; i++) {
643
		u32 data, dimm_dod[3], value[8];
644

645 646 647
		if (!pvt->pci_ch[i][0])
			continue;

648 649 650 651 652 653 654 655 656
		if (!CH_ACTIVE(pvt, i)) {
			debugf0("Channel %i is not active\n", i);
			continue;
		}
		if (CH_DISABLED(pvt, i)) {
			debugf0("Channel %i is disabled\n", i);
			continue;
		}

657
		/* Devices 4-6 function 0 */
658
		pci_read_config_dword(pvt->pci_ch[i][0],
659 660
				MC_CHANNEL_DIMM_INIT_PARAMS, &data);

661
		pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
662
						4 : 2;
663

664 665
		if (data & REGISTERED_DIMM)
			mtype = MEM_RDDR3;
666
		else
667 668
			mtype = MEM_DDR3;
#if 0
669 670 671 672 673 674
		if (data & THREE_DIMMS_PRESENT)
			pvt->channel[i].dimms = 3;
		else if (data & SINGLE_QUAD_RANK_PRESENT)
			pvt->channel[i].dimms = 1;
		else
			pvt->channel[i].dimms = 2;
675 676 677
#endif

		/* Devices 4-6 function 1 */
678
		pci_read_config_dword(pvt->pci_ch[i][1],
679
				MC_DOD_CH_DIMM0, &dimm_dod[0]);
680
		pci_read_config_dword(pvt->pci_ch[i][1],
681
				MC_DOD_CH_DIMM1, &dimm_dod[1]);
682
		pci_read_config_dword(pvt->pci_ch[i][1],
683
				MC_DOD_CH_DIMM2, &dimm_dod[2]);
684

685
		debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
686
			"%d ranks, %cDIMMs\n",
687 688 689
			i,
			RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
			data,
690
			pvt->channel[i].ranks,
691
			(data & REGISTERED_DIMM) ? 'R' : 'U');
692 693 694

		for (j = 0; j < 3; j++) {
			u32 banks, ranks, rows, cols;
695
			u32 size, npages;
696 697 698 699 700 701 702 703 704

			if (!DIMM_PRESENT(dimm_dod[j]))
				continue;

			banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
			ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
			rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
			cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));

705 706 707
			/* DDR3 has 8 I/O banks */
			size = (rows * cols * banks * ranks) >> (20 - 3);

708
			pvt->channel[i].dimms++;
709

710 711 712
			debugf0("\tdimm %d %d Mb offset: %x, "
				"bank: %d, rank: %d, row: %#x, col: %#x\n",
				j, size,
713 714 715
				RANKOFFSET(dimm_dod[j]),
				banks, ranks, rows, cols);

716
			npages = MiB_TO_PAGES(size);
717

718
			csr = &mci->csrows[csrow];
719 720 721 722 723
			csr->first_page = last_page + 1;
			last_page += npages;
			csr->last_page = last_page;
			csr->nr_pages = npages;

724
			csr->page_mask = 0;
725
			csr->csrow_idx = csrow;
726 727 728 729
			csr->nr_channels = 1;

			csr->channels[0].chan_idx = i;
			csr->channels[0].ce_count = 0;
730

731
			pvt->csrow_map[i][j] = csrow;
732

733
			dimm = csr->channels[0].dimm;
734 735
			switch (banks) {
			case 4:
736
				dimm->dtype = DEV_X4;
737 738
				break;
			case 8:
739
				dimm->dtype = DEV_X8;
740 741
				break;
			case 16:
742
				dimm->dtype = DEV_X16;
743 744
				break;
			default:
745
				dimm->dtype = DEV_UNKNOWN;
746 747
			}

748 749 750 751 752 753
			snprintf(dimm->label, sizeof(dimm->label),
				 "CPU#%uChannel#%u_DIMM#%u",
				 pvt->i7core_dev->socket, i, j);
			dimm->grain = 8;
			dimm->edac_mode = mode;
			dimm->mtype = mtype;
754
		}
755

756 757 758 759 760 761 762 763
		pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
		pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
		pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
		pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
		pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
		pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
		pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
		pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
764
		debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
765
		for (j = 0; j < 8; j++)
766
			debugf1("\t\t%#x\t%#x\t%#x\n",
767 768
				(value[j] >> 27) & 0x1,
				(value[j] >> 24) & 0x7,
769
				(value[j] & ((1 << 24) - 1)));
770 771
	}

772 773 774
	return 0;
}

775 776 777 778 779 780 781 782 783 784 785
/****************************************************************************
			Error insertion routines
 ****************************************************************************/

/* The i7core has independent error injection features per channel.
   However, to have a simpler code, we don't allow enabling error injection
   on more than one channel.
   Also, since a change at an inject parameter will be applied only at enable,
   we're disabling error injection on all write calls to the sysfs nodes that
   controls the error code injection.
 */
786
static int disable_inject(const struct mem_ctl_info *mci)
787 788 789 790 791
{
	struct i7core_pvt *pvt = mci->pvt_info;

	pvt->inject.enable = 0;

792
	if (!pvt->pci_ch[pvt->inject.channel][0])
793 794
		return -ENODEV;

795
	pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
796
				MC_CHANNEL_ERROR_INJECT, 0);
797 798

	return 0;
799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815
}

/*
 * i7core inject inject.section
 *
 *	accept and store error injection inject.section value
 *	bit 0 - refers to the lower 32-byte half cacheline
 *	bit 1 - refers to the upper 32-byte half cacheline
 */
static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
					   const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
816
		disable_inject(mci);
817 818 819

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 3))
820
		return -EIO;
821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848

	pvt->inject.section = (u32) value;
	return count;
}

static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.section);
}

/*
 * i7core inject.type
 *
 *	accept and store error injection inject.section value
 *	bit 0 - repeat enable - Enable error repetition
 *	bit 1 - inject ECC error
 *	bit 2 - inject parity error
 */
static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
					const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
849
		disable_inject(mci);
850 851 852

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 7))
853
		return -EIO;
854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883

	pvt->inject.type = (u32) value;
	return count;
}

static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.type);
}

/*
 * i7core_inject_inject.eccmask_store
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */
static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
					const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
884
		disable_inject(mci);
885 886 887

	rc = strict_strtoul(data, 10, &value);
	if (rc < 0)
888
		return -EIO;
889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911

	pvt->inject.eccmask = (u32) value;
	return count;
}

static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
}

/*
 * i7core_addrmatch
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */

912 913 914 915 916
#define DECLARE_ADDR_MATCH(param, limit)			\
static ssize_t i7core_inject_store_##param(			\
		struct mem_ctl_info *mci,			\
		const char *data, size_t count)			\
{								\
917
	struct i7core_pvt *pvt;					\
918 919 920
	long value;						\
	int rc;							\
								\
921 922 923
	debugf1("%s()\n", __func__);				\
	pvt = mci->pvt_info;					\
								\
924 925 926
	if (pvt->inject.enable)					\
		disable_inject(mci);				\
								\
927
	if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943
		value = -1;					\
	else {							\
		rc = strict_strtoul(data, 10, &value);		\
		if ((rc < 0) || (value >= limit))		\
			return -EIO;				\
	}							\
								\
	pvt->inject.param = value;				\
								\
	return count;						\
}								\
								\
static ssize_t i7core_inject_show_##param(			\
		struct mem_ctl_info *mci,			\
		char *data)					\
{								\
944 945 946 947
	struct i7core_pvt *pvt;					\
								\
	pvt = mci->pvt_info;					\
	debugf1("%s() pvt=%p\n", __func__, pvt);		\
948 949 950 951
	if (pvt->inject.param < 0)				\
		return sprintf(data, "any\n");			\
	else							\
		return sprintf(data, "%d\n", pvt->inject.param);\
952 953
}

954 955 956 957 958 959 960 961 962
#define ATTR_ADDR_MATCH(param)					\
	{							\
		.attr = {					\
			.name = #param,				\
			.mode = (S_IRUGO | S_IWUSR)		\
		},						\
		.show  = i7core_inject_show_##param,		\
		.store = i7core_inject_store_##param,		\
	}
963

964 965 966 967 968 969
DECLARE_ADDR_MATCH(channel, 3);
DECLARE_ADDR_MATCH(dimm, 3);
DECLARE_ADDR_MATCH(rank, 4);
DECLARE_ADDR_MATCH(bank, 32);
DECLARE_ADDR_MATCH(page, 0x10000);
DECLARE_ADDR_MATCH(col, 0x4000);
970

971
static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
972 973 974 975
{
	u32 read;
	int count;

976 977 978 979
	debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
		dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
		where, val);

980 981
	for (count = 0; count < 10; count++) {
		if (count)
982
			msleep(100);
983 984 985 986 987 988 989
		pci_write_config_dword(dev, where, val);
		pci_read_config_dword(dev, where, &read);

		if (read == val)
			return 0;
	}

990 991 992 993
	i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
		"write=%08x. Read=%08x\n",
		dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
		where, val, read);
994 995 996 997

	return -EINVAL;
}

998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024
/*
 * This routine prepares the Memory Controller for error injection.
 * The error will be injected when some process tries to write to the
 * memory that matches the given criteria.
 * The criteria can be set in terms of a mask where dimm, rank, bank, page
 * and col can be specified.
 * A -1 value for any of the mask items will make the MCU to ignore
 * that matching criteria for error injection.
 *
 * It should be noticed that the error will only happen after a write operation
 * on a memory that matches the condition. if REPEAT_EN is not enabled at
 * inject mask, then it will produce just one error. Otherwise, it will repeat
 * until the injectmask would be cleaned.
 *
 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
 *    is reliable enough to check if the MC is using the
 *    three channels. However, this is not clear at the datasheet.
 */
static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
				       const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	u32 injectmask;
	u64 mask = 0;
	int  rc;
	long enable;

1025
	if (!pvt->pci_ch[pvt->inject.channel][0])
1026 1027
		return 0;

1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040
	rc = strict_strtoul(data, 10, &enable);
	if ((rc < 0))
		return 0;

	if (enable) {
		pvt->inject.enable = 1;
	} else {
		disable_inject(mci);
		return count;
	}

	/* Sets pvt->inject.dimm mask */
	if (pvt->inject.dimm < 0)
1041
		mask |= 1LL << 41;
1042
	else {
1043
		if (pvt->channel[pvt->inject.channel].dimms > 2)
1044
			mask |= (pvt->inject.dimm & 0x3LL) << 35;
1045
		else
1046
			mask |= (pvt->inject.dimm & 0x1LL) << 36;
1047 1048 1049 1050
	}

	/* Sets pvt->inject.rank mask */
	if (pvt->inject.rank < 0)
1051
		mask |= 1LL << 40;
1052
	else {
1053
		if (pvt->channel[pvt->inject.channel].dimms > 2)
1054
			mask |= (pvt->inject.rank & 0x1LL) << 34;
1055
		else
1056
			mask |= (pvt->inject.rank & 0x3LL) << 34;
1057 1058 1059 1060
	}

	/* Sets pvt->inject.bank mask */
	if (pvt->inject.bank < 0)
1061
		mask |= 1LL << 39;
1062
	else
1063
		mask |= (pvt->inject.bank & 0x15LL) << 30;
1064 1065 1066

	/* Sets pvt->inject.page mask */
	if (pvt->inject.page < 0)
1067
		mask |= 1LL << 38;
1068
	else
1069
		mask |= (pvt->inject.page & 0xffff) << 14;
1070 1071 1072

	/* Sets pvt->inject.column mask */
	if (pvt->inject.col < 0)
1073
		mask |= 1LL << 37;
1074
	else
1075
		mask |= (pvt->inject.col & 0x3fff);
1076

1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088
	/*
	 * bit    0: REPEAT_EN
	 * bits 1-2: MASK_HALF_CACHELINE
	 * bit    3: INJECT_ECC
	 * bit    4: INJECT_ADDR_PARITY
	 */

	injectmask = (pvt->inject.type & 1) |
		     (pvt->inject.section & 0x3) << 1 |
		     (pvt->inject.type & 0x6) << (3 - 1);

	/* Unlock writes to registers - this register is write only */
1089
	pci_write_config_dword(pvt->pci_noncore,
1090
			       MC_CFG_CONTROL, 0x2);
1091

1092
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1093
			       MC_CHANNEL_ADDR_MATCH, mask);
1094
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1095 1096
			       MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);

1097
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1098 1099
			       MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);

1100
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1101
			       MC_CHANNEL_ERROR_INJECT, injectmask);
1102

1103
	/*
1104 1105 1106
	 * This is something undocumented, based on my tests
	 * Without writing 8 to this register, errors aren't injected. Not sure
	 * why.
1107
	 */
1108
	pci_write_config_dword(pvt->pci_noncore,
1109
			       MC_CFG_CONTROL, 8);
1110

1111 1112
	debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
		" inject 0x%08x\n",
1113 1114
		mask, pvt->inject.eccmask, injectmask);

1115

1116 1117 1118 1119 1120 1121 1122
	return count;
}

static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
					char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
1123 1124
	u32 injectmask;

1125 1126 1127
	if (!pvt->pci_ch[pvt->inject.channel][0])
		return 0;

1128
	pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1129
			       MC_CHANNEL_ERROR_INJECT, &injectmask);
1130 1131 1132 1133 1134 1135

	debugf0("Inject error read: 0x%018x\n", injectmask);

	if (injectmask & 0x0c)
		pvt->inject.enable = 1;

1136 1137 1138
	return sprintf(data, "%d\n", pvt->inject.enable);
}

1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151
#define DECLARE_COUNTER(param)					\
static ssize_t i7core_show_counter_##param(			\
		struct mem_ctl_info *mci,			\
		char *data)					\
{								\
	struct i7core_pvt *pvt = mci->pvt_info;			\
								\
	debugf1("%s() \n", __func__);				\
	if (!pvt->ce_count_available || (pvt->is_registered))	\
		return sprintf(data, "data unavailable\n");	\
	return sprintf(data, "%lu\n",				\
			pvt->udimm_ce_count[param]);		\
}
1152

1153 1154 1155 1156 1157 1158 1159
#define ATTR_COUNTER(param)					\
	{							\
		.attr = {					\
			.name = __stringify(udimm##param),	\
			.mode = (S_IRUGO | S_IWUSR)		\
		},						\
		.show  = i7core_show_counter_##param		\
1160
	}
1161

1162 1163 1164
DECLARE_COUNTER(0);
DECLARE_COUNTER(1);
DECLARE_COUNTER(2);
1165

1166 1167 1168
/*
 * Sysfs struct
 */
1169

1170
static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
1171 1172 1173 1174 1175 1176
	ATTR_ADDR_MATCH(channel),
	ATTR_ADDR_MATCH(dimm),
	ATTR_ADDR_MATCH(rank),
	ATTR_ADDR_MATCH(bank),
	ATTR_ADDR_MATCH(page),
	ATTR_ADDR_MATCH(col),
1177
	{ } /* End of list */
1178 1179
};

1180
static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
1181 1182 1183 1184
	.name  = "inject_addrmatch",
	.mcidev_attr = i7core_addrmatch_attrs,
};

1185
static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
1186 1187 1188
	ATTR_COUNTER(0),
	ATTR_COUNTER(1),
	ATTR_COUNTER(2),
1189
	{ .attr = { .name = NULL } }
1190 1191
};

1192
static const struct mcidev_sysfs_group i7core_udimm_counters = {
1193 1194 1195 1196
	.name  = "all_channel_counts",
	.mcidev_attr = i7core_udimm_counters_attrs,
};

1197
static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219
	{
		.attr = {
			.name = "inject_section",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_section_show,
		.store = i7core_inject_section_store,
	}, {
		.attr = {
			.name = "inject_type",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_type_show,
		.store = i7core_inject_type_store,
	}, {
		.attr = {
			.name = "inject_eccmask",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_eccmask_show,
		.store = i7core_inject_eccmask_store,
	}, {
1220
		.grp = &i7core_inject_addrmatch,
1221 1222 1223 1224 1225 1226 1227 1228
	}, {
		.attr = {
			.name = "inject_enable",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_enable_show,
		.store = i7core_inject_enable_store,
	},
1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266
	{ }	/* End of list */
};

static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
	{
		.attr = {
			.name = "inject_section",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_section_show,
		.store = i7core_inject_section_store,
	}, {
		.attr = {
			.name = "inject_type",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_type_show,
		.store = i7core_inject_type_store,
	}, {
		.attr = {
			.name = "inject_eccmask",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_eccmask_show,
		.store = i7core_inject_eccmask_store,
	}, {
		.grp = &i7core_inject_addrmatch,
	}, {
		.attr = {
			.name = "inject_enable",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_enable_show,
		.store = i7core_inject_enable_store,
	}, {
		.grp = &i7core_udimm_counters,
	},
	{ }	/* End of list */
1267 1268
};

1269 1270 1271 1272 1273
/****************************************************************************
	Device initialization routines: put/get, init/exit
 ****************************************************************************/

/*
1274
 *	i7core_put_all_devices	'put' all the devices that we have
1275 1276
 *				reserved via 'get'
 */
1277
static void i7core_put_devices(struct i7core_dev *i7core_dev)
1278
{
1279
	int i;
1280

1281
	debugf0(__FILE__ ": %s()\n", __func__);
1282
	for (i = 0; i < i7core_dev->n_devs; i++) {
1283 1284 1285 1286 1287 1288 1289 1290
		struct pci_dev *pdev = i7core_dev->pdev[i];
		if (!pdev)
			continue;
		debugf0("Removing dev %02x:%02x.%d\n",
			pdev->bus->number,
			PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
		pci_dev_put(pdev);
	}
1291
}
1292

1293 1294
static void i7core_put_all_devices(void)
{
1295
	struct i7core_dev *i7core_dev, *tmp;
1296

1297
	list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
1298
		i7core_put_devices(i7core_dev);
1299
		free_i7core_dev(i7core_dev);
1300
	}
1301 1302
}

1303
static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
1304 1305 1306
{
	struct pci_dev *pdev = NULL;
	int i;
1307

1308
	/*
D
David Sterba 已提交
1309
	 * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses
1310 1311 1312
	 * aren't announced by acpi. So, we need to use a legacy scan probing
	 * to detect them
	 */
1313 1314 1315 1316 1317 1318
	while (table && table->descr) {
		pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
		if (unlikely(!pdev)) {
			for (i = 0; i < MAX_SOCKET_BUSES; i++)
				pcibios_scan_specific_bus(255-i);
		}
1319
		pci_dev_put(pdev);
1320
		table++;
1321 1322 1323
	}
}

1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340
static unsigned i7core_pci_lastbus(void)
{
	int last_bus = 0, bus;
	struct pci_bus *b = NULL;

	while ((b = pci_find_next_bus(b)) != NULL) {
		bus = b->number;
		debugf0("Found bus %d\n", bus);
		if (bus > last_bus)
			last_bus = bus;
	}

	debugf0("Last bus %d\n", last_bus);

	return last_bus;
}

1341
/*
1342
 *	i7core_get_all_devices	Find and perform 'get' operation on the MCH's
1343 1344 1345 1346
 *			device/functions we want to reference for this driver
 *
 *			Need to 'get' device 16 func 1 and func 2
 */
1347 1348 1349 1350
static int i7core_get_onedevice(struct pci_dev **prev,
				const struct pci_id_table *table,
				const unsigned devno,
				const unsigned last_bus)
1351
{
1352
	struct i7core_dev *i7core_dev;
1353
	const struct pci_id_descr *dev_descr = &table->descr[devno];
1354

1355
	struct pci_dev *pdev = NULL;
1356 1357
	u8 bus = 0;
	u8 socket = 0;
1358

1359
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1360
			      dev_descr->dev_id, *prev);
1361

1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375
	/*
	 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
	 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
	 * to probe for the alternate address in case of failure
	 */
	if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
		pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
				      PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);

	if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
		pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
				      PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
				      *prev);

1376 1377 1378 1379
	if (!pdev) {
		if (*prev) {
			*prev = pdev;
			return 0;
1380 1381
		}

1382
		if (dev_descr->optional)
1383
			return 0;
1384

1385 1386 1387
		if (devno == 0)
			return -ENODEV;

1388
		i7core_printk(KERN_INFO,
1389
			"Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1390 1391
			dev_descr->dev, dev_descr->func,
			PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1392

1393 1394 1395 1396
		/* End of list, leave */
		return -ENODEV;
	}
	bus = pdev->bus->number;
1397

1398
	socket = last_bus - bus;
1399

1400 1401
	i7core_dev = get_i7core_dev(socket);
	if (!i7core_dev) {
1402
		i7core_dev = alloc_i7core_dev(socket, table);
1403 1404
		if (!i7core_dev) {
			pci_dev_put(pdev);
1405
			return -ENOMEM;
1406
		}
1407
	}
1408

1409
	if (i7core_dev->pdev[devno]) {
1410 1411 1412
		i7core_printk(KERN_ERR,
			"Duplicated device for "
			"dev %02x:%02x.%d PCI ID %04x:%04x\n",
1413 1414
			bus, dev_descr->dev, dev_descr->func,
			PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1415 1416 1417
		pci_dev_put(pdev);
		return -ENODEV;
	}
1418

1419
	i7core_dev->pdev[devno] = pdev;
1420 1421

	/* Sanity check */
1422 1423
	if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
			PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1424 1425 1426
		i7core_printk(KERN_ERR,
			"Device PCI ID %04x:%04x "
			"has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
1427
			PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1428
			bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1429
			bus, dev_descr->dev, dev_descr->func);
1430 1431
		return -ENODEV;
	}
1432

1433 1434 1435 1436 1437
	/* Be sure that the device is enabled */
	if (unlikely(pci_enable_device(pdev) < 0)) {
		i7core_printk(KERN_ERR,
			"Couldn't enable "
			"dev %02x:%02x.%d PCI ID %04x:%04x\n",
1438 1439
			bus, dev_descr->dev, dev_descr->func,
			PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1440 1441
		return -ENODEV;
	}
1442

1443
	debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
1444 1445 1446
		socket, bus, dev_descr->dev,
		dev_descr->func,
		PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1447

1448 1449 1450 1451 1452 1453 1454
	/*
	 * As stated on drivers/pci/search.c, the reference count for
	 * @from is always decremented if it is not %NULL. So, as we need
	 * to get all devices up to null, we need to do a get for the device
	 */
	pci_dev_get(pdev);

1455
	*prev = pdev;
1456

1457 1458
	return 0;
}
1459

1460
static int i7core_get_all_devices(void)
1461
{
1462
	int i, rc, last_bus;
1463
	struct pci_dev *pdev = NULL;
1464
	const struct pci_id_table *table = pci_dev_table;
1465

1466 1467
	last_bus = i7core_pci_lastbus();

1468
	while (table && table->descr) {
1469 1470 1471
		for (i = 0; i < table->n_devs; i++) {
			pdev = NULL;
			do {
1472
				rc = i7core_get_onedevice(&pdev, table, i,
1473
							  last_bus);
1474 1475 1476 1477 1478 1479 1480 1481 1482 1483
				if (rc < 0) {
					if (i == 0) {
						i = table->n_devs;
						break;
					}
					i7core_put_all_devices();
					return -ENODEV;
				}
			} while (pdev);
		}
1484
		table++;
1485
	}
1486

1487 1488 1489
	return 0;
}

1490 1491
static int mci_bind_devs(struct mem_ctl_info *mci,
			 struct i7core_dev *i7core_dev)
1492 1493 1494
{
	struct i7core_pvt *pvt = mci->pvt_info;
	struct pci_dev *pdev;
1495
	int i, func, slot;
1496
	char *family;
1497

1498 1499
	pvt->is_registered = false;
	pvt->enable_scrub  = false;
1500
	for (i = 0; i < i7core_dev->n_devs; i++) {
1501 1502
		pdev = i7core_dev->pdev[i];
		if (!pdev)
1503 1504
			continue;

1505 1506 1507 1508 1509 1510 1511 1512
		func = PCI_FUNC(pdev->devfn);
		slot = PCI_SLOT(pdev->devfn);
		if (slot == 3) {
			if (unlikely(func > MAX_MCR_FUNC))
				goto error;
			pvt->pci_mcr[func] = pdev;
		} else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
			if (unlikely(func > MAX_CHAN_FUNC))
1513
				goto error;
1514
			pvt->pci_ch[slot - 4][func] = pdev;
1515
		} else if (!slot && !func) {
1516
			pvt->pci_noncore = pdev;
1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545

			/* Detect the processor family */
			switch (pdev->device) {
			case PCI_DEVICE_ID_INTEL_I7_NONCORE:
				family = "Xeon 35xx/ i7core";
				pvt->enable_scrub = false;
				break;
			case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT:
				family = "i7-800/i5-700";
				pvt->enable_scrub = false;
				break;
			case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE:
				family = "Xeon 34xx";
				pvt->enable_scrub = false;
				break;
			case PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT:
				family = "Xeon 55xx";
				pvt->enable_scrub = true;
				break;
			case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2:
				family = "Xeon 56xx / i7-900";
				pvt->enable_scrub = true;
				break;
			default:
				family = "unknown";
				pvt->enable_scrub = false;
			}
			debugf0("Detected a processor type %s\n", family);
		} else
1546
			goto error;
1547

1548 1549 1550
		debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
			PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
			pdev, i7core_dev->socket);
1551

1552 1553
		if (PCI_SLOT(pdev->devfn) == 3 &&
			PCI_FUNC(pdev->devfn) == 2)
1554
			pvt->is_registered = true;
1555
	}
1556

1557
	return 0;
1558 1559 1560 1561 1562 1563

error:
	i7core_printk(KERN_ERR, "Device %d, function %d "
		      "is out of the expected range\n",
		      slot, func);
	return -EINVAL;
1564 1565
}

1566 1567 1568
/****************************************************************************
			Error check routines
 ****************************************************************************/
1569
static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
1570 1571 1572
				      const int chan,
				      const int dimm,
				      const int add)
1573 1574 1575
{
	char *msg;
	struct i7core_pvt *pvt = mci->pvt_info;
1576
	int row = pvt->csrow_map[chan][dimm], i;
1577 1578 1579

	for (i = 0; i < add; i++) {
		msg = kasprintf(GFP_KERNEL, "Corrected error "
1580 1581
				"(Socket=%d channel=%d dimm=%d)",
				pvt->i7core_dev->socket, chan, dimm);
1582 1583 1584 1585 1586 1587 1588

		edac_mc_handle_fbd_ce(mci, row, 0, msg);
		kfree (msg);
	}
}

static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
1589 1590 1591 1592
					 const int chan,
					 const int new0,
					 const int new1,
					 const int new2)
1593 1594 1595 1596
{
	struct i7core_pvt *pvt = mci->pvt_info;
	int add0 = 0, add1 = 0, add2 = 0;
	/* Updates CE counters if it is not the first time here */
1597
	if (pvt->ce_count_available) {
1598 1599
		/* Updates CE counters */

1600 1601 1602
		add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
		add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
		add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
1603 1604 1605

		if (add2 < 0)
			add2 += 0x7fff;
1606
		pvt->rdimm_ce_count[chan][2] += add2;
1607 1608 1609

		if (add1 < 0)
			add1 += 0x7fff;
1610
		pvt->rdimm_ce_count[chan][1] += add1;
1611 1612 1613

		if (add0 < 0)
			add0 += 0x7fff;
1614
		pvt->rdimm_ce_count[chan][0] += add0;
1615
	} else
1616
		pvt->ce_count_available = 1;
1617 1618

	/* Store the new values */
1619 1620 1621
	pvt->rdimm_last_ce_count[chan][2] = new2;
	pvt->rdimm_last_ce_count[chan][1] = new1;
	pvt->rdimm_last_ce_count[chan][0] = new0;
1622 1623 1624

	/*updated the edac core */
	if (add0 != 0)
1625
		i7core_rdimm_update_csrow(mci, chan, 0, add0);
1626
	if (add1 != 0)
1627
		i7core_rdimm_update_csrow(mci, chan, 1, add1);
1628
	if (add2 != 0)
1629
		i7core_rdimm_update_csrow(mci, chan, 2, add2);
1630 1631 1632

}

1633
static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1634 1635 1636 1637 1638 1639
{
	struct i7core_pvt *pvt = mci->pvt_info;
	u32 rcv[3][2];
	int i, new0, new1, new2;

	/*Read DEV 3: FUN 2:  MC_COR_ECC_CNT regs directly*/
1640
	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
1641
								&rcv[0][0]);
1642
	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
1643
								&rcv[0][1]);
1644
	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
1645
								&rcv[1][0]);
1646
	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
1647
								&rcv[1][1]);
1648
	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
1649
								&rcv[2][0]);
1650
	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
1651 1652 1653 1654 1655
								&rcv[2][1]);
	for (i = 0 ; i < 3; i++) {
		debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
			(i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
		/*if the channel has 3 dimms*/
1656
		if (pvt->channel[i].dimms > 2) {
1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667
			new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
			new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
			new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
		} else {
			new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
					DIMM_BOT_COR_ERR(rcv[i][0]);
			new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
					DIMM_BOT_COR_ERR(rcv[i][1]);
			new2 = 0;
		}

1668
		i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
1669 1670
	}
}
1671 1672 1673 1674 1675 1676 1677

/* This function is based on the device 3 function 4 registers as described on:
 * Intel Xeon Processor 5500 Series Datasheet Volume 2
 *	http://www.intel.com/Assets/PDF/datasheet/321322.pdf
 * also available at:
 * 	http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */
1678
static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1679 1680 1681 1682 1683
{
	struct i7core_pvt *pvt = mci->pvt_info;
	u32 rcv1, rcv0;
	int new0, new1, new2;

1684
	if (!pvt->pci_mcr[4]) {
1685
		debugf0("%s MCR registers not found\n", __func__);
1686 1687 1688
		return;
	}

1689
	/* Corrected test errors */
1690 1691
	pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
	pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
1692 1693 1694 1695 1696 1697 1698

	/* Store the new values */
	new2 = DIMM2_COR_ERR(rcv1);
	new1 = DIMM1_COR_ERR(rcv0);
	new0 = DIMM0_COR_ERR(rcv0);

	/* Updates CE counters if it is not the first time here */
1699
	if (pvt->ce_count_available) {
1700 1701 1702
		/* Updates CE counters */
		int add0, add1, add2;

1703 1704 1705
		add2 = new2 - pvt->udimm_last_ce_count[2];
		add1 = new1 - pvt->udimm_last_ce_count[1];
		add0 = new0 - pvt->udimm_last_ce_count[0];
1706 1707 1708

		if (add2 < 0)
			add2 += 0x7fff;
1709
		pvt->udimm_ce_count[2] += add2;
1710 1711 1712

		if (add1 < 0)
			add1 += 0x7fff;
1713
		pvt->udimm_ce_count[1] += add1;
1714 1715 1716

		if (add0 < 0)
			add0 += 0x7fff;
1717
		pvt->udimm_ce_count[0] += add0;
1718 1719 1720 1721 1722

		if (add0 | add1 | add2)
			i7core_printk(KERN_ERR, "New Corrected error(s): "
				      "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
				      add0, add1, add2);
1723
	} else
1724
		pvt->ce_count_available = 1;
1725 1726

	/* Store the new values */
1727 1728 1729
	pvt->udimm_last_ce_count[2] = new2;
	pvt->udimm_last_ce_count[1] = new1;
	pvt->udimm_last_ce_count[0] = new0;
1730 1731
}

1732 1733 1734
/*
 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
 * Architectures Software Developer’s Manual Volume 3B.
1735 1736 1737
 * Nehalem are defined as family 0x06, model 0x1a
 *
 * The MCA registers used here are the following ones:
1738
 *     struct mce field	MCA Register
1739 1740 1741
 *     m->status	MSR_IA32_MC8_STATUS
 *     m->addr		MSR_IA32_MC8_ADDR
 *     m->misc		MSR_IA32_MC8_MISC
1742 1743 1744
 * In the case of Nehalem, the error information is masked at .status and .misc
 * fields
 */
1745
static void i7core_mce_output_error(struct mem_ctl_info *mci,
1746
				    const struct mce *m)
1747
{
1748
	struct i7core_pvt *pvt = mci->pvt_info;
1749
	char *type, *optype, *err, *msg;
1750
	unsigned long error = m->status & 0x1ff0000l;
1751
	u32 optypenum = (m->status >> 4) & 0x07;
1752
	u32 core_err_cnt = (m->status >> 38) & 0x7fff;
1753 1754 1755 1756
	u32 dimm = (m->misc >> 16) & 0x3;
	u32 channel = (m->misc >> 18) & 0x3;
	u32 syndrome = m->misc >> 32;
	u32 errnum = find_first_bit(&error, 32);
1757
	int csrow;
1758

1759 1760 1761 1762 1763
	if (m->mcgstatus & 1)
		type = "FATAL";
	else
		type = "NON_FATAL";

1764
	switch (optypenum) {
1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782
	case 0:
		optype = "generic undef request";
		break;
	case 1:
		optype = "read error";
		break;
	case 2:
		optype = "write error";
		break;
	case 3:
		optype = "addr/cmd error";
		break;
	case 4:
		optype = "scrubbing error";
		break;
	default:
		optype = "reserved";
		break;
1783 1784
	}

1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814
	switch (errnum) {
	case 16:
		err = "read ECC error";
		break;
	case 17:
		err = "RAS ECC error";
		break;
	case 18:
		err = "write parity error";
		break;
	case 19:
		err = "redundacy loss";
		break;
	case 20:
		err = "reserved";
		break;
	case 21:
		err = "memory range error";
		break;
	case 22:
		err = "RTID out of range";
		break;
	case 23:
		err = "address parity error";
		break;
	case 24:
		err = "byte enable parity error";
		break;
	default:
		err = "unknown";
1815 1816
	}

1817
	/* FIXME: should convert addr into bank and rank information */
1818
	msg = kasprintf(GFP_ATOMIC,
1819
		"%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
1820
		"syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
1821
		type, (long long) m->addr, m->cpu, dimm, channel,
1822 1823
		syndrome, core_err_cnt, (long long)m->status,
		(long long)m->misc, optype, err);
1824 1825

	debugf0("%s", msg);
1826

1827
	csrow = pvt->csrow_map[channel][dimm];
1828

1829
	/* Call the helper to output message */
1830 1831 1832
	if (m->mcgstatus & 1)
		edac_mc_handle_fbd_ue(mci, csrow, 0,
				0 /* FIXME: should be channel here */, msg);
1833
	else if (!pvt->is_registered)
1834 1835
		edac_mc_handle_fbd_ce(mci, csrow,
				0 /* FIXME: should be channel here */, msg);
1836 1837

	kfree(msg);
1838 1839
}

1840 1841 1842 1843 1844 1845
/*
 *	i7core_check_error	Retrieve and process errors reported by the
 *				hardware. Called by the Core module.
 */
static void i7core_check_error(struct mem_ctl_info *mci)
{
1846 1847 1848
	struct i7core_pvt *pvt = mci->pvt_info;
	int i;
	unsigned count = 0;
1849
	struct mce *m;
1850

1851 1852 1853
	/*
	 * MCE first step: Copy all mce errors into a temporary buffer
	 * We use a double buffering here, to reduce the risk of
L
Lucas De Marchi 已提交
1854
	 * losing an error.
1855 1856
	 */
	smp_rmb();
1857 1858
	count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
		% MCE_LOG_LEN;
1859
	if (!count)
1860
		goto check_ce_error;
1861

1862
	m = pvt->mce_outentry;
1863 1864
	if (pvt->mce_in + count > MCE_LOG_LEN) {
		unsigned l = MCE_LOG_LEN - pvt->mce_in;
1865

1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882
		memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
		smp_wmb();
		pvt->mce_in = 0;
		count -= l;
		m += l;
	}
	memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
	smp_wmb();
	pvt->mce_in += count;

	smp_rmb();
	if (pvt->mce_overrun) {
		i7core_printk(KERN_ERR, "Lost %d memory errors\n",
			      pvt->mce_overrun);
		smp_wmb();
		pvt->mce_overrun = 0;
	}
1883

1884 1885 1886
	/*
	 * MCE second step: parse errors and display
	 */
1887
	for (i = 0; i < count; i++)
1888
		i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
1889

1890 1891 1892
	/*
	 * Now, let's increment CE error counts
	 */
1893
check_ce_error:
1894 1895 1896 1897
	if (!pvt->is_registered)
		i7core_udimm_check_mc_ecc_err(mci);
	else
		i7core_rdimm_check_mc_ecc_err(mci);
1898 1899
}

1900 1901 1902 1903 1904
/*
 * i7core_mce_check_error	Replicates mcelog routine to get errors
 *				This routine simply queues mcelog errors, and
 *				return. The error itself should be handled later
 *				by i7core_check_error.
1905 1906
 * WARNING: As this routine should be called at NMI time, extra care should
 * be taken to avoid deadlocks, and to be as fast as possible.
1907
 */
1908 1909
static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
				  void *data)
1910
{
1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921
	struct mce *mce = (struct mce *)data;
	struct i7core_dev *i7_dev;
	struct mem_ctl_info *mci;
	struct i7core_pvt *pvt;

	i7_dev = get_i7core_dev(mce->socketid);
	if (!i7_dev)
		return NOTIFY_BAD;

	mci = i7_dev->mci;
	pvt = mci->pvt_info;
1922

1923 1924 1925 1926 1927
	/*
	 * Just let mcelog handle it if the error is
	 * outside the memory controller
	 */
	if (((mce->status & 0xffff) >> 7) != 1)
1928
		return NOTIFY_DONE;
1929

1930 1931
	/* Bank 8 registers are the only ones that we know how to handle */
	if (mce->bank != 8)
1932
		return NOTIFY_DONE;
1933

R
Randy Dunlap 已提交
1934
#ifdef CONFIG_SMP
1935
	/* Only handle if it is the right mc controller */
1936
	if (mce->socketid != pvt->i7core_dev->socket)
1937
		return NOTIFY_DONE;
R
Randy Dunlap 已提交
1938
#endif
1939

1940
	smp_rmb();
1941
	if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1942 1943
		smp_wmb();
		pvt->mce_overrun++;
1944
		return NOTIFY_DONE;
1945
	}
1946 1947 1948

	/* Copy memory error at the ringbuffer */
	memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1949
	smp_wmb();
1950
	pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1951

1952 1953 1954 1955
	/* Handle fatal errors immediately */
	if (mce->mcgstatus & 1)
		i7core_check_error(mci);

D
David Sterba 已提交
1956
	/* Advise mcelog that the errors were handled */
1957
	return NOTIFY_STOP;
1958 1959
}

1960 1961 1962 1963
static struct notifier_block i7_mce_dec = {
	.notifier_call	= i7core_mce_check_error,
};

N
Nils Carlson 已提交
1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069
struct memdev_dmi_entry {
	u8 type;
	u8 length;
	u16 handle;
	u16 phys_mem_array_handle;
	u16 mem_err_info_handle;
	u16 total_width;
	u16 data_width;
	u16 size;
	u8 form;
	u8 device_set;
	u8 device_locator;
	u8 bank_locator;
	u8 memory_type;
	u16 type_detail;
	u16 speed;
	u8 manufacturer;
	u8 serial_number;
	u8 asset_tag;
	u8 part_number;
	u8 attributes;
	u32 extended_size;
	u16 conf_mem_clk_speed;
} __attribute__((__packed__));


/*
 * Decode the DRAM Clock Frequency, be paranoid, make sure that all
 * memory devices show the same speed, and if they don't then consider
 * all speeds to be invalid.
 */
static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq)
{
	int *dclk_freq = _dclk_freq;
	u16 dmi_mem_clk_speed;

	if (*dclk_freq == -1)
		return;

	if (dh->type == DMI_ENTRY_MEM_DEVICE) {
		struct memdev_dmi_entry *memdev_dmi_entry =
			(struct memdev_dmi_entry *)dh;
		unsigned long conf_mem_clk_speed_offset =
			(unsigned long)&memdev_dmi_entry->conf_mem_clk_speed -
			(unsigned long)&memdev_dmi_entry->type;
		unsigned long speed_offset =
			(unsigned long)&memdev_dmi_entry->speed -
			(unsigned long)&memdev_dmi_entry->type;

		/* Check that a DIMM is present */
		if (memdev_dmi_entry->size == 0)
			return;

		/*
		 * Pick the configured speed if it's available, otherwise
		 * pick the DIMM speed, or we don't have a speed.
		 */
		if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) {
			dmi_mem_clk_speed =
				memdev_dmi_entry->conf_mem_clk_speed;
		} else if (memdev_dmi_entry->length > speed_offset) {
			dmi_mem_clk_speed = memdev_dmi_entry->speed;
		} else {
			*dclk_freq = -1;
			return;
		}

		if (*dclk_freq == 0) {
			/* First pass, speed was 0 */
			if (dmi_mem_clk_speed > 0) {
				/* Set speed if a valid speed is read */
				*dclk_freq = dmi_mem_clk_speed;
			} else {
				/* Otherwise we don't have a valid speed */
				*dclk_freq = -1;
			}
		} else if (*dclk_freq > 0 &&
			   *dclk_freq != dmi_mem_clk_speed) {
			/*
			 * If we have a speed, check that all DIMMS are the same
			 * speed, otherwise set the speed as invalid.
			 */
			*dclk_freq = -1;
		}
	}
}

/*
 * The default DCLK frequency is used as a fallback if we
 * fail to find anything reliable in the DMI. The value
 * is taken straight from the datasheet.
 */
#define DEFAULT_DCLK_FREQ 800

static int get_dclk_freq(void)
{
	int dclk_freq = 0;

	dmi_walk(decode_dclk, (void *)&dclk_freq);

	if (dclk_freq < 1)
		return DEFAULT_DCLK_FREQ;

	return dclk_freq;
}

2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092
/*
 * set_sdram_scrub_rate		This routine sets byte/sec bandwidth scrub rate
 *				to hardware according to SCRUBINTERVAL formula
 *				found in datasheet.
 */
static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	struct pci_dev *pdev;
	u32 dw_scrub;
	u32 dw_ssr;

	/* Get data from the MC register, function 2 */
	pdev = pvt->pci_mcr[2];
	if (!pdev)
		return -ENODEV;

	pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &dw_scrub);

	if (new_bw == 0) {
		/* Prepare to disable petrol scrub */
		dw_scrub &= ~STARTSCRUB;
		/* Stop the patrol scrub engine */
N
Nils Carlson 已提交
2093 2094
		write_and_test(pdev, MC_SCRUB_CONTROL,
			       dw_scrub & ~SCRUBINTERVAL_MASK);
2095 2096 2097 2098 2099 2100

		/* Get current status of scrub rate and set bit to disable */
		pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
		dw_ssr &= ~SSR_MODE_MASK;
		dw_ssr |= SSR_MODE_DISABLE;
	} else {
N
Nils Carlson 已提交
2101 2102 2103
		const int cache_line_size = 64;
		const u32 freq_dclk_mhz = pvt->dclk_freq;
		unsigned long long scrub_interval;
2104 2105
		/*
		 * Translate the desired scrub rate to a register value and
N
Nils Carlson 已提交
2106
		 * program the corresponding register value.
2107
		 */
N
Nils Carlson 已提交
2108
		scrub_interval = (unsigned long long)freq_dclk_mhz *
2109 2110
			cache_line_size * 1000000;
		do_div(scrub_interval, new_bw);
N
Nils Carlson 已提交
2111 2112 2113 2114 2115

		if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK)
			return -EINVAL;

		dw_scrub = SCRUBINTERVAL_MASK & scrub_interval;
2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141

		/* Start the patrol scrub engine */
		pci_write_config_dword(pdev, MC_SCRUB_CONTROL,
				       STARTSCRUB | dw_scrub);

		/* Get current status of scrub rate and set bit to enable */
		pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
		dw_ssr &= ~SSR_MODE_MASK;
		dw_ssr |= SSR_MODE_ENABLE;
	}
	/* Disable or enable scrubbing */
	pci_write_config_dword(pdev, MC_SSRCONTROL, dw_ssr);

	return new_bw;
}

/*
 * get_sdram_scrub_rate		This routine convert current scrub rate value
 *				into byte/sec bandwidth accourding to
 *				SCRUBINTERVAL formula found in datasheet.
 */
static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	struct pci_dev *pdev;
	const u32 cache_line_size = 64;
N
Nils Carlson 已提交
2142 2143
	const u32 freq_dclk_mhz = pvt->dclk_freq;
	unsigned long long scrub_rate;
2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154
	u32 scrubval;

	/* Get data from the MC register, function 2 */
	pdev = pvt->pci_mcr[2];
	if (!pdev)
		return -ENODEV;

	/* Get current scrub control data */
	pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval);

	/* Mask highest 8-bits to 0 */
N
Nils Carlson 已提交
2155
	scrubval &=  SCRUBINTERVAL_MASK;
2156 2157 2158 2159
	if (!scrubval)
		return 0;

	/* Calculate scrub rate value into byte/sec bandwidth */
N
Nils Carlson 已提交
2160
	scrub_rate =  (unsigned long long)freq_dclk_mhz *
2161 2162
		1000000 * cache_line_size;
	do_div(scrub_rate, scrubval);
N
Nils Carlson 已提交
2163
	return (int)scrub_rate;
2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192
}

static void enable_sdram_scrub_setting(struct mem_ctl_info *mci)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	u32 pci_lock;

	/* Unlock writes to pci registers */
	pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
	pci_lock &= ~0x3;
	pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
			       pci_lock | MC_CFG_UNLOCK);

	mci->set_sdram_scrub_rate = set_sdram_scrub_rate;
	mci->get_sdram_scrub_rate = get_sdram_scrub_rate;
}

static void disable_sdram_scrub_setting(struct mem_ctl_info *mci)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	u32 pci_lock;

	/* Lock writes to pci registers */
	pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
	pci_lock &= ~0x3;
	pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
			       pci_lock | MC_CFG_LOCK);
}

2193 2194 2195 2196 2197 2198
static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
{
	pvt->i7core_pci = edac_pci_create_generic_ctl(
						&pvt->i7core_dev->pdev[0]->dev,
						EDAC_MOD_STR);
	if (unlikely(!pvt->i7core_pci))
2199 2200
		i7core_printk(KERN_WARNING,
			      "Unable to setup PCI error report via EDAC\n");
2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213
}

static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
{
	if (likely(pvt->i7core_pci))
		edac_pci_release_generic_ctl(pvt->i7core_pci);
	else
		i7core_printk(KERN_ERR,
				"Couldn't find mem_ctl_info for socket %d\n",
				pvt->i7core_dev->socket);
	pvt->i7core_pci = NULL;
}

2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231
static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
{
	struct mem_ctl_info *mci = i7core_dev->mci;
	struct i7core_pvt *pvt;

	if (unlikely(!mci || !mci->pvt_info)) {
		debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
			__func__, &i7core_dev->pdev[0]->dev);

		i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
		return;
	}

	pvt = mci->pvt_info;

	debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
		__func__, mci, &i7core_dev->pdev[0]->dev);

2232
	/* Disable scrubrate setting */
2233 2234
	if (pvt->enable_scrub)
		disable_sdram_scrub_setting(mci);
2235

2236
	mce_unregister_decode_chain(&i7_mce_dec);
2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249

	/* Disable EDAC polling */
	i7core_pci_ctl_release(pvt);

	/* Remove MC sysfs nodes */
	edac_mc_del_mc(mci->dev);

	debugf1("%s: free mci struct\n", mci->ctl_name);
	kfree(mci->ctl_name);
	edac_mc_free(mci);
	i7core_dev->mci = NULL;
}

2250
static int i7core_register_mci(struct i7core_dev *i7core_dev)
2251 2252 2253
{
	struct mem_ctl_info *mci;
	struct i7core_pvt *pvt;
2254 2255 2256 2257 2258 2259
	int rc, channels, csrows;

	/* Check the number of active and not disabled channels */
	rc = i7core_get_active_channels(i7core_dev->socket, &channels, &csrows);
	if (unlikely(rc < 0))
		return rc;
2260 2261

	/* allocate a new MC control structure */
2262
	mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, i7core_dev->socket);
2263 2264
	if (unlikely(!mci))
		return -ENOMEM;
2265

2266 2267
	debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
		__func__, mci, &i7core_dev->pdev[0]->dev);
2268 2269

	pvt = mci->pvt_info;
2270
	memset(pvt, 0, sizeof(*pvt));
2271

2272 2273 2274 2275
	/* Associates i7core_dev and mci for future usage */
	pvt->i7core_dev = i7core_dev;
	i7core_dev->mci = mci;

2276 2277 2278 2279 2280 2281
	/*
	 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
	 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
	 * memory channels
	 */
	mci->mtype_cap = MEM_FLAG_DDR3;
2282 2283 2284 2285
	mci->edac_ctl_cap = EDAC_FLAG_NONE;
	mci->edac_cap = EDAC_FLAG_NONE;
	mci->mod_name = "i7core_edac.c";
	mci->mod_ver = I7CORE_REVISION;
2286 2287 2288
	mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
				  i7core_dev->socket);
	mci->dev_name = pci_name(i7core_dev->pdev[0]);
2289
	mci->ctl_page_to_phys = NULL;
2290

2291
	/* Store pci devices at mci for faster access */
2292
	rc = mci_bind_devs(mci, i7core_dev);
2293
	if (unlikely(rc < 0))
2294
		goto fail0;
2295

2296 2297 2298 2299 2300
	if (pvt->is_registered)
		mci->mc_driver_sysfs_attributes = i7core_sysfs_rdimm_attrs;
	else
		mci->mc_driver_sysfs_attributes = i7core_sysfs_udimm_attrs;

2301
	/* Get dimm basic config */
2302
	get_dimm_config(mci);
2303 2304 2305 2306
	/* record ptr to the generic device */
	mci->dev = &i7core_dev->pdev[0]->dev;
	/* Set the function pointer to an actual operation function */
	mci->edac_check = i7core_check_error;
2307

2308
	/* Enable scrubrate setting */
2309 2310
	if (pvt->enable_scrub)
		enable_sdram_scrub_setting(mci);
2311

2312
	/* add this new MC control structure to EDAC's list of MCs */
2313
	if (unlikely(edac_mc_add_mc(mci))) {
2314 2315 2316 2317 2318
		debugf0("MC: " __FILE__
			": %s(): failed edac_mc_add_mc()\n", __func__);
		/* FIXME: perhaps some code should go here that disables error
		 * reporting if we just enabled it
		 */
2319 2320

		rc = -EINVAL;
2321
		goto fail0;
2322 2323
	}

2324
	/* Default error mask is any memory */
2325
	pvt->inject.channel = 0;
2326 2327 2328 2329 2330 2331
	pvt->inject.dimm = -1;
	pvt->inject.rank = -1;
	pvt->inject.bank = -1;
	pvt->inject.page = -1;
	pvt->inject.col = -1;

2332 2333 2334
	/* allocating generic PCI control info */
	i7core_pci_ctl_create(pvt);

N
Nils Carlson 已提交
2335 2336 2337
	/* DCLK for scrub rate setting */
	pvt->dclk_freq = get_dclk_freq();

2338
	mce_register_decode_chain(&i7_mce_dec);
2339

2340 2341 2342 2343 2344
	return 0;

fail0:
	kfree(mci->ctl_name);
	edac_mc_free(mci);
2345
	i7core_dev->mci = NULL;
2346 2347 2348 2349 2350 2351 2352 2353 2354 2355
	return rc;
}

/*
 *	i7core_probe	Probe for ONE instance of device to see if it is
 *			present.
 *	return:
 *		0 for FOUND a device
 *		< 0 for error code
 */
2356

2357 2358 2359
static int __devinit i7core_probe(struct pci_dev *pdev,
				  const struct pci_device_id *id)
{
2360
	int rc, count = 0;
2361 2362
	struct i7core_dev *i7core_dev;

2363 2364 2365
	/* get the pci devices we want to reserve for our use */
	mutex_lock(&i7core_edac_lock);

2366
	/*
2367
	 * All memory controllers are allocated at the first pass.
2368
	 */
2369 2370
	if (unlikely(probed >= 1)) {
		mutex_unlock(&i7core_edac_lock);
2371
		return -ENODEV;
2372 2373
	}
	probed++;
2374

2375
	rc = i7core_get_all_devices();
2376 2377 2378 2379
	if (unlikely(rc < 0))
		goto fail0;

	list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
2380
		count++;
2381
		rc = i7core_register_mci(i7core_dev);
2382 2383
		if (unlikely(rc < 0))
			goto fail1;
2384 2385
	}

2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401
	/*
	 * Nehalem-EX uses a different memory controller. However, as the
	 * memory controller is not visible on some Nehalem/Nehalem-EP, we
	 * need to indirectly probe via a X58 PCI device. The same devices
	 * are found on (some) Nehalem-EX. So, on those machines, the
	 * probe routine needs to return -ENODEV, as the actual Memory
	 * Controller registers won't be detected.
	 */
	if (!count) {
		rc = -ENODEV;
		goto fail1;
	}

	i7core_printk(KERN_INFO,
		      "Driver loaded, %d memory controller(s) found.\n",
		      count);
2402

2403
	mutex_unlock(&i7core_edac_lock);
2404 2405
	return 0;

2406
fail1:
2407 2408 2409
	list_for_each_entry(i7core_dev, &i7core_edac_list, list)
		i7core_unregister_mci(i7core_dev);

2410
	i7core_put_all_devices();
2411 2412
fail0:
	mutex_unlock(&i7core_edac_lock);
2413
	return rc;
2414 2415 2416 2417 2418 2419 2420 2421
}

/*
 *	i7core_remove	destructor for one instance of device
 *
 */
static void __devexit i7core_remove(struct pci_dev *pdev)
{
2422
	struct i7core_dev *i7core_dev;
2423 2424 2425

	debugf0(__FILE__ ": %s()\n", __func__);

2426 2427 2428 2429 2430 2431 2432
	/*
	 * we have a trouble here: pdev value for removal will be wrong, since
	 * it will point to the X58 register used to detect that the machine
	 * is a Nehalem or upper design. However, due to the way several PCI
	 * devices are grouped together to provide MC functionality, we need
	 * to use a different method for releasing the devices
	 */
2433

2434
	mutex_lock(&i7core_edac_lock);
2435 2436 2437 2438 2439 2440

	if (unlikely(!probed)) {
		mutex_unlock(&i7core_edac_lock);
		return;
	}

2441 2442
	list_for_each_entry(i7core_dev, &i7core_edac_list, list)
		i7core_unregister_mci(i7core_dev);
2443 2444 2445 2446

	/* Release PCI resources */
	i7core_put_all_devices();

2447 2448
	probed--;

2449
	mutex_unlock(&i7core_edac_lock);
2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477
}

MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);

/*
 *	i7core_driver	pci_driver structure for this module
 *
 */
static struct pci_driver i7core_driver = {
	.name     = "i7core_edac",
	.probe    = i7core_probe,
	.remove   = __devexit_p(i7core_remove),
	.id_table = i7core_pci_tbl,
};

/*
 *	i7core_init		Module entry function
 *			Try to initialize this module for its devices
 */
static int __init i7core_init(void)
{
	int pci_rc;

	debugf2("MC: " __FILE__ ": %s()\n", __func__);

	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	opstate_init();

2478 2479
	if (use_pci_fixup)
		i7core_xeon_pci_fixup(pci_dev_table);
2480

2481 2482
	pci_rc = pci_register_driver(&i7core_driver);

2483 2484 2485 2486 2487 2488 2489
	if (pci_rc >= 0)
		return 0;

	i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
		      pci_rc);

	return pci_rc;
2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512
}

/*
 *	i7core_exit()	Module exit function
 *			Unregister the driver
 */
static void __exit i7core_exit(void)
{
	debugf2("MC: " __FILE__ ": %s()\n", __func__);
	pci_unregister_driver(&i7core_driver);
}

module_init(i7core_init);
module_exit(i7core_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
		   I7CORE_REVISION);

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");