* difftest: fix false-positive difftest intRF writeback, adapt to new difftest API

* csr: skip mip difftest

* bump difftest

* bump difftest

* fix some typos
Signed-off-by: Ncuishuang <imcusg@gmail.com>

* Bump difftest and ready-to-run

* add copy-and-run test for CI

* Bump ready-to-run: update NEMU

* CI: specify reference in ready-to-run repo

old missqueue: cache req miss slot and mem access-er
Problem: these two func are totally different, make mq hard to handle in a single select policy.
Solution: divide these two funciton into two module.
  new MissQueue: only hold reqs that page cache miss and need re-req cache， a simple flushable queue
  llptw: Last level ptw, only access ptes, priorityMux queue

* mmu: rename PTW.scala to L2TLB.scala

* mmu: rename PTW to L2TLB

* mmu: rename PtwFsm to PTW

* mmu.l2tlb: divide missqueue into 'missqueue' and llptw

old missqueue: cache req miss slot and mem access-er
Problem: these two func are totally different, make mq hard to handle
  in single select policy.
Solution: divide these two funciton into two module.
  new MissQueue: only hold reqs that page cache miss and new re-req
  cache
  llptw: Last level ptw, only access ptes

* mmu.l2tlb: syntax bug that misses io assign

* mmu.l2tlb: fix bug that mistakes ptw's block signal

* mem: optimize missq reject to lq timing

DCache replay request is quite slow to generate, as it need to compare
load address with address in all valid miss queue entries.

Now we delay the usage of replay request from data cache.
Now replay request will not influence normal execuation flow until
load_s3 (1 cycle after load_s2, load result writeback to RS).

It is worth mentioning that "select refilling inst for load
writeback" will be disabled if dcacheRequireReplay in the
last cycle.

* dcache: compare probe block addr instead of full addr

* mem: do not replay from RS when ldld vio or fwd failed

ld-ld violation or forward failure will let an normal load inst replay
from fetch. If TLB hit and ld-ld violation / forward failure happens,
we write back that inst immediately. Meanwhile, such insts will not be
replayed from rs.

It should fix "mem: optimize missq reject to lq timing"

* mem: fix replay from rs condition

* mem: reduce refill to use latency

This commit update lq entry flag carefully in load_s3 to avoid extra
refill delay. It will remove the extra refill delay introduced by #1375
without harming memblock timing.

In #1375, we delayed load refill when dcache miss queue entry fails
to accept a miss. #1375 exchanges performance for better timing.

* mem: fix rs feedback priority

When dataInvalid && mshrFull, a succeed refill should not cancel
rs replay.

Corner Case that makes l2tlb's performance decrease sharply:
core may have mis-speculative memory access, which may cause tlb-miss and ptw req to l2tlb.
In l2tlb, the reqs may still miss and even have invalid pte that won't be stored in l2tlb.cache.
If the relative ptes are invalid, these reqs will be held by miss queue and wait for page walker performing
page table walk one by one. It's too slow and will raise time out assert in l2tlb.missqueue.

Solution:
store invalid entries(only super entries) into sp.
Bad news is that sp only has16 entries, so invaid entries will pollute sp as well.
Good news is that the invalid reqs are always in same super page, so only one entries is mostly enough.

* l2tlb.cache: sp entries now handles invalid entries

* l2tlb.cache: fix syntax error, forgot assgin some signals

Add support for compiling XiangShan with CIRCT

* bump huancun

* sram: fix sram, keep rdata when w.valid

* tlb: when refill, just return miss at next cycle, rm unused assert

bump difftest and fix Makefile for VCS support

iprefetch uses vaddr instead of paddr.

Fix the file extension for inline verilog modules.

* IFU <bug-fix>: deal with itlb miss for resend

* IFU <bug fix>: enable crossPageFault for resend-pf
Co-authored-by: NDeltaZero <lacrosseelis@gmail.com>

* readme: update dir structure description and sync en/zh readme

* readme: update fig of nanhu-arch

* readme: update docs information

* readme: fix md format

* bump huancun

* bump huancun

* bump huancun

* Insert 1 buffer betwwen L2 and L3
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>

* mem: opt dcache tag error check timing

dcache.resp.bits.miss used to depend on tag_error, it causes severe
timing problem. That dependence is now removed.

Now when tag_error, we:

* Set access fault bit in exception vec
* Do not update miss queue. That is to say, if miss, that inst
may not be refilled
* Mark that inst as dataForwarded so it will not wait for refill
* Report error to CSR and BEU

If tag_error come with a miss, writeback taht inst from load
queue. Otherwise, writeback it from load pipeline.

* mem: opt tag error exception writeback logic

dcache.resp.bits.miss used to depend on tag_error, it causes severe
timing problem. That dependence is now removed.

Now when tag_error, we:

* Set access fault bit in exception vec
* Do not update miss queue. That is to say, if miss, that inst
may not be refilled
* Mark that inst as dataForwarded so it will not wait for refill
* Report error to CSR and BEU

If tag_error come with a miss, writeback taht inst from load
queue. Otherwise, writeback it from load pipeline.

* ITLB <timing>: delay miss and flush req for ITLB

* add 2 ILTB requestor and delete tlb_arb

* Bump huancun

* ICacheMainPipe <bug-fix>: fix slot invalid condition

* ITLB <timing>: add port to 6

* ICacheMainPipe <bug-fix>: stop pipe when tlb miss

* ICacheMainPipe <bug-fix>: fix illegal flush
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>

* mem: fix ldld vio mask gen logic

* mem: fix lq released flag update logic

Make sure that every load before a probe has correct released flag

See the PR of this commit for illustration

* mem: fix ld-ld violation check logic

* ci: clean up workspace before do real test

* mem: reduce lq released flag update delay for 1 cycle

* chore: bump difftest to run no-smp diff

* ci: add mc test

* mem: fix lq released flag update logic

* chore: set difftest firstCommit_limit to 10000

* ci: use dual-nemu-so for mc test

the mulitple-hit problem is yet to be solved (although it may be very rare)

* SoC: remove error_xbar; add more buffers

* Bump huancun

* Misc: set timeout threshold to 10000 cycles

* Bump huancun