translate.c 307.5 KB
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/*
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 *  PowerPC emulation for qemu: main translation routines.
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 *
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 *  Copyright (c) 2003-2007 Jocelyn Mayer
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 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
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 */
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#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>

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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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#include "tcg-op.h"
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#include "qemu-common.h"
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#include "helper.h"
#define GEN_HELPER 1
#include "helper.h"

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#define CPU_SINGLE_STEP 0x1
#define CPU_BRANCH_STEP 0x2
#define GDBSTUB_SINGLE_STEP 0x4

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/* Include definitions for instructions classes and implementations flags */
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//#define DO_SINGLE_STEP
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//#define PPC_DEBUG_DISAS
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//#define DO_PPC_STATISTICS
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#ifdef PPC_DEBUG_DISAS
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#  define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
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#else
#  define LOG_DISAS(...) do { } while (0)
#endif
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/*****************************************************************************/
/* Code translation helpers                                                  */
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/* global register indexes */
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static TCGv_ptr cpu_env;
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static char cpu_reg_names[10*3 + 22*4 /* GPR */
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#if !defined(TARGET_PPC64)
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    + 10*4 + 22*5 /* SPE GPRh */
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#endif
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    + 10*4 + 22*5 /* FPR */
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    + 2*(10*6 + 22*7) /* AVRh, AVRl */
    + 8*5 /* CRF */];
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static TCGv cpu_gpr[32];
#if !defined(TARGET_PPC64)
static TCGv cpu_gprh[32];
#endif
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static TCGv_i64 cpu_fpr[32];
static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
static TCGv_i32 cpu_crf[8];
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static TCGv cpu_nip;
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static TCGv cpu_msr;
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static TCGv cpu_ctr;
static TCGv cpu_lr;
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static TCGv cpu_xer;
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static TCGv cpu_reserve;
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static TCGv_i32 cpu_fpscr;
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static TCGv_i32 cpu_access_type;
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#include "gen-icount.h"

void ppc_translate_init(void)
{
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    int i;
    char* p;
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    static int done_init = 0;
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    if (done_init)
        return;
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    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

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    p = cpu_reg_names;
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    for (i = 0; i < 8; i++) {
        sprintf(p, "crf%d", i);
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        cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
                                            offsetof(CPUState, crf[i]), p);
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        p += 5;
    }

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    for (i = 0; i < 32; i++) {
        sprintf(p, "r%d", i);
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        cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
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                                        offsetof(CPUState, gpr[i]), p);
        p += (i < 10) ? 3 : 4;
#if !defined(TARGET_PPC64)
        sprintf(p, "r%dH", i);
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        cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
                                             offsetof(CPUState, gprh[i]), p);
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        p += (i < 10) ? 4 : 5;
#endif
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        sprintf(p, "fp%d", i);
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        cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
                                            offsetof(CPUState, fpr[i]), p);
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        p += (i < 10) ? 4 : 5;
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        sprintf(p, "avr%dH", i);
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#ifdef WORDS_BIGENDIAN
        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
                                             offsetof(CPUState, avr[i].u64[0]), p);
#else
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        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
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                                             offsetof(CPUState, avr[i].u64[1]), p);
#endif
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        p += (i < 10) ? 6 : 7;
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        sprintf(p, "avr%dL", i);
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#ifdef WORDS_BIGENDIAN
        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
                                             offsetof(CPUState, avr[i].u64[1]), p);
#else
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        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
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                                             offsetof(CPUState, avr[i].u64[0]), p);
#endif
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        p += (i < 10) ? 6 : 7;
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    }
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    cpu_nip = tcg_global_mem_new(TCG_AREG0,
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                                 offsetof(CPUState, nip), "nip");

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    cpu_msr = tcg_global_mem_new(TCG_AREG0,
                                 offsetof(CPUState, msr), "msr");

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    cpu_ctr = tcg_global_mem_new(TCG_AREG0,
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                                 offsetof(CPUState, ctr), "ctr");

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    cpu_lr = tcg_global_mem_new(TCG_AREG0,
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                                offsetof(CPUState, lr), "lr");

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    cpu_xer = tcg_global_mem_new(TCG_AREG0,
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                                 offsetof(CPUState, xer), "xer");

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    cpu_reserve = tcg_global_mem_new(TCG_AREG0,
                                     offsetof(CPUState, reserve), "reserve");

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    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
                                       offsetof(CPUState, fpscr), "fpscr");
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    cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
                                             offsetof(CPUState, access_type), "access_type");

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    /* register helpers */
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#define GEN_HELPER 2
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#include "helper.h"

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    done_init = 1;
}

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/* internal defines */
typedef struct DisasContext {
    struct TranslationBlock *tb;
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    target_ulong nip;
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    uint32_t opcode;
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    uint32_t exception;
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    /* Routine used to access memory */
    int mem_idx;
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    int access_type;
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    /* Translation flags */
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    int le_mode;
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#if defined(TARGET_PPC64)
    int sf_mode;
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#endif
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    int fpu_enabled;
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    int altivec_enabled;
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    int spe_enabled;
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    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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    int singlestep_enabled;
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} DisasContext;

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struct opc_handler_t {
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    /* invalid bits */
    uint32_t inval;
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    /* instruction type */
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    uint64_t type;
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    /* handler */
    void (*handler)(DisasContext *ctx);
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#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
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    const char *oname;
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#endif
#if defined(DO_PPC_STATISTICS)
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    uint64_t count;
#endif
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};
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static always_inline void gen_reset_fpstatus (void)
{
#ifdef CONFIG_SOFTFLOAT
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    gen_helper_reset_fpstatus();
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#endif
}

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static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
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{
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    TCGv_i32 t0 = tcg_temp_new_i32();
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    if (set_fprf != 0) {
        /* This case might be optimized later */
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        tcg_gen_movi_i32(t0, 1);
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        gen_helper_compute_fprf(t0, arg, t0);
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        if (unlikely(set_rc)) {
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            tcg_gen_mov_i32(cpu_crf[1], t0);
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        }
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        gen_helper_float_check_status();
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    } else if (unlikely(set_rc)) {
        /* We always need to compute fpcc */
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        tcg_gen_movi_i32(t0, 0);
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        gen_helper_compute_fprf(t0, arg, t0);
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        tcg_gen_mov_i32(cpu_crf[1], t0);
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    }
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    tcg_temp_free_i32(t0);
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}

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static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
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{
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    if (ctx->access_type != access_type) {
        tcg_gen_movi_i32(cpu_access_type, access_type);
        ctx->access_type = access_type;
    }
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}

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static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
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{
#if defined(TARGET_PPC64)
    if (ctx->sf_mode)
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        tcg_gen_movi_tl(cpu_nip, nip);
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    else
#endif
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        tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
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}

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static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
{
    TCGv_i32 t0, t1;
    if (ctx->exception == POWERPC_EXCP_NONE) {
        gen_update_nip(ctx, ctx->nip);
    }
    t0 = tcg_const_i32(excp);
    t1 = tcg_const_i32(error);
    gen_helper_raise_exception_err(t0, t1);
    tcg_temp_free_i32(t0);
    tcg_temp_free_i32(t1);
    ctx->exception = (excp);
}
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static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
{
    TCGv_i32 t0;
    if (ctx->exception == POWERPC_EXCP_NONE) {
        gen_update_nip(ctx, ctx->nip);
    }
    t0 = tcg_const_i32(excp);
    gen_helper_raise_exception(t0);
    tcg_temp_free_i32(t0);
    ctx->exception = (excp);
}
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static always_inline void gen_debug_exception (DisasContext *ctx)
{
    TCGv_i32 t0;
    gen_update_nip(ctx, ctx->nip);
    t0 = tcg_const_i32(EXCP_DEBUG);
    gen_helper_raise_exception(t0);
    tcg_temp_free_i32(t0);
}
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static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
{
    gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
}
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/* Stop translation */
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static always_inline void gen_stop_exception (DisasContext *ctx)
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{
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    gen_update_nip(ctx, ctx->nip);
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    ctx->exception = POWERPC_EXCP_STOP;
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}

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/* No need to update nip here, as execution flow will change */
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static always_inline void gen_sync_exception (DisasContext *ctx)
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{
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    ctx->exception = POWERPC_EXCP_SYNC;
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}

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#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
static void gen_##name (DisasContext *ctx);                                   \
GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
static void gen_##name (DisasContext *ctx)

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#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
static void gen_##name (DisasContext *ctx);                                   \
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \
static void gen_##name (DisasContext *ctx)

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typedef struct opcode_t {
    unsigned char opc1, opc2, opc3;
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#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
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    unsigned char pad[5];
#else
    unsigned char pad[1];
#endif
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    opc_handler_t handler;
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    const char *oname;
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} opcode_t;

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/*****************************************************************************/
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/***                           Instruction decoding                        ***/
#define EXTRACT_HELPER(name, shift, nb)                                       \
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static always_inline uint32_t name (uint32_t opcode)                          \
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{                                                                             \
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
}

#define EXTRACT_SHELPER(name, shift, nb)                                      \
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static always_inline int32_t name (uint32_t opcode)                           \
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{                                                                             \
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    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
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}

/* Opcode part 1 */
EXTRACT_HELPER(opc1, 26, 6);
/* Opcode part 2 */
EXTRACT_HELPER(opc2, 1, 5);
/* Opcode part 3 */
EXTRACT_HELPER(opc3, 6, 5);
/* Update Cr0 flags */
EXTRACT_HELPER(Rc, 0, 1);
/* Destination */
EXTRACT_HELPER(rD, 21, 5);
/* Source */
EXTRACT_HELPER(rS, 21, 5);
/* First operand */
EXTRACT_HELPER(rA, 16, 5);
/* Second operand */
EXTRACT_HELPER(rB, 11, 5);
/* Third operand */
EXTRACT_HELPER(rC, 6, 5);
/***                               Get CRn                                 ***/
EXTRACT_HELPER(crfD, 23, 3);
EXTRACT_HELPER(crfS, 18, 3);
EXTRACT_HELPER(crbD, 21, 5);
EXTRACT_HELPER(crbA, 16, 5);
EXTRACT_HELPER(crbB, 11, 5);
/* SPR / TBL */
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EXTRACT_HELPER(_SPR, 11, 10);
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static always_inline uint32_t SPR (uint32_t opcode)
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{
    uint32_t sprn = _SPR(opcode);

    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
}
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/***                              Get constants                            ***/
EXTRACT_HELPER(IMM, 12, 8);
/* 16 bits signed immediate value */
EXTRACT_SHELPER(SIMM, 0, 16);
/* 16 bits unsigned immediate value */
EXTRACT_HELPER(UIMM, 0, 16);
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/* 5 bits signed immediate value */
EXTRACT_HELPER(SIMM5, 16, 5);
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/* 5 bits signed immediate value */
EXTRACT_HELPER(UIMM5, 16, 5);
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/* Bit count */
EXTRACT_HELPER(NB, 11, 5);
/* Shift count */
EXTRACT_HELPER(SH, 11, 5);
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/* Vector shift count */
EXTRACT_HELPER(VSH, 6, 4);
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/* Mask start */
EXTRACT_HELPER(MB, 6, 5);
/* Mask end */
EXTRACT_HELPER(ME, 1, 5);
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/* Trap operand */
EXTRACT_HELPER(TO, 21, 5);
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EXTRACT_HELPER(CRM, 12, 8);
EXTRACT_HELPER(FM, 17, 8);
EXTRACT_HELPER(SR, 16, 4);
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EXTRACT_HELPER(FPIMM, 12, 4);
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/***                            Jump target decoding                       ***/
/* Displacement */
EXTRACT_SHELPER(d, 0, 16);
/* Immediate address */
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static always_inline target_ulong LI (uint32_t opcode)
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{
    return (opcode >> 0) & 0x03FFFFFC;
}

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static always_inline uint32_t BD (uint32_t opcode)
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{
    return (opcode >> 0) & 0xFFFC;
}

EXTRACT_HELPER(BO, 21, 5);
EXTRACT_HELPER(BI, 16, 5);
/* Absolute/relative address */
EXTRACT_HELPER(AA, 1, 1);
/* Link */
EXTRACT_HELPER(LK, 0, 1);

/* Create a mask between <start> and <end> bits */
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static always_inline target_ulong MASK (uint32_t start, uint32_t end)
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{
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    target_ulong ret;
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#if defined(TARGET_PPC64)
    if (likely(start == 0)) {
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        ret = UINT64_MAX << (63 - end);
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    } else if (likely(end == 63)) {
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        ret = UINT64_MAX >> start;
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    }
#else
    if (likely(start == 0)) {
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        ret = UINT32_MAX << (31  - end);
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    } else if (likely(end == 31)) {
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        ret = UINT32_MAX >> start;
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    }
#endif
    else {
        ret = (((target_ulong)(-1ULL)) >> (start)) ^
            (((target_ulong)(-1ULL) >> (end)) >> 1);
        if (unlikely(start > end))
            return ~ret;
    }
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    return ret;
}

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/*****************************************************************************/
/* PowerPC Instructions types definitions                                    */
enum {
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    PPC_NONE           = 0x0000000000000000ULL,
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    /* PowerPC base instructions set                                         */
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    PPC_INSNS_BASE     = 0x0000000000000001ULL,
    /*   integer operations instructions                                     */
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#define PPC_INTEGER PPC_INSNS_BASE
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    /*   flow control instructions                                           */
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#define PPC_FLOW    PPC_INSNS_BASE
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    /*   virtual memory instructions                                         */
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#define PPC_MEM     PPC_INSNS_BASE
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    /*   ld/st with reservation instructions                                 */
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#define PPC_RES     PPC_INSNS_BASE
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    /*   spr/msr access instructions                                         */
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#define PPC_MISC    PPC_INSNS_BASE
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    /* Deprecated instruction sets                                           */
    /*   Original POWER instruction set                                      */
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    PPC_POWER          = 0x0000000000000002ULL,
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    /*   POWER2 instruction set extension                                    */
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    PPC_POWER2         = 0x0000000000000004ULL,
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    /*   Power RTC support                                                   */
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    PPC_POWER_RTC      = 0x0000000000000008ULL,
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    /*   Power-to-PowerPC bridge (601)                                       */
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    PPC_POWER_BR       = 0x0000000000000010ULL,
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    /* 64 bits PowerPC instruction set                                       */
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    PPC_64B            = 0x0000000000000020ULL,
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    /*   New 64 bits extensions (PowerPC 2.0x)                               */
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    PPC_64BX           = 0x0000000000000040ULL,
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    /*   64 bits hypervisor extensions                                       */
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    PPC_64H            = 0x0000000000000080ULL,
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    /*   New wait instruction (PowerPC 2.0x)                                 */
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    PPC_WAIT           = 0x0000000000000100ULL,
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    /*   Time base mftb instruction                                          */
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    PPC_MFTB           = 0x0000000000000200ULL,
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    /* Fixed-point unit extensions                                           */
    /*   PowerPC 602 specific                                                */
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    PPC_602_SPEC       = 0x0000000000000400ULL,
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    /*   isel instruction                                                    */
    PPC_ISEL           = 0x0000000000000800ULL,
    /*   popcntb instruction                                                 */
    PPC_POPCNTB        = 0x0000000000001000ULL,
    /*   string load / store                                                 */
    PPC_STRING         = 0x0000000000002000ULL,
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    /* Floating-point unit extensions                                        */
    /*   Optional floating point instructions                                */
    PPC_FLOAT          = 0x0000000000010000ULL,
    /* New floating-point extensions (PowerPC 2.0x)                          */
    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,

    /* Vector/SIMD extensions                                                */
    /*   Altivec support                                                     */
    PPC_ALTIVEC        = 0x0000000001000000ULL,
    /*   PowerPC 2.03 SPE extension                                          */
511
    PPC_SPE            = 0x0000000002000000ULL,
512
    /*   PowerPC 2.03 SPE floating-point extension                           */
513
    PPC_SPEFPU         = 0x0000000004000000ULL,
514

515
    /* Optional memory control instructions                                  */
516 517 518 519 520 521 522 523 524
    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
    /*   sync instruction                                                    */
    PPC_MEM_SYNC       = 0x0000000080000000ULL,
    /*   eieio instruction                                                   */
    PPC_MEM_EIEIO      = 0x0000000100000000ULL,

    /* Cache control instructions                                            */
525
    PPC_CACHE          = 0x0000000200000000ULL,
526
    /*   icbi instruction                                                    */
527
    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
528
    /*   dcbz instruction with fixed cache line size                         */
529
    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
530
    /*   dcbz instruction with tunable cache line size                       */
531
    PPC_CACHE_DCBZT    = 0x0000001000000000ULL,
532
    /*   dcba instruction                                                    */
533 534 535
    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
    /*   Freescale cache locking instructions                                */
    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
536 537 538

    /* MMU related extensions                                                */
    /*   external control instructions                                       */
539
    PPC_EXTERN         = 0x0000010000000000ULL,
540
    /*   segment register access instructions                                */
541
    PPC_SEGMENT        = 0x0000020000000000ULL,
542
    /*   PowerPC 6xx TLB management instructions                             */
543
    PPC_6xx_TLB        = 0x0000040000000000ULL,
544
    /* PowerPC 74xx TLB management instructions                              */
545
    PPC_74xx_TLB       = 0x0000080000000000ULL,
546
    /*   PowerPC 40x TLB management instructions                             */
547
    PPC_40x_TLB        = 0x0000100000000000ULL,
548
    /*   segment register access instructions for PowerPC 64 "bridge"        */
549
    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
550
    /*   SLB management                                                      */
551
    PPC_SLBI           = 0x0000400000000000ULL,
552

553
    /* Embedded PowerPC dedicated instructions                               */
554
    PPC_WRTEE          = 0x0001000000000000ULL,
555
    /* PowerPC 40x exception model                                           */
556
    PPC_40x_EXCP       = 0x0002000000000000ULL,
557
    /* PowerPC 405 Mac instructions                                          */
558
    PPC_405_MAC        = 0x0004000000000000ULL,
559
    /* PowerPC 440 specific instructions                                     */
560
    PPC_440_SPEC       = 0x0008000000000000ULL,
561
    /* BookE (embedded) PowerPC specification                                */
562 563 564 565 566 567 568
    PPC_BOOKE          = 0x0010000000000000ULL,
    /* mfapidi instruction                                                   */
    PPC_MFAPIDI        = 0x0020000000000000ULL,
    /* tlbiva instruction                                                    */
    PPC_TLBIVA         = 0x0040000000000000ULL,
    /* tlbivax instruction                                                   */
    PPC_TLBIVAX        = 0x0080000000000000ULL,
569
    /* PowerPC 4xx dedicated instructions                                    */
570
    PPC_4xx_COMMON     = 0x0100000000000000ULL,
571
    /* PowerPC 40x ibct instructions                                         */
572
    PPC_40x_ICBT       = 0x0200000000000000ULL,
573
    /* rfmci is not implemented in all BookE PowerPC                         */
574 575 576 577 578 579 580
    PPC_RFMCI          = 0x0400000000000000ULL,
    /* rfdi instruction                                                      */
    PPC_RFDI           = 0x0800000000000000ULL,
    /* DCR accesses                                                          */
    PPC_DCR            = 0x1000000000000000ULL,
    /* DCR extended accesse                                                  */
    PPC_DCRX           = 0x2000000000000000ULL,
581
    /* user-mode DCR access, implemented in PowerPC 460                      */
582
    PPC_DCRUX          = 0x4000000000000000ULL,
583 584 585 586
};

/*****************************************************************************/
/* PowerPC instructions table                                                */
587 588 589 590 591
#if HOST_LONG_BITS == 64
#define OPC_ALIGN 8
#else
#define OPC_ALIGN 4
#endif
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#if defined(__APPLE__)
593
#define OPCODES_SECTION                                                       \
594
    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
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#else
596
#define OPCODES_SECTION                                                       \
597
    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
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#endif

600
#if defined(DO_PPC_STATISTICS)
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#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
602
OPCODES_SECTION opcode_t opc_##name = {                                       \
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    .opc1 = op1,                                                              \
    .opc2 = op2,                                                              \
    .opc3 = op3,                                                              \
606
    .pad  = { 0, },                                                           \
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    .handler = {                                                              \
        .inval   = invl,                                                      \
609
        .type = _typ,                                                         \
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        .handler = &gen_##name,                                               \
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        .oname = stringify(name),                                             \
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    },                                                                        \
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    .oname = stringify(name),                                                 \
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}
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#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
OPCODES_SECTION opcode_t opc_##name = {                                       \
    .opc1 = op1,                                                              \
    .opc2 = op2,                                                              \
    .opc3 = op3,                                                              \
    .pad  = { 0, },                                                           \
    .handler = {                                                              \
        .inval   = invl,                                                      \
        .type = _typ,                                                         \
        .handler = &gen_##name,                                               \
        .oname = onam,                                                        \
    },                                                                        \
    .oname = onam,                                                            \
}
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#else
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
OPCODES_SECTION opcode_t opc_##name = {                                       \
    .opc1 = op1,                                                              \
    .opc2 = op2,                                                              \
    .opc3 = op3,                                                              \
    .pad  = { 0, },                                                           \
    .handler = {                                                              \
        .inval   = invl,                                                      \
        .type = _typ,                                                         \
        .handler = &gen_##name,                                               \
    },                                                                        \
    .oname = stringify(name),                                                 \
}
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#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
OPCODES_SECTION opcode_t opc_##name = {                                       \
    .opc1 = op1,                                                              \
    .opc2 = op2,                                                              \
    .opc3 = op3,                                                              \
    .pad  = { 0, },                                                           \
    .handler = {                                                              \
        .inval   = invl,                                                      \
        .type = _typ,                                                         \
        .handler = &gen_##name,                                               \
    },                                                                        \
    .oname = onam,                                                            \
}
656
#endif
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#define GEN_OPCODE_MARK(name)                                                 \
659
OPCODES_SECTION opcode_t opc_##name = {                                       \
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    .opc1 = 0xFF,                                                             \
    .opc2 = 0xFF,                                                             \
    .opc3 = 0xFF,                                                             \
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    .pad  = { 0, },                                                           \
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    .handler = {                                                              \
        .inval   = 0x00000000,                                                \
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        .type = 0x00,                                                         \
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        .handler = NULL,                                                      \
    },                                                                        \
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    .oname = stringify(name),                                                 \
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}

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/* SPR load/store helpers */
static always_inline void gen_load_spr(TCGv t, int reg)
{
    tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
}

static always_inline void gen_store_spr(int reg, TCGv t)
{
    tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
}

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/* Start opcode list */
GEN_OPCODE_MARK(start);

/* Invalid instruction */
687 688
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
{
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    gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
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}

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static opc_handler_t invalid_handler = {
    .inval   = 0xFFFFFFFF,
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    .type    = PPC_NONE,
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    .handler = gen_invalid,
};

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/***                           Integer comparison                          ***/

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static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
701 702 703
{
    int l1, l2, l3;

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    tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
    tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
706 707 708 709 710 711
    tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);

    l1 = gen_new_label();
    l2 = gen_new_label();
    l3 = gen_new_label();
    if (s) {
712 713
        tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
        tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
714
    } else {
715 716
        tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
        tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
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    }
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
    tcg_gen_br(l3);
    gen_set_label(l1);
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
    tcg_gen_br(l3);
    gen_set_label(l2);
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
    gen_set_label(l3);
}

728
static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
729
{
730 731 732
    TCGv t0 = tcg_const_local_tl(arg1);
    gen_op_cmp(arg0, t0, s, crf);
    tcg_temp_free(t0);
733 734 735
}

#if defined(TARGET_PPC64)
736
static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
737
{
738
    TCGv t0, t1;
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    t0 = tcg_temp_local_new();
    t1 = tcg_temp_local_new();
741
    if (s) {
742 743
        tcg_gen_ext32s_tl(t0, arg0);
        tcg_gen_ext32s_tl(t1, arg1);
744
    } else {
745 746
        tcg_gen_ext32u_tl(t0, arg0);
        tcg_gen_ext32u_tl(t1, arg1);
747
    }
748 749 750
    gen_op_cmp(t0, t1, s, crf);
    tcg_temp_free(t1);
    tcg_temp_free(t0);
751 752
}

753
static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
754
{
755 756 757
    TCGv t0 = tcg_const_local_tl(arg1);
    gen_op_cmp32(arg0, t0, s, crf);
    tcg_temp_free(t0);
758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828
}
#endif

static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
{
#if defined(TARGET_PPC64)
    if (!(ctx->sf_mode))
        gen_op_cmpi32(reg, 0, 1, 0);
    else
#endif
        gen_op_cmpi(reg, 0, 1, 0);
}

/* cmp */
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
{
#if defined(TARGET_PPC64)
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
                     1, crfD(ctx->opcode));
    else
#endif
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
                   1, crfD(ctx->opcode));
}

/* cmpi */
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
{
#if defined(TARGET_PPC64)
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
                      1, crfD(ctx->opcode));
    else
#endif
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
                    1, crfD(ctx->opcode));
}

/* cmpl */
GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
{
#if defined(TARGET_PPC64)
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
                     0, crfD(ctx->opcode));
    else
#endif
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
                   0, crfD(ctx->opcode));
}

/* cmpli */
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
{
#if defined(TARGET_PPC64)
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
                      0, crfD(ctx->opcode));
    else
#endif
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
                    0, crfD(ctx->opcode));
}

/* isel (PowerPC 2.03 specification) */
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
{
    int l1, l2;
    uint32_t bi = rC(ctx->opcode);
    uint32_t mask;
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    TCGv_i32 t0;
830 831 832 833 834

    l1 = gen_new_label();
    l2 = gen_new_label();

    mask = 1 << (3 - (bi & 0x03));
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    t0 = tcg_temp_new_i32();
836 837
    tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
    tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
838 839 840 841 842 843 844 845
    if (rA(ctx->opcode) == 0)
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
    else
        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
    gen_set_label(l2);
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    tcg_temp_free_i32(t0);
847 848
}

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/***                           Integer arithmetic                          ***/

851 852 853 854
static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
{
    int l1;
    TCGv t0;
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856 857 858
    l1 = gen_new_label();
    /* Start with XER OV disabled, the most likely case */
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
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    t0 = tcg_temp_local_new();
860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880
    tcg_gen_xor_tl(t0, arg0, arg1);
#if defined(TARGET_PPC64)
    if (!ctx->sf_mode)
        tcg_gen_ext32s_tl(t0, t0);
#endif
    if (sub)
        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
    else
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
    tcg_gen_xor_tl(t0, arg1, arg2);
#if defined(TARGET_PPC64)
    if (!ctx->sf_mode)
        tcg_gen_ext32s_tl(t0, t0);
#endif
    if (sub)
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
    else
        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
    gen_set_label(l1);
    tcg_temp_free(t0);
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}

883 884 885
static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
{
    int l1 = gen_new_label();
886 887

#if defined(TARGET_PPC64)
888 889
    if (!(ctx->sf_mode)) {
        TCGv t0, t1;
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890 891
        t0 = tcg_temp_new();
        t1 = tcg_temp_new();
892

893 894 895 896
        tcg_gen_ext32u_tl(t0, arg1);
        tcg_gen_ext32u_tl(t1, arg2);
        if (sub) {
            tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
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        } else {
898 899
            tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
        }
900 901 902 903
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
        gen_set_label(l1);
        tcg_temp_free(t0);
        tcg_temp_free(t1);
904 905
    } else
#endif
906 907 908 909 910 911 912 913
    {
        if (sub) {
            tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
        } else {
            tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
        }
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
        gen_set_label(l1);
914
    }
915 916
}

917 918 919 920 921
/* Common add function */
static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
                                           int add_ca, int compute_ca, int compute_ov)
{
    TCGv t0, t1;
922

923
    if ((!compute_ca && !compute_ov) ||
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        (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2)))  {
925 926
        t0 = ret;
    } else {
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        t0 = tcg_temp_local_new();
928
    }
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930
    if (add_ca) {
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        t1 = tcg_temp_local_new();
932 933 934
        tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
        tcg_gen_shri_tl(t1, t1, XER_CA);
    }
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936 937 938 939 940 941 942 943 944 945
    if (compute_ca && compute_ov) {
        /* Start with XER CA and OV disabled, the most likely case */
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
    } else if (compute_ca) {
        /* Start with XER CA disabled, the most likely case */
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
    } else if (compute_ov) {
        /* Start with XER OV disabled, the most likely case */
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
    }
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947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963
    tcg_gen_add_tl(t0, arg1, arg2);

    if (compute_ca) {
        gen_op_arith_compute_ca(ctx, t0, arg1, 0);
    }
    if (add_ca) {
        tcg_gen_add_tl(t0, t0, t1);
        gen_op_arith_compute_ca(ctx, t0, t1, 0);
        tcg_temp_free(t1);
    }
    if (compute_ov) {
        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
    }

    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, t0);

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    if (!TCGV_EQUAL(t0, ret)) {
965 966 967
        tcg_gen_mov_tl(ret, t0);
        tcg_temp_free(t0);
    }
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}
969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005
/* Add functions with two operands */
#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER)                  \
{                                                                             \
    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
                     add_ca, compute_ca, compute_ov);                         \
}
/* Add functions with one operand and one immediate */
#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \
                                add_ca, compute_ca, compute_ov)               \
GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER)                  \
{                                                                             \
    TCGv t0 = tcg_const_local_tl(const_val);                                  \
    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
                     cpu_gpr[rA(ctx->opcode)], t0,                            \
                     add_ca, compute_ca, compute_ov);                         \
    tcg_temp_free(t0);                                                        \
}

/* add  add.  addo  addo. */
GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
/* addc  addc.  addco  addco. */
GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
/* adde  adde.  addeo  addeo. */
GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
/* addme  addme.  addmeo  addmeo.  */
GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
/* addze  addze.  addzeo  addzeo.*/
GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
/* addi */
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1006
{
1007 1008 1009 1010 1011 1012 1013 1014
    target_long simm = SIMM(ctx->opcode);

    if (rA(ctx->opcode) == 0) {
        /* li case */
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
    } else {
        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
    }
1015
}
1016 1017 1018
/* addic  addic.*/
static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
                                        int compute_Rc0)
1019
{
1020 1021 1022 1023 1024 1025
    target_long simm = SIMM(ctx->opcode);

    /* Start with XER CA and OV disabled, the most likely case */
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));

    if (likely(simm != 0)) {
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        TCGv t0 = tcg_temp_local_new();
1027 1028 1029 1030 1031 1032 1033 1034 1035 1036
        tcg_gen_addi_tl(t0, arg1, simm);
        gen_op_arith_compute_ca(ctx, t0, arg1, 0);
        tcg_gen_mov_tl(ret, t0);
        tcg_temp_free(t0);
    } else {
        tcg_gen_mov_tl(ret, arg1);
    }
    if (compute_Rc0) {
        gen_set_Rc0(ctx, ret);
    }
1037
}
1038
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1039
{
1040
    gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1041
}
1042
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1043
{
1044
    gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1045
}
1046 1047
/* addis */
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1048
{
1049 1050 1051 1052 1053 1054 1055 1056
    target_long simm = SIMM(ctx->opcode);

    if (rA(ctx->opcode) == 0) {
        /* lis case */
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
    } else {
        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
    }
1057
}
1058 1059 1060

static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
                                             int sign, int compute_ov)
1061
{
1062 1063
    int l1 = gen_new_label();
    int l2 = gen_new_label();
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1064 1065
    TCGv_i32 t0 = tcg_temp_local_new_i32();
    TCGv_i32 t1 = tcg_temp_local_new_i32();
1066

1067 1068 1069
    tcg_gen_trunc_tl_i32(t0, arg1);
    tcg_gen_trunc_tl_i32(t1, arg2);
    tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1070
    if (sign) {
1071 1072 1073
        int l3 = gen_new_label();
        tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
        tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1074
        gen_set_label(l3);
1075
        tcg_gen_div_i32(t0, t0, t1);
1076
    } else {
1077
        tcg_gen_divu_i32(t0, t0, t1);
1078 1079 1080 1081 1082 1083 1084
    }
    if (compute_ov) {
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
    }
    tcg_gen_br(l2);
    gen_set_label(l1);
    if (sign) {
1085
        tcg_gen_sari_i32(t0, t0, 31);
1086 1087 1088 1089 1090 1091 1092
    } else {
        tcg_gen_movi_i32(t0, 0);
    }
    if (compute_ov) {
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
    }
    gen_set_label(l2);
1093
    tcg_gen_extu_i32_tl(ret, t0);
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    tcg_temp_free_i32(t0);
    tcg_temp_free_i32(t1);
1096 1097
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, ret);
1098
}
1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112
/* Div functions */
#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)                  \
{                                                                             \
    gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)],                          \
                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
                     sign, compute_ov);                                       \
}
/* divwu  divwu.  divwuo  divwuo.   */
GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
/* divw  divw.  divwo  divwo.   */
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1113
#if defined(TARGET_PPC64)
1114 1115
static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
                                             int sign, int compute_ov)
1116
{
1117 1118
    int l1 = gen_new_label();
    int l2 = gen_new_label();
1119 1120 1121

    tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
    if (sign) {
1122
        int l3 = gen_new_label();
1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145
        tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
        tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
        gen_set_label(l3);
        tcg_gen_div_i64(ret, arg1, arg2);
    } else {
        tcg_gen_divu_i64(ret, arg1, arg2);
    }
    if (compute_ov) {
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
    }
    tcg_gen_br(l2);
    gen_set_label(l1);
    if (sign) {
        tcg_gen_sari_i64(ret, arg1, 63);
    } else {
        tcg_gen_movi_i64(ret, 0);
    }
    if (compute_ov) {
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
    }
    gen_set_label(l2);
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, ret);
1146
}
1147 1148 1149
#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)                      \
{                                                                             \
1150 1151 1152
    gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)],                          \
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
                      sign, compute_ov);                                      \
1153 1154 1155 1156 1157 1158 1159
}
/* divwu  divwu.  divwuo  divwuo.   */
GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
/* divw  divw.  divwo  divwo.   */
GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1160
#endif
1161 1162 1163

/* mulhw  mulhw. */
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1164
{
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    TCGv_i64 t0, t1;
1166

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1167 1168
    t0 = tcg_temp_new_i64();
    t1 = tcg_temp_new_i64();
1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180
#if defined(TARGET_PPC64)
    tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
    tcg_gen_mul_i64(t0, t0, t1);
    tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
#else
    tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
    tcg_gen_mul_i64(t0, t0, t1);
    tcg_gen_shri_i64(t0, t0, 32);
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
#endif
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1181 1182
    tcg_temp_free_i64(t0);
    tcg_temp_free_i64(t1);
1183 1184
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1185
}
1186 1187
/* mulhwu  mulhwu.  */
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1188
{
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1189
    TCGv_i64 t0, t1;
1190

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1191 1192
    t0 = tcg_temp_new_i64();
    t1 = tcg_temp_new_i64();
1193
#if defined(TARGET_PPC64)
1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204
    tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
    tcg_gen_mul_i64(t0, t0, t1);
    tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
#else
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
    tcg_gen_mul_i64(t0, t0, t1);
    tcg_gen_shri_i64(t0, t0, 32);
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
#endif
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1205 1206
    tcg_temp_free_i64(t0);
    tcg_temp_free_i64(t1);
1207 1208
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1209
}
1210 1211
/* mullw  mullw. */
GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1212
{
1213 1214
    tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
                   cpu_gpr[rB(ctx->opcode)]);
1215
    tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1216 1217
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1218
}
1219 1220
/* mullwo  mullwo. */
GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1221
{
1222
    int l1;
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1223
    TCGv_i64 t0, t1;
1224

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1225 1226
    t0 = tcg_temp_new_i64();
    t1 = tcg_temp_new_i64();
1227 1228 1229 1230 1231 1232 1233 1234 1235
    l1 = gen_new_label();
    /* Start with XER OV disabled, the most likely case */
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
#if defined(TARGET_PPC64)
    tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
#else
    tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1236
#endif
1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
    tcg_gen_mul_i64(t0, t0, t1);
#if defined(TARGET_PPC64)
    tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
#else
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_gen_ext32s_i64(t1, t0);
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
#endif
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
    gen_set_label(l1);
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1248 1249
    tcg_temp_free_i64(t0);
    tcg_temp_free_i64(t1);
1250 1251
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1252
}
1253 1254
/* mulli */
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1255
{
1256 1257
    tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
                    SIMM(ctx->opcode));
1258 1259
}
#if defined(TARGET_PPC64)
1260 1261 1262
#define GEN_INT_ARITH_MUL_HELPER(name, opc3)                                  \
GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)                      \
{                                                                             \
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1263
    gen_helper_##name (cpu_gpr[rD(ctx->opcode)],                              \
1264 1265 1266
                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);   \
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);                           \
1267
}
1268 1269 1270 1271 1272 1273
/* mulhd  mulhd. */
GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
/* mulhdu  mulhdu. */
GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
/* mulld  mulld. */
GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1274
{
1275 1276 1277 1278
    tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
                   cpu_gpr[rB(ctx->opcode)]);
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1279
}
1280 1281
/* mulldo  mulldo. */
GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1282
#endif
1283 1284

/* neg neg. nego nego. */
A
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1285
static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1286
{
A
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1287 1288
    int l1 = gen_new_label();
    int l2 = gen_new_label();
P
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1289
    TCGv t0 = tcg_temp_local_new();
1290
#if defined(TARGET_PPC64)
1291
    if (ctx->sf_mode) {
A
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1292
        tcg_gen_mov_tl(t0, arg1);
A
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1293 1294 1295 1296 1297
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
    } else
#endif
    {
        tcg_gen_ext32s_tl(t0, arg1);
1298 1299 1300 1301 1302 1303 1304 1305
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
    }
    tcg_gen_neg_tl(ret, arg1);
    if (ov_check) {
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
    }
    tcg_gen_br(l2);
    gen_set_label(l1);
A
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1306
    tcg_gen_mov_tl(ret, t0);
1307 1308 1309 1310
    if (ov_check) {
        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
    }
    gen_set_label(l2);
A
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1311
    tcg_temp_free(t0);
1312 1313 1314 1315
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, ret);
}
GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1316
{
A
aurel32 已提交
1317
    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1318
}
1319
GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
B
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1320
{
A
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1321
    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
B
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1322
}
1323 1324 1325 1326

/* Common subf function */
static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
                                            int add_ca, int compute_ca, int compute_ov)
B
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1327
{
1328
    TCGv t0, t1;
1329

1330
    if ((!compute_ca && !compute_ov) ||
P
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1331
        (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2)))  {
1332
        t0 = ret;
J
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1333
    } else {
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1334
        t0 = tcg_temp_local_new();
1335
    }
1336

1337
    if (add_ca) {
P
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1338
        t1 = tcg_temp_local_new();
1339 1340
        tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
        tcg_gen_shri_tl(t1, t1, XER_CA);
1341
    }
B
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1342

1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360
    if (compute_ca && compute_ov) {
        /* Start with XER CA and OV disabled, the most likely case */
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
    } else if (compute_ca) {
        /* Start with XER CA disabled, the most likely case */
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
    } else if (compute_ov) {
        /* Start with XER OV disabled, the most likely case */
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
    }

    if (add_ca) {
        tcg_gen_not_tl(t0, arg1);
        tcg_gen_add_tl(t0, t0, arg2);
        gen_op_arith_compute_ca(ctx, t0, arg2, 0);
        tcg_gen_add_tl(t0, t0, t1);
        gen_op_arith_compute_ca(ctx, t0, t1, 0);
        tcg_temp_free(t1);
B
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1361
    } else {
1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373
        tcg_gen_sub_tl(t0, arg2, arg1);
        if (compute_ca) {
            gen_op_arith_compute_ca(ctx, t0, arg2, 1);
        }
    }
    if (compute_ov) {
        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
    }

    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, t0);

P
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    if (!TCGV_EQUAL(t0, ret)) {
1375 1376
        tcg_gen_mov_tl(ret, t0);
        tcg_temp_free(t0);
B
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1377 1378
    }
}
1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412
/* Sub functions with Two operands functions */
#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER)                  \
{                                                                             \
    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
                      add_ca, compute_ca, compute_ov);                        \
}
/* Sub functions with one operand and one immediate */
#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
                                add_ca, compute_ca, compute_ov)               \
GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER)                  \
{                                                                             \
    TCGv t0 = tcg_const_local_tl(const_val);                                  \
    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
                      cpu_gpr[rA(ctx->opcode)], t0,                           \
                      add_ca, compute_ca, compute_ov);                        \
    tcg_temp_free(t0);                                                        \
}
/* subf  subf.  subfo  subfo. */
GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
/* subfc  subfc.  subfco  subfco. */
GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
/* subfe  subfe.  subfeo  subfo. */
GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
/* subfme  subfme.  subfmeo  subfmeo.  */
GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
/* subfze  subfze.  subfzeo  subfzeo.*/
GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
B
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1413 1414 1415
/* subfic */
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
1416 1417
    /* Start with XER CA and OV disabled, the most likely case */
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
P
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1418
    TCGv t0 = tcg_temp_local_new();
1419 1420 1421 1422 1423 1424
    TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
    tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
    gen_op_arith_compute_ca(ctx, t0, t1, 1);
    tcg_temp_free(t1);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free(t0);
B
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1425 1426 1427
}

/***                            Integer logical                            ***/
1428 1429
#define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)                          \
B
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1430
{                                                                             \
1431 1432
    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],                \
       cpu_gpr[rB(ctx->opcode)]);                                             \
1433
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1434
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
B
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1435 1436
}

1437
#define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
1438
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)                          \
B
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1439
{                                                                             \
1440
    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);               \
1441
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1442
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
B
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1443 1444 1445
}

/* and & and. */
1446
GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
B
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1447
/* andc & andc. */
1448
GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
B
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1449
/* andi. */
1450
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
B
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{
1452 1453
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
B
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1454 1455
}
/* andis. */
1456
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
B
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1457
{
1458 1459
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
B
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1460 1461
}
/* cntlzw */
1462 1463
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
{
P
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1464
    gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1465
    if (unlikely(Rc(ctx->opcode) != 0))
P
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1466
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1467
}
B
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1468
/* eqv & eqv. */
1469
GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
B
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1470
/* extsb & extsb. */
1471
GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
B
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1472
/* extsh & extsh. */
1473
GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
B
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1474
/* nand & nand. */
1475
GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
B
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1476
/* nor & nor. */
1477
GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
B
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1478
/* or & or. */
1479 1480
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
{
1481 1482 1483 1484 1485 1486 1487
    int rs, ra, rb;

    rs = rS(ctx->opcode);
    ra = rA(ctx->opcode);
    rb = rB(ctx->opcode);
    /* Optimisation for mr. ri case */
    if (rs != ra || rs != rb) {
1488 1489 1490 1491
        if (rs != rb)
            tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
        else
            tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1492
        if (unlikely(Rc(ctx->opcode) != 0))
1493
            gen_set_Rc0(ctx, cpu_gpr[ra]);
1494
    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1495
        gen_set_Rc0(ctx, cpu_gpr[rs]);
1496 1497
#if defined(TARGET_PPC64)
    } else {
1498 1499
        int prio = 0;

1500 1501 1502
        switch (rs) {
        case 1:
            /* Set process priority to low */
1503
            prio = 2;
1504 1505 1506
            break;
        case 6:
            /* Set process priority to medium-low */
1507
            prio = 3;
1508 1509 1510
            break;
        case 2:
            /* Set process priority to normal */
1511
            prio = 4;
1512
            break;
1513 1514
#if !defined(CONFIG_USER_ONLY)
        case 31:
A
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1515
            if (ctx->mem_idx > 0) {
1516
                /* Set process priority to very low */
1517
                prio = 1;
1518 1519 1520
            }
            break;
        case 5:
A
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1521
            if (ctx->mem_idx > 0) {
1522
                /* Set process priority to medium-hight */
1523
                prio = 5;
1524 1525 1526
            }
            break;
        case 3:
A
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1527
            if (ctx->mem_idx > 0) {
1528
                /* Set process priority to high */
1529
                prio = 6;
1530 1531 1532
            }
            break;
        case 7:
A
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1533
            if (ctx->mem_idx > 1) {
1534
                /* Set process priority to very high */
1535
                prio = 7;
1536 1537 1538
            }
            break;
#endif
1539 1540 1541 1542
        default:
            /* nop */
            break;
        }
1543
        if (prio) {
P
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1544
            TCGv t0 = tcg_temp_new();
1545
            gen_load_spr(t0, SPR_PPR);
1546 1547
            tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
            tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1548
            gen_store_spr(SPR_PPR, t0);
1549
            tcg_temp_free(t0);
1550
        }
1551
#endif
1552 1553
    }
}
B
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/* orc & orc. */
1555
GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
B
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1556
/* xor & xor. */
1557 1558 1559
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
{
    /* Optimisation for "set to zero" case */
1560
    if (rS(ctx->opcode) != rB(ctx->opcode))
A
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1561
        tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1562 1563
    else
        tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1564
    if (unlikely(Rc(ctx->opcode) != 0))
1565
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1566
}
B
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1567 1568 1569
/* ori */
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
1570
    target_ulong uimm = UIMM(ctx->opcode);
B
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1571

1572 1573
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
        /* NOP */
1574
        /* XXX: should handle special NOPs for POWER series */
1575
        return;
1576
    }
1577
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
B
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1578 1579 1580 1581
}
/* oris */
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
1582
    target_ulong uimm = UIMM(ctx->opcode);
B
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1583

1584 1585 1586
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
        /* NOP */
        return;
1587
    }
1588
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
B
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1589 1590 1591 1592
}
/* xori */
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
1593
    target_ulong uimm = UIMM(ctx->opcode);
1594 1595 1596 1597 1598

    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
        /* NOP */
        return;
    }
1599
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
B
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1600 1601 1602 1603
}
/* xoris */
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
1604
    target_ulong uimm = UIMM(ctx->opcode);
1605 1606 1607 1608 1609

    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
        /* NOP */
        return;
    }
1610
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
B
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1611
}
1612
/* popcntb : PowerPC 2.03 specification */
1613
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1614 1615 1616
{
#if defined(TARGET_PPC64)
    if (ctx->sf_mode)
P
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1617
        gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1618 1619
    else
#endif
P
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1620
        gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1621 1622 1623 1624
}

#if defined(TARGET_PPC64)
/* extsw & extsw. */
1625
GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1626
/* cntlzd */
1627 1628
GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
{
P
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1629
    gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1630 1631 1632
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
1633 1634
#endif

B
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1635 1636 1637 1638
/***                             Integer rotate                            ***/
/* rlwimi & rlwimi. */
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
1639
    uint32_t mb, me, sh;
B
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1640 1641 1642

    mb = MB(ctx->opcode);
    me = ME(ctx->opcode);
1643
    sh = SH(ctx->opcode);
1644 1645 1646 1647
    if (likely(sh == 0 && mb == 0 && me == 31)) {
        tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
    } else {
        target_ulong mask;
P
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1648 1649
        TCGv t1;
        TCGv t0 = tcg_temp_new();
1650
#if defined(TARGET_PPC64)
P
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1651 1652 1653 1654 1655
        TCGv_i32 t2 = tcg_temp_new_i32();
        tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
        tcg_gen_rotli_i32(t2, t2, sh);
        tcg_gen_extu_i32_i64(t0, t2);
        tcg_temp_free_i32(t2);
1656 1657 1658
#else
        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
#endif
1659
#if defined(TARGET_PPC64)
1660 1661
        mb += 32;
        me += 32;
1662
#endif
1663
        mask = MASK(mb, me);
P
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1664
        t1 = tcg_temp_new();
1665 1666 1667 1668 1669 1670
        tcg_gen_andi_tl(t0, t0, mask);
        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
        tcg_temp_free(t0);
        tcg_temp_free(t1);
    }
1671
    if (unlikely(Rc(ctx->opcode) != 0))
1672
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
B
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1673 1674 1675 1676 1677
}
/* rlwinm & rlwinm. */
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
    uint32_t mb, me, sh;
1678

B
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1679 1680 1681
    sh = SH(ctx->opcode);
    mb = MB(ctx->opcode);
    me = ME(ctx->opcode);
1682 1683 1684 1685 1686

    if (likely(mb == 0 && me == (31 - sh))) {
        if (likely(sh == 0)) {
            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
        } else {
P
pbrook 已提交
1687
            TCGv t0 = tcg_temp_new();
1688 1689 1690 1691
            tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
            tcg_gen_shli_tl(t0, t0, sh);
            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
            tcg_temp_free(t0);
B
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1692
        }
1693
    } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
P
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1694
        TCGv t0 = tcg_temp_new();
1695 1696 1697 1698 1699
        tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
        tcg_gen_shri_tl(t0, t0, mb);
        tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
        tcg_temp_free(t0);
    } else {
P
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1700
        TCGv t0 = tcg_temp_new();
1701
#if defined(TARGET_PPC64)
P
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1702
        TCGv_i32 t1 = tcg_temp_new_i32();
1703 1704 1705
        tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
        tcg_gen_rotli_i32(t1, t1, sh);
        tcg_gen_extu_i32_i64(t0, t1);
P
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1706
        tcg_temp_free_i32(t1);
1707 1708 1709
#else
        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
#endif
1710
#if defined(TARGET_PPC64)
1711 1712
        mb += 32;
        me += 32;
1713
#endif
1714 1715 1716
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
        tcg_temp_free(t0);
    }
1717
    if (unlikely(Rc(ctx->opcode) != 0))
1718
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
B
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1719 1720 1721 1722 1723
}
/* rlwnm & rlwnm. */
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
    uint32_t mb, me;
1724 1725
    TCGv t0;
#if defined(TARGET_PPC64)
P
pbrook 已提交
1726
    TCGv_i32 t1, t2;
1727
#endif
B
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1728 1729 1730

    mb = MB(ctx->opcode);
    me = ME(ctx->opcode);
P
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1731
    t0 = tcg_temp_new();
1732
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1733
#if defined(TARGET_PPC64)
P
pbrook 已提交
1734 1735
    t1 = tcg_temp_new_i32();
    t2 = tcg_temp_new_i32();
1736 1737 1738 1739
    tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
    tcg_gen_trunc_i64_i32(t2, t0);
    tcg_gen_rotl_i32(t1, t1, t2);
    tcg_gen_extu_i32_i64(t0, t1);
P
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1740 1741
    tcg_temp_free_i32(t1);
    tcg_temp_free_i32(t2);
1742 1743 1744
#else
    tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
#endif
1745 1746 1747 1748 1749
    if (unlikely(mb != 0 || me != 31)) {
#if defined(TARGET_PPC64)
        mb += 32;
        me += 32;
#endif
1750
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1751
    } else {
1752
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
B
bellard 已提交
1753
    }
1754
    tcg_temp_free(t0);
1755
    if (unlikely(Rc(ctx->opcode) != 0))
1756
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
B
bellard 已提交
1757 1758
}

1759 1760
#if defined(TARGET_PPC64)
#define GEN_PPC64_R2(name, opc1, opc2)                                        \
1761
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1762 1763 1764
{                                                                             \
    gen_##name(ctx, 0);                                                       \
}                                                                             \
1765 1766
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
             PPC_64B)                                                         \
1767 1768 1769 1770
{                                                                             \
    gen_##name(ctx, 1);                                                       \
}
#define GEN_PPC64_R4(name, opc1, opc2)                                        \
1771
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1772 1773 1774
{                                                                             \
    gen_##name(ctx, 0, 0);                                                    \
}                                                                             \
1775 1776
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
             PPC_64B)                                                         \
1777 1778 1779
{                                                                             \
    gen_##name(ctx, 0, 1);                                                    \
}                                                                             \
1780 1781
GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
             PPC_64B)                                                         \
1782 1783 1784
{                                                                             \
    gen_##name(ctx, 1, 0);                                                    \
}                                                                             \
1785 1786
GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
             PPC_64B)                                                         \
1787 1788 1789
{                                                                             \
    gen_##name(ctx, 1, 1);                                                    \
}
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1791 1792
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
                                      uint32_t me, uint32_t sh)
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1793
{
1794 1795 1796 1797 1798
    if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
        tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
    } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
        tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
    } else {
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        TCGv t0 = tcg_temp_new();
1800
        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1801
        if (likely(mb == 0 && me == 63)) {
1802
            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1803 1804
        } else {
            tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
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1805
        }
1806
        tcg_temp_free(t0);
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1807 1808
    }
    if (unlikely(Rc(ctx->opcode) != 0))
1809
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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1810
}
1811
/* rldicl - rldicl. */
1812
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1813
{
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1814
    uint32_t sh, mb;
1815

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1816 1817
    sh = SH(ctx->opcode) | (shn << 5);
    mb = MB(ctx->opcode) | (mbn << 5);
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1818
    gen_rldinm(ctx, mb, 63, sh);
1819
}
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1820
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1821
/* rldicr - rldicr. */
1822
static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1823
{
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1824
    uint32_t sh, me;
1825

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1826 1827
    sh = SH(ctx->opcode) | (shn << 5);
    me = MB(ctx->opcode) | (men << 5);
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1828
    gen_rldinm(ctx, 0, me, sh);
1829
}
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1830
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1831
/* rldic - rldic. */
1832
static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1833
{
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1834
    uint32_t sh, mb;
1835

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1836 1837
    sh = SH(ctx->opcode) | (shn << 5);
    mb = MB(ctx->opcode) | (mbn << 5);
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1838 1839 1840 1841
    gen_rldinm(ctx, mb, 63 - sh, sh);
}
GEN_PPC64_R4(rldic, 0x1E, 0x04);

1842 1843
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
                                     uint32_t me)
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1844
{
1845
    TCGv t0;
1846 1847 1848

    mb = MB(ctx->opcode);
    me = ME(ctx->opcode);
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    t0 = tcg_temp_new();
1850
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1851
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
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1852
    if (unlikely(mb != 0 || me != 63)) {
1853 1854 1855 1856 1857
        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
    } else {
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
    }
    tcg_temp_free(t0);
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1858
    if (unlikely(Rc(ctx->opcode) != 0))
1859
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1860
}
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1861

1862
/* rldcl - rldcl. */
1863
static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1864
{
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1865
    uint32_t mb;
1866

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1867
    mb = MB(ctx->opcode) | (mbn << 5);
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1868
    gen_rldnm(ctx, mb, 63);
1869
}
1870
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1871
/* rldcr - rldcr. */
1872
static always_inline void gen_rldcr (DisasContext *ctx, int men)
1873
{
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1874
    uint32_t me;
1875

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1876
    me = MB(ctx->opcode) | (men << 5);
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1877
    gen_rldnm(ctx, 0, me);
1878
}
1879
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1880
/* rldimi - rldimi. */
1881
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1882
{
1883
    uint32_t sh, mb, me;
1884

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1885 1886
    sh = SH(ctx->opcode) | (shn << 5);
    mb = MB(ctx->opcode) | (mbn << 5);
1887
    me = 63 - sh;
1888 1889 1890 1891 1892 1893
    if (unlikely(sh == 0 && mb == 0)) {
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
    } else {
        TCGv t0, t1;
        target_ulong mask;

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        t0 = tcg_temp_new();
1895
        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
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1896
        t1 = tcg_temp_new();
1897 1898 1899 1900 1901 1902
        mask = MASK(mb, me);
        tcg_gen_andi_tl(t0, t0, mask);
        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
        tcg_temp_free(t0);
        tcg_temp_free(t1);
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1903 1904
    }
    if (unlikely(Rc(ctx->opcode) != 0))
1905
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1906
}
1907
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1908 1909
#endif

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1910 1911
/***                             Integer shift                             ***/
/* slw & slw. */
1912 1913
GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
{
1914
    TCGv t0;
1915 1916 1917 1918
    int l1, l2;
    l1 = gen_new_label();
    l2 = gen_new_label();

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1919
    t0 = tcg_temp_local_new();
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1920 1921
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1922 1923 1924
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
    tcg_gen_br(l2);
    gen_set_label(l1);
1925
    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1926 1927
    tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    gen_set_label(l2);
1928
    tcg_temp_free(t0);
1929 1930 1931
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
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1932
/* sraw & sraw. */
1933 1934
GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
{
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1935 1936
    gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1937 1938 1939
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
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1940 1941 1942
/* srawi & srawi. */
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
{
1943 1944 1945
    int sh = SH(ctx->opcode);
    if (sh != 0) {
        int l1, l2;
1946
        TCGv t0;
1947 1948
        l1 = gen_new_label();
        l2 = gen_new_label();
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1949
        t0 = tcg_temp_local_new();
1950 1951 1952 1953
        tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1954
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1955 1956
        tcg_gen_br(l2);
        gen_set_label(l1);
1957
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1958
        gen_set_label(l2);
1959 1960 1961
        tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
        tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
        tcg_temp_free(t0);
1962 1963
    } else {
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1964
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1965
    }
1966
    if (unlikely(Rc(ctx->opcode) != 0))
1967
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
B
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1968 1969
}
/* srw & srw. */
1970 1971
GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
{
1972
    TCGv t0, t1;
1973 1974 1975
    int l1, l2;
    l1 = gen_new_label();
    l2 = gen_new_label();
1976

P
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1977
    t0 = tcg_temp_local_new();
A
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1978 1979
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1980 1981 1982
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
    tcg_gen_br(l2);
    gen_set_label(l1);
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1983
    t1 = tcg_temp_new();
1984 1985 1986
    tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
    tcg_temp_free(t1);
1987
    gen_set_label(l2);
1988
    tcg_temp_free(t0);
1989 1990 1991
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
1992 1993
#if defined(TARGET_PPC64)
/* sld & sld. */
1994 1995
GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
{
1996
    TCGv t0;
1997 1998 1999 2000
    int l1, l2;
    l1 = gen_new_label();
    l2 = gen_new_label();

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2001
    t0 = tcg_temp_local_new();
A
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2002 2003
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2004 2005 2006
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
    tcg_gen_br(l2);
    gen_set_label(l1);
2007
    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2008
    gen_set_label(l2);
2009
    tcg_temp_free(t0);
2010 2011 2012
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
2013
/* srad & srad. */
2014 2015
GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
{
P
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2016 2017
    gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2018 2019 2020
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
2021
/* sradi & sradi. */
2022
static always_inline void gen_sradi (DisasContext *ctx, int n)
2023
{
2024
    int sh = SH(ctx->opcode) + (n << 5);
2025
    if (sh != 0) {
2026
        int l1, l2;
2027
        TCGv t0;
2028 2029
        l1 = gen_new_label();
        l2 = gen_new_label();
P
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2030
        t0 = tcg_temp_local_new();
2031
        tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2032 2033
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2034
        tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2035 2036
        tcg_gen_br(l2);
        gen_set_label(l1);
2037
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2038
        gen_set_label(l2);
2039
        tcg_temp_free(t0);
2040 2041 2042
        tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
    } else {
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2043
        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2044 2045
    }
    if (unlikely(Rc(ctx->opcode) != 0))
2046
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2047
}
2048
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2049 2050 2051
{
    gen_sradi(ctx, 0);
}
2052
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2053 2054 2055 2056
{
    gen_sradi(ctx, 1);
}
/* srd & srd. */
2057 2058
GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
{
2059
    TCGv t0;
2060 2061 2062 2063
    int l1, l2;
    l1 = gen_new_label();
    l2 = gen_new_label();

P
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2064
    t0 = tcg_temp_local_new();
A
aurel32 已提交
2065 2066
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
    tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2067 2068 2069
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
    tcg_gen_br(l2);
    gen_set_label(l1);
2070
    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2071
    gen_set_label(l2);
2072
    tcg_temp_free(t0);
2073 2074 2075
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
2076
#endif
B
bellard 已提交
2077 2078

/***                       Floating-Point arithmetic                       ***/
2079
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type)           \
2080
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)                        \
2081
{                                                                             \
2082
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
2083
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
B
bellard 已提交
2084 2085
        return;                                                               \
    }                                                                         \
2086 2087
    /* NIP cannot be restored if the memory exception comes from an helper */ \
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2088
    gen_reset_fpstatus();                                                     \
A
aurel32 已提交
2089 2090
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
                     cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);     \
2091
    if (isfloat) {                                                            \
A
aurel32 已提交
2092
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2093
    }                                                                         \
A
aurel32 已提交
2094 2095
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf,                      \
                     Rc(ctx->opcode) != 0);                                   \
2096 2097
}

2098 2099 2100
#define GEN_FLOAT_ACB(name, op2, set_fprf, type)                              \
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type);                     \
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2101

2102 2103
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
2104
{                                                                             \
2105
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
2106
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
B
bellard 已提交
2107 2108
        return;                                                               \
    }                                                                         \
2109 2110
    /* NIP cannot be restored if the memory exception comes from an helper */ \
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2111
    gen_reset_fpstatus();                                                     \
A
aurel32 已提交
2112 2113
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
                     cpu_fpr[rB(ctx->opcode)]);                               \
2114
    if (isfloat) {                                                            \
A
aurel32 已提交
2115
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2116
    }                                                                         \
A
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2117 2118
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2119
}
2120 2121 2122
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type)                        \
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2123

2124 2125
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
2126
{                                                                             \
2127
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
2128
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
B
bellard 已提交
2129 2130
        return;                                                               \
    }                                                                         \
2131 2132
    /* NIP cannot be restored if the memory exception comes from an helper */ \
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2133
    gen_reset_fpstatus();                                                     \
A
aurel32 已提交
2134 2135
    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],      \
                       cpu_fpr[rC(ctx->opcode)]);                             \
2136
    if (isfloat) {                                                            \
A
aurel32 已提交
2137
        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);  \
2138
    }                                                                         \
A
aurel32 已提交
2139 2140
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
                     set_fprf, Rc(ctx->opcode) != 0);                         \
2141
}
2142 2143 2144
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type)                        \
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2145

2146
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type)                           \
2147
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)                        \
2148
{                                                                             \
2149
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
2150
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
B
bellard 已提交
2151 2152
        return;                                                               \
    }                                                                         \
2153 2154
    /* NIP cannot be restored if the memory exception comes from an helper */ \
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2155
    gen_reset_fpstatus();                                                     \
A
aurel32 已提交
2156 2157 2158
    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);   \
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
                     set_fprf, Rc(ctx->opcode) != 0);                         \
B
bellard 已提交
2159 2160
}

2161
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type)                          \
2162
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)                        \
2163
{                                                                             \
2164
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
2165
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
B
bellard 已提交
2166 2167
        return;                                                               \
    }                                                                         \
2168 2169
    /* NIP cannot be restored if the memory exception comes from an helper */ \
    gen_update_nip(ctx, ctx->nip - 4);                                        \
2170
    gen_reset_fpstatus();                                                     \
A
aurel32 已提交
2171 2172 2173
    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);   \
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)],                                \
                     set_fprf, Rc(ctx->opcode) != 0);                         \
B
bellard 已提交
2174 2175
}

2176
/* fadd - fadds */
2177
GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2178
/* fdiv - fdivs */
2179
GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2180
/* fmul - fmuls */
2181
GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
B
bellard 已提交
2182

2183
/* fre */
2184
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2185

2186
/* fres */
2187
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
B
bellard 已提交
2188

2189
/* frsqrte */
2190 2191 2192
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);

/* frsqrtes */
A
aurel32 已提交
2193
GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2194
{
A
aurel32 已提交
2195
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2196
        gen_exception(ctx, POWERPC_EXCP_FPU);
A
aurel32 已提交
2197 2198
        return;
    }
2199 2200
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
A
aurel32 已提交
2201 2202 2203 2204
    gen_reset_fpstatus();
    gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2205
}
B
bellard 已提交
2206

2207
/* fsel */
2208
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2209
/* fsub - fsubs */
2210
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
B
bellard 已提交
2211 2212
/* Optional: */
/* fsqrt */
2213
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2214
{
2215
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2216
        gen_exception(ctx, POWERPC_EXCP_FPU);
2217 2218
        return;
    }
2219 2220
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
2221
    gen_reset_fpstatus();
A
aurel32 已提交
2222 2223
    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2224
}
B
bellard 已提交
2225

2226
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
B
bellard 已提交
2227
{
2228
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2229
        gen_exception(ctx, POWERPC_EXCP_FPU);
B
bellard 已提交
2230 2231
        return;
    }
2232 2233
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
2234
    gen_reset_fpstatus();
A
aurel32 已提交
2235 2236 2237
    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
B
bellard 已提交
2238 2239 2240
}

/***                     Floating-Point multiply-and-add                   ***/
2241
/* fmadd - fmadds */
2242
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2243
/* fmsub - fmsubs */
2244
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2245
/* fnmadd - fnmadds */
2246
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2247
/* fnmsub - fnmsubs */
2248
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
B
bellard 已提交
2249 2250 2251

/***                     Floating-Point round & convert                    ***/
/* fctiw */
2252
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
B
bellard 已提交
2253
/* fctiwz */
2254
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
B
bellard 已提交
2255
/* frsp */
2256
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
J
j_mayer 已提交
2257 2258
#if defined(TARGET_PPC64)
/* fcfid */
2259
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
J
j_mayer 已提交
2260
/* fctid */
2261
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
J
j_mayer 已提交
2262
/* fctidz */
2263
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
J
j_mayer 已提交
2264
#endif
B
bellard 已提交
2265

2266
/* frin */
2267
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2268
/* friz */
2269
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2270
/* frip */
2271
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2272
/* frim */
2273
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2274

B
bellard 已提交
2275 2276
/***                         Floating-Point compare                        ***/
/* fcmpo */
2277
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
B
bellard 已提交
2278
{
A
aurel32 已提交
2279
    TCGv_i32 crf;
2280
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2281
        gen_exception(ctx, POWERPC_EXCP_FPU);
B
bellard 已提交
2282 2283
        return;
    }
2284 2285
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
2286
    gen_reset_fpstatus();
A
aurel32 已提交
2287 2288
    crf = tcg_const_i32(crfD(ctx->opcode));
    gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
A
aurel32 已提交
2289
    tcg_temp_free_i32(crf);
A
aurel32 已提交
2290
    gen_helper_float_check_status();
B
bellard 已提交
2291 2292 2293
}

/* fcmpu */
2294
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
B
bellard 已提交
2295
{
A
aurel32 已提交
2296
    TCGv_i32 crf;
2297
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2298
        gen_exception(ctx, POWERPC_EXCP_FPU);
B
bellard 已提交
2299 2300
        return;
    }
2301 2302
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
2303
    gen_reset_fpstatus();
A
aurel32 已提交
2304 2305
    crf = tcg_const_i32(crfD(ctx->opcode));
    gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
A
aurel32 已提交
2306
    tcg_temp_free_i32(crf);
A
aurel32 已提交
2307
    gen_helper_float_check_status();
B
bellard 已提交
2308 2309
}

2310 2311
/***                         Floating-point move                           ***/
/* fabs */
2312 2313
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2314 2315

/* fmr  - fmr. */
2316
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2317 2318
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
{
2319
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2320
        gen_exception(ctx, POWERPC_EXCP_FPU);
B
bellard 已提交
2321 2322
        return;
    }
A
aurel32 已提交
2323 2324
    tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2325 2326 2327
}

/* fnabs */
2328 2329
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2330
/* fneg */
2331 2332
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2333

B
bellard 已提交
2334 2335 2336 2337
/***                  Floating-Point status & ctrl register                ***/
/* mcrfs */
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
{
2338 2339
    int bfa;

2340
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2341
        gen_exception(ctx, POWERPC_EXCP_FPU);
B
bellard 已提交
2342 2343
        return;
    }
2344
    bfa = 4 * (7 - crfS(ctx->opcode));
2345 2346
    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
A
aurel32 已提交
2347
    tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
B
bellard 已提交
2348 2349 2350 2351 2352
}

/* mffs */
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
{
2353
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2354
        gen_exception(ctx, POWERPC_EXCP_FPU);
B
bellard 已提交
2355 2356
        return;
    }
2357
    gen_reset_fpstatus();
A
aurel32 已提交
2358 2359
    tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
B
bellard 已提交
2360 2361 2362 2363 2364
}

/* mtfsb0 */
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
{
B
bellard 已提交
2365
    uint8_t crb;
2366

2367
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2368
        gen_exception(ctx, POWERPC_EXCP_FPU);
B
bellard 已提交
2369 2370
        return;
    }
A
aurel32 已提交
2371
    crb = 31 - crbD(ctx->opcode);
2372
    gen_reset_fpstatus();
A
aurel32 已提交
2373
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2374 2375 2376 2377
        TCGv_i32 t0;
        /* NIP cannot be restored if the memory exception comes from an helper */
        gen_update_nip(ctx, ctx->nip - 4);
        t0 = tcg_const_i32(crb);
A
aurel32 已提交
2378 2379 2380
        gen_helper_fpscr_clrbit(t0);
        tcg_temp_free_i32(t0);
    }
2381
    if (unlikely(Rc(ctx->opcode) != 0)) {
2382
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2383
    }
B
bellard 已提交
2384 2385 2386 2387 2388
}

/* mtfsb1 */
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
{
B
bellard 已提交
2389
    uint8_t crb;
2390

2391
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2392
        gen_exception(ctx, POWERPC_EXCP_FPU);
B
bellard 已提交
2393 2394
        return;
    }
A
aurel32 已提交
2395
    crb = 31 - crbD(ctx->opcode);
2396 2397
    gen_reset_fpstatus();
    /* XXX: we pretend we can only do IEEE floating-point computations */
A
aurel32 已提交
2398
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2399 2400 2401 2402
        TCGv_i32 t0;
        /* NIP cannot be restored if the memory exception comes from an helper */
        gen_update_nip(ctx, ctx->nip - 4);
        t0 = tcg_const_i32(crb);
A
aurel32 已提交
2403
        gen_helper_fpscr_setbit(t0);
2404
        tcg_temp_free_i32(t0);
A
aurel32 已提交
2405
    }
2406
    if (unlikely(Rc(ctx->opcode) != 0)) {
2407
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2408 2409
    }
    /* We can raise a differed exception */
A
aurel32 已提交
2410
    gen_helper_float_check_status();
B
bellard 已提交
2411 2412 2413 2414 2415
}

/* mtfsf */
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
{
2416
    TCGv_i32 t0;
A
aurel32 已提交
2417

2418
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2419
        gen_exception(ctx, POWERPC_EXCP_FPU);
B
bellard 已提交
2420 2421
        return;
    }
2422 2423
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
2424
    gen_reset_fpstatus();
A
aurel32 已提交
2425 2426
    t0 = tcg_const_i32(FM(ctx->opcode));
    gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2427
    tcg_temp_free_i32(t0);
2428
    if (unlikely(Rc(ctx->opcode) != 0)) {
2429
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2430 2431
    }
    /* We can raise a differed exception */
A
aurel32 已提交
2432
    gen_helper_float_check_status();
B
bellard 已提交
2433 2434 2435 2436 2437
}

/* mtfsfi */
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
{
2438
    int bf, sh;
2439 2440
    TCGv_i64 t0;
    TCGv_i32 t1;
2441

2442
    if (unlikely(!ctx->fpu_enabled)) {
A
aurel32 已提交
2443
        gen_exception(ctx, POWERPC_EXCP_FPU);
B
bellard 已提交
2444 2445
        return;
    }
2446 2447
    bf = crbD(ctx->opcode) >> 2;
    sh = 7 - bf;
2448 2449
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
2450
    gen_reset_fpstatus();
2451
    t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
A
aurel32 已提交
2452 2453
    t1 = tcg_const_i32(1 << sh);
    gen_helper_store_fpscr(t0, t1);
2454 2455
    tcg_temp_free_i64(t0);
    tcg_temp_free_i32(t1);
2456
    if (unlikely(Rc(ctx->opcode) != 0)) {
2457
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2458 2459
    }
    /* We can raise a differed exception */
A
aurel32 已提交
2460
    gen_helper_float_check_status();
B
bellard 已提交
2461 2462
}

2463 2464
/***                           Addressing modes                            ***/
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
A
aurel32 已提交
2465
static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2466 2467 2468
{
    target_long simm = SIMM(ctx->opcode);

2469
    simm &= ~maskl;
A
aurel32 已提交
2470 2471 2472 2473 2474 2475
    if (rA(ctx->opcode) == 0) {
#if defined(TARGET_PPC64)
        if (!ctx->sf_mode) {
            tcg_gen_movi_tl(EA, (uint32_t)simm);
        } else
#endif
2476
        tcg_gen_movi_tl(EA, simm);
A
aurel32 已提交
2477
    } else if (likely(simm != 0)) {
2478
        tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
A
aurel32 已提交
2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489
#if defined(TARGET_PPC64)
        if (!ctx->sf_mode) {
            tcg_gen_ext32u_tl(EA, EA);
        }
#endif
    } else {
#if defined(TARGET_PPC64)
        if (!ctx->sf_mode) {
            tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
        } else
#endif
2490
        tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
A
aurel32 已提交
2491
    }
2492 2493
}

A
aurel32 已提交
2494
static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2495
{
A
aurel32 已提交
2496 2497 2498 2499 2500 2501
    if (rA(ctx->opcode) == 0) {
#if defined(TARGET_PPC64)
        if (!ctx->sf_mode) {
            tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
        } else
#endif
2502
        tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
A
aurel32 已提交
2503
    } else {
2504
        tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
A
aurel32 已提交
2505 2506 2507 2508 2509 2510
#if defined(TARGET_PPC64)
        if (!ctx->sf_mode) {
            tcg_gen_ext32u_tl(EA, EA);
        }
#endif
    }
2511 2512
}

A
aurel32 已提交
2513
static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2514
{
A
aurel32 已提交
2515
    if (rA(ctx->opcode) == 0) {
2516
        tcg_gen_movi_tl(EA, 0);
A
aurel32 已提交
2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534
    } else {
#if defined(TARGET_PPC64)
        if (!ctx->sf_mode) {
            tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
        } else
#endif
            tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
    }
}

static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
{
    tcg_gen_addi_tl(ret, arg1, val);
#if defined(TARGET_PPC64)
    if (!ctx->sf_mode) {
        tcg_gen_ext32u_tl(ret, ret);
    }
#endif
2535 2536
}

2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554
static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
{
    int l1 = gen_new_label();
    TCGv t0 = tcg_temp_new();
    TCGv_i32 t1, t2;
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
    tcg_gen_andi_tl(t0, EA, mask);
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
    t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
    t2 = tcg_const_i32(0);
    gen_helper_raise_exception_err(t1, t2);
    tcg_temp_free_i32(t1);
    tcg_temp_free_i32(t2);
    gen_set_label(l1);
    tcg_temp_free(t0);
}

2555
/***                             Integer load                              ***/
A
aurel32 已提交
2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569
static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
    tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
}

static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
    tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
}

static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
    tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
    if (unlikely(ctx->le_mode)) {
A
aurel32 已提交
2570
#if defined(TARGET_PPC64)
A
aurel32 已提交
2571 2572
        TCGv_i32 t0 = tcg_temp_new_i32();
        tcg_gen_trunc_tl_i32(t0, arg1);
2573
        tcg_gen_bswap16_i32(t0, t0);
A
aurel32 已提交
2574
        tcg_gen_extu_i32_tl(arg1, t0);
P
pbrook 已提交
2575
        tcg_temp_free_i32(t0);
A
aurel32 已提交
2576 2577 2578 2579
#else
        tcg_gen_bswap16_i32(arg1, arg1);
#endif
    }
A
aurel32 已提交
2580 2581
}

A
aurel32 已提交
2582
static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
A
aurel32 已提交
2583
{
A
aurel32 已提交
2584 2585
    if (unlikely(ctx->le_mode)) {
#if defined(TARGET_PPC64)
P
pbrook 已提交
2586
        TCGv_i32 t0;
A
aurel32 已提交
2587
        tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
P
pbrook 已提交
2588
        t0 = tcg_temp_new_i32();
A
aurel32 已提交
2589
        tcg_gen_trunc_tl_i32(t0, arg1);
2590
        tcg_gen_bswap16_i32(t0, t0);
A
aurel32 已提交
2591 2592
        tcg_gen_extu_i32_tl(arg1, t0);
        tcg_gen_ext16s_tl(arg1, arg1);
P
pbrook 已提交
2593
        tcg_temp_free_i32(t0);
A
aurel32 已提交
2594 2595 2596 2597 2598 2599 2600 2601
#else
        tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
        tcg_gen_bswap16_i32(arg1, arg1);
        tcg_gen_ext16s_i32(arg1, arg1);
#endif
    } else {
        tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
    }
A
aurel32 已提交
2602 2603
}

A
aurel32 已提交
2604
static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
A
aurel32 已提交
2605
{
A
aurel32 已提交
2606 2607 2608 2609 2610
    tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
    if (unlikely(ctx->le_mode)) {
#if defined(TARGET_PPC64)
        TCGv_i32 t0 = tcg_temp_new_i32();
        tcg_gen_trunc_tl_i32(t0, arg1);
2611
        tcg_gen_bswap_i32(t0, t0);
A
aurel32 已提交
2612
        tcg_gen_extu_i32_tl(arg1, t0);
P
pbrook 已提交
2613
        tcg_temp_free_i32(t0);
A
aurel32 已提交
2614 2615 2616 2617
#else
        tcg_gen_bswap_i32(arg1, arg1);
#endif
    }
A
aurel32 已提交
2618 2619
}

A
aurel32 已提交
2620 2621
#if defined(TARGET_PPC64)
static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
A
aurel32 已提交
2622
{
A
aurel32 已提交
2623
    if (unlikely(ctx->mem_idx)) {
P
pbrook 已提交
2624
        TCGv_i32 t0;
A
aurel32 已提交
2625
        tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
P
pbrook 已提交
2626
        t0 = tcg_temp_new_i32();
A
aurel32 已提交
2627
        tcg_gen_trunc_tl_i32(t0, arg1);
2628
        tcg_gen_bswap_i32(t0, t0);
A
aurel32 已提交
2629
        tcg_gen_ext_i32_tl(arg1, t0);
P
pbrook 已提交
2630
        tcg_temp_free_i32(t0);
A
aurel32 已提交
2631
    } else
A
aurel32 已提交
2632
        tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
A
aurel32 已提交
2633
}
A
aurel32 已提交
2634
#endif
A
aurel32 已提交
2635

A
aurel32 已提交
2636
static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
A
aurel32 已提交
2637
{
A
aurel32 已提交
2638 2639 2640 2641
    tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
    if (unlikely(ctx->le_mode)) {
        tcg_gen_bswap_i64(arg1, arg1);
    }
A
aurel32 已提交
2642 2643
}

A
aurel32 已提交
2644
static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
A
aurel32 已提交
2645
{
A
aurel32 已提交
2646
    tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
A
aurel32 已提交
2647 2648
}

A
aurel32 已提交
2649
static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
A
aurel32 已提交
2650
{
A
aurel32 已提交
2651 2652
    if (unlikely(ctx->le_mode)) {
#if defined(TARGET_PPC64)
P
pbrook 已提交
2653
        TCGv_i32 t0;
A
aurel32 已提交
2654
        TCGv t1;
P
pbrook 已提交
2655
        t0 = tcg_temp_new_i32();
A
aurel32 已提交
2656
        tcg_gen_trunc_tl_i32(t0, arg1);
2657 2658
        tcg_gen_ext16u_i32(t0, t0);
        tcg_gen_bswap16_i32(t0, t0);
A
aurel32 已提交
2659
        t1 = tcg_temp_new();
2660
        tcg_gen_extu_i32_tl(t1, t0);
P
pbrook 已提交
2661
        tcg_temp_free_i32(t0);
A
aurel32 已提交
2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673
        tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
        tcg_temp_free(t1);
#else
        TCGv t0 = tcg_temp_new();
        tcg_gen_ext16u_tl(t0, arg1);
        tcg_gen_bswap16_i32(t0, t0);
        tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
        tcg_temp_free(t0);
#endif
    } else {
        tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
    }
A
aurel32 已提交
2674 2675
}

A
aurel32 已提交
2676
static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
A
aurel32 已提交
2677
{
A
aurel32 已提交
2678 2679
    if (unlikely(ctx->le_mode)) {
#if defined(TARGET_PPC64)
P
pbrook 已提交
2680
        TCGv_i32 t0;
A
aurel32 已提交
2681
        TCGv t1;
P
pbrook 已提交
2682
        t0 = tcg_temp_new_i32();
A
aurel32 已提交
2683
        tcg_gen_trunc_tl_i32(t0, arg1);
2684
        tcg_gen_bswap_i32(t0, t0);
A
aurel32 已提交
2685
        t1 = tcg_temp_new();
2686
        tcg_gen_extu_i32_tl(t1, t0);
P
pbrook 已提交
2687
        tcg_temp_free_i32(t0);
A
aurel32 已提交
2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698
        tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
        tcg_temp_free(t1);
#else
        TCGv t0 = tcg_temp_new_i32();
        tcg_gen_bswap_i32(t0, arg1);
        tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
        tcg_temp_free(t0);
#endif
    } else {
        tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
    }
A
aurel32 已提交
2699 2700
}

A
aurel32 已提交
2701
static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
A
aurel32 已提交
2702
{
A
aurel32 已提交
2703
    if (unlikely(ctx->le_mode)) {
P
pbrook 已提交
2704
        TCGv_i64 t0 = tcg_temp_new_i64();
A
aurel32 已提交
2705 2706
        tcg_gen_bswap_i64(t0, arg1);
        tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
P
pbrook 已提交
2707
        tcg_temp_free_i64(t0);
A
aurel32 已提交
2708
    } else
A
aurel32 已提交
2709
        tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
A
aurel32 已提交
2710 2711
}

2712 2713
#define GEN_LD(name, ldop, opc, type)                                         \
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
B
bellard 已提交
2714
{                                                                             \
A
aurel32 已提交
2715 2716 2717 2718 2719
    TCGv EA;                                                                  \
    gen_set_access_type(ctx, ACCESS_INT);                                     \
    EA = tcg_temp_new();                                                      \
    gen_addr_imm_index(ctx, EA, 0);                                           \
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
A
aurel32 已提交
2720
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
2721 2722
}

2723 2724
#define GEN_LDU(name, ldop, opc, type)                                        \
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
B
bellard 已提交
2725
{                                                                             \
A
aurel32 已提交
2726
    TCGv EA;                                                                  \
2727 2728
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
A
aurel32 已提交
2729
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2730
        return;                                                               \
2731
    }                                                                         \
A
aurel32 已提交
2732
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2733
    EA = tcg_temp_new();                                                      \
J
j_mayer 已提交
2734
    if (type == PPC_64B)                                                      \
A
aurel32 已提交
2735
        gen_addr_imm_index(ctx, EA, 0x03);                                    \
J
j_mayer 已提交
2736
    else                                                                      \
A
aurel32 已提交
2737 2738
        gen_addr_imm_index(ctx, EA, 0);                                       \
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
A
aurel32 已提交
2739 2740
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
2741 2742
}

2743 2744
#define GEN_LDUX(name, ldop, opc2, opc3, type)                                \
GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type)                     \
B
bellard 已提交
2745
{                                                                             \
A
aurel32 已提交
2746
    TCGv EA;                                                                  \
2747 2748
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
A
aurel32 已提交
2749
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2750
        return;                                                               \
2751
    }                                                                         \
A
aurel32 已提交
2752
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2753
    EA = tcg_temp_new();                                                      \
A
aurel32 已提交
2754 2755
    gen_addr_reg_index(ctx, EA);                                              \
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
A
aurel32 已提交
2756 2757
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
2758 2759
}

2760 2761
#define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
B
bellard 已提交
2762
{                                                                             \
A
aurel32 已提交
2763 2764 2765 2766 2767
    TCGv EA;                                                                  \
    gen_set_access_type(ctx, ACCESS_INT);                                     \
    EA = tcg_temp_new();                                                      \
    gen_addr_reg_index(ctx, EA);                                              \
    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
A
aurel32 已提交
2768
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
2769 2770
}

2771 2772 2773 2774 2775
#define GEN_LDS(name, ldop, op, type)                                         \
GEN_LD(name, ldop, op | 0x20, type);                                          \
GEN_LDU(name, ldop, op | 0x21, type);                                         \
GEN_LDUX(name, ldop, 0x17, op | 0x01, type);                                  \
GEN_LDX(name, ldop, 0x17, op | 0x00, type)
B
bellard 已提交
2776 2777

/* lbz lbzu lbzux lbzx */
2778
GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
B
bellard 已提交
2779
/* lha lhau lhaux lhax */
2780
GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
B
bellard 已提交
2781
/* lhz lhzu lhzux lhzx */
2782
GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
B
bellard 已提交
2783
/* lwz lwzu lwzux lwzx */
2784
GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2785 2786
#if defined(TARGET_PPC64)
/* lwaux */
2787
GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2788
/* lwax */
2789
GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2790
/* ldux */
2791
GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2792
/* ldx */
2793
GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2794 2795
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
{
A
aurel32 已提交
2796
    TCGv EA;
2797 2798 2799
    if (Rc(ctx->opcode)) {
        if (unlikely(rA(ctx->opcode) == 0 ||
                     rA(ctx->opcode) == rD(ctx->opcode))) {
A
aurel32 已提交
2800
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2801 2802 2803
            return;
        }
    }
A
aurel32 已提交
2804
    gen_set_access_type(ctx, ACCESS_INT);
P
pbrook 已提交
2805
    EA = tcg_temp_new();
A
aurel32 已提交
2806
    gen_addr_imm_index(ctx, EA, 0x03);
2807 2808
    if (ctx->opcode & 0x02) {
        /* lwa (lwau is undefined) */
A
aurel32 已提交
2809
        gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2810 2811
    } else {
        /* ld - ldu */
A
aurel32 已提交
2812
        gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2813 2814
    }
    if (Rc(ctx->opcode))
A
aurel32 已提交
2815 2816
        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
    tcg_temp_free(EA);
2817
}
2818 2819 2820 2821
/* lq */
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
2822
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2823 2824
#else
    int ra, rd;
A
aurel32 已提交
2825
    TCGv EA;
2826 2827

    /* Restore CPU state */
A
aurel32 已提交
2828
    if (unlikely(ctx->mem_idx == 0)) {
A
aurel32 已提交
2829
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2830 2831 2832 2833 2834
        return;
    }
    ra = rA(ctx->opcode);
    rd = rD(ctx->opcode);
    if (unlikely((rd & 1) || rd == ra)) {
A
aurel32 已提交
2835
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2836 2837
        return;
    }
A
aurel32 已提交
2838
    if (unlikely(ctx->le_mode)) {
2839
        /* Little-endian mode is not handled */
A
aurel32 已提交
2840
        gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2841 2842
        return;
    }
A
aurel32 已提交
2843
    gen_set_access_type(ctx, ACCESS_INT);
P
pbrook 已提交
2844
    EA = tcg_temp_new();
A
aurel32 已提交
2845 2846 2847 2848
    gen_addr_imm_index(ctx, EA, 0x0F);
    gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
    gen_addr_add(ctx, EA, EA, 8);
    gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
A
aurel32 已提交
2849
    tcg_temp_free(EA);
2850 2851
#endif
}
2852
#endif
B
bellard 已提交
2853 2854

/***                              Integer store                            ***/
2855 2856
#define GEN_ST(name, stop, opc, type)                                         \
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
B
bellard 已提交
2857
{                                                                             \
A
aurel32 已提交
2858 2859 2860 2861 2862
    TCGv EA;                                                                  \
    gen_set_access_type(ctx, ACCESS_INT);                                     \
    EA = tcg_temp_new();                                                      \
    gen_addr_imm_index(ctx, EA, 0);                                           \
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
A
aurel32 已提交
2863
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
2864 2865
}

2866 2867
#define GEN_STU(name, stop, opc, type)                                        \
GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
B
bellard 已提交
2868
{                                                                             \
A
aurel32 已提交
2869
    TCGv EA;                                                                  \
2870
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
A
aurel32 已提交
2871
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2872
        return;                                                               \
2873
    }                                                                         \
A
aurel32 已提交
2874
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2875
    EA = tcg_temp_new();                                                      \
J
j_mayer 已提交
2876
    if (type == PPC_64B)                                                      \
A
aurel32 已提交
2877
        gen_addr_imm_index(ctx, EA, 0x03);                                    \
J
j_mayer 已提交
2878
    else                                                                      \
A
aurel32 已提交
2879 2880
        gen_addr_imm_index(ctx, EA, 0);                                       \
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
A
aurel32 已提交
2881 2882
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
2883 2884
}

2885 2886
#define GEN_STUX(name, stop, opc2, opc3, type)                                \
GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type)                     \
B
bellard 已提交
2887
{                                                                             \
A
aurel32 已提交
2888
    TCGv EA;                                                                  \
2889
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
A
aurel32 已提交
2890
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2891
        return;                                                               \
2892
    }                                                                         \
A
aurel32 已提交
2893
    gen_set_access_type(ctx, ACCESS_INT);                                     \
2894
    EA = tcg_temp_new();                                                      \
A
aurel32 已提交
2895 2896
    gen_addr_reg_index(ctx, EA);                                              \
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
A
aurel32 已提交
2897 2898
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
2899 2900
}

2901 2902
#define GEN_STX(name, stop, opc2, opc3, type)                                 \
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
B
bellard 已提交
2903
{                                                                             \
A
aurel32 已提交
2904 2905 2906 2907 2908
    TCGv EA;                                                                  \
    gen_set_access_type(ctx, ACCESS_INT);                                     \
    EA = tcg_temp_new();                                                      \
    gen_addr_reg_index(ctx, EA);                                              \
    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
A
aurel32 已提交
2909
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
2910 2911
}

2912 2913 2914 2915 2916
#define GEN_STS(name, stop, op, type)                                         \
GEN_ST(name, stop, op | 0x20, type);                                          \
GEN_STU(name, stop, op | 0x21, type);                                         \
GEN_STUX(name, stop, 0x17, op | 0x01, type);                                  \
GEN_STX(name, stop, 0x17, op | 0x00, type)
B
bellard 已提交
2917 2918

/* stb stbu stbux stbx */
2919
GEN_STS(stb, st8, 0x06, PPC_INTEGER);
B
bellard 已提交
2920
/* sth sthu sthux sthx */
2921
GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
B
bellard 已提交
2922
/* stw stwu stwux stwx */
2923
GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2924
#if defined(TARGET_PPC64)
2925 2926
GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2927
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2928
{
2929
    int rs;
A
aurel32 已提交
2930
    TCGv EA;
2931 2932 2933 2934

    rs = rS(ctx->opcode);
    if ((ctx->opcode & 0x3) == 0x2) {
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
2935
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2936 2937
#else
        /* stq */
A
aurel32 已提交
2938
        if (unlikely(ctx->mem_idx == 0)) {
A
aurel32 已提交
2939
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2940 2941 2942
            return;
        }
        if (unlikely(rs & 1)) {
A
aurel32 已提交
2943
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2944 2945
            return;
        }
A
aurel32 已提交
2946
        if (unlikely(ctx->le_mode)) {
2947
            /* Little-endian mode is not handled */
A
aurel32 已提交
2948
            gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2949 2950
            return;
        }
A
aurel32 已提交
2951
        gen_set_access_type(ctx, ACCESS_INT);
P
pbrook 已提交
2952
        EA = tcg_temp_new();
A
aurel32 已提交
2953 2954 2955 2956
        gen_addr_imm_index(ctx, EA, 0x03);
        gen_qemu_st64(ctx, cpu_gpr[rs], EA);
        gen_addr_add(ctx, EA, EA, 8);
        gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
A
aurel32 已提交
2957
        tcg_temp_free(EA);
2958 2959 2960 2961 2962
#endif
    } else {
        /* std / stdu */
        if (Rc(ctx->opcode)) {
            if (unlikely(rA(ctx->opcode) == 0)) {
A
aurel32 已提交
2963
                gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2964 2965 2966
                return;
            }
        }
A
aurel32 已提交
2967
        gen_set_access_type(ctx, ACCESS_INT);
P
pbrook 已提交
2968
        EA = tcg_temp_new();
A
aurel32 已提交
2969 2970
        gen_addr_imm_index(ctx, EA, 0x03);
        gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2971
        if (Rc(ctx->opcode))
A
aurel32 已提交
2972 2973
            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
        tcg_temp_free(EA);
2974 2975 2976
    }
}
#endif
B
bellard 已提交
2977 2978
/***                Integer load and store with byte reverse               ***/
/* lhbrx */
A
aurel32 已提交
2979
static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
A
aurel32 已提交
2980
{
A
aurel32 已提交
2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992
    tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
    if (likely(!ctx->le_mode)) {
#if defined(TARGET_PPC64)
        TCGv_i32 t0 = tcg_temp_new_i32();
        tcg_gen_trunc_tl_i32(t0, arg1);
        tcg_gen_bswap16_i32(t0, t0);
        tcg_gen_extu_i32_tl(arg1, t0);
        tcg_temp_free_i32(t0);
#else
        tcg_gen_bswap16_i32(arg1, arg1);
#endif
    }
A
aurel32 已提交
2993
}
2994
GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
A
aurel32 已提交
2995

B
bellard 已提交
2996
/* lwbrx */
A
aurel32 已提交
2997
static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
A
aurel32 已提交
2998
{
A
aurel32 已提交
2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010
    tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
    if (likely(!ctx->le_mode)) {
#if defined(TARGET_PPC64)
        TCGv_i32 t0 = tcg_temp_new_i32();
        tcg_gen_trunc_tl_i32(t0, arg1);
        tcg_gen_bswap_i32(t0, t0);
        tcg_gen_extu_i32_tl(arg1, t0);
        tcg_temp_free_i32(t0);
#else
        tcg_gen_bswap_i32(arg1, arg1);
#endif
    }
A
aurel32 已提交
3011
}
3012
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
A
aurel32 已提交
3013

B
bellard 已提交
3014
/* sthbrx */
A
aurel32 已提交
3015
static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
A
aurel32 已提交
3016
{
A
aurel32 已提交
3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039
    if (likely(!ctx->le_mode)) {
#if defined(TARGET_PPC64)
        TCGv_i32 t0;
        TCGv t1;
        t0 = tcg_temp_new_i32();
        tcg_gen_trunc_tl_i32(t0, arg1);
        tcg_gen_ext16u_i32(t0, t0);
        tcg_gen_bswap16_i32(t0, t0);
        t1 = tcg_temp_new();
        tcg_gen_extu_i32_tl(t1, t0);
        tcg_temp_free_i32(t0);
        tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
        tcg_temp_free(t1);
#else
        TCGv t0 = tcg_temp_new();
        tcg_gen_ext16u_tl(t0, arg1);
        tcg_gen_bswap16_i32(t0, t0);
        tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
        tcg_temp_free(t0);
#endif
    } else {
        tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
    }
A
aurel32 已提交
3040
}
3041
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
A
aurel32 已提交
3042

B
bellard 已提交
3043
/* stwbrx */
A
aurel32 已提交
3044
static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
A
aurel32 已提交
3045
{
A
aurel32 已提交
3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066
    if (likely(!ctx->le_mode)) {
#if defined(TARGET_PPC64)
        TCGv_i32 t0;
        TCGv t1;
        t0 = tcg_temp_new_i32();
        tcg_gen_trunc_tl_i32(t0, arg1);
        tcg_gen_bswap_i32(t0, t0);
        t1 = tcg_temp_new();
        tcg_gen_extu_i32_tl(t1, t0);
        tcg_temp_free_i32(t0);
        tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
        tcg_temp_free(t1);
#else
        TCGv t0 = tcg_temp_new_i32();
        tcg_gen_bswap_i32(t0, arg1);
        tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
        tcg_temp_free(t0);
#endif
    } else {
        tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
    }
A
aurel32 已提交
3067
}
3068
GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
B
bellard 已提交
3069 3070 3071 3072 3073

/***                    Integer load and store multiple                    ***/
/* lmw */
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
A
aurel32 已提交
3074 3075 3076
    TCGv t0;
    TCGv_i32 t1;
    gen_set_access_type(ctx, ACCESS_INT);
3077
    /* NIP cannot be restored if the memory exception comes from an helper */
3078
    gen_update_nip(ctx, ctx->nip - 4);
A
aurel32 已提交
3079 3080 3081
    t0 = tcg_temp_new();
    t1 = tcg_const_i32(rD(ctx->opcode));
    gen_addr_imm_index(ctx, t0, 0);
3082 3083 3084
    gen_helper_lmw(t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free_i32(t1);
B
bellard 已提交
3085 3086 3087 3088 3089
}

/* stmw */
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
A
aurel32 已提交
3090 3091 3092
    TCGv t0;
    TCGv_i32 t1;
    gen_set_access_type(ctx, ACCESS_INT);
3093
    /* NIP cannot be restored if the memory exception comes from an helper */
3094
    gen_update_nip(ctx, ctx->nip - 4);
A
aurel32 已提交
3095 3096 3097
    t0 = tcg_temp_new();
    t1 = tcg_const_i32(rS(ctx->opcode));
    gen_addr_imm_index(ctx, t0, 0);
3098 3099 3100
    gen_helper_stmw(t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free_i32(t1);
B
bellard 已提交
3101 3102 3103 3104
}

/***                    Integer load and store strings                     ***/
/* lswi */
3105
/* PowerPC32 specification says we must generate an exception if
3106 3107 3108 3109
 * rA is in the range of registers to be loaded.
 * In an other hand, IBM says this is valid, but rA won't be loaded.
 * For now, I'll follow the spec...
 */
3110
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
B
bellard 已提交
3111
{
3112 3113
    TCGv t0;
    TCGv_i32 t1, t2;
B
bellard 已提交
3114 3115
    int nb = NB(ctx->opcode);
    int start = rD(ctx->opcode);
3116
    int ra = rA(ctx->opcode);
B
bellard 已提交
3117 3118 3119 3120 3121
    int nr;

    if (nb == 0)
        nb = 32;
    nr = nb / 4;
3122 3123 3124
    if (unlikely(((start + nr) > 32  &&
                  start <= ra && (start + nr - 32) > ra) ||
                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
A
aurel32 已提交
3125
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3126
        return;
B
bellard 已提交
3127
    }
A
aurel32 已提交
3128
    gen_set_access_type(ctx, ACCESS_INT);
3129
    /* NIP cannot be restored if the memory exception comes from an helper */
3130
    gen_update_nip(ctx, ctx->nip - 4);
3131
    t0 = tcg_temp_new();
A
aurel32 已提交
3132
    gen_addr_register(ctx, t0);
3133 3134 3135 3136 3137 3138
    t1 = tcg_const_i32(nb);
    t2 = tcg_const_i32(start);
    gen_helper_lsw(t0, t1, t2);
    tcg_temp_free(t0);
    tcg_temp_free_i32(t1);
    tcg_temp_free_i32(t2);
B
bellard 已提交
3139 3140 3141
}

/* lswx */
3142
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
B
bellard 已提交
3143
{
A
aurel32 已提交
3144 3145 3146
    TCGv t0;
    TCGv_i32 t1, t2, t3;
    gen_set_access_type(ctx, ACCESS_INT);
3147
    /* NIP cannot be restored if the memory exception comes from an helper */
3148
    gen_update_nip(ctx, ctx->nip - 4);
A
aurel32 已提交
3149 3150 3151 3152 3153
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
    t1 = tcg_const_i32(rD(ctx->opcode));
    t2 = tcg_const_i32(rA(ctx->opcode));
    t3 = tcg_const_i32(rB(ctx->opcode));
3154 3155 3156 3157 3158
    gen_helper_lswx(t0, t1, t2, t3);
    tcg_temp_free(t0);
    tcg_temp_free_i32(t1);
    tcg_temp_free_i32(t2);
    tcg_temp_free_i32(t3);
B
bellard 已提交
3159 3160 3161
}

/* stswi */
3162
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
B
bellard 已提交
3163
{
A
aurel32 已提交
3164 3165
    TCGv t0;
    TCGv_i32 t1, t2;
B
bellard 已提交
3166
    int nb = NB(ctx->opcode);
A
aurel32 已提交
3167
    gen_set_access_type(ctx, ACCESS_INT);
3168
    /* NIP cannot be restored if the memory exception comes from an helper */
3169
    gen_update_nip(ctx, ctx->nip - 4);
A
aurel32 已提交
3170 3171
    t0 = tcg_temp_new();
    gen_addr_register(ctx, t0);
B
bellard 已提交
3172 3173
    if (nb == 0)
        nb = 32;
3174
    t1 = tcg_const_i32(nb);
A
aurel32 已提交
3175
    t2 = tcg_const_i32(rS(ctx->opcode));
3176 3177 3178 3179
    gen_helper_stsw(t0, t1, t2);
    tcg_temp_free(t0);
    tcg_temp_free_i32(t1);
    tcg_temp_free_i32(t2);
B
bellard 已提交
3180 3181 3182
}

/* stswx */
3183
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
B
bellard 已提交
3184
{
A
aurel32 已提交
3185 3186 3187
    TCGv t0;
    TCGv_i32 t1, t2;
    gen_set_access_type(ctx, ACCESS_INT);
3188
    /* NIP cannot be restored if the memory exception comes from an helper */
3189
    gen_update_nip(ctx, ctx->nip - 4);
A
aurel32 已提交
3190 3191 3192
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
    t1 = tcg_temp_new_i32();
3193 3194
    tcg_gen_trunc_tl_i32(t1, cpu_xer);
    tcg_gen_andi_i32(t1, t1, 0x7F);
A
aurel32 已提交
3195
    t2 = tcg_const_i32(rS(ctx->opcode));
3196 3197 3198 3199
    gen_helper_stsw(t0, t1, t2);
    tcg_temp_free(t0);
    tcg_temp_free_i32(t1);
    tcg_temp_free_i32(t2);
B
bellard 已提交
3200 3201 3202 3203
}

/***                        Memory synchronisation                         ***/
/* eieio */
3204
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
B
bellard 已提交
3205 3206 3207 3208
{
}

/* isync */
3209
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
B
bellard 已提交
3210
{
A
aurel32 已提交
3211
    gen_stop_exception(ctx);
B
bellard 已提交
3212 3213
}

3214
/* lwarx */
3215
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
B
bellard 已提交
3216
{
A
aurel32 已提交
3217 3218 3219 3220
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_RES);
    t0 = tcg_temp_local_new();
    gen_addr_reg_index(ctx, t0);
3221
    gen_check_align(ctx, t0, 0x03);
A
aurel32 已提交
3222
    gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3223 3224
    tcg_gen_mov_tl(cpu_reserve, t0);
    tcg_temp_free(t0);
B
bellard 已提交
3225 3226 3227
}

/* stwcx. */
3228
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
B
bellard 已提交
3229
{
A
aurel32 已提交
3230 3231 3232 3233 3234
    int l1;
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_RES);
    t0 = tcg_temp_local_new();
    gen_addr_reg_index(ctx, t0);
3235 3236 3237 3238
    gen_check_align(ctx, t0, 0x03);
    tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
    tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
    tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
A
aurel32 已提交
3239
    l1 = gen_new_label();
3240 3241
    tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
    tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
A
aurel32 已提交
3242
    gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3243 3244 3245
    gen_set_label(l1);
    tcg_gen_movi_tl(cpu_reserve, -1);
    tcg_temp_free(t0);
B
bellard 已提交
3246 3247
}

J
j_mayer 已提交
3248 3249
#if defined(TARGET_PPC64)
/* ldarx */
3250
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
J
j_mayer 已提交
3251
{
A
aurel32 已提交
3252 3253 3254 3255
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_RES);
    t0 = tcg_temp_local_new();
    gen_addr_reg_index(ctx, t0);
3256
    gen_check_align(ctx, t0, 0x07);
A
aurel32 已提交
3257
    gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3258 3259
    tcg_gen_mov_tl(cpu_reserve, t0);
    tcg_temp_free(t0);
J
j_mayer 已提交
3260 3261 3262
}

/* stdcx. */
3263
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
J
j_mayer 已提交
3264
{
A
aurel32 已提交
3265 3266 3267 3268 3269
    int l1;
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_RES);
    t0 = tcg_temp_local_new();
    gen_addr_reg_index(ctx, t0);
3270 3271 3272 3273
    gen_check_align(ctx, t0, 0x07);
    tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
    tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
    tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
A
aurel32 已提交
3274
    l1 = gen_new_label();
3275 3276
    tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
    tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
A
aurel32 已提交
3277
    gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3278 3279 3280
    gen_set_label(l1);
    tcg_gen_movi_tl(cpu_reserve, -1);
    tcg_temp_free(t0);
J
j_mayer 已提交
3281 3282 3283
}
#endif /* defined(TARGET_PPC64) */

B
bellard 已提交
3284
/* sync */
3285
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
B
bellard 已提交
3286 3287 3288
{
}

3289 3290 3291
/* wait */
GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
{
3292 3293 3294
    TCGv_i32 t0 = tcg_temp_new_i32();
    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
    tcg_temp_free_i32(t0);
3295
    /* Stop translation, as the CPU is supposed to sleep from now */
A
aurel32 已提交
3296
    gen_exception_err(ctx, EXCP_HLT, 1);
3297 3298
}

B
bellard 已提交
3299
/***                         Floating-point load                           ***/
3300 3301
#define GEN_LDF(name, ldop, opc, type)                                        \
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
B
bellard 已提交
3302
{                                                                             \
3303
    TCGv EA;                                                                  \
3304
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
3305
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3306 3307
        return;                                                               \
    }                                                                         \
A
aurel32 已提交
3308
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3309
    EA = tcg_temp_new();                                                      \
A
aurel32 已提交
3310 3311
    gen_addr_imm_index(ctx, EA, 0);                                           \
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3312
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
3313 3314
}

3315 3316
#define GEN_LDUF(name, ldop, opc, type)                                       \
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
B
bellard 已提交
3317
{                                                                             \
3318
    TCGv EA;                                                                  \
3319
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
3320
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3321 3322
        return;                                                               \
    }                                                                         \
3323
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
A
aurel32 已提交
3324
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3325
        return;                                                               \
3326
    }                                                                         \
A
aurel32 已提交
3327
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3328
    EA = tcg_temp_new();                                                      \
A
aurel32 已提交
3329 3330
    gen_addr_imm_index(ctx, EA, 0);                                           \
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3331 3332
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
3333 3334
}

3335 3336
#define GEN_LDUXF(name, ldop, opc, type)                                      \
GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type)                      \
B
bellard 已提交
3337
{                                                                             \
3338
    TCGv EA;                                                                  \
3339
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
3340
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3341 3342
        return;                                                               \
    }                                                                         \
3343
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
A
aurel32 已提交
3344
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3345
        return;                                                               \
3346
    }                                                                         \
A
aurel32 已提交
3347
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3348
    EA = tcg_temp_new();                                                      \
A
aurel32 已提交
3349 3350
    gen_addr_reg_index(ctx, EA);                                              \
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3351 3352
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
3353 3354
}

3355 3356
#define GEN_LDXF(name, ldop, opc2, opc3, type)                                \
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
B
bellard 已提交
3357
{                                                                             \
3358
    TCGv EA;                                                                  \
3359
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
3360
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3361 3362
        return;                                                               \
    }                                                                         \
A
aurel32 已提交
3363
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3364
    EA = tcg_temp_new();                                                      \
A
aurel32 已提交
3365 3366
    gen_addr_reg_index(ctx, EA);                                              \
    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3367
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
3368 3369
}

3370 3371 3372 3373 3374 3375
#define GEN_LDFS(name, ldop, op, type)                                        \
GEN_LDF(name, ldop, op | 0x20, type);                                         \
GEN_LDUF(name, ldop, op | 0x21, type);                                        \
GEN_LDUXF(name, ldop, op | 0x01, type);                                       \
GEN_LDXF(name, ldop, 0x17, op | 0x00, type)

A
aurel32 已提交
3376
static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3377 3378 3379
{
    TCGv t0 = tcg_temp_new();
    TCGv_i32 t1 = tcg_temp_new_i32();
A
aurel32 已提交
3380
    gen_qemu_ld32u(ctx, t0, arg2);
3381 3382 3383 3384 3385
    tcg_gen_trunc_tl_i32(t1, t0);
    tcg_temp_free(t0);
    gen_helper_float32_to_float64(arg1, t1);
    tcg_temp_free_i32(t1);
}
B
bellard 已提交
3386

3387 3388 3389 3390
 /* lfd lfdu lfdux lfdx */
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
 /* lfs lfsu lfsux lfsx */
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
B
bellard 已提交
3391 3392

/***                         Floating-point store                          ***/
3393 3394
#define GEN_STF(name, stop, opc, type)                                        \
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type)                          \
B
bellard 已提交
3395
{                                                                             \
3396
    TCGv EA;                                                                  \
3397
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
3398
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3399 3400
        return;                                                               \
    }                                                                         \
A
aurel32 已提交
3401
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3402
    EA = tcg_temp_new();                                                      \
A
aurel32 已提交
3403 3404
    gen_addr_imm_index(ctx, EA, 0);                                           \
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3405
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
3406 3407
}

3408 3409
#define GEN_STUF(name, stop, opc, type)                                       \
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type)                       \
B
bellard 已提交
3410
{                                                                             \
3411
    TCGv EA;                                                                  \
3412
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
3413
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3414 3415
        return;                                                               \
    }                                                                         \
3416
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
A
aurel32 已提交
3417
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3418
        return;                                                               \
3419
    }                                                                         \
A
aurel32 已提交
3420
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3421
    EA = tcg_temp_new();                                                      \
A
aurel32 已提交
3422 3423
    gen_addr_imm_index(ctx, EA, 0);                                           \
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3424 3425
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
3426 3427
}

3428 3429
#define GEN_STUXF(name, stop, opc, type)                                      \
GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type)                      \
B
bellard 已提交
3430
{                                                                             \
3431
    TCGv EA;                                                                  \
3432
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
3433
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3434 3435
        return;                                                               \
    }                                                                         \
3436
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
A
aurel32 已提交
3437
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3438
        return;                                                               \
3439
    }                                                                         \
A
aurel32 已提交
3440
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3441
    EA = tcg_temp_new();                                                      \
A
aurel32 已提交
3442 3443
    gen_addr_reg_index(ctx, EA);                                              \
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3444 3445
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
3446 3447
}

3448 3449
#define GEN_STXF(name, stop, opc2, opc3, type)                                \
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type)                      \
B
bellard 已提交
3450
{                                                                             \
3451
    TCGv EA;                                                                  \
3452
    if (unlikely(!ctx->fpu_enabled)) {                                        \
A
aurel32 已提交
3453
        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3454 3455
        return;                                                               \
    }                                                                         \
A
aurel32 已提交
3456
    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3457
    EA = tcg_temp_new();                                                      \
A
aurel32 已提交
3458 3459
    gen_addr_reg_index(ctx, EA);                                              \
    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3460
    tcg_temp_free(EA);                                                        \
B
bellard 已提交
3461 3462
}

3463 3464 3465 3466 3467 3468
#define GEN_STFS(name, stop, op, type)                                        \
GEN_STF(name, stop, op | 0x20, type);                                         \
GEN_STUF(name, stop, op | 0x21, type);                                        \
GEN_STUXF(name, stop, op | 0x01, type);                                       \
GEN_STXF(name, stop, 0x17, op | 0x00, type)

A
aurel32 已提交
3469
static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3470 3471 3472 3473 3474 3475
{
    TCGv_i32 t0 = tcg_temp_new_i32();
    TCGv t1 = tcg_temp_new();
    gen_helper_float64_to_float32(t0, arg1);
    tcg_gen_extu_i32_tl(t1, t0);
    tcg_temp_free_i32(t0);
A
aurel32 已提交
3476
    gen_qemu_st32(ctx, t1, arg2);
3477 3478
    tcg_temp_free(t1);
}
B
bellard 已提交
3479 3480

/* stfd stfdu stfdux stfdx */
3481
GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
B
bellard 已提交
3482
/* stfs stfsu stfsux stfsx */
3483
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
B
bellard 已提交
3484 3485

/* Optional: */
A
aurel32 已提交
3486
static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3487 3488 3489
{
    TCGv t0 = tcg_temp_new();
    tcg_gen_trunc_i64_tl(t0, arg1),
A
aurel32 已提交
3490
    gen_qemu_st32(ctx, t0, arg2);
3491 3492
    tcg_temp_free(t0);
}
B
bellard 已提交
3493
/* stfiwx */
3494
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
B
bellard 已提交
3495 3496

/***                                Branch                                 ***/
3497 3498
static always_inline void gen_goto_tb (DisasContext *ctx, int n,
                                       target_ulong dest)
3499 3500 3501
{
    TranslationBlock *tb;
    tb = ctx->tb;
3502 3503 3504 3505
#if defined(TARGET_PPC64)
    if (!ctx->sf_mode)
        dest = (uint32_t) dest;
#endif
B
bellard 已提交
3506
    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3507
        likely(!ctx->singlestep_enabled)) {
B
bellard 已提交
3508
        tcg_gen_goto_tb(n);
3509
        tcg_gen_movi_tl(cpu_nip, dest & ~3);
B
bellard 已提交
3510
        tcg_gen_exit_tb((long)tb + n);
3511
    } else {
3512
        tcg_gen_movi_tl(cpu_nip, dest & ~3);
3513 3514
        if (unlikely(ctx->singlestep_enabled)) {
            if ((ctx->singlestep_enabled &
A
aurel32 已提交
3515
                (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3516 3517 3518
                ctx->exception == POWERPC_EXCP_BRANCH) {
                target_ulong tmp = ctx->nip;
                ctx->nip = dest;
A
aurel32 已提交
3519
                gen_exception(ctx, POWERPC_EXCP_TRACE);
3520 3521 3522
                ctx->nip = tmp;
            }
            if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
A
aurel32 已提交
3523
                gen_debug_exception(ctx);
3524 3525
            }
        }
B
bellard 已提交
3526
        tcg_gen_exit_tb(0);
3527
    }
B
bellard 已提交
3528 3529
}

3530
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3531 3532
{
#if defined(TARGET_PPC64)
3533 3534
    if (ctx->sf_mode == 0)
        tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3535 3536
    else
#endif
3537
        tcg_gen_movi_tl(cpu_lr, nip);
3538 3539
}

B
bellard 已提交
3540 3541 3542
/* b ba bl bla */
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
{
3543
    target_ulong li, target;
B
bellard 已提交
3544

3545
    ctx->exception = POWERPC_EXCP_BRANCH;
B
bellard 已提交
3546
    /* sign extend LI */
3547
#if defined(TARGET_PPC64)
3548 3549 3550
    if (ctx->sf_mode)
        li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
    else
3551
#endif
3552
        li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3553
    if (likely(AA(ctx->opcode) == 0))
B
bellard 已提交
3554
        target = ctx->nip + li - 4;
B
bellard 已提交
3555
    else
3556
        target = li;
3557 3558
    if (LK(ctx->opcode))
        gen_setlr(ctx, ctx->nip);
3559
    gen_goto_tb(ctx, 0, target);
B
bellard 已提交
3560 3561
}

3562 3563 3564 3565
#define BCOND_IM  0
#define BCOND_LR  1
#define BCOND_CTR 2

3566
static always_inline void gen_bcond (DisasContext *ctx, int type)
3567 3568
{
    uint32_t bo = BO(ctx->opcode);
3569 3570
    int l1 = gen_new_label();
    TCGv target;
3571

3572
    ctx->exception = POWERPC_EXCP_BRANCH;
3573
    if (type == BCOND_LR || type == BCOND_CTR) {
P
pbrook 已提交
3574
        target = tcg_temp_local_new();
3575 3576 3577 3578
        if (type == BCOND_CTR)
            tcg_gen_mov_tl(target, cpu_ctr);
        else
            tcg_gen_mov_tl(target, cpu_lr);
3579
    }
3580 3581
    if (LK(ctx->opcode))
        gen_setlr(ctx, ctx->nip);
3582 3583 3584
    l1 = gen_new_label();
    if ((bo & 0x4) == 0) {
        /* Decrement and test CTR */
P
pbrook 已提交
3585
        TCGv temp = tcg_temp_new();
3586
        if (unlikely(type == BCOND_CTR)) {
A
aurel32 已提交
3587
            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3588 3589 3590
            return;
        }
        tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3591
#if defined(TARGET_PPC64)
3592 3593 3594
        if (!ctx->sf_mode)
            tcg_gen_ext32u_tl(temp, cpu_ctr);
        else
3595
#endif
3596 3597 3598 3599 3600
            tcg_gen_mov_tl(temp, cpu_ctr);
        if (bo & 0x2) {
            tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
        } else {
            tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3601
        }
P
pbrook 已提交
3602
        tcg_temp_free(temp);
3603 3604 3605 3606 3607
    }
    if ((bo & 0x10) == 0) {
        /* Test CR */
        uint32_t bi = BI(ctx->opcode);
        uint32_t mask = 1 << (3 - (bi & 0x03));
P
pbrook 已提交
3608
        TCGv_i32 temp = tcg_temp_new_i32();
3609

3610
        if (bo & 0x8) {
3611 3612
            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
            tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3613
        } else {
3614 3615
            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
            tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3616
        }
P
pbrook 已提交
3617
        tcg_temp_free_i32(temp);
3618
    }
3619
    if (type == BCOND_IM) {
3620 3621 3622 3623 3624 3625
        target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
        if (likely(AA(ctx->opcode) == 0)) {
            gen_goto_tb(ctx, 0, ctx->nip + li - 4);
        } else {
            gen_goto_tb(ctx, 0, li);
        }
B
bellard 已提交
3626
        gen_set_label(l1);
3627
        gen_goto_tb(ctx, 1, ctx->nip);
3628
    } else {
3629
#if defined(TARGET_PPC64)
3630 3631 3632 3633 3634 3635 3636 3637 3638 3639
        if (!(ctx->sf_mode))
            tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
        else
#endif
            tcg_gen_andi_tl(cpu_nip, target, ~3);
        tcg_gen_exit_tb(0);
        gen_set_label(l1);
#if defined(TARGET_PPC64)
        if (!(ctx->sf_mode))
            tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3640 3641
        else
#endif
3642
            tcg_gen_movi_tl(cpu_nip, ctx->nip);
B
bellard 已提交
3643
        tcg_gen_exit_tb(0);
J
j_mayer 已提交
3644
    }
3645 3646 3647
}

GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3648
{
3649 3650 3651 3652
    gen_bcond(ctx, BCOND_IM);
}

GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3653
{
3654 3655 3656 3657
    gen_bcond(ctx, BCOND_CTR);
}

GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3658
{
3659 3660
    gen_bcond(ctx, BCOND_LR);
}
B
bellard 已提交
3661 3662

/***                      Condition register logical                       ***/
3663 3664
#define GEN_CRLOGIC(name, tcg_op, opc)                                        \
GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                   \
B
bellard 已提交
3665
{                                                                             \
3666 3667
    uint8_t bitmask;                                                          \
    int sh;                                                                   \
P
pbrook 已提交
3668
    TCGv_i32 t0, t1;                                                          \
3669
    sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
P
pbrook 已提交
3670
    t0 = tcg_temp_new_i32();                                                  \
3671
    if (sh > 0)                                                               \
3672
        tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh);            \
3673
    else if (sh < 0)                                                          \
3674
        tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh);           \
3675
    else                                                                      \
3676
        tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]);                 \
P
pbrook 已提交
3677
    t1 = tcg_temp_new_i32();                                                  \
3678 3679
    sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
    if (sh > 0)                                                               \
3680
        tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh);            \
3681
    else if (sh < 0)                                                          \
3682
        tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh);           \
3683
    else                                                                      \
3684 3685
        tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]);                 \
    tcg_op(t0, t0, t1);                                                       \
3686
    bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));                          \
3687 3688 3689
    tcg_gen_andi_i32(t0, t0, bitmask);                                        \
    tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);          \
    tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);                  \
P
pbrook 已提交
3690 3691
    tcg_temp_free_i32(t0);                                                    \
    tcg_temp_free_i32(t1);                                                    \
B
bellard 已提交
3692 3693 3694
}

/* crand */
3695
GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
B
bellard 已提交
3696
/* crandc */
3697
GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
B
bellard 已提交
3698
/* creqv */
3699
GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
B
bellard 已提交
3700
/* crnand */
3701
GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
B
bellard 已提交
3702
/* crnor */
3703
GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
B
bellard 已提交
3704
/* cror */
3705
GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
B
bellard 已提交
3706
/* crorc */
3707
GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
B
bellard 已提交
3708
/* crxor */
3709
GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
B
bellard 已提交
3710 3711 3712
/* mcrf */
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
{
A
aurel32 已提交
3713
    tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
B
bellard 已提交
3714 3715 3716
}

/***                           System linkage                              ***/
A
aurel32 已提交
3717
/* rfi (mem_idx only) */
3718
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
B
bellard 已提交
3719
{
3720
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
3721
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3722 3723
#else
    /* Restore CPU state */
A
aurel32 已提交
3724
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
3725
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3726
        return;
3727
    }
3728
    gen_helper_rfi();
A
aurel32 已提交
3729
    gen_sync_exception(ctx);
3730
#endif
B
bellard 已提交
3731 3732
}

J
j_mayer 已提交
3733
#if defined(TARGET_PPC64)
3734
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
J
j_mayer 已提交
3735 3736
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
3737
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
J
j_mayer 已提交
3738 3739
#else
    /* Restore CPU state */
A
aurel32 已提交
3740
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
3741
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
J
j_mayer 已提交
3742 3743
        return;
    }
3744
    gen_helper_rfid();
A
aurel32 已提交
3745
    gen_sync_exception(ctx);
J
j_mayer 已提交
3746 3747 3748
#endif
}

J
j_mayer 已提交
3749
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3750 3751
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
3752
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3753 3754
#else
    /* Restore CPU state */
A
aurel32 已提交
3755
    if (unlikely(ctx->mem_idx <= 1)) {
A
aurel32 已提交
3756
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3757 3758
        return;
    }
3759
    gen_helper_hrfid();
A
aurel32 已提交
3760
    gen_sync_exception(ctx);
3761 3762 3763 3764
#endif
}
#endif

B
bellard 已提交
3765
/* sc */
3766 3767 3768 3769 3770
#if defined(CONFIG_USER_ONLY)
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
#else
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
#endif
3771
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
B
bellard 已提交
3772
{
3773 3774 3775
    uint32_t lev;

    lev = (ctx->opcode >> 5) & 0x7F;
A
aurel32 已提交
3776
    gen_exception_err(ctx, POWERPC_SYSCALL, lev);
B
bellard 已提交
3777 3778 3779 3780
}

/***                                Trap                                   ***/
/* tw */
3781
GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
B
bellard 已提交
3782
{
3783
    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3784
    /* Update the nip since this might generate a trap exception */
3785
    gen_update_nip(ctx, ctx->nip);
3786 3787
    gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
    tcg_temp_free_i32(t0);
B
bellard 已提交
3788 3789 3790 3791 3792
}

/* twi */
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
{
3793 3794
    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3795 3796
    /* Update the nip since this might generate a trap exception */
    gen_update_nip(ctx, ctx->nip);
3797 3798 3799
    gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free_i32(t1);
B
bellard 已提交
3800 3801
}

3802 3803 3804 3805
#if defined(TARGET_PPC64)
/* td */
GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
{
3806
    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3807 3808
    /* Update the nip since this might generate a trap exception */
    gen_update_nip(ctx, ctx->nip);
3809 3810
    gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
    tcg_temp_free_i32(t0);
3811 3812 3813 3814 3815
}

/* tdi */
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
{
3816 3817
    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3818 3819
    /* Update the nip since this might generate a trap exception */
    gen_update_nip(ctx, ctx->nip);
3820 3821 3822
    gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free_i32(t1);
3823 3824 3825
}
#endif

B
bellard 已提交
3826 3827 3828 3829
/***                          Processor control                            ***/
/* mcrxr */
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
{
A
aurel32 已提交
3830 3831
    tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3832
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
B
bellard 已提交
3833 3834 3835
}

/* mfcr */
3836
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
B
bellard 已提交
3837
{
3838
    uint32_t crm, crn;
3839

3840 3841 3842 3843
    if (likely(ctx->opcode & 0x00100000)) {
        crm = CRM(ctx->opcode);
        if (likely((crm ^ (crm - 1)) == 0)) {
            crn = ffs(crm);
3844
            tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3845
        }
3846
    } else {
P
pbrook 已提交
3847
        gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3848
    }
B
bellard 已提交
3849 3850 3851 3852 3853
}

/* mfmsr */
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
{
3854
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
3855
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3856
#else
A
aurel32 已提交
3857
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
3858
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3859
        return;
3860
    }
3861
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3862
#endif
B
bellard 已提交
3863 3864
}

J
j_mayer 已提交
3865
#if 1
3866
#define SPR_NOACCESS ((void *)(-1UL))
3867 3868 3869 3870 3871 3872 3873 3874 3875
#else
static void spr_noaccess (void *opaque, int sprn)
{
    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
    printf("ERROR: try to access SPR %d !\n", sprn);
}
#define SPR_NOACCESS (&spr_noaccess)
#endif

B
bellard 已提交
3876
/* mfspr */
3877
static always_inline void gen_op_mfspr (DisasContext *ctx)
B
bellard 已提交
3878
{
A
aurel32 已提交
3879
    void (*read_cb)(void *opaque, int gprn, int sprn);
B
bellard 已提交
3880 3881
    uint32_t sprn = SPR(ctx->opcode);

3882
#if !defined(CONFIG_USER_ONLY)
A
aurel32 已提交
3883
    if (ctx->mem_idx == 2)
3884
        read_cb = ctx->spr_cb[sprn].hea_read;
A
aurel32 已提交
3885
    else if (ctx->mem_idx)
3886 3887
        read_cb = ctx->spr_cb[sprn].oea_read;
    else
3888
#endif
3889
        read_cb = ctx->spr_cb[sprn].uea_read;
3890 3891
    if (likely(read_cb != NULL)) {
        if (likely(read_cb != SPR_NOACCESS)) {
A
aurel32 已提交
3892
            (*read_cb)(ctx, rD(ctx->opcode), sprn);
3893 3894
        } else {
            /* Privilege exception */
3895 3896 3897 3898 3899
            /* This is a hack to avoid warnings when running Linux:
             * this OS breaks the PowerPC virtualisation model,
             * allowing userland application to read the PVR
             */
            if (sprn != SPR_PVR) {
3900
                qemu_log("Trying to read privileged spr %d %03x at "
J
j_mayer 已提交
3901 3902 3903
                            ADDRX "\n", sprn, sprn, ctx->nip);
                printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
                       sprn, sprn, ctx->nip);
3904
            }
A
aurel32 已提交
3905
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
B
bellard 已提交
3906
        }
3907 3908
    } else {
        /* Not defined */
3909
        qemu_log("Trying to read invalid spr %d %03x at "
J
j_mayer 已提交
3910 3911 3912
                    ADDRX "\n", sprn, sprn, ctx->nip);
        printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
               sprn, sprn, ctx->nip);
A
aurel32 已提交
3913
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
B
bellard 已提交
3914 3915 3916
    }
}

3917
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
B
bellard 已提交
3918
{
3919
    gen_op_mfspr(ctx);
3920
}
3921 3922

/* mftb */
3923
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3924 3925
{
    gen_op_mfspr(ctx);
B
bellard 已提交
3926 3927 3928
}

/* mtcrf */
3929
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
B
bellard 已提交
3930
{
3931
    uint32_t crm, crn;
3932

3933 3934
    crm = CRM(ctx->opcode);
    if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
P
pbrook 已提交
3935
        TCGv_i32 temp = tcg_temp_new_i32();
3936
        crn = ffs(crm);
P
pbrook 已提交
3937 3938
        tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
        tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3939
        tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
P
pbrook 已提交
3940
        tcg_temp_free_i32(temp);
3941
    } else {
P
pbrook 已提交
3942 3943 3944
        TCGv_i32 temp = tcg_const_i32(crm);
        gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
        tcg_temp_free_i32(temp);
3945
    }
B
bellard 已提交
3946 3947 3948
}

/* mtmsr */
J
j_mayer 已提交
3949
#if defined(TARGET_PPC64)
3950
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
J
j_mayer 已提交
3951 3952
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
3953
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
J
j_mayer 已提交
3954
#else
A
aurel32 已提交
3955
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
3956
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
J
j_mayer 已提交
3957 3958
        return;
    }
3959 3960
    if (ctx->opcode & 0x00010000) {
        /* Special form that does not need any synchronisation */
3961 3962 3963 3964 3965
        TCGv t0 = tcg_temp_new();
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
        tcg_temp_free(t0);
3966
    } else {
3967 3968 3969 3970
        /* XXX: we need to update nip before the store
         *      if we enter power saving mode, we will exit the loop
         *      directly from ppc_store_msr
         */
3971
        gen_update_nip(ctx, ctx->nip);
3972
        gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3973 3974
        /* Must stop the translation as machine state (may have) changed */
        /* Note that mtmsr is not always defined as context-synchronizing */
A
aurel32 已提交
3975
        gen_stop_exception(ctx);
3976
    }
J
j_mayer 已提交
3977 3978 3979 3980
#endif
}
#endif

B
bellard 已提交
3981 3982
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
{
3983
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
3984
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3985
#else
A
aurel32 已提交
3986
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
3987
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3988
        return;
3989
    }
3990 3991
    if (ctx->opcode & 0x00010000) {
        /* Special form that does not need any synchronisation */
3992 3993 3994 3995 3996
        TCGv t0 = tcg_temp_new();
        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
        tcg_temp_free(t0);
3997
    } else {
3998 3999 4000 4001
        /* XXX: we need to update nip before the store
         *      if we enter power saving mode, we will exit the loop
         *      directly from ppc_store_msr
         */
4002
        gen_update_nip(ctx, ctx->nip);
4003
#if defined(TARGET_PPC64)
4004 4005 4006 4007 4008 4009 4010 4011 4012 4013
        if (!ctx->sf_mode) {
            TCGv t0 = tcg_temp_new();
            TCGv t1 = tcg_temp_new();
            tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
            tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
            tcg_gen_or_tl(t0, t0, t1);
            tcg_temp_free(t1);
            gen_helper_store_msr(t0);
            tcg_temp_free(t0);
        } else
4014
#endif
4015
            gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
4016
        /* Must stop the translation as machine state (may have) changed */
4017
        /* Note that mtmsr is not always defined as context-synchronizing */
A
aurel32 已提交
4018
        gen_stop_exception(ctx);
4019
    }
4020
#endif
B
bellard 已提交
4021 4022 4023 4024 4025
}

/* mtspr */
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
{
A
aurel32 已提交
4026
    void (*write_cb)(void *opaque, int sprn, int gprn);
B
bellard 已提交
4027 4028
    uint32_t sprn = SPR(ctx->opcode);

4029
#if !defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4030
    if (ctx->mem_idx == 2)
4031
        write_cb = ctx->spr_cb[sprn].hea_write;
A
aurel32 已提交
4032
    else if (ctx->mem_idx)
4033 4034
        write_cb = ctx->spr_cb[sprn].oea_write;
    else
4035
#endif
4036
        write_cb = ctx->spr_cb[sprn].uea_write;
4037 4038
    if (likely(write_cb != NULL)) {
        if (likely(write_cb != SPR_NOACCESS)) {
A
aurel32 已提交
4039
            (*write_cb)(ctx, sprn, rS(ctx->opcode));
4040 4041
        } else {
            /* Privilege exception */
4042
            qemu_log("Trying to write privileged spr %d %03x at "
J
j_mayer 已提交
4043 4044 4045
                        ADDRX "\n", sprn, sprn, ctx->nip);
            printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
                   sprn, sprn, ctx->nip);
A
aurel32 已提交
4046
            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4047
        }
4048 4049
    } else {
        /* Not defined */
4050
        qemu_log("Trying to write invalid spr %d %03x at "
J
j_mayer 已提交
4051 4052 4053
                    ADDRX "\n", sprn, sprn, ctx->nip);
        printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
               sprn, sprn, ctx->nip);
A
aurel32 已提交
4054
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
B
bellard 已提交
4055 4056 4057 4058 4059
    }
}

/***                         Cache management                              ***/
/* dcbf */
4060
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
B
bellard 已提交
4061
{
J
j_mayer 已提交
4062
    /* XXX: specification says this is treated as a load by the MMU */
A
aurel32 已提交
4063 4064 4065 4066 4067
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_CACHE);
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
    gen_qemu_ld8u(ctx, t0, t0);
4068
    tcg_temp_free(t0);
B
bellard 已提交
4069 4070 4071
}

/* dcbi (Supervisor only) */
4072
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
B
bellard 已提交
4073
{
4074
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4075
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4076
#else
A
aurel32 已提交
4077
    TCGv EA, val;
A
aurel32 已提交
4078
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4079
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4080
        return;
4081
    }
P
pbrook 已提交
4082
    EA = tcg_temp_new();
A
aurel32 已提交
4083 4084
    gen_set_access_type(ctx, ACCESS_CACHE);
    gen_addr_reg_index(ctx, EA);
P
pbrook 已提交
4085
    val = tcg_temp_new();
4086
    /* XXX: specification says this should be treated as a store by the MMU */
A
aurel32 已提交
4087 4088
    gen_qemu_ld8u(ctx, val, EA);
    gen_qemu_st8(ctx, val, EA);
A
aurel32 已提交
4089 4090
    tcg_temp_free(val);
    tcg_temp_free(EA);
4091
#endif
B
bellard 已提交
4092 4093 4094
}

/* dcdst */
4095
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
B
bellard 已提交
4096
{
4097
    /* XXX: specification say this is treated as a load by the MMU */
A
aurel32 已提交
4098 4099 4100 4101 4102
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_CACHE);
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
    gen_qemu_ld8u(ctx, t0, t0);
4103
    tcg_temp_free(t0);
B
bellard 已提交
4104 4105 4106
}

/* dcbt */
4107
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
B
bellard 已提交
4108
{
4109
    /* interpreted as no-op */
4110 4111 4112
    /* XXX: specification say this is treated as a load by the MMU
     *      but does not generate any exception
     */
B
bellard 已提交
4113 4114 4115
}

/* dcbtst */
4116
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
B
bellard 已提交
4117
{
4118
    /* interpreted as no-op */
4119 4120 4121
    /* XXX: specification say this is treated as a load by the MMU
     *      but does not generate any exception
     */
B
bellard 已提交
4122 4123 4124
}

/* dcbz */
4125
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
B
bellard 已提交
4126
{
A
aurel32 已提交
4127 4128
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_CACHE);
4129 4130
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
A
aurel32 已提交
4131 4132
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
4133 4134
    gen_helper_dcbz(t0);
    tcg_temp_free(t0);
4135 4136
}

4137
GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4138
{
A
aurel32 已提交
4139 4140
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_CACHE);
4141 4142
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
A
aurel32 已提交
4143 4144
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
4145
    if (ctx->opcode & 0x00200000)
4146
        gen_helper_dcbz(t0);
4147
    else
4148 4149
        gen_helper_dcbz_970(t0);
    tcg_temp_free(t0);
B
bellard 已提交
4150 4151
}

4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178
/* dst / dstt */
GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
{
    if (rA(ctx->opcode) == 0) {
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
    } else {
        /* interpreted as no-op */
    }
}

/* dstst /dststt */
GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
{
    if (rA(ctx->opcode) == 0) {
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
    } else {
        /* interpreted as no-op */
    }

}

/* dss / dssall */
GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
{
    /* interpreted as no-op */
}

B
bellard 已提交
4179
/* icbi */
4180
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
B
bellard 已提交
4181
{
A
aurel32 已提交
4182 4183
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_CACHE);
4184 4185
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
A
aurel32 已提交
4186 4187
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
4188 4189
    gen_helper_icbi(t0);
    tcg_temp_free(t0);
B
bellard 已提交
4190 4191 4192 4193
}

/* Optional: */
/* dcba */
4194
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
B
bellard 已提交
4195
{
4196 4197 4198 4199
    /* interpreted as no-op */
    /* XXX: specification say this is treated as a store by the MMU
     *      but does not generate any exception
     */
B
bellard 已提交
4200 4201 4202 4203 4204 4205 4206
}

/***                    Segment register manipulation                      ***/
/* Supervisor only: */
/* mfsr */
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
{
4207
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4208
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4209
#else
4210
    TCGv t0;
A
aurel32 已提交
4211
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4212
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4213
        return;
4214
    }
4215 4216 4217
    t0 = tcg_const_tl(SR(ctx->opcode));
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free(t0);
4218
#endif
B
bellard 已提交
4219 4220 4221
}

/* mfsrin */
4222
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
B
bellard 已提交
4223
{
4224
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4225
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4226
#else
4227
    TCGv t0;
A
aurel32 已提交
4228
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4229
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4230
        return;
4231
    }
4232 4233 4234 4235 4236
    t0 = tcg_temp_new();
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
    tcg_gen_andi_tl(t0, t0, 0xF);
    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free(t0);
4237
#endif
B
bellard 已提交
4238 4239 4240
}

/* mtsr */
B
bellard 已提交
4241
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
B
bellard 已提交
4242
{
4243
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4244
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4245
#else
4246
    TCGv t0;
A
aurel32 已提交
4247
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4248
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4249
        return;
4250
    }
4251 4252 4253
    t0 = tcg_const_tl(SR(ctx->opcode));
    gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
    tcg_temp_free(t0);
4254
#endif
B
bellard 已提交
4255 4256 4257
}

/* mtsrin */
4258
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
B
bellard 已提交
4259
{
4260
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4261
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4262
#else
4263
    TCGv t0;
A
aurel32 已提交
4264
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4265
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4266
        return;
4267
    }
4268 4269 4270 4271 4272
    t0 = tcg_temp_new();
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
    tcg_gen_andi_tl(t0, t0, 0xF);
    gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
    tcg_temp_free(t0);
4273
#endif
B
bellard 已提交
4274 4275
}

4276 4277 4278
#if defined(TARGET_PPC64)
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
/* mfsr */
4279
GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4280 4281
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4282
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4283
#else
4284
    TCGv t0;
A
aurel32 已提交
4285
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4286
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4287 4288
        return;
    }
4289 4290 4291
    t0 = tcg_const_tl(SR(ctx->opcode));
    gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free(t0);
4292 4293 4294 4295
#endif
}

/* mfsrin */
4296 4297
GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
             PPC_SEGMENT_64B)
4298 4299
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4300
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4301
#else
4302
    TCGv t0;
A
aurel32 已提交
4303
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4304
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4305 4306
        return;
    }
4307 4308 4309 4310 4311
    t0 = tcg_temp_new();
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
    tcg_gen_andi_tl(t0, t0, 0xF);
    gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free(t0);
4312 4313 4314 4315
#endif
}

/* mtsr */
4316
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4317 4318
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4319
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4320
#else
4321
    TCGv t0;
A
aurel32 已提交
4322
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4323
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4324 4325
        return;
    }
4326 4327 4328
    t0 = tcg_const_tl(SR(ctx->opcode));
    gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
    tcg_temp_free(t0);
4329 4330 4331 4332
#endif
}

/* mtsrin */
4333 4334
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
             PPC_SEGMENT_64B)
4335 4336
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4337
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4338
#else
4339
    TCGv t0;
A
aurel32 已提交
4340
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4341
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4342 4343
        return;
    }
4344 4345 4346 4347 4348
    t0 = tcg_temp_new();
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
    tcg_gen_andi_tl(t0, t0, 0xF);
    gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
    tcg_temp_free(t0);
4349 4350 4351 4352
#endif
}
#endif /* defined(TARGET_PPC64) */

B
bellard 已提交
4353
/***                      Lookaside buffer management                      ***/
A
aurel32 已提交
4354
/* Optional & mem_idx only: */
B
bellard 已提交
4355
/* tlbia */
4356
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
B
bellard 已提交
4357
{
4358
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4359
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4360
#else
A
aurel32 已提交
4361
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4362
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4363
        return;
4364
    }
4365
    gen_helper_tlbia();
4366
#endif
B
bellard 已提交
4367 4368 4369
}

/* tlbie */
4370
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
B
bellard 已提交
4371
{
4372
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4373
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4374
#else
A
aurel32 已提交
4375
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4376
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4377
        return;
4378
    }
4379
#if defined(TARGET_PPC64)
4380 4381 4382 4383 4384 4385
    if (!ctx->sf_mode) {
        TCGv t0 = tcg_temp_new();
        tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
        gen_helper_tlbie(t0);
        tcg_temp_free(t0);
    } else
4386
#endif
4387
        gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4388
#endif
B
bellard 已提交
4389 4390 4391
}

/* tlbsync */
4392
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
B
bellard 已提交
4393
{
4394
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4395
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4396
#else
A
aurel32 已提交
4397
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4398
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4399
        return;
4400 4401 4402 4403
    }
    /* This has no effect: it should ensure that all previous
     * tlbie have completed
     */
A
aurel32 已提交
4404
    gen_stop_exception(ctx);
4405
#endif
B
bellard 已提交
4406 4407
}

J
j_mayer 已提交
4408 4409 4410 4411 4412
#if defined(TARGET_PPC64)
/* slbia */
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4413
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
J
j_mayer 已提交
4414
#else
A
aurel32 已提交
4415
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4416
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
J
j_mayer 已提交
4417 4418
        return;
    }
4419
    gen_helper_slbia();
J
j_mayer 已提交
4420 4421 4422 4423 4424 4425 4426
#endif
}

/* slbie */
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
4427
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
J
j_mayer 已提交
4428
#else
A
aurel32 已提交
4429
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
4430
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
J
j_mayer 已提交
4431 4432
        return;
    }
4433
    gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
J
j_mayer 已提交
4434 4435 4436 4437
#endif
}
#endif

B
bellard 已提交
4438 4439
/***                              External control                         ***/
/* Optional: */
4440
/* eciwx */
B
bellard 已提交
4441 4442
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
{
A
aurel32 已提交
4443
    TCGv t0;
4444
    /* Should check EAR[E] ! */
A
aurel32 已提交
4445 4446 4447
    gen_set_access_type(ctx, ACCESS_EXT);
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
4448
    gen_check_align(ctx, t0, 0x03);
A
aurel32 已提交
4449
    gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4450
    tcg_temp_free(t0);
4451 4452 4453 4454 4455
}

/* ecowx */
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
{
A
aurel32 已提交
4456
    TCGv t0;
4457
    /* Should check EAR[E] ! */
A
aurel32 已提交
4458 4459 4460
    gen_set_access_type(ctx, ACCESS_EXT);
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
4461
    gen_check_align(ctx, t0, 0x03);
A
aurel32 已提交
4462
    gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4463
    tcg_temp_free(t0);
4464 4465 4466 4467 4468 4469
}

/* PowerPC 601 specific instructions */
/* abs - abs. */
GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
{
4470 4471 4472 4473 4474 4475 4476 4477
    int l1 = gen_new_label();
    int l2 = gen_new_label();
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    gen_set_label(l2);
4478
    if (unlikely(Rc(ctx->opcode) != 0))
4479
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4480 4481 4482 4483 4484
}

/* abso - abso. */
GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
{
4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499
    int l1 = gen_new_label();
    int l2 = gen_new_label();
    int l3 = gen_new_label();
    /* Start with XER OV disabled, the most likely case */
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_br(l3);
    gen_set_label(l2);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    gen_set_label(l3);
4500
    if (unlikely(Rc(ctx->opcode) != 0))
4501
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4502 4503 4504
}

/* clcs */
4505
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4506
{
4507 4508 4509
    TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
    gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free_i32(t0);
4510
    /* Rc=1 sets CR0 to an undefined state */
4511 4512 4513 4514 4515
}

/* div - div. */
GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
{
4516
    gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4517
    if (unlikely(Rc(ctx->opcode) != 0))
4518
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4519 4520 4521 4522 4523
}

/* divo - divo. */
GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
{
4524
    gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4525
    if (unlikely(Rc(ctx->opcode) != 0))
4526
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4527 4528 4529 4530 4531
}

/* divs - divs. */
GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
{
4532
    gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4533
    if (unlikely(Rc(ctx->opcode) != 0))
4534
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4535 4536 4537 4538 4539
}

/* divso - divso. */
GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
{
4540
    gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4541
    if (unlikely(Rc(ctx->opcode) != 0))
4542
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4543 4544 4545 4546 4547
}

/* doz - doz. */
GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
{
4548 4549 4550 4551 4552 4553 4554 4555
    int l1 = gen_new_label();
    int l2 = gen_new_label();
    tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
    tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
    gen_set_label(l2);
4556
    if (unlikely(Rc(ctx->opcode) != 0))
4557
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4558 4559 4560 4561 4562
}

/* dozo - dozo. */
GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
{
4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584
    int l1 = gen_new_label();
    int l2 = gen_new_label();
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    TCGv t2 = tcg_temp_new();
    /* Start with XER OV disabled, the most likely case */
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
    tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
    tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
    tcg_gen_andc_tl(t1, t1, t2);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
    gen_set_label(l2);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
    tcg_temp_free(t2);
4585
    if (unlikely(Rc(ctx->opcode) != 0))
4586
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4587 4588 4589 4590 4591
}

/* dozi */
GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
{
4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602
    target_long simm = SIMM(ctx->opcode);
    int l1 = gen_new_label();
    int l2 = gen_new_label();
    tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
    tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
    gen_set_label(l2);
    if (unlikely(Rc(ctx->opcode) != 0))
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4603 4604 4605 4606 4607
}

/* lscbx - lscbx. */
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
{
4608 4609 4610 4611
    TCGv t0 = tcg_temp_new();
    TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
    TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
    TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4612

A
aurel32 已提交
4613
    gen_addr_reg_index(ctx, t0);
4614
    /* NIP cannot be restored if the memory exception comes from an helper */
4615
    gen_update_nip(ctx, ctx->nip - 4);
4616 4617 4618 4619
    gen_helper_lscbx(t0, t0, t1, t2, t3);
    tcg_temp_free_i32(t1);
    tcg_temp_free_i32(t2);
    tcg_temp_free_i32(t3);
A
aurel32 已提交
4620
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4621
    tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4622
    if (unlikely(Rc(ctx->opcode) != 0))
4623 4624
        gen_set_Rc0(ctx, t0);
    tcg_temp_free(t0);
4625 4626 4627 4628 4629
}

/* maskg - maskg. */
GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
{
4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648
    int l1 = gen_new_label();
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    TCGv t2 = tcg_temp_new();
    TCGv t3 = tcg_temp_new();
    tcg_gen_movi_tl(t3, 0xFFFFFFFF);
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
    tcg_gen_addi_tl(t2, t0, 1);
    tcg_gen_shr_tl(t2, t3, t2);
    tcg_gen_shr_tl(t3, t3, t1);
    tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
    tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
    tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    gen_set_label(l1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
    tcg_temp_free(t2);
    tcg_temp_free(t3);
4649
    if (unlikely(Rc(ctx->opcode) != 0))
4650
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4651 4652 4653 4654 4655
}

/* maskir - maskir. */
GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
{
4656 4657 4658 4659 4660 4661 4662
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
    tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
4663
    if (unlikely(Rc(ctx->opcode) != 0))
4664
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4665 4666 4667 4668 4669
}

/* mul - mul. */
GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
{
4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682
    TCGv_i64 t0 = tcg_temp_new_i64();
    TCGv_i64 t1 = tcg_temp_new_i64();
    TCGv t2 = tcg_temp_new();
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
    tcg_gen_mul_i64(t0, t0, t1);
    tcg_gen_trunc_i64_tl(t2, t0);
    gen_store_spr(SPR_MQ, t2);
    tcg_gen_shri_i64(t1, t0, 32);
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
    tcg_temp_free_i64(t0);
    tcg_temp_free_i64(t1);
    tcg_temp_free(t2);
4683
    if (unlikely(Rc(ctx->opcode) != 0))
4684
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4685 4686 4687 4688 4689
}

/* mulo - mulo. */
GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
{
4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709
    int l1 = gen_new_label();
    TCGv_i64 t0 = tcg_temp_new_i64();
    TCGv_i64 t1 = tcg_temp_new_i64();
    TCGv t2 = tcg_temp_new();
    /* Start with XER OV disabled, the most likely case */
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
    tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
    tcg_gen_mul_i64(t0, t0, t1);
    tcg_gen_trunc_i64_tl(t2, t0);
    gen_store_spr(SPR_MQ, t2);
    tcg_gen_shri_i64(t1, t0, 32);
    tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
    tcg_gen_ext32s_i64(t1, t0);
    tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
    gen_set_label(l1);
    tcg_temp_free_i64(t0);
    tcg_temp_free_i64(t1);
    tcg_temp_free(t2);
4710
    if (unlikely(Rc(ctx->opcode) != 0))
4711
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4712 4713 4714 4715 4716
}

/* nabs - nabs. */
GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
{
4717 4718 4719 4720 4721 4722 4723 4724
    int l1 = gen_new_label();
    int l2 = gen_new_label();
    tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    gen_set_label(l2);
4725
    if (unlikely(Rc(ctx->opcode) != 0))
4726
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4727 4728 4729 4730 4731
}

/* nabso - nabso. */
GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
{
4732 4733 4734 4735 4736 4737 4738 4739 4740 4741
    int l1 = gen_new_label();
    int l2 = gen_new_label();
    tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
    gen_set_label(l2);
    /* nabs never overflows */
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4742
    if (unlikely(Rc(ctx->opcode) != 0))
4743
        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4744 4745 4746 4747 4748
}

/* rlmi - rlmi. */
GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
{
4749 4750 4751 4752 4753 4754 4755 4756 4757
    uint32_t mb = MB(ctx->opcode);
    uint32_t me = ME(ctx->opcode);
    TCGv t0 = tcg_temp_new();
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
    tcg_gen_andi_tl(t0, t0, MASK(mb, me));
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
    tcg_temp_free(t0);
4758
    if (unlikely(Rc(ctx->opcode) != 0))
4759
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4760 4761 4762 4763 4764
}

/* rrib - rrib. */
GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
{
4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_movi_tl(t1, 0x80000000);
    tcg_gen_shr_tl(t1, t1, t0);
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
    tcg_gen_and_tl(t0, t0, t1);
    tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
4776
    if (unlikely(Rc(ctx->opcode) != 0))
4777
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4778 4779 4780 4781 4782
}

/* sle - sle. */
GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
{
4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
    tcg_gen_subfi_tl(t1, 32, t1);
    tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
    tcg_gen_or_tl(t1, t0, t1);
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
    gen_store_spr(SPR_MQ, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
4794
    if (unlikely(Rc(ctx->opcode) != 0))
4795
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4796 4797 4798 4799 4800
}

/* sleq - sleq. */
GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
{
4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    TCGv t2 = tcg_temp_new();
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_movi_tl(t2, 0xFFFFFFFF);
    tcg_gen_shl_tl(t2, t2, t0);
    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
    gen_load_spr(t1, SPR_MQ);
    gen_store_spr(SPR_MQ, t0);
    tcg_gen_and_tl(t0, t0, t2);
    tcg_gen_andc_tl(t1, t1, t2);
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
    tcg_temp_free(t2);
4816
    if (unlikely(Rc(ctx->opcode) != 0))
4817
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4818 4819 4820 4821 4822
}

/* sliq - sliq. */
GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
{
4823 4824 4825 4826 4827 4828 4829 4830 4831 4832
    int sh = SH(ctx->opcode);
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
    tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
    tcg_gen_or_tl(t1, t0, t1);
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
    gen_store_spr(SPR_MQ, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
4833
    if (unlikely(Rc(ctx->opcode) != 0))
4834
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4835 4836 4837 4838 4839
}

/* slliq - slliq. */
GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
{
4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850
    int sh = SH(ctx->opcode);
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
    gen_load_spr(t1, SPR_MQ);
    gen_store_spr(SPR_MQ, t0);
    tcg_gen_andi_tl(t0, t0,  (0xFFFFFFFFU << sh));
    tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
4851
    if (unlikely(Rc(ctx->opcode) != 0))
4852
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4853 4854 4855 4856 4857
}

/* sllq - sllq. */
GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
{
4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879
    int l1 = gen_new_label();
    int l2 = gen_new_label();
    TCGv t0 = tcg_temp_local_new();
    TCGv t1 = tcg_temp_local_new();
    TCGv t2 = tcg_temp_local_new();
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_movi_tl(t1, 0xFFFFFFFF);
    tcg_gen_shl_tl(t1, t1, t2);
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
    gen_load_spr(t0, SPR_MQ);
    tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
    gen_load_spr(t2, SPR_MQ);
    tcg_gen_andc_tl(t1, t2, t1);
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
    gen_set_label(l2);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
    tcg_temp_free(t2);
4880
    if (unlikely(Rc(ctx->opcode) != 0))
4881
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4882 4883 4884 4885 4886
}

/* slq - slq. */
GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
{
4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902
    int l1 = gen_new_label();
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
    tcg_gen_subfi_tl(t1, 32, t1);
    tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
    tcg_gen_or_tl(t1, t0, t1);
    gen_store_spr(SPR_MQ, t1);
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
    gen_set_label(l1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
4903
    if (unlikely(Rc(ctx->opcode) != 0))
4904
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4905 4906
}

4907
/* sraiq - sraiq. */
4908 4909
GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
{
4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925
    int sh = SH(ctx->opcode);
    int l1 = gen_new_label();
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
    tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
    tcg_gen_or_tl(t0, t0, t1);
    gen_store_spr(SPR_MQ, t0);
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
    gen_set_label(l1);
    tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
4926
    if (unlikely(Rc(ctx->opcode) != 0))
4927
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4928 4929 4930 4931 4932
}

/* sraq - sraq. */
GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
{
4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958
    int l1 = gen_new_label();
    int l2 = gen_new_label();
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_local_new();
    TCGv t2 = tcg_temp_local_new();
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
    tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
    tcg_gen_subfi_tl(t2, 32, t2);
    tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
    tcg_gen_or_tl(t0, t0, t2);
    gen_store_spr(SPR_MQ, t0);
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
    tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
    tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
    gen_set_label(l1);
    tcg_temp_free(t0);
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
    tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
    tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
    gen_set_label(l2);
    tcg_temp_free(t1);
    tcg_temp_free(t2);
4959
    if (unlikely(Rc(ctx->opcode) != 0))
4960
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4961 4962 4963 4964 4965
}

/* sre - sre. */
GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
{
4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
    tcg_gen_subfi_tl(t1, 32, t1);
    tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
    tcg_gen_or_tl(t1, t0, t1);
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
    gen_store_spr(SPR_MQ, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
4977
    if (unlikely(Rc(ctx->opcode) != 0))
4978
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4979 4980 4981 4982 4983
}

/* srea - srea. */
GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
{
4984 4985 4986 4987 4988 4989 4990 4991
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
    gen_store_spr(SPR_MQ, t0);
    tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
4992
    if (unlikely(Rc(ctx->opcode) != 0))
4993
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4994 4995 4996 4997 4998
}

/* sreq */
GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
{
4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    TCGv t2 = tcg_temp_new();
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_movi_tl(t1, 0xFFFFFFFF);
    tcg_gen_shr_tl(t1, t1, t0);
    tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
    gen_load_spr(t2, SPR_MQ);
    gen_store_spr(SPR_MQ, t0);
    tcg_gen_and_tl(t0, t0, t1);
    tcg_gen_andc_tl(t2, t2, t1);
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
    tcg_temp_free(t2);
5014
    if (unlikely(Rc(ctx->opcode) != 0))
5015
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5016 5017 5018 5019 5020
}

/* sriq */
GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
{
5021 5022 5023 5024 5025 5026 5027 5028 5029 5030
    int sh = SH(ctx->opcode);
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
    tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
    tcg_gen_or_tl(t1, t0, t1);
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
    gen_store_spr(SPR_MQ, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
5031
    if (unlikely(Rc(ctx->opcode) != 0))
5032
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5033 5034 5035 5036 5037
}

/* srliq */
GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
{
5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048
    int sh = SH(ctx->opcode);
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
    gen_load_spr(t1, SPR_MQ);
    gen_store_spr(SPR_MQ, t0);
    tcg_gen_andi_tl(t0, t0,  (0xFFFFFFFFU >> sh));
    tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
5049
    if (unlikely(Rc(ctx->opcode) != 0))
5050
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5051 5052 5053 5054 5055
}

/* srlq */
GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
{
5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078
    int l1 = gen_new_label();
    int l2 = gen_new_label();
    TCGv t0 = tcg_temp_local_new();
    TCGv t1 = tcg_temp_local_new();
    TCGv t2 = tcg_temp_local_new();
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_movi_tl(t1, 0xFFFFFFFF);
    tcg_gen_shr_tl(t2, t1, t2);
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
    gen_load_spr(t0, SPR_MQ);
    tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
    tcg_gen_and_tl(t0, t0, t2);
    gen_load_spr(t1, SPR_MQ);
    tcg_gen_andc_tl(t1, t1, t2);
    tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
    gen_set_label(l2);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
    tcg_temp_free(t2);
5079
    if (unlikely(Rc(ctx->opcode) != 0))
5080
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5081 5082 5083 5084 5085
}

/* srq */
GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
{
5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101
    int l1 = gen_new_label();
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
    tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
    tcg_gen_subfi_tl(t1, 32, t1);
    tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
    tcg_gen_or_tl(t1, t0, t1);
    gen_store_spr(SPR_MQ, t1);
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
    tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
    gen_set_label(l1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
5102
    if (unlikely(Rc(ctx->opcode) != 0))
5103
        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5104 5105 5106 5107 5108 5109 5110
}

/* PowerPC 602 specific instructions */
/* dsa  */
GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
{
    /* XXX: TODO */
A
aurel32 已提交
5111
    gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5112 5113 5114 5115 5116 5117
}

/* esa */
GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
{
    /* XXX: TODO */
A
aurel32 已提交
5118
    gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5119 5120 5121 5122 5123 5124
}

/* mfrom */
GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5125
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5126
#else
A
aurel32 已提交
5127
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5128
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5129 5130
        return;
    }
5131
    gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5132 5133 5134 5135 5136
#endif
}

/* 602 - 603 - G2 TLB management */
/* tlbld */
5137
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5138 5139
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5140
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5141
#else
A
aurel32 已提交
5142
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5143
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5144 5145
        return;
    }
5146
    gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5147 5148 5149 5150
#endif
}

/* tlbli */
5151
GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5152 5153
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5154
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5155
#else
A
aurel32 已提交
5156
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5157
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5158 5159
        return;
    }
5160
    gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5161 5162 5163
#endif
}

5164 5165
/* 74xx TLB management */
/* tlbld */
5166
GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5167 5168
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5169
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5170
#else
A
aurel32 已提交
5171
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5172
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5173 5174
        return;
    }
5175
    gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5176 5177 5178 5179
#endif
}

/* tlbli */
5180
GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5181 5182
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5183
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5184
#else
A
aurel32 已提交
5185
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5186
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5187 5188
        return;
    }
5189
    gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5190 5191 5192
#endif
}

5193 5194 5195 5196 5197 5198 5199 5200 5201 5202
/* POWER instructions not in PowerPC 601 */
/* clf */
GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
{
    /* Cache line flush: implemented as no-op */
}

/* cli */
GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
{
B
blueswir1 已提交
5203
    /* Cache line invalidate: privileged and treated as no-op */
5204
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5205
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5206
#else
A
aurel32 已提交
5207
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5208
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222
        return;
    }
#endif
}

/* dclst */
GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
{
    /* Data cache line store: treated as no-op */
}

GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5223
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5224
#else
5225 5226 5227
    int ra = rA(ctx->opcode);
    int rd = rD(ctx->opcode);
    TCGv t0;
A
aurel32 已提交
5228
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5229
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5230 5231
        return;
    }
5232
    t0 = tcg_temp_new();
A
aurel32 已提交
5233
    gen_addr_reg_index(ctx, t0);
5234 5235 5236 5237
    tcg_gen_shri_tl(t0, t0, 28);
    tcg_gen_andi_tl(t0, t0, 0xF);
    gen_helper_load_sr(cpu_gpr[rd], t0);
    tcg_temp_free(t0);
5238
    if (ra != 0 && ra != rd)
5239
        tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5240 5241 5242 5243 5244 5245
#endif
}

GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5246
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5247
#else
5248
    TCGv t0;
A
aurel32 已提交
5249
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5250
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5251 5252
        return;
    }
5253
    t0 = tcg_temp_new();
A
aurel32 已提交
5254
    gen_addr_reg_index(ctx, t0);
5255 5256
    gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free(t0);
5257 5258 5259 5260 5261 5262
#endif
}

GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5263
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5264
#else
A
aurel32 已提交
5265
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5266
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5267 5268
        return;
    }
5269
    gen_helper_rfsvc();
A
aurel32 已提交
5270
    gen_sync_exception(ctx);
5271 5272 5273 5274 5275 5276 5277 5278 5279 5280 5281
#endif
}

/* svc is not implemented for now */

/* POWER2 specific instructions */
/* Quad manipulation (load/store two floats at a time) */

/* lfq */
GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
{
5282
    int rd = rD(ctx->opcode);
A
aurel32 已提交
5283 5284 5285 5286 5287 5288 5289
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_FLOAT);
    t0 = tcg_temp_new();
    gen_addr_imm_index(ctx, t0, 0);
    gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
    gen_addr_add(ctx, t0, t0, 8);
    gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5290
    tcg_temp_free(t0);
5291 5292 5293 5294 5295 5296
}

/* lfqu */
GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
{
    int ra = rA(ctx->opcode);
5297
    int rd = rD(ctx->opcode);
A
aurel32 已提交
5298 5299 5300 5301 5302 5303 5304 5305
    TCGv t0, t1;
    gen_set_access_type(ctx, ACCESS_FLOAT);
    t0 = tcg_temp_new();
    t1 = tcg_temp_new();
    gen_addr_imm_index(ctx, t0, 0);
    gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
    gen_addr_add(ctx, t1, t0, 8);
    gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5306
    if (ra != 0)
5307 5308 5309
        tcg_gen_mov_tl(cpu_gpr[ra], t0);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
5310 5311 5312 5313 5314 5315
}

/* lfqux */
GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
{
    int ra = rA(ctx->opcode);
5316
    int rd = rD(ctx->opcode);
A
aurel32 已提交
5317 5318 5319 5320 5321 5322 5323 5324 5325
    gen_set_access_type(ctx, ACCESS_FLOAT);
    TCGv t0, t1;
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
    gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
    t1 = tcg_temp_new();
    gen_addr_add(ctx, t1, t0, 8);
    gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
    tcg_temp_free(t1);
5326
    if (ra != 0)
5327 5328
        tcg_gen_mov_tl(cpu_gpr[ra], t0);
    tcg_temp_free(t0);
5329 5330 5331 5332 5333
}

/* lfqx */
GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
{
5334
    int rd = rD(ctx->opcode);
A
aurel32 已提交
5335 5336 5337 5338 5339 5340 5341
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_FLOAT);
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
    gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
    gen_addr_add(ctx, t0, t0, 8);
    gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5342
    tcg_temp_free(t0);
5343 5344 5345 5346 5347
}

/* stfq */
GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
{
5348
    int rd = rD(ctx->opcode);
A
aurel32 已提交
5349 5350 5351 5352 5353 5354 5355
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_FLOAT);
    t0 = tcg_temp_new();
    gen_addr_imm_index(ctx, t0, 0);
    gen_qemu_st64(ctx, cpu_fpr[rd], t0);
    gen_addr_add(ctx, t0, t0, 8);
    gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5356
    tcg_temp_free(t0);
5357 5358 5359 5360 5361 5362
}

/* stfqu */
GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
{
    int ra = rA(ctx->opcode);
5363
    int rd = rD(ctx->opcode);
A
aurel32 已提交
5364 5365 5366 5367 5368 5369 5370 5371 5372
    TCGv t0, t1;
    gen_set_access_type(ctx, ACCESS_FLOAT);
    t0 = tcg_temp_new();
    gen_addr_imm_index(ctx, t0, 0);
    gen_qemu_st64(ctx, cpu_fpr[rd], t0);
    t1 = tcg_temp_new();
    gen_addr_add(ctx, t1, t0, 8);
    gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
    tcg_temp_free(t1);
5373
    if (ra != 0)
5374 5375
        tcg_gen_mov_tl(cpu_gpr[ra], t0);
    tcg_temp_free(t0);
5376 5377 5378 5379 5380 5381
}

/* stfqux */
GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
{
    int ra = rA(ctx->opcode);
5382
    int rd = rD(ctx->opcode);
A
aurel32 已提交
5383 5384 5385 5386 5387 5388 5389 5390 5391
    TCGv t0, t1;
    gen_set_access_type(ctx, ACCESS_FLOAT);
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
    gen_qemu_st64(ctx, cpu_fpr[rd], t0);
    t1 = tcg_temp_new();
    gen_addr_add(ctx, t1, t0, 8);
    gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
    tcg_temp_free(t1);
5392
    if (ra != 0)
5393 5394
        tcg_gen_mov_tl(cpu_gpr[ra], t0);
    tcg_temp_free(t0);
5395 5396 5397 5398 5399
}

/* stfqx */
GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
{
5400
    int rd = rD(ctx->opcode);
A
aurel32 已提交
5401 5402 5403 5404 5405 5406 5407
    TCGv t0;
    gen_set_access_type(ctx, ACCESS_FLOAT);
    t0 = tcg_temp_new();
    gen_addr_reg_index(ctx, t0);
    gen_qemu_st64(ctx, cpu_fpr[rd], t0);
    gen_addr_add(ctx, t0, t0, 8);
    gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5408
    tcg_temp_free(t0);
5409 5410 5411
}

/* BookE specific instructions */
5412
/* XXX: not implemented on 440 ? */
5413
GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5414 5415
{
    /* XXX: TODO */
A
aurel32 已提交
5416
    gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5417 5418
}

5419
/* XXX: not implemented on 440 ? */
5420
GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5421 5422
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5423
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5424
#else
5425
    TCGv t0;
A
aurel32 已提交
5426
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5427
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5428 5429
        return;
    }
5430
    t0 = tcg_temp_new();
A
aurel32 已提交
5431
    gen_addr_reg_index(ctx, t0);
5432 5433
    gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
    tcg_temp_free(t0);
5434 5435 5436 5437
#endif
}

/* All 405 MAC instructions are translated here */
5438 5439 5440
static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
                                                int opc2, int opc3,
                                                int ra, int rb, int rt, int Rc)
5441
{
5442 5443
    TCGv t0, t1;

P
pbrook 已提交
5444 5445
    t0 = tcg_temp_local_new();
    t1 = tcg_temp_local_new();
5446

5447 5448 5449 5450 5451 5452 5453
    switch (opc3 & 0x0D) {
    case 0x05:
        /* macchw    - macchw.    - macchwo   - macchwo.   */
        /* macchws   - macchws.   - macchwso  - macchwso.  */
        /* nmacchw   - nmacchw.   - nmacchwo  - nmacchwo.  */
        /* nmacchws  - nmacchws.  - nmacchwso - nmacchwso. */
        /* mulchw - mulchw. */
5454 5455 5456
        tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
        tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
        tcg_gen_ext16s_tl(t1, t1);
5457 5458 5459 5460 5461
        break;
    case 0x04:
        /* macchwu   - macchwu.   - macchwuo  - macchwuo.  */
        /* macchwsu  - macchwsu.  - macchwsuo - macchwsuo. */
        /* mulchwu - mulchwu. */
5462 5463 5464
        tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
        tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
        tcg_gen_ext16u_tl(t1, t1);
5465 5466 5467 5468 5469 5470 5471
        break;
    case 0x01:
        /* machhw    - machhw.    - machhwo   - machhwo.   */
        /* machhws   - machhws.   - machhwso  - machhwso.  */
        /* nmachhw   - nmachhw.   - nmachhwo  - nmachhwo.  */
        /* nmachhws  - nmachhws.  - nmachhwso - nmachhwso. */
        /* mulhhw - mulhhw. */
5472 5473 5474 5475
        tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
        tcg_gen_ext16s_tl(t0, t0);
        tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
        tcg_gen_ext16s_tl(t1, t1);
5476 5477 5478 5479 5480
        break;
    case 0x00:
        /* machhwu   - machhwu.   - machhwuo  - machhwuo.  */
        /* machhwsu  - machhwsu.  - machhwsuo - machhwsuo. */
        /* mulhhwu - mulhhwu. */
5481 5482 5483 5484
        tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
        tcg_gen_ext16u_tl(t0, t0);
        tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
        tcg_gen_ext16u_tl(t1, t1);
5485 5486 5487 5488 5489 5490 5491
        break;
    case 0x0D:
        /* maclhw    - maclhw.    - maclhwo   - maclhwo.   */
        /* maclhws   - maclhws.   - maclhwso  - maclhwso.  */
        /* nmaclhw   - nmaclhw.   - nmaclhwo  - nmaclhwo.  */
        /* nmaclhws  - nmaclhws.  - nmaclhwso - nmaclhwso. */
        /* mullhw - mullhw. */
5492 5493
        tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
        tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5494 5495 5496 5497 5498
        break;
    case 0x0C:
        /* maclhwu   - maclhwu.   - maclhwuo  - maclhwuo.  */
        /* maclhwsu  - maclhwsu.  - maclhwsuo - maclhwsuo. */
        /* mullhwu - mullhwu. */
5499 5500
        tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
        tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5501 5502 5503
        break;
    }
    if (opc2 & 0x04) {
5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520 5521 5522 5523 5524 5525 5526 5527
        /* (n)multiply-and-accumulate (0x0C / 0x0E) */
        tcg_gen_mul_tl(t1, t0, t1);
        if (opc2 & 0x02) {
            /* nmultiply-and-accumulate (0x0E) */
            tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
        } else {
            /* multiply-and-accumulate (0x0C) */
            tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
        }

        if (opc3 & 0x12) {
            /* Check overflow and/or saturate */
            int l1 = gen_new_label();

            if (opc3 & 0x10) {
                /* Start with XER OV disabled, the most likely case */
                tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
            }
            if (opc3 & 0x01) {
                /* Signed */
                tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
                tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
                tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
                tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
A
aurel32 已提交
5528
                if (opc3 & 0x02) {
5529 5530 5531 5532 5533 5534 5535
                    /* Saturate */
                    tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
                    tcg_gen_xori_tl(t0, t0, 0x7fffffff);
                }
            } else {
                /* Unsigned */
                tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
A
aurel32 已提交
5536
                if (opc3 & 0x02) {
5537 5538 5539 5540 5541 5542 5543 5544 5545 5546 5547 5548 5549
                    /* Saturate */
                    tcg_gen_movi_tl(t0, UINT32_MAX);
                }
            }
            if (opc3 & 0x10) {
                /* Check overflow */
                tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
            }
            gen_set_label(l1);
            tcg_gen_mov_tl(cpu_gpr[rt], t0);
        }
    } else {
        tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5550
    }
5551 5552
    tcg_temp_free(t0);
    tcg_temp_free(t1);
5553 5554
    if (unlikely(Rc) != 0) {
        /* Update Rc0 */
5555
        gen_set_Rc0(ctx, cpu_gpr[rt]);
5556 5557 5558
    }
}

5559 5560
#define GEN_MAC_HANDLER(name, opc2, opc3)                                     \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)                  \
5561 5562 5563 5564 5565 5566
{                                                                             \
    gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode),   \
                         rD(ctx->opcode), Rc(ctx->opcode));                   \
}

/* macchw    - macchw.    */
5567
GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5568
/* macchwo   - macchwo.   */
5569
GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5570
/* macchws   - macchws.   */
5571
GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5572
/* macchwso  - macchwso.  */
5573
GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5574
/* macchwsu  - macchwsu.  */
5575
GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5576
/* macchwsuo - macchwsuo. */
5577
GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5578
/* macchwu   - macchwu.   */
5579
GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5580
/* macchwuo  - macchwuo.  */
5581
GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5582
/* machhw    - machhw.    */
5583
GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5584
/* machhwo   - machhwo.   */
5585
GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5586
/* machhws   - machhws.   */
5587
GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5588
/* machhwso  - machhwso.  */
5589
GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5590
/* machhwsu  - machhwsu.  */
5591
GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5592
/* machhwsuo - machhwsuo. */
5593
GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5594
/* machhwu   - machhwu.   */
5595
GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5596
/* machhwuo  - machhwuo.  */
5597
GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5598
/* maclhw    - maclhw.    */
5599
GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5600
/* maclhwo   - maclhwo.   */
5601
GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5602
/* maclhws   - maclhws.   */
5603
GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5604
/* maclhwso  - maclhwso.  */
5605
GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5606
/* maclhwu   - maclhwu.   */
5607
GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5608
/* maclhwuo  - maclhwuo.  */
5609
GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5610
/* maclhwsu  - maclhwsu.  */
5611
GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5612
/* maclhwsuo - maclhwsuo. */
5613
GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5614
/* nmacchw   - nmacchw.   */
5615
GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5616
/* nmacchwo  - nmacchwo.  */
5617
GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5618
/* nmacchws  - nmacchws.  */
5619
GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5620
/* nmacchwso - nmacchwso. */
5621
GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5622
/* nmachhw   - nmachhw.   */
5623
GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5624
/* nmachhwo  - nmachhwo.  */
5625
GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5626
/* nmachhws  - nmachhws.  */
5627
GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5628
/* nmachhwso - nmachhwso. */
5629
GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5630
/* nmaclhw   - nmaclhw.   */
5631
GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5632
/* nmaclhwo  - nmaclhwo.  */
5633
GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5634
/* nmaclhws  - nmaclhws.  */
5635
GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5636
/* nmaclhwso - nmaclhwso. */
5637
GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5638 5639

/* mulchw  - mulchw.  */
5640
GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5641
/* mulchwu - mulchwu. */
5642
GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5643
/* mulhhw  - mulhhw.  */
5644
GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5645
/* mulhhwu - mulhhwu. */
5646
GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5647
/* mullhw  - mullhw.  */
5648
GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5649
/* mullhwu - mullhwu. */
5650
GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5651 5652

/* mfdcr */
5653
GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5654 5655
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5656
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5657
#else
5658
    TCGv dcrn;
A
aurel32 已提交
5659
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5660
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5661 5662
        return;
    }
5663 5664 5665 5666 5667
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
    dcrn = tcg_const_tl(SPR(ctx->opcode));
    gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
    tcg_temp_free(dcrn);
5668 5669 5670 5671
#endif
}

/* mtdcr */
5672
GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5673 5674
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5675
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5676
#else
5677
    TCGv dcrn;
A
aurel32 已提交
5678
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5679
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5680 5681
        return;
    }
5682 5683 5684 5685 5686
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
    dcrn = tcg_const_tl(SPR(ctx->opcode));
    gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
    tcg_temp_free(dcrn);
5687 5688 5689 5690
#endif
}

/* mfdcrx */
5691
/* XXX: not implemented on 440 ? */
5692
GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5693 5694
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5695
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5696
#else
A
aurel32 已提交
5697
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5698
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5699 5700
        return;
    }
5701 5702 5703
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
    gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5704
    /* Note: Rc update flag set leads to undefined state of Rc0 */
5705 5706 5707 5708
#endif
}

/* mtdcrx */
5709
/* XXX: not implemented on 440 ? */
5710
GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5711 5712
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5713
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5714
#else
A
aurel32 已提交
5715
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5716
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5717 5718
        return;
    }
5719 5720 5721
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
    gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5722
    /* Note: Rc update flag set leads to undefined state of Rc0 */
5723 5724 5725
#endif
}

5726 5727 5728
/* mfdcrux (PPC 460) : user-mode access to DCR */
GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
{
5729 5730 5731
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
    gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5732 5733 5734 5735 5736 5737
    /* Note: Rc update flag set leads to undefined state of Rc0 */
}

/* mtdcrux (PPC 460) : user-mode access to DCR */
GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
{
5738 5739 5740
    /* NIP cannot be restored if the memory exception comes from an helper */
    gen_update_nip(ctx, ctx->nip - 4);
    gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5741 5742 5743
    /* Note: Rc update flag set leads to undefined state of Rc0 */
}

5744 5745 5746 5747
/* dccci */
GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5748
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5749
#else
A
aurel32 已提交
5750
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5751
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5752 5753 5754 5755 5756 5757 5758 5759 5760 5761
        return;
    }
    /* interpreted as no-op */
#endif
}

/* dcread */
GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5762
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5763
#else
A
aurel32 已提交
5764
    TCGv EA, val;
A
aurel32 已提交
5765
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5766
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5767 5768
        return;
    }
A
aurel32 已提交
5769
    gen_set_access_type(ctx, ACCESS_CACHE);
P
pbrook 已提交
5770
    EA = tcg_temp_new();
A
aurel32 已提交
5771
    gen_addr_reg_index(ctx, EA);
P
pbrook 已提交
5772
    val = tcg_temp_new();
A
aurel32 已提交
5773
    gen_qemu_ld32u(ctx, val, EA);
A
aurel32 已提交
5774 5775 5776
    tcg_temp_free(val);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
    tcg_temp_free(EA);
5777 5778 5779 5780
#endif
}

/* icbt */
5781
GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5782 5783 5784 5785 5786 5787 5788 5789 5790 5791 5792
{
    /* interpreted as no-op */
    /* XXX: specification say this is treated as a load by the MMU
     *      but does not generate any exception
     */
}

/* iccci */
GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5793
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5794
#else
A
aurel32 已提交
5795
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5796
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5797 5798 5799 5800 5801 5802 5803 5804 5805 5806
        return;
    }
    /* interpreted as no-op */
#endif
}

/* icread */
GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5807
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5808
#else
A
aurel32 已提交
5809
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5810
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5811 5812 5813 5814 5815 5816
        return;
    }
    /* interpreted as no-op */
#endif
}

A
aurel32 已提交
5817
/* rfci (mem_idx only) */
5818
GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5819 5820
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5821
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5822
#else
A
aurel32 已提交
5823
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5824
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5825 5826 5827
        return;
    }
    /* Restore CPU state */
5828
    gen_helper_40x_rfci();
A
aurel32 已提交
5829
    gen_sync_exception(ctx);
5830 5831 5832 5833 5834 5835
#endif
}

GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5836
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5837
#else
A
aurel32 已提交
5838
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5839
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5840 5841 5842
        return;
    }
    /* Restore CPU state */
5843
    gen_helper_rfci();
A
aurel32 已提交
5844
    gen_sync_exception(ctx);
5845 5846 5847 5848
#endif
}

/* BookE specific */
5849
/* XXX: not implemented on 440 ? */
5850
GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5851 5852
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5853
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5854
#else
A
aurel32 已提交
5855
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5856
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5857 5858 5859
        return;
    }
    /* Restore CPU state */
5860
    gen_helper_rfdi();
A
aurel32 已提交
5861
    gen_sync_exception(ctx);
5862 5863 5864
#endif
}

5865
/* XXX: not implemented on 440 ? */
5866
GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5867 5868
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5869
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5870
#else
A
aurel32 已提交
5871
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5872
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5873 5874 5875
        return;
    }
    /* Restore CPU state */
5876
    gen_helper_rfmci();
A
aurel32 已提交
5877
    gen_sync_exception(ctx);
5878 5879
#endif
}
5880

5881
/* TLB management - PowerPC 405 implementation */
5882
/* tlbre */
5883
GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5884 5885
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5886
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5887
#else
A
aurel32 已提交
5888
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5889
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5890 5891 5892 5893
        return;
    }
    switch (rB(ctx->opcode)) {
    case 0:
5894
        gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5895 5896
        break;
    case 1:
5897
        gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5898 5899
        break;
    default:
A
aurel32 已提交
5900
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5901
        break;
5902
    }
5903 5904 5905
#endif
}

5906
/* tlbsx - tlbsx. */
5907
GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5908 5909
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5910
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5911
#else
5912
    TCGv t0;
A
aurel32 已提交
5913
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5914
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5915 5916
        return;
    }
5917
    t0 = tcg_temp_new();
A
aurel32 已提交
5918
    gen_addr_reg_index(ctx, t0);
5919 5920 5921 5922 5923 5924 5925 5926 5927 5928 5929
    gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free(t0);
    if (Rc(ctx->opcode)) {
        int l1 = gen_new_label();
        tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
        tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
        tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
        tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
        gen_set_label(l1);
    }
5930
#endif
B
bellard 已提交
5931 5932
}

5933
/* tlbwe */
5934
GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
B
bellard 已提交
5935
{
5936
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5937
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5938
#else
A
aurel32 已提交
5939
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5940
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5941 5942 5943 5944
        return;
    }
    switch (rB(ctx->opcode)) {
    case 0:
5945
        gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5946 5947
        break;
    case 1:
5948
        gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5949 5950
        break;
    default:
A
aurel32 已提交
5951
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5952
        break;
5953
    }
5954 5955 5956
#endif
}

5957
/* TLB management - PowerPC 440 implementation */
5958
/* tlbre */
5959
GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5960 5961
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5962
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5963
#else
A
aurel32 已提交
5964
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5965
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5966 5967 5968 5969 5970 5971
        return;
    }
    switch (rB(ctx->opcode)) {
    case 0:
    case 1:
    case 2:
5972 5973 5974 5975 5976
        {
            TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
            gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
            tcg_temp_free_i32(t0);
        }
5977 5978
        break;
    default:
A
aurel32 已提交
5979
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5980 5981 5982 5983 5984 5985
        break;
    }
#endif
}

/* tlbsx - tlbsx. */
5986
GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5987 5988
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
5989
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5990
#else
5991
    TCGv t0;
A
aurel32 已提交
5992
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
5993
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5994 5995
        return;
    }
5996
    t0 = tcg_temp_new();
A
aurel32 已提交
5997
    gen_addr_reg_index(ctx, t0);
5998 5999 6000 6001 6002 6003 6004 6005 6006 6007 6008
    gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free(t0);
    if (Rc(ctx->opcode)) {
        int l1 = gen_new_label();
        tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
        tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
        tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
        tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
        gen_set_label(l1);
    }
6009 6010 6011 6012
#endif
}

/* tlbwe */
6013
GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
6014 6015
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
6016
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6017
#else
A
aurel32 已提交
6018
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
6019
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6020 6021 6022 6023 6024 6025
        return;
    }
    switch (rB(ctx->opcode)) {
    case 0:
    case 1:
    case 2:
6026 6027 6028 6029 6030
        {
            TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
            gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
            tcg_temp_free_i32(t0);
        }
6031 6032
        break;
    default:
A
aurel32 已提交
6033
        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6034 6035 6036 6037 6038
        break;
    }
#endif
}

6039
/* wrtee */
6040
GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6041 6042
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
6043
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6044
#else
6045
    TCGv t0;
A
aurel32 已提交
6046
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
6047
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6048 6049
        return;
    }
6050 6051 6052 6053 6054
    t0 = tcg_temp_new();
    tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
    tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
    tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
    tcg_temp_free(t0);
J
j_mayer 已提交
6055 6056 6057
    /* Stop translation to have a chance to raise an exception
     * if we just set msr_ee to 1
     */
A
aurel32 已提交
6058
    gen_stop_exception(ctx);
6059 6060 6061 6062
#endif
}

/* wrteei */
6063
GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6064 6065
{
#if defined(CONFIG_USER_ONLY)
A
aurel32 已提交
6066
    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6067
#else
A
aurel32 已提交
6068
    if (unlikely(!ctx->mem_idx)) {
A
aurel32 已提交
6069
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6070 6071
        return;
    }
6072 6073 6074
    if (ctx->opcode & 0x00010000) {
        tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
        /* Stop translation to have a chance to raise an exception */
A
aurel32 已提交
6075
        gen_stop_exception(ctx);
6076
    } else {
A
aurel32 已提交
6077
        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6078
    }
6079 6080 6081
#endif
}

J
j_mayer 已提交
6082
/* PowerPC 440 specific instructions */
6083 6084 6085
/* dlmzb */
GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
{
6086 6087 6088 6089
    TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
    gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
                     cpu_gpr[rB(ctx->opcode)], t0);
    tcg_temp_free_i32(t0);
6090 6091 6092
}

/* mbar replaces eieio on 440 */
A
aurel32 已提交
6093
GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
6094 6095 6096 6097 6098
{
    /* interpreted as no-op */
}

/* msync replaces sync on 440 */
6099
GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
6100 6101 6102 6103 6104
{
    /* interpreted as no-op */
}

/* icbt */
6105
GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
6106 6107 6108 6109 6110
{
    /* interpreted as no-op */
    /* XXX: specification say this is treated as a load by the MMU
     *      but does not generate any exception
     */
B
bellard 已提交
6111 6112
}

6113 6114 6115
/***                      Altivec vector extension                         ***/
/* Altivec registers moves */

A
aurel32 已提交
6116 6117
static always_inline TCGv_ptr gen_avr_ptr(int reg)
{
A
aurel32 已提交
6118
    TCGv_ptr r = tcg_temp_new_ptr();
A
aurel32 已提交
6119 6120 6121 6122
    tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
    return r;
}

6123
#define GEN_VR_LDX(name, opc2, opc3)                                          \
6124
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)                  \
6125
{                                                                             \
6126
    TCGv EA;                                                                  \
6127
    if (unlikely(!ctx->altivec_enabled)) {                                    \
A
aurel32 已提交
6128
        gen_exception(ctx, POWERPC_EXCP_VPU);                                 \
6129 6130
        return;                                                               \
    }                                                                         \
A
aurel32 已提交
6131
    gen_set_access_type(ctx, ACCESS_INT);                                     \
6132
    EA = tcg_temp_new();                                                      \
A
aurel32 已提交
6133
    gen_addr_reg_index(ctx, EA);                                              \
6134
    tcg_gen_andi_tl(EA, EA, ~0xf);                                            \
A
aurel32 已提交
6135 6136
    if (ctx->le_mode) {                                                       \
        gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA);                    \
6137
        tcg_gen_addi_tl(EA, EA, 8);                                           \
A
aurel32 已提交
6138
        gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA);                    \
6139
    } else {                                                                  \
A
aurel32 已提交
6140
        gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA);                    \
6141
        tcg_gen_addi_tl(EA, EA, 8);                                           \
A
aurel32 已提交
6142
        gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA);                    \
6143 6144
    }                                                                         \
    tcg_temp_free(EA);                                                        \
6145 6146 6147 6148 6149
}

#define GEN_VR_STX(name, opc2, opc3)                                          \
GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)              \
{                                                                             \
6150
    TCGv EA;                                                                  \
6151
    if (unlikely(!ctx->altivec_enabled)) {                                    \
A
aurel32 已提交
6152
        gen_exception(ctx, POWERPC_EXCP_VPU);                                 \
6153 6154
        return;                                                               \
    }                                                                         \
A
aurel32 已提交
6155
    gen_set_access_type(ctx, ACCESS_INT);                                     \
6156
    EA = tcg_temp_new();                                                      \
A
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    gen_addr_reg_index(ctx, EA);                                              \
6158
    tcg_gen_andi_tl(EA, EA, ~0xf);                                            \
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6159 6160
    if (ctx->le_mode) {                                                       \
        gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA);                    \
6161
        tcg_gen_addi_tl(EA, EA, 8);                                           \
A
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6162
        gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA);                    \
6163
    } else {                                                                  \
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        gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA);                    \
6165
        tcg_gen_addi_tl(EA, EA, 8);                                           \
A
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        gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA);                    \
6167 6168
    }                                                                         \
    tcg_temp_free(EA);                                                        \
6169 6170
}

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6171 6172 6173 6174 6175 6176 6177 6178 6179 6180 6181 6182 6183 6184 6185 6186 6187 6188 6189 6190 6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206
#define GEN_VR_LVE(name, opc2, opc3)                                    \
    GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)   \
    {                                                                   \
        TCGv EA;                                                        \
        TCGv_ptr rs;                                                    \
        if (unlikely(!ctx->altivec_enabled)) {                          \
            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
            return;                                                     \
        }                                                               \
        gen_set_access_type(ctx, ACCESS_INT);                           \
        EA = tcg_temp_new();                                            \
        gen_addr_reg_index(ctx, EA);                                    \
        rs = gen_avr_ptr(rS(ctx->opcode));                              \
        gen_helper_lve##name (rs, EA);                                  \
        tcg_temp_free(EA);                                              \
        tcg_temp_free_ptr(rs);                                          \
    }

#define GEN_VR_STVE(name, opc2, opc3)                                   \
    GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)  \
    {                                                                   \
        TCGv EA;                                                        \
        TCGv_ptr rs;                                                    \
        if (unlikely(!ctx->altivec_enabled)) {                          \
            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
            return;                                                     \
        }                                                               \
        gen_set_access_type(ctx, ACCESS_INT);                           \
        EA = tcg_temp_new();                                            \
        gen_addr_reg_index(ctx, EA);                                    \
        rs = gen_avr_ptr(rS(ctx->opcode));                              \
        gen_helper_stve##name (rs, EA);                                 \
        tcg_temp_free(EA);                                              \
        tcg_temp_free_ptr(rs);                                          \
    }

6207
GEN_VR_LDX(lvx, 0x07, 0x03);
6208
/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6209
GEN_VR_LDX(lvxl, 0x07, 0x0B);
6210

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GEN_VR_LVE(bx, 0x07, 0x00);
GEN_VR_LVE(hx, 0x07, 0x01);
GEN_VR_LVE(wx, 0x07, 0x02);

6215
GEN_VR_STX(svx, 0x07, 0x07);
6216
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6217
GEN_VR_STX(svxl, 0x07, 0x0F);
6218

A
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6219 6220 6221 6222
GEN_VR_STVE(bx, 0x07, 0x04);
GEN_VR_STVE(hx, 0x07, 0x05);
GEN_VR_STVE(wx, 0x07, 0x06);

A
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6223 6224 6225 6226 6227 6228 6229 6230 6231 6232 6233 6234 6235 6236 6237 6238 6239 6240 6241 6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252 6253 6254
GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
{
    TCGv_ptr rd;
    TCGv EA;
    if (unlikely(!ctx->altivec_enabled)) {
        gen_exception(ctx, POWERPC_EXCP_VPU);
        return;
    }
    EA = tcg_temp_new();
    gen_addr_reg_index(ctx, EA);
    rd = gen_avr_ptr(rD(ctx->opcode));
    gen_helper_lvsl(rd, EA);
    tcg_temp_free(EA);
    tcg_temp_free_ptr(rd);
}

GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
{
    TCGv_ptr rd;
    TCGv EA;
    if (unlikely(!ctx->altivec_enabled)) {
        gen_exception(ctx, POWERPC_EXCP_VPU);
        return;
    }
    EA = tcg_temp_new();
    gen_addr_reg_index(ctx, EA);
    rd = gen_avr_ptr(rD(ctx->opcode));
    gen_helper_lvsr(rd, EA);
    tcg_temp_free(EA);
    tcg_temp_free_ptr(rd);
}

6255 6256 6257 6258 6259 6260 6261 6262 6263 6264 6265 6266 6267 6268 6269 6270 6271 6272 6273 6274 6275 6276 6277 6278 6279 6280 6281
GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
{
    TCGv_i32 t;
    if (unlikely(!ctx->altivec_enabled)) {
        gen_exception(ctx, POWERPC_EXCP_VPU);
        return;
    }
    tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
    t = tcg_temp_new_i32();
    tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
    tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
    tcg_temp_free(t);
}

GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
{
    TCGv_i32 t;
    if (unlikely(!ctx->altivec_enabled)) {
        gen_exception(ctx, POWERPC_EXCP_VPU);
        return;
    }
    t = tcg_temp_new_i32();
    tcg_gen_trunc_i64_i32(t, cpu_avrl[rD(ctx->opcode)]);
    tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr));
    tcg_temp_free_i32(t);
}

6282 6283 6284 6285 6286 6287 6288 6289 6290 6291 6292 6293 6294 6295 6296 6297 6298 6299
/* Logical operations */
#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3)                        \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)            \
{                                                                       \
    if (unlikely(!ctx->altivec_enabled)) {                              \
        gen_exception(ctx, POWERPC_EXCP_VPU);                           \
        return;                                                         \
    }                                                                   \
    tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
    tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
}

GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);

6300 6301 6302 6303 6304 6305 6306 6307 6308 6309 6310 6311 6312 6313 6314 6315 6316
#define GEN_VXFORM(name, opc2, opc3)                                    \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)            \
{                                                                       \
    TCGv_ptr ra, rb, rd;                                                \
    if (unlikely(!ctx->altivec_enabled)) {                              \
        gen_exception(ctx, POWERPC_EXCP_VPU);                           \
        return;                                                         \
    }                                                                   \
    ra = gen_avr_ptr(rA(ctx->opcode));                                  \
    rb = gen_avr_ptr(rB(ctx->opcode));                                  \
    rd = gen_avr_ptr(rD(ctx->opcode));                                  \
    gen_helper_##name (rd, ra, rb);                                     \
    tcg_temp_free_ptr(ra);                                              \
    tcg_temp_free_ptr(rb);                                              \
    tcg_temp_free_ptr(rd);                                              \
}

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GEN_VXFORM(vaddubm, 0, 0);
GEN_VXFORM(vadduhm, 0, 1);
GEN_VXFORM(vadduwm, 0, 2);
GEN_VXFORM(vsububm, 0, 16);
GEN_VXFORM(vsubuhm, 0, 17);
GEN_VXFORM(vsubuwm, 0, 18);
6323 6324 6325 6326 6327 6328 6329 6330 6331 6332 6333 6334
GEN_VXFORM(vmaxub, 1, 0);
GEN_VXFORM(vmaxuh, 1, 1);
GEN_VXFORM(vmaxuw, 1, 2);
GEN_VXFORM(vmaxsb, 1, 4);
GEN_VXFORM(vmaxsh, 1, 5);
GEN_VXFORM(vmaxsw, 1, 6);
GEN_VXFORM(vminub, 1, 8);
GEN_VXFORM(vminuh, 1, 9);
GEN_VXFORM(vminuw, 1, 10);
GEN_VXFORM(vminsb, 1, 12);
GEN_VXFORM(vminsh, 1, 13);
GEN_VXFORM(vminsw, 1, 14);
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GEN_VXFORM(vavgub, 1, 16);
GEN_VXFORM(vavguh, 1, 17);
GEN_VXFORM(vavguw, 1, 18);
GEN_VXFORM(vavgsb, 1, 20);
GEN_VXFORM(vavgsh, 1, 21);
GEN_VXFORM(vavgsw, 1, 22);
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GEN_VXFORM(vmrghb, 6, 0);
GEN_VXFORM(vmrghh, 6, 1);
GEN_VXFORM(vmrghw, 6, 2);
GEN_VXFORM(vmrglb, 6, 4);
GEN_VXFORM(vmrglh, 6, 5);
GEN_VXFORM(vmrglw, 6, 6);
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6347 6348 6349 6350 6351 6352 6353 6354
GEN_VXFORM(vmuloub, 4, 0);
GEN_VXFORM(vmulouh, 4, 1);
GEN_VXFORM(vmulosb, 4, 4);
GEN_VXFORM(vmulosh, 4, 5);
GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmulesb, 4, 12);
GEN_VXFORM(vmulesh, 4, 13);
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GEN_VXFORM(vslb, 2, 4);
GEN_VXFORM(vslh, 2, 5);
GEN_VXFORM(vslw, 2, 6);
A
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6358 6359 6360 6361 6362 6363
GEN_VXFORM(vsrb, 2, 8);
GEN_VXFORM(vsrh, 2, 9);
GEN_VXFORM(vsrw, 2, 10);
GEN_VXFORM(vsrab, 2, 12);
GEN_VXFORM(vsrah, 2, 13);
GEN_VXFORM(vsraw, 2, 14);
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6364 6365
GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
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6366 6367
GEN_VXFORM(vaddcuw, 0, 6);
GEN_VXFORM(vsubcuw, 0, 22);
6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379
GEN_VXFORM(vaddubs, 0, 8);
GEN_VXFORM(vadduhs, 0, 9);
GEN_VXFORM(vadduws, 0, 10);
GEN_VXFORM(vaddsbs, 0, 12);
GEN_VXFORM(vaddshs, 0, 13);
GEN_VXFORM(vaddsws, 0, 14);
GEN_VXFORM(vsububs, 0, 24);
GEN_VXFORM(vsubuhs, 0, 25);
GEN_VXFORM(vsubuws, 0, 26);
GEN_VXFORM(vsubsbs, 0, 28);
GEN_VXFORM(vsubshs, 0, 29);
GEN_VXFORM(vsubsws, 0, 30);
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6380 6381 6382
GEN_VXFORM(vrlb, 2, 0);
GEN_VXFORM(vrlh, 2, 1);
GEN_VXFORM(vrlw, 2, 2);
A
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6383 6384
GEN_VXFORM(vsl, 2, 7);
GEN_VXFORM(vsr, 2, 11);
6385 6386 6387 6388 6389 6390 6391 6392
GEN_VXFORM(vpkuhum, 7, 0);
GEN_VXFORM(vpkuwum, 7, 1);
GEN_VXFORM(vpkuhus, 7, 2);
GEN_VXFORM(vpkuwus, 7, 3);
GEN_VXFORM(vpkshus, 7, 4);
GEN_VXFORM(vpkswus, 7, 5);
GEN_VXFORM(vpkshss, 7, 6);
GEN_VXFORM(vpkswss, 7, 7);
A
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6393
GEN_VXFORM(vpkpx, 7, 12);
6394 6395 6396 6397 6398
GEN_VXFORM(vsum4ubs, 4, 24);
GEN_VXFORM(vsum4sbs, 4, 28);
GEN_VXFORM(vsum4shs, 4, 25);
GEN_VXFORM(vsum2sws, 4, 26);
GEN_VXFORM(vsumsws, 4, 30);
A
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6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414 6415 6416 6417 6418 6419 6420
#define GEN_VXRFORM1(opname, name, str, opc2, opc3)                     \
    GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC)   \
    {                                                                   \
        TCGv_ptr ra, rb, rd;                                            \
        if (unlikely(!ctx->altivec_enabled)) {                          \
            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
            return;                                                     \
        }                                                               \
        ra = gen_avr_ptr(rA(ctx->opcode));                              \
        rb = gen_avr_ptr(rB(ctx->opcode));                              \
        rd = gen_avr_ptr(rD(ctx->opcode));                              \
        gen_helper_##opname (rd, ra, rb);                               \
        tcg_temp_free_ptr(ra);                                          \
        tcg_temp_free_ptr(rb);                                          \
        tcg_temp_free_ptr(rd);                                          \
    }

#define GEN_VXRFORM(name, opc2, opc3)                                \
    GEN_VXRFORM1(name, name, #name, opc2, opc3)                      \
    GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))

6421 6422 6423 6424 6425 6426 6427 6428 6429 6430
GEN_VXRFORM(vcmpequb, 3, 0)
GEN_VXRFORM(vcmpequh, 3, 1)
GEN_VXRFORM(vcmpequw, 3, 2)
GEN_VXRFORM(vcmpgtsb, 3, 12)
GEN_VXRFORM(vcmpgtsh, 3, 13)
GEN_VXRFORM(vcmpgtsw, 3, 14)
GEN_VXRFORM(vcmpgtub, 3, 8)
GEN_VXRFORM(vcmpgtuh, 3, 9)
GEN_VXRFORM(vcmpgtuw, 3, 10)

A
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6431 6432 6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443 6444 6445 6446 6447 6448 6449 6450
#define GEN_VXFORM_SIMM(name, opc2, opc3)                               \
    GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)        \
    {                                                                   \
        TCGv_ptr rd;                                                    \
        TCGv_i32 simm;                                                  \
        if (unlikely(!ctx->altivec_enabled)) {                          \
            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
            return;                                                     \
        }                                                               \
        simm = tcg_const_i32(SIMM5(ctx->opcode));                       \
        rd = gen_avr_ptr(rD(ctx->opcode));                              \
        gen_helper_##name (rd, simm);                                   \
        tcg_temp_free_i32(simm);                                        \
        tcg_temp_free_ptr(rd);                                          \
    }

GEN_VXFORM_SIMM(vspltisb, 6, 12);
GEN_VXFORM_SIMM(vspltish, 6, 13);
GEN_VXFORM_SIMM(vspltisw, 6, 14);

6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463 6464 6465
#define GEN_VXFORM_NOA(name, opc2, opc3)                                \
    GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)        \
    {                                                                   \
        TCGv_ptr rb, rd;                                                \
        if (unlikely(!ctx->altivec_enabled)) {                          \
            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
            return;                                                     \
        }                                                               \
        rb = gen_avr_ptr(rB(ctx->opcode));                              \
        rd = gen_avr_ptr(rD(ctx->opcode));                              \
        gen_helper_##name (rd, rb);                                     \
        tcg_temp_free_ptr(rb);                                          \
        tcg_temp_free_ptr(rd);                                         \
    }

A
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6466 6467 6468 6469
GEN_VXFORM_NOA(vupkhsb, 7, 8);
GEN_VXFORM_NOA(vupkhsh, 7, 9);
GEN_VXFORM_NOA(vupklsb, 7, 10);
GEN_VXFORM_NOA(vupklsh, 7, 11);
A
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6470 6471 6472
GEN_VXFORM_NOA(vupkhpx, 7, 13);
GEN_VXFORM_NOA(vupklpx, 7, 15);

6473 6474 6475 6476 6477 6478 6479 6480 6481 6482 6483 6484 6485 6486 6487 6488
#define GEN_VXFORM_SIMM(name, opc2, opc3)                               \
    GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)        \
    {                                                                   \
        TCGv_ptr rd;                                                    \
        TCGv_i32 simm;                                                  \
        if (unlikely(!ctx->altivec_enabled)) {                          \
            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
            return;                                                     \
        }                                                               \
        simm = tcg_const_i32(SIMM5(ctx->opcode));                       \
        rd = gen_avr_ptr(rD(ctx->opcode));                              \
        gen_helper_##name (rd, simm);                                   \
        tcg_temp_free_i32(simm);                                        \
        tcg_temp_free_ptr(rd);                                          \
    }

6489 6490 6491 6492 6493 6494 6495 6496 6497 6498 6499 6500 6501 6502 6503 6504 6505 6506
#define GEN_VXFORM_UIMM(name, opc2, opc3)                               \
    GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)        \
    {                                                                   \
        TCGv_ptr rb, rd;                                                \
        TCGv_i32 uimm;                                                  \
        if (unlikely(!ctx->altivec_enabled)) {                          \
            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
            return;                                                     \
        }                                                               \
        uimm = tcg_const_i32(UIMM5(ctx->opcode));                       \
        rb = gen_avr_ptr(rB(ctx->opcode));                              \
        rd = gen_avr_ptr(rD(ctx->opcode));                              \
        gen_helper_##name (rd, rb, uimm);                               \
        tcg_temp_free_i32(uimm);                                        \
        tcg_temp_free_ptr(rb);                                          \
        tcg_temp_free_ptr(rd);                                          \
    }

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GEN_VXFORM_UIMM(vspltb, 6, 8);
GEN_VXFORM_UIMM(vsplth, 6, 9);
GEN_VXFORM_UIMM(vspltw, 6, 10);

A
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6511 6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523 6524 6525 6526 6527 6528 6529
GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
{
    TCGv_ptr ra, rb, rd;
    TCGv sh;
    if (unlikely(!ctx->altivec_enabled)) {
        gen_exception(ctx, POWERPC_EXCP_VPU);
        return;
    }
    ra = gen_avr_ptr(rA(ctx->opcode));
    rb = gen_avr_ptr(rB(ctx->opcode));
    rd = gen_avr_ptr(rD(ctx->opcode));
    sh = tcg_const_i32(VSH(ctx->opcode));
    gen_helper_vsldoi (rd, ra, rb, sh);
    tcg_temp_free_ptr(ra);
    tcg_temp_free_ptr(rb);
    tcg_temp_free_ptr(rd);
    tcg_temp_free(sh);
}

6530 6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547 6548 6549 6550 6551 6552
#define GEN_VAFORM_PAIRED(name0, name1, opc2)                           \
    GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
    {                                                                   \
        TCGv_ptr ra, rb, rc, rd;                                        \
        if (unlikely(!ctx->altivec_enabled)) {                          \
            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
            return;                                                     \
        }                                                               \
        ra = gen_avr_ptr(rA(ctx->opcode));                              \
        rb = gen_avr_ptr(rB(ctx->opcode));                              \
        rc = gen_avr_ptr(rC(ctx->opcode));                              \
        rd = gen_avr_ptr(rD(ctx->opcode));                              \
        if (Rc(ctx->opcode)) {                                          \
            gen_helper_##name1 (rd, ra, rb, rc);                        \
        } else {                                                        \
            gen_helper_##name0 (rd, ra, rb, rc);                        \
        }                                                               \
        tcg_temp_free_ptr(ra);                                          \
        tcg_temp_free_ptr(rb);                                          \
        tcg_temp_free_ptr(rc);                                          \
        tcg_temp_free_ptr(rd);                                          \
    }

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6553 6554
GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)

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6555 6556 6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567 6568 6569 6570 6571 6572
GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
{
    TCGv_ptr ra, rb, rc, rd;
    if (unlikely(!ctx->altivec_enabled)) {
        gen_exception(ctx, POWERPC_EXCP_VPU);
        return;
    }
    ra = gen_avr_ptr(rA(ctx->opcode));
    rb = gen_avr_ptr(rB(ctx->opcode));
    rc = gen_avr_ptr(rC(ctx->opcode));
    rd = gen_avr_ptr(rD(ctx->opcode));
    gen_helper_vmladduhm(rd, ra, rb, rc);
    tcg_temp_free_ptr(ra);
    tcg_temp_free_ptr(rb);
    tcg_temp_free_ptr(rc);
    tcg_temp_free_ptr(rd);
}

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GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
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6574
GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
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6575
GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
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6576
GEN_VAFORM_PAIRED(vsel, vperm, 21)
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6577

6578 6579
/***                           SPE extension                               ***/
/* Register moves */
6580

P
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6581
static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
A
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6582 6583 6584
#if defined(TARGET_PPC64)
    tcg_gen_mov_i64(t, cpu_gpr[reg]);
#else
P
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6585
    tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6586
#endif
A
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6587
}
6588

P
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6589
static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
A
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6590 6591 6592
#if defined(TARGET_PPC64)
    tcg_gen_mov_i64(cpu_gpr[reg], t);
#else
P
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6593
    TCGv_i64 tmp = tcg_temp_new_i64();
A
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6594 6595 6596
    tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
    tcg_gen_shri_i64(tmp, t, 32);
    tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
P
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6597
    tcg_temp_free_i64(tmp);
6598
#endif
A
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6599
}
6600

6601 6602 6603 6604 6605 6606 6607 6608 6609 6610
#define GEN_SPE(name0, name1, opc2, opc3, inval, type)                        \
GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type)                   \
{                                                                             \
    if (Rc(ctx->opcode))                                                      \
        gen_##name1(ctx);                                                     \
    else                                                                      \
        gen_##name0(ctx);                                                     \
}

/* Handler for undefined SPE opcodes */
6611
static always_inline void gen_speundef (DisasContext *ctx)
6612
{
A
aurel32 已提交
6613
    gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6614 6615
}

6616 6617 6618
/* SPE logic */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_LOGIC2(name, tcg_op)                                        \
6619
static always_inline void gen_##name (DisasContext *ctx)                      \
6620 6621
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
6622
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6623 6624
        return;                                                               \
    }                                                                         \
6625 6626 6627 6628 6629 6630 6631 6632
    tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],                \
           cpu_gpr[rB(ctx->opcode)]);                                         \
}
#else
#define GEN_SPEOP_LOGIC2(name, tcg_op)                                        \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
6633
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6634 6635 6636 6637 6638 6639
        return;                                                               \
    }                                                                         \
    tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],                \
           cpu_gpr[rB(ctx->opcode)]);                                         \
    tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],              \
           cpu_gprh[rB(ctx->opcode)]);                                        \
6640
}
6641 6642 6643 6644 6645 6646 6647 6648 6649 6650
#endif

GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6651

6652 6653 6654
/* SPE logic immediate */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi)                               \
6655 6656 6657
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
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6658
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6659 6660
        return;                                                               \
    }                                                                         \
P
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6661 6662 6663
    TCGv_i32 t0 = tcg_temp_local_new_i32();                                   \
    TCGv_i32 t1 = tcg_temp_local_new_i32();                                   \
    TCGv_i64 t2 = tcg_temp_local_new_i64();                                   \
6664 6665 6666 6667
    tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]);                      \
    tcg_opi(t0, t0, rB(ctx->opcode));                                         \
    tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32);                       \
    tcg_gen_trunc_i64_i32(t1, t2);                                            \
P
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6668
    tcg_temp_free_i64(t2);                                                    \
6669 6670
    tcg_opi(t1, t1, rB(ctx->opcode));                                         \
    tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);                 \
P
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6671 6672
    tcg_temp_free_i32(t0);                                                    \
    tcg_temp_free_i32(t1);                                                    \
6673
}
6674 6675
#else
#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi)                               \
6676
static always_inline void gen_##name (DisasContext *ctx)                      \
6677 6678
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
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6679
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6680 6681
        return;                                                               \
    }                                                                         \
6682 6683 6684 6685
    tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],               \
            rB(ctx->opcode));                                                 \
    tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],             \
            rB(ctx->opcode));                                                 \
6686
}
6687 6688 6689 6690 6691
#endif
GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6692

6693 6694 6695
/* SPE arithmetic */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_ARITH1(name, tcg_op)                                        \
6696
static always_inline void gen_##name (DisasContext *ctx)                      \
6697 6698
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
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6699
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6700 6701
        return;                                                               \
    }                                                                         \
P
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6702 6703 6704
    TCGv_i32 t0 = tcg_temp_local_new_i32();                                   \
    TCGv_i32 t1 = tcg_temp_local_new_i32();                                   \
    TCGv_i64 t2 = tcg_temp_local_new_i64();                                   \
6705 6706 6707 6708
    tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]);                      \
    tcg_op(t0, t0);                                                           \
    tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32);                       \
    tcg_gen_trunc_i64_i32(t1, t2);                                            \
P
pbrook 已提交
6709
    tcg_temp_free_i64(t2);                                                    \
6710 6711
    tcg_op(t1, t1);                                                           \
    tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);                 \
P
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6712 6713
    tcg_temp_free_i32(t0);                                                    \
    tcg_temp_free_i32(t1);                                                    \
6714
}
6715
#else
P
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6716
#define GEN_SPEOP_ARITH1(name, tcg_op)                                        \
6717 6718 6719
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
6720
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6721 6722 6723 6724 6725 6726
        return;                                                               \
    }                                                                         \
    tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);               \
    tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);             \
}
#endif
6727

P
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6728
static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6729 6730 6731
{
    int l1 = gen_new_label();
    int l2 = gen_new_label();
6732

6733 6734 6735 6736
    tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
    tcg_gen_neg_i32(ret, arg1);
    tcg_gen_br(l2);
    gen_set_label(l1);
P
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6737
    tcg_gen_mov_i32(ret, arg1);
6738 6739 6740 6741 6742 6743
    gen_set_label(l2);
}
GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
P
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6744
static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6745
{
6746 6747 6748 6749
    tcg_gen_addi_i32(ret, arg1, 0x8000);
    tcg_gen_ext16u_i32(ret, ret);
}
GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
P
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6750 6751
GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6752

6753 6754 6755
#if defined(TARGET_PPC64)
#define GEN_SPEOP_ARITH2(name, tcg_op)                                        \
static always_inline void gen_##name (DisasContext *ctx)                      \
6756 6757
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
6758
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6759 6760
        return;                                                               \
    }                                                                         \
P
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6761 6762 6763
    TCGv_i32 t0 = tcg_temp_local_new_i32();                                   \
    TCGv_i32 t1 = tcg_temp_local_new_i32();                                   \
    TCGv_i32 t2 = tcg_temp_local_new_i32();                                   \
6764
    TCGv_i64 t3 = tcg_temp_local_new_i64();                                   \
6765 6766 6767 6768 6769 6770 6771
    tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]);                      \
    tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]);                      \
    tcg_op(t0, t0, t2);                                                       \
    tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32);                       \
    tcg_gen_trunc_i64_i32(t1, t3);                                            \
    tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32);                       \
    tcg_gen_trunc_i64_i32(t2, t3);                                            \
P
pbrook 已提交
6772
    tcg_temp_free_i64(t3);                                                    \
6773
    tcg_op(t1, t1, t2);                                                       \
P
pbrook 已提交
6774
    tcg_temp_free_i32(t2);                                                    \
6775
    tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);                 \
P
pbrook 已提交
6776 6777
    tcg_temp_free_i32(t0);                                                    \
    tcg_temp_free_i32(t1);                                                    \
6778
}
6779 6780 6781
#else
#define GEN_SPEOP_ARITH2(name, tcg_op)                                        \
static always_inline void gen_##name (DisasContext *ctx)                      \
6782 6783
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
6784
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6785 6786
        return;                                                               \
    }                                                                         \
6787 6788 6789 6790
    tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],                \
           cpu_gpr[rB(ctx->opcode)]);                                         \
    tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],              \
           cpu_gprh[rB(ctx->opcode)]);                                        \
6791
}
6792
#endif
6793

P
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6794
static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6795
{
P
pbrook 已提交
6796
    TCGv_i32 t0;
6797
    int l1, l2;
6798

6799 6800
    l1 = gen_new_label();
    l2 = gen_new_label();
P
pbrook 已提交
6801
    t0 = tcg_temp_local_new_i32();
6802 6803 6804 6805 6806 6807 6808 6809
    /* No error here: 6 bits are used */
    tcg_gen_andi_i32(t0, arg2, 0x3F);
    tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
    tcg_gen_shr_i32(ret, arg1, t0);
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_movi_i32(ret, 0);
    tcg_gen_br(l2);
P
pbrook 已提交
6810
    tcg_temp_free_i32(t0);
6811 6812
}
GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
P
pbrook 已提交
6813
static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6814
{
P
pbrook 已提交
6815
    TCGv_i32 t0;
6816 6817 6818 6819
    int l1, l2;

    l1 = gen_new_label();
    l2 = gen_new_label();
P
pbrook 已提交
6820
    t0 = tcg_temp_local_new_i32();
6821 6822 6823 6824 6825 6826 6827 6828
    /* No error here: 6 bits are used */
    tcg_gen_andi_i32(t0, arg2, 0x3F);
    tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
    tcg_gen_sar_i32(ret, arg1, t0);
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_movi_i32(ret, 0);
    tcg_gen_br(l2);
P
pbrook 已提交
6829
    tcg_temp_free_i32(t0);
6830 6831
}
GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
P
pbrook 已提交
6832
static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6833
{
P
pbrook 已提交
6834
    TCGv_i32 t0;
6835 6836 6837 6838
    int l1, l2;

    l1 = gen_new_label();
    l2 = gen_new_label();
P
pbrook 已提交
6839
    t0 = tcg_temp_local_new_i32();
6840 6841 6842 6843 6844 6845 6846 6847
    /* No error here: 6 bits are used */
    tcg_gen_andi_i32(t0, arg2, 0x3F);
    tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
    tcg_gen_shl_i32(ret, arg1, t0);
    tcg_gen_br(l2);
    gen_set_label(l1);
    tcg_gen_movi_i32(ret, 0);
    tcg_gen_br(l2);
P
pbrook 已提交
6848
    tcg_temp_free_i32(t0);
6849 6850
}
GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
P
pbrook 已提交
6851
static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6852
{
P
pbrook 已提交
6853
    TCGv_i32 t0 = tcg_temp_new_i32();
6854 6855
    tcg_gen_andi_i32(t0, arg2, 0x1F);
    tcg_gen_rotl_i32(ret, arg1, t0);
P
pbrook 已提交
6856
    tcg_temp_free_i32(t0);
6857 6858 6859 6860 6861
}
GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
static always_inline void gen_evmergehi (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
A
aurel32 已提交
6862
        gen_exception(ctx, POWERPC_EXCP_APU);
6863 6864 6865
        return;
    }
#if defined(TARGET_PPC64)
P
pbrook 已提交
6866 6867
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
6868 6869 6870 6871 6872 6873 6874 6875 6876 6877 6878
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
    tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
#else
    tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
    tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
#endif
}
GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
P
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6879
static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6880
{
6881 6882 6883
    tcg_gen_sub_i32(ret, arg2, arg1);
}
GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6884

6885 6886 6887 6888 6889 6890
/* SPE arithmetic immediate */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_ARITH_IMM2(name, tcg_op)                                    \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
6891
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6892 6893
        return;                                                               \
    }                                                                         \
P
pbrook 已提交
6894 6895 6896
    TCGv_i32 t0 = tcg_temp_local_new_i32();                                   \
    TCGv_i32 t1 = tcg_temp_local_new_i32();                                   \
    TCGv_i64 t2 = tcg_temp_local_new_i64();                                   \
6897 6898 6899 6900
    tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]);                      \
    tcg_op(t0, t0, rA(ctx->opcode));                                          \
    tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32);                       \
    tcg_gen_trunc_i64_i32(t1, t2);                                            \
A
aurel32 已提交
6901
    tcg_temp_free_i64(t2);                                                    \
6902 6903
    tcg_op(t1, t1, rA(ctx->opcode));                                          \
    tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);                 \
P
pbrook 已提交
6904 6905
    tcg_temp_free_i32(t0);                                                    \
    tcg_temp_free_i32(t1);                                                    \
6906 6907 6908 6909 6910 6911
}
#else
#define GEN_SPEOP_ARITH_IMM2(name, tcg_op)                                    \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
6912
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6913 6914 6915 6916 6917 6918 6919 6920 6921 6922 6923 6924 6925 6926 6927 6928 6929
        return;                                                               \
    }                                                                         \
    tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],                \
           rA(ctx->opcode));                                                  \
    tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)],              \
           rA(ctx->opcode));                                                  \
}
#endif
GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);

/* SPE comparison */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_COMP(name, tcg_cond)                                        \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
6930
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6931 6932 6933 6934 6935 6936
        return;                                                               \
    }                                                                         \
    int l1 = gen_new_label();                                                 \
    int l2 = gen_new_label();                                                 \
    int l3 = gen_new_label();                                                 \
    int l4 = gen_new_label();                                                 \
P
pbrook 已提交
6937 6938 6939
    TCGv_i32 t0 = tcg_temp_local_new_i32();                                   \
    TCGv_i32 t1 = tcg_temp_local_new_i32();                                   \
    TCGv_i64 t2 = tcg_temp_local_new_i64();                                   \
6940 6941 6942
    tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]);                      \
    tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]);                      \
    tcg_gen_brcond_i32(tcg_cond, t0, t1, l1);                                 \
P
pbrook 已提交
6943
    tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0);                          \
6944 6945 6946 6947 6948 6949 6950 6951 6952
    tcg_gen_br(l2);                                                           \
    gen_set_label(l1);                                                        \
    tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)],                              \
                     CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL);                  \
    gen_set_label(l2);                                                        \
    tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32);                       \
    tcg_gen_trunc_i64_i32(t0, t2);                                            \
    tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32);                       \
    tcg_gen_trunc_i64_i32(t1, t2);                                            \
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    tcg_temp_free_i64(t2);                                                    \
6954 6955 6956 6957 6958 6959 6960 6961
    tcg_gen_brcond_i32(tcg_cond, t0, t1, l3);                                 \
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],  \
                     ~(CRF_CH | CRF_CH_AND_CL));                              \
    tcg_gen_br(l4);                                                           \
    gen_set_label(l3);                                                        \
    tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],   \
                    CRF_CH | CRF_CH_OR_CL);                                   \
    gen_set_label(l4);                                                        \
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6962 6963
    tcg_temp_free_i32(t0);                                                    \
    tcg_temp_free_i32(t1);                                                    \
6964 6965 6966 6967 6968 6969
}
#else
#define GEN_SPEOP_COMP(name, tcg_cond)                                        \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
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6970
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
6971 6972 6973 6974 6975 6976 6977 6978 6979 6980 6981 6982 6983 6984 6985 6986 6987 6988 6989 6990 6991 6992 6993 6994 6995 6996 6997 6998 6999 7000 7001 7002 7003 7004 7005 7006
        return;                                                               \
    }                                                                         \
    int l1 = gen_new_label();                                                 \
    int l2 = gen_new_label();                                                 \
    int l3 = gen_new_label();                                                 \
    int l4 = gen_new_label();                                                 \
                                                                              \
    tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)],                    \
                       cpu_gpr[rB(ctx->opcode)], l1);                         \
    tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0);                           \
    tcg_gen_br(l2);                                                           \
    gen_set_label(l1);                                                        \
    tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)],                              \
                     CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL);                  \
    gen_set_label(l2);                                                        \
    tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)],                   \
                       cpu_gprh[rB(ctx->opcode)], l3);                        \
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],  \
                     ~(CRF_CH | CRF_CH_AND_CL));                              \
    tcg_gen_br(l4);                                                           \
    gen_set_label(l3);                                                        \
    tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],   \
                    CRF_CH | CRF_CH_OR_CL);                                   \
    gen_set_label(l4);                                                        \
}
#endif
GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);

/* SPE misc */
static always_inline void gen_brinc (DisasContext *ctx)
{
    /* Note: brinc is usable even if SPE is disabled */
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    gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7009
}
7010 7011 7012
static always_inline void gen_evmergelo (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
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7013
        gen_exception(ctx, POWERPC_EXCP_APU);
7014 7015 7016
        return;
    }
#if defined(TARGET_PPC64)
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    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
7019 7020 7021 7022 7023 7024 7025 7026 7027 7028 7029 7030 7031
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
    tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
#else
    tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
    tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
#endif
}
static always_inline void gen_evmergehilo (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
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        gen_exception(ctx, POWERPC_EXCP_APU);
7033 7034 7035
        return;
    }
#if defined(TARGET_PPC64)
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7036 7037
    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
7038 7039 7040 7041 7042 7043 7044 7045 7046 7047 7048 7049 7050
    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
    tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
#else
    tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
    tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
#endif
}
static always_inline void gen_evmergelohi (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
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7051
        gen_exception(ctx, POWERPC_EXCP_APU);
7052 7053 7054
        return;
    }
#if defined(TARGET_PPC64)
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    TCGv t0 = tcg_temp_new();
    TCGv t1 = tcg_temp_new();
7057 7058 7059 7060 7061 7062 7063 7064 7065 7066 7067 7068
    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
    tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
    tcg_temp_free(t0);
    tcg_temp_free(t1);
#else
    tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
    tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
#endif
}
static always_inline void gen_evsplati (DisasContext *ctx)
{
7069
    uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
7070

7071
#if defined(TARGET_PPC64)
7072
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7073 7074 7075 7076 7077
#else
    tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
    tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
#endif
}
7078
static always_inline void gen_evsplatfi (DisasContext *ctx)
7079
{
7080
    uint64_t imm = rA(ctx->opcode) << 11;
7081

7082
#if defined(TARGET_PPC64)
7083
    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7084 7085 7086 7087
#else
    tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
    tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
#endif
7088 7089
}

7090 7091 7092 7093 7094 7095
static always_inline void gen_evsel (DisasContext *ctx)
{
    int l1 = gen_new_label();
    int l2 = gen_new_label();
    int l3 = gen_new_label();
    int l4 = gen_new_label();
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7096
    TCGv_i32 t0 = tcg_temp_local_new_i32();
7097
#if defined(TARGET_PPC64)
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7098 7099
    TCGv t1 = tcg_temp_local_new();
    TCGv t2 = tcg_temp_local_new();
7100 7101 7102 7103 7104 7105 7106 7107 7108 7109 7110 7111 7112 7113 7114 7115 7116 7117 7118 7119 7120 7121 7122 7123 7124 7125 7126 7127 7128 7129 7130
#endif
    tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
    tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
#if defined(TARGET_PPC64)
    tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
#else
    tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
#endif
    tcg_gen_br(l2);
    gen_set_label(l1);
#if defined(TARGET_PPC64)
    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
#else
    tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
#endif
    gen_set_label(l2);
    tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
    tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
#if defined(TARGET_PPC64)
    tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
#else
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
#endif
    tcg_gen_br(l4);
    gen_set_label(l3);
#if defined(TARGET_PPC64)
    tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
#else
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
#endif
    gen_set_label(l4);
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    tcg_temp_free_i32(t0);
7132 7133 7134 7135 7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146 7147 7148 7149 7150 7151 7152 7153
#if defined(TARGET_PPC64)
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
    tcg_temp_free(t1);
    tcg_temp_free(t2);
#endif
}
GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
{
    gen_evsel(ctx);
}
GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
{
    gen_evsel(ctx);
}
GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
{
    gen_evsel(ctx);
}
GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
{
    gen_evsel(ctx);
}
7154 7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166 7167 7168 7169 7170 7171 7172 7173 7174 7175 7176 7177 7178 7179 7180

GEN_SPE(evaddw,         speundef,      0x00, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(evaddiw,        speundef,      0x01, 0x08, 0x00000000, PPC_SPE);
GEN_SPE(evsubfw,        speundef,      0x02, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(evsubifw,       speundef,      0x03, 0x08, 0x00000000, PPC_SPE);
GEN_SPE(evabs,          evneg,         0x04, 0x08, 0x0000F800, PPC_SPE); ////
GEN_SPE(evextsb,        evextsh,       0x05, 0x08, 0x0000F800, PPC_SPE); ////
GEN_SPE(evrndw,         evcntlzw,      0x06, 0x08, 0x0000F800, PPC_SPE); ////
GEN_SPE(evcntlsw,       brinc,         0x07, 0x08, 0x00000000, PPC_SPE); //
GEN_SPE(speundef,       evand,         0x08, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(evandc,         speundef,      0x09, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(evxor,          evor,          0x0B, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(evnor,          eveqv,         0x0C, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(speundef,       evorc,         0x0D, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(evnand,         speundef,      0x0F, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(evsrwu,         evsrws,        0x10, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(evsrwiu,        evsrwis,       0x11, 0x08, 0x00000000, PPC_SPE);
GEN_SPE(evslw,          speundef,      0x12, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(evslwi,         speundef,      0x13, 0x08, 0x00000000, PPC_SPE);
GEN_SPE(evrlw,          evsplati,      0x14, 0x08, 0x00000000, PPC_SPE); //
GEN_SPE(evrlwi,         evsplatfi,     0x15, 0x08, 0x00000000, PPC_SPE);
GEN_SPE(evmergehi,      evmergelo,     0x16, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(evmergehilo,    evmergelohi,   0x17, 0x08, 0x00000000, PPC_SPE); ////
GEN_SPE(evcmpgtu,       evcmpgts,      0x18, 0x08, 0x00600000, PPC_SPE); ////
GEN_SPE(evcmpltu,       evcmplts,      0x19, 0x08, 0x00600000, PPC_SPE); ////
GEN_SPE(evcmpeq,        speundef,      0x1A, 0x08, 0x00600000, PPC_SPE); ////

7181
/* SPE load and stores */
A
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7182
static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
7183 7184 7185
{
    target_ulong uimm = rB(ctx->opcode);

A
aurel32 已提交
7186
    if (rA(ctx->opcode) == 0) {
7187
        tcg_gen_movi_tl(EA, uimm << sh);
A
aurel32 已提交
7188
    } else {
7189
        tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
A
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7190 7191 7192 7193 7194 7195
#if defined(TARGET_PPC64)
        if (!ctx->sf_mode) {
            tcg_gen_ext32u_tl(EA, EA);
        }
#endif
    }
7196
}
7197 7198 7199 7200

static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
A
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7201
    gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7202 7203
#else
    TCGv_i64 t0 = tcg_temp_new_i64();
A
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7204
    gen_qemu_ld64(ctx, t0, addr);
7205 7206 7207 7208 7209
    tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
    tcg_gen_shri_i64(t0, t0, 32);
    tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
    tcg_temp_free_i64(t0);
#endif
7210
}
7211 7212 7213

static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
{
7214
#if defined(TARGET_PPC64)
7215
    TCGv t0 = tcg_temp_new();
A
aurel32 已提交
7216
    gen_qemu_ld32u(ctx, t0, addr);
7217
    tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
A
aurel32 已提交
7218 7219
    gen_addr_add(ctx, addr, addr, 4);
    gen_qemu_ld32u(ctx, t0, addr);
7220 7221 7222
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free(t0);
#else
A
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7223 7224 7225
    gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
    gen_addr_add(ctx, addr, addr, 4);
    gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7226
#endif
7227
}
7228 7229 7230 7231 7232

static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
{
    TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
A
aurel32 已提交
7233
    gen_qemu_ld16u(ctx, t0, addr);
7234
    tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
A
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7235 7236
    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, t0, addr);
7237 7238
    tcg_gen_shli_tl(t0, t0, 32);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
A
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7239 7240
    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, t0, addr);
7241 7242
    tcg_gen_shli_tl(t0, t0, 16);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
A
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7243 7244
    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, t0, addr);
7245
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7246
#else
A
aurel32 已提交
7247
    gen_qemu_ld16u(ctx, t0, addr);
7248
    tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
A
aurel32 已提交
7249 7250
    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, t0, addr);
7251
    tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
A
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7252 7253
    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, t0, addr);
7254
    tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
A
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7255 7256
    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, t0, addr);
7257
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7258
#endif
7259
    tcg_temp_free(t0);
7260 7261
}

7262 7263 7264
static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
{
    TCGv t0 = tcg_temp_new();
A
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7265
    gen_qemu_ld16u(ctx, t0, addr);
7266 7267 7268 7269 7270 7271 7272 7273 7274 7275
#if defined(TARGET_PPC64)
    tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
    tcg_gen_shli_tl(t0, t0, 16);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
#else
    tcg_gen_shli_tl(t0, t0, 16);
    tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
#endif
    tcg_temp_free(t0);
7276 7277
}

7278 7279 7280
static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
{
    TCGv t0 = tcg_temp_new();
A
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7281
    gen_qemu_ld16u(ctx, t0, addr);
7282 7283 7284 7285 7286 7287 7288 7289
#if defined(TARGET_PPC64)
    tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
#else
    tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
#endif
    tcg_temp_free(t0);
7290 7291
}

7292 7293 7294
static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
{
    TCGv t0 = tcg_temp_new();
A
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7295
    gen_qemu_ld16s(ctx, t0, addr);
7296 7297 7298 7299 7300 7301 7302 7303 7304 7305 7306 7307 7308 7309 7310
#if defined(TARGET_PPC64)
    tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
    tcg_gen_ext32u_tl(t0, t0);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
#else
    tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
#endif
    tcg_temp_free(t0);
}

static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
{
    TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
A
aurel32 已提交
7311
    gen_qemu_ld16u(ctx, t0, addr);
7312
    tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
A
aurel32 已提交
7313 7314
    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, t0, addr);
7315 7316 7317
    tcg_gen_shli_tl(t0, t0, 16);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
#else
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    gen_qemu_ld16u(ctx, t0, addr);
7319
    tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
A
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7320 7321
    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, t0, addr);
7322 7323 7324 7325 7326 7327 7328 7329 7330
    tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
#endif
    tcg_temp_free(t0);
}

static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
    TCGv t0 = tcg_temp_new();
A
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7331 7332 7333
    gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, t0, addr);
7334 7335 7336 7337
    tcg_gen_shli_tl(t0, t0, 32);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free(t0);
#else
A
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7338 7339 7340
    gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7341 7342 7343 7344 7345 7346 7347
#endif
}

static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
    TCGv t0 = tcg_temp_new();
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    gen_qemu_ld16s(ctx, t0, addr);
7349
    tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
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    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16s(ctx, t0, addr);
7352 7353 7354 7355
    tcg_gen_shli_tl(t0, t0, 32);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
    tcg_temp_free(t0);
#else
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    gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7359 7360 7361 7362 7363 7364
#endif
}

static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
{
    TCGv t0 = tcg_temp_new();
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    gen_qemu_ld32u(ctx, t0, addr);
7366
#if defined(TARGET_PPC64)
7367 7368 7369 7370 7371 7372 7373 7374 7375 7376 7377 7378 7379
    tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
#else
    tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
#endif
    tcg_temp_free(t0);
}

static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
{
    TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
A
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    gen_qemu_ld16u(ctx, t0, addr);
7381 7382 7383
    tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
    tcg_gen_shli_tl(t0, t0, 32);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
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    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, t0, addr);
7386 7387 7388 7389
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
    tcg_gen_shli_tl(t0, t0, 16);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
#else
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    gen_qemu_ld16u(ctx, t0, addr);
7391 7392
    tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
    tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
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    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_ld16u(ctx, t0, addr);
7395 7396
    tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7397
#endif
7398 7399 7400 7401 7402 7403
    tcg_temp_free(t0);
}

static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
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    gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7405
#else
7406 7407
    TCGv_i64 t0 = tcg_temp_new_i64();
    tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
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    gen_qemu_st64(ctx, t0, addr);
7409 7410 7411 7412 7413 7414
    tcg_temp_free_i64(t0);
#endif
}

static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
{
7415
#if defined(TARGET_PPC64)
7416 7417
    TCGv t0 = tcg_temp_new();
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
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    gen_qemu_st32(ctx, t0, addr);
7419 7420
    tcg_temp_free(t0);
#else
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    gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7422
#endif
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    gen_addr_add(ctx, addr, addr, 4);
    gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7425 7426 7427 7428 7429 7430 7431 7432 7433 7434
}

static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
{
    TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
#else
    tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
#endif
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    gen_qemu_st16(ctx, t0, addr);
    gen_addr_add(ctx, addr, addr, 2);
7437 7438
#if defined(TARGET_PPC64)
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
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    gen_qemu_st16(ctx, t0, addr);
7440
#else
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    gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7442
#endif
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    gen_addr_add(ctx, addr, addr, 2);
7444
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
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    gen_qemu_st16(ctx, t0, addr);
7446
    tcg_temp_free(t0);
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    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7449 7450 7451 7452 7453 7454 7455 7456 7457 7458
}

static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
{
    TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
#else
    tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
#endif
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    gen_qemu_st16(ctx, t0, addr);
    gen_addr_add(ctx, addr, addr, 2);
7461
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
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    gen_qemu_st16(ctx, t0, addr);
7463 7464 7465 7466 7467 7468 7469 7470
    tcg_temp_free(t0);
}

static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
    TCGv t0 = tcg_temp_new();
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
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    gen_qemu_st16(ctx, t0, addr);
7472 7473
    tcg_temp_free(t0);
#else
A
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    gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7475
#endif
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    gen_addr_add(ctx, addr, addr, 2);
    gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7478 7479 7480 7481 7482 7483 7484
}

static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
    TCGv t0 = tcg_temp_new();
    tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
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    gen_qemu_st32(ctx, t0, addr);
7486 7487
    tcg_temp_free(t0);
#else
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    gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7489 7490 7491 7492 7493
#endif
}

static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
{
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    gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7495 7496 7497
}

#define GEN_SPEOP_LDST(name, opc2, sh)                                        \
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GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)                      \
7499 7500 7501
{                                                                             \
    TCGv t0;                                                                  \
    if (unlikely(!ctx->spe_enabled)) {                                        \
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        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
7503 7504
        return;                                                               \
    }                                                                         \
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    gen_set_access_type(ctx, ACCESS_INT);                                     \
7506 7507
    t0 = tcg_temp_new();                                                      \
    if (Rc(ctx->opcode)) {                                                    \
A
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        gen_addr_spe_imm_index(ctx, t0, sh);                                  \
7509
    } else {                                                                  \
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        gen_addr_reg_index(ctx, t0);                                          \
7511 7512 7513 7514 7515 7516 7517 7518 7519 7520 7521 7522 7523 7524 7525 7526 7527 7528 7529 7530 7531 7532 7533 7534
    }                                                                         \
    gen_op_##name(ctx, t0);                                                   \
    tcg_temp_free(t0);                                                        \
}

GEN_SPEOP_LDST(evldd, 0x00, 3);
GEN_SPEOP_LDST(evldw, 0x01, 3);
GEN_SPEOP_LDST(evldh, 0x02, 3);
GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
GEN_SPEOP_LDST(evlwhe, 0x08, 2);
GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);

GEN_SPEOP_LDST(evstdd, 0x10, 3);
GEN_SPEOP_LDST(evstdw, 0x11, 3);
GEN_SPEOP_LDST(evstdh, 0x12, 3);
GEN_SPEOP_LDST(evstwhe, 0x18, 2);
GEN_SPEOP_LDST(evstwho, 0x1A, 2);
GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7535 7536 7537 7538 7539 7540 7541 7542 7543 7544 7545 7546 7547 7548 7549 7550 7551 7552 7553 7554 7555 7556 7557 7558 7559 7560 7561 7562 7563 7564 7565 7566 7567 7568 7569 7570 7571 7572 7573 7574 7575 7576 7577 7578 7579 7580 7581 7582 7583 7584 7585 7586 7587 7588 7589 7590 7591 7592 7593 7594 7595 7596 7597 7598 7599 7600 7601 7602 7603 7604 7605 7606 7607 7608 7609 7610 7611 7612

/* Multiply and add - TODO */
#if 0
GEN_SPE(speundef,       evmhessf,      0x01, 0x10, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhossf,      0x03, 0x10, 0x00000000, PPC_SPE);
GEN_SPE(evmheumi,       evmhesmi,      0x04, 0x10, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhesmf,      0x05, 0x10, 0x00000000, PPC_SPE);
GEN_SPE(evmhoumi,       evmhosmi,      0x06, 0x10, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhosmf,      0x07, 0x10, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhessfa,     0x11, 0x10, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhossfa,     0x13, 0x10, 0x00000000, PPC_SPE);
GEN_SPE(evmheumia,      evmhesmia,     0x14, 0x10, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhesmfa,     0x15, 0x10, 0x00000000, PPC_SPE);
GEN_SPE(evmhoumia,      evmhosmia,     0x16, 0x10, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhosmfa,     0x17, 0x10, 0x00000000, PPC_SPE);

GEN_SPE(speundef,       evmwhssf,      0x03, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(evmwlumi,       speundef,      0x04, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(evmwhumi,       evmwhsmi,      0x06, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmwhsmf,      0x07, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmwssf,       0x09, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(evmwumi,        evmwsmi,       0x0C, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmwsmf,       0x0D, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmwhssfa,     0x13, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(evmwlumia,      speundef,      0x14, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(evmwhumia,      evmwhsmia,     0x16, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmwhsmfa,     0x17, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmwssfa,      0x19, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(evmwumia,       evmwsmia,      0x1C, 0x11, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmwsmfa,      0x1D, 0x11, 0x00000000, PPC_SPE);

GEN_SPE(evadduiaaw,     evaddsiaaw,    0x00, 0x13, 0x0000F800, PPC_SPE);
GEN_SPE(evsubfusiaaw,   evsubfssiaaw,  0x01, 0x13, 0x0000F800, PPC_SPE);
GEN_SPE(evaddumiaaw,    evaddsmiaaw,   0x04, 0x13, 0x0000F800, PPC_SPE);
GEN_SPE(evsubfumiaaw,   evsubfsmiaaw,  0x05, 0x13, 0x0000F800, PPC_SPE);
GEN_SPE(evdivws,        evdivwu,       0x06, 0x13, 0x00000000, PPC_SPE);
GEN_SPE(evmra,          speundef,      0x07, 0x13, 0x0000F800, PPC_SPE);

GEN_SPE(evmheusiaaw,    evmhessiaaw,   0x00, 0x14, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhessfaaw,   0x01, 0x14, 0x00000000, PPC_SPE);
GEN_SPE(evmhousiaaw,    evmhossiaaw,   0x02, 0x14, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhossfaaw,   0x03, 0x14, 0x00000000, PPC_SPE);
GEN_SPE(evmheumiaaw,    evmhesmiaaw,   0x04, 0x14, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhesmfaaw,   0x05, 0x14, 0x00000000, PPC_SPE);
GEN_SPE(evmhoumiaaw,    evmhosmiaaw,   0x06, 0x14, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhosmfaaw,   0x07, 0x14, 0x00000000, PPC_SPE);
GEN_SPE(evmhegumiaa,    evmhegsmiaa,   0x14, 0x14, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhegsmfaa,   0x15, 0x14, 0x00000000, PPC_SPE);
GEN_SPE(evmhogumiaa,    evmhogsmiaa,   0x16, 0x14, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhogsmfaa,   0x17, 0x14, 0x00000000, PPC_SPE);

GEN_SPE(evmwlusiaaw,    evmwlssiaaw,   0x00, 0x15, 0x00000000, PPC_SPE);
GEN_SPE(evmwlumiaaw,    evmwlsmiaaw,   0x04, 0x15, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmwssfaa,     0x09, 0x15, 0x00000000, PPC_SPE);
GEN_SPE(evmwumiaa,      evmwsmiaa,     0x0C, 0x15, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmwsmfaa,     0x0D, 0x15, 0x00000000, PPC_SPE);

GEN_SPE(evmheusianw,    evmhessianw,   0x00, 0x16, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhessfanw,   0x01, 0x16, 0x00000000, PPC_SPE);
GEN_SPE(evmhousianw,    evmhossianw,   0x02, 0x16, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhossfanw,   0x03, 0x16, 0x00000000, PPC_SPE);
GEN_SPE(evmheumianw,    evmhesmianw,   0x04, 0x16, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhesmfanw,   0x05, 0x16, 0x00000000, PPC_SPE);
GEN_SPE(evmhoumianw,    evmhosmianw,   0x06, 0x16, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhosmfanw,   0x07, 0x16, 0x00000000, PPC_SPE);
GEN_SPE(evmhegumian,    evmhegsmian,   0x14, 0x16, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhegsmfan,   0x15, 0x16, 0x00000000, PPC_SPE);
GEN_SPE(evmhigumian,    evmhigsmian,   0x16, 0x16, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmhogsmfan,   0x17, 0x16, 0x00000000, PPC_SPE);

GEN_SPE(evmwlusianw,    evmwlssianw,   0x00, 0x17, 0x00000000, PPC_SPE);
GEN_SPE(evmwlumianw,    evmwlsmianw,   0x04, 0x17, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmwssfan,     0x09, 0x17, 0x00000000, PPC_SPE);
GEN_SPE(evmwumian,      evmwsmian,     0x0C, 0x17, 0x00000000, PPC_SPE);
GEN_SPE(speundef,       evmwsmfan,     0x0D, 0x17, 0x00000000, PPC_SPE);
#endif

/***                      SPE floating-point extension                     ***/
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7613 7614
#if defined(TARGET_PPC64)
#define GEN_SPEFPUOP_CONV_32_32(name)                                         \
7615
static always_inline void gen_##name (DisasContext *ctx)                      \
7616
{                                                                             \
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    TCGv_i32 t0;                                                              \
    TCGv t1;                                                                  \
    t0 = tcg_temp_new_i32();                                                  \
    tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);                       \
    gen_helper_##name(t0, t0);                                                \
    t1 = tcg_temp_new();                                                      \
    tcg_gen_extu_i32_tl(t1, t0);                                              \
    tcg_temp_free_i32(t0);                                                    \
    tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)],       \
                    0xFFFFFFFF00000000ULL);                                   \
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1);    \
    tcg_temp_free(t1);                                                        \
7629
}
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#define GEN_SPEFPUOP_CONV_32_64(name)                                         \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    TCGv_i32 t0;                                                              \
    TCGv t1;                                                                  \
    t0 = tcg_temp_new_i32();                                                  \
    gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]);                          \
    t1 = tcg_temp_new();                                                      \
    tcg_gen_extu_i32_tl(t1, t0);                                              \
    tcg_temp_free_i32(t0);                                                    \
    tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)],       \
                    0xFFFFFFFF00000000ULL);                                   \
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1);    \
    tcg_temp_free(t1);                                                        \
}
#define GEN_SPEFPUOP_CONV_64_32(name)                                         \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    TCGv_i32 t0 = tcg_temp_new_i32();                                         \
    tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);                       \
    gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0);                          \
    tcg_temp_free_i32(t0);                                                    \
}
#define GEN_SPEFPUOP_CONV_64_64(name)                                         \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);    \
}
#define GEN_SPEFPUOP_ARITH2_32_32(name)                                       \
7659 7660
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
A
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7661 7662
    TCGv_i32 t0, t1;                                                          \
    TCGv_i64 t2;                                                              \
7663
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
7664
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
7665 7666
        return;                                                               \
    }                                                                         \
A
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7667 7668 7669 7670 7671 7672 7673 7674 7675 7676 7677 7678 7679
    t0 = tcg_temp_new_i32();                                                  \
    t1 = tcg_temp_new_i32();                                                  \
    tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);                       \
    tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);                       \
    gen_helper_##name(t0, t0, t1);                                            \
    tcg_temp_free_i32(t1);                                                    \
    t2 = tcg_temp_new();                                                      \
    tcg_gen_extu_i32_tl(t2, t0);                                              \
    tcg_temp_free_i32(t0);                                                    \
    tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)],       \
                    0xFFFFFFFF00000000ULL);                                   \
    tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2);    \
    tcg_temp_free(t2);                                                        \
7680
}
A
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7681
#define GEN_SPEFPUOP_ARITH2_64_64(name)                                       \
7682 7683 7684
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
7685
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
7686 7687
        return;                                                               \
    }                                                                         \
A
aurel32 已提交
7688 7689
    gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],     \
                      cpu_gpr[rB(ctx->opcode)]);                              \
7690
}
A
aurel32 已提交
7691
#define GEN_SPEFPUOP_COMP_32(name)                                            \
7692 7693
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
A
aurel32 已提交
7694
    TCGv_i32 t0, t1;                                                          \
7695
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
7696
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
7697 7698
        return;                                                               \
    }                                                                         \
A
aurel32 已提交
7699 7700 7701 7702 7703 7704 7705 7706 7707 7708 7709 7710
    t0 = tcg_temp_new_i32();                                                  \
    t1 = tcg_temp_new_i32();                                                  \
    tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);                       \
    tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);                       \
    gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1);                    \
    tcg_temp_free_i32(t0);                                                    \
    tcg_temp_free_i32(t1);                                                    \
}
#define GEN_SPEFPUOP_COMP_64(name)                                            \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
7711
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
A
aurel32 已提交
7712 7713 7714 7715 7716 7717 7718 7719 7720 7721
        return;                                                               \
    }                                                                         \
    gen_helper_##name(cpu_crf[crfD(ctx->opcode)],                             \
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);    \
}
#else
#define GEN_SPEFPUOP_CONV_32_32(name)                                         \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);    \
7722
}
A
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7723 7724 7725 7726 7727 7728 7729 7730 7731 7732 7733 7734 7735 7736 7737 7738 7739 7740 7741 7742 7743 7744 7745 7746 7747 7748 7749 7750 7751
#define GEN_SPEFPUOP_CONV_32_64(name)                                         \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    TCGv_i64 t0 = tcg_temp_new_i64();                                         \
    gen_load_gpr64(t0, rB(ctx->opcode));                                      \
    gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0);                          \
    tcg_temp_free_i64(t0);                                                    \
}
#define GEN_SPEFPUOP_CONV_64_32(name)                                         \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    TCGv_i64 t0 = tcg_temp_new_i64();                                         \
    gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]);                          \
    gen_store_gpr64(rD(ctx->opcode), t0);                                     \
    tcg_temp_free_i64(t0);                                                    \
}
#define GEN_SPEFPUOP_CONV_64_64(name)                                         \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    TCGv_i64 t0 = tcg_temp_new_i64();                                         \
    gen_load_gpr64(t0, rB(ctx->opcode));                                      \
    gen_helper_##name(t0, t0);                                                \
    gen_store_gpr64(rD(ctx->opcode), t0);                                     \
    tcg_temp_free_i64(t0);                                                    \
}
#define GEN_SPEFPUOP_ARITH2_32_32(name)                                       \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
7752
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
A
aurel32 已提交
7753 7754 7755 7756 7757 7758 7759 7760 7761 7762
        return;                                                               \
    }                                                                         \
    gen_helper_##name(cpu_gpr[rD(ctx->opcode)],                               \
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);    \
}
#define GEN_SPEFPUOP_ARITH2_64_64(name)                                       \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    TCGv_i64 t0, t1;                                                          \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
7763
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
A
aurel32 已提交
7764 7765 7766 7767 7768 7769 7770 7771 7772 7773 7774 7775 7776 7777 7778
        return;                                                               \
    }                                                                         \
    t0 = tcg_temp_new_i64();                                                  \
    t1 = tcg_temp_new_i64();                                                  \
    gen_load_gpr64(t0, rA(ctx->opcode));                                      \
    gen_load_gpr64(t1, rB(ctx->opcode));                                      \
    gen_helper_##name(t0, t0, t1);                                            \
    gen_store_gpr64(rD(ctx->opcode), t0);                                     \
    tcg_temp_free_i64(t0);                                                    \
    tcg_temp_free_i64(t1);                                                    \
}
#define GEN_SPEFPUOP_COMP_32(name)                                            \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
7779
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
A
aurel32 已提交
7780 7781 7782 7783 7784 7785 7786 7787 7788 7789
        return;                                                               \
    }                                                                         \
    gen_helper_##name(cpu_crf[crfD(ctx->opcode)],                             \
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);    \
}
#define GEN_SPEFPUOP_COMP_64(name)                                            \
static always_inline void gen_##name (DisasContext *ctx)                      \
{                                                                             \
    TCGv_i64 t0, t1;                                                          \
    if (unlikely(!ctx->spe_enabled)) {                                        \
A
aurel32 已提交
7790
        gen_exception(ctx, POWERPC_EXCP_APU);                                 \
A
aurel32 已提交
7791 7792 7793 7794 7795 7796 7797 7798 7799 7800 7801
        return;                                                               \
    }                                                                         \
    t0 = tcg_temp_new_i64();                                                  \
    t1 = tcg_temp_new_i64();                                                  \
    gen_load_gpr64(t0, rA(ctx->opcode));                                      \
    gen_load_gpr64(t1, rB(ctx->opcode));                                      \
    gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1);                    \
    tcg_temp_free_i64(t0);                                                    \
    tcg_temp_free_i64(t1);                                                    \
}
#endif
7802

7803 7804
/* Single precision floating-point vectors operations */
/* Arithmetic */
A
aurel32 已提交
7805 7806 7807 7808 7809 7810 7811
GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
GEN_SPEFPUOP_ARITH2_64_64(evfssub);
GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
static always_inline void gen_evfsabs (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
A
aurel32 已提交
7812
        gen_exception(ctx, POWERPC_EXCP_APU);
A
aurel32 已提交
7813 7814 7815 7816 7817 7818 7819 7820 7821 7822 7823 7824
        return;
    }
#if defined(TARGET_PPC64)
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
#else
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
    tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
#endif
}
static always_inline void gen_evfsnabs (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
A
aurel32 已提交
7825
        gen_exception(ctx, POWERPC_EXCP_APU);
A
aurel32 已提交
7826 7827 7828 7829 7830 7831 7832 7833 7834 7835 7836 7837
        return;
    }
#if defined(TARGET_PPC64)
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
#else
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
    tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
#endif
}
static always_inline void gen_evfsneg (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
A
aurel32 已提交
7838
        gen_exception(ctx, POWERPC_EXCP_APU);
A
aurel32 已提交
7839 7840 7841 7842 7843 7844 7845 7846 7847 7848
        return;
    }
#if defined(TARGET_PPC64)
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
#else
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
    tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
#endif
}

7849
/* Conversion */
A
aurel32 已提交
7850 7851 7852 7853 7854 7855 7856 7857 7858 7859 7860
GEN_SPEFPUOP_CONV_64_64(evfscfui);
GEN_SPEFPUOP_CONV_64_64(evfscfsi);
GEN_SPEFPUOP_CONV_64_64(evfscfuf);
GEN_SPEFPUOP_CONV_64_64(evfscfsf);
GEN_SPEFPUOP_CONV_64_64(evfsctui);
GEN_SPEFPUOP_CONV_64_64(evfsctsi);
GEN_SPEFPUOP_CONV_64_64(evfsctuf);
GEN_SPEFPUOP_CONV_64_64(evfsctsf);
GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
GEN_SPEFPUOP_CONV_64_64(evfsctsiz);

7861
/* Comparison */
A
aurel32 已提交
7862 7863 7864 7865 7866 7867
GEN_SPEFPUOP_COMP_64(evfscmpgt);
GEN_SPEFPUOP_COMP_64(evfscmplt);
GEN_SPEFPUOP_COMP_64(evfscmpeq);
GEN_SPEFPUOP_COMP_64(evfststgt);
GEN_SPEFPUOP_COMP_64(evfststlt);
GEN_SPEFPUOP_COMP_64(evfststeq);
7868 7869 7870 7871 7872 7873 7874 7875 7876 7877 7878 7879 7880 7881 7882 7883 7884 7885 7886

/* Opcodes definitions */
GEN_SPE(evfsadd,        evfssub,       0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
GEN_SPE(evfsabs,        evfsnabs,      0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
GEN_SPE(evfsneg,        speundef,      0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
GEN_SPE(evfsmul,        evfsdiv,       0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
GEN_SPE(evfscmpgt,      evfscmplt,     0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
GEN_SPE(evfscmpeq,      speundef,      0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
GEN_SPE(evfscfui,       evfscfsi,      0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
GEN_SPE(evfscfuf,       evfscfsf,      0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
GEN_SPE(evfsctui,       evfsctsi,      0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
GEN_SPE(evfsctuf,       evfsctsf,      0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
GEN_SPE(evfsctuiz,      speundef,      0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
GEN_SPE(evfsctsiz,      speundef,      0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
GEN_SPE(evfststgt,      evfststlt,     0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
GEN_SPE(evfststeq,      speundef,      0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //

/* Single precision floating-point operations */
/* Arithmetic */
A
aurel32 已提交
7887 7888 7889 7890 7891 7892 7893
GEN_SPEFPUOP_ARITH2_32_32(efsadd);
GEN_SPEFPUOP_ARITH2_32_32(efssub);
GEN_SPEFPUOP_ARITH2_32_32(efsmul);
GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
static always_inline void gen_efsabs (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
A
aurel32 已提交
7894
        gen_exception(ctx, POWERPC_EXCP_APU);
A
aurel32 已提交
7895 7896 7897 7898 7899 7900 7901
        return;
    }
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
}
static always_inline void gen_efsnabs (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
A
aurel32 已提交
7902
        gen_exception(ctx, POWERPC_EXCP_APU);
A
aurel32 已提交
7903 7904 7905 7906 7907 7908 7909
        return;
    }
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
}
static always_inline void gen_efsneg (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
A
aurel32 已提交
7910
        gen_exception(ctx, POWERPC_EXCP_APU);
A
aurel32 已提交
7911 7912 7913 7914 7915
        return;
    }
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
}

7916
/* Conversion */
A
aurel32 已提交
7917 7918 7919 7920 7921 7922 7923 7924 7925 7926 7927 7928
GEN_SPEFPUOP_CONV_32_32(efscfui);
GEN_SPEFPUOP_CONV_32_32(efscfsi);
GEN_SPEFPUOP_CONV_32_32(efscfuf);
GEN_SPEFPUOP_CONV_32_32(efscfsf);
GEN_SPEFPUOP_CONV_32_32(efsctui);
GEN_SPEFPUOP_CONV_32_32(efsctsi);
GEN_SPEFPUOP_CONV_32_32(efsctuf);
GEN_SPEFPUOP_CONV_32_32(efsctsf);
GEN_SPEFPUOP_CONV_32_32(efsctuiz);
GEN_SPEFPUOP_CONV_32_32(efsctsiz);
GEN_SPEFPUOP_CONV_32_64(efscfd);

7929
/* Comparison */
A
aurel32 已提交
7930 7931 7932 7933 7934 7935
GEN_SPEFPUOP_COMP_32(efscmpgt);
GEN_SPEFPUOP_COMP_32(efscmplt);
GEN_SPEFPUOP_COMP_32(efscmpeq);
GEN_SPEFPUOP_COMP_32(efststgt);
GEN_SPEFPUOP_COMP_32(efststlt);
GEN_SPEFPUOP_COMP_32(efststeq);
7936 7937

/* Opcodes definitions */
7938
GEN_SPE(efsadd,         efssub,        0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
7939 7940 7941 7942 7943 7944 7945 7946 7947
GEN_SPE(efsabs,         efsnabs,       0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
GEN_SPE(efsneg,         speundef,      0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
GEN_SPE(efsmul,         efsdiv,        0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
GEN_SPE(efscmpgt,       efscmplt,      0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
GEN_SPE(efscmpeq,       efscfd,        0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
GEN_SPE(efscfui,        efscfsi,       0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efscfuf,        efscfsf,       0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efsctui,        efsctsi,       0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efsctuf,        efsctsf,       0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
7948 7949
GEN_SPE(efsctuiz,       speundef,      0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efsctsiz,       speundef,      0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
7950 7951 7952 7953 7954
GEN_SPE(efststgt,       efststlt,      0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
GEN_SPE(efststeq,       speundef,      0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //

/* Double precision floating-point operations */
/* Arithmetic */
A
aurel32 已提交
7955 7956 7957 7958 7959 7960 7961
GEN_SPEFPUOP_ARITH2_64_64(efdadd);
GEN_SPEFPUOP_ARITH2_64_64(efdsub);
GEN_SPEFPUOP_ARITH2_64_64(efdmul);
GEN_SPEFPUOP_ARITH2_64_64(efddiv);
static always_inline void gen_efdabs (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
A
aurel32 已提交
7962
        gen_exception(ctx, POWERPC_EXCP_APU);
A
aurel32 已提交
7963 7964 7965 7966 7967 7968 7969 7970 7971 7972 7973
        return;
    }
#if defined(TARGET_PPC64)
    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
#else
    tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
#endif
}
static always_inline void gen_efdnabs (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
A
aurel32 已提交
7974
        gen_exception(ctx, POWERPC_EXCP_APU);
A
aurel32 已提交
7975 7976 7977 7978 7979 7980 7981 7982 7983 7984 7985
        return;
    }
#if defined(TARGET_PPC64)
    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
#else
    tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
#endif
}
static always_inline void gen_efdneg (DisasContext *ctx)
{
    if (unlikely(!ctx->spe_enabled)) {
A
aurel32 已提交
7986
        gen_exception(ctx, POWERPC_EXCP_APU);
A
aurel32 已提交
7987 7988 7989 7990 7991 7992 7993 7994 7995
        return;
    }
#if defined(TARGET_PPC64)
    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
#else
    tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
#endif
}

7996
/* Conversion */
A
aurel32 已提交
7997 7998 7999 8000 8001 8002 8003 8004 8005 8006 8007 8008 8009 8010 8011
GEN_SPEFPUOP_CONV_64_32(efdcfui);
GEN_SPEFPUOP_CONV_64_32(efdcfsi);
GEN_SPEFPUOP_CONV_64_32(efdcfuf);
GEN_SPEFPUOP_CONV_64_32(efdcfsf);
GEN_SPEFPUOP_CONV_32_64(efdctui);
GEN_SPEFPUOP_CONV_32_64(efdctsi);
GEN_SPEFPUOP_CONV_32_64(efdctuf);
GEN_SPEFPUOP_CONV_32_64(efdctsf);
GEN_SPEFPUOP_CONV_32_64(efdctuiz);
GEN_SPEFPUOP_CONV_32_64(efdctsiz);
GEN_SPEFPUOP_CONV_64_32(efdcfs);
GEN_SPEFPUOP_CONV_64_64(efdcfuid);
GEN_SPEFPUOP_CONV_64_64(efdcfsid);
GEN_SPEFPUOP_CONV_64_64(efdctuidz);
GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8012 8013

/* Comparison */
A
aurel32 已提交
8014 8015 8016 8017 8018 8019
GEN_SPEFPUOP_COMP_64(efdcmpgt);
GEN_SPEFPUOP_COMP_64(efdcmplt);
GEN_SPEFPUOP_COMP_64(efdcmpeq);
GEN_SPEFPUOP_COMP_64(efdtstgt);
GEN_SPEFPUOP_COMP_64(efdtstlt);
GEN_SPEFPUOP_COMP_64(efdtsteq);
8020 8021 8022 8023 8024 8025 8026 8027 8028 8029 8030 8031 8032 8033 8034 8035 8036 8037 8038

/* Opcodes definitions */
GEN_SPE(efdadd,         efdsub,        0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
GEN_SPE(efdcfuid,       efdcfsid,      0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efdabs,         efdnabs,       0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
GEN_SPE(efdneg,         speundef,      0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
GEN_SPE(efdmul,         efddiv,        0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
GEN_SPE(efdctuidz,      efdctsidz,     0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efdcmpgt,       efdcmplt,      0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
GEN_SPE(efdcmpeq,       efdcfs,        0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
GEN_SPE(efdcfui,        efdcfsi,       0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efdcfuf,        efdcfsf,       0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efdctui,        efdctsi,       0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efdctuf,        efdctsf,       0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efdctuiz,       speundef,      0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efdctsiz,       speundef,      0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efdtstgt,       efdtstlt,      0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
GEN_SPE(efdtsteq,       speundef,      0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //

B
bellard 已提交
8039 8040 8041
/* End opcode list */
GEN_OPCODE_MARK(end);

8042
#include "translate_init.c"
8043
#include "helper_regs.h"
B
bellard 已提交
8044

8045
/*****************************************************************************/
8046
/* Misc PowerPC helpers */
8047 8048 8049
void cpu_dump_state (CPUState *env, FILE *f,
                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
                     int flags)
B
bellard 已提交
8050
{
8051 8052 8053
#define RGPL  4
#define RFPL  4

B
bellard 已提交
8054 8055
    int i;

J
j_mayer 已提交
8056
    cpu_fprintf(f, "NIP " ADDRX "   LR " ADDRX " CTR " ADDRX " XER %08x\n",
A
aurel32 已提交
8057
                env->nip, env->lr, env->ctr, env->xer);
8058 8059
    cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX "  HF " ADDRX " idx %d\n",
                env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
8060
#if !defined(NO_TIMER_DUMP)
J
j_mayer 已提交
8061
    cpu_fprintf(f, "TB %08x %08x "
8062 8063 8064 8065
#if !defined(CONFIG_USER_ONLY)
                "DECR %08x"
#endif
                "\n",
J
j_mayer 已提交
8066
                cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8067 8068 8069 8070
#if !defined(CONFIG_USER_ONLY)
                , cpu_ppc_load_decr(env)
#endif
                );
J
j_mayer 已提交
8071
#endif
8072
    for (i = 0; i < 32; i++) {
8073 8074
        if ((i & (RGPL - 1)) == 0)
            cpu_fprintf(f, "GPR%02d", i);
8075
        cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
8076
        if ((i & (RGPL - 1)) == (RGPL - 1))
B
bellard 已提交
8077
            cpu_fprintf(f, "\n");
8078
    }
8079
    cpu_fprintf(f, "CR ");
8080
    for (i = 0; i < 8; i++)
B
bellard 已提交
8081 8082
        cpu_fprintf(f, "%01x", env->crf[i]);
    cpu_fprintf(f, "  [");
8083 8084 8085 8086 8087 8088 8089 8090
    for (i = 0; i < 8; i++) {
        char a = '-';
        if (env->crf[i] & 0x08)
            a = 'L';
        else if (env->crf[i] & 0x04)
            a = 'G';
        else if (env->crf[i] & 0x02)
            a = 'E';
B
bellard 已提交
8091
        cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8092
    }
8093
    cpu_fprintf(f, " ]             RES " ADDRX "\n", env->reserve);
8094 8095 8096
    for (i = 0; i < 32; i++) {
        if ((i & (RFPL - 1)) == 0)
            cpu_fprintf(f, "FPR%02d", i);
B
bellard 已提交
8097
        cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
8098
        if ((i & (RFPL - 1)) == (RFPL - 1))
B
bellard 已提交
8099
            cpu_fprintf(f, "\n");
B
bellard 已提交
8100
    }
8101
    cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
8102
#if !defined(CONFIG_USER_ONLY)
8103
    cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
8104
                env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
8105
#endif
B
bellard 已提交
8106

8107 8108
#undef RGPL
#undef RFPL
B
bellard 已提交
8109 8110
}

8111 8112 8113 8114 8115 8116 8117 8118 8119 8120 8121 8122 8123 8124 8125 8126 8127 8128 8129 8130 8131 8132 8133 8134 8135 8136 8137 8138 8139 8140 8141 8142 8143 8144 8145 8146 8147 8148 8149 8150 8151 8152 8153 8154 8155 8156 8157
void cpu_dump_statistics (CPUState *env, FILE*f,
                          int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
                          int flags)
{
#if defined(DO_PPC_STATISTICS)
    opc_handler_t **t1, **t2, **t3, *handler;
    int op1, op2, op3;

    t1 = env->opcodes;
    for (op1 = 0; op1 < 64; op1++) {
        handler = t1[op1];
        if (is_indirect_opcode(handler)) {
            t2 = ind_table(handler);
            for (op2 = 0; op2 < 32; op2++) {
                handler = t2[op2];
                if (is_indirect_opcode(handler)) {
                    t3 = ind_table(handler);
                    for (op3 = 0; op3 < 32; op3++) {
                        handler = t3[op3];
                        if (handler->count == 0)
                            continue;
                        cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
                                    "%016llx %lld\n",
                                    op1, op2, op3, op1, (op3 << 5) | op2,
                                    handler->oname,
                                    handler->count, handler->count);
                    }
                } else {
                    if (handler->count == 0)
                        continue;
                    cpu_fprintf(f, "%02x %02x    (%02x %04d) %16s: "
                                "%016llx %lld\n",
                                op1, op2, op1, op2, handler->oname,
                                handler->count, handler->count);
                }
            }
        } else {
            if (handler->count == 0)
                continue;
            cpu_fprintf(f, "%02x       (%02x     ) %16s: %016llx %lld\n",
                        op1, op1, handler->oname,
                        handler->count, handler->count);
        }
    }
#endif
}

8158
/*****************************************************************************/
8159 8160 8161
static always_inline void gen_intermediate_code_internal (CPUState *env,
                                                          TranslationBlock *tb,
                                                          int search_pc)
B
bellard 已提交
8162
{
8163
    DisasContext ctx, *ctxp = &ctx;
B
bellard 已提交
8164
    opc_handler_t **table, *handler;
B
bellard 已提交
8165
    target_ulong pc_start;
B
bellard 已提交
8166
    uint16_t *gen_opc_end;
8167
    CPUBreakpoint *bp;
B
bellard 已提交
8168
    int j, lj = -1;
P
pbrook 已提交
8169 8170
    int num_insns;
    int max_insns;
B
bellard 已提交
8171 8172 8173

    pc_start = tb->pc;
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
B
bellard 已提交
8174
    ctx.nip = pc_start;
B
bellard 已提交
8175
    ctx.tb = tb;
8176
    ctx.exception = POWERPC_EXCP_NONE;
8177
    ctx.spr_cb = env->spr_cb;
A
aurel32 已提交
8178 8179 8180
    ctx.mem_idx = env->mmu_idx;
    ctx.access_type = -1;
    ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
8181 8182
#if defined(TARGET_PPC64)
    ctx.sf_mode = msr_sf;
8183
#endif
B
bellard 已提交
8184
    ctx.fpu_enabled = msr_fp;
8185
    if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
8186 8187 8188
        ctx.spe_enabled = msr_spe;
    else
        ctx.spe_enabled = 0;
8189 8190 8191 8192
    if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
        ctx.altivec_enabled = msr_vr;
    else
        ctx.altivec_enabled = 0;
8193
    if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8194
        ctx.singlestep_enabled = CPU_SINGLE_STEP;
8195
    else
8196
        ctx.singlestep_enabled = 0;
8197
    if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8198 8199 8200
        ctx.singlestep_enabled |= CPU_BRANCH_STEP;
    if (unlikely(env->singlestep_enabled))
        ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
8201
#if defined (DO_SINGLE_STEP) && 0
8202 8203 8204
    /* Single step trace mode */
    msr_se = 1;
#endif
P
pbrook 已提交
8205 8206 8207 8208 8209 8210
    num_insns = 0;
    max_insns = tb->cflags & CF_COUNT_MASK;
    if (max_insns == 0)
        max_insns = CF_COUNT_MASK;

    gen_icount_start();
8211
    /* Set env in case of segfault during code fetch */
8212
    while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
8213 8214
        if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
            TAILQ_FOREACH(bp, &env->breakpoints, entry) {
8215
                if (bp->pc == ctx.nip) {
A
aurel32 已提交
8216
                    gen_debug_exception(ctxp);
8217 8218 8219 8220
                    break;
                }
            }
        }
8221
        if (unlikely(search_pc)) {
B
bellard 已提交
8222 8223 8224 8225 8226
            j = gen_opc_ptr - gen_opc_buf;
            if (lj < j) {
                lj++;
                while (lj < j)
                    gen_opc_instr_start[lj++] = 0;
B
bellard 已提交
8227
                gen_opc_pc[lj] = ctx.nip;
B
bellard 已提交
8228
                gen_opc_instr_start[lj] = 1;
P
pbrook 已提交
8229
                gen_opc_icount[lj] = num_insns;
B
bellard 已提交
8230 8231
            }
        }
8232 8233 8234
        LOG_DISAS("----------------\n");
        LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
                  ctx.nip, ctx.mem_idx, (int)msr_ir);
P
pbrook 已提交
8235 8236
        if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
            gen_io_start();
A
aurel32 已提交
8237
        if (unlikely(ctx.le_mode)) {
8238 8239 8240
            ctx.opcode = bswap32(ldl_code(ctx.nip));
        } else {
            ctx.opcode = ldl_code(ctx.nip);
8241
        }
8242
        LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
8243
                    ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
8244
                    opc3(ctx.opcode), little_endian ? "little" : "big");
B
bellard 已提交
8245
        ctx.nip += 4;
8246
        table = env->opcodes;
P
pbrook 已提交
8247
        num_insns++;
B
bellard 已提交
8248 8249 8250 8251 8252 8253 8254 8255 8256 8257
        handler = table[opc1(ctx.opcode)];
        if (is_indirect_opcode(handler)) {
            table = ind_table(handler);
            handler = table[opc2(ctx.opcode)];
            if (is_indirect_opcode(handler)) {
                table = ind_table(handler);
                handler = table[opc3(ctx.opcode)];
            }
        }
        /* Is opcode *REALLY* valid ? */
8258
        if (unlikely(handler->handler == &gen_invalid)) {
8259 8260 8261 8262 8263
            if (qemu_log_enabled()) {
                qemu_log("invalid/unsupported opcode: "
                          "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
                          opc1(ctx.opcode), opc2(ctx.opcode),
                          opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
B
bellard 已提交
8264 8265
            } else {
                printf("invalid/unsupported opcode: "
8266
                       "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
B
bellard 已提交
8267
                       opc1(ctx.opcode), opc2(ctx.opcode),
8268
                       opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
B
bellard 已提交
8269
            }
8270 8271
        } else {
            if (unlikely((ctx.opcode & handler->inval) != 0)) {
8272 8273 8274 8275 8276 8277
                if (qemu_log_enabled()) {
                    qemu_log("invalid bits: %08x for opcode: "
                              "%02x - %02x - %02x (%08x) " ADDRX "\n",
                              ctx.opcode & handler->inval, opc1(ctx.opcode),
                              opc2(ctx.opcode), opc3(ctx.opcode),
                              ctx.opcode, ctx.nip - 4);
8278 8279
                } else {
                    printf("invalid bits: %08x for opcode: "
8280
                           "%02x - %02x - %02x (%08x) " ADDRX "\n",
8281 8282
                           ctx.opcode & handler->inval, opc1(ctx.opcode),
                           opc2(ctx.opcode), opc3(ctx.opcode),
B
bellard 已提交
8283
                           ctx.opcode, ctx.nip - 4);
8284
                }
A
aurel32 已提交
8285
                gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
B
bellard 已提交
8286
                break;
B
bellard 已提交
8287 8288
            }
        }
B
bellard 已提交
8289
        (*(handler->handler))(&ctx);
8290 8291 8292
#if defined(DO_PPC_STATISTICS)
        handler->count++;
#endif
8293
        /* Check trace mode exceptions */
8294 8295 8296 8297 8298
        if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
                     (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
                     ctx.exception != POWERPC_SYSCALL &&
                     ctx.exception != POWERPC_EXCP_TRAP &&
                     ctx.exception != POWERPC_EXCP_BRANCH)) {
A
aurel32 已提交
8299
            gen_exception(ctxp, POWERPC_EXCP_TRACE);
8300
        } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
P
pbrook 已提交
8301 8302
                            (env->singlestep_enabled) ||
                            num_insns >= max_insns)) {
8303 8304 8305
            /* if we reach a page boundary or are single stepping, stop
             * generation
             */
8306
            break;
8307
        }
8308 8309 8310 8311
#if defined (DO_SINGLE_STEP)
        break;
#endif
    }
P
pbrook 已提交
8312 8313
    if (tb->cflags & CF_LAST_IO)
        gen_io_end();
8314
    if (ctx.exception == POWERPC_EXCP_NONE) {
8315
        gen_goto_tb(&ctx, 0, ctx.nip);
8316
    } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8317
        if (unlikely(env->singlestep_enabled)) {
A
aurel32 已提交
8318
            gen_debug_exception(ctxp);
8319
        }
8320
        /* Generate the return instruction */
B
bellard 已提交
8321
        tcg_gen_exit_tb(0);
8322
    }
P
pbrook 已提交
8323
    gen_icount_end(tb, num_insns);
B
bellard 已提交
8324
    *gen_opc_ptr = INDEX_op_end;
8325
    if (unlikely(search_pc)) {
8326 8327 8328 8329 8330
        j = gen_opc_ptr - gen_opc_buf;
        lj++;
        while (lj <= j)
            gen_opc_instr_start[lj++] = 0;
    } else {
B
bellard 已提交
8331
        tb->size = ctx.nip - pc_start;
P
pbrook 已提交
8332
        tb->icount = num_insns;
8333
    }
8334
#if defined(DEBUG_DISAS)
8335 8336
    qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
    log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8337
    if (loglevel & CPU_LOG_TB_IN_ASM) {
8338
        int flags;
8339
        flags = env->bfd_mach;
A
aurel32 已提交
8340
        flags |= ctx.le_mode << 16;
8341 8342 8343
        qemu_log("IN: %s\n", lookup_symbol(pc_start));
        log_target_disas(pc_start, ctx.nip - pc_start, flags);
        qemu_log("\n");
8344
    }
B
bellard 已提交
8345 8346 8347
#endif
}

8348
void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
B
bellard 已提交
8349
{
8350
    gen_intermediate_code_internal(env, tb, 0);
B
bellard 已提交
8351 8352
}

8353
void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
B
bellard 已提交
8354
{
8355
    gen_intermediate_code_internal(env, tb, 1);
B
bellard 已提交
8356
}
A
aurel32 已提交
8357 8358 8359 8360 8361 8362

void gen_pc_load(CPUState *env, TranslationBlock *tb,
                unsigned long searched_pc, int pc_pos, void *puc)
{
    env->nip = gen_opc_pc[pc_pos];
}