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提交 9a64fbe4 编写于 作者: B bellard
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PowerPC system emulation (Jocelyn Mayer) - modified patch to use new TLB api 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@528 c046a42c-6fe2-441c-8c8c-71466251a162
上级 efe160c5
展开全部 隐藏空白更改
内联 并排
Showing with 4596 addition and 1429 deletion
target-ppc/cpu.h
浏览文件 @ 9a64fbe4
......@@ -25,6 +25,8 @@
#include "cpu-defs.h"
//#define USE_OPEN_FIRMWARE
/*** Sign extend constants ***/
/* 8 to 32 bits */
static inline int32_t s_ext8 (uint8_t value)
......@@ -54,56 +56,28 @@ static inline int32_t s_ext24 (uint32_t value)
#include "config.h"
#include <setjmp.h>
/* Floting point status and control register */
#define FPSCR_FX 31
#define FPSCR_FEX 30
#define FPSCR_VX 29
#define FPSCR_OX 28
#define FPSCR_UX 27
#define FPSCR_ZX 26
#define FPSCR_XX 25
#define FPSCR_VXSNAN 24
#define FPSCR_VXISI 26
#define FPSCR_VXIDI 25
#define FPSCR_VXZDZ 21
#define FPSCR_VXIMZ 20
/* Instruction types */
enum {
PPC_NONE = 0x0000,
PPC_INTEGER = 0x0001, /* CPU has integer operations instructions */
PPC_FLOAT = 0x0002, /* CPU has floating point operations instructions */
PPC_FLOW = 0x0004, /* CPU has flow control instructions */
PPC_MEM = 0x0008, /* CPU has virtual memory instructions */
PPC_RES = 0x0010, /* CPU has ld/st with reservation instructions */
PPC_CACHE = 0x0020, /* CPU has cache control instructions */
PPC_MISC = 0x0040, /* CPU has spr/msr access instructions */
PPC_EXTERN = 0x0080, /* CPU has external control instructions */
PPC_SEGMENT = 0x0100, /* CPU has memory segment instructions */
PPC_CACHE_OPT= 0x0200,
PPC_FLOAT_OPT= 0x0400,
PPC_MEM_OPT = 0x0800,
};
#define FPSCR_VXVC 18
#define FPSCR_FR 17
#define FPSCR_FI 16
#define FPSCR_FPRF 11
#define FPSCR_VXSOFT 9
#define FPSCR_VXSQRT 8
#define FPSCR_VXCVI 7
#define FPSCR_OE 6
#define FPSCR_UE 5
#define FPSCR_ZE 4
#define FPSCR_XE 3
#define FPSCR_NI 2
#define FPSCR_RN 0
#define fpscr_fx env->fpscr[FPSCR_FX]
#define fpscr_fex env->fpscr[FPSCR_FEX]
#define fpscr_vx env->fpscr[FPSCR_VX]
#define fpscr_ox env->fpscr[FPSCR_OX]
#define fpscr_ux env->fpscr[FPSCR_UX]
#define fpscr_zx env->fpscr[FPSCR_ZX]
#define fpscr_xx env->fpscr[FPSCR_XX]
#define fpscr_vsxnan env->fpscr[FPSCR_VXSNAN]
#define fpscr_vxisi env->fpscr[FPSCR_VXISI]
#define fpscr_vxidi env->fpscr[FPSCR_VXIDI]
#define fpscr_vxzdz env->fpscr[FPSCR_VXZDZ]
#define fpscr_vximz env->fpscr[FPSCR_VXIMZ]
#define fpscr_fr env->fpscr[FPSCR_FR]
#define fpscr_fi env->fpscr[FPSCR_FI]
#define fpscr_fprf env->fpscr[FPSCR_FPRF]
#define fpscr_vxsoft env->fpscr[FPSCR_VXSOFT]
#define fpscr_vxsqrt env->fpscr[FPSCR_VXSQRT]
#define fpscr_oe env->fpscr[FPSCR_OE]
#define fpscr_ue env->fpscr[FPSCR_UE]
#define fpscr_ze env->fpscr[FPSCR_ZE]
#define fpscr_xe env->fpscr[FPSCR_XE]
#define fpscr_ni env->fpscr[FPSCR_NI]
#define fpscr_rn env->fpscr[FPSCR_RN]
#define PPC_COMMON (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
/* PPC 740/745/750/755 (aka G3) has external access instructions */
#define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)
/* Supervisor mode registers */
/* Machine state register */
......@@ -139,26 +113,16 @@ static inline int32_t s_ext24 (uint32_t value)
#define msr_le env->msr[MSR_LE]
/* Segment registers */
typedef struct ppc_sr_t {
uint32_t t:1;
uint32_t ks:1;
uint32_t kp:1;
uint32_t n:1;
uint32_t res:4;
uint32_t vsid:24;
} ppc_sr_t;
typedef struct CPUPPCState {
/* general purpose registers */
uint32_t gpr[32];
/* floating point registers */
double fpr[32];
/* segment registers */
ppc_sr_t sr[16];
/* special purpose registers */
uint32_t spr[1024];
uint32_t sdr1;
uint32_t sr[16];
/* XER */
uint8_t xer[32];
uint8_t xer[4];
/* Reservation address */
uint32_t reserve;
/* machine state register */
......@@ -166,11 +130,20 @@ typedef struct CPUPPCState {
/* condition register */
uint8_t crf[8];
/* floating point status and control register */
uint8_t fpscr[32];
uint8_t fpscr[8];
uint32_t nip;
/* CPU exception code */
uint32_t exception;
/* special purpose registers */
uint32_t lr;
uint32_t ctr;
/* Time base */
uint32_t tb[2];
/* decrementer */
uint32_t decr;
/* BATs */
uint32_t DBAT[2][8];
uint32_t IBAT[2][8];
/* all others */
uint32_t spr[1024];
/* qemu dedicated */
/* temporary float registers */
double ft0;
......@@ -180,9 +153,14 @@ typedef struct CPUPPCState {
jmp_buf jmp_env;
int exception_index;
int error_code;
uint32_t exceptions; /* exception queue */
uint32_t errors[16];
int user_mode_only; /* user mode only simulation */
struct TranslationBlock *current_tb; /* currently executing TB */
/* soft mmu support */
/* 0 = kernel, 1 = user */
CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
/* user data */
void *opaque;
} CPUPPCState;
......@@ -198,107 +176,99 @@ int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
void *puc);
void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
void cpu_loop_exit(void);
void dump_stack (CPUPPCState *env);
uint32_t _load_xer (void);
void _store_xer (uint32_t value);
uint32_t _load_msr (void);
void _store_msr (uint32_t value);
void do_interrupt (CPUPPCState *env);
#define TARGET_PAGE_BITS 12
#include "cpu-all.h"
#define ugpr(n) (env->gpr[n])
#define fpr(n) (env->fpr[n])
#define fprd(n) (env->fpr[n])
#define fprs(n) ((float)env->fpr[n])
#define fpru(n) ((uint32_t)env->fpr[n])
#define fpri(n) ((int32_t)env->fpr[n])
#define SPR_ENCODE(sprn) \
(((sprn) >> 5) | (((sprn) & 0x1F) << 5))
/* User mode SPR */
#define spr(n) env->spr[n]
//#define XER spr[1]
#define XER env->xer
#define XER_SO 31
#define XER_OV 30
#define XER_CA 29
#define XER_BC 0
#define xer_so env->xer[XER_SO]
#define xer_ov env->xer[XER_OV]
#define xer_ca env->xer[XER_CA]
#define xer_bc env->xer[XER_BC]
#define xer_so env->xer[3]
#define xer_ov env->xer[2]
#define xer_ca env->xer[1]
#define xer_bc env->xer[0]
#define LR spr[SPR_ENCODE(8)]
#define CTR spr[SPR_ENCODE(9)]
#define XER SPR_ENCODE(1)
#define LR SPR_ENCODE(8)
#define CTR SPR_ENCODE(9)
/* VEA mode SPR */
#define V_TBL spr[SPR_ENCODE(268)]
#define V_TBU spr[SPR_ENCODE(269)]
#define V_TBL SPR_ENCODE(268)
#define V_TBU SPR_ENCODE(269)
/* supervisor mode SPR */
#define DSISR spr[SPR_ENCODE(18)]
#define DAR spr[SPR_ENCODE(19)]
#define DEC spr[SPR_ENCODE(22)]
#define SDR1 spr[SPR_ENCODE(25)]
typedef struct ppc_sdr1_t {
uint32_t htaborg:16;
uint32_t res:7;
uint32_t htabmask:9;
} ppc_sdr1_t;
#define SRR0 spr[SPR_ENCODE(26)]
#define SRR0_MASK 0xFFFFFFFC
#define SRR1 spr[SPR_ENCODE(27)]
#define SPRG0 spr[SPR_ENCODE(272)]
#define SPRG1 spr[SPR_ENCODE(273)]
#define SPRG2 spr[SPR_ENCODE(274)]
#define SPRG3 spr[SPR_ENCODE(275)]
#define EAR spr[SPR_ENCODE(282)]
typedef struct ppc_ear_t {
uint32_t e:1;
uint32_t res:25;
uint32_t rid:6;
} ppc_ear_t;
#define TBL spr[SPR_ENCODE(284)]
#define TBU spr[SPR_ENCODE(285)]
#define PVR spr[SPR_ENCODE(287)]
typedef struct ppc_pvr_t {
uint32_t version:16;
uint32_t revision:16;
} ppc_pvr_t;
#define IBAT0U spr[SPR_ENCODE(528)]
#define IBAT0L spr[SPR_ENCODE(529)]
#define IBAT1U spr[SPR_ENCODE(530)]
#define IBAT1L spr[SPR_ENCODE(531)]
#define IBAT2U spr[SPR_ENCODE(532)]
#define IBAT2L spr[SPR_ENCODE(533)]
#define IBAT3U spr[SPR_ENCODE(534)]
#define IBAT3L spr[SPR_ENCODE(535)]
#define DBAT0U spr[SPR_ENCODE(536)]
#define DBAT0L spr[SPR_ENCODE(537)]
#define DBAT1U spr[SPR_ENCODE(538)]
#define DBAT1L spr[SPR_ENCODE(539)]
#define DBAT2U spr[SPR_ENCODE(540)]
#define DBAT2L spr[SPR_ENCODE(541)]
#define DBAT3U spr[SPR_ENCODE(542)]
#define DBAT3L spr[SPR_ENCODE(543)]
typedef struct ppc_ubat_t {
uint32_t bepi:15;
uint32_t res:4;
uint32_t bl:11;
uint32_t vs:1;
uint32_t vp:1;
} ppc_ubat_t;
typedef struct ppc_lbat_t {
uint32_t brpn:15;
uint32_t res0:10;
uint32_t w:1;
uint32_t i:1;
uint32_t m:1;
uint32_t g:1;
uint32_t res1:1;
uint32_t pp:2;
} ppc_lbat_t;
#define DABR spr[SPR_ENCODE(1013)]
#define DSISR SPR_ENCODE(18)
#define DAR SPR_ENCODE(19)
#define DECR SPR_ENCODE(22)
#define SDR1 SPR_ENCODE(25)
#define SRR0 SPR_ENCODE(26)
#define SRR1 SPR_ENCODE(27)
#define SPRG0 SPR_ENCODE(272)
#define SPRG1 SPR_ENCODE(273)
#define SPRG2 SPR_ENCODE(274)
#define SPRG3 SPR_ENCODE(275)
#define SPRG4 SPR_ENCODE(276)
#define SPRG5 SPR_ENCODE(277)
#define SPRG6 SPR_ENCODE(278)
#define SPRG7 SPR_ENCODE(279)
#define ASR SPR_ENCODE(280)
#define EAR SPR_ENCODE(282)
#define O_TBL SPR_ENCODE(284)
#define O_TBU SPR_ENCODE(285)
#define PVR SPR_ENCODE(287)
#define IBAT0U SPR_ENCODE(528)
#define IBAT0L SPR_ENCODE(529)
#define IBAT1U SPR_ENCODE(530)
#define IBAT1L SPR_ENCODE(531)
#define IBAT2U SPR_ENCODE(532)
#define IBAT2L SPR_ENCODE(533)
#define IBAT3U SPR_ENCODE(534)
#define IBAT3L SPR_ENCODE(535)
#define DBAT0U SPR_ENCODE(536)
#define DBAT0L SPR_ENCODE(537)
#define DBAT1U SPR_ENCODE(538)
#define DBAT1L SPR_ENCODE(539)
#define DBAT2U SPR_ENCODE(540)
#define DBAT2L SPR_ENCODE(541)
#define DBAT3U SPR_ENCODE(542)
#define DBAT3L SPR_ENCODE(543)
#define IBAT4U SPR_ENCODE(560)
#define IBAT4L SPR_ENCODE(561)
#define IBAT5U SPR_ENCODE(562)
#define IBAT5L SPR_ENCODE(563)
#define IBAT6U SPR_ENCODE(564)
#define IBAT6L SPR_ENCODE(565)
#define IBAT7U SPR_ENCODE(566)
#define IBAT7L SPR_ENCODE(567)
#define DBAT4U SPR_ENCODE(568)
#define DBAT4L SPR_ENCODE(569)
#define DBAT5U SPR_ENCODE(570)
#define DBAT5L SPR_ENCODE(571)
#define DBAT6U SPR_ENCODE(572)
#define DBAT6L SPR_ENCODE(573)
#define DBAT7U SPR_ENCODE(574)
#define DBAT7L SPR_ENCODE(575)
#define DABR SPR_ENCODE(1013)
#define DABR_MASK 0xFFFFFFF8
typedef struct ppc_dabr_t {
uint32_t dab:29;
uint32_t bt:1;
uint32_t dw:1;
uint32_t dr:1;
} ppc_dabr_t;
#define FPECR spr[SPR_ENCODE(1022)]
#define PIR spr[SPR_ENCODE(1023)]
#define FPECR SPR_ENCODE(1022)
#define PIR SPR_ENCODE(1023)
#define TARGET_PAGE_BITS 12
#include "cpu-all.h"
......@@ -307,10 +277,30 @@ CPUPPCState *cpu_ppc_init(void);
int cpu_ppc_exec(CPUPPCState *s);
void cpu_ppc_close(CPUPPCState *s);
void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
void PPC_init_hw (CPUPPCState *env, uint32_t mem_size,
uint32_t kernel_addr, uint32_t kernel_size,
uint32_t stack_addr, int boot_device);
/* Exeptions */
/* Memory access type :
* may be needed for precise access rights control and precise exceptions.
*/
enum {
EXCP_NONE = 0x00,
/* 1 bit to define user level / supervisor access */
ACCESS_USER = 0x00,
ACCESS_SUPER = 0x01,
/* Type of instruction that generated the access */
ACCESS_CODE = 0x10, /* Code fetch access */
ACCESS_INT = 0x20, /* Integer load/store access */
ACCESS_FLOAT = 0x30, /* floating point load/store access */
ACCESS_RES = 0x40, /* load/store with reservation */
ACCESS_EXT = 0x50, /* external access */
ACCESS_CACHE = 0x60, /* Cache manipulation */
};
/*****************************************************************************/
/* Exceptions */
enum {
EXCP_NONE = -1,
/* PPC hardware exceptions : exception vector / 0x100 */
EXCP_RESET = 0x01, /* System reset */
EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */
......@@ -326,55 +316,80 @@ enum {
EXCP_SYSCALL = 0x0C, /* System call */
EXCP_TRACE = 0x0D, /* Trace exception (optional) */
EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */
#if 0
/* Exeption subtypes for EXCP_DSI */
EXCP_DSI_TRANSLATE = 0x10301, /* Data address can't be translated */
EXCP_DSI_NOTSUP = 0x10302, /* Access type not supported */
EXCP_DSI_PROT = 0x10303, /* Memory protection violation */
EXCP_DSI_EXTERNAL = 0x10304, /* External access disabled */
EXCP_DSI_DABR = 0x10305, /* Data address breakpoint */
/* Exeption subtypes for EXCP_ISI */
EXCP_ISI_TRANSLATE = 0x10401, /* Code address can't be translated */
EXCP_ISI_NOTSUP = 0x10402, /* Access type not supported */
EXCP_ISI_PROT = 0x10403, /* Memory protection violation */
EXCP_ISI_GUARD = 0x10404, /* Fetch into guarded memory */
/* Exeption subtypes for EXCP_ALIGN */
EXCP_ALIGN_FP = 0x10601, /* FP alignment exception */
EXCP_ALIGN_LST = 0x10602, /* Unaligned memory load/store */
EXCP_ALIGN_LE = 0x10603, /* Unaligned little-endian access */
EXCP_ALIGN_PROT = 0x10604, /* Access cross protection boundary */
EXCP_ALIGN_BAT = 0x10605, /* Access cross a BAT/seg boundary */
EXCP_ALIGN_CACHE = 0x10606, /* Impossible dcbz access */
/* Exeption subtypes for EXCP_PROGRAM */
/* MPC740/745/750 & IBM 750 */
EXCP_PERF = 0x0F, /* Performance monitor */
EXCP_IABR = 0x13, /* Instruction address breakpoint */
EXCP_SMI = 0x14, /* System management interrupt */
EXCP_THRM = 0x15, /* Thermal management interrupt */
/* MPC755 */
EXCP_TLBMISS = 0x10, /* Instruction TLB miss */
EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */
EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */
EXCP_PPC_MAX = 0x16,
/* Qemu exception */
EXCP_OFCALL = 0x20, /* Call open-firmware emulator */
EXCP_RTASCALL = 0x21, /* Call RTAS emulator */
/* Special cases where we want to stop translation */
EXCP_MTMSR = 0x104, /* mtmsr instruction: */
/* may change privilege level */
EXCP_BRANCH = 0x108, /* branch instruction */
EXCP_RFI = 0x10C, /* return from interrupt */
EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
};
/* Error codes */
enum {
/* Exception subtypes for EXCP_DSI */
EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */
EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */
EXCP_DSI_PROT = 0x03, /* Memory protection violation */
EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */
EXCP_DSI_DABR = 0x05, /* Data address breakpoint */
/* flags for EXCP_DSI */
EXCP_DSI_DIRECT = 0x10,
EXCP_DSI_STORE = 0x20,
EXCP_ECXW = 0x40,
/* Exception subtypes for EXCP_ISI */
EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */
EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */
EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */
EXCP_ISI_PROT = 0x04, /* Memory protection violation */
/* Exception subtypes for EXCP_ALIGN */
EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
/* Exception subtypes for EXCP_PROGRAM */
/* FP exceptions */
EXCP_FP_OX = 0x10701, /* FP overflow */
EXCP_FP_UX = 0x10702, /* FP underflow */
EXCP_FP_ZX = 0x10703, /* FP divide by zero */
EXCP_FP_XX = 0x10704, /* FP inexact */
EXCP_FP_VXNAN = 0x10705, /* FP invalid SNaN op */
EXCP_FP_VXISI = 0x10706, /* FP invalid infinite substraction */
EXCP_FP_VXIDI = 0x10707, /* FP invalid infinite divide */
EXCP_FP_VXZDZ = 0x10708, /* FP invalid zero divide */
EXCP_FP_VXIMZ = 0x10709, /* FP invalid infinite * zero */
EXCP_FP_VXVC = 0x1070A, /* FP invalid compare */
EXCP_FP_VXSOFT = 0x1070B, /* FP invalid operation */
EXCP_FP_VXSQRT = 0x1070C, /* FP invalid square root */
EXCP_FP_VXCVI = 0x1070D, /* FP invalid integer conversion */
EXCP_FP = 0x10,
EXCP_FP_OX = 0x01, /* FP overflow */
EXCP_FP_UX = 0x02, /* FP underflow */
EXCP_FP_ZX = 0x03, /* FP divide by zero */
EXCP_FP_XX = 0x04, /* FP inexact */
EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
/* Invalid instruction */
EXCP_INVAL_INVAL = 0x10711, /* Invalid instruction */
EXCP_INVAL_LSWX = 0x10712, /* Invalid lswx instruction */
EXCP_INVAL_SPR = 0x10713, /* Invalid SPR access */
EXCP_INVAL_FP = 0x10714, /* Unimplemented mandatory fp instr */
#endif
EXCP_INVAL = 0x70, /* Invalid instruction */
EXCP_INVAL = 0x20,
EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
/* Privileged instruction */
EXCP_PRIV = 0x71, /* Privileged instruction */
EXCP_PRIV = 0x30,
EXCP_PRIV_OPC = 0x01,
EXCP_PRIV_REG = 0x02,
/* Trap */
EXCP_TRAP = 0x72, /* Trap */
/* Special cases where we want to stop translation */
EXCP_MTMSR = 0x103, /* mtmsr instruction: */
/* may change privilege level */
EXCP_BRANCH = 0x104, /* branch instruction */
EXCP_TRAP = 0x40,
};
/*****************************************************************************/
#endif /* !defined (__CPU_PPC_H__) */
target-ppc/exec.h
浏览文件 @ 9a64fbe4
......@@ -41,126 +41,119 @@ register uint32_t T2 asm(AREG3);
#include "cpu.h"
#include "exec-all.h"
static inline uint8_t ld8 (uint32_t EA)
static inline uint32_t rotl (uint32_t i, int n)
{
return *((uint8_t *)EA);
return ((i << n) | (i >> (32 - n)));
}
static inline uint16_t ld16 (uint32_t EA)
{
return __be16_to_cpu(*((uint16_t *)EA));
}
/* XXX: move that to a generic header */
#if !defined(CONFIG_USER_ONLY)
static inline uint16_t ld16r (uint32_t EA)
{
return __le16_to_cpu(*((uint16_t *)EA));
}
#define ldul_user ldl_user
#define ldul_kernel ldl_kernel
static inline uint32_t ld32 (uint32_t EA)
{
return __be32_to_cpu(*((uint32_t *)EA));
}
static inline uint32_t ld32r (uint32_t EA)
{
return __le32_to_cpu(*((uint32_t *)EA));
}
#define ACCESS_TYPE 0
#define MEMSUFFIX _kernel
#define DATA_SIZE 1
#include "softmmu_header.h"
static inline uint64_t ld64 (uint32_t EA)
{
return __be64_to_cpu(*((uint64_t *)EA));
}
#define DATA_SIZE 2
#include "softmmu_header.h"
static inline uint64_t ld64r (uint32_t EA)
{
return __le64_to_cpu(*((uint64_t *)EA));
}
#define DATA_SIZE 4
#include "softmmu_header.h"
static inline void st8 (uint32_t EA, uint8_t data)
{
*((uint8_t *)EA) = data;
}
#define DATA_SIZE 8
#include "softmmu_header.h"
#undef ACCESS_TYPE
#undef MEMSUFFIX
static inline void st16 (uint32_t EA, uint16_t data)
{
*((uint16_t *)EA) = __cpu_to_be16(data);
}
#define ACCESS_TYPE 1
#define MEMSUFFIX _user
#define DATA_SIZE 1
#include "softmmu_header.h"
static inline void st16r (uint32_t EA, uint16_t data)
{
*((uint16_t *)EA) = __cpu_to_le16(data);
}
#define DATA_SIZE 2
#include "softmmu_header.h"
static inline void st32 (uint32_t EA, uint32_t data)
{
*((uint32_t *)EA) = __cpu_to_be32(data);
}
#define DATA_SIZE 4
#include "softmmu_header.h"
static inline void st32r (uint32_t EA, uint32_t data)
{
*((uint32_t *)EA) = __cpu_to_le32(data);
}
#define DATA_SIZE 8
#include "softmmu_header.h"
#undef ACCESS_TYPE
#undef MEMSUFFIX
static inline void st64 (uint32_t EA, uint64_t data)
{
*((uint64_t *)EA) = __cpu_to_be64(data);
}
/* these access are slower, they must be as rare as possible */
#define ACCESS_TYPE 2
#define MEMSUFFIX _data
#define DATA_SIZE 1
#include "softmmu_header.h"
static inline void st64r (uint32_t EA, uint64_t data)
{
*((uint64_t *)EA) = __cpu_to_le64(data);
}
#define DATA_SIZE 2
#include "softmmu_header.h"
static inline void set_CRn(int n, uint8_t value)
{
env->crf[n] = value;
}
#define DATA_SIZE 4
#include "softmmu_header.h"
static inline void set_carry (void)
{
xer_ca = 1;
}
#define DATA_SIZE 8
#include "softmmu_header.h"
#undef ACCESS_TYPE
#undef MEMSUFFIX
static inline void reset_carry (void)
{
xer_ca = 0;
}
#define ldub(p) ldub_data(p)
#define ldsb(p) ldsb_data(p)
#define lduw(p) lduw_data(p)
#define ldsw(p) ldsw_data(p)
#define ldl(p) ldl_data(p)
#define ldq(p) ldq_data(p)
static inline void set_overflow (void)
{
xer_so = 1;
xer_ov = 1;
}
#define stb(p, v) stb_data(p, v)
#define stw(p, v) stw_data(p, v)
#define stl(p, v) stl_data(p, v)
#define stq(p, v) stq_data(p, v)
static inline void reset_overflow (void)
{
xer_ov = 0;
}
#endif /* !defined(CONFIG_USER_ONLY) */
static inline uint32_t rotl (uint32_t i, int n)
{
return ((i << n) | (i >> (32 - n)));
}
int check_exception_state (CPUState *env);
void raise_exception (int exception_index);
void raise_exception_err (int exception_index, int error_code);
void do_queue_exception_err (uint32_t exception, int error_code);
void do_queue_exception (uint32_t exception);
void do_process_exceptions (void);
void do_check_exception_state (void);
uint32_t do_load_cr (void);
void do_store_cr (uint32_t crn, uint32_t value);
uint32_t do_load_xer (void);
void do_store_xer (uint32_t value);
uint32_t do_load_msr (void);
void do_store_msr (uint32_t msr_value);
void do_load_cr (void);
void do_store_cr (uint32_t mask);
void do_load_xer (void);
void do_store_xer (void);
void do_load_msr (void);
void do_store_msr (void);
void do_load_fpscr (void);
void do_store_fpscr (uint32_t mask);
int32_t do_sraw(int32_t Ta, uint32_t Tb);
void do_lmw (int reg, uint32_t src);
void do_stmw (int reg, uint32_t dest);
void do_lsw (uint32_t reg, int count, uint32_t src);
void do_stsw (uint32_t reg, int count, uint32_t dest);
void do_sraw(void);
void do_fctiw (void);
void do_fctiwz (void);
void do_fsqrt (void);
void do_fsqrts (void);
void do_fres (void);
void do_fsqrte (void);
void do_fsel (void);
void do_fcmpu (void);
void do_fcmpo (void);
void do_fabs (void);
void do_fnabs (void);
void do_dcbz (void);
void do_icbi (void);
void do_tlbia (void);
void do_tlbie (void);
void dump_rfi (void);
void dump_store_sr (int srnum);
void dump_store_ibat (int ul, int nr);
void dump_store_dbat (int ul, int nr);
void dump_store_tb (int ul);
void dump_update_tb(uint32_t param);
#endif /* !defined (__PPC_H__) */
target-ppc/helper.c
浏览文件 @ 9a64fbe4
此差异已折叠。
target-ppc/hw.c 0 → 100644
浏览文件 @ 9a64fbe4
此差异已折叠。
target-ppc/op.c
浏览文件 @ 9a64fbe4
此差异已折叠。
target-ppc/op_helper.c 0 → 100644
浏览文件 @ 9a64fbe4
/*
* PPC emulation helpers for qemu.
*
* Copyright (c) 2003 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <math.h>
#include "exec.h"
#if defined(CONFIG_USER_ONLY)
#define MEMSUFFIX _raw
#include "op_helper_mem.h"
#else
#define MEMSUFFIX _user
#include "op_helper_mem.h"
#define MEMSUFFIX _kernel
#include "op_helper_mem.h"
#endif
/*****************************************************************************/
/* Exceptions processing helpers */
void do_queue_exception_err (uint32_t exception, int error_code)
{
/* Queue real PPC exceptions */
if (exception < EXCP_PPC_MAX) {
env->exceptions |= 1 << exception;
env->errors[exception] = error_code;
} else {
/* Preserve compatibility with qemu core */
env->exceptions |= 1;
env->exception_index = exception;
env->error_code = error_code;
}
}
void do_queue_exception (uint32_t exception)
{
do_queue_exception_err(exception, 0);
}
void do_check_exception_state (void)
{
if ((env->exceptions & 1) == 1 || check_exception_state(env)) {
env->exceptions &= ~1;
cpu_loop_exit();
}
}
/*****************************************************************************/
/* Helpers for "fat" micro operations */
/* Special registers load and store */
void do_load_cr (void)
{
T0 = (env->crf[0] << 28) |
(env->crf[1] << 24) |
(env->crf[2] << 20) |
(env->crf[3] << 16) |
(env->crf[4] << 12) |
(env->crf[5] << 8) |
(env->crf[6] << 4) |
(env->crf[7] << 0);
}
void do_store_cr (uint32_t mask)
{
int i, sh;
for (i = 0, sh = 7; i < 8; i++, sh --) {
if (mask & (1 << sh))
env->crf[i] = (T0 >> (sh * 4)) & 0xF;
}
}
void do_load_xer (void)
{
T0 = (xer_so << XER_SO) |
(xer_ov << XER_OV) |
(xer_ca << XER_CA) |
(xer_bc << XER_BC);
}
void do_store_xer (void)
{
xer_so = (T0 >> XER_SO) & 0x01;
xer_ov = (T0 >> XER_OV) & 0x01;
xer_ca = (T0 >> XER_CA) & 0x01;
xer_bc = (T0 >> XER_BC) & 0x1f;
}
void do_load_msr (void)
{
T0 = (msr_pow << MSR_POW) |
(msr_ile << MSR_ILE) |
(msr_ee << MSR_EE) |
(msr_pr << MSR_PR) |
(msr_fp << MSR_FP) |
(msr_me << MSR_ME) |
(msr_fe0 << MSR_FE0) |
(msr_se << MSR_SE) |
(msr_be << MSR_BE) |
(msr_fe1 << MSR_FE1) |
(msr_ip << MSR_IP) |
(msr_ir << MSR_IR) |
(msr_dr << MSR_DR) |
(msr_ri << MSR_RI) |
(msr_le << MSR_LE);
}
void do_store_msr (void)
{
if (((T0 >> MSR_IR) & 0x01) != msr_ir ||
((T0 >> MSR_DR) & 0x01) != msr_dr ||
((T0 >> MSR_PR) & 0x01) != msr_pr) {
/* Flush all tlb when changing translation mode or privilege level */
do_tlbia();
}
#if 0
if ((T0 >> MSR_IP) & 0x01) {
printf("Halting CPU. Stop emulation\n");
do_queue_exception(EXCP_HLT);
cpu_loop_exit();
}
#endif
msr_pow = (T0 >> MSR_POW) & 0x03;
msr_ile = (T0 >> MSR_ILE) & 0x01;
msr_ee = (T0 >> MSR_EE) & 0x01;
msr_pr = (T0 >> MSR_PR) & 0x01;
msr_fp = (T0 >> MSR_FP) & 0x01;
msr_me = (T0 >> MSR_ME) & 0x01;
msr_fe0 = (T0 >> MSR_FE0) & 0x01;
msr_se = (T0 >> MSR_SE) & 0x01;
msr_be = (T0 >> MSR_BE) & 0x01;
msr_fe1 = (T0 >> MSR_FE1) & 0x01;
msr_ip = (T0 >> MSR_IP) & 0x01;
msr_ir = (T0 >> MSR_IR) & 0x01;
msr_dr = (T0 >> MSR_DR) & 0x01;
msr_ri = (T0 >> MSR_RI) & 0x01;
msr_le = (T0 >> MSR_LE) & 0x01;
}
/* shift right arithmetic helper */
void do_sraw (void)
{
int32_t ret;
xer_ca = 0;
if (T1 & 0x20) {
ret = (-1) * (T0 >> 31);
if (ret < 0)
xer_ca = 1;
} else {
ret = (int32_t)T0 >> (T1 & 0x1f);
if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0)
xer_ca = 1;
}
(int32_t)T0 = ret;
}
/* Floating point operations helpers */
void do_load_fpscr (void)
{
/* The 32 MSB of the target fpr are undefined.
* They'll be zero...
*/
union {
double d;
struct {
uint32_t u[2];
} s;
} u;
int i;
u.s.u[0] = 0;
u.s.u[1] = 0;
for (i = 0; i < 8; i++)
u.s.u[1] |= env->fpscr[i] << (4 * i);
FT0 = u.d;
}
void do_store_fpscr (uint32_t mask)
{
/*
* We use only the 32 LSB of the incoming fpr
*/
union {
double d;
struct {
uint32_t u[2];
} s;
} u;
int i;
u.d = FT0;
if (mask & 0x80)
env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[1] >> 28) & ~0x9);
for (i = 1; i < 7; i++) {
if (mask & (1 << (7 - i)))
env->fpscr[i] = (u.s.u[1] >> (4 * (7 - i))) & 0xF;
}
/* TODO: update FEX & VX */
/* Set rounding mode */
switch (env->fpscr[0] & 0x3) {
case 0:
/* Best approximation (round to nearest) */
fesetround(FE_TONEAREST);
break;
case 1:
/* Smaller magnitude (round toward zero) */
fesetround(FE_TOWARDZERO);
break;
case 2:
/* Round toward +infinite */
fesetround(FE_UPWARD);
break;
case 3:
/* Round toward -infinite */
fesetround(FE_DOWNWARD);
break;
}
}
void do_fctiw (void)
{
union {
double d;
uint64_t i;
} *p = (void *)&FT1;
if (FT0 > (double)0x7FFFFFFF)
p->i = 0x7FFFFFFFULL << 32;
else if (FT0 < -(double)0x80000000)
p->i = 0x80000000ULL << 32;
else
p->i = 0;
p->i |= (uint32_t)FT0;
FT0 = p->d;
}
void do_fctiwz (void)
{
union {
double d;
uint64_t i;
} *p = (void *)&FT1;
int cround = fegetround();
fesetround(FE_TOWARDZERO);
if (FT0 > (double)0x7FFFFFFF)
p->i = 0x7FFFFFFFULL << 32;
else if (FT0 < -(double)0x80000000)
p->i = 0x80000000ULL << 32;
else
p->i = 0;
p->i |= (uint32_t)FT0;
FT0 = p->d;
fesetround(cround);
}
void do_fsqrt (void)
{
FT0 = sqrt(FT0);
}
void do_fsqrts (void)
{
FT0 = (float)sqrt((float)FT0);
}
void do_fres (void)
{
FT0 = 1.0 / FT0;
}
void do_fsqrte (void)
{
FT0 = 1.0 / sqrt(FT0);
}
void do_fsel (void)
{
if (FT0 >= 0)
FT0 = FT2;
else
FT0 = FT1;
}
void do_fcmpu (void)
{
env->fpscr[4] &= ~0x1;
if (isnan(FT0) || isnan(FT1)) {
T0 = 0x01;
env->fpscr[4] |= 0x1;
env->fpscr[6] |= 0x1;
} else if (FT0 < FT1) {
T0 = 0x08;
} else if (FT0 > FT1) {
T0 = 0x04;
} else {
T0 = 0x02;
}
env->fpscr[3] |= T0;
}
void do_fcmpo (void)
{
env->fpscr[4] &= ~0x1;
if (isnan(FT0) || isnan(FT1)) {
T0 = 0x01;
env->fpscr[4] |= 0x1;
/* I don't know how to test "quiet" nan... */
if (0 /* || ! quiet_nan(...) */) {
env->fpscr[6] |= 0x1;
if (!(env->fpscr[1] & 0x8))
env->fpscr[4] |= 0x8;
} else {
env->fpscr[4] |= 0x8;
}
} else if (FT0 < FT1) {
T0 = 0x08;
} else if (FT0 > FT1) {
T0 = 0x04;
} else {
T0 = 0x02;
}
env->fpscr[3] |= T0;
}
void do_fabs (void)
{
FT0 = fabsl(FT0);
}
void do_fnabs (void)
{
FT0 = -fabsl(FT0);
}
/* Instruction cache invalidation helper */
void do_icbi (void)
{
// tb_invalidate_page(T0);
}
/* TLB invalidation helpers */
void do_tlbia (void)
{
tlb_flush(env);
}
void do_tlbie (void)
{
tlb_flush_page(env, T0);
}
/*****************************************************************************/
/* Special helpers for debug */
void dump_rfi (void)
{
#if 0
printf("Return from interrupt\n");
printf("nip=0x%08x LR=0x%08x CTR=0x%08x MSR=0x%08x\n",
env->nip, env->lr, env->ctr,
(msr_pow << MSR_POW) | (msr_ile << MSR_ILE) | (msr_ee << MSR_EE) |
(msr_pr << MSR_PR) | (msr_fp << MSR_FP) | (msr_me << MSR_ME) |
(msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) | (msr_be << MSR_BE) |
(msr_fe1 << MSR_FE1) | (msr_ip << MSR_IP) | (msr_ir << MSR_IR) |
(msr_dr << MSR_DR) | (msr_ri << MSR_RI) | (msr_le << MSR_LE));
{
int i;
for (i = 0; i < 32; i++) {
if ((i & 7) == 0)
printf("GPR%02d:", i);
printf(" %08x", env->gpr[i]);
if ((i & 7) == 7)
printf("\n");
}
printf("CR: 0x");
for (i = 0; i < 8; i++)
printf("%01x", env->crf[i]);
printf(" [");
for (i = 0; i < 8; i++) {
char a = '-';
if (env->crf[i] & 0x08)
a = 'L';
else if (env->crf[i] & 0x04)
a = 'G';
else if (env->crf[i] & 0x02)
a = 'E';
printf(" %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
}
printf(" ] ");
}
printf("TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
printf("SRR0 0x%08x SRR1 0x%08x\n", env->spr[SRR0], env->spr[SRR1]);
#endif
}
void dump_store_sr (int srnum)
{
#if 0
printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0);
#endif
}
static void _dump_store_bat (char ID, int ul, int nr)
{
printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n",
ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip);
}
void dump_store_ibat (int ul, int nr)
{
_dump_store_bat('I', ul, nr);
}
void dump_store_dbat (int ul, int nr)
{
_dump_store_bat('D', ul, nr);
}
void dump_store_tb (int ul)
{
printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0);
}
void dump_update_tb(uint32_t param)
{
#if 0
printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0);
#endif
}
target-ppc/op_helper_mem.h 0 → 100644
浏览文件 @ 9a64fbe4
void glue(do_lsw, MEMSUFFIX) (int dst)
{
uint32_t tmp;
int sh;
if (loglevel > 0) {
fprintf(logfile, "%s: addr=0x%08x count=%d reg=%d\n",
__func__, T0, T1, dst);
}
for (; T1 > 3; T1 -= 4, T0 += 4) {
ugpr(dst++) = glue(_ldl, MEMSUFFIX)((void *)T0, ACCESS_INT);
if (dst == 32)
dst = 0;
}
if (T1 > 0) {
tmp = 0;
for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) {
tmp |= glue(_ldub, MEMSUFFIX)((void *)T0, ACCESS_INT) << sh;
}
ugpr(dst) = tmp;
}
}
void glue(do_stsw, MEMSUFFIX) (int src)
{
int sh;
if (loglevel > 0) {
fprintf(logfile, "%s: addr=0x%08x count=%d reg=%d\n",
__func__, T0, T1, src);
}
for (; T1 > 3; T1 -= 4, T0 += 4) {
glue(_stl, MEMSUFFIX)((void *)T0, ugpr(src++), ACCESS_INT);
if (src == 32)
src = 0;
}
if (T1 > 0) {
for (sh = 24; T1 > 0; T1--, T0++, sh -= 8)
glue(_stb, MEMSUFFIX)((void *)T0, (ugpr(src) >> sh) & 0xFF,
ACCESS_INT);
}
}
#undef MEMSUFFIX
target-ppc/op_mem.h 0 → 100644
浏览文件 @ 9a64fbe4
/* External helpers */
void glue(do_lsw, MEMSUFFIX) (int dst);
void glue(do_stsw, MEMSUFFIX) (int src);
/* Internal helpers for sign extension and byte-reverse */
static inline uint32_t glue(_ld16x, MEMSUFFIX) (void *EA, int type)
{
return s_ext16(glue(_lduw, MEMSUFFIX)(EA, type));
}
static inline uint16_t glue(_ld16r, MEMSUFFIX) (void *EA, int type)
{
uint16_t tmp = glue(_lduw, MEMSUFFIX)(EA, type);
return ((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8);
}
static inline uint32_t glue(_ld32r, MEMSUFFIX) (void *EA, int type)
{
uint32_t tmp = glue(_ldl, MEMSUFFIX)(EA, type);
return ((tmp & 0xFF000000) >> 24) | ((tmp & 0x00FF0000) >> 8) |
((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24);
}
static inline void glue(_st16r, MEMSUFFIX) (void *EA, uint16_t data, int type)
{
uint16_t tmp = ((data & 0xFF00) >> 8) | ((data & 0x00FF) << 8);
glue(_stw, MEMSUFFIX)(EA, tmp, type);
}
static inline void glue(_st32r, MEMSUFFIX) (void *EA, uint32_t data, int type)
{
uint32_t tmp = ((data & 0xFF000000) >> 24) | ((data & 0x00FF0000) >> 8) |
((data & 0x0000FF00) << 8) | ((data & 0x000000FF) << 24);
glue(_stl, MEMSUFFIX)(EA, tmp, type);
}
/*** Integer load ***/
#define PPC_LD_OP(name, op) \
PPC_OP(glue(glue(l, name), MEMSUFFIX)) \
{ \
T1 = glue(op, MEMSUFFIX)((void *)T0, ACCESS_INT); \
RETURN(); \
}
#define PPC_ST_OP(name, op) \
PPC_OP(glue(glue(st, name), MEMSUFFIX)) \
{ \
glue(op, MEMSUFFIX)((void *)T0, T1, ACCESS_INT); \
RETURN(); \
}
PPC_LD_OP(bz, _ldub);
PPC_LD_OP(ha, _ld16x);
PPC_LD_OP(hz, _lduw);
PPC_LD_OP(wz, _ldl);
/*** Integer store ***/
PPC_ST_OP(b, _stb);
PPC_ST_OP(h, _stw);
PPC_ST_OP(w, _stl);
/*** Integer load and store with byte reverse ***/
PPC_LD_OP(hbr, _ld16r);
PPC_LD_OP(wbr, _ld32r);
PPC_ST_OP(hbr, _st16r);
PPC_ST_OP(wbr, _st32r);
/*** Integer load and store multiple ***/
PPC_OP(glue(lmw, MEMSUFFIX))
{
int dst = PARAM(1);
for (; dst < 32; dst++, T0 += 4) {
ugpr(dst) = glue(_ldl, MEMSUFFIX)((void *)T0, ACCESS_INT);
}
RETURN();
}
PPC_OP(glue(stmw, MEMSUFFIX))
{
int src = PARAM(1);
for (; src < 32; src++, T0 += 4) {
glue(_stl, MEMSUFFIX)((void *)T0, ugpr(src), ACCESS_INT);
}
RETURN();
}
/*** Integer load and store strings ***/
PPC_OP(glue(lswi, MEMSUFFIX))
{
glue(do_lsw, MEMSUFFIX)(PARAM(1));
RETURN();
}
/* PPC32 specification says we must generate an exception if
* rA is in the range of registers to be loaded.
* In an other hand, IBM says this is valid, but rA won't be loaded.
* For now, I'll follow the spec...
*/
PPC_OP(glue(lswx, MEMSUFFIX))
{
if (T1 > 0) {
if ((PARAM(1) < PARAM(2) && (PARAM(1) + T1) > PARAM(2)) ||
(PARAM(1) < PARAM(3) && (PARAM(1) + T1) > PARAM(3))) {
do_queue_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
do_process_exceptions();
} else {
glue(do_lsw, MEMSUFFIX)(PARAM(1));
}
}
RETURN();
}
PPC_OP(glue(stsw, MEMSUFFIX))
{
glue(do_stsw, MEMSUFFIX)(PARAM(1));
RETURN();
}
/*** Floating-point store ***/
#define PPC_STF_OP(name, op) \
PPC_OP(glue(glue(st, name), MEMSUFFIX)) \
{ \
glue(op, MEMSUFFIX)((void *)T0, FT1); \
RETURN(); \
}
PPC_STF_OP(fd, stfq);
PPC_STF_OP(fs, stfl);
/*** Floating-point load ***/
#define PPC_LDF_OP(name, op) \
PPC_OP(glue(glue(l, name), MEMSUFFIX)) \
{ \
FT1 = glue(op, MEMSUFFIX)((void *)T0); \
RETURN(); \
}
PPC_LDF_OP(fd, ldfq);
PPC_LDF_OP(fs, ldfl);
/* Store with reservation */
PPC_OP(glue(stwcx, MEMSUFFIX))
{
if (T0 & 0x03) {
do_queue_exception(EXCP_ALIGN);
do_process_exceptions();
} else {
if (regs->reserve != T0) {
env->crf[0] = xer_ov;
} else {
glue(_stl, MEMSUFFIX)((void *)T0, T1, ACCESS_RES);
env->crf[0] = xer_ov | 0x02;
}
}
regs->reserve = 0;
RETURN();
}
PPC_OP(glue(dcbz, MEMSUFFIX))
{
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x00), 0, ACCESS_INT);
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x04), 0, ACCESS_INT);
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x08), 0, ACCESS_INT);
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x0C), 0, ACCESS_INT);
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x10), 0, ACCESS_INT);
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x14), 0, ACCESS_INT);
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x18), 0, ACCESS_INT);
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x1C), 0, ACCESS_INT);
RETURN();
}
/* External access */
PPC_OP(glue(eciwx, MEMSUFFIX))
{
T1 = glue(_ldl, MEMSUFFIX)((void *)T0, ACCESS_EXT);
RETURN();
}
PPC_OP(glue(ecowx, MEMSUFFIX))
{
glue(_stl, MEMSUFFIX)((void *)T0, T1, ACCESS_EXT);
RETURN();
}
#undef MEMSUFFIX
target-ppc/op_template.h
浏览文件 @ 9a64fbe4
......@@ -18,56 +18,67 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* General purpose registers moves */
void OPPROTO glue(op_load_gpr_T0_gpr, REG)(void)
{
T0 = regs->gpr[REG];
RETURN();
}
void OPPROTO glue(op_load_gpr_T1_gpr, REG)(void)
{
T1 = regs->gpr[REG];
RETURN();
}
void OPPROTO glue(op_load_gpr_T2_gpr, REG)(void)
{
T2 = regs->gpr[REG];
RETURN();
}
void OPPROTO glue(op_store_T0_gpr_gpr, REG)(void)
{
regs->gpr[REG] = T0;
RETURN();
}
void OPPROTO glue(op_store_T1_gpr_gpr, REG)(void)
{
regs->gpr[REG] = T1;
RETURN();
}
void OPPROTO glue(op_store_T2_gpr_gpr, REG)(void)
{
regs->gpr[REG] = T2;
RETURN();
}
#if REG <= 7
/* Condition register moves */
void OPPROTO glue(op_load_crf_T0_crf, REG)(void)
{
T0 = regs->crf[REG];
RETURN();
}
void OPPROTO glue(op_load_crf_T1_crf, REG)(void)
{
T1 = regs->crf[REG];
RETURN();
}
void OPPROTO glue(op_store_T0_crf_crf, REG)(void)
{
regs->crf[REG] = T0;
RETURN();
}
void OPPROTO glue(op_store_T1_crf_crf, REG)(void)
{
regs->crf[REG] = T1;
RETURN();
}
/* Floating point condition and status register moves */
......@@ -117,8 +128,6 @@ void OPPROTO glue(op_clear_fpscr_fpscr, REG)(void)
#endif /* REG <= 7 */
/* float moves */
/* floating point registers moves */
void OPPROTO glue(op_load_fpr_FT0_fpr, REG)(void)
{
......@@ -156,4 +165,22 @@ void OPPROTO glue(op_store_FT2_fpr_fpr, REG)(void)
RETURN();
}
#if REG <= 15
/* Segment register moves */
void OPPROTO glue(op_load_sr, REG)(void)
{
T0 = env->sr[REG];
RETURN();
}
void OPPROTO glue(op_store_sr, REG)(void)
{
#if defined (DEBUG_OP)
dump_store_sr(REG);
#endif
env->sr[REG] = T0;
RETURN();
}
#endif
#undef REG
target-ppc/translate.c
浏览文件 @ 9a64fbe4
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