intel_dp.c 103.6 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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struct dp_link_dpll {
	int link_bw;
	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
	{ DP_LINK_BW_1_62,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ DP_LINK_BW_2_7,
		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_dp *intel_dp);
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static int
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
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	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
		max_link_bw = DP_LINK_BW_2_7;
		break;
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	default:
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		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
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		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static int
intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
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		target_clock = fixed_mode->clock;
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	}

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	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);

	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

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	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

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	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

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static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out);
static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *out);

static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	enum pipe pipe;

	/* modeset should have pipe */
	if (crtc)
		return to_intel_crtc(crtc)->pipe;

	/* init time, try to find a pipe with this port selected */
	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
		if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
			return pipe;
		if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
			return pipe;
	}

	/* shrug */
	return PIPE_A;
}

static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static u32 _pp_stat_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

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static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;

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	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
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}

static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;

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	return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
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}

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static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!is_edp(intel_dp))
		return;
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	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
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		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
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			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
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	}
}

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static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
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	uint32_t status;
	bool done;

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#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
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	if (has_aux_irq)
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		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
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					  msecs_to_jiffies_timeout(10));
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	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

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static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
				      int index)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	/* The clock divider is based off the hrawclk,
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	 * and would like to run at 2MHz. So, take the
	 * hrawclk value and divide by 2 and use that
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	 *
	 * Note that PCH attached eDP panels should use a 125MHz input
	 * clock divider.
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	 */
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	if (IS_VALLEYVIEW(dev)) {
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		return index ? 0 : 100;
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	} else if (intel_dig_port->port == PORT_A) {
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		if (index)
			return 0;
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		if (HAS_DDI(dev))
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			return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
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		else if (IS_GEN6(dev) || IS_GEN7(dev))
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			return 200; /* SNB & IVB eDP input clock at 400Mhz */
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		else
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			return 225; /* eDP input clock at 450Mhz */
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	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
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		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
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	} else if (HAS_PCH_SPLIT(dev)) {
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		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
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	} else {
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		return index ? 0 :intel_hrawclk(dev) / 2;
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	}
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}

static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
	uint32_t ch_data = ch_ctl + 4;
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	uint32_t aux_clock_divider;
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	int i, ret, recv_bytes;
	uint32_t status;
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	int try, precharge, clock = 0;
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	bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
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	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

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	intel_aux_display_runtime_get(dev_priv);

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	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
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		status = I915_READ_NOTRACE(ch_ctl);
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		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
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		ret = -EBUSY;
		goto out;
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	}

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	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

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	while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
				I915_WRITE(ch_data + i,
					   pack_aux(send + i, send_bytes - i));

			/* Send the command and wait for it to complete */
			I915_WRITE(ch_ctl,
				   DP_AUX_CH_CTL_SEND_BUSY |
				   (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
				   DP_AUX_CH_CTL_TIME_OUT_400us |
				   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
				   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
				   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

			if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
				      DP_AUX_CH_CTL_RECEIVE_ERROR))
				continue;
			if (status & DP_AUX_CH_CTL_DONE)
				break;
		}
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		if (status & DP_AUX_CH_CTL_DONE)
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			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
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		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
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		ret = -EBUSY;
		goto out;
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	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
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	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
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		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
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		ret = -EIO;
		goto out;
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	}
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	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
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	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
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		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
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		ret = -ETIMEDOUT;
		goto out;
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	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
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	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
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	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
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	intel_aux_display_runtime_put(dev_priv);
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	return ret;
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}

/* Write data to the aux channel in native mode */
static int
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intel_dp_aux_native_write(struct intel_dp *intel_dp,
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			  uint16_t address, uint8_t *send, int send_bytes)
{
	int ret;
	uint8_t	msg[20];
	int msg_bytes;
	uint8_t	ack;

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	if (WARN_ON(send_bytes > 16))
		return -E2BIG;

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	intel_dp_check_edp(intel_dp);
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	msg[0] = AUX_NATIVE_WRITE << 4;
	msg[1] = address >> 8;
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	msg[2] = address & 0xff;
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	msg[3] = send_bytes - 1;
	memcpy(&msg[4], send, send_bytes);
	msg_bytes = send_bytes + 4;
	for (;;) {
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		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
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		if (ret < 0)
			return ret;
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
			break;
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
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			return -EIO;
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	}
	return send_bytes;
}

/* Write a single byte to the aux channel in native mode */
static int
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intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
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			    uint16_t address, uint8_t byte)
{
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	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
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}

/* read bytes from a native aux channel */
static int
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intel_dp_aux_native_read(struct intel_dp *intel_dp,
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			 uint16_t address, uint8_t *recv, int recv_bytes)
{
	uint8_t msg[4];
	int msg_bytes;
	uint8_t reply[20];
	int reply_bytes;
	uint8_t ack;
	int ret;

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	if (WARN_ON(recv_bytes > 19))
		return -E2BIG;

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	intel_dp_check_edp(intel_dp);
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	msg[0] = AUX_NATIVE_READ << 4;
	msg[1] = address >> 8;
	msg[2] = address & 0xff;
	msg[3] = recv_bytes - 1;

	msg_bytes = 4;
	reply_bytes = recv_bytes + 1;

	for (;;) {
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		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
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				      reply, reply_bytes);
594 595 596
		if (ret == 0)
			return -EPROTO;
		if (ret < 0)
597 598 599 600 601 602 603 604 605
			return ret;
		ack = reply[0];
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
			memcpy(recv, reply + 1, ret - 1);
			return ret - 1;
		}
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
606
			return -EIO;
607 608 609 610
	}
}

static int
611 612
intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		    uint8_t write_byte, uint8_t *read_byte)
613
{
614
	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
C
Chris Wilson 已提交
615 616 617
	struct intel_dp *intel_dp = container_of(adapter,
						struct intel_dp,
						adapter);
618 619 620
	uint16_t address = algo_data->address;
	uint8_t msg[5];
	uint8_t reply[2];
621
	unsigned retry;
622 623 624 625
	int msg_bytes;
	int reply_bytes;
	int ret;

626
	intel_dp_check_edp(intel_dp);
627 628 629 630 631 632 633 634
	/* Set up the command byte */
	if (mode & MODE_I2C_READ)
		msg[0] = AUX_I2C_READ << 4;
	else
		msg[0] = AUX_I2C_WRITE << 4;

	if (!(mode & MODE_I2C_STOP))
		msg[0] |= AUX_I2C_MOT << 4;
635

636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656
	msg[1] = address >> 8;
	msg[2] = address;

	switch (mode) {
	case MODE_I2C_WRITE:
		msg[3] = 0;
		msg[4] = write_byte;
		msg_bytes = 5;
		reply_bytes = 1;
		break;
	case MODE_I2C_READ:
		msg[3] = 0;
		msg_bytes = 4;
		reply_bytes = 2;
		break;
	default:
		msg_bytes = 3;
		reply_bytes = 1;
		break;
	}

657 658 659 660 661 662
	/*
	 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
	 * required to retry at least seven times upon receiving AUX_DEFER
	 * before giving up the AUX transaction.
	 */
	for (retry = 0; retry < 7; retry++) {
663 664 665
		ret = intel_dp_aux_ch(intel_dp,
				      msg, msg_bytes,
				      reply, reply_bytes);
666
		if (ret < 0) {
667
			DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
668 669
			return ret;
		}
670 671 672 673 674 675 676 677 678 679 680

		switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
		case AUX_NATIVE_REPLY_ACK:
			/* I2C-over-AUX Reply field is only valid
			 * when paired with AUX ACK.
			 */
			break;
		case AUX_NATIVE_REPLY_NACK:
			DRM_DEBUG_KMS("aux_ch native nack\n");
			return -EREMOTEIO;
		case AUX_NATIVE_REPLY_DEFER:
681 682 683 684 685 686 687 688 689 690 691 692
			/*
			 * For now, just give more slack to branch devices. We
			 * could check the DPCD for I2C bit rate capabilities,
			 * and if available, adjust the interval. We could also
			 * be more careful with DP-to-Legacy adapters where a
			 * long legacy cable may force very low I2C bit rates.
			 */
			if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			    DP_DWN_STRM_PORT_PRESENT)
				usleep_range(500, 600);
			else
				usleep_range(300, 400);
693 694 695 696 697 698 699
			continue;
		default:
			DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
				  reply[0]);
			return -EREMOTEIO;
		}

700 701 702 703 704 705 706
		switch (reply[0] & AUX_I2C_REPLY_MASK) {
		case AUX_I2C_REPLY_ACK:
			if (mode == MODE_I2C_READ) {
				*read_byte = reply[1];
			}
			return reply_bytes - 1;
		case AUX_I2C_REPLY_NACK:
707
			DRM_DEBUG_KMS("aux_i2c nack\n");
708 709
			return -EREMOTEIO;
		case AUX_I2C_REPLY_DEFER:
710
			DRM_DEBUG_KMS("aux_i2c defer\n");
711 712 713
			udelay(100);
			break;
		default:
714
			DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
715 716 717
			return -EREMOTEIO;
		}
	}
718 719 720

	DRM_ERROR("too many retries, giving up\n");
	return -EREMOTEIO;
721 722 723
}

static int
C
Chris Wilson 已提交
724
intel_dp_i2c_init(struct intel_dp *intel_dp,
725
		  struct intel_connector *intel_connector, const char *name)
726
{
727 728
	int	ret;

Z
Zhenyu Wang 已提交
729
	DRM_DEBUG_KMS("i2c_init %s\n", name);
C
Chris Wilson 已提交
730 731 732 733
	intel_dp->algo.running = false;
	intel_dp->algo.address = 0;
	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;

734
	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
C
Chris Wilson 已提交
735 736
	intel_dp->adapter.owner = THIS_MODULE;
	intel_dp->adapter.class = I2C_CLASS_DDC;
737
	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
C
Chris Wilson 已提交
738 739 740 741
	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
	intel_dp->adapter.algo_data = &intel_dp->algo;
	intel_dp->adapter.dev.parent = &intel_connector->base.kdev;

742 743
	ironlake_edp_panel_vdd_on(intel_dp);
	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
744
	ironlake_edp_panel_vdd_off(intel_dp, false);
745
	return ret;
746 747
}

748 749 750 751 752
static void
intel_dp_set_clock(struct intel_encoder *encoder,
		   struct intel_crtc_config *pipe_config, int link_bw)
{
	struct drm_device *dev = encoder->base.dev;
753 754
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
755 756

	if (IS_G4X(dev)) {
757 758
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
759 760 761
	} else if (IS_HASWELL(dev)) {
		/* Haswell has special-purpose DP DDI clocks. */
	} else if (HAS_PCH_SPLIT(dev)) {
762 763
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
764
	} else if (IS_VALLEYVIEW(dev)) {
765 766
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
767
	}
768 769 770 771 772 773 774 775 776

	if (divisor && count) {
		for (i = 0; i < count; i++) {
			if (link_bw == divisor[i].link_bw) {
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
777 778 779
	}
}

P
Paulo Zanoni 已提交
780
bool
781 782
intel_dp_compute_config(struct intel_encoder *encoder,
			struct intel_crtc_config *pipe_config)
783
{
784
	struct drm_device *dev = encoder->base.dev;
785
	struct drm_i915_private *dev_priv = dev->dev_private;
786 787
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
788
	enum port port = dp_to_dig_port(intel_dp)->port;
789
	struct intel_crtc *intel_crtc = encoder->new_crtc;
790
	struct intel_connector *intel_connector = intel_dp->attached_connector;
791
	int lane_count, clock;
792
	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
C
Chris Wilson 已提交
793
	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
794
	int bpp, mode_rate;
795
	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
796
	int link_avail, link_clock;
797

798
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
799 800
		pipe_config->has_pch_encoder = true;

801
	pipe_config->has_dp_encoder = true;
802

803 804 805
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
806 807 808 809
		if (!HAS_PCH_SPLIT(dev))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
810 811
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
812 813
	}

814
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
815 816
		return false;

817 818
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max bw %02x pixel clock %iKHz\n",
819 820
		      max_lane_count, bws[max_clock],
		      adjusted_mode->crtc_clock);
821

822 823
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
824
	bpp = pipe_config->pipe_bpp;
825 826 827
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
		DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
			      dev_priv->vbt.edp_bpp);
828
		bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
829
	}
830

831
	for (; bpp >= 6*3; bpp -= 2*3) {
832 833
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
834 835 836 837 838 839 840 841 842 843 844 845 846

		for (clock = 0; clock <= max_clock; clock++) {
			for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
847

848
	return false;
849

850
found:
851 852 853 854 855 856
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
857
		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
858 859 860 861 862
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
		else
			intel_dp->color_range = 0;
	}

863
	if (intel_dp->color_range)
864
		pipe_config->limited_color_range = true;
865

866 867
	intel_dp->link_bw = bws[clock];
	intel_dp->lane_count = lane_count;
868
	pipe_config->pipe_bpp = bpp;
869
	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
870

871 872
	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
		      intel_dp->link_bw, intel_dp->lane_count,
873
		      pipe_config->port_clock, bpp);
874 875
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
876

877
	intel_link_compute_m_n(bpp, lane_count,
878 879
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
880
			       &pipe_config->dp_m_n);
881

882 883
	intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);

884
	return true;
885 886
}

887
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
888
{
889 890 891
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	struct drm_device *dev = crtc->base.dev;
892 893 894
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

895
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
896 897 898
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

899
	if (crtc->config.port_clock == 162000) {
900 901 902 903
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
904
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
905
		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
906 907
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
908
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
909
	}
910

911 912 913 914 915 916
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

917
static void intel_dp_mode_set(struct intel_encoder *encoder)
918
{
919
	struct drm_device *dev = encoder->base.dev;
920
	struct drm_i915_private *dev_priv = dev->dev_private;
921
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
922
	enum port port = dp_to_dig_port(intel_dp)->port;
923 924
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
925

926
	/*
K
Keith Packard 已提交
927
	 * There are four kinds of DP registers:
928 929
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
930 931
	 * 	SNB CPU
	 *	IVB CPU
932 933 934 935 936 937 938 939 940 941
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
942

943 944 945 946
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
947

948 949
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
950
	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
951

952 953
	if (intel_dp->has_audio) {
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
954
				 pipe_name(crtc->pipe));
C
Chris Wilson 已提交
955
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
956
		intel_write_eld(&encoder->base, adjusted_mode);
957
	}
958

959
	/* Split out the IBX/CPU vs CPT settings */
960

961
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
962 963 964 965 966 967
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

968
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
969 970
			intel_dp->DP |= DP_ENHANCED_FRAMING;

971
		intel_dp->DP |= crtc->pipe << 29;
972
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
973
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
974
			intel_dp->DP |= intel_dp->color_range;
975 976 977 978 979 980 981

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

982
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
983 984
			intel_dp->DP |= DP_ENHANCED_FRAMING;

985
		if (crtc->pipe == 1)
986 987 988
			intel_dp->DP |= DP_PIPEB_SELECT;
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
989
	}
990

991
	if (port == PORT_A && !IS_VALLEYVIEW(dev))
992
		ironlake_set_pll_cpu_edp(intel_dp);
993 994
}

995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006
#define IDLE_ON_MASK		(PP_ON | 0 	  | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | 0 	  | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)

#define IDLE_OFF_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_OFF_VALUE		(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

#define IDLE_CYCLE_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
				       u32 mask,
				       u32 value)
1007
{
1008
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1009
	struct drm_i915_private *dev_priv = dev->dev_private;
1010 1011
	u32 pp_stat_reg, pp_ctrl_reg;

1012 1013
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1014

1015
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1016 1017 1018
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
1019

1020
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1021
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1022 1023
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1024
	}
1025
}
1026

1027 1028 1029 1030
static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
	ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1031 1032
}

1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045
static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
	ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
}

static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
	ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}


1046 1047 1048 1049
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1050
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1051
{
1052 1053 1054
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1055

1056
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1057 1058 1059
	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
1060 1061
}

1062
void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1063
{
1064
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1065 1066
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1067
	u32 pp_stat_reg, pp_ctrl_reg;
1068

1069 1070
	if (!is_edp(intel_dp))
		return;
1071
	DRM_DEBUG_KMS("Turn eDP VDD on\n");
1072

1073 1074 1075 1076
	WARN(intel_dp->want_panel_vdd,
	     "eDP VDD already requested on\n");

	intel_dp->want_panel_vdd = true;
1077

1078 1079 1080 1081 1082
	if (ironlake_edp_have_panel_vdd(intel_dp)) {
		DRM_DEBUG_KMS("eDP VDD already on\n");
		return;
	}

1083 1084 1085
	if (!ironlake_edp_have_panel_power(intel_dp))
		ironlake_wait_panel_power_cycle(intel_dp);

1086
	pp = ironlake_get_pp_control(intel_dp);
1087
	pp |= EDP_FORCE_VDD;
1088

1089 1090
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1091 1092 1093 1094 1095

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1096 1097 1098 1099
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
	if (!ironlake_edp_have_panel_power(intel_dp)) {
1100
		DRM_DEBUG_KMS("eDP was not running\n");
1101 1102
		msleep(intel_dp->panel_power_up_delay);
	}
1103 1104
}

1105
static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1106
{
1107
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1108 1109
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1110
	u32 pp_stat_reg, pp_ctrl_reg;
1111

1112 1113
	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));

1114
	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1115
		pp = ironlake_get_pp_control(intel_dp);
1116 1117
		pp &= ~EDP_FORCE_VDD;

1118 1119
		pp_stat_reg = _pp_ctrl_reg(intel_dp);
		pp_ctrl_reg = _pp_stat_reg(intel_dp);
1120 1121 1122

		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1123

1124 1125 1126
		/* Make sure sequencer is idle before allowing subsequent activity */
		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1127
		msleep(intel_dp->panel_power_down_delay);
1128 1129
	}
}
1130

1131 1132 1133 1134
static void ironlake_panel_vdd_work(struct work_struct *__work)
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);
1135
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1136

1137
	mutex_lock(&dev->mode_config.mutex);
1138
	ironlake_panel_vdd_off_sync(intel_dp);
1139
	mutex_unlock(&dev->mode_config.mutex);
1140 1141
}

1142
void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1143
{
1144 1145
	if (!is_edp(intel_dp))
		return;
1146

1147 1148
	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1149

1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162
	intel_dp->want_panel_vdd = false;

	if (sync) {
		ironlake_panel_vdd_off_sync(intel_dp);
	} else {
		/*
		 * Queue the timer to fire a long
		 * time from now (relative to the power down delay)
		 * to keep the panel power up across a sequence of operations
		 */
		schedule_delayed_work(&intel_dp->panel_vdd_work,
				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
	}
1163 1164
}

1165
void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1166
{
1167
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1168
	struct drm_i915_private *dev_priv = dev->dev_private;
1169
	u32 pp;
1170
	u32 pp_ctrl_reg;
1171

1172
	if (!is_edp(intel_dp))
1173
		return;
1174 1175 1176 1177 1178

	DRM_DEBUG_KMS("Turn eDP power on\n");

	if (ironlake_edp_have_panel_power(intel_dp)) {
		DRM_DEBUG_KMS("eDP power already on\n");
1179
		return;
1180
	}
1181

1182
	ironlake_wait_panel_power_cycle(intel_dp);
1183

1184
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1185
	pp = ironlake_get_pp_control(intel_dp);
1186 1187 1188
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
1189 1190
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1191
	}
1192

1193
	pp |= POWER_TARGET_ON;
1194 1195 1196
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1197 1198
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1199

1200
	ironlake_wait_panel_on(intel_dp);
1201

1202 1203
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1204 1205
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1206
	}
1207 1208
}

1209
void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1210
{
1211
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1212
	struct drm_i915_private *dev_priv = dev->dev_private;
1213
	u32 pp;
1214
	u32 pp_ctrl_reg;
1215

1216 1217
	if (!is_edp(intel_dp))
		return;
1218

1219
	DRM_DEBUG_KMS("Turn eDP power off\n");
1220

1221
	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1222

1223
	pp = ironlake_get_pp_control(intel_dp);
1224 1225 1226
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1227

1228
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1229 1230 1231

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1232

1233 1234
	intel_dp->want_panel_vdd = false;

1235
	ironlake_wait_panel_off(intel_dp);
1236 1237
}

1238
void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1239
{
1240 1241
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1242
	struct drm_i915_private *dev_priv = dev->dev_private;
1243
	int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1244
	u32 pp;
1245
	u32 pp_ctrl_reg;
1246

1247 1248 1249
	if (!is_edp(intel_dp))
		return;

1250
	DRM_DEBUG_KMS("\n");
1251 1252 1253 1254 1255 1256
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1257
	msleep(intel_dp->backlight_on_delay);
1258
	pp = ironlake_get_pp_control(intel_dp);
1259
	pp |= EDP_BLC_ENABLE;
1260

1261
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1262 1263 1264

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1265 1266

	intel_panel_enable_backlight(dev, pipe);
1267 1268
}

1269
void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1270
{
1271
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1272 1273
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1274
	u32 pp_ctrl_reg;
1275

1276 1277 1278
	if (!is_edp(intel_dp))
		return;

1279 1280
	intel_panel_disable_backlight(dev);

1281
	DRM_DEBUG_KMS("\n");
1282
	pp = ironlake_get_pp_control(intel_dp);
1283
	pp &= ~EDP_BLC_ENABLE;
1284

1285
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1286 1287 1288

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1289
	msleep(intel_dp->backlight_off_delay);
1290
}
1291

1292
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1293
{
1294 1295 1296
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1297 1298 1299
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1300 1301 1302
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1303 1304
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1305 1306 1307 1308 1309 1310 1311 1312 1313
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
1314 1315
	POSTING_READ(DP_A);
	udelay(200);
1316 1317
}

1318
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1319
{
1320 1321 1322
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1323 1324 1325
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1326 1327 1328
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1329
	dpa_ctl = I915_READ(DP_A);
1330 1331 1332 1333 1334 1335 1336
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
1337
	dpa_ctl &= ~DP_PLL_ENABLE;
1338
	I915_WRITE(DP_A, dpa_ctl);
1339
	POSTING_READ(DP_A);
1340 1341 1342
	udelay(200);
}

1343
/* If the sink supports it, try to set the power state appropriately */
1344
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
		ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
						  DP_SET_POWER_D3);
		if (ret != 1)
			DRM_DEBUG_DRIVER("failed to write sink power state\n");
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
			ret = intel_dp_aux_native_write_1(intel_dp,
							  DP_SET_POWER,
							  DP_SET_POWER_D0);
			if (ret == 1)
				break;
			msleep(1);
		}
	}
}

1373 1374
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
1375
{
1376
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1377
	enum port port = dp_to_dig_port(intel_dp)->port;
1378 1379 1380 1381 1382 1383 1384
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 tmp = I915_READ(intel_dp->output_reg);

	if (!(tmp & DP_PORT_EN))
		return false;

1385
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1386
		*pipe = PORT_TO_PIPE_CPT(tmp);
1387
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415
		*pipe = PORT_TO_PIPE(tmp);
	} else {
		u32 trans_sel;
		u32 trans_dp;
		int i;

		switch (intel_dp->output_reg) {
		case PCH_DP_B:
			trans_sel = TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			trans_sel = TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			trans_sel = TRANS_DP_PORT_SEL_D;
			break;
		default:
			return true;
		}

		for_each_pipe(i) {
			trans_dp = I915_READ(TRANS_DP_CTL(i));
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
				*pipe = i;
				return true;
			}
		}

1416 1417 1418
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
	}
1419

1420 1421
	return true;
}
1422

1423 1424 1425 1426 1427
static void intel_dp_get_config(struct intel_encoder *encoder,
				struct intel_crtc_config *pipe_config)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
1428 1429 1430 1431
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1432
	int dotclock;
1433

1434 1435 1436 1437 1438 1439
	if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
		tmp = I915_READ(intel_dp->output_reg);
		if (tmp & DP_SYNC_HS_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1440

1441 1442 1443 1444 1445 1446 1447 1448 1449 1450
		if (tmp & DP_SYNC_VS_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1451

1452 1453 1454 1455 1456
		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
1457 1458

	pipe_config->adjusted_mode.flags |= flags;
1459

1460 1461 1462 1463
	pipe_config->has_dp_encoder = true;

	intel_dp_get_m_n(crtc, pipe_config);

1464
	if (port == PORT_A) {
1465 1466 1467 1468 1469
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
1470 1471 1472 1473 1474 1475 1476

	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
					    &pipe_config->dp_m_n);

	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

1477
	pipe_config->adjusted_mode.crtc_clock = dotclock;
1478 1479
}

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static bool is_edp_psr(struct drm_device *dev)
1481
{
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	struct drm_i915_private *dev_priv = dev->dev_private;

	return dev_priv->psr.sink_support;
1485 1486
}

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static bool intel_edp_is_psr_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1491
	if (!HAS_PSR(dev))
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		return false;

1494
	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
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}

static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
				    struct edp_vsc_psr *vsc_psr)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
	uint32_t *data = (uint32_t *) vsc_psr;
	unsigned int i;

	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
	   the video DIP being updated before program video DIP data buffer
	   registers for DIP being updated. */
	I915_WRITE(ctl_reg, 0);
	POSTING_READ(ctl_reg);

	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
		if (i < sizeof(struct edp_vsc_psr))
			I915_WRITE(data_reg + i, *data++);
		else
			I915_WRITE(data_reg + i, 0);
	}

	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
	POSTING_READ(ctl_reg);
}

static void intel_edp_psr_setup(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_vsc_psr psr_vsc;

	if (intel_dp->psr_setup_done)
		return;

	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
	memset(&psr_vsc, 0, sizeof(psr_vsc));
	psr_vsc.sdp_header.HB0 = 0;
	psr_vsc.sdp_header.HB1 = 0x7;
	psr_vsc.sdp_header.HB2 = 0x2;
	psr_vsc.sdp_header.HB3 = 0x8;
	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);

	/* Avoid continuous PSR exit by masking memup and hpd */
1544
	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
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1545 1546 1547 1548 1549 1550 1551 1552 1553
		   EDP_PSR_DEBUG_MASK_HPD);

	intel_dp->psr_setup_done = true;
}

static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
1554
	uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
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	int precharge = 0x3;
	int msg_size = 5;       /* Header(4) + Message(1) */

	/* Enable PSR in sink */
	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
		intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
					    DP_PSR_ENABLE &
					    ~DP_PSR_MAIN_LINK_ACTIVE);
	else
		intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
					    DP_PSR_ENABLE |
					    DP_PSR_MAIN_LINK_ACTIVE);

	/* Setup AUX registers */
1569 1570 1571
	I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
	I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
	I915_WRITE(EDP_PSR_AUX_CTL(dev),
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		   DP_AUX_CH_CTL_TIME_OUT_400us |
		   (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
}

static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t max_sleep_time = 0x1f;
	uint32_t idle_frames = 1;
	uint32_t val = 0x0;

	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
		val |= EDP_PSR_LINK_STANDBY;
		val |= EDP_PSR_TP2_TP3_TIME_0us;
		val |= EDP_PSR_TP1_TIME_0us;
		val |= EDP_PSR_SKIP_AUX_EXIT;
	} else
		val |= EDP_PSR_LINK_DISABLE;

1594
	I915_WRITE(EDP_PSR_CTL(dev), val |
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		   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
		   EDP_PSR_ENABLE);
}

1601 1602 1603 1604 1605 1606 1607 1608 1609 1610
static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;

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	dev_priv->psr.source_ok = false;

1613
	if (!HAS_PSR(dev)) {
1614 1615 1616 1617 1618 1619 1620 1621 1622 1623
		DRM_DEBUG_KMS("PSR not supported on this platform\n");
		return false;
	}

	if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
	    (dig_port->port != PORT_A)) {
		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
		return false;
	}

1624 1625 1626 1627 1628
	if (!i915_enable_psr) {
		DRM_DEBUG_KMS("PSR disable by flag\n");
		return false;
	}

1629 1630 1631 1632 1633 1634 1635
	crtc = dig_port->base.base.crtc;
	if (crtc == NULL) {
		DRM_DEBUG_KMS("crtc not active for PSR\n");
		return false;
	}

	intel_crtc = to_intel_crtc(crtc);
1636
	if (!intel_crtc_active(crtc)) {
1637 1638 1639 1640
		DRM_DEBUG_KMS("crtc not active for PSR\n");
		return false;
	}

1641
	obj = to_intel_framebuffer(crtc->fb)->obj;
1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658
	if (obj->tiling_mode != I915_TILING_X ||
	    obj->fence_reg == I915_FENCE_REG_NONE) {
		DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
		return false;
	}

	if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
		return false;
	}

	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
	    S3D_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
		return false;
	}

1659
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1660 1661 1662 1663
		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
		return false;
	}

R
Rodrigo Vivi 已提交
1664
	dev_priv->psr.source_ok = true;
1665 1666 1667
	return true;
}

1668
static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
R
Rodrigo Vivi 已提交
1669 1670 1671
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

1672 1673
	if (!intel_edp_psr_match_conditions(intel_dp) ||
	    intel_edp_is_psr_enabled(dev))
R
Rodrigo Vivi 已提交
1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685
		return;

	/* Setup PSR once */
	intel_edp_psr_setup(intel_dp);

	/* Enable PSR on the panel */
	intel_edp_psr_enable_sink(intel_dp);

	/* Enable PSR on the host */
	intel_edp_psr_enable_source(intel_dp);
}

1686 1687 1688 1689 1690 1691 1692 1693 1694
void intel_edp_psr_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (intel_edp_psr_match_conditions(intel_dp) &&
	    !intel_edp_is_psr_enabled(dev))
		intel_edp_psr_do_enable(intel_dp);
}

R
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1695 1696 1697 1698 1699 1700 1701 1702
void intel_edp_psr_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!intel_edp_is_psr_enabled(dev))
		return;

1703 1704
	I915_WRITE(EDP_PSR_CTL(dev),
		   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
R
Rodrigo Vivi 已提交
1705 1706

	/* Wait till PSR is idle */
1707
	if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
R
Rodrigo Vivi 已提交
1708 1709 1710 1711
		       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
		DRM_ERROR("Timed out waiting for PSR Idle State\n");
}

1712 1713 1714 1715 1716 1717 1718 1719 1720
void intel_edp_psr_update(struct drm_device *dev)
{
	struct intel_encoder *encoder;
	struct intel_dp *intel_dp = NULL;

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
		if (encoder->type == INTEL_OUTPUT_EDP) {
			intel_dp = enc_to_intel_dp(&encoder->base);

R
Rodrigo Vivi 已提交
1721
			if (!is_edp_psr(dev))
1722 1723 1724 1725 1726 1727 1728 1729 1730 1731
				return;

			if (!intel_edp_psr_match_conditions(intel_dp))
				intel_edp_psr_disable(intel_dp);
			else
				if (!intel_edp_is_psr_enabled(dev))
					intel_edp_psr_do_enable(intel_dp);
		}
}

1732
static void intel_disable_dp(struct intel_encoder *encoder)
1733
{
1734
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1735 1736
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct drm_device *dev = encoder->base.dev;
1737 1738 1739 1740

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
	ironlake_edp_panel_vdd_on(intel_dp);
1741
	ironlake_edp_backlight_off(intel_dp);
1742
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1743
	ironlake_edp_panel_off(intel_dp);
1744 1745

	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1746
	if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1747
		intel_dp_link_down(intel_dp);
1748 1749
}

1750
static void intel_post_disable_dp(struct intel_encoder *encoder)
1751
{
1752
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1753
	enum port port = dp_to_dig_port(intel_dp)->port;
1754
	struct drm_device *dev = encoder->base.dev;
1755

1756
	if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1757
		intel_dp_link_down(intel_dp);
1758 1759
		if (!IS_VALLEYVIEW(dev))
			ironlake_edp_pll_off(intel_dp);
1760
	}
1761 1762
}

1763
static void intel_enable_dp(struct intel_encoder *encoder)
1764
{
1765 1766 1767 1768
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1769

1770 1771
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
1772

1773
	ironlake_edp_panel_vdd_on(intel_dp);
1774
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1775
	intel_dp_start_link_train(intel_dp);
1776
	ironlake_edp_panel_on(intel_dp);
1777
	ironlake_edp_panel_vdd_off(intel_dp, true);
1778
	intel_dp_complete_link_train(intel_dp);
1779
	intel_dp_stop_link_train(intel_dp);
1780
}
1781

1782 1783
static void g4x_enable_dp(struct intel_encoder *encoder)
{
1784 1785
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

1786
	intel_enable_dp(encoder);
1787
	ironlake_edp_backlight_on(intel_dp);
1788
}
1789

1790 1791
static void vlv_enable_dp(struct intel_encoder *encoder)
{
1792 1793 1794
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	ironlake_edp_backlight_on(intel_dp);
1795 1796
}

1797
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1798 1799 1800 1801 1802 1803 1804 1805 1806
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

	if (dport->port == PORT_A)
		ironlake_edp_pll_on(intel_dp);
}

static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1807
{
1808
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1809
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1810
	struct drm_device *dev = encoder->base.dev;
1811
	struct drm_i915_private *dev_priv = dev->dev_private;
1812 1813 1814
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	int port = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
1815
	struct edp_power_seq power_seq;
1816
	u32 val;
1817

1818
	mutex_lock(&dev_priv->dpio_lock);
1819

1820
	val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
1821 1822 1823 1824 1825 1826
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
1827 1828 1829
	vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
	vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
1830

1831 1832
	mutex_unlock(&dev_priv->dpio_lock);

1833 1834 1835 1836 1837
	/* init power sequencer on this pipe and port */
	intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
						      &power_seq);

1838 1839 1840
	intel_enable_dp(encoder);

	vlv_wait_port_ready(dev_priv, port);
1841 1842
}

1843
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1844 1845 1846 1847
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1848 1849
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
1850
	int port = vlv_dport_to_channel(dport);
1851
	int pipe = intel_crtc->pipe;
1852 1853

	/* Program Tx lane resets to default */
1854
	mutex_lock(&dev_priv->dpio_lock);
1855
	vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
1856 1857
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
1858
	vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
1859 1860 1861 1862 1863 1864
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
1865 1866 1867
	vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
1868
	mutex_unlock(&dev_priv->dpio_lock);
1869 1870 1871
}

/*
1872 1873
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
1874 1875
 */
static bool
1876 1877
intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
			       uint8_t *recv, int recv_bytes)
1878
{
1879 1880
	int ret, i;

1881 1882 1883 1884
	/*
	 * Sinks are *supposed* to come up within 1ms from an off state,
	 * but we're also supposed to retry 3 times per the spec.
	 */
1885
	for (i = 0; i < 3; i++) {
1886 1887 1888
		ret = intel_dp_aux_native_read(intel_dp, address, recv,
					       recv_bytes);
		if (ret == recv_bytes)
1889 1890 1891
			return true;
		msleep(1);
	}
1892

1893
	return false;
1894 1895 1896 1897 1898 1899 1900
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
1901
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1902
{
1903 1904
	return intel_dp_aux_native_read_retry(intel_dp,
					      DP_LANE0_1_STATUS,
1905
					      link_status,
1906
					      DP_LINK_STATUS_SIZE);
1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926
}

#if 0
static char	*voltage_names[] = {
	"0.4V", "0.6V", "0.8V", "1.2V"
};
static char	*pre_emph_names[] = {
	"0dB", "3.5dB", "6dB", "9.5dB"
};
static char	*link_train_names[] = {
	"pattern 1", "pattern 2", "idle", "off"
};
#endif

/*
 * These are source-specific values; current Intel hardware supports
 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 */

static uint8_t
K
Keith Packard 已提交
1927
intel_dp_voltage_max(struct intel_dp *intel_dp)
1928
{
1929
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1930
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
1931

1932 1933
	if (IS_VALLEYVIEW(dev))
		return DP_TRAIN_VOLTAGE_SWING_1200;
1934
	else if (IS_GEN7(dev) && port == PORT_A)
K
Keith Packard 已提交
1935
		return DP_TRAIN_VOLTAGE_SWING_800;
1936
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
K
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1937 1938 1939 1940 1941 1942 1943 1944
		return DP_TRAIN_VOLTAGE_SWING_1200;
	else
		return DP_TRAIN_VOLTAGE_SWING_800;
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
1945
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1946
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
1947

1948
	if (HAS_DDI(dev)) {
1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
1972
	} else if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
1994 1995 1996
	}
}

1997 1998 1999 2000 2001
static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2002 2003
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dport->base.base.crtc);
2004 2005 2006
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
2007
	int port = vlv_dport_to_channel(dport);
2008
	int pipe = intel_crtc->pipe;
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
	case DP_TRAIN_PRE_EMPHASIS_0:
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_1200:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

2083
	mutex_lock(&dev_priv->dpio_lock);
2084 2085 2086
	vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
2087
			 uniqtranscale_reg_value);
2088 2089 2090 2091
	vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
2092
	mutex_unlock(&dev_priv->dpio_lock);
2093 2094 2095 2096

	return 0;
}

2097
static void
J
Jani Nikula 已提交
2098 2099
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
2100 2101 2102 2103
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
2104 2105
	uint8_t voltage_max;
	uint8_t preemph_max;
2106

2107
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
2108 2109
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2110 2111 2112 2113 2114 2115 2116

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
2117
	voltage_max = intel_dp_voltage_max(intel_dp);
2118 2119
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2120

K
Keith Packard 已提交
2121 2122 2123
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2124 2125

	for (lane = 0; lane < 4; lane++)
2126
		intel_dp->train_set[lane] = v | p;
2127 2128 2129
}

static uint32_t
2130
intel_gen4_signal_levels(uint8_t train_set)
2131
{
2132
	uint32_t	signal_levels = 0;
2133

2134
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
2149
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

2167 2168 2169 2170
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
2171 2172 2173
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
2174
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2175 2176 2177 2178
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2179
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2180 2181
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2182
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2183 2184
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2185
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2186 2187
	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2188
	default:
2189 2190 2191
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2192 2193 2194
	}
}

K
Keith Packard 已提交
2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

2226 2227
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
static uint32_t
2228
intel_hsw_signal_levels(uint8_t train_set)
2229
{
2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
		return DDI_BUF_EMP_400MV_9_5DB_HSW;
2241

2242 2243 2244 2245 2246 2247
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_HSW;
2248

2249 2250 2251 2252 2253 2254 2255 2256
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_HSW;
	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_HSW;
2257 2258 2259
	}
}

2260 2261 2262 2263 2264
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2265
	enum port port = intel_dig_port->port;
2266 2267 2268 2269
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t signal_levels, mask;
	uint8_t train_set = intel_dp->train_set[0];

2270
	if (HAS_DDI(dev)) {
2271 2272
		signal_levels = intel_hsw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
2273 2274 2275
	} else if (IS_VALLEYVIEW(dev)) {
		signal_levels = intel_vlv_signal_levels(intel_dp);
		mask = 0;
2276
	} else if (IS_GEN7(dev) && port == PORT_A) {
2277 2278
		signal_levels = intel_gen7_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2279
	} else if (IS_GEN6(dev) && port == PORT_A) {
2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291
		signal_levels = intel_gen6_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
		signal_levels = intel_gen4_signal_levels(train_set);
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	*DP = (*DP & ~mask) | signal_levels;
}

2292
static bool
C
Chris Wilson 已提交
2293
intel_dp_set_link_train(struct intel_dp *intel_dp,
2294
			uint32_t *DP,
2295
			uint8_t dp_train_pat)
2296
{
2297 2298
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2299
	struct drm_i915_private *dev_priv = dev->dev_private;
2300
	enum port port = intel_dig_port->port;
2301 2302
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;
2303

2304
	if (HAS_DDI(dev)) {
2305
		uint32_t temp = I915_READ(DP_TP_CTL(port));
2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
2328
		I915_WRITE(DP_TP_CTL(port), temp);
2329

2330
	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2331
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
2332 2333 2334

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
2335
			*DP |= DP_LINK_TRAIN_OFF_CPT;
2336 2337
			break;
		case DP_TRAINING_PATTERN_1:
2338
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
2339 2340
			break;
		case DP_TRAINING_PATTERN_2:
2341
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2342 2343 2344
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
2345
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2346 2347 2348 2349
			break;
		}

	} else {
2350
		*DP &= ~DP_LINK_TRAIN_MASK;
2351 2352 2353

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
2354
			*DP |= DP_LINK_TRAIN_OFF;
2355 2356
			break;
		case DP_TRAINING_PATTERN_1:
2357
			*DP |= DP_LINK_TRAIN_PAT_1;
2358 2359
			break;
		case DP_TRAINING_PATTERN_2:
2360
			*DP |= DP_LINK_TRAIN_PAT_2;
2361 2362 2363
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
2364
			*DP |= DP_LINK_TRAIN_PAT_2;
2365 2366 2367 2368
			break;
		}
	}

2369
	I915_WRITE(intel_dp->output_reg, *DP);
C
Chris Wilson 已提交
2370
	POSTING_READ(intel_dp->output_reg);
2371

2372 2373
	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2374
	    DP_TRAINING_PATTERN_DISABLE) {
2375 2376 2377 2378 2379 2380
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
2381
	}
2382

2383 2384 2385 2386
	ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
					buf, len);

	return ret == len;
2387 2388
}

2389 2390 2391 2392
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
			uint8_t dp_train_pat)
{
2393
	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2394 2395 2396 2397 2398 2399
	intel_dp_set_signal_levels(intel_dp, DP);
	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
J
Jani Nikula 已提交
2400
			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	intel_get_adjust_train(intel_dp, link_status);
	intel_dp_set_signal_levels(intel_dp, DP);

	I915_WRITE(intel_dp->output_reg, *DP);
	POSTING_READ(intel_dp->output_reg);

	ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
					intel_dp->train_set,
					intel_dp->lane_count);

	return ret == intel_dp->lane_count;
}

2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

2451
/* Enable corresponding port and start training pattern 1 */
2452
void
2453
intel_dp_start_link_train(struct intel_dp *intel_dp)
2454
{
2455
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2456
	struct drm_device *dev = encoder->dev;
2457 2458
	int i;
	uint8_t voltage;
2459
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
2460
	uint32_t DP = intel_dp->DP;
2461
	uint8_t link_config[2];
2462

P
Paulo Zanoni 已提交
2463
	if (HAS_DDI(dev))
2464 2465
		intel_ddi_prepare_link_retrain(encoder);

2466
	/* Write the link configuration data */
2467 2468 2469 2470 2471 2472 2473 2474 2475
	link_config[0] = intel_dp->link_bw;
	link_config[1] = intel_dp->lane_count;
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
	intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2476 2477

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
2478

2479 2480 2481 2482 2483 2484 2485 2486
	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp, &DP,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

2487
	voltage = 0xff;
2488 2489
	voltage_tries = 0;
	loop_tries = 0;
2490
	for (;;) {
2491
		uint8_t link_status[DP_LINK_STATUS_SIZE];
2492

2493
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2494 2495
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
2496
			break;
2497
		}
2498

2499
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2500
			DRM_DEBUG_KMS("clock recovery OK\n");
2501 2502 2503 2504 2505 2506
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2507
				break;
2508
		if (i == intel_dp->lane_count) {
2509 2510
			++loop_tries;
			if (loop_tries == 5) {
2511
				DRM_ERROR("too many full retries, give up\n");
2512 2513
				break;
			}
2514 2515 2516
			intel_dp_reset_link_train(intel_dp, &DP,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
2517 2518 2519
			voltage_tries = 0;
			continue;
		}
2520

2521
		/* Check to see if we've tried the same voltage 5 times */
2522
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2523
			++voltage_tries;
2524
			if (voltage_tries == 5) {
2525
				DRM_ERROR("too many voltage retries, give up\n");
2526 2527 2528 2529 2530
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2531

2532 2533 2534 2535 2536
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
2537 2538
	}

2539 2540 2541
	intel_dp->DP = DP;
}

2542
void
2543 2544 2545
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
2546
	int tries, cr_tries;
2547 2548
	uint32_t DP = intel_dp->DP;

2549
	/* channel equalization */
2550 2551 2552 2553 2554 2555 2556
	if (!intel_dp_set_link_train(intel_dp, &DP,
				     DP_TRAINING_PATTERN_2 |
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

2557
	tries = 0;
2558
	cr_tries = 0;
2559 2560
	channel_eq = false;
	for (;;) {
2561
		uint8_t link_status[DP_LINK_STATUS_SIZE];
2562

2563 2564 2565 2566 2567 2568
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			intel_dp_link_down(intel_dp);
			break;
		}

2569
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2570 2571
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
2572
			break;
2573
		}
2574

2575
		/* Make sure clock is still ok */
2576
		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2577
			intel_dp_start_link_train(intel_dp);
2578 2579 2580
			intel_dp_set_link_train(intel_dp, &DP,
						DP_TRAINING_PATTERN_2 |
						DP_LINK_SCRAMBLING_DISABLE);
2581 2582 2583 2584
			cr_tries++;
			continue;
		}

2585
		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2586 2587 2588
			channel_eq = true;
			break;
		}
2589

2590 2591 2592 2593
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
2594 2595 2596
			intel_dp_set_link_train(intel_dp, &DP,
						DP_TRAINING_PATTERN_2 |
						DP_LINK_SCRAMBLING_DISABLE);
2597 2598 2599 2600
			tries = 0;
			cr_tries++;
			continue;
		}
2601

2602 2603 2604 2605 2606
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
2607
		++tries;
2608
	}
2609

2610 2611 2612 2613
	intel_dp_set_idle_link_train(intel_dp);

	intel_dp->DP = DP;

2614
	if (channel_eq)
M
Masanari Iida 已提交
2615
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2616

2617 2618 2619 2620
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
2621
	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2622
				DP_TRAINING_PATTERN_DISABLE);
2623 2624 2625
}

static void
C
Chris Wilson 已提交
2626
intel_dp_link_down(struct intel_dp *intel_dp)
2627
{
2628
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2629
	enum port port = intel_dig_port->port;
2630
	struct drm_device *dev = intel_dig_port->base.base.dev;
2631
	struct drm_i915_private *dev_priv = dev->dev_private;
2632 2633
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
C
Chris Wilson 已提交
2634
	uint32_t DP = intel_dp->DP;
2635

2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650
	/*
	 * DDI code has a strict mode set sequence and we should try to respect
	 * it, otherwise we might hang the machine in many different ways. So we
	 * really should be disabling the port only on a complete crtc_disable
	 * sequence. This function is just called under two conditions on DDI
	 * code:
	 * - Link train failed while doing crtc_enable, and on this case we
	 *   really should respect the mode set sequence and wait for a
	 *   crtc_disable.
	 * - Someone turned the monitor off and intel_dp_check_link_status
	 *   called us. We don't need to disable the whole port on this case, so
	 *   when someone turns the monitor on again,
	 *   intel_ddi_prepare_link_retrain will take care of redoing the link
	 *   train.
	 */
P
Paulo Zanoni 已提交
2651
	if (HAS_DDI(dev))
2652 2653
		return;

2654
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2655 2656
		return;

2657
	DRM_DEBUG_KMS("\n");
2658

2659
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2660
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
2661
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2662 2663
	} else {
		DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
2664
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2665
	}
2666
	POSTING_READ(intel_dp->output_reg);
2667

2668 2669
	/* We don't really know why we're doing this */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
2670

2671
	if (HAS_PCH_IBX(dev) &&
2672
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2673
		struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2674

2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
2689 2690 2691 2692
		if (WARN_ON(crtc == NULL)) {
			/* We should never try to disable a port without a crtc
			 * attached. For paranoia keep the code around for a
			 * bit. */
2693 2694 2695
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
2696
			intel_wait_for_vblank(dev, intel_crtc->pipe);
2697 2698
	}

2699
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
2700 2701
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
2702
	msleep(intel_dp->panel_power_down_delay);
2703 2704
}

2705 2706
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
2707
{
R
Rodrigo Vivi 已提交
2708 2709 2710 2711
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

2712 2713
	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];

2714
	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2715 2716
					   sizeof(intel_dp->dpcd)) == 0)
		return false; /* aux transfer failed */
2717

2718 2719 2720 2721
	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
			   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);

2722 2723 2724
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

2725 2726
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2727 2728 2729 2730
	if (is_edp(intel_dp)) {
		intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
					       intel_dp->psr_dpcd,
					       sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
2731 2732
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
2733
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
2734
		}
2735 2736
	}

2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

	if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
					   intel_dp->downstream_ports,
					   DP_MAX_DOWNSTREAM_PORTS) == 0)
		return false; /* downstream port status fetch failed */

	return true;
2750 2751
}

2752 2753 2754 2755 2756 2757 2758 2759
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

D
Daniel Vetter 已提交
2760 2761
	ironlake_edp_panel_vdd_on(intel_dp);

2762 2763 2764 2765 2766 2767 2768
	if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

	if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
D
Daniel Vetter 已提交
2769 2770

	ironlake_edp_panel_vdd_off(intel_dp, false);
2771 2772
}

2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_aux_native_read_retry(intel_dp,
					     DP_DEVICE_SERVICE_IRQ_VECTOR,
					     sink_irq_vector, 1);
	if (!ret)
		return false;

	return true;
}

static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
2791
	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2792 2793
}

2794 2795 2796 2797 2798 2799 2800 2801 2802
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */

P
Paulo Zanoni 已提交
2803
void
C
Chris Wilson 已提交
2804
intel_dp_check_link_status(struct intel_dp *intel_dp)
2805
{
2806
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2807
	u8 sink_irq_vector;
2808
	u8 link_status[DP_LINK_STATUS_SIZE];
2809

2810
	if (!intel_encoder->connectors_active)
2811
		return;
2812

2813
	if (WARN_ON(!intel_encoder->base.crtc))
2814 2815
		return;

2816
	/* Try to read receiver status if the link appears to be up */
2817
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
C
Chris Wilson 已提交
2818
		intel_dp_link_down(intel_dp);
2819 2820 2821
		return;
	}

2822
	/* Now read the DPCD to see if it's actually running */
2823
	if (!intel_dp_get_dpcd(intel_dp)) {
2824 2825 2826 2827
		intel_dp_link_down(intel_dp);
		return;
	}

2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		intel_dp_aux_native_write_1(intel_dp,
					    DP_DEVICE_SERVICE_IRQ_VECTOR,
					    sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

2842
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2843
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2844
			      drm_get_encoder_name(&intel_encoder->base));
2845 2846
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
2847
		intel_dp_stop_link_train(intel_dp);
2848
	}
2849 2850
}

2851
/* XXX this is probably wrong for multiple downstream ports */
2852
static enum drm_connector_status
2853
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2854
{
2855 2856 2857 2858 2859 2860 2861 2862
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2863
		return connector_status_connected;
2864 2865

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
2866 2867
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2868
		uint8_t reg;
2869
		if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2870
						    &reg, 1))
2871
			return connector_status_unknown;
2872 2873
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
2874 2875 2876 2877
	}

	/* If no HPD, poke DDC gently */
	if (drm_probe_ddc(&intel_dp->adapter))
2878
		return connector_status_connected;
2879 2880

	/* Well we tried, say unknown for unreliable port types */
2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
2893 2894 2895

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2896
	return connector_status_disconnected;
2897 2898
}

2899
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2900
ironlake_dp_detect(struct intel_dp *intel_dp)
2901
{
2902
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2903 2904
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2905 2906
	enum drm_connector_status status;

2907 2908
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
2909
		status = intel_panel_detect(dev);
2910 2911 2912 2913
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}
2914

2915 2916 2917
	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		return connector_status_disconnected;

2918
	return intel_dp_detect_dpcd(intel_dp);
2919 2920
}

2921
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2922
g4x_dp_detect(struct intel_dp *intel_dp)
2923
{
2924
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2925
	struct drm_i915_private *dev_priv = dev->dev_private;
2926
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2927
	uint32_t bit;
2928

2929 2930 2931 2932 2933 2934 2935 2936 2937 2938
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

2939 2940
	switch (intel_dig_port->port) {
	case PORT_B:
2941
		bit = PORTB_HOTPLUG_LIVE_STATUS;
2942
		break;
2943
	case PORT_C:
2944
		bit = PORTC_HOTPLUG_LIVE_STATUS;
2945
		break;
2946
	case PORT_D:
2947
		bit = PORTD_HOTPLUG_LIVE_STATUS;
2948 2949 2950 2951 2952
		break;
	default:
		return connector_status_unknown;
	}

2953
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2954 2955
		return connector_status_disconnected;

2956
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
2957 2958
}

2959 2960 2961
static struct edid *
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
{
2962
	struct intel_connector *intel_connector = to_intel_connector(connector);
2963

2964 2965 2966 2967
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
2968 2969
			return NULL;

J
Jani Nikula 已提交
2970
		return drm_edid_duplicate(intel_connector->edid);
2971
	}
2972

2973
	return drm_get_edid(connector, adapter);
2974 2975 2976 2977 2978
}

static int
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
{
2979
	struct intel_connector *intel_connector = to_intel_connector(connector);
2980

2981 2982 2983 2984 2985 2986 2987 2988
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
			return 0;

		return intel_connector_update_modes(connector,
						    intel_connector->edid);
2989 2990
	}

2991
	return intel_ddc_get_modes(connector, adapter);
2992 2993
}

Z
Zhenyu Wang 已提交
2994 2995 2996 2997
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2998 2999
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3000
	struct drm_device *dev = connector->dev;
Z
Zhenyu Wang 已提交
3001 3002 3003
	enum drm_connector_status status;
	struct edid *edid = NULL;

3004 3005 3006
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector));

Z
Zhenyu Wang 已提交
3007 3008 3009 3010 3011 3012
	intel_dp->has_audio = false;

	if (HAS_PCH_SPLIT(dev))
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
3013

Z
Zhenyu Wang 已提交
3014 3015 3016
	if (status != connector_status_connected)
		return status;

3017 3018
	intel_dp_probe_oui(intel_dp);

3019 3020
	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3021
	} else {
3022
		edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3023 3024 3025 3026
		if (edid) {
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
			kfree(edid);
		}
Z
Zhenyu Wang 已提交
3027 3028
	}

3029 3030
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Z
Zhenyu Wang 已提交
3031
	return connector_status_connected;
3032 3033 3034 3035
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
3036
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3037
	struct intel_connector *intel_connector = to_intel_connector(connector);
3038
	struct drm_device *dev = connector->dev;
3039
	int ret;
3040 3041 3042 3043

	/* We should parse the EDID data and find out if it has an audio sink
	 */

3044
	ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3045
	if (ret)
3046 3047
		return ret;

3048
	/* if eDP has no EDID, fall back to fixed mode */
3049
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3050
		struct drm_display_mode *mode;
3051 3052
		mode = drm_mode_duplicate(dev,
					  intel_connector->panel.fixed_mode);
3053
		if (mode) {
3054 3055 3056 3057 3058
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
3059 3060
}

3061 3062 3063 3064 3065 3066 3067
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct edid *edid;
	bool has_audio = false;

3068
	edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3069 3070 3071 3072 3073 3074 3075 3076
	if (edid) {
		has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}

	return has_audio;
}

3077 3078 3079 3080 3081
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
3082
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
3083
	struct intel_connector *intel_connector = to_intel_connector(connector);
3084 3085
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3086 3087
	int ret;

3088
	ret = drm_object_property_set_value(&connector->base, property, val);
3089 3090 3091
	if (ret)
		return ret;

3092
	if (property == dev_priv->force_audio_property) {
3093 3094 3095 3096
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
3097 3098
			return 0;

3099
		intel_dp->force_audio = i;
3100

3101
		if (i == HDMI_AUDIO_AUTO)
3102 3103
			has_audio = intel_dp_detect_audio(connector);
		else
3104
			has_audio = (i == HDMI_AUDIO_ON);
3105 3106

		if (has_audio == intel_dp->has_audio)
3107 3108
			return 0;

3109
		intel_dp->has_audio = has_audio;
3110 3111 3112
		goto done;
	}

3113
	if (property == dev_priv->broadcast_rgb_property) {
3114 3115 3116
		bool old_auto = intel_dp->color_range_auto;
		uint32_t old_range = intel_dp->color_range;

3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
			break;
		default:
			return -EINVAL;
		}
3132 3133 3134 3135 3136

		if (old_auto == intel_dp->color_range_auto &&
		    old_range == intel_dp->color_range)
			return 0;

3137 3138 3139
		goto done;
	}

3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

3156 3157 3158
	return -EINVAL;

done:
3159 3160
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
3161 3162 3163 3164

	return 0;
}

3165
static void
3166
intel_dp_connector_destroy(struct drm_connector *connector)
3167
{
3168
	struct intel_connector *intel_connector = to_intel_connector(connector);
3169

3170 3171 3172
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

3173 3174 3175
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3176
		intel_panel_fini(&intel_connector->panel);
3177

3178
	drm_connector_cleanup(connector);
3179
	kfree(connector);
3180 3181
}

P
Paulo Zanoni 已提交
3182
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3183
{
3184 3185
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
3186
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3187 3188 3189

	i2c_del_adapter(&intel_dp->adapter);
	drm_encoder_cleanup(encoder);
3190 3191
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3192
		mutex_lock(&dev->mode_config.mutex);
3193
		ironlake_panel_vdd_off_sync(intel_dp);
3194
		mutex_unlock(&dev->mode_config.mutex);
3195
	}
3196
	kfree(intel_dig_port);
3197 3198
}

3199
static const struct drm_connector_funcs intel_dp_connector_funcs = {
3200
	.dpms = intel_connector_dpms,
3201 3202
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
3203
	.set_property = intel_dp_set_property,
3204
	.destroy = intel_dp_connector_destroy,
3205 3206 3207 3208 3209
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
3210
	.best_encoder = intel_best_encoder,
3211 3212 3213
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3214
	.destroy = intel_dp_encoder_destroy,
3215 3216
};

3217
static void
3218
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3219
{
3220
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3221

3222
	intel_dp_check_link_status(intel_dp);
3223
}
3224

3225 3226
/* Return which DP Port should be selected for Transcoder DP control */
int
3227
intel_trans_dp_port_sel(struct drm_crtc *crtc)
3228 3229
{
	struct drm_device *dev = crtc->dev;
3230 3231
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
3232

3233 3234
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
3235

3236 3237
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
3238
			return intel_dp->output_reg;
3239
	}
C
Chris Wilson 已提交
3240

3241 3242 3243
	return -1;
}

3244
/* check the VBT to see whether the eDP is on DP-D port */
3245
bool intel_dpd_is_edp(struct drm_device *dev)
3246 3247
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3248
	union child_device_config *p_child;
3249 3250
	int i;

3251
	if (!dev_priv->vbt.child_dev_num)
3252 3253
		return false;

3254 3255
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
3256

3257 3258
		if (p_child->common.dvo_port == PORT_IDPD &&
		    p_child->common.device_type == DEVICE_TYPE_eDP)
3259 3260 3261 3262 3263
			return true;
	}
	return false;
}

3264 3265 3266
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
3267 3268
	struct intel_connector *intel_connector = to_intel_connector(connector);

3269
	intel_attach_force_audio_property(connector);
3270
	intel_attach_broadcast_rgb_property(connector);
3271
	intel_dp->color_range_auto = true;
3272 3273 3274

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
3275 3276
		drm_object_attach_property(
			&connector->base,
3277
			connector->dev->mode_config.scaling_mode_property,
3278 3279
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3280
	}
3281 3282
}

3283 3284
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3285 3286
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out)
3287 3288 3289 3290
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_power_seq cur, vbt, spec, final;
	u32 pp_on, pp_off, pp_div, pp;
3291
	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3292 3293

	if (HAS_PCH_SPLIT(dev)) {
3294
		pp_ctrl_reg = PCH_PP_CONTROL;
3295 3296 3297 3298
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
3299 3300 3301 3302 3303 3304
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3305
	}
3306 3307 3308

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
3309
	pp = ironlake_get_pp_control(intel_dp);
3310
	I915_WRITE(pp_ctrl_reg, pp);
3311

3312 3313 3314
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
	pp_div = I915_READ(pp_div_reg);
3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

3335
	vbt = dev_priv->vbt.edp_pps;
3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
#define assign_final(field)	final.field = (max(cur.field, vbt.field) == 0 ? \
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

#define get_delay(field)	(DIV_ROUND_UP(final.field, 10))
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);

	if (out)
		*out = final;
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *seq)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3389 3390 3391 3392 3393 3394 3395 3396 3397
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
	int pp_on_reg, pp_off_reg, pp_div_reg;

	if (HAS_PCH_SPLIT(dev)) {
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
3398 3399 3400 3401 3402
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3403 3404
	}

3405
	/* And finally store the new values in the power sequencer. */
3406 3407 3408 3409
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
		(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3410 3411
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
3412
	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3413
	pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3414 3415 3416 3417
			<< PANEL_POWER_CYCLE_DELAY_SHIFT);

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
3418
	if (IS_VALLEYVIEW(dev)) {
3419 3420 3421 3422
		if (dp_to_dig_port(intel_dp)->port == PORT_B)
			port_sel = PANEL_PORT_SELECT_DPB_VLV;
		else
			port_sel = PANEL_PORT_SELECT_DPC_VLV;
3423 3424
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
		if (dp_to_dig_port(intel_dp)->port == PORT_A)
3425
			port_sel = PANEL_PORT_SELECT_DPA;
3426
		else
3427
			port_sel = PANEL_PORT_SELECT_DPD;
3428 3429
	}

3430 3431 3432 3433 3434
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
	I915_WRITE(pp_div_reg, pp_div);
3435 3436

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3437 3438 3439
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
		      I915_READ(pp_div_reg));
3440 3441
}

3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
				     struct intel_connector *intel_connector)
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
	struct edp_power_seq power_seq = { 0 };
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;

	if (!is_edp(intel_dp))
		return true;

	intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);

	/* Cache DPCD and EDID for edp. */
	ironlake_edp_panel_vdd_on(intel_dp);
	has_dpcd = intel_dp_get_dpcd(intel_dp);
	ironlake_edp_panel_vdd_off(intel_dp, false);

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
						      &power_seq);

	ironlake_edp_panel_vdd_on(intel_dp);
	edid = drm_get_edid(connector, &intel_dp->adapter);
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}

	ironlake_edp_panel_vdd_off(intel_dp, false);

	intel_panel_init(&intel_connector->panel, fixed_mode);
	intel_panel_setup_backlight(connector);

	return true;
}

3520
bool
3521 3522
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
3523
{
3524 3525 3526 3527
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
3528
	struct drm_i915_private *dev_priv = dev->dev_private;
3529
	enum port port = intel_dig_port->port;
3530
	const char *name = NULL;
3531
	int type, error;
3532

3533 3534
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
3535
	intel_dp->attached_connector = intel_connector;
3536

3537
	type = DRM_MODE_CONNECTOR_DisplayPort;
3538 3539 3540 3541
	/*
	 * FIXME : We need to initialize built-in panels before external panels.
	 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
	 */
3542 3543
	switch (port) {
	case PORT_A:
3544
		type = DRM_MODE_CONNECTOR_eDP;
3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555
		break;
	case PORT_C:
		if (IS_VALLEYVIEW(dev))
			type = DRM_MODE_CONNECTOR_eDP;
		break;
	case PORT_D:
		if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
			type = DRM_MODE_CONNECTOR_eDP;
		break;
	default:	/* silence GCC warning */
		break;
3556 3557
	}

3558 3559 3560 3561 3562 3563 3564 3565
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

3566 3567 3568 3569
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

3570
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3571 3572 3573 3574 3575
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

3576 3577
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
			  ironlake_panel_vdd_work);
3578

3579
	intel_connector_attach_encoder(intel_connector, intel_encoder);
3580 3581
	drm_sysfs_connector_add(connector);

P
Paulo Zanoni 已提交
3582
	if (HAS_DDI(dev))
3583 3584 3585 3586
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;

3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605
	intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
	if (HAS_DDI(dev)) {
		switch (intel_dig_port->port) {
		case PORT_A:
			intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
			break;
		case PORT_B:
			intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
			break;
		case PORT_C:
			intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
			break;
		case PORT_D:
			intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
			break;
		default:
			BUG();
		}
	}
3606

3607
	/* Set up the DDC bus. */
3608 3609
	switch (port) {
	case PORT_A:
3610
		intel_encoder->hpd_pin = HPD_PORT_A;
3611 3612 3613
		name = "DPDDC-A";
		break;
	case PORT_B:
3614
		intel_encoder->hpd_pin = HPD_PORT_B;
3615 3616 3617
		name = "DPDDC-B";
		break;
	case PORT_C:
3618
		intel_encoder->hpd_pin = HPD_PORT_C;
3619 3620 3621
		name = "DPDDC-C";
		break;
	case PORT_D:
3622
		intel_encoder->hpd_pin = HPD_PORT_D;
3623 3624 3625
		name = "DPDDC-D";
		break;
	default:
3626
		BUG();
3627 3628
	}

3629 3630 3631
	error = intel_dp_i2c_init(intel_dp, intel_connector, name);
	WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
	     error, port_name(port));
3632

R
Rodrigo Vivi 已提交
3633 3634
	intel_dp->psr_setup_done = false;

3635
	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3636 3637 3638 3639 3640 3641 3642
		i2c_del_adapter(&intel_dp->adapter);
		if (is_edp(intel_dp)) {
			cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
			mutex_lock(&dev->mode_config.mutex);
			ironlake_panel_vdd_off_sync(intel_dp);
			mutex_unlock(&dev->mode_config.mutex);
		}
3643 3644
		drm_sysfs_connector_remove(connector);
		drm_connector_cleanup(connector);
3645
		return false;
3646
	}
3647

3648 3649
	intel_dp_add_properties(intel_dp, connector);

3650 3651 3652 3653 3654 3655 3656 3657
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
3658 3659

	return true;
3660
}
3661 3662 3663 3664 3665 3666 3667 3668 3669

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

3670
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3671 3672 3673
	if (!intel_dig_port)
		return;

3674
	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

3686
	intel_encoder->compute_config = intel_dp_compute_config;
3687
	intel_encoder->mode_set = intel_dp_mode_set;
P
Paulo Zanoni 已提交
3688 3689 3690
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->post_disable = intel_post_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
3691
	intel_encoder->get_config = intel_dp_get_config;
3692
	if (IS_VALLEYVIEW(dev)) {
3693
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3694 3695 3696
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
	} else {
3697 3698
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
3699
	}
3700

3701
	intel_dig_port->port = port;
3702 3703
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
3704
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3705 3706 3707 3708
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	intel_encoder->cloneable = false;
	intel_encoder->hot_plug = intel_dp_hot_plug;

3709 3710 3711
	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
		drm_encoder_cleanup(encoder);
		kfree(intel_dig_port);
3712
		kfree(intel_connector);
3713
	}
3714
}