i915_gem.c 134.4 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

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#include <drm/drmP.h>
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#include <drm/drm_vma_manager.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
C
Chris Wilson 已提交
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#include "i915_trace.h"
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#include "intel_drv.h"
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#include <linux/oom.h>
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#include <linux/shmem_fs.h>
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#include <linux/slab.h>
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#include <linux/swap.h>
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#include <linux/pci.h>
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#include <linux/dma-buf.h>
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static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
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static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
						   bool force);
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static __must_check int
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i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly);
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static void
i915_gem_object_retire(struct drm_i915_gem_object *obj);

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static void i915_gem_write_fence(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj);
static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
					 struct drm_i915_fence_reg *fence,
					 bool enable);

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static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
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					     struct shrink_control *sc);
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static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
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					    struct shrink_control *sc);
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static int i915_gem_shrinker_oom(struct notifier_block *nb,
				 unsigned long event,
				 void *ptr);
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static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
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static bool cpu_cache_is_coherent(struct drm_device *dev,
				  enum i915_cache_level level)
{
	return HAS_LLC(dev) || level != I915_CACHE_NONE;
}

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static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
	if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
		return true;

	return obj->pin_display;
}

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static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
{
	if (obj->tiling_mode)
		i915_gem_release_mmap(obj);

	/* As we do not have an associated fence register, we will force
	 * a tiling change if we ever need to acquire one.
	 */
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	obj->fence_dirty = false;
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	obj->fence_reg = I915_FENCE_REG_NONE;
}

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/* some bookkeeping */
static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
				  size_t size)
{
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	spin_lock(&dev_priv->mm.object_stat_lock);
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	dev_priv->mm.object_count++;
	dev_priv->mm.object_memory += size;
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	spin_unlock(&dev_priv->mm.object_stat_lock);
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}

static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
				     size_t size)
{
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	spin_lock(&dev_priv->mm.object_stat_lock);
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	dev_priv->mm.object_count--;
	dev_priv->mm.object_memory -= size;
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	spin_unlock(&dev_priv->mm.object_stat_lock);
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}

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static int
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i915_gem_wait_for_error(struct i915_gpu_error *error)
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{
	int ret;

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#define EXIT_COND (!i915_reset_in_progress(error) || \
		   i915_terminally_wedged(error))
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	if (EXIT_COND)
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		return 0;

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	/*
	 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
	 * userspace. If it takes that long something really bad is going on and
	 * we should simply try to bail out and fail as gracefully as possible.
	 */
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	ret = wait_event_interruptible_timeout(error->reset_queue,
					       EXIT_COND,
					       10*HZ);
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	if (ret == 0) {
		DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
		return -EIO;
	} else if (ret < 0) {
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		return ret;
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	}
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#undef EXIT_COND
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	return 0;
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}

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int i915_mutex_lock_interruptible(struct drm_device *dev)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	int ret;

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	ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
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	if (ret)
		return ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

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	WARN_ON(i915_verify_lists(dev));
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	return 0;
}
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static inline bool
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i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
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{
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	return i915_gem_obj_bound_any(obj) && !obj->active;
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}

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int
i915_gem_init_ioctl(struct drm_device *dev, void *data,
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		    struct drm_file *file)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct drm_i915_gem_init *args = data;
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	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;

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	if (args->gtt_start >= args->gtt_end ||
	    (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
		return -EINVAL;
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	/* GEM with user mode setting was never supported on ilk and later. */
	if (INTEL_INFO(dev)->gen >= 5)
		return -ENODEV;

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	mutex_lock(&dev->struct_mutex);
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	i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
				  args->gtt_end);
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	dev_priv->gtt.mappable_end = args->gtt_end;
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	mutex_unlock(&dev->struct_mutex);

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	return 0;
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}

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int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
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			    struct drm_file *file)
192
{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct drm_i915_gem_get_aperture *args = data;
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	struct drm_i915_gem_object *obj;
	size_t pinned;
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	pinned = 0;
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	mutex_lock(&dev->struct_mutex);
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	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
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		if (i915_gem_obj_is_pinned(obj))
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			pinned += i915_gem_obj_ggtt_size(obj);
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	mutex_unlock(&dev->struct_mutex);
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	args->aper_size = dev_priv->gtt.base.total;
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	args->aper_available_size = args->aper_size - pinned;
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	return 0;
}

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static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
{
	drm_dma_handle_t *phys = obj->phys_handle;

	if (!phys)
		return;

	if (obj->madv == I915_MADV_WILLNEED) {
		struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
		char *vaddr = phys->vaddr;
		int i;

		for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
			struct page *page = shmem_read_mapping_page(mapping, i);
			if (!IS_ERR(page)) {
				char *dst = kmap_atomic(page);
				memcpy(dst, vaddr, PAGE_SIZE);
				drm_clflush_virt_range(dst, PAGE_SIZE);
				kunmap_atomic(dst);

				set_page_dirty(page);
				mark_page_accessed(page);
				page_cache_release(page);
			}
			vaddr += PAGE_SIZE;
		}
		i915_gem_chipset_flush(obj->base.dev);
	}

#ifdef CONFIG_X86
	set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
#endif
	drm_pci_free(obj->base.dev, phys);
	obj->phys_handle = NULL;
}

int
i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
			    int align)
{
	drm_dma_handle_t *phys;
	struct address_space *mapping;
	char *vaddr;
	int i;

	if (obj->phys_handle) {
		if ((unsigned long)obj->phys_handle->vaddr & (align -1))
			return -EBUSY;

		return 0;
	}

	if (obj->madv != I915_MADV_WILLNEED)
		return -EFAULT;

	if (obj->base.filp == NULL)
		return -EINVAL;

	/* create a new object */
	phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
	if (!phys)
		return -ENOMEM;

	vaddr = phys->vaddr;
#ifdef CONFIG_X86
	set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
#endif
	mapping = file_inode(obj->base.filp)->i_mapping;
	for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
		struct page *page;
		char *src;

		page = shmem_read_mapping_page(mapping, i);
		if (IS_ERR(page)) {
#ifdef CONFIG_X86
			set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
#endif
			drm_pci_free(obj->base.dev, phys);
			return PTR_ERR(page);
		}

		src = kmap_atomic(page);
		memcpy(vaddr, src, PAGE_SIZE);
		kunmap_atomic(src);

		mark_page_accessed(page);
		page_cache_release(page);

		vaddr += PAGE_SIZE;
	}

	obj->phys_handle = phys;
	return 0;
}

static int
i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
		     struct drm_i915_gem_pwrite *args,
		     struct drm_file *file_priv)
{
	struct drm_device *dev = obj->base.dev;
	void *vaddr = obj->phys_handle->vaddr + args->offset;
	char __user *user_data = to_user_ptr(args->data_ptr);

	if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
		unsigned long unwritten;

		/* The physical object once assigned is fixed for the lifetime
		 * of the obj, so we can safely drop the lock and continue
		 * to access vaddr.
		 */
		mutex_unlock(&dev->struct_mutex);
		unwritten = copy_from_user(vaddr, user_data, args->size);
		mutex_lock(&dev->struct_mutex);
		if (unwritten)
			return -EFAULT;
	}

	i915_gem_chipset_flush(dev);
	return 0;
}

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void *i915_gem_object_alloc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
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}

void i915_gem_object_free(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	kmem_cache_free(dev_priv->slab, obj);
}

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static int
i915_gem_create(struct drm_file *file,
		struct drm_device *dev,
		uint64_t size,
		uint32_t *handle_p)
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{
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	struct drm_i915_gem_object *obj;
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	int ret;
	u32 handle;
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355
	size = roundup(size, PAGE_SIZE);
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	if (size == 0)
		return -EINVAL;
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	/* Allocate the new object */
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	obj = i915_gem_alloc_object(dev, size);
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	if (obj == NULL)
		return -ENOMEM;

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	ret = drm_gem_handle_create(file, &obj->base, &handle);
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	/* drop reference from allocate - handle holds it now */
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	drm_gem_object_unreference_unlocked(&obj->base);
	if (ret)
		return ret;
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370
	*handle_p = handle;
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	return 0;
}

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int
i915_gem_dumb_create(struct drm_file *file,
		     struct drm_device *dev,
		     struct drm_mode_create_dumb *args)
{
	/* have to work out size/pitch and return them */
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	args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
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	args->size = args->pitch * args->height;
	return i915_gem_create(file, dev,
			       args->size, &args->handle);
}

/**
 * Creates a new mm object and returns a handle to it.
 */
int
i915_gem_create_ioctl(struct drm_device *dev, void *data,
		      struct drm_file *file)
{
	struct drm_i915_gem_create *args = data;
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	return i915_gem_create(file, dev,
			       args->size, &args->handle);
}

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static inline int
__copy_to_user_swizzled(char __user *cpu_vaddr,
			const char *gpu_vaddr, int gpu_offset,
			int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_to_user(cpu_vaddr + cpu_offset,
				     gpu_vaddr + swizzled_gpu_offset,
				     this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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static inline int
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__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
			  const char __user *cpu_vaddr,
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			  int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
				       cpu_vaddr + cpu_offset,
				       this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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/*
 * Pins the specified object's pages and synchronizes the object with
 * GPU accesses. Sets needs_clflush to non-zero if the caller should
 * flush the object from the CPU cache.
 */
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    int *needs_clflush)
{
	int ret;

	*needs_clflush = 0;

	if (!obj->base.filp)
		return -EINVAL;

	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
		/* If we're not in the cpu read domain, set ourself into the gtt
		 * read domain and manually flush cachelines (if required). This
		 * optimizes for the case when the gpu will dirty the data
		 * anyway again before the next pread happens. */
		*needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
							obj->cache_level);
		ret = i915_gem_object_wait_rendering(obj, true);
		if (ret)
			return ret;
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		i915_gem_object_retire(obj);
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	}

	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ret;

	i915_gem_object_pin_pages(obj);

	return ret;
}

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/* Per-page copy function for the shmem pread fastpath.
 * Flushes invalid cachelines before reading the target if
 * needs_clflush is set. */
492
static int
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shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;

500
	if (unlikely(page_do_bit17_swizzling))
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		return -EINVAL;

	vaddr = kmap_atomic(page);
	if (needs_clflush)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	ret = __copy_to_user_inatomic(user_data,
				      vaddr + shmem_page_offset,
				      page_length);
	kunmap_atomic(vaddr);

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	return ret ? -EFAULT : 0;
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}

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static void
shmem_clflush_swizzled_range(char *addr, unsigned long length,
			     bool swizzled)
{
519
	if (unlikely(swizzled)) {
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		unsigned long start = (unsigned long) addr;
		unsigned long end = (unsigned long) addr + length;

		/* For swizzling simply ensure that we always flush both
		 * channels. Lame, but simple and it works. Swizzled
		 * pwrite/pread is far from a hotpath - current userspace
		 * doesn't use it at all. */
		start = round_down(start, 128);
		end = round_up(end, 128);

		drm_clflush_virt_range((void *)start, end - start);
	} else {
		drm_clflush_virt_range(addr, length);
	}

}

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/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
static int
shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;

	vaddr = kmap(page);
	if (needs_clflush)
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		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
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	if (page_do_bit17_swizzling)
		ret = __copy_to_user_swizzled(user_data,
					      vaddr, shmem_page_offset,
					      page_length);
	else
		ret = __copy_to_user(user_data,
				     vaddr + shmem_page_offset,
				     page_length);
	kunmap(page);

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	return ret ? - EFAULT : 0;
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}

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static int
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i915_gem_shmem_pread(struct drm_device *dev,
		     struct drm_i915_gem_object *obj,
		     struct drm_i915_gem_pread *args,
		     struct drm_file *file)
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{
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	char __user *user_data;
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	ssize_t remain;
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	loff_t offset;
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	int shmem_page_offset, page_length, ret = 0;
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	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
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	int prefaulted = 0;
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	int needs_clflush = 0;
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	struct sg_page_iter sg_iter;
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	user_data = to_user_ptr(args->data_ptr);
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	remain = args->size;

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	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
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	ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
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	if (ret)
		return ret;

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	offset = args->offset;
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	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
			 offset >> PAGE_SHIFT) {
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		struct page *page = sg_page_iter_page(&sg_iter);
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		if (remain <= 0)
			break;

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		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
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		shmem_page_offset = offset_in_page(offset);
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		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;

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		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;

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		ret = shmem_pread_fast(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
		if (ret == 0)
			goto next_page;
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		mutex_unlock(&dev->struct_mutex);

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		if (likely(!i915.prefault_disable) && !prefaulted) {
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			ret = fault_in_multipages_writeable(user_data, remain);
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			/* Userspace is tricking us, but we've already clobbered
			 * its pages with the prefault and promised to write the
			 * data up to the first fault. Hence ignore any errors
			 * and just continue. */
			(void)ret;
			prefaulted = 1;
		}
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		ret = shmem_pread_slow(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
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634
		mutex_lock(&dev->struct_mutex);
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		if (ret)
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			goto out;

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next_page:
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		remain -= page_length;
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		user_data += page_length;
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		offset += page_length;
	}

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out:
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	i915_gem_object_unpin_pages(obj);

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	return ret;
}

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/**
 * Reads data from the object referenced by handle.
 *
 * On error, the contents of *data are undefined.
 */
int
i915_gem_pread_ioctl(struct drm_device *dev, void *data,
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		     struct drm_file *file)
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{
	struct drm_i915_gem_pread *args = data;
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	struct drm_i915_gem_object *obj;
662
	int ret = 0;
663

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	if (args->size == 0)
		return 0;

	if (!access_ok(VERIFY_WRITE,
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		       to_user_ptr(args->data_ptr),
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		       args->size))
		return -EFAULT;

672
	ret = i915_mutex_lock_interruptible(dev);
673
	if (ret)
674
		return ret;
675

676
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
677
	if (&obj->base == NULL) {
678 679
		ret = -ENOENT;
		goto unlock;
680
	}
681

682
	/* Bounds check source.  */
683 684
	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
685
		ret = -EINVAL;
686
		goto out;
687 688
	}

689 690 691 692 693 694 695 696
	/* prime objects have no backing filp to GEM pread/pwrite
	 * pages from.
	 */
	if (!obj->base.filp) {
		ret = -EINVAL;
		goto out;
	}

697 698
	trace_i915_gem_object_pread(obj, args->offset, args->size);

699
	ret = i915_gem_shmem_pread(dev, obj, args, file);
700

701
out:
702
	drm_gem_object_unreference(&obj->base);
703
unlock:
704
	mutex_unlock(&dev->struct_mutex);
705
	return ret;
706 707
}

708 709
/* This is the fast write path which cannot handle
 * page faults in the source data
710
 */
711 712 713 714 715 716

static inline int
fast_user_write(struct io_mapping *mapping,
		loff_t page_base, int page_offset,
		char __user *user_data,
		int length)
717
{
718 719
	void __iomem *vaddr_atomic;
	void *vaddr;
720
	unsigned long unwritten;
721

722
	vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
723 724 725
	/* We can use the cpu mem copy function because this is X86. */
	vaddr = (void __force*)vaddr_atomic + page_offset;
	unwritten = __copy_from_user_inatomic_nocache(vaddr,
726
						      user_data, length);
727
	io_mapping_unmap_atomic(vaddr_atomic);
728
	return unwritten;
729 730
}

731 732 733 734
/**
 * This is the fast pwrite path, where we copy the data directly from the
 * user into the GTT, uncached.
 */
735
static int
736 737
i915_gem_gtt_pwrite_fast(struct drm_device *dev,
			 struct drm_i915_gem_object *obj,
738
			 struct drm_i915_gem_pwrite *args,
739
			 struct drm_file *file)
740
{
741
	struct drm_i915_private *dev_priv = dev->dev_private;
742
	ssize_t remain;
743
	loff_t offset, page_base;
744
	char __user *user_data;
745 746
	int page_offset, page_length, ret;

747
	ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
748 749 750 751 752 753 754 755 756 757
	if (ret)
		goto out;

	ret = i915_gem_object_set_to_gtt_domain(obj, true);
	if (ret)
		goto out_unpin;

	ret = i915_gem_object_put_fence(obj);
	if (ret)
		goto out_unpin;
758

759
	user_data = to_user_ptr(args->data_ptr);
760 761
	remain = args->size;

762
	offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
763 764 765 766

	while (remain > 0) {
		/* Operation in this page
		 *
767 768 769
		 * page_base = page offset within aperture
		 * page_offset = offset within page
		 * page_length = bytes to copy for this page
770
		 */
771 772
		page_base = offset & PAGE_MASK;
		page_offset = offset_in_page(offset);
773 774 775 776 777
		page_length = remain;
		if ((page_offset + remain) > PAGE_SIZE)
			page_length = PAGE_SIZE - page_offset;

		/* If we get a fault while copying data, then (presumably) our
778 779
		 * source page isn't available.  Return the error and we'll
		 * retry in the slow path.
780
		 */
781
		if (fast_user_write(dev_priv->gtt.mappable, page_base,
782 783 784 785
				    page_offset, user_data, page_length)) {
			ret = -EFAULT;
			goto out_unpin;
		}
786

787 788 789
		remain -= page_length;
		user_data += page_length;
		offset += page_length;
790 791
	}

792
out_unpin:
793
	i915_gem_object_ggtt_unpin(obj);
794
out:
795
	return ret;
796 797
}

798 799 800 801
/* Per-page copy function for the shmem pwrite fastpath.
 * Flushes invalid cachelines before writing to the target if
 * needs_clflush_before is set and flushes out any written cachelines after
 * writing if needs_clflush is set. */
802
static int
803 804 805 806 807
shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
808
{
809
	char *vaddr;
810
	int ret;
811

812
	if (unlikely(page_do_bit17_swizzling))
813
		return -EINVAL;
814

815 816 817 818
	vaddr = kmap_atomic(page);
	if (needs_clflush_before)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
819 820
	ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
					user_data, page_length);
821 822 823 824
	if (needs_clflush_after)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	kunmap_atomic(vaddr);
825

826
	return ret ? -EFAULT : 0;
827 828
}

829 830
/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
831
static int
832 833 834 835 836
shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
837
{
838 839
	char *vaddr;
	int ret;
840

841
	vaddr = kmap(page);
842
	if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
843 844 845
		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
846 847
	if (page_do_bit17_swizzling)
		ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
848 849
						user_data,
						page_length);
850 851 852 853 854
	else
		ret = __copy_from_user(vaddr + shmem_page_offset,
				       user_data,
				       page_length);
	if (needs_clflush_after)
855 856 857
		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
858
	kunmap(page);
859

860
	return ret ? -EFAULT : 0;
861 862 863
}

static int
864 865 866 867
i915_gem_shmem_pwrite(struct drm_device *dev,
		      struct drm_i915_gem_object *obj,
		      struct drm_i915_gem_pwrite *args,
		      struct drm_file *file)
868 869
{
	ssize_t remain;
870 871
	loff_t offset;
	char __user *user_data;
872
	int shmem_page_offset, page_length, ret = 0;
873
	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
874
	int hit_slowpath = 0;
875 876
	int needs_clflush_after = 0;
	int needs_clflush_before = 0;
877
	struct sg_page_iter sg_iter;
878

879
	user_data = to_user_ptr(args->data_ptr);
880 881
	remain = args->size;

882
	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
883

884 885 886 887 888
	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
		/* If we're not in the cpu write domain, set ourself into the gtt
		 * write domain and manually flush cachelines (if required). This
		 * optimizes for the case when the gpu will use the data
		 * right away and we therefore have to clflush anyway. */
889
		needs_clflush_after = cpu_write_needs_clflush(obj);
890 891 892
		ret = i915_gem_object_wait_rendering(obj, false);
		if (ret)
			return ret;
893 894

		i915_gem_object_retire(obj);
895
	}
896 897 898 899 900
	/* Same trick applies to invalidate partially written cachelines read
	 * before writing. */
	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
		needs_clflush_before =
			!cpu_cache_is_coherent(dev, obj->cache_level);
901

902 903 904 905 906 907
	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ret;

	i915_gem_object_pin_pages(obj);

908
	offset = args->offset;
909
	obj->dirty = 1;
910

911 912
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
			 offset >> PAGE_SHIFT) {
913
		struct page *page = sg_page_iter_page(&sg_iter);
914
		int partial_cacheline_write;
915

916 917 918
		if (remain <= 0)
			break;

919 920 921 922 923
		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
924
		shmem_page_offset = offset_in_page(offset);
925 926 927 928 929

		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;

930 931 932 933 934 935 936
		/* If we don't overwrite a cacheline completely we need to be
		 * careful to have up-to-date data by first clflushing. Don't
		 * overcomplicate things and flush the entire patch. */
		partial_cacheline_write = needs_clflush_before &&
			((shmem_page_offset | page_length)
				& (boot_cpu_data.x86_clflush_size - 1));

937 938 939
		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;

940 941 942 943 944 945
		ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
					user_data, page_do_bit17_swizzling,
					partial_cacheline_write,
					needs_clflush_after);
		if (ret == 0)
			goto next_page;
946 947 948

		hit_slowpath = 1;
		mutex_unlock(&dev->struct_mutex);
949 950 951 952
		ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
					user_data, page_do_bit17_swizzling,
					partial_cacheline_write,
					needs_clflush_after);
953

954
		mutex_lock(&dev->struct_mutex);
955 956

		if (ret)
957 958
			goto out;

959
next_page:
960
		remain -= page_length;
961
		user_data += page_length;
962
		offset += page_length;
963 964
	}

965
out:
966 967
	i915_gem_object_unpin_pages(obj);

968
	if (hit_slowpath) {
969 970 971 972 973 974 975
		/*
		 * Fixup: Flush cpu caches in case we didn't flush the dirty
		 * cachelines in-line while writing and the object moved
		 * out of the cpu write domain while we've dropped the lock.
		 */
		if (!needs_clflush_after &&
		    obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
976 977
			if (i915_gem_clflush_object(obj, obj->pin_display))
				i915_gem_chipset_flush(dev);
978
		}
979
	}
980

981
	if (needs_clflush_after)
982
		i915_gem_chipset_flush(dev);
983

984
	return ret;
985 986 987 988 989 990 991 992 993
}

/**
 * Writes data to the object referenced by handle.
 *
 * On error, the contents of the buffer that were to be modified are undefined.
 */
int
i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
994
		      struct drm_file *file)
995 996
{
	struct drm_i915_gem_pwrite *args = data;
997
	struct drm_i915_gem_object *obj;
998 999 1000 1001 1002 1003
	int ret;

	if (args->size == 0)
		return 0;

	if (!access_ok(VERIFY_READ,
1004
		       to_user_ptr(args->data_ptr),
1005 1006 1007
		       args->size))
		return -EFAULT;

1008
	if (likely(!i915.prefault_disable)) {
1009 1010 1011 1012 1013
		ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
						   args->size);
		if (ret)
			return -EFAULT;
	}
1014

1015
	ret = i915_mutex_lock_interruptible(dev);
1016
	if (ret)
1017
		return ret;
1018

1019
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1020
	if (&obj->base == NULL) {
1021 1022
		ret = -ENOENT;
		goto unlock;
1023
	}
1024

1025
	/* Bounds check destination. */
1026 1027
	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
1028
		ret = -EINVAL;
1029
		goto out;
1030 1031
	}

1032 1033 1034 1035 1036 1037 1038 1039
	/* prime objects have no backing filp to GEM pread/pwrite
	 * pages from.
	 */
	if (!obj->base.filp) {
		ret = -EINVAL;
		goto out;
	}

1040 1041
	trace_i915_gem_object_pwrite(obj, args->offset, args->size);

1042
	ret = -EFAULT;
1043 1044 1045 1046 1047 1048
	/* We can only do the GTT pwrite on untiled buffers, as otherwise
	 * it would end up going through the fenced access, and we'll get
	 * different detiling behavior between reading and writing.
	 * pread/pwrite currently are reading and writing from the CPU
	 * perspective, requiring manual detiling by the client.
	 */
1049 1050
	if (obj->phys_handle) {
		ret = i915_gem_phys_pwrite(obj, args, file);
1051 1052 1053
		goto out;
	}

1054 1055 1056
	if (obj->tiling_mode == I915_TILING_NONE &&
	    obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
	    cpu_write_needs_clflush(obj)) {
1057
		ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1058 1059 1060
		/* Note that the gtt paths might fail with non-page-backed user
		 * pointers (e.g. gtt mappings when moving data between
		 * textures). Fallback to the shmem path in that case. */
1061
	}
1062

1063
	if (ret == -EFAULT || ret == -ENOSPC)
1064
		ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1065

1066
out:
1067
	drm_gem_object_unreference(&obj->base);
1068
unlock:
1069
	mutex_unlock(&dev->struct_mutex);
1070 1071 1072
	return ret;
}

1073
int
1074
i915_gem_check_wedge(struct i915_gpu_error *error,
1075 1076
		     bool interruptible)
{
1077
	if (i915_reset_in_progress(error)) {
1078 1079 1080 1081 1082
		/* Non-interruptible callers can't handle -EAGAIN, hence return
		 * -EIO unconditionally for these. */
		if (!interruptible)
			return -EIO;

1083 1084
		/* Recovery complete, but the reset failed ... */
		if (i915_terminally_wedged(error))
1085 1086
			return -EIO;

1087 1088 1089 1090 1091 1092 1093
		/*
		 * Check if GPU Reset is in progress - we need intel_ring_begin
		 * to work properly to reinit the hw state while the gpu is
		 * still marked as reset-in-progress. Handle this with a flag.
		 */
		if (!error->reload_in_reset)
			return -EAGAIN;
1094 1095 1096 1097 1098 1099 1100 1101 1102
	}

	return 0;
}

/*
 * Compare seqno against outstanding lazy request. Emit a request if they are
 * equal.
 */
1103
int
1104
i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1105 1106 1107 1108 1109 1110
{
	int ret;

	BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));

	ret = 0;
1111
	if (seqno == ring->outstanding_lazy_seqno)
1112
		ret = i915_add_request(ring, NULL);
1113 1114 1115 1116

	return ret;
}

1117 1118 1119 1120 1121 1122
static void fake_irq(unsigned long data)
{
	wake_up_process((struct task_struct *)data);
}

static bool missed_irq(struct drm_i915_private *dev_priv,
1123
		       struct intel_engine_cs *ring)
1124 1125 1126 1127
{
	return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
}

1128 1129 1130 1131 1132 1133 1134 1135
static bool can_wait_boost(struct drm_i915_file_private *file_priv)
{
	if (file_priv == NULL)
		return true;

	return !atomic_xchg(&file_priv->rps_wait_boost, true);
}

1136 1137 1138 1139
/**
 * __wait_seqno - wait until execution of seqno has finished
 * @ring: the ring expected to report seqno
 * @seqno: duh!
1140
 * @reset_counter: reset sequence associated with the given seqno
1141 1142 1143
 * @interruptible: do an interruptible wait (normally yes)
 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 *
1144 1145 1146 1147 1148 1149 1150
 * Note: It is of utmost importance that the passed in seqno and reset_counter
 * values have been read by the caller in an smp safe manner. Where read-side
 * locks are involved, it is sufficient to read the reset_counter before
 * unlocking the lock that protects the seqno. For lockless tricks, the
 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
 * inserted.
 *
1151 1152 1153
 * Returns 0 if the seqno was found within the alloted time. Else returns the
 * errno with remaining time filled in timeout argument.
 */
1154
static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1155
			unsigned reset_counter,
1156
			bool interruptible,
1157
			s64 *timeout,
1158
			struct drm_i915_file_private *file_priv)
1159
{
1160
	struct drm_device *dev = ring->dev;
1161
	struct drm_i915_private *dev_priv = dev->dev_private;
1162 1163
	const bool irq_test_in_progress =
		ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1164
	DEFINE_WAIT(wait);
1165
	unsigned long timeout_expire;
1166
	s64 before, now;
1167 1168
	int ret;

1169
	WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1170

1171 1172 1173
	if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
		return 0;

1174
	timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1175

1176
	if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1177 1178 1179 1180 1181 1182 1183
		gen6_rps_boost(dev_priv);
		if (file_priv)
			mod_delayed_work(dev_priv->wq,
					 &file_priv->mm.idle_work,
					 msecs_to_jiffies(100));
	}

1184
	if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1185 1186
		return -ENODEV;

1187 1188
	/* Record current time in case interrupted by signal, or wedged */
	trace_i915_gem_request_wait_begin(ring, seqno);
1189
	before = ktime_get_raw_ns();
1190 1191
	for (;;) {
		struct timer_list timer;
1192

1193 1194
		prepare_to_wait(&ring->irq_queue, &wait,
				interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1195

1196 1197
		/* We need to check whether any gpu reset happened in between
		 * the caller grabbing the seqno and now ... */
1198 1199 1200 1201 1202 1203 1204 1205
		if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
			/* ... but upgrade the -EAGAIN to an -EIO if the gpu
			 * is truely gone. */
			ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
			if (ret == 0)
				ret = -EAGAIN;
			break;
		}
1206

1207 1208 1209 1210
		if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
			ret = 0;
			break;
		}
1211

1212 1213 1214 1215 1216
		if (interruptible && signal_pending(current)) {
			ret = -ERESTARTSYS;
			break;
		}

1217
		if (timeout && time_after_eq(jiffies, timeout_expire)) {
1218 1219 1220 1221 1222 1223
			ret = -ETIME;
			break;
		}

		timer.function = NULL;
		if (timeout || missed_irq(dev_priv, ring)) {
1224 1225
			unsigned long expire;

1226
			setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1227
			expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1228 1229 1230
			mod_timer(&timer, expire);
		}

1231
		io_schedule();
1232 1233 1234 1235 1236 1237

		if (timer.function) {
			del_singleshot_timer_sync(&timer);
			destroy_timer_on_stack(&timer);
		}
	}
1238
	now = ktime_get_raw_ns();
1239
	trace_i915_gem_request_wait_end(ring, seqno);
1240

1241 1242
	if (!irq_test_in_progress)
		ring->irq_put(ring);
1243 1244

	finish_wait(&ring->irq_queue, &wait);
1245 1246

	if (timeout) {
1247 1248 1249
		s64 tres = *timeout - (now - before);

		*timeout = tres < 0 ? 0 : tres;
1250 1251
	}

1252
	return ret;
1253 1254 1255 1256 1257 1258 1259
}

/**
 * Waits for a sequence number to be signaled, and cleans up the
 * request and object lists appropriately for that event.
 */
int
1260
i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1261 1262 1263 1264 1265 1266 1267 1268 1269
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool interruptible = dev_priv->mm.interruptible;
	int ret;

	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
	BUG_ON(seqno == 0);

1270
	ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1271 1272 1273 1274 1275 1276 1277
	if (ret)
		return ret;

	ret = i915_gem_check_olr(ring, seqno);
	if (ret)
		return ret;

1278 1279
	return __wait_seqno(ring, seqno,
			    atomic_read(&dev_priv->gpu_error.reset_counter),
1280
			    interruptible, NULL, NULL);
1281 1282
}

1283 1284
static int
i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1285
				     struct intel_engine_cs *ring)
1286
{
1287 1288
	if (!obj->active)
		return 0;
1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301

	/* Manually manage the write flush as we may have not yet
	 * retired the buffer.
	 *
	 * Note that the last_write_seqno is always the earlier of
	 * the two (read/write) seqno, so if we haved successfully waited,
	 * we know we have passed the last write.
	 */
	obj->last_write_seqno = 0;

	return 0;
}

1302 1303 1304 1305 1306 1307 1308 1309
/**
 * Ensures that all rendering to the object has completed and the object is
 * safe to unbind from the GTT or access from the CPU.
 */
static __must_check int
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly)
{
1310
	struct intel_engine_cs *ring = obj->ring;
1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321
	u32 seqno;
	int ret;

	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
	if (seqno == 0)
		return 0;

	ret = i915_wait_seqno(ring, seqno);
	if (ret)
		return ret;

1322
	return i915_gem_object_wait_rendering__tail(obj, ring);
1323 1324
}

1325 1326 1327 1328 1329
/* A nonblocking variant of the above wait. This is a highly dangerous routine
 * as the object state may change during this call.
 */
static __must_check int
i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1330
					    struct drm_i915_file_private *file_priv,
1331 1332 1333 1334
					    bool readonly)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1335
	struct intel_engine_cs *ring = obj->ring;
1336
	unsigned reset_counter;
1337 1338 1339 1340 1341 1342 1343 1344 1345 1346
	u32 seqno;
	int ret;

	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
	BUG_ON(!dev_priv->mm.interruptible);

	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
	if (seqno == 0)
		return 0;

1347
	ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1348 1349 1350 1351 1352 1353 1354
	if (ret)
		return ret;

	ret = i915_gem_check_olr(ring, seqno);
	if (ret)
		return ret;

1355
	reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1356
	mutex_unlock(&dev->struct_mutex);
1357
	ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1358
	mutex_lock(&dev->struct_mutex);
1359 1360
	if (ret)
		return ret;
1361

1362
	return i915_gem_object_wait_rendering__tail(obj, ring);
1363 1364
}

1365
/**
1366 1367
 * Called when user space prepares to use an object with the CPU, either
 * through the mmap ioctl's mapping or a GTT mapping.
1368 1369 1370
 */
int
i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1371
			  struct drm_file *file)
1372 1373
{
	struct drm_i915_gem_set_domain *args = data;
1374
	struct drm_i915_gem_object *obj;
1375 1376
	uint32_t read_domains = args->read_domains;
	uint32_t write_domain = args->write_domain;
1377 1378
	int ret;

1379
	/* Only handle setting domains to types used by the CPU. */
1380
	if (write_domain & I915_GEM_GPU_DOMAINS)
1381 1382
		return -EINVAL;

1383
	if (read_domains & I915_GEM_GPU_DOMAINS)
1384 1385 1386 1387 1388 1389 1390 1391
		return -EINVAL;

	/* Having something in the write domain implies it's in the read
	 * domain, and only that read domain.  Enforce that in the request.
	 */
	if (write_domain != 0 && read_domains != write_domain)
		return -EINVAL;

1392
	ret = i915_mutex_lock_interruptible(dev);
1393
	if (ret)
1394
		return ret;
1395

1396
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1397
	if (&obj->base == NULL) {
1398 1399
		ret = -ENOENT;
		goto unlock;
1400
	}
1401

1402 1403 1404 1405
	/* Try to flush the object off the GPU without holding the lock.
	 * We will repeat the flush holding the lock in the normal manner
	 * to catch cases where we are gazumped.
	 */
1406 1407 1408
	ret = i915_gem_object_wait_rendering__nonblocking(obj,
							  file->driver_priv,
							  !write_domain);
1409 1410 1411
	if (ret)
		goto unref;

1412 1413
	if (read_domains & I915_GEM_DOMAIN_GTT) {
		ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1414 1415 1416 1417 1418 1419 1420

		/* Silently promote "you're not bound, there was nothing to do"
		 * to success, since the client was just asking us to
		 * make sure everything was done.
		 */
		if (ret == -EINVAL)
			ret = 0;
1421
	} else {
1422
		ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1423 1424
	}

1425
unref:
1426
	drm_gem_object_unreference(&obj->base);
1427
unlock:
1428 1429 1430 1431 1432 1433 1434 1435 1436
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
 * Called when user space has done writes to this buffer
 */
int
i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1437
			 struct drm_file *file)
1438 1439
{
	struct drm_i915_gem_sw_finish *args = data;
1440
	struct drm_i915_gem_object *obj;
1441 1442
	int ret = 0;

1443
	ret = i915_mutex_lock_interruptible(dev);
1444
	if (ret)
1445
		return ret;
1446

1447
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1448
	if (&obj->base == NULL) {
1449 1450
		ret = -ENOENT;
		goto unlock;
1451 1452 1453
	}

	/* Pinned buffers may be scanout, so flush the cache */
1454 1455
	if (obj->pin_display)
		i915_gem_object_flush_cpu_write_domain(obj, true);
1456

1457
	drm_gem_object_unreference(&obj->base);
1458
unlock:
1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
 * Maps the contents of an object, returning the address it is mapped
 * into.
 *
 * While the mapping holds a reference on the contents of the object, it doesn't
 * imply a ref on the object itself.
 */
int
i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1472
		    struct drm_file *file)
1473 1474 1475 1476 1477
{
	struct drm_i915_gem_mmap *args = data;
	struct drm_gem_object *obj;
	unsigned long addr;

1478
	obj = drm_gem_object_lookup(dev, file, args->handle);
1479
	if (obj == NULL)
1480
		return -ENOENT;
1481

1482 1483 1484 1485 1486 1487 1488 1489
	/* prime objects have no backing filp to GEM mmap
	 * pages from.
	 */
	if (!obj->filp) {
		drm_gem_object_unreference_unlocked(obj);
		return -EINVAL;
	}

1490
	addr = vm_mmap(obj->filp, 0, args->size,
1491 1492
		       PROT_READ | PROT_WRITE, MAP_SHARED,
		       args->offset);
1493
	drm_gem_object_unreference_unlocked(obj);
1494 1495 1496 1497 1498 1499 1500 1501
	if (IS_ERR((void *)addr))
		return addr;

	args->addr_ptr = (uint64_t) addr;

	return 0;
}

1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519
/**
 * i915_gem_fault - fault a page into the GTT
 * vma: VMA in question
 * vmf: fault info
 *
 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
 * from userspace.  The fault handler takes care of binding the object to
 * the GTT (if needed), allocating and programming a fence register (again,
 * only if needed based on whether the old reg is still valid or the object
 * is tiled) and inserting a new PTE into the faulting process.
 *
 * Note that the faulting process may involve evicting existing objects
 * from the GTT and/or fence registers to make room.  So performance may
 * suffer if the GTT working set is large or there are few fence registers
 * left.
 */
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
{
1520 1521
	struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
	struct drm_device *dev = obj->base.dev;
1522
	struct drm_i915_private *dev_priv = dev->dev_private;
1523 1524 1525
	pgoff_t page_offset;
	unsigned long pfn;
	int ret = 0;
1526
	bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1527

1528 1529
	intel_runtime_pm_get(dev_priv);

1530 1531 1532 1533
	/* We don't use vmf->pgoff since that has the fake offset */
	page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
		PAGE_SHIFT;

1534 1535 1536
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		goto out;
1537

1538 1539
	trace_i915_gem_object_fault(obj, page_offset, true, write);

1540 1541 1542 1543 1544 1545 1546 1547 1548
	/* Try to flush the object off the GPU first without holding the lock.
	 * Upon reacquiring the lock, we will perform our sanity checks and then
	 * repeat the flush holding the lock in the normal manner to catch cases
	 * where we are gazumped.
	 */
	ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
	if (ret)
		goto unlock;

1549 1550
	/* Access to snoopable pages through the GTT is incoherent. */
	if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1551
		ret = -EFAULT;
1552 1553 1554
		goto unlock;
	}

1555
	/* Now bind it into the GTT if needed */
1556
	ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1557 1558
	if (ret)
		goto unlock;
1559

1560 1561 1562
	ret = i915_gem_object_set_to_gtt_domain(obj, write);
	if (ret)
		goto unpin;
1563

1564
	ret = i915_gem_object_get_fence(obj);
1565
	if (ret)
1566
		goto unpin;
1567

1568
	/* Finally, remap it using the new GTT offset */
1569 1570
	pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
	pfn >>= PAGE_SHIFT;
1571

1572
	if (!obj->fault_mappable) {
1573 1574 1575
		unsigned long size = min_t(unsigned long,
					   vma->vm_end - vma->vm_start,
					   obj->base.size);
1576 1577
		int i;

1578
		for (i = 0; i < size >> PAGE_SHIFT; i++) {
1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590
			ret = vm_insert_pfn(vma,
					    (unsigned long)vma->vm_start + i * PAGE_SIZE,
					    pfn + i);
			if (ret)
				break;
		}

		obj->fault_mappable = true;
	} else
		ret = vm_insert_pfn(vma,
				    (unsigned long)vmf->virtual_address,
				    pfn + page_offset);
1591
unpin:
1592
	i915_gem_object_ggtt_unpin(obj);
1593
unlock:
1594
	mutex_unlock(&dev->struct_mutex);
1595
out:
1596
	switch (ret) {
1597
	case -EIO:
1598 1599 1600 1601 1602 1603 1604
		/*
		 * We eat errors when the gpu is terminally wedged to avoid
		 * userspace unduly crashing (gl has no provisions for mmaps to
		 * fail). But any other -EIO isn't ours (e.g. swap in failure)
		 * and so needs to be reported.
		 */
		if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1605 1606 1607
			ret = VM_FAULT_SIGBUS;
			break;
		}
1608
	case -EAGAIN:
1609 1610 1611 1612
		/*
		 * EAGAIN means the gpu is hung and we'll wait for the error
		 * handler to reset everything when re-faulting in
		 * i915_mutex_lock_interruptible.
1613
		 */
1614 1615
	case 0:
	case -ERESTARTSYS:
1616
	case -EINTR:
1617 1618 1619 1620 1621
	case -EBUSY:
		/*
		 * EBUSY is ok: this just means that another thread
		 * already did the job.
		 */
1622 1623
		ret = VM_FAULT_NOPAGE;
		break;
1624
	case -ENOMEM:
1625 1626
		ret = VM_FAULT_OOM;
		break;
1627
	case -ENOSPC:
1628
	case -EFAULT:
1629 1630
		ret = VM_FAULT_SIGBUS;
		break;
1631
	default:
1632
		WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1633 1634
		ret = VM_FAULT_SIGBUS;
		break;
1635
	}
1636 1637 1638

	intel_runtime_pm_put(dev_priv);
	return ret;
1639 1640
}

1641 1642 1643 1644
/**
 * i915_gem_release_mmap - remove physical page mappings
 * @obj: obj in question
 *
1645
 * Preserve the reservation of the mmapping with the DRM core code, but
1646 1647 1648 1649 1650 1651 1652 1653 1654
 * relinquish ownership of the pages back to the system.
 *
 * It is vital that we remove the page mapping if we have mapped a tiled
 * object through the GTT and then lose the fence register due to
 * resource pressure. Similarly if the object has been moved out of the
 * aperture, than pages mapped into userspace must be revoked. Removing the
 * mapping will then trigger a page fault on the next user access, allowing
 * fixup by i915_gem_fault().
 */
1655
void
1656
i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1657
{
1658 1659
	if (!obj->fault_mappable)
		return;
1660

1661 1662
	drm_vma_node_unmap(&obj->base.vma_node,
			   obj->base.dev->anon_inode->i_mapping);
1663
	obj->fault_mappable = false;
1664 1665
}

1666 1667 1668 1669 1670 1671 1672 1673 1674
void
i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
{
	struct drm_i915_gem_object *obj;

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
		i915_gem_release_mmap(obj);
}

1675
uint32_t
1676
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1677
{
1678
	uint32_t gtt_size;
1679 1680

	if (INTEL_INFO(dev)->gen >= 4 ||
1681 1682
	    tiling_mode == I915_TILING_NONE)
		return size;
1683 1684 1685

	/* Previous chips need a power-of-two fence region when tiling */
	if (INTEL_INFO(dev)->gen == 3)
1686
		gtt_size = 1024*1024;
1687
	else
1688
		gtt_size = 512*1024;
1689

1690 1691
	while (gtt_size < size)
		gtt_size <<= 1;
1692

1693
	return gtt_size;
1694 1695
}

1696 1697 1698 1699 1700
/**
 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
 * @obj: object to check
 *
 * Return the required GTT alignment for an object, taking into account
1701
 * potential fence register mapping.
1702
 */
1703 1704 1705
uint32_t
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
			   int tiling_mode, bool fenced)
1706 1707 1708 1709 1710
{
	/*
	 * Minimum alignment is 4k (GTT page size), but might be greater
	 * if a fence register is needed for the object.
	 */
1711
	if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1712
	    tiling_mode == I915_TILING_NONE)
1713 1714
		return 4096;

1715 1716 1717 1718
	/*
	 * Previous chips need to be aligned to the size of the smallest
	 * fence register that can contain the object.
	 */
1719
	return i915_gem_get_gtt_size(dev, size, tiling_mode);
1720 1721
}

1722 1723 1724 1725 1726
static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	int ret;

1727
	if (drm_vma_node_has_offset(&obj->base.vma_node))
1728 1729
		return 0;

1730 1731
	dev_priv->mm.shrinker_no_lock_stealing = true;

1732 1733
	ret = drm_gem_create_mmap_offset(&obj->base);
	if (ret != -ENOSPC)
1734
		goto out;
1735 1736 1737 1738 1739 1740 1741 1742

	/* Badly fragmented mmap space? The only way we can recover
	 * space is by destroying unwanted objects. We can't randomly release
	 * mmap_offsets as userspace expects them to be persistent for the
	 * lifetime of the objects. The closest we can is to release the
	 * offsets on purgeable objects by truncating it and marking it purged,
	 * which prevents userspace from ever using that object again.
	 */
1743 1744 1745 1746 1747
	i915_gem_shrink(dev_priv,
			obj->base.size >> PAGE_SHIFT,
			I915_SHRINK_BOUND |
			I915_SHRINK_UNBOUND |
			I915_SHRINK_PURGEABLE);
1748 1749
	ret = drm_gem_create_mmap_offset(&obj->base);
	if (ret != -ENOSPC)
1750
		goto out;
1751 1752

	i915_gem_shrink_all(dev_priv);
1753 1754 1755 1756 1757
	ret = drm_gem_create_mmap_offset(&obj->base);
out:
	dev_priv->mm.shrinker_no_lock_stealing = false;

	return ret;
1758 1759 1760 1761 1762 1763 1764
}

static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
{
	drm_gem_free_mmap_offset(&obj->base);
}

1765
int
1766 1767 1768 1769
i915_gem_mmap_gtt(struct drm_file *file,
		  struct drm_device *dev,
		  uint32_t handle,
		  uint64_t *offset)
1770
{
1771
	struct drm_i915_private *dev_priv = dev->dev_private;
1772
	struct drm_i915_gem_object *obj;
1773 1774
	int ret;

1775
	ret = i915_mutex_lock_interruptible(dev);
1776
	if (ret)
1777
		return ret;
1778

1779
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1780
	if (&obj->base == NULL) {
1781 1782 1783
		ret = -ENOENT;
		goto unlock;
	}
1784

1785
	if (obj->base.size > dev_priv->gtt.mappable_end) {
1786
		ret = -E2BIG;
1787
		goto out;
1788 1789
	}

1790
	if (obj->madv != I915_MADV_WILLNEED) {
1791
		DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1792
		ret = -EFAULT;
1793
		goto out;
1794 1795
	}

1796 1797 1798
	ret = i915_gem_object_create_mmap_offset(obj);
	if (ret)
		goto out;
1799

1800
	*offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1801

1802
out:
1803
	drm_gem_object_unreference(&obj->base);
1804
unlock:
1805
	mutex_unlock(&dev->struct_mutex);
1806
	return ret;
1807 1808
}

1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832
/**
 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
 * @dev: DRM device
 * @data: GTT mapping ioctl data
 * @file: GEM object info
 *
 * Simply returns the fake offset to userspace so it can mmap it.
 * The mmap call will end up in drm_gem_mmap(), which will set things
 * up so we can get faults in the handler above.
 *
 * The fault handler will take care of binding the object into the GTT
 * (since it may have been evicted to make room for something), allocating
 * a fence register, and mapping the appropriate aperture address into
 * userspace.
 */
int
i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file)
{
	struct drm_i915_gem_mmap_gtt *args = data;

	return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
}

1833 1834 1835 1836 1837 1838
static inline int
i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
{
	return obj->madv == I915_MADV_DONTNEED;
}

1839 1840 1841
/* Immediately discard the backing storage */
static void
i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1842
{
1843
	i915_gem_object_free_mmap_offset(obj);
1844

1845 1846
	if (obj->base.filp == NULL)
		return;
1847

1848 1849 1850 1851 1852
	/* Our goal here is to return as much of the memory as
	 * is possible back to the system as we are called from OOM.
	 * To do this we must instruct the shmfs to drop all of its
	 * backing pages, *now*.
	 */
1853
	shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1854 1855
	obj->madv = __I915_MADV_PURGED;
}
1856

1857 1858 1859
/* Try to discard unwanted pages */
static void
i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1860
{
1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874
	struct address_space *mapping;

	switch (obj->madv) {
	case I915_MADV_DONTNEED:
		i915_gem_object_truncate(obj);
	case __I915_MADV_PURGED:
		return;
	}

	if (obj->base.filp == NULL)
		return;

	mapping = file_inode(obj->base.filp)->i_mapping,
	invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1875 1876
}

1877
static void
1878
i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1879
{
1880 1881
	struct sg_page_iter sg_iter;
	int ret;
1882

1883
	BUG_ON(obj->madv == __I915_MADV_PURGED);
1884

1885 1886 1887 1888 1889 1890
	ret = i915_gem_object_set_to_cpu_domain(obj, true);
	if (ret) {
		/* In the event of a disaster, abandon all caches and
		 * hope for the best.
		 */
		WARN_ON(ret != -EIO);
1891
		i915_gem_clflush_object(obj, true);
1892 1893 1894
		obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	}

1895
	if (i915_gem_object_needs_bit17_swizzle(obj))
1896 1897
		i915_gem_object_save_bit_17_swizzle(obj);

1898 1899
	if (obj->madv == I915_MADV_DONTNEED)
		obj->dirty = 0;
1900

1901
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1902
		struct page *page = sg_page_iter_page(&sg_iter);
1903

1904
		if (obj->dirty)
1905
			set_page_dirty(page);
1906

1907
		if (obj->madv == I915_MADV_WILLNEED)
1908
			mark_page_accessed(page);
1909

1910
		page_cache_release(page);
1911
	}
1912
	obj->dirty = 0;
1913

1914 1915
	sg_free_table(obj->pages);
	kfree(obj->pages);
1916
}
1917

1918
int
1919 1920 1921 1922
i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
{
	const struct drm_i915_gem_object_ops *ops = obj->ops;

1923
	if (obj->pages == NULL)
1924 1925
		return 0;

1926 1927 1928
	if (obj->pages_pin_count)
		return -EBUSY;

1929
	BUG_ON(i915_gem_obj_bound_any(obj));
1930

1931 1932 1933
	/* ->put_pages might need to allocate memory for the bit17 swizzle
	 * array, hence protect them from being reaped by removing them from gtt
	 * lists early. */
1934
	list_del(&obj->global_list);
1935

1936
	ops->put_pages(obj);
1937
	obj->pages = NULL;
1938

1939
	i915_gem_object_invalidate(obj);
1940 1941 1942 1943

	return 0;
}

1944 1945 1946
unsigned long
i915_gem_shrink(struct drm_i915_private *dev_priv,
		long target, unsigned flags)
1947
{
1948
	const bool purgeable_only = flags & I915_SHRINK_PURGEABLE;
1949
	unsigned long count = 0;
1950

1951
	/*
1952
	 * As we may completely rewrite the (un)bound list whilst unbinding
1953 1954 1955
	 * (due to retiring requests) we have to strictly process only
	 * one element of the list at the time, and recheck the list
	 * on every iteration.
1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968
	 *
	 * In particular, we must hold a reference whilst removing the
	 * object as we may end up waiting for and/or retiring the objects.
	 * This might release the final reference (held by the active list)
	 * and result in the object being freed from under us. This is
	 * similar to the precautions the eviction code must take whilst
	 * removing objects.
	 *
	 * Also note that although these lists do not hold a reference to
	 * the object we can safely grab one here: The final object
	 * unreferencing and the bound_list are both protected by the
	 * dev->struct_mutex and so we won't ever be able to observe an
	 * object on the bound_list with a reference count equals 0.
1969
	 */
1970 1971
	if (flags & I915_SHRINK_UNBOUND) {
		struct list_head still_in_list;
1972

1973 1974 1975
		INIT_LIST_HEAD(&still_in_list);
		while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
			struct drm_i915_gem_object *obj;
1976

1977 1978 1979
			obj = list_first_entry(&dev_priv->mm.unbound_list,
					       typeof(*obj), global_list);
			list_move_tail(&obj->global_list, &still_in_list);
1980

1981 1982
			if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
				continue;
1983

1984 1985 1986 1987 1988 1989 1990 1991
			drm_gem_object_reference(&obj->base);

			if (i915_gem_object_put_pages(obj) == 0)
				count += obj->base.size >> PAGE_SHIFT;

			drm_gem_object_unreference(&obj->base);
		}
		list_splice(&still_in_list, &dev_priv->mm.unbound_list);
1992 1993
	}

1994 1995
	if (flags & I915_SHRINK_BOUND) {
		struct list_head still_in_list;
1996

1997 1998 1999 2000
		INIT_LIST_HEAD(&still_in_list);
		while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
			struct drm_i915_gem_object *obj;
			struct i915_vma *vma, *v;
2001

2002 2003 2004
			obj = list_first_entry(&dev_priv->mm.bound_list,
					       typeof(*obj), global_list);
			list_move_tail(&obj->global_list, &still_in_list);
2005

2006 2007
			if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
				continue;
2008

2009
			drm_gem_object_reference(&obj->base);
2010

2011 2012 2013
			list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
				if (i915_vma_unbind(vma))
					break;
2014

2015 2016 2017 2018 2019 2020
			if (i915_gem_object_put_pages(obj) == 0)
				count += obj->base.size >> PAGE_SHIFT;

			drm_gem_object_unreference(&obj->base);
		}
		list_splice(&still_in_list, &dev_priv->mm.bound_list);
2021 2022 2023 2024 2025
	}

	return count;
}

2026
static unsigned long
2027 2028 2029
i915_gem_shrink_all(struct drm_i915_private *dev_priv)
{
	i915_gem_evict_everything(dev_priv->dev);
2030 2031
	return i915_gem_shrink(dev_priv, LONG_MAX,
			       I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2032 2033
}

2034
static int
2035
i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2036
{
2037
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2038 2039
	int page_count, i;
	struct address_space *mapping;
2040 2041
	struct sg_table *st;
	struct scatterlist *sg;
2042
	struct sg_page_iter sg_iter;
2043
	struct page *page;
2044
	unsigned long last_pfn = 0;	/* suppress gcc warning */
2045
	gfp_t gfp;
2046

2047 2048 2049 2050 2051 2052 2053
	/* Assert that the object is not currently in any GPU domain. As it
	 * wasn't in the GTT, there shouldn't be any way it could have been in
	 * a GPU cache
	 */
	BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
	BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);

2054 2055 2056 2057
	st = kmalloc(sizeof(*st), GFP_KERNEL);
	if (st == NULL)
		return -ENOMEM;

2058
	page_count = obj->base.size / PAGE_SIZE;
2059 2060
	if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
		kfree(st);
2061
		return -ENOMEM;
2062
	}
2063

2064 2065 2066 2067 2068
	/* Get the list of pages out of our struct file.  They'll be pinned
	 * at this point until we release them.
	 *
	 * Fail silently without starting the shrinker
	 */
A
Al Viro 已提交
2069
	mapping = file_inode(obj->base.filp)->i_mapping;
2070
	gfp = mapping_gfp_mask(mapping);
2071
	gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2072
	gfp &= ~(__GFP_IO | __GFP_WAIT);
2073 2074 2075
	sg = st->sgl;
	st->nents = 0;
	for (i = 0; i < page_count; i++) {
2076 2077
		page = shmem_read_mapping_page_gfp(mapping, i, gfp);
		if (IS_ERR(page)) {
2078 2079 2080 2081 2082
			i915_gem_shrink(dev_priv,
					page_count,
					I915_SHRINK_BOUND |
					I915_SHRINK_UNBOUND |
					I915_SHRINK_PURGEABLE);
2083 2084 2085 2086 2087 2088 2089 2090
			page = shmem_read_mapping_page_gfp(mapping, i, gfp);
		}
		if (IS_ERR(page)) {
			/* We've tried hard to allocate the memory by reaping
			 * our own buffer, now let the real VM do its job and
			 * go down in flames if truly OOM.
			 */
			i915_gem_shrink_all(dev_priv);
2091
			page = shmem_read_mapping_page(mapping, i);
2092 2093 2094
			if (IS_ERR(page))
				goto err_pages;
		}
2095 2096 2097 2098 2099 2100 2101 2102
#ifdef CONFIG_SWIOTLB
		if (swiotlb_nr_tbl()) {
			st->nents++;
			sg_set_page(sg, page, PAGE_SIZE, 0);
			sg = sg_next(sg);
			continue;
		}
#endif
2103 2104 2105 2106 2107 2108 2109 2110 2111
		if (!i || page_to_pfn(page) != last_pfn + 1) {
			if (i)
				sg = sg_next(sg);
			st->nents++;
			sg_set_page(sg, page, PAGE_SIZE, 0);
		} else {
			sg->length += PAGE_SIZE;
		}
		last_pfn = page_to_pfn(page);
2112 2113 2114

		/* Check that the i965g/gm workaround works. */
		WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2115
	}
2116 2117 2118 2119
#ifdef CONFIG_SWIOTLB
	if (!swiotlb_nr_tbl())
#endif
		sg_mark_end(sg);
2120 2121
	obj->pages = st;

2122
	if (i915_gem_object_needs_bit17_swizzle(obj))
2123 2124 2125 2126 2127
		i915_gem_object_do_bit_17_swizzle(obj);

	return 0;

err_pages:
2128 2129
	sg_mark_end(sg);
	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2130
		page_cache_release(sg_page_iter_page(&sg_iter));
2131 2132
	sg_free_table(st);
	kfree(st);
2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145

	/* shmemfs first checks if there is enough memory to allocate the page
	 * and reports ENOSPC should there be insufficient, along with the usual
	 * ENOMEM for a genuine allocation failure.
	 *
	 * We use ENOSPC in our driver to mean that we have run out of aperture
	 * space and so want to translate the error from shmemfs back to our
	 * usual understanding of ENOMEM.
	 */
	if (PTR_ERR(page) == -ENOSPC)
		return -ENOMEM;
	else
		return PTR_ERR(page);
2146 2147
}

2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161
/* Ensure that the associated pages are gathered from the backing storage
 * and pinned into our object. i915_gem_object_get_pages() may be called
 * multiple times before they are released by a single call to
 * i915_gem_object_put_pages() - once the pages are no longer referenced
 * either as a result of memory pressure (reaping pages under the shrinker)
 * or as the object is itself released.
 */
int
i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	const struct drm_i915_gem_object_ops *ops = obj->ops;
	int ret;

2162
	if (obj->pages)
2163 2164
		return 0;

2165
	if (obj->madv != I915_MADV_WILLNEED) {
2166
		DRM_DEBUG("Attempting to obtain a purgeable object\n");
2167
		return -EFAULT;
2168 2169
	}

2170 2171
	BUG_ON(obj->pages_pin_count);

2172 2173 2174 2175
	ret = ops->get_pages(obj);
	if (ret)
		return ret;

2176
	list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2177
	return 0;
2178 2179
}

2180
static void
2181
i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2182
			       struct intel_engine_cs *ring)
2183
{
2184
	u32 seqno = intel_ring_get_seqno(ring);
2185

2186
	BUG_ON(ring == NULL);
2187 2188 2189 2190
	if (obj->ring != ring && obj->last_write_seqno) {
		/* Keep the seqno relative to the current ring */
		obj->last_write_seqno = seqno;
	}
2191
	obj->ring = ring;
2192 2193

	/* Add a reference if we're newly entering the active list. */
2194 2195 2196
	if (!obj->active) {
		drm_gem_object_reference(&obj->base);
		obj->active = 1;
2197
	}
2198

2199
	list_move_tail(&obj->ring_list, &ring->active_list);
2200

2201
	obj->last_read_seqno = seqno;
2202 2203
}

2204
void i915_vma_move_to_active(struct i915_vma *vma,
2205
			     struct intel_engine_cs *ring)
2206 2207 2208 2209 2210
{
	list_move_tail(&vma->mm_list, &vma->vm->active_list);
	return i915_gem_object_move_to_active(vma->obj, ring);
}

2211 2212
static void
i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2213
{
2214
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2215 2216
	struct i915_address_space *vm;
	struct i915_vma *vma;
2217

2218
	BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2219
	BUG_ON(!obj->active);
2220

2221 2222 2223 2224 2225
	list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
		vma = i915_gem_obj_to_vma(obj, vm);
		if (vma && !list_empty(&vma->mm_list))
			list_move_tail(&vma->mm_list, &vm->inactive_list);
	}
2226

2227 2228
	intel_fb_obj_flush(obj, true);

2229
	list_del_init(&obj->ring_list);
2230 2231
	obj->ring = NULL;

2232 2233 2234 2235 2236
	obj->last_read_seqno = 0;
	obj->last_write_seqno = 0;
	obj->base.write_domain = 0;

	obj->last_fenced_seqno = 0;
2237 2238 2239 2240 2241

	obj->active = 0;
	drm_gem_object_unreference(&obj->base);

	WARN_ON(i915_verify_lists(dev));
2242
}
2243

2244 2245 2246
static void
i915_gem_object_retire(struct drm_i915_gem_object *obj)
{
2247
	struct intel_engine_cs *ring = obj->ring;
2248 2249 2250 2251 2252 2253 2254 2255 2256

	if (ring == NULL)
		return;

	if (i915_seqno_passed(ring->get_seqno(ring, true),
			      obj->last_read_seqno))
		i915_gem_object_move_to_inactive(obj);
}

2257
static int
2258
i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2259
{
2260
	struct drm_i915_private *dev_priv = dev->dev_private;
2261
	struct intel_engine_cs *ring;
2262
	int ret, i, j;
2263

2264
	/* Carefully retire all requests without writing to the rings */
2265
	for_each_ring(ring, dev_priv, i) {
2266 2267 2268
		ret = intel_ring_idle(ring);
		if (ret)
			return ret;
2269 2270
	}
	i915_gem_retire_requests(dev);
2271 2272

	/* Finally reset hw state */
2273
	for_each_ring(ring, dev_priv, i) {
2274
		intel_ring_init_seqno(ring, seqno);
2275

2276 2277
		for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
			ring->semaphore.sync_seqno[j] = 0;
2278
	}
2279

2280
	return 0;
2281 2282
}

2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308
int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	if (seqno == 0)
		return -EINVAL;

	/* HWS page needs to be set less than what we
	 * will inject to ring
	 */
	ret = i915_gem_init_seqno(dev, seqno - 1);
	if (ret)
		return ret;

	/* Carefully set the last_seqno value so that wrap
	 * detection still works
	 */
	dev_priv->next_seqno = seqno;
	dev_priv->last_seqno = seqno - 1;
	if (dev_priv->last_seqno == 0)
		dev_priv->last_seqno--;

	return 0;
}

2309 2310
int
i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2311
{
2312 2313 2314 2315
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* reserve 0 for non-seqno */
	if (dev_priv->next_seqno == 0) {
2316
		int ret = i915_gem_init_seqno(dev, 0);
2317 2318
		if (ret)
			return ret;
2319

2320 2321
		dev_priv->next_seqno = 1;
	}
2322

2323
	*seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2324
	return 0;
2325 2326
}

2327
int __i915_add_request(struct intel_engine_cs *ring,
2328
		       struct drm_file *file,
2329
		       struct drm_i915_gem_object *obj,
2330
		       u32 *out_seqno)
2331
{
2332
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2333
	struct drm_i915_gem_request *request;
2334
	struct intel_ringbuffer *ringbuf;
2335
	u32 request_ring_position, request_start;
2336 2337
	int ret;

2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348
	request = ring->preallocated_lazy_request;
	if (WARN_ON(request == NULL))
		return -ENOMEM;

	if (i915.enable_execlists) {
		struct intel_context *ctx = request->ctx;
		ringbuf = ctx->engine[ring->id].ringbuf;
	} else
		ringbuf = ring->buffer;

	request_start = intel_ring_get_tail(ringbuf);
2349 2350 2351 2352 2353 2354 2355
	/*
	 * Emit any outstanding flushes - execbuf can fail to emit the flush
	 * after having emitted the batchbuffer command. Hence we need to fix
	 * things up similar to emitting the lazy request. The difference here
	 * is that the flush _must_ happen before the next request, no matter
	 * what.
	 */
2356 2357 2358 2359 2360 2361 2362 2363 2364
	if (i915.enable_execlists) {
		ret = logical_ring_flush_all_caches(ringbuf);
		if (ret)
			return ret;
	} else {
		ret = intel_ring_flush_all_caches(ring);
		if (ret)
			return ret;
	}
2365

2366 2367 2368 2369 2370
	/* Record the position of the start of the request so that
	 * should we detect the updated seqno part-way through the
	 * GPU processing the request, we never over-estimate the
	 * position of the head.
	 */
2371
	request_ring_position = intel_ring_get_tail(ringbuf);
2372

2373 2374 2375 2376 2377 2378 2379 2380 2381
	if (i915.enable_execlists) {
		ret = ring->emit_request(ringbuf);
		if (ret)
			return ret;
	} else {
		ret = ring->add_request(ring);
		if (ret)
			return ret;
	}
2382

2383
	request->seqno = intel_ring_get_seqno(ring);
2384
	request->ring = ring;
2385
	request->head = request_start;
2386
	request->tail = request_ring_position;
2387 2388 2389 2390 2391 2392 2393

	/* Whilst this request exists, batch_obj will be on the
	 * active_list, and so will hold the active reference. Only when this
	 * request is retired will the the batch_obj be moved onto the
	 * inactive_list and lose its active reference. Hence we do not need
	 * to explicitly hold another reference here.
	 */
2394
	request->batch_obj = obj;
2395

2396 2397 2398 2399 2400 2401 2402 2403
	if (!i915.enable_execlists) {
		/* Hold a reference to the current context so that we can inspect
		 * it later in case a hangcheck error event fires.
		 */
		request->ctx = ring->last_context;
		if (request->ctx)
			i915_gem_context_reference(request->ctx);
	}
2404

2405
	request->emitted_jiffies = jiffies;
2406
	list_add_tail(&request->list, &ring->request_list);
2407
	request->file_priv = NULL;
2408

2409 2410 2411
	if (file) {
		struct drm_i915_file_private *file_priv = file->driver_priv;

2412
		spin_lock(&file_priv->mm.lock);
2413
		request->file_priv = file_priv;
2414
		list_add_tail(&request->client_list,
2415
			      &file_priv->mm.request_list);
2416
		spin_unlock(&file_priv->mm.lock);
2417
	}
2418

2419
	trace_i915_gem_request_add(ring, request->seqno);
2420
	ring->outstanding_lazy_seqno = 0;
2421
	ring->preallocated_lazy_request = NULL;
2422

2423
	if (!dev_priv->ums.mm_suspended) {
2424 2425
		i915_queue_hangcheck(ring->dev);

2426 2427 2428 2429 2430
		cancel_delayed_work_sync(&dev_priv->mm.idle_work);
		queue_delayed_work(dev_priv->wq,
				   &dev_priv->mm.retire_work,
				   round_jiffies_up_relative(HZ));
		intel_mark_busy(dev_priv->dev);
2431
	}
2432

2433
	if (out_seqno)
2434
		*out_seqno = request->seqno;
2435
	return 0;
2436 2437
}

2438 2439
static inline void
i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2440
{
2441
	struct drm_i915_file_private *file_priv = request->file_priv;
2442

2443 2444
	if (!file_priv)
		return;
C
Chris Wilson 已提交
2445

2446
	spin_lock(&file_priv->mm.lock);
2447 2448
	list_del(&request->client_list);
	request->file_priv = NULL;
2449
	spin_unlock(&file_priv->mm.lock);
2450 2451
}

2452
static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2453
				   const struct intel_context *ctx)
2454
{
2455
	unsigned long elapsed;
2456

2457 2458 2459
	elapsed = get_seconds() - ctx->hang_stats.guilty_ts;

	if (ctx->hang_stats.banned)
2460 2461 2462
		return true;

	if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2463
		if (!i915_gem_context_is_default(ctx)) {
2464
			DRM_DEBUG("context hanging too fast, banning!\n");
2465
			return true;
2466 2467 2468
		} else if (i915_stop_ring_allow_ban(dev_priv)) {
			if (i915_stop_ring_allow_warn(dev_priv))
				DRM_ERROR("gpu hanging too fast, banning!\n");
2469
			return true;
2470
		}
2471 2472 2473 2474 2475
	}

	return false;
}

2476
static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2477
				  struct intel_context *ctx,
2478
				  const bool guilty)
2479
{
2480 2481 2482 2483
	struct i915_ctx_hang_stats *hs;

	if (WARN_ON(!ctx))
		return;
2484

2485 2486 2487
	hs = &ctx->hang_stats;

	if (guilty) {
2488
		hs->banned = i915_context_is_banned(dev_priv, ctx);
2489 2490 2491 2492
		hs->batch_active++;
		hs->guilty_ts = get_seconds();
	} else {
		hs->batch_pending++;
2493 2494 2495
	}
}

2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506
static void i915_gem_free_request(struct drm_i915_gem_request *request)
{
	list_del(&request->list);
	i915_gem_request_remove_from_client(request);

	if (request->ctx)
		i915_gem_context_unreference(request->ctx);

	kfree(request);
}

2507
struct drm_i915_gem_request *
2508
i915_gem_find_active_request(struct intel_engine_cs *ring)
2509
{
2510
	struct drm_i915_gem_request *request;
2511 2512 2513
	u32 completed_seqno;

	completed_seqno = ring->get_seqno(ring, false);
2514 2515 2516 2517

	list_for_each_entry(request, &ring->request_list, list) {
		if (i915_seqno_passed(completed_seqno, request->seqno))
			continue;
2518

2519
		return request;
2520
	}
2521 2522 2523 2524 2525

	return NULL;
}

static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2526
				       struct intel_engine_cs *ring)
2527 2528 2529 2530
{
	struct drm_i915_gem_request *request;
	bool ring_hung;

2531
	request = i915_gem_find_active_request(ring);
2532 2533 2534 2535 2536 2537

	if (request == NULL)
		return;

	ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;

2538
	i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2539 2540

	list_for_each_entry_continue(request, &ring->request_list, list)
2541
		i915_set_reset_status(dev_priv, request->ctx, false);
2542
}
2543

2544
static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2545
					struct intel_engine_cs *ring)
2546
{
2547
	while (!list_empty(&ring->active_list)) {
2548
		struct drm_i915_gem_object *obj;
2549

2550 2551 2552
		obj = list_first_entry(&ring->active_list,
				       struct drm_i915_gem_object,
				       ring_list);
2553

2554
		i915_gem_object_move_to_inactive(obj);
2555
	}
2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572

	/*
	 * We must free the requests after all the corresponding objects have
	 * been moved off active lists. Which is the same order as the normal
	 * retire_requests function does. This is important if object hold
	 * implicit references on things like e.g. ppgtt address spaces through
	 * the request.
	 */
	while (!list_empty(&ring->request_list)) {
		struct drm_i915_gem_request *request;

		request = list_first_entry(&ring->request_list,
					   struct drm_i915_gem_request,
					   list);

		i915_gem_free_request(request);
	}
2573

2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585
	while (!list_empty(&ring->execlist_queue)) {
		struct intel_ctx_submit_request *submit_req;

		submit_req = list_first_entry(&ring->execlist_queue,
				struct intel_ctx_submit_request,
				execlist_link);
		list_del(&submit_req->execlist_link);
		intel_runtime_pm_put(dev_priv);
		i915_gem_context_unreference(submit_req->ctx);
		kfree(submit_req);
	}

2586 2587 2588 2589
	/* These may not have been flush before the reset, do so now */
	kfree(ring->preallocated_lazy_request);
	ring->preallocated_lazy_request = NULL;
	ring->outstanding_lazy_seqno = 0;
2590 2591
}

2592
void i915_gem_restore_fences(struct drm_device *dev)
2593 2594 2595 2596
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

2597
	for (i = 0; i < dev_priv->num_fence_regs; i++) {
2598
		struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2599

2600 2601 2602 2603 2604 2605 2606 2607 2608 2609
		/*
		 * Commit delayed tiling changes if we have an object still
		 * attached to the fence, otherwise just clear the fence.
		 */
		if (reg->obj) {
			i915_gem_object_update_fence(reg->obj, reg,
						     reg->obj->tiling_mode);
		} else {
			i915_gem_write_fence(dev, i, NULL);
		}
2610 2611 2612
	}
}

2613
void i915_gem_reset(struct drm_device *dev)
2614
{
2615
	struct drm_i915_private *dev_priv = dev->dev_private;
2616
	struct intel_engine_cs *ring;
2617
	int i;
2618

2619 2620 2621 2622 2623 2624 2625 2626
	/*
	 * Before we free the objects from the requests, we need to inspect
	 * them for finding the guilty party. As the requests only borrow
	 * their reference to the objects, the inspection must be done first.
	 */
	for_each_ring(ring, dev_priv, i)
		i915_gem_reset_ring_status(dev_priv, ring);

2627
	for_each_ring(ring, dev_priv, i)
2628
		i915_gem_reset_ring_cleanup(dev_priv, ring);
2629

2630 2631
	i915_gem_context_reset(dev);

2632
	i915_gem_restore_fences(dev);
2633 2634 2635 2636 2637
}

/**
 * This function clears the request list as sequence numbers are passed.
 */
2638
void
2639
i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2640 2641 2642
{
	uint32_t seqno;

2643
	if (list_empty(&ring->request_list))
2644 2645
		return;

2646
	WARN_ON(i915_verify_lists(ring->dev));
2647

2648
	seqno = ring->get_seqno(ring, true);
2649

2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667
	/* Move any buffers on the active list that are no longer referenced
	 * by the ringbuffer to the flushing/inactive lists as appropriate,
	 * before we free the context associated with the requests.
	 */
	while (!list_empty(&ring->active_list)) {
		struct drm_i915_gem_object *obj;

		obj = list_first_entry(&ring->active_list,
				      struct drm_i915_gem_object,
				      ring_list);

		if (!i915_seqno_passed(seqno, obj->last_read_seqno))
			break;

		i915_gem_object_move_to_inactive(obj);
	}


2668
	while (!list_empty(&ring->request_list)) {
2669
		struct drm_i915_gem_request *request;
2670
		struct intel_ringbuffer *ringbuf;
2671

2672
		request = list_first_entry(&ring->request_list,
2673 2674 2675
					   struct drm_i915_gem_request,
					   list);

2676
		if (!i915_seqno_passed(seqno, request->seqno))
2677 2678
			break;

2679
		trace_i915_gem_request_retire(ring, request->seqno);
2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691

		/* This is one of the few common intersection points
		 * between legacy ringbuffer submission and execlists:
		 * we need to tell them apart in order to find the correct
		 * ringbuffer to which the request belongs to.
		 */
		if (i915.enable_execlists) {
			struct intel_context *ctx = request->ctx;
			ringbuf = ctx->engine[ring->id].ringbuf;
		} else
			ringbuf = ring->buffer;

2692 2693 2694 2695 2696
		/* We know the GPU must have read the request to have
		 * sent us the seqno + interrupt, so use the position
		 * of tail of the request to update the last known position
		 * of the GPU head.
		 */
2697
		ringbuf->last_retired_head = request->tail;
2698

2699
		i915_gem_free_request(request);
2700
	}
2701

2702 2703
	if (unlikely(ring->trace_irq_seqno &&
		     i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2704
		ring->irq_put(ring);
2705
		ring->trace_irq_seqno = 0;
2706
	}
2707

2708
	WARN_ON(i915_verify_lists(ring->dev));
2709 2710
}

2711
bool
2712 2713
i915_gem_retire_requests(struct drm_device *dev)
{
2714
	struct drm_i915_private *dev_priv = dev->dev_private;
2715
	struct intel_engine_cs *ring;
2716
	bool idle = true;
2717
	int i;
2718

2719
	for_each_ring(ring, dev_priv, i) {
2720
		i915_gem_retire_requests_ring(ring);
2721 2722 2723 2724 2725 2726 2727 2728 2729
		idle &= list_empty(&ring->request_list);
	}

	if (idle)
		mod_delayed_work(dev_priv->wq,
				   &dev_priv->mm.idle_work,
				   msecs_to_jiffies(100));

	return idle;
2730 2731
}

2732
static void
2733 2734
i915_gem_retire_work_handler(struct work_struct *work)
{
2735 2736 2737
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), mm.retire_work.work);
	struct drm_device *dev = dev_priv->dev;
2738
	bool idle;
2739

2740
	/* Come back later if the device is busy... */
2741 2742 2743 2744
	idle = false;
	if (mutex_trylock(&dev->struct_mutex)) {
		idle = i915_gem_retire_requests(dev);
		mutex_unlock(&dev->struct_mutex);
2745
	}
2746
	if (!idle)
2747 2748
		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
				   round_jiffies_up_relative(HZ));
2749
}
2750

2751 2752 2753 2754 2755 2756 2757
static void
i915_gem_idle_work_handler(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), mm.idle_work.work);

	intel_mark_idle(dev_priv->dev);
2758 2759
}

2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770
/**
 * Ensures that an object will eventually get non-busy by flushing any required
 * write domains, emitting any outstanding lazy request and retiring and
 * completed requests.
 */
static int
i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
{
	int ret;

	if (obj->active) {
2771
		ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2772 2773 2774 2775 2776 2777 2778 2779 2780
		if (ret)
			return ret;

		i915_gem_retire_requests_ring(obj->ring);
	}

	return 0;
}

2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805
/**
 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
 * @DRM_IOCTL_ARGS: standard ioctl arguments
 *
 * Returns 0 if successful, else an error is returned with the remaining time in
 * the timeout parameter.
 *  -ETIME: object is still busy after timeout
 *  -ERESTARTSYS: signal interrupted the wait
 *  -ENONENT: object doesn't exist
 * Also possible, but rare:
 *  -EAGAIN: GPU wedged
 *  -ENOMEM: damn
 *  -ENODEV: Internal IRQ fail
 *  -E?: The add request failed
 *
 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
 * non-zero timeout parameter the wait ioctl will wait for the given number of
 * nanoseconds on an object becoming unbusy. Since the wait itself does so
 * without holding struct_mutex the object may become re-busied before this
 * function completes. A similar but shorter * race condition exists in the busy
 * ioctl
 */
int
i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
{
2806
	struct drm_i915_private *dev_priv = dev->dev_private;
2807 2808
	struct drm_i915_gem_wait *args = data;
	struct drm_i915_gem_object *obj;
2809
	struct intel_engine_cs *ring = NULL;
2810
	unsigned reset_counter;
2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823
	u32 seqno = 0;
	int ret = 0;

	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
	if (&obj->base == NULL) {
		mutex_unlock(&dev->struct_mutex);
		return -ENOENT;
	}

2824 2825
	/* Need to make sure the object gets inactive eventually. */
	ret = i915_gem_object_flush_active(obj);
2826 2827 2828 2829
	if (ret)
		goto out;

	if (obj->active) {
2830
		seqno = obj->last_read_seqno;
2831 2832 2833 2834 2835 2836 2837
		ring = obj->ring;
	}

	if (seqno == 0)
		 goto out;

	/* Do this after OLR check to make sure we make forward progress polling
2838
	 * on this IOCTL with a timeout <=0 (like busy ioctl)
2839
	 */
2840
	if (args->timeout_ns <= 0) {
2841 2842 2843 2844 2845
		ret = -ETIME;
		goto out;
	}

	drm_gem_object_unreference(&obj->base);
2846
	reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2847 2848
	mutex_unlock(&dev->struct_mutex);

2849 2850
	return __wait_seqno(ring, seqno, reset_counter, true, &args->timeout_ns,
			    file->driver_priv);
2851 2852 2853 2854 2855 2856 2857

out:
	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869
/**
 * i915_gem_object_sync - sync an object to a ring.
 *
 * @obj: object which may be in use on another ring.
 * @to: ring we wish to use the object on. May be NULL.
 *
 * This code is meant to abstract object synchronization with the GPU.
 * Calling with NULL implies synchronizing the object with the CPU
 * rather than a particular GPU ring.
 *
 * Returns 0 if successful, else propagates up the lower layer error.
 */
2870 2871
int
i915_gem_object_sync(struct drm_i915_gem_object *obj,
2872
		     struct intel_engine_cs *to)
2873
{
2874
	struct intel_engine_cs *from = obj->ring;
2875 2876 2877 2878 2879 2880
	u32 seqno;
	int ret, idx;

	if (from == NULL || to == from)
		return 0;

2881
	if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2882
		return i915_gem_object_wait_rendering(obj, false);
2883 2884 2885

	idx = intel_ring_sync_index(from, to);

2886
	seqno = obj->last_read_seqno;
2887 2888
	/* Optimization: Avoid semaphore sync when we are sure we already
	 * waited for an object with higher seqno */
2889
	if (seqno <= from->semaphore.sync_seqno[idx])
2890 2891
		return 0;

2892 2893 2894
	ret = i915_gem_check_olr(obj->ring, seqno);
	if (ret)
		return ret;
2895

2896
	trace_i915_gem_ring_sync_to(from, to, seqno);
2897
	ret = to->semaphore.sync_to(to, from, seqno);
2898
	if (!ret)
2899 2900 2901 2902
		/* We use last_read_seqno because sync_to()
		 * might have just caused seqno wrap under
		 * the radar.
		 */
2903
		from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2904

2905
	return ret;
2906 2907
}

2908 2909 2910 2911 2912 2913 2914
static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
{
	u32 old_write_domain, old_read_domains;

	/* Force a pagefault for domain tracking on next user access */
	i915_gem_release_mmap(obj);

2915 2916 2917
	if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
		return;

2918 2919 2920
	/* Wait for any direct GTT access to complete */
	mb();

2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931
	old_read_domains = obj->base.read_domains;
	old_write_domain = obj->base.write_domain;

	obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
	obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;

	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);
}

2932
int i915_vma_unbind(struct i915_vma *vma)
2933
{
2934
	struct drm_i915_gem_object *obj = vma->obj;
2935
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2936
	int ret;
2937

2938
	if (list_empty(&vma->vma_link))
2939 2940
		return 0;

2941 2942 2943 2944
	if (!drm_mm_node_allocated(&vma->node)) {
		i915_gem_vma_destroy(vma);
		return 0;
	}
2945

2946
	if (vma->pin_count)
2947
		return -EBUSY;
2948

2949 2950
	BUG_ON(obj->pages == NULL);

2951
	ret = i915_gem_object_finish_gpu(obj);
2952
	if (ret)
2953 2954 2955 2956 2957 2958
		return ret;
	/* Continue on if we fail due to EIO, the GPU is hung so we
	 * should be safe and we need to cleanup or else we might
	 * cause memory corruption through use-after-free.
	 */

2959 2960 2961
	/* Throw away the active reference before moving to the unbound list */
	i915_gem_object_retire(obj);

2962 2963
	if (i915_is_ggtt(vma->vm)) {
		i915_gem_object_finish_gtt(obj);
2964

2965 2966 2967 2968 2969
		/* release the fence reg _after_ flushing */
		ret = i915_gem_object_put_fence(obj);
		if (ret)
			return ret;
	}
2970

2971
	trace_i915_vma_unbind(vma);
2972

2973 2974
	vma->unbind_vma(vma);

2975
	list_del_init(&vma->mm_list);
2976
	if (i915_is_ggtt(vma->vm))
2977
		obj->map_and_fenceable = false;
2978

B
Ben Widawsky 已提交
2979 2980 2981 2982
	drm_mm_remove_node(&vma->node);
	i915_gem_vma_destroy(vma);

	/* Since the unbound list is global, only move to that list if
2983
	 * no more VMAs exist. */
2984 2985
	if (list_empty(&obj->vma_list)) {
		i915_gem_gtt_finish_object(obj);
B
Ben Widawsky 已提交
2986
		list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2987
	}
2988

2989 2990 2991 2992 2993 2994
	/* And finally now the object is completely decoupled from this vma,
	 * we can drop its hold on the backing storage and allow it to be
	 * reaped by the shrinker.
	 */
	i915_gem_object_unpin_pages(obj);

2995
	return 0;
2996 2997
}

2998
int i915_gpu_idle(struct drm_device *dev)
2999
{
3000
	struct drm_i915_private *dev_priv = dev->dev_private;
3001
	struct intel_engine_cs *ring;
3002
	int ret, i;
3003 3004

	/* Flush everything onto the inactive list. */
3005
	for_each_ring(ring, dev_priv, i) {
3006 3007 3008 3009 3010
		if (!i915.enable_execlists) {
			ret = i915_switch_context(ring, ring->default_context);
			if (ret)
				return ret;
		}
3011

3012
		ret = intel_ring_idle(ring);
3013 3014 3015
		if (ret)
			return ret;
	}
3016

3017
	return 0;
3018 3019
}

3020 3021
static void i965_write_fence_reg(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj)
3022
{
3023
	struct drm_i915_private *dev_priv = dev->dev_private;
3024 3025
	int fence_reg;
	int fence_pitch_shift;
3026

3027 3028 3029 3030 3031 3032 3033 3034
	if (INTEL_INFO(dev)->gen >= 6) {
		fence_reg = FENCE_REG_SANDYBRIDGE_0;
		fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
	} else {
		fence_reg = FENCE_REG_965_0;
		fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
	}

3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048
	fence_reg += reg * 8;

	/* To w/a incoherency with non-atomic 64-bit register updates,
	 * we split the 64-bit update into two 32-bit writes. In order
	 * for a partial fence not to be evaluated between writes, we
	 * precede the update with write to turn off the fence register,
	 * and only enable the fence as the last step.
	 *
	 * For extra levels of paranoia, we make sure each step lands
	 * before applying the next step.
	 */
	I915_WRITE(fence_reg, 0);
	POSTING_READ(fence_reg);

3049
	if (obj) {
3050
		u32 size = i915_gem_obj_ggtt_size(obj);
3051
		uint64_t val;
3052

3053
		val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3054
				 0xfffff000) << 32;
3055
		val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3056
		val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3057 3058 3059
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
		val |= I965_FENCE_REG_VALID;
3060

3061 3062 3063 3064 3065 3066 3067 3068 3069
		I915_WRITE(fence_reg + 4, val >> 32);
		POSTING_READ(fence_reg + 4);

		I915_WRITE(fence_reg + 0, val);
		POSTING_READ(fence_reg);
	} else {
		I915_WRITE(fence_reg + 4, 0);
		POSTING_READ(fence_reg + 4);
	}
3070 3071
}

3072 3073
static void i915_write_fence_reg(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj)
3074
{
3075
	struct drm_i915_private *dev_priv = dev->dev_private;
3076
	u32 val;
3077

3078
	if (obj) {
3079
		u32 size = i915_gem_obj_ggtt_size(obj);
3080 3081
		int pitch_val;
		int tile_width;
3082

3083
		WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3084
		     (size & -size) != size ||
3085 3086 3087
		     (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
		     "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
		     i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3088

3089 3090 3091 3092 3093 3094 3095 3096 3097
		if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
			tile_width = 128;
		else
			tile_width = 512;

		/* Note: pitch better be a power of two tile widths */
		pitch_val = obj->stride / tile_width;
		pitch_val = ffs(pitch_val) - 1;

3098
		val = i915_gem_obj_ggtt_offset(obj);
3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I830_FENCE_TILING_Y_SHIFT;
		val |= I915_FENCE_SIZE_BITS(size);
		val |= pitch_val << I830_FENCE_PITCH_SHIFT;
		val |= I830_FENCE_REG_VALID;
	} else
		val = 0;

	if (reg < 8)
		reg = FENCE_REG_830_0 + reg * 4;
	else
		reg = FENCE_REG_945_8 + (reg - 8) * 4;

	I915_WRITE(reg, val);
	POSTING_READ(reg);
3114 3115
}

3116 3117
static void i830_write_fence_reg(struct drm_device *dev, int reg,
				struct drm_i915_gem_object *obj)
3118
{
3119
	struct drm_i915_private *dev_priv = dev->dev_private;
3120 3121
	uint32_t val;

3122
	if (obj) {
3123
		u32 size = i915_gem_obj_ggtt_size(obj);
3124
		uint32_t pitch_val;
3125

3126
		WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3127
		     (size & -size) != size ||
3128 3129 3130
		     (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
		     "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
		     i915_gem_obj_ggtt_offset(obj), size);
3131

3132 3133
		pitch_val = obj->stride / 128;
		pitch_val = ffs(pitch_val) - 1;
3134

3135
		val = i915_gem_obj_ggtt_offset(obj);
3136 3137 3138 3139 3140 3141 3142
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I830_FENCE_TILING_Y_SHIFT;
		val |= I830_FENCE_SIZE_BITS(size);
		val |= pitch_val << I830_FENCE_PITCH_SHIFT;
		val |= I830_FENCE_REG_VALID;
	} else
		val = 0;
3143

3144 3145 3146 3147
	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
	POSTING_READ(FENCE_REG_830_0 + reg * 4);
}

3148 3149 3150 3151 3152
inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
{
	return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
}

3153 3154 3155
static void i915_gem_write_fence(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj)
{
3156 3157 3158 3159 3160 3161 3162 3163
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* Ensure that all CPU reads are completed before installing a fence
	 * and all writes before removing the fence.
	 */
	if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
		mb();

3164 3165 3166 3167
	WARN(obj && (!obj->stride || !obj->tiling_mode),
	     "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
	     obj->stride, obj->tiling_mode);

3168
	switch (INTEL_INFO(dev)->gen) {
3169
	case 8:
3170
	case 7:
3171
	case 6:
3172 3173 3174 3175
	case 5:
	case 4: i965_write_fence_reg(dev, reg, obj); break;
	case 3: i915_write_fence_reg(dev, reg, obj); break;
	case 2: i830_write_fence_reg(dev, reg, obj); break;
3176
	default: BUG();
3177
	}
3178 3179 3180 3181 3182 3183

	/* And similarly be paranoid that no direct access to this region
	 * is reordered to before the fence is installed.
	 */
	if (i915_gem_object_needs_mb(obj))
		mb();
3184 3185
}

3186 3187 3188 3189 3190 3191 3192 3193 3194 3195
static inline int fence_number(struct drm_i915_private *dev_priv,
			       struct drm_i915_fence_reg *fence)
{
	return fence - dev_priv->fence_regs;
}

static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
					 struct drm_i915_fence_reg *fence,
					 bool enable)
{
3196
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3197 3198 3199
	int reg = fence_number(dev_priv, fence);

	i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3200 3201

	if (enable) {
3202
		obj->fence_reg = reg;
3203 3204 3205 3206 3207 3208 3209
		fence->obj = obj;
		list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
	} else {
		obj->fence_reg = I915_FENCE_REG_NONE;
		fence->obj = NULL;
		list_del_init(&fence->lru_list);
	}
3210
	obj->fence_dirty = false;
3211 3212
}

3213
static int
3214
i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3215
{
3216
	if (obj->last_fenced_seqno) {
3217
		int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3218 3219
		if (ret)
			return ret;
3220 3221 3222 3223 3224 3225 3226 3227 3228 3229

		obj->last_fenced_seqno = 0;
	}

	return 0;
}

int
i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
{
3230
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3231
	struct drm_i915_fence_reg *fence;
3232 3233
	int ret;

3234
	ret = i915_gem_object_wait_fence(obj);
3235 3236 3237
	if (ret)
		return ret;

3238 3239
	if (obj->fence_reg == I915_FENCE_REG_NONE)
		return 0;
3240

3241 3242
	fence = &dev_priv->fence_regs[obj->fence_reg];

3243 3244 3245
	if (WARN_ON(fence->pin_count))
		return -EBUSY;

3246
	i915_gem_object_fence_lost(obj);
3247
	i915_gem_object_update_fence(obj, fence, false);
3248 3249 3250 3251 3252

	return 0;
}

static struct drm_i915_fence_reg *
3253
i915_find_fence_reg(struct drm_device *dev)
3254 3255
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3256
	struct drm_i915_fence_reg *reg, *avail;
3257
	int i;
3258 3259

	/* First try to find a free reg */
3260
	avail = NULL;
3261 3262 3263
	for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
		reg = &dev_priv->fence_regs[i];
		if (!reg->obj)
3264
			return reg;
3265

3266
		if (!reg->pin_count)
3267
			avail = reg;
3268 3269
	}

3270
	if (avail == NULL)
3271
		goto deadlock;
3272 3273

	/* None available, try to steal one or wait for a user to finish */
3274
	list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3275
		if (reg->pin_count)
3276 3277
			continue;

3278
		return reg;
3279 3280
	}

3281 3282 3283 3284 3285 3286
deadlock:
	/* Wait for completion of pending flips which consume fences */
	if (intel_has_pending_fb_unpin(dev))
		return ERR_PTR(-EAGAIN);

	return ERR_PTR(-EDEADLK);
3287 3288
}

3289
/**
3290
 * i915_gem_object_get_fence - set up fencing for an object
3291 3292 3293 3294 3295 3296 3297 3298 3299
 * @obj: object to map through a fence reg
 *
 * When mapping objects through the GTT, userspace wants to be able to write
 * to them without having to worry about swizzling if the object is tiled.
 * This function walks the fence regs looking for a free one for @obj,
 * stealing one if it can't find any.
 *
 * It then sets up the reg based on the object's properties: address, pitch
 * and tiling format.
3300 3301
 *
 * For an untiled surface, this removes any existing fence.
3302
 */
3303
int
3304
i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3305
{
3306
	struct drm_device *dev = obj->base.dev;
3307
	struct drm_i915_private *dev_priv = dev->dev_private;
3308
	bool enable = obj->tiling_mode != I915_TILING_NONE;
3309
	struct drm_i915_fence_reg *reg;
3310
	int ret;
3311

3312 3313 3314
	/* Have we updated the tiling parameters upon the object and so
	 * will need to serialise the write to the associated fence register?
	 */
3315
	if (obj->fence_dirty) {
3316
		ret = i915_gem_object_wait_fence(obj);
3317 3318 3319
		if (ret)
			return ret;
	}
3320

3321
	/* Just update our place in the LRU if our fence is getting reused. */
3322 3323
	if (obj->fence_reg != I915_FENCE_REG_NONE) {
		reg = &dev_priv->fence_regs[obj->fence_reg];
3324
		if (!obj->fence_dirty) {
3325 3326 3327 3328 3329
			list_move_tail(&reg->lru_list,
				       &dev_priv->mm.fence_list);
			return 0;
		}
	} else if (enable) {
3330 3331 3332
		if (WARN_ON(!obj->map_and_fenceable))
			return -EINVAL;

3333
		reg = i915_find_fence_reg(dev);
3334 3335
		if (IS_ERR(reg))
			return PTR_ERR(reg);
3336

3337 3338 3339
		if (reg->obj) {
			struct drm_i915_gem_object *old = reg->obj;

3340
			ret = i915_gem_object_wait_fence(old);
3341 3342 3343
			if (ret)
				return ret;

3344
			i915_gem_object_fence_lost(old);
3345
		}
3346
	} else
3347 3348
		return 0;

3349 3350
	i915_gem_object_update_fence(obj, reg, enable);

3351
	return 0;
3352 3353
}

3354
static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3355 3356
				     unsigned long cache_level)
{
3357
	struct drm_mm_node *gtt_space = &vma->node;
3358 3359
	struct drm_mm_node *other;

3360 3361 3362 3363 3364 3365
	/*
	 * On some machines we have to be careful when putting differing types
	 * of snoopable memory together to avoid the prefetcher crossing memory
	 * domains and dying. During vm initialisation, we decide whether or not
	 * these constraints apply and set the drm_mm.color_adjust
	 * appropriately.
3366
	 */
3367
	if (vma->vm->mm.color_adjust == NULL)
3368 3369
		return true;

3370
	if (!drm_mm_node_allocated(gtt_space))
3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386
		return true;

	if (list_empty(&gtt_space->node_list))
		return true;

	other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
	if (other->allocated && !other->hole_follows && other->color != cache_level)
		return false;

	other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
	if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
		return false;

	return true;
}

3387 3388 3389
/**
 * Finds free space in the GTT aperture and binds the object there.
 */
3390
static struct i915_vma *
3391 3392 3393
i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
			   struct i915_address_space *vm,
			   unsigned alignment,
3394
			   uint64_t flags)
3395
{
3396
	struct drm_device *dev = obj->base.dev;
3397
	struct drm_i915_private *dev_priv = dev->dev_private;
3398
	u32 size, fence_size, fence_alignment, unfenced_alignment;
3399 3400 3401
	unsigned long start =
		flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
	unsigned long end =
3402
		flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
B
Ben Widawsky 已提交
3403
	struct i915_vma *vma;
3404
	int ret;
3405

3406 3407 3408 3409 3410
	fence_size = i915_gem_get_gtt_size(dev,
					   obj->base.size,
					   obj->tiling_mode);
	fence_alignment = i915_gem_get_gtt_alignment(dev,
						     obj->base.size,
3411
						     obj->tiling_mode, true);
3412
	unfenced_alignment =
3413
		i915_gem_get_gtt_alignment(dev,
3414 3415
					   obj->base.size,
					   obj->tiling_mode, false);
3416

3417
	if (alignment == 0)
3418
		alignment = flags & PIN_MAPPABLE ? fence_alignment :
3419
						unfenced_alignment;
3420
	if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3421
		DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3422
		return ERR_PTR(-EINVAL);
3423 3424
	}

3425
	size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3426

3427 3428 3429
	/* If the object is bigger than the entire aperture, reject it early
	 * before evicting everything in a vain attempt to find space.
	 */
3430 3431
	if (obj->base.size > end) {
		DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3432
			  obj->base.size,
3433
			  flags & PIN_MAPPABLE ? "mappable" : "total",
3434
			  end);
3435
		return ERR_PTR(-E2BIG);
3436 3437
	}

3438
	ret = i915_gem_object_get_pages(obj);
3439
	if (ret)
3440
		return ERR_PTR(ret);
3441

3442 3443
	i915_gem_object_pin_pages(obj);

3444
	vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3445
	if (IS_ERR(vma))
3446
		goto err_unpin;
B
Ben Widawsky 已提交
3447

3448
search_free:
3449
	ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3450
						  size, alignment,
3451 3452
						  obj->cache_level,
						  start, end,
3453 3454
						  DRM_MM_SEARCH_DEFAULT,
						  DRM_MM_CREATE_DEFAULT);
3455
	if (ret) {
3456
		ret = i915_gem_evict_something(dev, vm, size, alignment,
3457 3458 3459
					       obj->cache_level,
					       start, end,
					       flags);
3460 3461
		if (ret == 0)
			goto search_free;
3462

3463
		goto err_free_vma;
3464
	}
3465
	if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
B
Ben Widawsky 已提交
3466
		ret = -EINVAL;
3467
		goto err_remove_node;
3468 3469
	}

3470
	ret = i915_gem_gtt_prepare_object(obj);
B
Ben Widawsky 已提交
3471
	if (ret)
3472
		goto err_remove_node;
3473

3474
	list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3475
	list_add_tail(&vma->mm_list, &vm->inactive_list);
3476

3477 3478
	if (i915_is_ggtt(vm)) {
		bool mappable, fenceable;
3479

3480 3481
		fenceable = (vma->node.size == fence_size &&
			     (vma->node.start & (fence_alignment - 1)) == 0);
3482

3483 3484
		mappable = (vma->node.start + obj->base.size <=
			    dev_priv->gtt.mappable_end);
3485

3486
		obj->map_and_fenceable = mappable && fenceable;
3487
	}
3488

3489
	WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3490

3491
	trace_i915_vma_bind(vma, flags);
3492 3493 3494
	vma->bind_vma(vma, obj->cache_level,
		      flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);

3495
	return vma;
B
Ben Widawsky 已提交
3496

3497
err_remove_node:
3498
	drm_mm_remove_node(&vma->node);
3499
err_free_vma:
B
Ben Widawsky 已提交
3500
	i915_gem_vma_destroy(vma);
3501
	vma = ERR_PTR(ret);
3502
err_unpin:
B
Ben Widawsky 已提交
3503
	i915_gem_object_unpin_pages(obj);
3504
	return vma;
3505 3506
}

3507
bool
3508 3509
i915_gem_clflush_object(struct drm_i915_gem_object *obj,
			bool force)
3510 3511 3512 3513 3514
{
	/* If we don't have a page list set up, then we're not pinned
	 * to GPU, and we can ignore the cache flush because it'll happen
	 * again at bind time.
	 */
3515
	if (obj->pages == NULL)
3516
		return false;
3517

3518 3519 3520 3521 3522
	/*
	 * Stolen memory is always coherent with the GPU as it is explicitly
	 * marked as wc by the system, or the system is cache-coherent.
	 */
	if (obj->stolen)
3523
		return false;
3524

3525 3526 3527 3528 3529 3530 3531 3532
	/* If the GPU is snooping the contents of the CPU cache,
	 * we do not need to manually clear the CPU cache lines.  However,
	 * the caches are only snooped when the render cache is
	 * flushed/invalidated.  As we always have to emit invalidations
	 * and flushes when moving into and out of the RENDER domain, correct
	 * snooping behaviour occurs naturally as the result of our domain
	 * tracking.
	 */
3533
	if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3534
		return false;
3535

C
Chris Wilson 已提交
3536
	trace_i915_gem_object_clflush(obj);
3537
	drm_clflush_sg(obj->pages);
3538 3539

	return true;
3540 3541 3542 3543
}

/** Flushes the GTT write domain for the object if it's dirty. */
static void
3544
i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3545
{
C
Chris Wilson 已提交
3546 3547
	uint32_t old_write_domain;

3548
	if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3549 3550
		return;

3551
	/* No actual flushing is required for the GTT write domain.  Writes
3552 3553
	 * to it immediately go to main memory as far as we know, so there's
	 * no chipset flush.  It also doesn't land in render cache.
3554 3555 3556 3557
	 *
	 * However, we do have to enforce the order so that all writes through
	 * the GTT land before any writes to the device, such as updates to
	 * the GATT itself.
3558
	 */
3559 3560
	wmb();

3561 3562
	old_write_domain = obj->base.write_domain;
	obj->base.write_domain = 0;
C
Chris Wilson 已提交
3563

3564 3565
	intel_fb_obj_flush(obj, false);

C
Chris Wilson 已提交
3566
	trace_i915_gem_object_change_domain(obj,
3567
					    obj->base.read_domains,
C
Chris Wilson 已提交
3568
					    old_write_domain);
3569 3570 3571 3572
}

/** Flushes the CPU write domain for the object if it's dirty. */
static void
3573 3574
i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
				       bool force)
3575
{
C
Chris Wilson 已提交
3576
	uint32_t old_write_domain;
3577

3578
	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3579 3580
		return;

3581 3582 3583
	if (i915_gem_clflush_object(obj, force))
		i915_gem_chipset_flush(obj->base.dev);

3584 3585
	old_write_domain = obj->base.write_domain;
	obj->base.write_domain = 0;
C
Chris Wilson 已提交
3586

3587 3588
	intel_fb_obj_flush(obj, false);

C
Chris Wilson 已提交
3589
	trace_i915_gem_object_change_domain(obj,
3590
					    obj->base.read_domains,
C
Chris Wilson 已提交
3591
					    old_write_domain);
3592 3593
}

3594 3595 3596 3597 3598 3599
/**
 * Moves a single object to the GTT read, and possibly write domain.
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
3600
int
3601
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3602
{
3603
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3604
	struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
C
Chris Wilson 已提交
3605
	uint32_t old_write_domain, old_read_domains;
3606
	int ret;
3607

3608
	/* Not valid to be called on unbound objects. */
3609
	if (vma == NULL)
3610 3611
		return -EINVAL;

3612 3613 3614
	if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
		return 0;

3615
	ret = i915_gem_object_wait_rendering(obj, !write);
3616 3617 3618
	if (ret)
		return ret;

3619
	i915_gem_object_retire(obj);
3620
	i915_gem_object_flush_cpu_write_domain(obj, false);
C
Chris Wilson 已提交
3621

3622 3623 3624 3625 3626 3627 3628
	/* Serialise direct access to this object with the barriers for
	 * coherent writes from the GPU, by effectively invalidating the
	 * GTT domain upon first access.
	 */
	if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
		mb();

3629 3630
	old_write_domain = obj->base.write_domain;
	old_read_domains = obj->base.read_domains;
C
Chris Wilson 已提交
3631

3632 3633 3634
	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3635 3636
	BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3637
	if (write) {
3638 3639 3640
		obj->base.read_domains = I915_GEM_DOMAIN_GTT;
		obj->base.write_domain = I915_GEM_DOMAIN_GTT;
		obj->dirty = 1;
3641 3642
	}

3643 3644 3645
	if (write)
		intel_fb_obj_invalidate(obj, NULL);

C
Chris Wilson 已提交
3646 3647 3648 3649
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);

3650
	/* And bump the LRU for this access */
3651 3652 3653
	if (i915_gem_object_is_inactive(obj))
		list_move_tail(&vma->mm_list,
			       &dev_priv->gtt.base.inactive_list);
3654

3655 3656 3657
	return 0;
}

3658 3659 3660
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level)
{
3661
	struct drm_device *dev = obj->base.dev;
3662
	struct i915_vma *vma, *next;
3663 3664 3665 3666 3667
	int ret;

	if (obj->cache_level == cache_level)
		return 0;

3668
	if (i915_gem_obj_is_pinned(obj)) {
3669 3670 3671 3672
		DRM_DEBUG("can not change the cache level of pinned objects\n");
		return -EBUSY;
	}

3673
	list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3674
		if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3675
			ret = i915_vma_unbind(vma);
3676 3677 3678
			if (ret)
				return ret;
		}
3679 3680
	}

3681
	if (i915_gem_obj_bound_any(obj)) {
3682 3683 3684 3685 3686 3687 3688 3689 3690 3691
		ret = i915_gem_object_finish_gpu(obj);
		if (ret)
			return ret;

		i915_gem_object_finish_gtt(obj);

		/* Before SandyBridge, you could not use tiling or fence
		 * registers with snooped memory, so relinquish any fences
		 * currently pointing to our region in the aperture.
		 */
3692
		if (INTEL_INFO(dev)->gen < 6) {
3693 3694 3695 3696 3697
			ret = i915_gem_object_put_fence(obj);
			if (ret)
				return ret;
		}

3698
		list_for_each_entry(vma, &obj->vma_list, vma_link)
3699 3700 3701
			if (drm_mm_node_allocated(&vma->node))
				vma->bind_vma(vma, cache_level,
					      obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3702 3703
	}

3704 3705 3706 3707 3708
	list_for_each_entry(vma, &obj->vma_list, vma_link)
		vma->node.color = cache_level;
	obj->cache_level = cache_level;

	if (cpu_write_needs_clflush(obj)) {
3709 3710 3711 3712 3713 3714 3715 3716
		u32 old_read_domains, old_write_domain;

		/* If we're coming from LLC cached, then we haven't
		 * actually been tracking whether the data is in the
		 * CPU cache or not, since we only allow one bit set
		 * in obj->write_domain and have been skipping the clflushes.
		 * Just set it to the CPU cache for now.
		 */
3717
		i915_gem_object_retire(obj);
3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733
		WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);

		old_read_domains = obj->base.read_domains;
		old_write_domain = obj->base.write_domain;

		obj->base.read_domains = I915_GEM_DOMAIN_CPU;
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;

		trace_i915_gem_object_change_domain(obj,
						    old_read_domains,
						    old_write_domain);
	}

	return 0;
}

3734 3735
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file)
3736
{
3737
	struct drm_i915_gem_caching *args = data;
3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750
	struct drm_i915_gem_object *obj;
	int ret;

	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}

3751 3752 3753 3754 3755 3756
	switch (obj->cache_level) {
	case I915_CACHE_LLC:
	case I915_CACHE_L3_LLC:
		args->caching = I915_CACHING_CACHED;
		break;

3757 3758 3759 3760
	case I915_CACHE_WT:
		args->caching = I915_CACHING_DISPLAY;
		break;

3761 3762 3763 3764
	default:
		args->caching = I915_CACHING_NONE;
		break;
	}
3765 3766 3767 3768 3769 3770 3771

	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

3772 3773
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file)
3774
{
3775
	struct drm_i915_gem_caching *args = data;
3776 3777 3778 3779
	struct drm_i915_gem_object *obj;
	enum i915_cache_level level;
	int ret;

3780 3781
	switch (args->caching) {
	case I915_CACHING_NONE:
3782 3783
		level = I915_CACHE_NONE;
		break;
3784
	case I915_CACHING_CACHED:
3785 3786
		level = I915_CACHE_LLC;
		break;
3787 3788 3789
	case I915_CACHING_DISPLAY:
		level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
		break;
3790 3791 3792 3793
	default:
		return -EINVAL;
	}

3794 3795 3796 3797
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}

	ret = i915_gem_object_set_cache_level(obj, level);

	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

3812 3813
static bool is_pin_display(struct drm_i915_gem_object *obj)
{
3814 3815 3816 3817 3818 3819
	struct i915_vma *vma;

	vma = i915_gem_obj_to_ggtt(obj);
	if (!vma)
		return false;

3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830
	/* There are 3 sources that pin objects:
	 *   1. The display engine (scanouts, sprites, cursors);
	 *   2. Reservations for execbuffer;
	 *   3. The user.
	 *
	 * We can ignore reservations as we hold the struct_mutex and
	 * are only called outside of the reservation path.  The user
	 * can only increment pin_count once, and so if after
	 * subtracting the potential reference by the user, any pin_count
	 * remains, it must be due to another use by the display engine.
	 */
3831
	return vma->pin_count - !!obj->user_pin_count;
3832 3833
}

3834
/*
3835 3836 3837
 * Prepare buffer for display plane (scanout, cursors, etc).
 * Can be called from an uninterruptible phase (modesetting) and allows
 * any flushes to be pipelined (for pageflips).
3838 3839
 */
int
3840 3841
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3842
				     struct intel_engine_cs *pipelined)
3843
{
3844
	u32 old_read_domains, old_write_domain;
3845
	bool was_pin_display;
3846 3847
	int ret;

3848
	if (pipelined != obj->ring) {
3849 3850
		ret = i915_gem_object_sync(obj, pipelined);
		if (ret)
3851 3852 3853
			return ret;
	}

3854 3855 3856
	/* Mark the pin_display early so that we account for the
	 * display coherency whilst setting up the cache domains.
	 */
3857
	was_pin_display = obj->pin_display;
3858 3859
	obj->pin_display = true;

3860 3861 3862 3863 3864 3865 3866 3867 3868
	/* The display engine is not coherent with the LLC cache on gen6.  As
	 * a result, we make sure that the pinning that is about to occur is
	 * done with uncached PTEs. This is lowest common denominator for all
	 * chipsets.
	 *
	 * However for gen6+, we could do better by using the GFDT bit instead
	 * of uncaching, which would allow us to flush all the LLC-cached data
	 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
	 */
3869 3870
	ret = i915_gem_object_set_cache_level(obj,
					      HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3871
	if (ret)
3872
		goto err_unpin_display;
3873

3874 3875 3876 3877
	/* As the user may map the buffer once pinned in the display plane
	 * (e.g. libkms for the bootup splash), we have to ensure that we
	 * always use map_and_fenceable for all scanout buffers.
	 */
3878
	ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3879
	if (ret)
3880
		goto err_unpin_display;
3881

3882
	i915_gem_object_flush_cpu_write_domain(obj, true);
3883

3884
	old_write_domain = obj->base.write_domain;
3885
	old_read_domains = obj->base.read_domains;
3886 3887 3888 3889

	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3890
	obj->base.write_domain = 0;
3891
	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3892 3893 3894

	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
3895
					    old_write_domain);
3896 3897

	return 0;
3898 3899

err_unpin_display:
3900 3901
	WARN_ON(was_pin_display != is_pin_display(obj));
	obj->pin_display = was_pin_display;
3902 3903 3904 3905 3906 3907
	return ret;
}

void
i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
{
3908
	i915_gem_object_ggtt_unpin(obj);
3909
	obj->pin_display = is_pin_display(obj);
3910 3911
}

3912
int
3913
i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3914
{
3915 3916
	int ret;

3917
	if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3918 3919
		return 0;

3920
	ret = i915_gem_object_wait_rendering(obj, false);
3921 3922 3923
	if (ret)
		return ret;

3924 3925
	/* Ensure that we invalidate the GPU's caches and TLBs. */
	obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3926
	return 0;
3927 3928
}

3929 3930 3931 3932 3933 3934
/**
 * Moves a single object to the CPU read, and possibly write domain.
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
3935
int
3936
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3937
{
C
Chris Wilson 已提交
3938
	uint32_t old_write_domain, old_read_domains;
3939 3940
	int ret;

3941 3942 3943
	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
		return 0;

3944
	ret = i915_gem_object_wait_rendering(obj, !write);
3945 3946 3947
	if (ret)
		return ret;

3948
	i915_gem_object_retire(obj);
3949
	i915_gem_object_flush_gtt_write_domain(obj);
3950

3951 3952
	old_write_domain = obj->base.write_domain;
	old_read_domains = obj->base.read_domains;
C
Chris Wilson 已提交
3953

3954
	/* Flush the CPU cache if it's still invalid. */
3955
	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3956
		i915_gem_clflush_object(obj, false);
3957

3958
		obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3959 3960 3961 3962 3963
	}

	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3964
	BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3965 3966 3967 3968 3969

	/* If we're writing through the CPU, then the GPU read domains will
	 * need to be invalidated at next use.
	 */
	if (write) {
3970 3971
		obj->base.read_domains = I915_GEM_DOMAIN_CPU;
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3972
	}
3973

3974 3975 3976
	if (write)
		intel_fb_obj_invalidate(obj, NULL);

C
Chris Wilson 已提交
3977 3978 3979 3980
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);

3981 3982 3983
	return 0;
}

3984 3985 3986
/* Throttle our rendering by waiting until the ring has completed our requests
 * emitted over 20 msec ago.
 *
3987 3988 3989 3990
 * Note that if we were to use the current jiffies each time around the loop,
 * we wouldn't escape the function with any frames outstanding if the time to
 * render a frame was over 20ms.
 *
3991 3992 3993
 * This should get us reasonable parallelism between CPU and GPU but also
 * relatively low latency when blocking on a particular request to finish.
 */
3994
static int
3995
i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3996
{
3997 3998
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_file_private *file_priv = file->driver_priv;
3999
	unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4000
	struct drm_i915_gem_request *request;
4001
	struct intel_engine_cs *ring = NULL;
4002
	unsigned reset_counter;
4003 4004
	u32 seqno = 0;
	int ret;
4005

4006 4007 4008 4009 4010 4011 4012
	ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
	if (ret)
		return ret;

	ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
	if (ret)
		return ret;
4013

4014
	spin_lock(&file_priv->mm.lock);
4015
	list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4016 4017
		if (time_after_eq(request->emitted_jiffies, recent_enough))
			break;
4018

4019 4020
		ring = request->ring;
		seqno = request->seqno;
4021
	}
4022
	reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4023
	spin_unlock(&file_priv->mm.lock);
4024

4025 4026
	if (seqno == 0)
		return 0;
4027

4028
	ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4029 4030
	if (ret == 0)
		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4031 4032 4033 4034

	return ret;
}

4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053
static bool
i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
{
	struct drm_i915_gem_object *obj = vma->obj;

	if (alignment &&
	    vma->node.start & (alignment - 1))
		return true;

	if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
		return true;

	if (flags & PIN_OFFSET_BIAS &&
	    vma->node.start < (flags & PIN_OFFSET_MASK))
		return true;

	return false;
}

4054
int
4055
i915_gem_object_pin(struct drm_i915_gem_object *obj,
B
Ben Widawsky 已提交
4056
		    struct i915_address_space *vm,
4057
		    uint32_t alignment,
4058
		    uint64_t flags)
4059
{
4060
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4061
	struct i915_vma *vma;
4062 4063
	int ret;

4064 4065 4066
	if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
		return -ENODEV;

4067
	if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4068
		return -EINVAL;
4069 4070 4071

	vma = i915_gem_obj_to_vma(obj, vm);
	if (vma) {
4072 4073 4074
		if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
			return -EBUSY;

4075
		if (i915_vma_misplaced(vma, alignment, flags)) {
4076
			WARN(vma->pin_count,
4077
			     "bo is already pinned with incorrect alignment:"
4078
			     " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4079
			     " obj->map_and_fenceable=%d\n",
4080
			     i915_gem_obj_offset(obj, vm), alignment,
4081
			     !!(flags & PIN_MAPPABLE),
4082
			     obj->map_and_fenceable);
4083
			ret = i915_vma_unbind(vma);
4084 4085
			if (ret)
				return ret;
4086 4087

			vma = NULL;
4088 4089 4090
		}
	}

4091
	if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4092 4093 4094
		vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
		if (IS_ERR(vma))
			return PTR_ERR(vma);
4095
	}
J
Jesse Barnes 已提交
4096

4097 4098
	if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
		vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4099

4100
	vma->pin_count++;
4101 4102
	if (flags & PIN_MAPPABLE)
		obj->pin_mappable |= true;
4103 4104 4105 4106 4107

	return 0;
}

void
4108
i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4109
{
4110
	struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4111

4112 4113 4114 4115 4116
	BUG_ON(!vma);
	BUG_ON(vma->pin_count == 0);
	BUG_ON(!i915_gem_obj_ggtt_bound(obj));

	if (--vma->pin_count == 0)
4117
		obj->pin_mappable = false;
4118 4119
}

4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145
bool
i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
{
	if (obj->fence_reg != I915_FENCE_REG_NONE) {
		struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);

		WARN_ON(!ggtt_vma ||
			dev_priv->fence_regs[obj->fence_reg].pin_count >
			ggtt_vma->pin_count);
		dev_priv->fence_regs[obj->fence_reg].pin_count++;
		return true;
	} else
		return false;
}

void
i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
{
	if (obj->fence_reg != I915_FENCE_REG_NONE) {
		struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
		WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
		dev_priv->fence_regs[obj->fence_reg].pin_count--;
	}
}

4146 4147
int
i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4148
		   struct drm_file *file)
4149 4150
{
	struct drm_i915_gem_pin *args = data;
4151
	struct drm_i915_gem_object *obj;
4152 4153
	int ret;

4154 4155 4156
	if (INTEL_INFO(dev)->gen >= 6)
		return -ENODEV;

4157 4158 4159
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
4160

4161
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4162
	if (&obj->base == NULL) {
4163 4164
		ret = -ENOENT;
		goto unlock;
4165 4166
	}

4167
	if (obj->madv != I915_MADV_WILLNEED) {
4168
		DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4169
		ret = -EFAULT;
4170
		goto out;
4171 4172
	}

4173
	if (obj->pin_filp != NULL && obj->pin_filp != file) {
4174
		DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4175
			  args->handle);
4176 4177
		ret = -EINVAL;
		goto out;
4178 4179
	}

4180 4181 4182 4183 4184
	if (obj->user_pin_count == ULONG_MAX) {
		ret = -EBUSY;
		goto out;
	}

4185
	if (obj->user_pin_count == 0) {
4186
		ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4187 4188
		if (ret)
			goto out;
4189 4190
	}

4191 4192 4193
	obj->user_pin_count++;
	obj->pin_filp = file;

4194
	args->offset = i915_gem_obj_ggtt_offset(obj);
4195
out:
4196
	drm_gem_object_unreference(&obj->base);
4197
unlock:
4198
	mutex_unlock(&dev->struct_mutex);
4199
	return ret;
4200 4201 4202 4203
}

int
i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4204
		     struct drm_file *file)
4205 4206
{
	struct drm_i915_gem_pin *args = data;
4207
	struct drm_i915_gem_object *obj;
4208
	int ret;
4209

4210 4211 4212
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
4213

4214
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4215
	if (&obj->base == NULL) {
4216 4217
		ret = -ENOENT;
		goto unlock;
4218
	}
4219

4220
	if (obj->pin_filp != file) {
4221
		DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4222
			  args->handle);
4223 4224
		ret = -EINVAL;
		goto out;
4225
	}
4226 4227 4228
	obj->user_pin_count--;
	if (obj->user_pin_count == 0) {
		obj->pin_filp = NULL;
4229
		i915_gem_object_ggtt_unpin(obj);
4230
	}
4231

4232
out:
4233
	drm_gem_object_unreference(&obj->base);
4234
unlock:
4235
	mutex_unlock(&dev->struct_mutex);
4236
	return ret;
4237 4238 4239 4240
}

int
i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4241
		    struct drm_file *file)
4242 4243
{
	struct drm_i915_gem_busy *args = data;
4244
	struct drm_i915_gem_object *obj;
4245 4246
	int ret;

4247
	ret = i915_mutex_lock_interruptible(dev);
4248
	if (ret)
4249
		return ret;
4250

4251
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4252
	if (&obj->base == NULL) {
4253 4254
		ret = -ENOENT;
		goto unlock;
4255
	}
4256

4257 4258 4259 4260
	/* Count all active objects as busy, even if they are currently not used
	 * by the gpu. Users of this interface expect objects to eventually
	 * become non-busy without any further actions, therefore emit any
	 * necessary flushes here.
4261
	 */
4262
	ret = i915_gem_object_flush_active(obj);
4263

4264
	args->busy = obj->active;
4265 4266 4267 4268
	if (obj->ring) {
		BUILD_BUG_ON(I915_NUM_RINGS > 16);
		args->busy |= intel_ring_flag(obj->ring) << 16;
	}
4269

4270
	drm_gem_object_unreference(&obj->base);
4271
unlock:
4272
	mutex_unlock(&dev->struct_mutex);
4273
	return ret;
4274 4275 4276 4277 4278 4279
}

int
i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
4280
	return i915_gem_ring_throttle(dev, file_priv);
4281 4282
}

4283 4284 4285 4286 4287
int
i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
	struct drm_i915_gem_madvise *args = data;
4288
	struct drm_i915_gem_object *obj;
4289
	int ret;
4290 4291 4292 4293 4294 4295 4296 4297 4298

	switch (args->madv) {
	case I915_MADV_DONTNEED:
	case I915_MADV_WILLNEED:
	    break;
	default:
	    return -EINVAL;
	}

4299 4300 4301 4302
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

4303
	obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4304
	if (&obj->base == NULL) {
4305 4306
		ret = -ENOENT;
		goto unlock;
4307 4308
	}

4309
	if (i915_gem_obj_is_pinned(obj)) {
4310 4311
		ret = -EINVAL;
		goto out;
4312 4313
	}

4314 4315
	if (obj->madv != __I915_MADV_PURGED)
		obj->madv = args->madv;
4316

4317 4318
	/* if the object is no longer attached, discard its backing storage */
	if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4319 4320
		i915_gem_object_truncate(obj);

4321
	args->retained = obj->madv != __I915_MADV_PURGED;
4322

4323
out:
4324
	drm_gem_object_unreference(&obj->base);
4325
unlock:
4326
	mutex_unlock(&dev->struct_mutex);
4327
	return ret;
4328 4329
}

4330 4331
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			  const struct drm_i915_gem_object_ops *ops)
4332
{
4333
	INIT_LIST_HEAD(&obj->global_list);
4334
	INIT_LIST_HEAD(&obj->ring_list);
4335
	INIT_LIST_HEAD(&obj->obj_exec_link);
B
Ben Widawsky 已提交
4336
	INIT_LIST_HEAD(&obj->vma_list);
4337

4338 4339
	obj->ops = ops;

4340 4341 4342 4343 4344 4345
	obj->fence_reg = I915_FENCE_REG_NONE;
	obj->madv = I915_MADV_WILLNEED;

	i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
}

4346 4347 4348 4349 4350
static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
	.get_pages = i915_gem_object_get_pages_gtt,
	.put_pages = i915_gem_object_put_pages_gtt,
};

4351 4352
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size)
4353
{
4354
	struct drm_i915_gem_object *obj;
4355
	struct address_space *mapping;
4356
	gfp_t mask;
4357

4358
	obj = i915_gem_object_alloc(dev);
4359 4360
	if (obj == NULL)
		return NULL;
4361

4362
	if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4363
		i915_gem_object_free(obj);
4364 4365
		return NULL;
	}
4366

4367 4368 4369 4370 4371 4372 4373
	mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
	if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
		/* 965gm cannot relocate objects above 4GiB. */
		mask &= ~__GFP_HIGHMEM;
		mask |= __GFP_DMA32;
	}

A
Al Viro 已提交
4374
	mapping = file_inode(obj->base.filp)->i_mapping;
4375
	mapping_set_gfp_mask(mapping, mask);
4376

4377
	i915_gem_object_init(obj, &i915_gem_object_ops);
4378

4379 4380
	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4381

4382 4383
	if (HAS_LLC(dev)) {
		/* On some devices, we can have the GPU use the LLC (the CPU
4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398
		 * cache) for about a 10% performance improvement
		 * compared to uncached.  Graphics requests other than
		 * display scanout are coherent with the CPU in
		 * accessing this cache.  This means in this mode we
		 * don't need to clflush on the CPU side, and on the
		 * GPU side we only need to flush internal caches to
		 * get data visible to the CPU.
		 *
		 * However, we maintain the display planes as UC, and so
		 * need to rebind when first used as such.
		 */
		obj->cache_level = I915_CACHE_LLC;
	} else
		obj->cache_level = I915_CACHE_NONE;

4399 4400
	trace_i915_gem_object_create(obj);

4401
	return obj;
4402 4403
}

4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427
static bool discard_backing_storage(struct drm_i915_gem_object *obj)
{
	/* If we are the last user of the backing storage (be it shmemfs
	 * pages or stolen etc), we know that the pages are going to be
	 * immediately released. In this case, we can then skip copying
	 * back the contents from the GPU.
	 */

	if (obj->madv != I915_MADV_WILLNEED)
		return false;

	if (obj->base.filp == NULL)
		return true;

	/* At first glance, this looks racy, but then again so would be
	 * userspace racing mmap against close. However, the first external
	 * reference to the filp can only be obtained through the
	 * i915_gem_mmap_ioctl() which safeguards us against the user
	 * acquiring such a reference whilst we are in the middle of
	 * freeing the object.
	 */
	return atomic_long_read(&obj->base.filp->f_count) == 1;
}

4428
void i915_gem_free_object(struct drm_gem_object *gem_obj)
4429
{
4430
	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4431
	struct drm_device *dev = obj->base.dev;
4432
	struct drm_i915_private *dev_priv = dev->dev_private;
4433
	struct i915_vma *vma, *next;
4434

4435 4436
	intel_runtime_pm_get(dev_priv);

4437 4438
	trace_i915_gem_object_destroy(obj);

4439
	list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4440 4441 4442 4443
		int ret;

		vma->pin_count = 0;
		ret = i915_vma_unbind(vma);
4444 4445
		if (WARN_ON(ret == -ERESTARTSYS)) {
			bool was_interruptible;
4446

4447 4448
			was_interruptible = dev_priv->mm.interruptible;
			dev_priv->mm.interruptible = false;
4449

4450
			WARN_ON(i915_vma_unbind(vma));
4451

4452 4453
			dev_priv->mm.interruptible = was_interruptible;
		}
4454 4455
	}

4456 4457
	i915_gem_object_detach_phys(obj);

4458 4459 4460 4461 4462
	/* Stolen objects don't hold a ref, but do hold pin count. Fix that up
	 * before progressing. */
	if (obj->stolen)
		i915_gem_object_unpin_pages(obj);

4463 4464
	WARN_ON(obj->frontbuffer_bits);

4465 4466
	if (WARN_ON(obj->pages_pin_count))
		obj->pages_pin_count = 0;
4467
	if (discard_backing_storage(obj))
4468
		obj->madv = I915_MADV_DONTNEED;
4469
	i915_gem_object_put_pages(obj);
4470
	i915_gem_object_free_mmap_offset(obj);
4471

4472 4473
	BUG_ON(obj->pages);

4474 4475
	if (obj->base.import_attach)
		drm_prime_gem_destroy(&obj->base, NULL);
4476

4477 4478 4479
	if (obj->ops->release)
		obj->ops->release(obj);

4480 4481
	drm_gem_object_release(&obj->base);
	i915_gem_info_remove_obj(dev_priv, obj->base.size);
4482

4483
	kfree(obj->bit_17);
4484
	i915_gem_object_free(obj);
4485 4486

	intel_runtime_pm_put(dev_priv);
4487 4488
}

4489
struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
B
Ben Widawsky 已提交
4490
				     struct i915_address_space *vm)
4491 4492 4493 4494 4495 4496 4497 4498 4499
{
	struct i915_vma *vma;
	list_for_each_entry(vma, &obj->vma_list, vma_link)
		if (vma->vm == vm)
			return vma;

	return NULL;
}

B
Ben Widawsky 已提交
4500 4501
void i915_gem_vma_destroy(struct i915_vma *vma)
{
4502
	struct i915_address_space *vm = NULL;
B
Ben Widawsky 已提交
4503
	WARN_ON(vma->node.allocated);
4504 4505 4506 4507 4508

	/* Keep the vma as a placeholder in the execbuffer reservation lists */
	if (!list_empty(&vma->exec_list))
		return;

4509 4510
	vm = vma->vm;

4511 4512
	if (!i915_is_ggtt(vm))
		i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4513

4514
	list_del(&vma->vma_link);
4515

B
Ben Widawsky 已提交
4516 4517 4518
	kfree(vma);
}

4519 4520 4521 4522
static void
i915_gem_stop_ringbuffers(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4523
	struct intel_engine_cs *ring;
4524 4525 4526
	int i;

	for_each_ring(ring, dev_priv, i)
4527
		dev_priv->gt.stop_ring(ring);
4528 4529
}

4530
int
4531
i915_gem_suspend(struct drm_device *dev)
4532
{
4533
	struct drm_i915_private *dev_priv = dev->dev_private;
4534
	int ret = 0;
4535

4536
	mutex_lock(&dev->struct_mutex);
4537
	if (dev_priv->ums.mm_suspended)
4538
		goto err;
4539

4540
	ret = i915_gpu_idle(dev);
4541
	if (ret)
4542
		goto err;
4543

4544
	i915_gem_retire_requests(dev);
4545

4546
	/* Under UMS, be paranoid and evict. */
4547
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
4548
		i915_gem_evict_everything(dev);
4549 4550

	i915_kernel_lost_context(dev);
4551
	i915_gem_stop_ringbuffers(dev);
4552

4553 4554 4555 4556 4557 4558 4559 4560 4561
	/* Hack!  Don't let anybody do execbuf while we don't control the chip.
	 * We need to replace this with a semaphore, or something.
	 * And not confound ums.mm_suspended!
	 */
	dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
							     DRIVER_MODESET);
	mutex_unlock(&dev->struct_mutex);

	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4562
	cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4563
	flush_delayed_work(&dev_priv->mm.idle_work);
4564

4565
	return 0;
4566 4567 4568 4569

err:
	mutex_unlock(&dev->struct_mutex);
	return ret;
4570 4571
}

4572
int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4573
{
4574
	struct drm_device *dev = ring->dev;
4575
	struct drm_i915_private *dev_priv = dev->dev_private;
4576 4577
	u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
	u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4578
	int i, ret;
4579

4580
	if (!HAS_L3_DPF(dev) || !remap_info)
4581
		return 0;
4582

4583 4584 4585
	ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
	if (ret)
		return ret;
4586

4587 4588 4589 4590 4591
	/*
	 * Note: We do not worry about the concurrent register cacheline hang
	 * here because no other code should access these registers other than
	 * at initialization time.
	 */
4592
	for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4593 4594 4595
		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
		intel_ring_emit(ring, reg_base + i);
		intel_ring_emit(ring, remap_info[i/4]);
4596 4597
	}

4598
	intel_ring_advance(ring);
4599

4600
	return ret;
4601 4602
}

4603 4604
void i915_gem_init_swizzling(struct drm_device *dev)
{
4605
	struct drm_i915_private *dev_priv = dev->dev_private;
4606

4607
	if (INTEL_INFO(dev)->gen < 5 ||
4608 4609 4610 4611 4612 4613
	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
		return;

	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
				 DISP_TILE_SURFACE_SWIZZLING);

4614 4615 4616
	if (IS_GEN5(dev))
		return;

4617 4618
	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
	if (IS_GEN6(dev))
4619
		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4620
	else if (IS_GEN7(dev))
4621
		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4622 4623
	else if (IS_GEN8(dev))
		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4624 4625
	else
		BUG();
4626
}
D
Daniel Vetter 已提交
4627

4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643
static bool
intel_enable_blt(struct drm_device *dev)
{
	if (!HAS_BLT(dev))
		return false;

	/* The blitter was dysfunctional on early prototypes */
	if (IS_GEN6(dev) && dev->pdev->revision < 8) {
		DRM_INFO("BLT not supported on this pre-production hardware;"
			 " graphics performance will be degraded.\n");
		return false;
	}

	return true;
}

4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670
static void init_unused_ring(struct drm_device *dev, u32 base)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(RING_CTL(base), 0);
	I915_WRITE(RING_HEAD(base), 0);
	I915_WRITE(RING_TAIL(base), 0);
	I915_WRITE(RING_START(base), 0);
}

static void init_unused_rings(struct drm_device *dev)
{
	if (IS_I830(dev)) {
		init_unused_ring(dev, PRB1_BASE);
		init_unused_ring(dev, SRB0_BASE);
		init_unused_ring(dev, SRB1_BASE);
		init_unused_ring(dev, SRB2_BASE);
		init_unused_ring(dev, SRB3_BASE);
	} else if (IS_GEN2(dev)) {
		init_unused_ring(dev, SRB0_BASE);
		init_unused_ring(dev, SRB1_BASE);
	} else if (IS_GEN3(dev)) {
		init_unused_ring(dev, PRB1_BASE);
		init_unused_ring(dev, PRB2_BASE);
	}
}

4671
int i915_gem_init_rings(struct drm_device *dev)
4672
{
4673
	struct drm_i915_private *dev_priv = dev->dev_private;
4674
	int ret;
4675

4676 4677 4678 4679 4680 4681 4682 4683
	/*
	 * At least 830 can leave some of the unused rings
	 * "active" (ie. head != tail) after resume which
	 * will prevent c3 entry. Makes sure all unused rings
	 * are totally idle.
	 */
	init_unused_rings(dev);

4684
	ret = intel_init_render_ring_buffer(dev);
4685
	if (ret)
4686
		return ret;
4687 4688

	if (HAS_BSD(dev)) {
4689
		ret = intel_init_bsd_ring_buffer(dev);
4690 4691
		if (ret)
			goto cleanup_render_ring;
4692
	}
4693

4694
	if (intel_enable_blt(dev)) {
4695 4696 4697 4698 4699
		ret = intel_init_blt_ring_buffer(dev);
		if (ret)
			goto cleanup_bsd_ring;
	}

4700 4701 4702 4703 4704 4705
	if (HAS_VEBOX(dev)) {
		ret = intel_init_vebox_ring_buffer(dev);
		if (ret)
			goto cleanup_blt_ring;
	}

4706 4707 4708 4709 4710
	if (HAS_BSD2(dev)) {
		ret = intel_init_bsd2_ring_buffer(dev);
		if (ret)
			goto cleanup_vebox_ring;
	}
4711

4712
	ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4713
	if (ret)
4714
		goto cleanup_bsd2_ring;
4715 4716 4717

	return 0;

4718 4719
cleanup_bsd2_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4720 4721
cleanup_vebox_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734
cleanup_blt_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
cleanup_bsd_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
cleanup_render_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);

	return ret;
}

int
i915_gem_init_hw(struct drm_device *dev)
{
4735
	struct drm_i915_private *dev_priv = dev->dev_private;
4736
	int ret, i;
4737 4738 4739 4740

	if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
		return -EIO;

B
Ben Widawsky 已提交
4741
	if (dev_priv->ellc_size)
4742
		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4743

4744 4745 4746
	if (IS_HASWELL(dev))
		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4747

4748
	if (HAS_PCH_NOP(dev)) {
4749 4750 4751 4752 4753 4754 4755 4756 4757
		if (IS_IVYBRIDGE(dev)) {
			u32 temp = I915_READ(GEN7_MSG_CTL);
			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
			I915_WRITE(GEN7_MSG_CTL, temp);
		} else if (INTEL_INFO(dev)->gen >= 7) {
			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
		}
4758 4759
	}

4760 4761
	i915_gem_init_swizzling(dev);

4762
	ret = dev_priv->gt.init_rings(dev);
4763 4764 4765
	if (ret)
		return ret;

4766 4767 4768
	for (i = 0; i < NUM_L3_SLICES(dev); i++)
		i915_gem_l3_remap(&dev_priv->ring[RCS], i);

4769
	/*
4770 4771 4772 4773 4774
	 * XXX: Contexts should only be initialized once. Doing a switch to the
	 * default context switch however is something we'd like to do after
	 * reset or thaw (the latter may not actually be necessary for HW, but
	 * goes with our code better). Context switching requires rings (for
	 * the do_switch), but before enabling PPGTT. So don't move this.
4775
	 */
4776
	ret = i915_gem_context_enable(dev_priv);
4777
	if (ret && ret != -EIO) {
4778
		DRM_ERROR("Context enable failed %d\n", ret);
4779
		i915_gem_cleanup_ringbuffer(dev);
4780 4781 4782 4783 4784 4785 4786 4787

		return ret;
	}

	ret = i915_ppgtt_init_hw(dev);
	if (ret && ret != -EIO) {
		DRM_ERROR("PPGTT enable failed %d\n", ret);
		i915_gem_cleanup_ringbuffer(dev);
4788
	}
D
Daniel Vetter 已提交
4789

4790
	return ret;
4791 4792
}

4793 4794 4795 4796 4797
int i915_gem_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

4798 4799 4800
	i915.enable_execlists = intel_sanitize_enable_execlists(dev,
			i915.enable_execlists);

4801
	mutex_lock(&dev->struct_mutex);
4802 4803 4804

	if (IS_VALLEYVIEW(dev)) {
		/* VLVA0 (potential hack), BIOS isn't actually waking us */
4805 4806 4807
		I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
			      VLV_GTLC_ALLOWWAKEACK), 10))
4808 4809 4810
			DRM_DEBUG_DRIVER("allow wake ack timed out\n");
	}

4811 4812 4813 4814 4815
	if (!i915.enable_execlists) {
		dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
		dev_priv->gt.init_rings = i915_gem_init_rings;
		dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
		dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4816 4817 4818 4819 4820
	} else {
		dev_priv->gt.do_execbuf = intel_execlists_submission;
		dev_priv->gt.init_rings = intel_logical_rings_init;
		dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
		dev_priv->gt.stop_ring = intel_logical_ring_stop;
4821 4822
	}

4823 4824 4825 4826 4827 4828
	ret = i915_gem_init_userptr(dev);
	if (ret) {
		mutex_unlock(&dev->struct_mutex);
		return ret;
	}

4829
	i915_gem_init_global_gtt(dev);
4830

4831
	ret = i915_gem_context_init(dev);
4832 4833
	if (ret) {
		mutex_unlock(&dev->struct_mutex);
4834
		return ret;
4835
	}
4836

4837
	ret = i915_gem_init_hw(dev);
4838 4839 4840 4841 4842 4843 4844 4845
	if (ret == -EIO) {
		/* Allow ring initialisation to fail by marking the GPU as
		 * wedged. But we only want to do this where the GPU is angry,
		 * for all other failure, such as an allocation failure, bail.
		 */
		DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
		atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
		ret = 0;
4846
	}
4847
	mutex_unlock(&dev->struct_mutex);
4848

4849 4850 4851
	/* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		dev_priv->dri1.allow_batchbuffer = 1;
4852
	return ret;
4853 4854
}

4855 4856 4857
void
i915_gem_cleanup_ringbuffer(struct drm_device *dev)
{
4858
	struct drm_i915_private *dev_priv = dev->dev_private;
4859
	struct intel_engine_cs *ring;
4860
	int i;
4861

4862
	for_each_ring(ring, dev_priv, i)
4863
		dev_priv->gt.cleanup_ring(ring);
4864 4865
}

4866 4867 4868 4869
int
i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
4870
	struct drm_i915_private *dev_priv = dev->dev_private;
4871
	int ret;
4872

4873 4874 4875
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return 0;

4876
	if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4877
		DRM_ERROR("Reenabling wedged hardware, good luck\n");
4878
		atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4879 4880 4881
	}

	mutex_lock(&dev->struct_mutex);
4882
	dev_priv->ums.mm_suspended = 0;
4883

4884
	ret = i915_gem_init_hw(dev);
4885 4886
	if (ret != 0) {
		mutex_unlock(&dev->struct_mutex);
4887
		return ret;
4888
	}
4889

4890
	BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4891

4892
	ret = drm_irq_install(dev, dev->pdev->irq);
4893 4894
	if (ret)
		goto cleanup_ringbuffer;
4895
	mutex_unlock(&dev->struct_mutex);
4896

4897
	return 0;
4898 4899 4900

cleanup_ringbuffer:
	i915_gem_cleanup_ringbuffer(dev);
4901
	dev_priv->ums.mm_suspended = 1;
4902 4903 4904
	mutex_unlock(&dev->struct_mutex);

	return ret;
4905 4906 4907 4908 4909 4910
}

int
i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
4911 4912 4913
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return 0;

4914
	mutex_lock(&dev->struct_mutex);
4915
	drm_irq_uninstall(dev);
4916
	mutex_unlock(&dev->struct_mutex);
4917

4918
	return i915_gem_suspend(dev);
4919 4920 4921 4922 4923 4924 4925
}

void
i915_gem_lastclose(struct drm_device *dev)
{
	int ret;

4926 4927 4928
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return;

4929
	ret = i915_gem_suspend(dev);
4930 4931
	if (ret)
		DRM_ERROR("failed to idle hardware: %d\n", ret);
4932 4933
}

4934
static void
4935
init_ring_lists(struct intel_engine_cs *ring)
4936 4937 4938 4939 4940
{
	INIT_LIST_HEAD(&ring->active_list);
	INIT_LIST_HEAD(&ring->request_list);
}

4941 4942
void i915_init_vm(struct drm_i915_private *dev_priv,
		  struct i915_address_space *vm)
4943
{
4944 4945
	if (!i915_is_ggtt(vm))
		drm_mm_init(&vm->mm, vm->start, vm->total);
4946 4947 4948 4949
	vm->dev = dev_priv->dev;
	INIT_LIST_HEAD(&vm->active_list);
	INIT_LIST_HEAD(&vm->inactive_list);
	INIT_LIST_HEAD(&vm->global_link);
4950
	list_add_tail(&vm->global_link, &dev_priv->vm_list);
4951 4952
}

4953 4954 4955
void
i915_gem_load(struct drm_device *dev)
{
4956
	struct drm_i915_private *dev_priv = dev->dev_private;
4957 4958 4959 4960 4961 4962 4963
	int i;

	dev_priv->slab =
		kmem_cache_create("i915_gem_object",
				  sizeof(struct drm_i915_gem_object), 0,
				  SLAB_HWCACHE_ALIGN,
				  NULL);
4964

4965 4966 4967
	INIT_LIST_HEAD(&dev_priv->vm_list);
	i915_init_vm(dev_priv, &dev_priv->gtt.base);

4968
	INIT_LIST_HEAD(&dev_priv->context_list);
4969 4970
	INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
	INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4971
	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4972 4973
	for (i = 0; i < I915_NUM_RINGS; i++)
		init_ring_lists(&dev_priv->ring[i]);
4974
	for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4975
		INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4976 4977
	INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
			  i915_gem_retire_work_handler);
4978 4979
	INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
			  i915_gem_idle_work_handler);
4980
	init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4981

4982
	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4983
	if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4984 4985
		I915_WRITE(MI_ARB_STATE,
			   _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4986 4987
	}

4988 4989
	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;

4990
	/* Old X drivers will take 0-2 for front, back, depth buffers */
4991 4992
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		dev_priv->fence_reg_start = 3;
4993

4994 4995 4996
	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
		dev_priv->num_fence_regs = 32;
	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4997 4998 4999 5000
		dev_priv->num_fence_regs = 16;
	else
		dev_priv->num_fence_regs = 8;

5001
	/* Initialize fence registers to zero */
5002 5003
	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
	i915_gem_restore_fences(dev);
5004

5005
	i915_gem_detect_bit_6_swizzle(dev);
5006
	init_waitqueue_head(&dev_priv->pending_flip_queue);
5007

5008 5009
	dev_priv->mm.interruptible = true;

5010 5011 5012 5013
	dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
	dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
	dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
	register_shrinker(&dev_priv->mm.shrinker);
5014 5015 5016

	dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
	register_oom_notifier(&dev_priv->mm.oom_notifier);
5017 5018

	mutex_init(&dev_priv->fb_tracking.lock);
5019
}
5020

5021
void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5022
{
5023
	struct drm_i915_file_private *file_priv = file->driver_priv;
5024

5025 5026
	cancel_delayed_work_sync(&file_priv->mm.idle_work);

5027 5028 5029 5030
	/* Clean up our request list when the client is going away, so that
	 * later retire_requests won't dereference our soon-to-be-gone
	 * file_priv.
	 */
5031
	spin_lock(&file_priv->mm.lock);
5032 5033 5034 5035 5036 5037 5038 5039 5040
	while (!list_empty(&file_priv->mm.request_list)) {
		struct drm_i915_gem_request *request;

		request = list_first_entry(&file_priv->mm.request_list,
					   struct drm_i915_gem_request,
					   client_list);
		list_del(&request->client_list);
		request->file_priv = NULL;
	}
5041
	spin_unlock(&file_priv->mm.lock);
5042
}
5043

5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055
static void
i915_gem_file_idle_work_handler(struct work_struct *work)
{
	struct drm_i915_file_private *file_priv =
		container_of(work, typeof(*file_priv), mm.idle_work.work);

	atomic_set(&file_priv->rps_wait_boost, false);
}

int i915_gem_open(struct drm_device *dev, struct drm_file *file)
{
	struct drm_i915_file_private *file_priv;
5056
	int ret;
5057 5058 5059 5060 5061 5062 5063 5064 5065

	DRM_DEBUG_DRIVER("\n");

	file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
	if (!file_priv)
		return -ENOMEM;

	file->driver_priv = file_priv;
	file_priv->dev_priv = dev->dev_private;
5066
	file_priv->file = file;
5067 5068 5069 5070 5071 5072

	spin_lock_init(&file_priv->mm.lock);
	INIT_LIST_HEAD(&file_priv->mm.request_list);
	INIT_DELAYED_WORK(&file_priv->mm.idle_work,
			  i915_gem_file_idle_work_handler);

5073 5074 5075
	ret = i915_gem_context_open(dev, file);
	if (ret)
		kfree(file_priv);
5076

5077
	return ret;
5078 5079
}

5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096
void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits)
{
	if (old) {
		WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
		WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
		old->frontbuffer_bits &= ~frontbuffer_bits;
	}

	if (new) {
		WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
		WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
		new->frontbuffer_bits |= frontbuffer_bits;
	}
}

5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109
static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
{
	if (!mutex_is_locked(mutex))
		return false;

#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
	return mutex->owner == task;
#else
	/* Since UP may be pre-empted, we cannot assume that we own the lock */
	return false;
#endif
}

5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125
static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
{
	if (!mutex_trylock(&dev->struct_mutex)) {
		if (!mutex_is_locked_by(&dev->struct_mutex, current))
			return false;

		if (to_i915(dev)->mm.shrinker_no_lock_stealing)
			return false;

		*unlock = false;
	} else
		*unlock = true;

	return true;
}

5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137
static int num_vma_bound(struct drm_i915_gem_object *obj)
{
	struct i915_vma *vma;
	int count = 0;

	list_for_each_entry(vma, &obj->vma_list, vma_link)
		if (drm_mm_node_allocated(&vma->node))
			count++;

	return count;
}

5138
static unsigned long
5139
i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5140
{
5141
	struct drm_i915_private *dev_priv =
5142
		container_of(shrinker, struct drm_i915_private, mm.shrinker);
5143
	struct drm_device *dev = dev_priv->dev;
5144
	struct drm_i915_gem_object *obj;
5145
	unsigned long count;
5146
	bool unlock;
5147

5148 5149
	if (!i915_gem_shrinker_lock(dev, &unlock))
		return 0;
5150

5151
	count = 0;
5152
	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5153
		if (obj->pages_pin_count == 0)
5154
			count += obj->base.size >> PAGE_SHIFT;
5155 5156

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5157 5158
		if (!i915_gem_obj_is_pinned(obj) &&
		    obj->pages_pin_count == num_vma_bound(obj))
5159
			count += obj->base.size >> PAGE_SHIFT;
5160
	}
5161

5162 5163
	if (unlock)
		mutex_unlock(&dev->struct_mutex);
5164

5165
	return count;
5166
}
5167 5168 5169 5170 5171 5172 5173 5174

/* All the new VM stuff */
unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
				  struct i915_address_space *vm)
{
	struct drm_i915_private *dev_priv = o->base.dev->dev_private;
	struct i915_vma *vma;

5175
	WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5176 5177 5178 5179 5180 5181

	list_for_each_entry(vma, &o->vma_list, vma_link) {
		if (vma->vm == vm)
			return vma->node.start;

	}
5182 5183
	WARN(1, "%s vma for this object not found.\n",
	     i915_is_ggtt(vm) ? "global" : "ppgtt");
5184 5185 5186 5187 5188 5189 5190 5191 5192
	return -1;
}

bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
			struct i915_address_space *vm)
{
	struct i915_vma *vma;

	list_for_each_entry(vma, &o->vma_list, vma_link)
5193
		if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5194 5195 5196 5197 5198 5199 5200
			return true;

	return false;
}

bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
{
5201
	struct i915_vma *vma;
5202

5203 5204
	list_for_each_entry(vma, &o->vma_list, vma_link)
		if (drm_mm_node_allocated(&vma->node))
5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215
			return true;

	return false;
}

unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
				struct i915_address_space *vm)
{
	struct drm_i915_private *dev_priv = o->base.dev->dev_private;
	struct i915_vma *vma;

5216
	WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5217 5218 5219 5220 5221 5222 5223 5224 5225 5226

	BUG_ON(list_empty(&o->vma_list));

	list_for_each_entry(vma, &o->vma_list, vma_link)
		if (vma->vm == vm)
			return vma->node.size;

	return 0;
}

5227
static unsigned long
5228
i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5229 5230
{
	struct drm_i915_private *dev_priv =
5231
		container_of(shrinker, struct drm_i915_private, mm.shrinker);
5232 5233
	struct drm_device *dev = dev_priv->dev;
	unsigned long freed;
5234
	bool unlock;
5235

5236 5237
	if (!i915_gem_shrinker_lock(dev, &unlock))
		return SHRINK_STOP;
5238

5239 5240 5241 5242 5243
	freed = i915_gem_shrink(dev_priv,
				sc->nr_to_scan,
				I915_SHRINK_BOUND |
				I915_SHRINK_UNBOUND |
				I915_SHRINK_PURGEABLE);
5244
	if (freed < sc->nr_to_scan)
5245 5246 5247 5248
		freed += i915_gem_shrink(dev_priv,
					 sc->nr_to_scan - freed,
					 I915_SHRINK_BOUND |
					 I915_SHRINK_UNBOUND);
5249 5250
	if (unlock)
		mutex_unlock(&dev->struct_mutex);
5251

5252 5253
	return freed;
}
5254

5255 5256 5257 5258 5259 5260 5261 5262 5263 5264 5265 5266
static int
i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
{
	struct drm_i915_private *dev_priv =
		container_of(nb, struct drm_i915_private, mm.oom_notifier);
	struct drm_device *dev = dev_priv->dev;
	struct drm_i915_gem_object *obj;
	unsigned long timeout = msecs_to_jiffies(5000) + 1;
	unsigned long pinned, bound, unbound, freed;
	bool was_interruptible;
	bool unlock;

5267
	while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5268
		schedule_timeout_killable(1);
5269 5270 5271
		if (fatal_signal_pending(current))
			return NOTIFY_DONE;
	}
5272 5273 5274 5275 5276 5277 5278 5279 5280 5281 5282 5283 5284 5285 5286 5287 5288 5289 5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317 5318 5319 5320 5321
	if (timeout == 0) {
		pr_err("Unable to purge GPU memory due lock contention.\n");
		return NOTIFY_DONE;
	}

	was_interruptible = dev_priv->mm.interruptible;
	dev_priv->mm.interruptible = false;

	freed = i915_gem_shrink_all(dev_priv);

	dev_priv->mm.interruptible = was_interruptible;

	/* Because we may be allocating inside our own driver, we cannot
	 * assert that there are no objects with pinned pages that are not
	 * being pointed to by hardware.
	 */
	unbound = bound = pinned = 0;
	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
		if (!obj->base.filp) /* not backed by a freeable object */
			continue;

		if (obj->pages_pin_count)
			pinned += obj->base.size;
		else
			unbound += obj->base.size;
	}
	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
		if (!obj->base.filp)
			continue;

		if (obj->pages_pin_count)
			pinned += obj->base.size;
		else
			bound += obj->base.size;
	}

	if (unlock)
		mutex_unlock(&dev->struct_mutex);

	pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
		freed, pinned);
	if (unbound || bound)
		pr_err("%lu and %lu bytes still available in the "
		       "bound and unbound GPU page lists.\n",
		       bound, unbound);

	*(unsigned long *)ptr += freed;
	return NOTIFY_DONE;
}

5322 5323 5324 5325 5326
struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
{
	struct i915_vma *vma;

	vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5327
	if (vma->vm != i915_obj_to_ggtt(obj))
5328 5329 5330 5331
		return NULL;

	return vma;
}
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