i915_gem.c 121.7 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

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#include <drm/drmP.h>
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#include <drm/drm_vma_manager.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#include <linux/shmem_fs.h>
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#include <linux/slab.h>
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#include <linux/swap.h>
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#include <linux/pci.h>
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#include <linux/dma-buf.h>
39

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static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
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static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
						   bool force);
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static __must_check int
i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
			   struct i915_address_space *vm,
			   unsigned alignment,
			   bool map_and_fenceable,
			   bool nonblocking);
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static int i915_gem_phys_pwrite(struct drm_device *dev,
				struct drm_i915_gem_object *obj,
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				struct drm_i915_gem_pwrite *args,
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				struct drm_file *file);
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static void i915_gem_write_fence(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj);
static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
					 struct drm_i915_fence_reg *fence,
					 bool enable);

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static int i915_gem_inactive_shrink(struct shrinker *shrinker,
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				    struct shrink_control *sc);
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static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
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static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
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static bool cpu_cache_is_coherent(struct drm_device *dev,
				  enum i915_cache_level level)
{
	return HAS_LLC(dev) || level != I915_CACHE_NONE;
}

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static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
	if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
		return true;

	return obj->pin_display;
}

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static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
{
	if (obj->tiling_mode)
		i915_gem_release_mmap(obj);

	/* As we do not have an associated fence register, we will force
	 * a tiling change if we ever need to acquire one.
	 */
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	obj->fence_dirty = false;
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	obj->fence_reg = I915_FENCE_REG_NONE;
}

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/* some bookkeeping */
static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
				  size_t size)
{
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	spin_lock(&dev_priv->mm.object_stat_lock);
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	dev_priv->mm.object_count++;
	dev_priv->mm.object_memory += size;
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	spin_unlock(&dev_priv->mm.object_stat_lock);
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}

static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
				     size_t size)
{
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	spin_lock(&dev_priv->mm.object_stat_lock);
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	dev_priv->mm.object_count--;
	dev_priv->mm.object_memory -= size;
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	spin_unlock(&dev_priv->mm.object_stat_lock);
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}

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static int
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i915_gem_wait_for_error(struct i915_gpu_error *error)
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{
	int ret;

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#define EXIT_COND (!i915_reset_in_progress(error) || \
		   i915_terminally_wedged(error))
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	if (EXIT_COND)
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		return 0;

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	/*
	 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
	 * userspace. If it takes that long something really bad is going on and
	 * we should simply try to bail out and fail as gracefully as possible.
	 */
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	ret = wait_event_interruptible_timeout(error->reset_queue,
					       EXIT_COND,
					       10*HZ);
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	if (ret == 0) {
		DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
		return -EIO;
	} else if (ret < 0) {
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		return ret;
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	}
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#undef EXIT_COND
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137
	return 0;
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}

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int i915_mutex_lock_interruptible(struct drm_device *dev)
141
{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	int ret;

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	ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
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	if (ret)
		return ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

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	WARN_ON(i915_verify_lists(dev));
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	return 0;
}
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static inline bool
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i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
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{
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	return i915_gem_obj_bound_any(obj) && !obj->active;
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}

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int
i915_gem_init_ioctl(struct drm_device *dev, void *data,
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		    struct drm_file *file)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct drm_i915_gem_init *args = data;
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	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;

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	if (args->gtt_start >= args->gtt_end ||
	    (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
		return -EINVAL;
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	/* GEM with user mode setting was never supported on ilk and later. */
	if (INTEL_INFO(dev)->gen >= 5)
		return -ENODEV;

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	mutex_lock(&dev->struct_mutex);
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	i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
				  args->gtt_end);
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	dev_priv->gtt.mappable_end = args->gtt_end;
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	mutex_unlock(&dev->struct_mutex);

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	return 0;
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}

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int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
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			    struct drm_file *file)
193
{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct drm_i915_gem_get_aperture *args = data;
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	struct drm_i915_gem_object *obj;
	size_t pinned;
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	pinned = 0;
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	mutex_lock(&dev->struct_mutex);
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	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
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		if (obj->pin_count)
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			pinned += i915_gem_obj_ggtt_size(obj);
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	mutex_unlock(&dev->struct_mutex);
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	args->aper_size = dev_priv->gtt.base.total;
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	args->aper_available_size = args->aper_size - pinned;
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	return 0;
}

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void *i915_gem_object_alloc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
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}

void i915_gem_object_free(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	kmem_cache_free(dev_priv->slab, obj);
}

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static int
i915_gem_create(struct drm_file *file,
		struct drm_device *dev,
		uint64_t size,
		uint32_t *handle_p)
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{
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	struct drm_i915_gem_object *obj;
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	int ret;
	u32 handle;
233

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	size = roundup(size, PAGE_SIZE);
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	if (size == 0)
		return -EINVAL;
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	/* Allocate the new object */
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	obj = i915_gem_alloc_object(dev, size);
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	if (obj == NULL)
		return -ENOMEM;

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	ret = drm_gem_handle_create(file, &obj->base, &handle);
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	/* drop reference from allocate - handle holds it now */
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	drm_gem_object_unreference_unlocked(&obj->base);
	if (ret)
		return ret;
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	*handle_p = handle;
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	return 0;
}

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int
i915_gem_dumb_create(struct drm_file *file,
		     struct drm_device *dev,
		     struct drm_mode_create_dumb *args)
{
	/* have to work out size/pitch and return them */
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	args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
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	args->size = args->pitch * args->height;
	return i915_gem_create(file, dev,
			       args->size, &args->handle);
}

/**
 * Creates a new mm object and returns a handle to it.
 */
int
i915_gem_create_ioctl(struct drm_device *dev, void *data,
		      struct drm_file *file)
{
	struct drm_i915_gem_create *args = data;
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	return i915_gem_create(file, dev,
			       args->size, &args->handle);
}

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static inline int
__copy_to_user_swizzled(char __user *cpu_vaddr,
			const char *gpu_vaddr, int gpu_offset,
			int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_to_user(cpu_vaddr + cpu_offset,
				     gpu_vaddr + swizzled_gpu_offset,
				     this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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static inline int
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__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
			  const char __user *cpu_vaddr,
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			  int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
				       cpu_vaddr + cpu_offset,
				       this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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/* Per-page copy function for the shmem pread fastpath.
 * Flushes invalid cachelines before reading the target if
 * needs_clflush is set. */
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static int
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shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;

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	if (unlikely(page_do_bit17_swizzling))
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		return -EINVAL;

	vaddr = kmap_atomic(page);
	if (needs_clflush)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	ret = __copy_to_user_inatomic(user_data,
				      vaddr + shmem_page_offset,
				      page_length);
	kunmap_atomic(vaddr);

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	return ret ? -EFAULT : 0;
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}

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static void
shmem_clflush_swizzled_range(char *addr, unsigned long length,
			     bool swizzled)
{
360
	if (unlikely(swizzled)) {
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		unsigned long start = (unsigned long) addr;
		unsigned long end = (unsigned long) addr + length;

		/* For swizzling simply ensure that we always flush both
		 * channels. Lame, but simple and it works. Swizzled
		 * pwrite/pread is far from a hotpath - current userspace
		 * doesn't use it at all. */
		start = round_down(start, 128);
		end = round_up(end, 128);

		drm_clflush_virt_range((void *)start, end - start);
	} else {
		drm_clflush_virt_range(addr, length);
	}

}

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/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
static int
shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;

	vaddr = kmap(page);
	if (needs_clflush)
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		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
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	if (page_do_bit17_swizzling)
		ret = __copy_to_user_swizzled(user_data,
					      vaddr, shmem_page_offset,
					      page_length);
	else
		ret = __copy_to_user(user_data,
				     vaddr + shmem_page_offset,
				     page_length);
	kunmap(page);

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	return ret ? - EFAULT : 0;
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}

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static int
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i915_gem_shmem_pread(struct drm_device *dev,
		     struct drm_i915_gem_object *obj,
		     struct drm_i915_gem_pread *args,
		     struct drm_file *file)
412
{
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	char __user *user_data;
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	ssize_t remain;
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	loff_t offset;
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	int shmem_page_offset, page_length, ret = 0;
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	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
418
	int prefaulted = 0;
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	int needs_clflush = 0;
420
	struct sg_page_iter sg_iter;
421

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	user_data = to_user_ptr(args->data_ptr);
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	remain = args->size;

425
	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
426

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	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
		/* If we're not in the cpu read domain, set ourself into the gtt
		 * read domain and manually flush cachelines (if required). This
		 * optimizes for the case when the gpu will dirty the data
		 * anyway again before the next pread happens. */
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		needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
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		if (i915_gem_obj_bound_any(obj)) {
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			ret = i915_gem_object_set_to_gtt_domain(obj, false);
			if (ret)
				return ret;
		}
438
	}
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	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ret;

	i915_gem_object_pin_pages(obj);

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	offset = args->offset;
447

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	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
			 offset >> PAGE_SHIFT) {
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		struct page *page = sg_page_iter_page(&sg_iter);
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		if (remain <= 0)
			break;

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		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
460
		shmem_page_offset = offset_in_page(offset);
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		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;

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		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;

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		ret = shmem_pread_fast(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
		if (ret == 0)
			goto next_page;
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		mutex_unlock(&dev->struct_mutex);

476
		if (likely(!i915_prefault_disable) && !prefaulted) {
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			ret = fault_in_multipages_writeable(user_data, remain);
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			/* Userspace is tricking us, but we've already clobbered
			 * its pages with the prefault and promised to write the
			 * data up to the first fault. Hence ignore any errors
			 * and just continue. */
			(void)ret;
			prefaulted = 1;
		}
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		ret = shmem_pread_slow(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
489

490
		mutex_lock(&dev->struct_mutex);
491

492
next_page:
493 494
		mark_page_accessed(page);

495
		if (ret)
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			goto out;

498
		remain -= page_length;
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		user_data += page_length;
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		offset += page_length;
	}

503
out:
504 505
	i915_gem_object_unpin_pages(obj);

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	return ret;
}

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/**
 * Reads data from the object referenced by handle.
 *
 * On error, the contents of *data are undefined.
 */
int
i915_gem_pread_ioctl(struct drm_device *dev, void *data,
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		     struct drm_file *file)
517 518
{
	struct drm_i915_gem_pread *args = data;
519
	struct drm_i915_gem_object *obj;
520
	int ret = 0;
521

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	if (args->size == 0)
		return 0;

	if (!access_ok(VERIFY_WRITE,
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		       to_user_ptr(args->data_ptr),
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		       args->size))
		return -EFAULT;

530
	ret = i915_mutex_lock_interruptible(dev);
531
	if (ret)
532
		return ret;
533

534
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
535
	if (&obj->base == NULL) {
536 537
		ret = -ENOENT;
		goto unlock;
538
	}
539

540
	/* Bounds check source.  */
541 542
	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
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		ret = -EINVAL;
544
		goto out;
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	}

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	/* prime objects have no backing filp to GEM pread/pwrite
	 * pages from.
	 */
	if (!obj->base.filp) {
		ret = -EINVAL;
		goto out;
	}

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	trace_i915_gem_object_pread(obj, args->offset, args->size);

557
	ret = i915_gem_shmem_pread(dev, obj, args, file);
558

559
out:
560
	drm_gem_object_unreference(&obj->base);
561
unlock:
562
	mutex_unlock(&dev->struct_mutex);
563
	return ret;
564 565
}

566 567
/* This is the fast write path which cannot handle
 * page faults in the source data
568
 */
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static inline int
fast_user_write(struct io_mapping *mapping,
		loff_t page_base, int page_offset,
		char __user *user_data,
		int length)
575
{
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	void __iomem *vaddr_atomic;
	void *vaddr;
578
	unsigned long unwritten;
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	vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
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	/* We can use the cpu mem copy function because this is X86. */
	vaddr = (void __force*)vaddr_atomic + page_offset;
	unwritten = __copy_from_user_inatomic_nocache(vaddr,
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						      user_data, length);
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	io_mapping_unmap_atomic(vaddr_atomic);
586
	return unwritten;
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}

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/**
 * This is the fast pwrite path, where we copy the data directly from the
 * user into the GTT, uncached.
 */
593
static int
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i915_gem_gtt_pwrite_fast(struct drm_device *dev,
			 struct drm_i915_gem_object *obj,
596
			 struct drm_i915_gem_pwrite *args,
597
			 struct drm_file *file)
598
{
599
	drm_i915_private_t *dev_priv = dev->dev_private;
600
	ssize_t remain;
601
	loff_t offset, page_base;
602
	char __user *user_data;
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	int page_offset, page_length, ret;

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	ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
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	if (ret)
		goto out;

	ret = i915_gem_object_set_to_gtt_domain(obj, true);
	if (ret)
		goto out_unpin;

	ret = i915_gem_object_put_fence(obj);
	if (ret)
		goto out_unpin;
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	user_data = to_user_ptr(args->data_ptr);
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	remain = args->size;

620
	offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
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	while (remain > 0) {
		/* Operation in this page
		 *
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		 * page_base = page offset within aperture
		 * page_offset = offset within page
		 * page_length = bytes to copy for this page
628
		 */
629 630
		page_base = offset & PAGE_MASK;
		page_offset = offset_in_page(offset);
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		page_length = remain;
		if ((page_offset + remain) > PAGE_SIZE)
			page_length = PAGE_SIZE - page_offset;

		/* If we get a fault while copying data, then (presumably) our
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		 * source page isn't available.  Return the error and we'll
		 * retry in the slow path.
638
		 */
B
Ben Widawsky 已提交
639
		if (fast_user_write(dev_priv->gtt.mappable, page_base,
D
Daniel Vetter 已提交
640 641 642 643
				    page_offset, user_data, page_length)) {
			ret = -EFAULT;
			goto out_unpin;
		}
644

645 646 647
		remain -= page_length;
		user_data += page_length;
		offset += page_length;
648 649
	}

D
Daniel Vetter 已提交
650 651 652
out_unpin:
	i915_gem_object_unpin(obj);
out:
653
	return ret;
654 655
}

656 657 658 659
/* Per-page copy function for the shmem pwrite fastpath.
 * Flushes invalid cachelines before writing to the target if
 * needs_clflush_before is set and flushes out any written cachelines after
 * writing if needs_clflush is set. */
660
static int
661 662 663 664 665
shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
666
{
667
	char *vaddr;
668
	int ret;
669

670
	if (unlikely(page_do_bit17_swizzling))
671
		return -EINVAL;
672

673 674 675 676 677 678 679 680 681 682 683
	vaddr = kmap_atomic(page);
	if (needs_clflush_before)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
						user_data,
						page_length);
	if (needs_clflush_after)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	kunmap_atomic(vaddr);
684

685
	return ret ? -EFAULT : 0;
686 687
}

688 689
/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
690
static int
691 692 693 694 695
shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
696
{
697 698
	char *vaddr;
	int ret;
699

700
	vaddr = kmap(page);
701
	if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
702 703 704
		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
705 706
	if (page_do_bit17_swizzling)
		ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
707 708
						user_data,
						page_length);
709 710 711 712 713
	else
		ret = __copy_from_user(vaddr + shmem_page_offset,
				       user_data,
				       page_length);
	if (needs_clflush_after)
714 715 716
		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
717
	kunmap(page);
718

719
	return ret ? -EFAULT : 0;
720 721 722
}

static int
723 724 725 726
i915_gem_shmem_pwrite(struct drm_device *dev,
		      struct drm_i915_gem_object *obj,
		      struct drm_i915_gem_pwrite *args,
		      struct drm_file *file)
727 728
{
	ssize_t remain;
729 730
	loff_t offset;
	char __user *user_data;
731
	int shmem_page_offset, page_length, ret = 0;
732
	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
733
	int hit_slowpath = 0;
734 735
	int needs_clflush_after = 0;
	int needs_clflush_before = 0;
736
	struct sg_page_iter sg_iter;
737

V
Ville Syrjälä 已提交
738
	user_data = to_user_ptr(args->data_ptr);
739 740
	remain = args->size;

741
	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
742

743 744 745 746 747
	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
		/* If we're not in the cpu write domain, set ourself into the gtt
		 * write domain and manually flush cachelines (if required). This
		 * optimizes for the case when the gpu will use the data
		 * right away and we therefore have to clflush anyway. */
748
		needs_clflush_after = cpu_write_needs_clflush(obj);
749
		if (i915_gem_obj_bound_any(obj)) {
C
Chris Wilson 已提交
750 751 752 753
			ret = i915_gem_object_set_to_gtt_domain(obj, true);
			if (ret)
				return ret;
		}
754
	}
755 756 757 758 759
	/* Same trick applies to invalidate partially written cachelines read
	 * before writing. */
	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
		needs_clflush_before =
			!cpu_cache_is_coherent(dev, obj->cache_level);
760

761 762 763 764 765 766
	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ret;

	i915_gem_object_pin_pages(obj);

767
	offset = args->offset;
768
	obj->dirty = 1;
769

770 771
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
			 offset >> PAGE_SHIFT) {
772
		struct page *page = sg_page_iter_page(&sg_iter);
773
		int partial_cacheline_write;
774

775 776 777
		if (remain <= 0)
			break;

778 779 780 781 782
		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
783
		shmem_page_offset = offset_in_page(offset);
784 785 786 787 788

		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;

789 790 791 792 793 794 795
		/* If we don't overwrite a cacheline completely we need to be
		 * careful to have up-to-date data by first clflushing. Don't
		 * overcomplicate things and flush the entire patch. */
		partial_cacheline_write = needs_clflush_before &&
			((shmem_page_offset | page_length)
				& (boot_cpu_data.x86_clflush_size - 1));

796 797 798
		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;

799 800 801 802 803 804
		ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
					user_data, page_do_bit17_swizzling,
					partial_cacheline_write,
					needs_clflush_after);
		if (ret == 0)
			goto next_page;
805 806 807

		hit_slowpath = 1;
		mutex_unlock(&dev->struct_mutex);
808 809 810 811
		ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
					user_data, page_do_bit17_swizzling,
					partial_cacheline_write,
					needs_clflush_after);
812

813
		mutex_lock(&dev->struct_mutex);
814

815
next_page:
816 817 818
		set_page_dirty(page);
		mark_page_accessed(page);

819
		if (ret)
820 821
			goto out;

822
		remain -= page_length;
823
		user_data += page_length;
824
		offset += page_length;
825 826
	}

827
out:
828 829
	i915_gem_object_unpin_pages(obj);

830
	if (hit_slowpath) {
831 832 833 834 835 836 837
		/*
		 * Fixup: Flush cpu caches in case we didn't flush the dirty
		 * cachelines in-line while writing and the object moved
		 * out of the cpu write domain while we've dropped the lock.
		 */
		if (!needs_clflush_after &&
		    obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
838 839
			if (i915_gem_clflush_object(obj, obj->pin_display))
				i915_gem_chipset_flush(dev);
840
		}
841
	}
842

843
	if (needs_clflush_after)
844
		i915_gem_chipset_flush(dev);
845

846
	return ret;
847 848 849 850 851 852 853 854 855
}

/**
 * Writes data to the object referenced by handle.
 *
 * On error, the contents of the buffer that were to be modified are undefined.
 */
int
i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
856
		      struct drm_file *file)
857 858
{
	struct drm_i915_gem_pwrite *args = data;
859
	struct drm_i915_gem_object *obj;
860 861 862 863 864 865
	int ret;

	if (args->size == 0)
		return 0;

	if (!access_ok(VERIFY_READ,
V
Ville Syrjälä 已提交
866
		       to_user_ptr(args->data_ptr),
867 868 869
		       args->size))
		return -EFAULT;

870 871 872 873 874 875
	if (likely(!i915_prefault_disable)) {
		ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
						   args->size);
		if (ret)
			return -EFAULT;
	}
876

877
	ret = i915_mutex_lock_interruptible(dev);
878
	if (ret)
879
		return ret;
880

881
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
882
	if (&obj->base == NULL) {
883 884
		ret = -ENOENT;
		goto unlock;
885
	}
886

887
	/* Bounds check destination. */
888 889
	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
C
Chris Wilson 已提交
890
		ret = -EINVAL;
891
		goto out;
C
Chris Wilson 已提交
892 893
	}

894 895 896 897 898 899 900 901
	/* prime objects have no backing filp to GEM pread/pwrite
	 * pages from.
	 */
	if (!obj->base.filp) {
		ret = -EINVAL;
		goto out;
	}

C
Chris Wilson 已提交
902 903
	trace_i915_gem_object_pwrite(obj, args->offset, args->size);

D
Daniel Vetter 已提交
904
	ret = -EFAULT;
905 906 907 908 909 910
	/* We can only do the GTT pwrite on untiled buffers, as otherwise
	 * it would end up going through the fenced access, and we'll get
	 * different detiling behavior between reading and writing.
	 * pread/pwrite currently are reading and writing from the CPU
	 * perspective, requiring manual detiling by the client.
	 */
911
	if (obj->phys_obj) {
912
		ret = i915_gem_phys_pwrite(dev, obj, args, file);
913 914 915
		goto out;
	}

916 917 918
	if (obj->tiling_mode == I915_TILING_NONE &&
	    obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
	    cpu_write_needs_clflush(obj)) {
919
		ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
D
Daniel Vetter 已提交
920 921 922
		/* Note that the gtt paths might fail with non-page-backed user
		 * pointers (e.g. gtt mappings when moving data between
		 * textures). Fallback to the shmem path in that case. */
923
	}
924

925
	if (ret == -EFAULT || ret == -ENOSPC)
D
Daniel Vetter 已提交
926
		ret = i915_gem_shmem_pwrite(dev, obj, args, file);
927

928
out:
929
	drm_gem_object_unreference(&obj->base);
930
unlock:
931
	mutex_unlock(&dev->struct_mutex);
932 933 934
	return ret;
}

935
int
936
i915_gem_check_wedge(struct i915_gpu_error *error,
937 938
		     bool interruptible)
{
939
	if (i915_reset_in_progress(error)) {
940 941 942 943 944
		/* Non-interruptible callers can't handle -EAGAIN, hence return
		 * -EIO unconditionally for these. */
		if (!interruptible)
			return -EIO;

945 946
		/* Recovery complete, but the reset failed ... */
		if (i915_terminally_wedged(error))
947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967
			return -EIO;

		return -EAGAIN;
	}

	return 0;
}

/*
 * Compare seqno against outstanding lazy request. Emit a request if they are
 * equal.
 */
static int
i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
{
	int ret;

	BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));

	ret = 0;
	if (seqno == ring->outstanding_lazy_request)
968
		ret = i915_add_request(ring, NULL);
969 970 971 972 973 974 975 976

	return ret;
}

/**
 * __wait_seqno - wait until execution of seqno has finished
 * @ring: the ring expected to report seqno
 * @seqno: duh!
977
 * @reset_counter: reset sequence associated with the given seqno
978 979 980
 * @interruptible: do an interruptible wait (normally yes)
 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 *
981 982 983 984 985 986 987
 * Note: It is of utmost importance that the passed in seqno and reset_counter
 * values have been read by the caller in an smp safe manner. Where read-side
 * locks are involved, it is sufficient to read the reset_counter before
 * unlocking the lock that protects the seqno. For lockless tricks, the
 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
 * inserted.
 *
988 989 990 991
 * Returns 0 if the seqno was found within the alloted time. Else returns the
 * errno with remaining time filled in timeout argument.
 */
static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
992
			unsigned reset_counter,
993 994 995 996 997 998 999 1000 1001
			bool interruptible, struct timespec *timeout)
{
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	struct timespec before, now, wait_time={1,0};
	unsigned long timeout_jiffies;
	long end;
	bool wait_forever = true;
	int ret;

1002 1003
	WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");

1004 1005 1006 1007 1008 1009 1010 1011 1012 1013
	if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
		return 0;

	trace_i915_gem_request_wait_begin(ring, seqno);

	if (timeout != NULL) {
		wait_time = *timeout;
		wait_forever = false;
	}

1014
	timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1015 1016 1017 1018 1019 1020 1021 1022 1023

	if (WARN_ON(!ring->irq_get(ring)))
		return -ENODEV;

	/* Record current time in case interrupted by signal, or wedged * */
	getrawmonotonic(&before);

#define EXIT_COND \
	(i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1024 1025
	 i915_reset_in_progress(&dev_priv->gpu_error) || \
	 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1026 1027 1028 1029 1030 1031 1032 1033 1034
	do {
		if (interruptible)
			end = wait_event_interruptible_timeout(ring->irq_queue,
							       EXIT_COND,
							       timeout_jiffies);
		else
			end = wait_event_timeout(ring->irq_queue, EXIT_COND,
						 timeout_jiffies);

1035 1036 1037 1038 1039 1040 1041
		/* We need to check whether any gpu reset happened in between
		 * the caller grabbing the seqno and now ... */
		if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
			end = -EAGAIN;

		/* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
		 * gone. */
1042
		ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055
		if (ret)
			end = ret;
	} while (end == 0 && wait_forever);

	getrawmonotonic(&now);

	ring->irq_put(ring);
	trace_i915_gem_request_wait_end(ring, seqno);
#undef EXIT_COND

	if (timeout) {
		struct timespec sleep_time = timespec_sub(now, before);
		*timeout = timespec_sub(*timeout, sleep_time);
1056 1057
		if (!timespec_valid(timeout)) /* i.e. negative time remains */
			set_normalized_timespec(timeout, 0, 0);
1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087
	}

	switch (end) {
	case -EIO:
	case -EAGAIN: /* Wedged */
	case -ERESTARTSYS: /* Signal */
		return (int)end;
	case 0: /* Timeout */
		return -ETIME;
	default: /* Completed */
		WARN_ON(end < 0); /* We're not aware of other errors */
		return 0;
	}
}

/**
 * Waits for a sequence number to be signaled, and cleans up the
 * request and object lists appropriately for that event.
 */
int
i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool interruptible = dev_priv->mm.interruptible;
	int ret;

	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
	BUG_ON(seqno == 0);

1088
	ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1089 1090 1091 1092 1093 1094 1095
	if (ret)
		return ret;

	ret = i915_gem_check_olr(ring, seqno);
	if (ret)
		return ret;

1096 1097 1098
	return __wait_seqno(ring, seqno,
			    atomic_read(&dev_priv->gpu_error.reset_counter),
			    interruptible, NULL);
1099 1100
}

1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119
static int
i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
				     struct intel_ring_buffer *ring)
{
	i915_gem_retire_requests_ring(ring);

	/* Manually manage the write flush as we may have not yet
	 * retired the buffer.
	 *
	 * Note that the last_write_seqno is always the earlier of
	 * the two (read/write) seqno, so if we haved successfully waited,
	 * we know we have passed the last write.
	 */
	obj->last_write_seqno = 0;
	obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;

	return 0;
}

1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139
/**
 * Ensures that all rendering to the object has completed and the object is
 * safe to unbind from the GTT or access from the CPU.
 */
static __must_check int
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly)
{
	struct intel_ring_buffer *ring = obj->ring;
	u32 seqno;
	int ret;

	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
	if (seqno == 0)
		return 0;

	ret = i915_wait_seqno(ring, seqno);
	if (ret)
		return ret;

1140
	return i915_gem_object_wait_rendering__tail(obj, ring);
1141 1142
}

1143 1144 1145 1146 1147 1148 1149 1150 1151 1152
/* A nonblocking variant of the above wait. This is a highly dangerous routine
 * as the object state may change during this call.
 */
static __must_check int
i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
					    bool readonly)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring = obj->ring;
1153
	unsigned reset_counter;
1154 1155 1156 1157 1158 1159 1160 1161 1162 1163
	u32 seqno;
	int ret;

	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
	BUG_ON(!dev_priv->mm.interruptible);

	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
	if (seqno == 0)
		return 0;

1164
	ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1165 1166 1167 1168 1169 1170 1171
	if (ret)
		return ret;

	ret = i915_gem_check_olr(ring, seqno);
	if (ret)
		return ret;

1172
	reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1173
	mutex_unlock(&dev->struct_mutex);
1174
	ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1175
	mutex_lock(&dev->struct_mutex);
1176 1177
	if (ret)
		return ret;
1178

1179
	return i915_gem_object_wait_rendering__tail(obj, ring);
1180 1181
}

1182
/**
1183 1184
 * Called when user space prepares to use an object with the CPU, either
 * through the mmap ioctl's mapping or a GTT mapping.
1185 1186 1187
 */
int
i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1188
			  struct drm_file *file)
1189 1190
{
	struct drm_i915_gem_set_domain *args = data;
1191
	struct drm_i915_gem_object *obj;
1192 1193
	uint32_t read_domains = args->read_domains;
	uint32_t write_domain = args->write_domain;
1194 1195
	int ret;

1196
	/* Only handle setting domains to types used by the CPU. */
1197
	if (write_domain & I915_GEM_GPU_DOMAINS)
1198 1199
		return -EINVAL;

1200
	if (read_domains & I915_GEM_GPU_DOMAINS)
1201 1202 1203 1204 1205 1206 1207 1208
		return -EINVAL;

	/* Having something in the write domain implies it's in the read
	 * domain, and only that read domain.  Enforce that in the request.
	 */
	if (write_domain != 0 && read_domains != write_domain)
		return -EINVAL;

1209
	ret = i915_mutex_lock_interruptible(dev);
1210
	if (ret)
1211
		return ret;
1212

1213
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1214
	if (&obj->base == NULL) {
1215 1216
		ret = -ENOENT;
		goto unlock;
1217
	}
1218

1219 1220 1221 1222 1223 1224 1225 1226
	/* Try to flush the object off the GPU without holding the lock.
	 * We will repeat the flush holding the lock in the normal manner
	 * to catch cases where we are gazumped.
	 */
	ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
	if (ret)
		goto unref;

1227 1228
	if (read_domains & I915_GEM_DOMAIN_GTT) {
		ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1229 1230 1231 1232 1233 1234 1235

		/* Silently promote "you're not bound, there was nothing to do"
		 * to success, since the client was just asking us to
		 * make sure everything was done.
		 */
		if (ret == -EINVAL)
			ret = 0;
1236
	} else {
1237
		ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1238 1239
	}

1240
unref:
1241
	drm_gem_object_unreference(&obj->base);
1242
unlock:
1243 1244 1245 1246 1247 1248 1249 1250 1251
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
 * Called when user space has done writes to this buffer
 */
int
i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1252
			 struct drm_file *file)
1253 1254
{
	struct drm_i915_gem_sw_finish *args = data;
1255
	struct drm_i915_gem_object *obj;
1256 1257
	int ret = 0;

1258
	ret = i915_mutex_lock_interruptible(dev);
1259
	if (ret)
1260
		return ret;
1261

1262
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1263
	if (&obj->base == NULL) {
1264 1265
		ret = -ENOENT;
		goto unlock;
1266 1267 1268
	}

	/* Pinned buffers may be scanout, so flush the cache */
1269 1270
	if (obj->pin_display)
		i915_gem_object_flush_cpu_write_domain(obj, true);
1271

1272
	drm_gem_object_unreference(&obj->base);
1273
unlock:
1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
 * Maps the contents of an object, returning the address it is mapped
 * into.
 *
 * While the mapping holds a reference on the contents of the object, it doesn't
 * imply a ref on the object itself.
 */
int
i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1287
		    struct drm_file *file)
1288 1289 1290 1291 1292
{
	struct drm_i915_gem_mmap *args = data;
	struct drm_gem_object *obj;
	unsigned long addr;

1293
	obj = drm_gem_object_lookup(dev, file, args->handle);
1294
	if (obj == NULL)
1295
		return -ENOENT;
1296

1297 1298 1299 1300 1301 1302 1303 1304
	/* prime objects have no backing filp to GEM mmap
	 * pages from.
	 */
	if (!obj->filp) {
		drm_gem_object_unreference_unlocked(obj);
		return -EINVAL;
	}

1305
	addr = vm_mmap(obj->filp, 0, args->size,
1306 1307
		       PROT_READ | PROT_WRITE, MAP_SHARED,
		       args->offset);
1308
	drm_gem_object_unreference_unlocked(obj);
1309 1310 1311 1312 1313 1314 1315 1316
	if (IS_ERR((void *)addr))
		return addr;

	args->addr_ptr = (uint64_t) addr;

	return 0;
}

1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334
/**
 * i915_gem_fault - fault a page into the GTT
 * vma: VMA in question
 * vmf: fault info
 *
 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
 * from userspace.  The fault handler takes care of binding the object to
 * the GTT (if needed), allocating and programming a fence register (again,
 * only if needed based on whether the old reg is still valid or the object
 * is tiled) and inserting a new PTE into the faulting process.
 *
 * Note that the faulting process may involve evicting existing objects
 * from the GTT and/or fence registers to make room.  So performance may
 * suffer if the GTT working set is large or there are few fence registers
 * left.
 */
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
{
1335 1336
	struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
	struct drm_device *dev = obj->base.dev;
1337
	drm_i915_private_t *dev_priv = dev->dev_private;
1338 1339 1340
	pgoff_t page_offset;
	unsigned long pfn;
	int ret = 0;
1341
	bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1342 1343 1344 1345 1346

	/* We don't use vmf->pgoff since that has the fake offset */
	page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
		PAGE_SHIFT;

1347 1348 1349
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		goto out;
1350

C
Chris Wilson 已提交
1351 1352
	trace_i915_gem_object_fault(obj, page_offset, true, write);

1353 1354 1355 1356 1357 1358
	/* Access to snoopable pages through the GTT is incoherent. */
	if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
		ret = -EINVAL;
		goto unlock;
	}

1359
	/* Now bind it into the GTT if needed */
B
Ben Widawsky 已提交
1360
	ret = i915_gem_obj_ggtt_pin(obj,  0, true, false);
1361 1362
	if (ret)
		goto unlock;
1363

1364 1365 1366
	ret = i915_gem_object_set_to_gtt_domain(obj, write);
	if (ret)
		goto unpin;
1367

1368
	ret = i915_gem_object_get_fence(obj);
1369
	if (ret)
1370
		goto unpin;
1371

1372 1373
	obj->fault_mappable = true;

1374 1375 1376
	pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
	pfn >>= PAGE_SHIFT;
	pfn += page_offset;
1377 1378 1379

	/* Finally, remap it using the new GTT offset */
	ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1380 1381
unpin:
	i915_gem_object_unpin(obj);
1382
unlock:
1383
	mutex_unlock(&dev->struct_mutex);
1384
out:
1385
	switch (ret) {
1386
	case -EIO:
1387 1388 1389
		/* If this -EIO is due to a gpu hang, give the reset code a
		 * chance to clean up the mess. Otherwise return the proper
		 * SIGBUS. */
1390
		if (i915_terminally_wedged(&dev_priv->gpu_error))
1391
			return VM_FAULT_SIGBUS;
1392
	case -EAGAIN:
1393 1394 1395 1396 1397 1398 1399
		/* Give the error handler a chance to run and move the
		 * objects off the GPU active list. Next time we service the
		 * fault, we should be able to transition the page into the
		 * GTT without touching the GPU (and so avoid further
		 * EIO/EGAIN). If the GPU is wedged, then there is no issue
		 * with coherency, just lost writes.
		 */
1400
		set_need_resched();
1401 1402
	case 0:
	case -ERESTARTSYS:
1403
	case -EINTR:
1404 1405 1406 1407 1408
	case -EBUSY:
		/*
		 * EBUSY is ok: this just means that another thread
		 * already did the job.
		 */
1409
		return VM_FAULT_NOPAGE;
1410 1411
	case -ENOMEM:
		return VM_FAULT_OOM;
1412 1413
	case -ENOSPC:
		return VM_FAULT_SIGBUS;
1414
	default:
1415
		WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1416
		return VM_FAULT_SIGBUS;
1417 1418 1419
	}
}

1420 1421 1422 1423
/**
 * i915_gem_release_mmap - remove physical page mappings
 * @obj: obj in question
 *
1424
 * Preserve the reservation of the mmapping with the DRM core code, but
1425 1426 1427 1428 1429 1430 1431 1432 1433
 * relinquish ownership of the pages back to the system.
 *
 * It is vital that we remove the page mapping if we have mapped a tiled
 * object through the GTT and then lose the fence register due to
 * resource pressure. Similarly if the object has been moved out of the
 * aperture, than pages mapped into userspace must be revoked. Removing the
 * mapping will then trigger a page fault on the next user access, allowing
 * fixup by i915_gem_fault().
 */
1434
void
1435
i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1436
{
1437 1438
	if (!obj->fault_mappable)
		return;
1439

1440
	drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
1441
	obj->fault_mappable = false;
1442 1443
}

1444
uint32_t
1445
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1446
{
1447
	uint32_t gtt_size;
1448 1449

	if (INTEL_INFO(dev)->gen >= 4 ||
1450 1451
	    tiling_mode == I915_TILING_NONE)
		return size;
1452 1453 1454

	/* Previous chips need a power-of-two fence region when tiling */
	if (INTEL_INFO(dev)->gen == 3)
1455
		gtt_size = 1024*1024;
1456
	else
1457
		gtt_size = 512*1024;
1458

1459 1460
	while (gtt_size < size)
		gtt_size <<= 1;
1461

1462
	return gtt_size;
1463 1464
}

1465 1466 1467 1468 1469
/**
 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
 * @obj: object to check
 *
 * Return the required GTT alignment for an object, taking into account
1470
 * potential fence register mapping.
1471
 */
1472 1473 1474
uint32_t
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
			   int tiling_mode, bool fenced)
1475 1476 1477 1478 1479
{
	/*
	 * Minimum alignment is 4k (GTT page size), but might be greater
	 * if a fence register is needed for the object.
	 */
1480
	if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1481
	    tiling_mode == I915_TILING_NONE)
1482 1483
		return 4096;

1484 1485 1486 1487
	/*
	 * Previous chips need to be aligned to the size of the smallest
	 * fence register that can contain the object.
	 */
1488
	return i915_gem_get_gtt_size(dev, size, tiling_mode);
1489 1490
}

1491 1492 1493 1494 1495
static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	int ret;

1496
	if (drm_vma_node_has_offset(&obj->base.vma_node))
1497 1498
		return 0;

1499 1500
	dev_priv->mm.shrinker_no_lock_stealing = true;

1501 1502
	ret = drm_gem_create_mmap_offset(&obj->base);
	if (ret != -ENOSPC)
1503
		goto out;
1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514

	/* Badly fragmented mmap space? The only way we can recover
	 * space is by destroying unwanted objects. We can't randomly release
	 * mmap_offsets as userspace expects them to be persistent for the
	 * lifetime of the objects. The closest we can is to release the
	 * offsets on purgeable objects by truncating it and marking it purged,
	 * which prevents userspace from ever using that object again.
	 */
	i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
	ret = drm_gem_create_mmap_offset(&obj->base);
	if (ret != -ENOSPC)
1515
		goto out;
1516 1517

	i915_gem_shrink_all(dev_priv);
1518 1519 1520 1521 1522
	ret = drm_gem_create_mmap_offset(&obj->base);
out:
	dev_priv->mm.shrinker_no_lock_stealing = false;

	return ret;
1523 1524 1525 1526 1527 1528 1529
}

static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
{
	drm_gem_free_mmap_offset(&obj->base);
}

1530
int
1531 1532 1533 1534
i915_gem_mmap_gtt(struct drm_file *file,
		  struct drm_device *dev,
		  uint32_t handle,
		  uint64_t *offset)
1535
{
1536
	struct drm_i915_private *dev_priv = dev->dev_private;
1537
	struct drm_i915_gem_object *obj;
1538 1539
	int ret;

1540
	ret = i915_mutex_lock_interruptible(dev);
1541
	if (ret)
1542
		return ret;
1543

1544
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1545
	if (&obj->base == NULL) {
1546 1547 1548
		ret = -ENOENT;
		goto unlock;
	}
1549

B
Ben Widawsky 已提交
1550
	if (obj->base.size > dev_priv->gtt.mappable_end) {
1551
		ret = -E2BIG;
1552
		goto out;
1553 1554
	}

1555
	if (obj->madv != I915_MADV_WILLNEED) {
1556
		DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1557 1558
		ret = -EINVAL;
		goto out;
1559 1560
	}

1561 1562 1563
	ret = i915_gem_object_create_mmap_offset(obj);
	if (ret)
		goto out;
1564

1565
	*offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1566

1567
out:
1568
	drm_gem_object_unreference(&obj->base);
1569
unlock:
1570
	mutex_unlock(&dev->struct_mutex);
1571
	return ret;
1572 1573
}

1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597
/**
 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
 * @dev: DRM device
 * @data: GTT mapping ioctl data
 * @file: GEM object info
 *
 * Simply returns the fake offset to userspace so it can mmap it.
 * The mmap call will end up in drm_gem_mmap(), which will set things
 * up so we can get faults in the handler above.
 *
 * The fault handler will take care of binding the object into the GTT
 * (since it may have been evicted to make room for something), allocating
 * a fence register, and mapping the appropriate aperture address into
 * userspace.
 */
int
i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file)
{
	struct drm_i915_gem_mmap_gtt *args = data;

	return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
}

D
Daniel Vetter 已提交
1598 1599 1600
/* Immediately discard the backing storage */
static void
i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1601 1602 1603
{
	struct inode *inode;

1604
	i915_gem_object_free_mmap_offset(obj);
1605

1606 1607
	if (obj->base.filp == NULL)
		return;
1608

D
Daniel Vetter 已提交
1609 1610 1611 1612 1613
	/* Our goal here is to return as much of the memory as
	 * is possible back to the system as we are called from OOM.
	 * To do this we must instruct the shmfs to drop all of its
	 * backing pages, *now*.
	 */
A
Al Viro 已提交
1614
	inode = file_inode(obj->base.filp);
D
Daniel Vetter 已提交
1615
	shmem_truncate_range(inode, 0, (loff_t)-1);
1616

D
Daniel Vetter 已提交
1617 1618
	obj->madv = __I915_MADV_PURGED;
}
1619

D
Daniel Vetter 已提交
1620 1621 1622 1623
static inline int
i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
{
	return obj->madv == I915_MADV_DONTNEED;
1624 1625
}

1626
static void
1627
i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1628
{
1629 1630
	struct sg_page_iter sg_iter;
	int ret;
1631

1632
	BUG_ON(obj->madv == __I915_MADV_PURGED);
1633

C
Chris Wilson 已提交
1634 1635 1636 1637 1638 1639
	ret = i915_gem_object_set_to_cpu_domain(obj, true);
	if (ret) {
		/* In the event of a disaster, abandon all caches and
		 * hope for the best.
		 */
		WARN_ON(ret != -EIO);
1640
		i915_gem_clflush_object(obj, true);
C
Chris Wilson 已提交
1641 1642 1643
		obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	}

1644
	if (i915_gem_object_needs_bit17_swizzle(obj))
1645 1646
		i915_gem_object_save_bit_17_swizzle(obj);

1647 1648
	if (obj->madv == I915_MADV_DONTNEED)
		obj->dirty = 0;
1649

1650
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1651
		struct page *page = sg_page_iter_page(&sg_iter);
1652

1653
		if (obj->dirty)
1654
			set_page_dirty(page);
1655

1656
		if (obj->madv == I915_MADV_WILLNEED)
1657
			mark_page_accessed(page);
1658

1659
		page_cache_release(page);
1660
	}
1661
	obj->dirty = 0;
1662

1663 1664
	sg_free_table(obj->pages);
	kfree(obj->pages);
1665
}
C
Chris Wilson 已提交
1666

1667
int
1668 1669 1670 1671
i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
{
	const struct drm_i915_gem_object_ops *ops = obj->ops;

1672
	if (obj->pages == NULL)
1673 1674
		return 0;

1675 1676 1677
	if (obj->pages_pin_count)
		return -EBUSY;

1678
	BUG_ON(i915_gem_obj_bound_any(obj));
B
Ben Widawsky 已提交
1679

1680 1681 1682
	/* ->put_pages might need to allocate memory for the bit17 swizzle
	 * array, hence protect them from being reaped by removing them from gtt
	 * lists early. */
1683
	list_del(&obj->global_list);
1684

1685
	ops->put_pages(obj);
1686
	obj->pages = NULL;
1687

C
Chris Wilson 已提交
1688 1689 1690 1691 1692 1693 1694
	if (i915_gem_object_is_purgeable(obj))
		i915_gem_object_truncate(obj);

	return 0;
}

static long
1695 1696
__i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
		  bool purgeable_only)
C
Chris Wilson 已提交
1697 1698 1699 1700 1701 1702
{
	struct drm_i915_gem_object *obj, *next;
	long count = 0;

	list_for_each_entry_safe(obj, next,
				 &dev_priv->mm.unbound_list,
1703
				 global_list) {
1704
		if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1705
		    i915_gem_object_put_pages(obj) == 0) {
C
Chris Wilson 已提交
1706 1707 1708 1709 1710 1711
			count += obj->base.size >> PAGE_SHIFT;
			if (count >= target)
				return count;
		}
	}

1712 1713 1714
	list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list,
				 global_list) {
		struct i915_vma *vma, *v;
1715 1716 1717 1718

		if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
			continue;

1719 1720 1721
		list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
			if (i915_vma_unbind(vma))
				break;
1722 1723

		if (!i915_gem_object_put_pages(obj)) {
C
Chris Wilson 已提交
1724 1725 1726 1727 1728 1729 1730 1731 1732
			count += obj->base.size >> PAGE_SHIFT;
			if (count >= target)
				return count;
		}
	}

	return count;
}

1733 1734 1735 1736 1737 1738
static long
i915_gem_purge(struct drm_i915_private *dev_priv, long target)
{
	return __i915_gem_shrink(dev_priv, target, true);
}

C
Chris Wilson 已提交
1739 1740 1741 1742 1743 1744 1745
static void
i915_gem_shrink_all(struct drm_i915_private *dev_priv)
{
	struct drm_i915_gem_object *obj, *next;

	i915_gem_evict_everything(dev_priv->dev);

1746 1747
	list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
				 global_list)
1748
		i915_gem_object_put_pages(obj);
D
Daniel Vetter 已提交
1749 1750
}

1751
static int
C
Chris Wilson 已提交
1752
i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1753
{
C
Chris Wilson 已提交
1754
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1755 1756
	int page_count, i;
	struct address_space *mapping;
1757 1758
	struct sg_table *st;
	struct scatterlist *sg;
1759
	struct sg_page_iter sg_iter;
1760
	struct page *page;
1761
	unsigned long last_pfn = 0;	/* suppress gcc warning */
C
Chris Wilson 已提交
1762
	gfp_t gfp;
1763

C
Chris Wilson 已提交
1764 1765 1766 1767 1768 1769 1770
	/* Assert that the object is not currently in any GPU domain. As it
	 * wasn't in the GTT, there shouldn't be any way it could have been in
	 * a GPU cache
	 */
	BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
	BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);

1771 1772 1773 1774
	st = kmalloc(sizeof(*st), GFP_KERNEL);
	if (st == NULL)
		return -ENOMEM;

1775
	page_count = obj->base.size / PAGE_SIZE;
1776 1777
	if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
		kfree(st);
1778
		return -ENOMEM;
1779
	}
1780

1781 1782 1783 1784 1785
	/* Get the list of pages out of our struct file.  They'll be pinned
	 * at this point until we release them.
	 *
	 * Fail silently without starting the shrinker
	 */
A
Al Viro 已提交
1786
	mapping = file_inode(obj->base.filp)->i_mapping;
C
Chris Wilson 已提交
1787
	gfp = mapping_gfp_mask(mapping);
1788
	gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
C
Chris Wilson 已提交
1789
	gfp &= ~(__GFP_IO | __GFP_WAIT);
1790 1791 1792
	sg = st->sgl;
	st->nents = 0;
	for (i = 0; i < page_count; i++) {
C
Chris Wilson 已提交
1793 1794 1795 1796 1797 1798 1799 1800 1801 1802
		page = shmem_read_mapping_page_gfp(mapping, i, gfp);
		if (IS_ERR(page)) {
			i915_gem_purge(dev_priv, page_count);
			page = shmem_read_mapping_page_gfp(mapping, i, gfp);
		}
		if (IS_ERR(page)) {
			/* We've tried hard to allocate the memory by reaping
			 * our own buffer, now let the real VM do its job and
			 * go down in flames if truly OOM.
			 */
1803
			gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
C
Chris Wilson 已提交
1804 1805 1806 1807 1808 1809 1810
			gfp |= __GFP_IO | __GFP_WAIT;

			i915_gem_shrink_all(dev_priv);
			page = shmem_read_mapping_page_gfp(mapping, i, gfp);
			if (IS_ERR(page))
				goto err_pages;

1811
			gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
C
Chris Wilson 已提交
1812 1813
			gfp &= ~(__GFP_IO | __GFP_WAIT);
		}
1814 1815 1816 1817 1818 1819 1820 1821
#ifdef CONFIG_SWIOTLB
		if (swiotlb_nr_tbl()) {
			st->nents++;
			sg_set_page(sg, page, PAGE_SIZE, 0);
			sg = sg_next(sg);
			continue;
		}
#endif
1822 1823 1824 1825 1826 1827 1828 1829 1830
		if (!i || page_to_pfn(page) != last_pfn + 1) {
			if (i)
				sg = sg_next(sg);
			st->nents++;
			sg_set_page(sg, page, PAGE_SIZE, 0);
		} else {
			sg->length += PAGE_SIZE;
		}
		last_pfn = page_to_pfn(page);
1831
	}
1832 1833 1834 1835
#ifdef CONFIG_SWIOTLB
	if (!swiotlb_nr_tbl())
#endif
		sg_mark_end(sg);
1836 1837
	obj->pages = st;

1838
	if (i915_gem_object_needs_bit17_swizzle(obj))
1839 1840 1841 1842 1843
		i915_gem_object_do_bit_17_swizzle(obj);

	return 0;

err_pages:
1844 1845
	sg_mark_end(sg);
	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1846
		page_cache_release(sg_page_iter_page(&sg_iter));
1847 1848
	sg_free_table(st);
	kfree(st);
1849
	return PTR_ERR(page);
1850 1851
}

1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865
/* Ensure that the associated pages are gathered from the backing storage
 * and pinned into our object. i915_gem_object_get_pages() may be called
 * multiple times before they are released by a single call to
 * i915_gem_object_put_pages() - once the pages are no longer referenced
 * either as a result of memory pressure (reaping pages under the shrinker)
 * or as the object is itself released.
 */
int
i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	const struct drm_i915_gem_object_ops *ops = obj->ops;
	int ret;

1866
	if (obj->pages)
1867 1868
		return 0;

1869 1870 1871 1872 1873
	if (obj->madv != I915_MADV_WILLNEED) {
		DRM_ERROR("Attempting to obtain a purgeable object\n");
		return -EINVAL;
	}

1874 1875
	BUG_ON(obj->pages_pin_count);

1876 1877 1878 1879
	ret = ops->get_pages(obj);
	if (ret)
		return ret;

1880
	list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1881
	return 0;
1882 1883
}

1884
void
1885
i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1886
			       struct intel_ring_buffer *ring)
1887
{
1888
	struct drm_device *dev = obj->base.dev;
1889
	struct drm_i915_private *dev_priv = dev->dev_private;
1890
	u32 seqno = intel_ring_get_seqno(ring);
1891

1892
	BUG_ON(ring == NULL);
1893 1894 1895 1896
	if (obj->ring != ring && obj->last_write_seqno) {
		/* Keep the seqno relative to the current ring */
		obj->last_write_seqno = seqno;
	}
1897
	obj->ring = ring;
1898 1899

	/* Add a reference if we're newly entering the active list. */
1900 1901 1902
	if (!obj->active) {
		drm_gem_object_reference(&obj->base);
		obj->active = 1;
1903
	}
1904

1905
	list_move_tail(&obj->ring_list, &ring->active_list);
1906

1907
	obj->last_read_seqno = seqno;
1908

1909
	if (obj->fenced_gpu_access) {
1910 1911
		obj->last_fenced_seqno = seqno;

1912 1913 1914 1915 1916 1917 1918 1919
		/* Bump MRU to take account of the delayed flush */
		if (obj->fence_reg != I915_FENCE_REG_NONE) {
			struct drm_i915_fence_reg *reg;

			reg = &dev_priv->fence_regs[obj->fence_reg];
			list_move_tail(&reg->lru_list,
				       &dev_priv->mm.fence_list);
		}
1920 1921 1922 1923 1924
	}
}

static void
i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1925
{
B
Ben Widawsky 已提交
1926 1927 1928
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
	struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1929

1930
	BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1931
	BUG_ON(!obj->active);
1932

B
Ben Widawsky 已提交
1933
	list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
1934

1935
	list_del_init(&obj->ring_list);
1936 1937
	obj->ring = NULL;

1938 1939 1940 1941 1942
	obj->last_read_seqno = 0;
	obj->last_write_seqno = 0;
	obj->base.write_domain = 0;

	obj->last_fenced_seqno = 0;
1943 1944 1945 1946 1947 1948
	obj->fenced_gpu_access = false;

	obj->active = 0;
	drm_gem_object_unreference(&obj->base);

	WARN_ON(i915_verify_lists(dev));
1949
}
1950

1951
static int
1952
i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1953
{
1954 1955 1956
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring;
	int ret, i, j;
1957

1958
	/* Carefully retire all requests without writing to the rings */
1959
	for_each_ring(ring, dev_priv, i) {
1960 1961 1962
		ret = intel_ring_idle(ring);
		if (ret)
			return ret;
1963 1964
	}
	i915_gem_retire_requests(dev);
1965 1966

	/* Finally reset hw state */
1967
	for_each_ring(ring, dev_priv, i) {
1968
		intel_ring_init_seqno(ring, seqno);
1969

1970 1971 1972
		for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
			ring->sync_seqno[j] = 0;
	}
1973

1974
	return 0;
1975 1976
}

1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002
int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	if (seqno == 0)
		return -EINVAL;

	/* HWS page needs to be set less than what we
	 * will inject to ring
	 */
	ret = i915_gem_init_seqno(dev, seqno - 1);
	if (ret)
		return ret;

	/* Carefully set the last_seqno value so that wrap
	 * detection still works
	 */
	dev_priv->next_seqno = seqno;
	dev_priv->last_seqno = seqno - 1;
	if (dev_priv->last_seqno == 0)
		dev_priv->last_seqno--;

	return 0;
}

2003 2004
int
i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2005
{
2006 2007 2008 2009
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* reserve 0 for non-seqno */
	if (dev_priv->next_seqno == 0) {
2010
		int ret = i915_gem_init_seqno(dev, 0);
2011 2012
		if (ret)
			return ret;
2013

2014 2015
		dev_priv->next_seqno = 1;
	}
2016

2017
	*seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2018
	return 0;
2019 2020
}

2021 2022
int __i915_add_request(struct intel_ring_buffer *ring,
		       struct drm_file *file,
2023
		       struct drm_i915_gem_object *obj,
2024
		       u32 *out_seqno)
2025
{
C
Chris Wilson 已提交
2026
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
2027
	struct drm_i915_gem_request *request;
2028
	u32 request_ring_position, request_start;
2029
	int was_empty;
2030 2031
	int ret;

2032
	request_start = intel_ring_get_tail(ring);
2033 2034 2035 2036 2037 2038 2039
	/*
	 * Emit any outstanding flushes - execbuf can fail to emit the flush
	 * after having emitted the batchbuffer command. Hence we need to fix
	 * things up similar to emitting the lazy request. The difference here
	 * is that the flush _must_ happen before the next request, no matter
	 * what.
	 */
2040 2041 2042
	ret = intel_ring_flush_all_caches(ring);
	if (ret)
		return ret;
2043

2044 2045 2046
	request = kmalloc(sizeof(*request), GFP_KERNEL);
	if (request == NULL)
		return -ENOMEM;
2047

2048

2049 2050 2051 2052 2053 2054 2055
	/* Record the position of the start of the request so that
	 * should we detect the updated seqno part-way through the
	 * GPU processing the request, we never over-estimate the
	 * position of the head.
	 */
	request_ring_position = intel_ring_get_tail(ring);

2056
	ret = ring->add_request(ring);
2057 2058 2059 2060
	if (ret) {
		kfree(request);
		return ret;
	}
2061

2062
	request->seqno = intel_ring_get_seqno(ring);
2063
	request->ring = ring;
2064
	request->head = request_start;
2065
	request->tail = request_ring_position;
2066
	request->ctx = ring->last_context;
2067 2068 2069 2070 2071 2072 2073 2074
	request->batch_obj = obj;

	/* Whilst this request exists, batch_obj will be on the
	 * active_list, and so will hold the active reference. Only when this
	 * request is retired will the the batch_obj be moved onto the
	 * inactive_list and lose its active reference. Hence we do not need
	 * to explicitly hold another reference here.
	 */
2075 2076 2077 2078

	if (request->ctx)
		i915_gem_context_reference(request->ctx);

2079
	request->emitted_jiffies = jiffies;
2080 2081
	was_empty = list_empty(&ring->request_list);
	list_add_tail(&request->list, &ring->request_list);
2082
	request->file_priv = NULL;
2083

C
Chris Wilson 已提交
2084 2085 2086
	if (file) {
		struct drm_i915_file_private *file_priv = file->driver_priv;

2087
		spin_lock(&file_priv->mm.lock);
2088
		request->file_priv = file_priv;
2089
		list_add_tail(&request->client_list,
2090
			      &file_priv->mm.request_list);
2091
		spin_unlock(&file_priv->mm.lock);
2092
	}
2093

2094
	trace_i915_gem_request_add(ring, request->seqno);
2095
	ring->outstanding_lazy_request = 0;
C
Chris Wilson 已提交
2096

2097
	if (!dev_priv->ums.mm_suspended) {
2098 2099
		i915_queue_hangcheck(ring->dev);

2100
		if (was_empty) {
2101
			queue_delayed_work(dev_priv->wq,
2102 2103
					   &dev_priv->mm.retire_work,
					   round_jiffies_up_relative(HZ));
2104 2105
			intel_mark_busy(dev_priv->dev);
		}
B
Ben Gamari 已提交
2106
	}
2107

2108
	if (out_seqno)
2109
		*out_seqno = request->seqno;
2110
	return 0;
2111 2112
}

2113 2114
static inline void
i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2115
{
2116
	struct drm_i915_file_private *file_priv = request->file_priv;
2117

2118 2119
	if (!file_priv)
		return;
C
Chris Wilson 已提交
2120

2121
	spin_lock(&file_priv->mm.lock);
2122 2123 2124 2125
	if (request->file_priv) {
		list_del(&request->client_list);
		request->file_priv = NULL;
	}
2126
	spin_unlock(&file_priv->mm.lock);
2127 2128
}

2129 2130
static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
				    struct i915_address_space *vm)
2131
{
2132 2133
	if (acthd >= i915_gem_obj_offset(obj, vm) &&
	    acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155
		return true;

	return false;
}

static bool i915_head_inside_request(const u32 acthd_unmasked,
				     const u32 request_start,
				     const u32 request_end)
{
	const u32 acthd = acthd_unmasked & HEAD_ADDR;

	if (request_start < request_end) {
		if (acthd >= request_start && acthd < request_end)
			return true;
	} else if (request_start > request_end) {
		if (acthd >= request_start || acthd < request_end)
			return true;
	}

	return false;
}

2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166
static struct i915_address_space *
request_to_vm(struct drm_i915_gem_request *request)
{
	struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
	struct i915_address_space *vm;

	vm = &dev_priv->gtt.base;

	return vm;
}

2167 2168 2169 2170 2171 2172 2173 2174
static bool i915_request_guilty(struct drm_i915_gem_request *request,
				const u32 acthd, bool *inside)
{
	/* There is a possibility that unmasked head address
	 * pointing inside the ring, matches the batch_obj address range.
	 * However this is extremely unlikely.
	 */
	if (request->batch_obj) {
2175 2176
		if (i915_head_inside_object(acthd, request->batch_obj,
					    request_to_vm(request))) {
2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195
			*inside = true;
			return true;
		}
	}

	if (i915_head_inside_request(acthd, request->head, request->tail)) {
		*inside = false;
		return true;
	}

	return false;
}

static void i915_set_reset_status(struct intel_ring_buffer *ring,
				  struct drm_i915_gem_request *request,
				  u32 acthd)
{
	struct i915_ctx_hang_stats *hs = NULL;
	bool inside, guilty;
2196
	unsigned long offset = 0;
2197 2198 2199 2200

	/* Innocent until proven guilty */
	guilty = false;

2201 2202 2203 2204
	if (request->batch_obj)
		offset = i915_gem_obj_offset(request->batch_obj,
					     request_to_vm(request));

2205
	if (ring->hangcheck.action != HANGCHECK_WAIT &&
2206
	    i915_request_guilty(request, acthd, &inside)) {
2207
		DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2208 2209
			  ring->name,
			  inside ? "inside" : "flushing",
2210
			  offset,
2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232
			  request->ctx ? request->ctx->id : 0,
			  acthd);

		guilty = true;
	}

	/* If contexts are disabled or this is the default context, use
	 * file_priv->reset_state
	 */
	if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
		hs = &request->ctx->hang_stats;
	else if (request->file_priv)
		hs = &request->file_priv->hang_stats;

	if (hs) {
		if (guilty)
			hs->batch_active++;
		else
			hs->batch_pending++;
	}
}

2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243
static void i915_gem_free_request(struct drm_i915_gem_request *request)
{
	list_del(&request->list);
	i915_gem_request_remove_from_client(request);

	if (request->ctx)
		i915_gem_context_unreference(request->ctx);

	kfree(request);
}

2244 2245
static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
				      struct intel_ring_buffer *ring)
2246
{
2247 2248 2249 2250 2251 2252
	u32 completed_seqno;
	u32 acthd;

	acthd = intel_ring_get_active_head(ring);
	completed_seqno = ring->get_seqno(ring, false);

2253 2254
	while (!list_empty(&ring->request_list)) {
		struct drm_i915_gem_request *request;
2255

2256 2257 2258
		request = list_first_entry(&ring->request_list,
					   struct drm_i915_gem_request,
					   list);
2259

2260 2261 2262
		if (request->seqno > completed_seqno)
			i915_set_reset_status(ring, request, acthd);

2263
		i915_gem_free_request(request);
2264
	}
2265

2266
	while (!list_empty(&ring->active_list)) {
2267
		struct drm_i915_gem_object *obj;
2268

2269 2270 2271
		obj = list_first_entry(&ring->active_list,
				       struct drm_i915_gem_object,
				       ring_list);
2272

2273
		i915_gem_object_move_to_inactive(obj);
2274 2275 2276
	}
}

2277
void i915_gem_restore_fences(struct drm_device *dev)
2278 2279 2280 2281
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

2282
	for (i = 0; i < dev_priv->num_fence_regs; i++) {
2283
		struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2284

2285 2286 2287 2288 2289 2290 2291 2292 2293 2294
		/*
		 * Commit delayed tiling changes if we have an object still
		 * attached to the fence, otherwise just clear the fence.
		 */
		if (reg->obj) {
			i915_gem_object_update_fence(reg->obj, reg,
						     reg->obj->tiling_mode);
		} else {
			i915_gem_write_fence(dev, i, NULL);
		}
2295 2296 2297
	}
}

2298
void i915_gem_reset(struct drm_device *dev)
2299
{
2300
	struct drm_i915_private *dev_priv = dev->dev_private;
2301
	struct intel_ring_buffer *ring;
2302
	int i;
2303

2304 2305
	for_each_ring(ring, dev_priv, i)
		i915_gem_reset_ring_lists(dev_priv, ring);
2306

2307
	i915_gem_restore_fences(dev);
2308 2309 2310 2311 2312
}

/**
 * This function clears the request list as sequence numbers are passed.
 */
2313
void
C
Chris Wilson 已提交
2314
i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2315 2316 2317
{
	uint32_t seqno;

C
Chris Wilson 已提交
2318
	if (list_empty(&ring->request_list))
2319 2320
		return;

C
Chris Wilson 已提交
2321
	WARN_ON(i915_verify_lists(ring->dev));
2322

2323
	seqno = ring->get_seqno(ring, true);
2324

2325
	while (!list_empty(&ring->request_list)) {
2326 2327
		struct drm_i915_gem_request *request;

2328
		request = list_first_entry(&ring->request_list,
2329 2330 2331
					   struct drm_i915_gem_request,
					   list);

2332
		if (!i915_seqno_passed(seqno, request->seqno))
2333 2334
			break;

C
Chris Wilson 已提交
2335
		trace_i915_gem_request_retire(ring, request->seqno);
2336 2337 2338 2339 2340 2341
		/* We know the GPU must have read the request to have
		 * sent us the seqno + interrupt, so use the position
		 * of tail of the request to update the last known position
		 * of the GPU head.
		 */
		ring->last_retired_head = request->tail;
2342

2343
		i915_gem_free_request(request);
2344
	}
2345

2346 2347 2348 2349
	/* Move any buffers on the active list that are no longer referenced
	 * by the ringbuffer to the flushing/inactive lists as appropriate.
	 */
	while (!list_empty(&ring->active_list)) {
2350
		struct drm_i915_gem_object *obj;
2351

2352
		obj = list_first_entry(&ring->active_list,
2353 2354
				      struct drm_i915_gem_object,
				      ring_list);
2355

2356
		if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2357
			break;
2358

2359
		i915_gem_object_move_to_inactive(obj);
2360
	}
2361

C
Chris Wilson 已提交
2362 2363
	if (unlikely(ring->trace_irq_seqno &&
		     i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2364
		ring->irq_put(ring);
C
Chris Wilson 已提交
2365
		ring->trace_irq_seqno = 0;
2366
	}
2367

C
Chris Wilson 已提交
2368
	WARN_ON(i915_verify_lists(ring->dev));
2369 2370
}

2371 2372 2373 2374
void
i915_gem_retire_requests(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
2375
	struct intel_ring_buffer *ring;
2376
	int i;
2377

2378 2379
	for_each_ring(ring, dev_priv, i)
		i915_gem_retire_requests_ring(ring);
2380 2381
}

2382
static void
2383 2384 2385 2386
i915_gem_retire_work_handler(struct work_struct *work)
{
	drm_i915_private_t *dev_priv;
	struct drm_device *dev;
2387
	struct intel_ring_buffer *ring;
2388 2389
	bool idle;
	int i;
2390 2391 2392 2393 2394

	dev_priv = container_of(work, drm_i915_private_t,
				mm.retire_work.work);
	dev = dev_priv->dev;

2395 2396
	/* Come back later if the device is busy... */
	if (!mutex_trylock(&dev->struct_mutex)) {
2397 2398
		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
				   round_jiffies_up_relative(HZ));
2399 2400
		return;
	}
2401

2402
	i915_gem_retire_requests(dev);
2403

2404 2405
	/* Send a periodic flush down the ring so we don't hold onto GEM
	 * objects indefinitely.
2406
	 */
2407
	idle = true;
2408
	for_each_ring(ring, dev_priv, i) {
2409
		if (ring->gpu_caches_dirty)
2410
			i915_add_request(ring, NULL);
2411 2412

		idle &= list_empty(&ring->request_list);
2413 2414
	}

2415
	if (!dev_priv->ums.mm_suspended && !idle)
2416 2417
		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
				   round_jiffies_up_relative(HZ));
2418 2419
	if (idle)
		intel_mark_idle(dev);
2420

2421 2422 2423
	mutex_unlock(&dev->struct_mutex);
}

2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434
/**
 * Ensures that an object will eventually get non-busy by flushing any required
 * write domains, emitting any outstanding lazy request and retiring and
 * completed requests.
 */
static int
i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
{
	int ret;

	if (obj->active) {
2435
		ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2436 2437 2438 2439 2440 2441 2442 2443 2444
		if (ret)
			return ret;

		i915_gem_retire_requests_ring(obj->ring);
	}

	return 0;
}

2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469
/**
 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
 * @DRM_IOCTL_ARGS: standard ioctl arguments
 *
 * Returns 0 if successful, else an error is returned with the remaining time in
 * the timeout parameter.
 *  -ETIME: object is still busy after timeout
 *  -ERESTARTSYS: signal interrupted the wait
 *  -ENONENT: object doesn't exist
 * Also possible, but rare:
 *  -EAGAIN: GPU wedged
 *  -ENOMEM: damn
 *  -ENODEV: Internal IRQ fail
 *  -E?: The add request failed
 *
 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
 * non-zero timeout parameter the wait ioctl will wait for the given number of
 * nanoseconds on an object becoming unbusy. Since the wait itself does so
 * without holding struct_mutex the object may become re-busied before this
 * function completes. A similar but shorter * race condition exists in the busy
 * ioctl
 */
int
i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
{
2470
	drm_i915_private_t *dev_priv = dev->dev_private;
2471 2472 2473
	struct drm_i915_gem_wait *args = data;
	struct drm_i915_gem_object *obj;
	struct intel_ring_buffer *ring = NULL;
2474
	struct timespec timeout_stack, *timeout = NULL;
2475
	unsigned reset_counter;
2476 2477 2478
	u32 seqno = 0;
	int ret = 0;

2479 2480 2481 2482
	if (args->timeout_ns >= 0) {
		timeout_stack = ns_to_timespec(args->timeout_ns);
		timeout = &timeout_stack;
	}
2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493

	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
	if (&obj->base == NULL) {
		mutex_unlock(&dev->struct_mutex);
		return -ENOENT;
	}

2494 2495
	/* Need to make sure the object gets inactive eventually. */
	ret = i915_gem_object_flush_active(obj);
2496 2497 2498 2499
	if (ret)
		goto out;

	if (obj->active) {
2500
		seqno = obj->last_read_seqno;
2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515
		ring = obj->ring;
	}

	if (seqno == 0)
		 goto out;

	/* Do this after OLR check to make sure we make forward progress polling
	 * on this IOCTL with a 0 timeout (like busy ioctl)
	 */
	if (!args->timeout_ns) {
		ret = -ETIME;
		goto out;
	}

	drm_gem_object_unreference(&obj->base);
2516
	reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2517 2518
	mutex_unlock(&dev->struct_mutex);

2519
	ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2520
	if (timeout)
2521
		args->timeout_ns = timespec_to_ns(timeout);
2522 2523 2524 2525 2526 2527 2528 2529
	return ret;

out:
	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541
/**
 * i915_gem_object_sync - sync an object to a ring.
 *
 * @obj: object which may be in use on another ring.
 * @to: ring we wish to use the object on. May be NULL.
 *
 * This code is meant to abstract object synchronization with the GPU.
 * Calling with NULL implies synchronizing the object with the CPU
 * rather than a particular GPU ring.
 *
 * Returns 0 if successful, else propagates up the lower layer error.
 */
2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552
int
i915_gem_object_sync(struct drm_i915_gem_object *obj,
		     struct intel_ring_buffer *to)
{
	struct intel_ring_buffer *from = obj->ring;
	u32 seqno;
	int ret, idx;

	if (from == NULL || to == from)
		return 0;

2553
	if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2554
		return i915_gem_object_wait_rendering(obj, false);
2555 2556 2557

	idx = intel_ring_sync_index(from, to);

2558
	seqno = obj->last_read_seqno;
2559 2560 2561
	if (seqno <= from->sync_seqno[idx])
		return 0;

2562 2563 2564
	ret = i915_gem_check_olr(obj->ring, seqno);
	if (ret)
		return ret;
2565

2566
	ret = to->sync_to(to, from, seqno);
2567
	if (!ret)
2568 2569 2570 2571 2572
		/* We use last_read_seqno because sync_to()
		 * might have just caused seqno wrap under
		 * the radar.
		 */
		from->sync_seqno[idx] = obj->last_read_seqno;
2573

2574
	return ret;
2575 2576
}

2577 2578 2579 2580 2581 2582 2583
static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
{
	u32 old_write_domain, old_read_domains;

	/* Force a pagefault for domain tracking on next user access */
	i915_gem_release_mmap(obj);

2584 2585 2586
	if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
		return;

2587 2588 2589
	/* Wait for any direct GTT access to complete */
	mb();

2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600
	old_read_domains = obj->base.read_domains;
	old_write_domain = obj->base.write_domain;

	obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
	obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;

	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);
}

2601
int i915_vma_unbind(struct i915_vma *vma)
2602
{
2603
	struct drm_i915_gem_object *obj = vma->obj;
2604
	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2605
	int ret;
2606

2607
	if (list_empty(&vma->vma_link))
2608 2609
		return 0;

2610 2611 2612
	if (!drm_mm_node_allocated(&vma->node))
		goto destroy;

2613 2614
	if (obj->pin_count)
		return -EBUSY;
2615

2616 2617
	BUG_ON(obj->pages == NULL);

2618
	ret = i915_gem_object_finish_gpu(obj);
2619
	if (ret)
2620 2621 2622 2623 2624 2625
		return ret;
	/* Continue on if we fail due to EIO, the GPU is hung so we
	 * should be safe and we need to cleanup or else we might
	 * cause memory corruption through use-after-free.
	 */

2626
	i915_gem_object_finish_gtt(obj);
2627

2628
	/* release the fence reg _after_ flushing */
2629
	ret = i915_gem_object_put_fence(obj);
2630
	if (ret)
2631
		return ret;
2632

2633
	trace_i915_vma_unbind(vma);
C
Chris Wilson 已提交
2634

2635 2636
	if (obj->has_global_gtt_mapping)
		i915_gem_gtt_unbind_object(obj);
2637 2638 2639 2640
	if (obj->has_aliasing_ppgtt_mapping) {
		i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
		obj->has_aliasing_ppgtt_mapping = 0;
	}
2641
	i915_gem_gtt_finish_object(obj);
B
Ben Widawsky 已提交
2642
	i915_gem_object_unpin_pages(obj);
2643

B
Ben Widawsky 已提交
2644
	list_del(&vma->mm_list);
2645
	/* Avoid an unnecessary call to unbind on rebind. */
2646 2647
	if (i915_is_ggtt(vma->vm))
		obj->map_and_fenceable = true;
2648

B
Ben Widawsky 已提交
2649
	drm_mm_remove_node(&vma->node);
2650 2651

destroy:
B
Ben Widawsky 已提交
2652 2653 2654 2655 2656 2657 2658 2659
	i915_gem_vma_destroy(vma);

	/* Since the unbound list is global, only move to that list if
	 * no more VMAs exist.
	 * NB: Until we have real VMAs there will only ever be one */
	WARN_ON(!list_empty(&obj->vma_list));
	if (list_empty(&obj->vma_list))
		list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2660

2661
	return 0;
2662 2663
}

2664 2665 2666 2667 2668 2669 2670 2671 2672
/**
 * Unbinds an object from the global GTT aperture.
 */
int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	struct i915_address_space *ggtt = &dev_priv->gtt.base;

2673
	if (!i915_gem_obj_ggtt_bound(obj))
2674 2675 2676 2677 2678 2679 2680 2681 2682 2683
		return 0;

	if (obj->pin_count)
		return -EBUSY;

	BUG_ON(obj->pages == NULL);

	return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
}

2684
int i915_gpu_idle(struct drm_device *dev)
2685 2686
{
	drm_i915_private_t *dev_priv = dev->dev_private;
2687
	struct intel_ring_buffer *ring;
2688
	int ret, i;
2689 2690

	/* Flush everything onto the inactive list. */
2691
	for_each_ring(ring, dev_priv, i) {
2692 2693 2694 2695
		ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
		if (ret)
			return ret;

2696
		ret = intel_ring_idle(ring);
2697 2698 2699
		if (ret)
			return ret;
	}
2700

2701
	return 0;
2702 2703
}

2704 2705
static void i965_write_fence_reg(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj)
2706 2707
{
	drm_i915_private_t *dev_priv = dev->dev_private;
2708 2709
	int fence_reg;
	int fence_pitch_shift;
2710

2711 2712 2713 2714 2715 2716 2717 2718
	if (INTEL_INFO(dev)->gen >= 6) {
		fence_reg = FENCE_REG_SANDYBRIDGE_0;
		fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
	} else {
		fence_reg = FENCE_REG_965_0;
		fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
	}

2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732
	fence_reg += reg * 8;

	/* To w/a incoherency with non-atomic 64-bit register updates,
	 * we split the 64-bit update into two 32-bit writes. In order
	 * for a partial fence not to be evaluated between writes, we
	 * precede the update with write to turn off the fence register,
	 * and only enable the fence as the last step.
	 *
	 * For extra levels of paranoia, we make sure each step lands
	 * before applying the next step.
	 */
	I915_WRITE(fence_reg, 0);
	POSTING_READ(fence_reg);

2733
	if (obj) {
2734
		u32 size = i915_gem_obj_ggtt_size(obj);
2735
		uint64_t val;
2736

2737
		val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2738
				 0xfffff000) << 32;
2739
		val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2740
		val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2741 2742 2743
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
		val |= I965_FENCE_REG_VALID;
2744

2745 2746 2747 2748 2749 2750 2751 2752 2753
		I915_WRITE(fence_reg + 4, val >> 32);
		POSTING_READ(fence_reg + 4);

		I915_WRITE(fence_reg + 0, val);
		POSTING_READ(fence_reg);
	} else {
		I915_WRITE(fence_reg + 4, 0);
		POSTING_READ(fence_reg + 4);
	}
2754 2755
}

2756 2757
static void i915_write_fence_reg(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj)
2758 2759
{
	drm_i915_private_t *dev_priv = dev->dev_private;
2760
	u32 val;
2761

2762
	if (obj) {
2763
		u32 size = i915_gem_obj_ggtt_size(obj);
2764 2765
		int pitch_val;
		int tile_width;
2766

2767
		WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2768
		     (size & -size) != size ||
2769 2770 2771
		     (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
		     "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
		     i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2772

2773 2774 2775 2776 2777 2778 2779 2780 2781
		if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
			tile_width = 128;
		else
			tile_width = 512;

		/* Note: pitch better be a power of two tile widths */
		pitch_val = obj->stride / tile_width;
		pitch_val = ffs(pitch_val) - 1;

2782
		val = i915_gem_obj_ggtt_offset(obj);
2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I830_FENCE_TILING_Y_SHIFT;
		val |= I915_FENCE_SIZE_BITS(size);
		val |= pitch_val << I830_FENCE_PITCH_SHIFT;
		val |= I830_FENCE_REG_VALID;
	} else
		val = 0;

	if (reg < 8)
		reg = FENCE_REG_830_0 + reg * 4;
	else
		reg = FENCE_REG_945_8 + (reg - 8) * 4;

	I915_WRITE(reg, val);
	POSTING_READ(reg);
2798 2799
}

2800 2801
static void i830_write_fence_reg(struct drm_device *dev, int reg,
				struct drm_i915_gem_object *obj)
2802 2803 2804 2805
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	uint32_t val;

2806
	if (obj) {
2807
		u32 size = i915_gem_obj_ggtt_size(obj);
2808
		uint32_t pitch_val;
2809

2810
		WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2811
		     (size & -size) != size ||
2812 2813 2814
		     (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
		     "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
		     i915_gem_obj_ggtt_offset(obj), size);
2815

2816 2817
		pitch_val = obj->stride / 128;
		pitch_val = ffs(pitch_val) - 1;
2818

2819
		val = i915_gem_obj_ggtt_offset(obj);
2820 2821 2822 2823 2824 2825 2826
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I830_FENCE_TILING_Y_SHIFT;
		val |= I830_FENCE_SIZE_BITS(size);
		val |= pitch_val << I830_FENCE_PITCH_SHIFT;
		val |= I830_FENCE_REG_VALID;
	} else
		val = 0;
2827

2828 2829 2830 2831
	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
	POSTING_READ(FENCE_REG_830_0 + reg * 4);
}

2832 2833 2834 2835 2836
inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
{
	return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
}

2837 2838 2839
static void i915_gem_write_fence(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj)
{
2840 2841 2842 2843 2844 2845 2846 2847
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* Ensure that all CPU reads are completed before installing a fence
	 * and all writes before removing the fence.
	 */
	if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
		mb();

2848 2849 2850 2851
	WARN(obj && (!obj->stride || !obj->tiling_mode),
	     "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
	     obj->stride, obj->tiling_mode);

2852 2853
	switch (INTEL_INFO(dev)->gen) {
	case 7:
2854
	case 6:
2855 2856 2857 2858
	case 5:
	case 4: i965_write_fence_reg(dev, reg, obj); break;
	case 3: i915_write_fence_reg(dev, reg, obj); break;
	case 2: i830_write_fence_reg(dev, reg, obj); break;
2859
	default: BUG();
2860
	}
2861 2862 2863 2864 2865 2866

	/* And similarly be paranoid that no direct access to this region
	 * is reordered to before the fence is installed.
	 */
	if (i915_gem_object_needs_mb(obj))
		mb();
2867 2868
}

2869 2870 2871 2872 2873 2874 2875 2876 2877 2878
static inline int fence_number(struct drm_i915_private *dev_priv,
			       struct drm_i915_fence_reg *fence)
{
	return fence - dev_priv->fence_regs;
}

static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
					 struct drm_i915_fence_reg *fence,
					 bool enable)
{
2879
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2880 2881 2882
	int reg = fence_number(dev_priv, fence);

	i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2883 2884

	if (enable) {
2885
		obj->fence_reg = reg;
2886 2887 2888 2889 2890 2891 2892
		fence->obj = obj;
		list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
	} else {
		obj->fence_reg = I915_FENCE_REG_NONE;
		fence->obj = NULL;
		list_del_init(&fence->lru_list);
	}
2893
	obj->fence_dirty = false;
2894 2895
}

2896
static int
2897
i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2898
{
2899
	if (obj->last_fenced_seqno) {
2900
		int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2901 2902
		if (ret)
			return ret;
2903 2904 2905 2906

		obj->last_fenced_seqno = 0;
	}

2907
	obj->fenced_gpu_access = false;
2908 2909 2910 2911 2912 2913
	return 0;
}

int
i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
{
2914
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2915
	struct drm_i915_fence_reg *fence;
2916 2917
	int ret;

2918
	ret = i915_gem_object_wait_fence(obj);
2919 2920 2921
	if (ret)
		return ret;

2922 2923
	if (obj->fence_reg == I915_FENCE_REG_NONE)
		return 0;
2924

2925 2926
	fence = &dev_priv->fence_regs[obj->fence_reg];

2927
	i915_gem_object_fence_lost(obj);
2928
	i915_gem_object_update_fence(obj, fence, false);
2929 2930 2931 2932 2933

	return 0;
}

static struct drm_i915_fence_reg *
C
Chris Wilson 已提交
2934
i915_find_fence_reg(struct drm_device *dev)
2935 2936
{
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
2937
	struct drm_i915_fence_reg *reg, *avail;
2938
	int i;
2939 2940

	/* First try to find a free reg */
2941
	avail = NULL;
2942 2943 2944
	for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
		reg = &dev_priv->fence_regs[i];
		if (!reg->obj)
2945
			return reg;
2946

2947
		if (!reg->pin_count)
2948
			avail = reg;
2949 2950
	}

2951 2952
	if (avail == NULL)
		return NULL;
2953 2954

	/* None available, try to steal one or wait for a user to finish */
2955
	list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2956
		if (reg->pin_count)
2957 2958
			continue;

C
Chris Wilson 已提交
2959
		return reg;
2960 2961
	}

C
Chris Wilson 已提交
2962
	return NULL;
2963 2964
}

2965
/**
2966
 * i915_gem_object_get_fence - set up fencing for an object
2967 2968 2969 2970 2971 2972 2973 2974 2975
 * @obj: object to map through a fence reg
 *
 * When mapping objects through the GTT, userspace wants to be able to write
 * to them without having to worry about swizzling if the object is tiled.
 * This function walks the fence regs looking for a free one for @obj,
 * stealing one if it can't find any.
 *
 * It then sets up the reg based on the object's properties: address, pitch
 * and tiling format.
2976 2977
 *
 * For an untiled surface, this removes any existing fence.
2978
 */
2979
int
2980
i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2981
{
2982
	struct drm_device *dev = obj->base.dev;
J
Jesse Barnes 已提交
2983
	struct drm_i915_private *dev_priv = dev->dev_private;
2984
	bool enable = obj->tiling_mode != I915_TILING_NONE;
2985
	struct drm_i915_fence_reg *reg;
2986
	int ret;
2987

2988 2989 2990
	/* Have we updated the tiling parameters upon the object and so
	 * will need to serialise the write to the associated fence register?
	 */
2991
	if (obj->fence_dirty) {
2992
		ret = i915_gem_object_wait_fence(obj);
2993 2994 2995
		if (ret)
			return ret;
	}
2996

2997
	/* Just update our place in the LRU if our fence is getting reused. */
2998 2999
	if (obj->fence_reg != I915_FENCE_REG_NONE) {
		reg = &dev_priv->fence_regs[obj->fence_reg];
3000
		if (!obj->fence_dirty) {
3001 3002 3003 3004 3005 3006 3007 3008
			list_move_tail(&reg->lru_list,
				       &dev_priv->mm.fence_list);
			return 0;
		}
	} else if (enable) {
		reg = i915_find_fence_reg(dev);
		if (reg == NULL)
			return -EDEADLK;
3009

3010 3011 3012
		if (reg->obj) {
			struct drm_i915_gem_object *old = reg->obj;

3013
			ret = i915_gem_object_wait_fence(old);
3014 3015 3016
			if (ret)
				return ret;

3017
			i915_gem_object_fence_lost(old);
3018
		}
3019
	} else
3020 3021
		return 0;

3022 3023
	i915_gem_object_update_fence(obj, reg, enable);

3024
	return 0;
3025 3026
}

3027 3028 3029 3030 3031 3032 3033 3034
static bool i915_gem_valid_gtt_space(struct drm_device *dev,
				     struct drm_mm_node *gtt_space,
				     unsigned long cache_level)
{
	struct drm_mm_node *other;

	/* On non-LLC machines we have to be careful when putting differing
	 * types of snoopable memory together to avoid the prefetcher
3035
	 * crossing memory domains and dying.
3036 3037 3038 3039
	 */
	if (HAS_LLC(dev))
		return true;

3040
	if (!drm_mm_node_allocated(gtt_space))
3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063
		return true;

	if (list_empty(&gtt_space->node_list))
		return true;

	other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
	if (other->allocated && !other->hole_follows && other->color != cache_level)
		return false;

	other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
	if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
		return false;

	return true;
}

static void i915_gem_verify_gtt(struct drm_device *dev)
{
#if WATCH_GTT
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	int err = 0;

3064
	list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3065 3066 3067 3068 3069 3070 3071 3072
		if (obj->gtt_space == NULL) {
			printk(KERN_ERR "object found on GTT list with no space reserved\n");
			err++;
			continue;
		}

		if (obj->cache_level != obj->gtt_space->color) {
			printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3073 3074
			       i915_gem_obj_ggtt_offset(obj),
			       i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3075 3076 3077 3078 3079 3080 3081 3082 3083 3084
			       obj->cache_level,
			       obj->gtt_space->color);
			err++;
			continue;
		}

		if (!i915_gem_valid_gtt_space(dev,
					      obj->gtt_space,
					      obj->cache_level)) {
			printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3085 3086
			       i915_gem_obj_ggtt_offset(obj),
			       i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3087 3088 3089 3090 3091 3092 3093 3094 3095 3096
			       obj->cache_level);
			err++;
			continue;
		}
	}

	WARN_ON(err);
#endif
}

3097 3098 3099 3100
/**
 * Finds free space in the GTT aperture and binds the object there.
 */
static int
3101 3102 3103 3104 3105
i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
			   struct i915_address_space *vm,
			   unsigned alignment,
			   bool map_and_fenceable,
			   bool nonblocking)
3106
{
3107
	struct drm_device *dev = obj->base.dev;
3108
	drm_i915_private_t *dev_priv = dev->dev_private;
3109
	u32 size, fence_size, fence_alignment, unfenced_alignment;
3110 3111
	size_t gtt_max =
		map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
B
Ben Widawsky 已提交
3112
	struct i915_vma *vma;
3113
	int ret;
3114

3115 3116 3117 3118 3119
	fence_size = i915_gem_get_gtt_size(dev,
					   obj->base.size,
					   obj->tiling_mode);
	fence_alignment = i915_gem_get_gtt_alignment(dev,
						     obj->base.size,
3120
						     obj->tiling_mode, true);
3121
	unfenced_alignment =
3122
		i915_gem_get_gtt_alignment(dev,
3123
						    obj->base.size,
3124
						    obj->tiling_mode, false);
3125

3126
	if (alignment == 0)
3127 3128
		alignment = map_and_fenceable ? fence_alignment :
						unfenced_alignment;
3129
	if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3130 3131 3132 3133
		DRM_ERROR("Invalid object alignment requested %u\n", alignment);
		return -EINVAL;
	}

3134
	size = map_and_fenceable ? fence_size : obj->base.size;
3135

3136 3137 3138
	/* If the object is bigger than the entire aperture, reject it early
	 * before evicting everything in a vain attempt to find space.
	 */
3139
	if (obj->base.size > gtt_max) {
3140
		DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3141 3142
			  obj->base.size,
			  map_and_fenceable ? "mappable" : "total",
3143
			  gtt_max);
3144 3145 3146
		return -E2BIG;
	}

3147
	ret = i915_gem_object_get_pages(obj);
C
Chris Wilson 已提交
3148 3149 3150
	if (ret)
		return ret;

3151 3152
	i915_gem_object_pin_pages(obj);

3153 3154
	BUG_ON(!i915_is_ggtt(vm));

3155
	vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3156
	if (IS_ERR(vma)) {
3157 3158
		ret = PTR_ERR(vma);
		goto err_unpin;
B
Ben Widawsky 已提交
3159 3160
	}

3161 3162 3163
	/* For now we only ever use 1 vma per object */
	WARN_ON(!list_is_singular(&obj->vma_list));

3164
search_free:
3165
	ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3166
						  size, alignment,
3167 3168
						  obj->cache_level, 0, gtt_max,
						  DRM_MM_SEARCH_DEFAULT);
3169
	if (ret) {
3170
		ret = i915_gem_evict_something(dev, vm, size, alignment,
3171
					       obj->cache_level,
3172 3173
					       map_and_fenceable,
					       nonblocking);
3174 3175
		if (ret == 0)
			goto search_free;
3176

3177
		goto err_free_vma;
3178
	}
B
Ben Widawsky 已提交
3179
	if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3180
					      obj->cache_level))) {
B
Ben Widawsky 已提交
3181
		ret = -EINVAL;
3182
		goto err_remove_node;
3183 3184
	}

3185
	ret = i915_gem_gtt_prepare_object(obj);
B
Ben Widawsky 已提交
3186
	if (ret)
3187
		goto err_remove_node;
3188

3189
	list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
B
Ben Widawsky 已提交
3190
	list_add_tail(&vma->mm_list, &vm->inactive_list);
3191

3192 3193
	if (i915_is_ggtt(vm)) {
		bool mappable, fenceable;
3194

3195 3196
		fenceable = (vma->node.size == fence_size &&
			     (vma->node.start & (fence_alignment - 1)) == 0);
3197

3198 3199
		mappable = (vma->node.start + obj->base.size <=
			    dev_priv->gtt.mappable_end);
3200

3201
		obj->map_and_fenceable = mappable && fenceable;
3202
	}
3203

3204
	WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3205

3206
	trace_i915_vma_bind(vma, map_and_fenceable);
3207
	i915_gem_verify_gtt(dev);
3208
	return 0;
B
Ben Widawsky 已提交
3209

3210
err_remove_node:
3211
	drm_mm_remove_node(&vma->node);
3212
err_free_vma:
B
Ben Widawsky 已提交
3213
	i915_gem_vma_destroy(vma);
3214
err_unpin:
B
Ben Widawsky 已提交
3215 3216
	i915_gem_object_unpin_pages(obj);
	return ret;
3217 3218
}

3219
bool
3220 3221
i915_gem_clflush_object(struct drm_i915_gem_object *obj,
			bool force)
3222 3223 3224 3225 3226
{
	/* If we don't have a page list set up, then we're not pinned
	 * to GPU, and we can ignore the cache flush because it'll happen
	 * again at bind time.
	 */
3227
	if (obj->pages == NULL)
3228
		return false;
3229

3230 3231 3232 3233 3234
	/*
	 * Stolen memory is always coherent with the GPU as it is explicitly
	 * marked as wc by the system, or the system is cache-coherent.
	 */
	if (obj->stolen)
3235
		return false;
3236

3237 3238 3239 3240 3241 3242 3243 3244
	/* If the GPU is snooping the contents of the CPU cache,
	 * we do not need to manually clear the CPU cache lines.  However,
	 * the caches are only snooped when the render cache is
	 * flushed/invalidated.  As we always have to emit invalidations
	 * and flushes when moving into and out of the RENDER domain, correct
	 * snooping behaviour occurs naturally as the result of our domain
	 * tracking.
	 */
3245
	if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3246
		return false;
3247

C
Chris Wilson 已提交
3248
	trace_i915_gem_object_clflush(obj);
3249
	drm_clflush_sg(obj->pages);
3250 3251

	return true;
3252 3253 3254 3255
}

/** Flushes the GTT write domain for the object if it's dirty. */
static void
3256
i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3257
{
C
Chris Wilson 已提交
3258 3259
	uint32_t old_write_domain;

3260
	if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3261 3262
		return;

3263
	/* No actual flushing is required for the GTT write domain.  Writes
3264 3265
	 * to it immediately go to main memory as far as we know, so there's
	 * no chipset flush.  It also doesn't land in render cache.
3266 3267 3268 3269
	 *
	 * However, we do have to enforce the order so that all writes through
	 * the GTT land before any writes to the device, such as updates to
	 * the GATT itself.
3270
	 */
3271 3272
	wmb();

3273 3274
	old_write_domain = obj->base.write_domain;
	obj->base.write_domain = 0;
C
Chris Wilson 已提交
3275 3276

	trace_i915_gem_object_change_domain(obj,
3277
					    obj->base.read_domains,
C
Chris Wilson 已提交
3278
					    old_write_domain);
3279 3280 3281 3282
}

/** Flushes the CPU write domain for the object if it's dirty. */
static void
3283 3284
i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
				       bool force)
3285
{
C
Chris Wilson 已提交
3286
	uint32_t old_write_domain;
3287

3288
	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3289 3290
		return;

3291 3292 3293
	if (i915_gem_clflush_object(obj, force))
		i915_gem_chipset_flush(obj->base.dev);

3294 3295
	old_write_domain = obj->base.write_domain;
	obj->base.write_domain = 0;
C
Chris Wilson 已提交
3296 3297

	trace_i915_gem_object_change_domain(obj,
3298
					    obj->base.read_domains,
C
Chris Wilson 已提交
3299
					    old_write_domain);
3300 3301
}

3302 3303 3304 3305 3306 3307
/**
 * Moves a single object to the GTT read, and possibly write domain.
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
J
Jesse Barnes 已提交
3308
int
3309
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3310
{
3311
	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
C
Chris Wilson 已提交
3312
	uint32_t old_write_domain, old_read_domains;
3313
	int ret;
3314

3315
	/* Not valid to be called on unbound objects. */
3316
	if (!i915_gem_obj_bound_any(obj))
3317 3318
		return -EINVAL;

3319 3320 3321
	if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
		return 0;

3322
	ret = i915_gem_object_wait_rendering(obj, !write);
3323 3324 3325
	if (ret)
		return ret;

3326
	i915_gem_object_flush_cpu_write_domain(obj, false);
C
Chris Wilson 已提交
3327

3328 3329 3330 3331 3332 3333 3334
	/* Serialise direct access to this object with the barriers for
	 * coherent writes from the GPU, by effectively invalidating the
	 * GTT domain upon first access.
	 */
	if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
		mb();

3335 3336
	old_write_domain = obj->base.write_domain;
	old_read_domains = obj->base.read_domains;
C
Chris Wilson 已提交
3337

3338 3339 3340
	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3341 3342
	BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3343
	if (write) {
3344 3345 3346
		obj->base.read_domains = I915_GEM_DOMAIN_GTT;
		obj->base.write_domain = I915_GEM_DOMAIN_GTT;
		obj->dirty = 1;
3347 3348
	}

C
Chris Wilson 已提交
3349 3350 3351 3352
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);

3353
	/* And bump the LRU for this access */
B
Ben Widawsky 已提交
3354 3355 3356 3357 3358 3359 3360 3361
	if (i915_gem_object_is_inactive(obj)) {
		struct i915_vma *vma = i915_gem_obj_to_vma(obj,
							   &dev_priv->gtt.base);
		if (vma)
			list_move_tail(&vma->mm_list,
				       &dev_priv->gtt.base.inactive_list);

	}
3362

3363 3364 3365
	return 0;
}

3366 3367 3368
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level)
{
3369 3370
	struct drm_device *dev = obj->base.dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
3371
	struct i915_vma *vma;
3372 3373 3374 3375 3376 3377 3378 3379 3380 3381
	int ret;

	if (obj->cache_level == cache_level)
		return 0;

	if (obj->pin_count) {
		DRM_DEBUG("can not change the cache level of pinned objects\n");
		return -EBUSY;
	}

3382 3383
	list_for_each_entry(vma, &obj->vma_list, vma_link) {
		if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3384
			ret = i915_vma_unbind(vma);
3385 3386 3387 3388 3389
			if (ret)
				return ret;

			break;
		}
3390 3391
	}

3392
	if (i915_gem_obj_bound_any(obj)) {
3393 3394 3395 3396 3397 3398 3399 3400 3401 3402
		ret = i915_gem_object_finish_gpu(obj);
		if (ret)
			return ret;

		i915_gem_object_finish_gtt(obj);

		/* Before SandyBridge, you could not use tiling or fence
		 * registers with snooped memory, so relinquish any fences
		 * currently pointing to our region in the aperture.
		 */
3403
		if (INTEL_INFO(dev)->gen < 6) {
3404 3405 3406 3407 3408
			ret = i915_gem_object_put_fence(obj);
			if (ret)
				return ret;
		}

3409 3410
		if (obj->has_global_gtt_mapping)
			i915_gem_gtt_bind_object(obj, cache_level);
3411 3412 3413
		if (obj->has_aliasing_ppgtt_mapping)
			i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
					       obj, cache_level);
3414 3415
	}

3416 3417 3418 3419 3420
	list_for_each_entry(vma, &obj->vma_list, vma_link)
		vma->node.color = cache_level;
	obj->cache_level = cache_level;

	if (cpu_write_needs_clflush(obj)) {
3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441
		u32 old_read_domains, old_write_domain;

		/* If we're coming from LLC cached, then we haven't
		 * actually been tracking whether the data is in the
		 * CPU cache or not, since we only allow one bit set
		 * in obj->write_domain and have been skipping the clflushes.
		 * Just set it to the CPU cache for now.
		 */
		WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);

		old_read_domains = obj->base.read_domains;
		old_write_domain = obj->base.write_domain;

		obj->base.read_domains = I915_GEM_DOMAIN_CPU;
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;

		trace_i915_gem_object_change_domain(obj,
						    old_read_domains,
						    old_write_domain);
	}

3442
	i915_gem_verify_gtt(dev);
3443 3444 3445
	return 0;
}

B
Ben Widawsky 已提交
3446 3447
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file)
3448
{
B
Ben Widawsky 已提交
3449
	struct drm_i915_gem_caching *args = data;
3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462
	struct drm_i915_gem_object *obj;
	int ret;

	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}

3463 3464 3465 3466 3467 3468
	switch (obj->cache_level) {
	case I915_CACHE_LLC:
	case I915_CACHE_L3_LLC:
		args->caching = I915_CACHING_CACHED;
		break;

3469 3470 3471 3472
	case I915_CACHE_WT:
		args->caching = I915_CACHING_DISPLAY;
		break;

3473 3474 3475 3476
	default:
		args->caching = I915_CACHING_NONE;
		break;
	}
3477 3478 3479 3480 3481 3482 3483

	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

B
Ben Widawsky 已提交
3484 3485
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file)
3486
{
B
Ben Widawsky 已提交
3487
	struct drm_i915_gem_caching *args = data;
3488 3489 3490 3491
	struct drm_i915_gem_object *obj;
	enum i915_cache_level level;
	int ret;

B
Ben Widawsky 已提交
3492 3493
	switch (args->caching) {
	case I915_CACHING_NONE:
3494 3495
		level = I915_CACHE_NONE;
		break;
B
Ben Widawsky 已提交
3496
	case I915_CACHING_CACHED:
3497 3498
		level = I915_CACHE_LLC;
		break;
3499 3500 3501
	case I915_CACHING_DISPLAY:
		level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
		break;
3502 3503 3504 3505
	default:
		return -EINVAL;
	}

B
Ben Widawsky 已提交
3506 3507 3508 3509
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}

	ret = i915_gem_object_set_cache_level(obj, level);

	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539
static bool is_pin_display(struct drm_i915_gem_object *obj)
{
	/* There are 3 sources that pin objects:
	 *   1. The display engine (scanouts, sprites, cursors);
	 *   2. Reservations for execbuffer;
	 *   3. The user.
	 *
	 * We can ignore reservations as we hold the struct_mutex and
	 * are only called outside of the reservation path.  The user
	 * can only increment pin_count once, and so if after
	 * subtracting the potential reference by the user, any pin_count
	 * remains, it must be due to another use by the display engine.
	 */
	return obj->pin_count - !!obj->user_pin_count;
}

3540
/*
3541 3542 3543
 * Prepare buffer for display plane (scanout, cursors, etc).
 * Can be called from an uninterruptible phase (modesetting) and allows
 * any flushes to be pipelined (for pageflips).
3544 3545
 */
int
3546 3547
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3548
				     struct intel_ring_buffer *pipelined)
3549
{
3550
	u32 old_read_domains, old_write_domain;
3551 3552
	int ret;

3553
	if (pipelined != obj->ring) {
3554 3555
		ret = i915_gem_object_sync(obj, pipelined);
		if (ret)
3556 3557 3558
			return ret;
	}

3559 3560 3561 3562 3563
	/* Mark the pin_display early so that we account for the
	 * display coherency whilst setting up the cache domains.
	 */
	obj->pin_display = true;

3564 3565 3566 3567 3568 3569 3570 3571 3572
	/* The display engine is not coherent with the LLC cache on gen6.  As
	 * a result, we make sure that the pinning that is about to occur is
	 * done with uncached PTEs. This is lowest common denominator for all
	 * chipsets.
	 *
	 * However for gen6+, we could do better by using the GFDT bit instead
	 * of uncaching, which would allow us to flush all the LLC-cached data
	 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
	 */
3573 3574
	ret = i915_gem_object_set_cache_level(obj,
					      HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3575
	if (ret)
3576
		goto err_unpin_display;
3577

3578 3579 3580 3581
	/* As the user may map the buffer once pinned in the display plane
	 * (e.g. libkms for the bootup splash), we have to ensure that we
	 * always use map_and_fenceable for all scanout buffers.
	 */
B
Ben Widawsky 已提交
3582
	ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3583
	if (ret)
3584
		goto err_unpin_display;
3585

3586
	i915_gem_object_flush_cpu_write_domain(obj, true);
3587

3588
	old_write_domain = obj->base.write_domain;
3589
	old_read_domains = obj->base.read_domains;
3590 3591 3592 3593

	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3594
	obj->base.write_domain = 0;
3595
	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3596 3597 3598

	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
3599
					    old_write_domain);
3600 3601

	return 0;
3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612

err_unpin_display:
	obj->pin_display = is_pin_display(obj);
	return ret;
}

void
i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin(obj);
	obj->pin_display = is_pin_display(obj);
3613 3614
}

3615
int
3616
i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3617
{
3618 3619
	int ret;

3620
	if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3621 3622
		return 0;

3623
	ret = i915_gem_object_wait_rendering(obj, false);
3624 3625 3626
	if (ret)
		return ret;

3627 3628
	/* Ensure that we invalidate the GPU's caches and TLBs. */
	obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3629
	return 0;
3630 3631
}

3632 3633 3634 3635 3636 3637
/**
 * Moves a single object to the CPU read, and possibly write domain.
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
3638
int
3639
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3640
{
C
Chris Wilson 已提交
3641
	uint32_t old_write_domain, old_read_domains;
3642 3643
	int ret;

3644 3645 3646
	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
		return 0;

3647
	ret = i915_gem_object_wait_rendering(obj, !write);
3648 3649 3650
	if (ret)
		return ret;

3651
	i915_gem_object_flush_gtt_write_domain(obj);
3652

3653 3654
	old_write_domain = obj->base.write_domain;
	old_read_domains = obj->base.read_domains;
C
Chris Wilson 已提交
3655

3656
	/* Flush the CPU cache if it's still invalid. */
3657
	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3658
		i915_gem_clflush_object(obj, false);
3659

3660
		obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3661 3662 3663 3664 3665
	}

	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3666
	BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3667 3668 3669 3670 3671

	/* If we're writing through the CPU, then the GPU read domains will
	 * need to be invalidated at next use.
	 */
	if (write) {
3672 3673
		obj->base.read_domains = I915_GEM_DOMAIN_CPU;
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3674
	}
3675

C
Chris Wilson 已提交
3676 3677 3678 3679
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);

3680 3681 3682
	return 0;
}

3683 3684 3685
/* Throttle our rendering by waiting until the ring has completed our requests
 * emitted over 20 msec ago.
 *
3686 3687 3688 3689
 * Note that if we were to use the current jiffies each time around the loop,
 * we wouldn't escape the function with any frames outstanding if the time to
 * render a frame was over 20ms.
 *
3690 3691 3692
 * This should get us reasonable parallelism between CPU and GPU but also
 * relatively low latency when blocking on a particular request to finish.
 */
3693
static int
3694
i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3695
{
3696 3697
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_file_private *file_priv = file->driver_priv;
3698
	unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3699 3700
	struct drm_i915_gem_request *request;
	struct intel_ring_buffer *ring = NULL;
3701
	unsigned reset_counter;
3702 3703
	u32 seqno = 0;
	int ret;
3704

3705 3706 3707 3708 3709 3710 3711
	ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
	if (ret)
		return ret;

	ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
	if (ret)
		return ret;
3712

3713
	spin_lock(&file_priv->mm.lock);
3714
	list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3715 3716
		if (time_after_eq(request->emitted_jiffies, recent_enough))
			break;
3717

3718 3719
		ring = request->ring;
		seqno = request->seqno;
3720
	}
3721
	reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3722
	spin_unlock(&file_priv->mm.lock);
3723

3724 3725
	if (seqno == 0)
		return 0;
3726

3727
	ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3728 3729
	if (ret == 0)
		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3730 3731 3732 3733

	return ret;
}

3734
int
3735
i915_gem_object_pin(struct drm_i915_gem_object *obj,
B
Ben Widawsky 已提交
3736
		    struct i915_address_space *vm,
3737
		    uint32_t alignment,
3738 3739
		    bool map_and_fenceable,
		    bool nonblocking)
3740
{
3741
	struct i915_vma *vma;
3742 3743
	int ret;

3744 3745
	if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
		return -EBUSY;
3746

3747 3748 3749 3750 3751 3752 3753
	WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));

	vma = i915_gem_obj_to_vma(obj, vm);

	if (vma) {
		if ((alignment &&
		     vma->node.start & (alignment - 1)) ||
3754 3755
		    (map_and_fenceable && !obj->map_and_fenceable)) {
			WARN(obj->pin_count,
3756
			     "bo is already pinned with incorrect alignment:"
3757
			     " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3758
			     " obj->map_and_fenceable=%d\n",
3759
			     i915_gem_obj_offset(obj, vm), alignment,
3760
			     map_and_fenceable,
3761
			     obj->map_and_fenceable);
3762
			ret = i915_vma_unbind(vma);
3763 3764 3765 3766 3767
			if (ret)
				return ret;
		}
	}

3768
	if (!i915_gem_obj_bound(obj, vm)) {
3769 3770
		struct drm_i915_private *dev_priv = obj->base.dev->dev_private;

3771 3772 3773
		ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
						 map_and_fenceable,
						 nonblocking);
3774
		if (ret)
3775
			return ret;
3776 3777 3778

		if (!dev_priv->mm.aliasing_ppgtt)
			i915_gem_gtt_bind_object(obj, obj->cache_level);
3779
	}
J
Jesse Barnes 已提交
3780

3781 3782 3783
	if (!obj->has_global_gtt_mapping && map_and_fenceable)
		i915_gem_gtt_bind_object(obj, obj->cache_level);

3784
	obj->pin_count++;
3785
	obj->pin_mappable |= map_and_fenceable;
3786 3787 3788 3789 3790

	return 0;
}

void
3791
i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3792
{
3793
	BUG_ON(obj->pin_count == 0);
3794
	BUG_ON(!i915_gem_obj_bound_any(obj));
3795

3796
	if (--obj->pin_count == 0)
3797
		obj->pin_mappable = false;
3798 3799 3800 3801
}

int
i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3802
		   struct drm_file *file)
3803 3804
{
	struct drm_i915_gem_pin *args = data;
3805
	struct drm_i915_gem_object *obj;
3806 3807
	int ret;

3808 3809 3810
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
3811

3812
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3813
	if (&obj->base == NULL) {
3814 3815
		ret = -ENOENT;
		goto unlock;
3816 3817
	}

3818
	if (obj->madv != I915_MADV_WILLNEED) {
C
Chris Wilson 已提交
3819
		DRM_ERROR("Attempting to pin a purgeable buffer\n");
3820 3821
		ret = -EINVAL;
		goto out;
3822 3823
	}

3824
	if (obj->pin_filp != NULL && obj->pin_filp != file) {
J
Jesse Barnes 已提交
3825 3826
		DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
			  args->handle);
3827 3828
		ret = -EINVAL;
		goto out;
J
Jesse Barnes 已提交
3829 3830
	}

3831
	if (obj->user_pin_count == 0) {
B
Ben Widawsky 已提交
3832
		ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3833 3834
		if (ret)
			goto out;
3835 3836
	}

3837 3838 3839
	obj->user_pin_count++;
	obj->pin_filp = file;

3840
	args->offset = i915_gem_obj_ggtt_offset(obj);
3841
out:
3842
	drm_gem_object_unreference(&obj->base);
3843
unlock:
3844
	mutex_unlock(&dev->struct_mutex);
3845
	return ret;
3846 3847 3848 3849
}

int
i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3850
		     struct drm_file *file)
3851 3852
{
	struct drm_i915_gem_pin *args = data;
3853
	struct drm_i915_gem_object *obj;
3854
	int ret;
3855

3856 3857 3858
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
3859

3860
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3861
	if (&obj->base == NULL) {
3862 3863
		ret = -ENOENT;
		goto unlock;
3864
	}
3865

3866
	if (obj->pin_filp != file) {
J
Jesse Barnes 已提交
3867 3868
		DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
			  args->handle);
3869 3870
		ret = -EINVAL;
		goto out;
J
Jesse Barnes 已提交
3871
	}
3872 3873 3874
	obj->user_pin_count--;
	if (obj->user_pin_count == 0) {
		obj->pin_filp = NULL;
J
Jesse Barnes 已提交
3875 3876
		i915_gem_object_unpin(obj);
	}
3877

3878
out:
3879
	drm_gem_object_unreference(&obj->base);
3880
unlock:
3881
	mutex_unlock(&dev->struct_mutex);
3882
	return ret;
3883 3884 3885 3886
}

int
i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3887
		    struct drm_file *file)
3888 3889
{
	struct drm_i915_gem_busy *args = data;
3890
	struct drm_i915_gem_object *obj;
3891 3892
	int ret;

3893
	ret = i915_mutex_lock_interruptible(dev);
3894
	if (ret)
3895
		return ret;
3896

3897
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3898
	if (&obj->base == NULL) {
3899 3900
		ret = -ENOENT;
		goto unlock;
3901
	}
3902

3903 3904 3905 3906
	/* Count all active objects as busy, even if they are currently not used
	 * by the gpu. Users of this interface expect objects to eventually
	 * become non-busy without any further actions, therefore emit any
	 * necessary flushes here.
3907
	 */
3908
	ret = i915_gem_object_flush_active(obj);
3909

3910
	args->busy = obj->active;
3911 3912 3913 3914
	if (obj->ring) {
		BUILD_BUG_ON(I915_NUM_RINGS > 16);
		args->busy |= intel_ring_flag(obj->ring) << 16;
	}
3915

3916
	drm_gem_object_unreference(&obj->base);
3917
unlock:
3918
	mutex_unlock(&dev->struct_mutex);
3919
	return ret;
3920 3921 3922 3923 3924 3925
}

int
i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
3926
	return i915_gem_ring_throttle(dev, file_priv);
3927 3928
}

3929 3930 3931 3932 3933
int
i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
	struct drm_i915_gem_madvise *args = data;
3934
	struct drm_i915_gem_object *obj;
3935
	int ret;
3936 3937 3938 3939 3940 3941 3942 3943 3944

	switch (args->madv) {
	case I915_MADV_DONTNEED:
	case I915_MADV_WILLNEED:
	    break;
	default:
	    return -EINVAL;
	}

3945 3946 3947 3948
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

3949
	obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3950
	if (&obj->base == NULL) {
3951 3952
		ret = -ENOENT;
		goto unlock;
3953 3954
	}

3955
	if (obj->pin_count) {
3956 3957
		ret = -EINVAL;
		goto out;
3958 3959
	}

3960 3961
	if (obj->madv != __I915_MADV_PURGED)
		obj->madv = args->madv;
3962

C
Chris Wilson 已提交
3963 3964
	/* if the object is no longer attached, discard its backing storage */
	if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3965 3966
		i915_gem_object_truncate(obj);

3967
	args->retained = obj->madv != __I915_MADV_PURGED;
C
Chris Wilson 已提交
3968

3969
out:
3970
	drm_gem_object_unreference(&obj->base);
3971
unlock:
3972
	mutex_unlock(&dev->struct_mutex);
3973
	return ret;
3974 3975
}

3976 3977
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			  const struct drm_i915_gem_object_ops *ops)
3978
{
3979
	INIT_LIST_HEAD(&obj->global_list);
3980
	INIT_LIST_HEAD(&obj->ring_list);
3981
	INIT_LIST_HEAD(&obj->obj_exec_link);
B
Ben Widawsky 已提交
3982
	INIT_LIST_HEAD(&obj->vma_list);
3983

3984 3985
	obj->ops = ops;

3986 3987 3988 3989 3990 3991 3992 3993
	obj->fence_reg = I915_FENCE_REG_NONE;
	obj->madv = I915_MADV_WILLNEED;
	/* Avoid an unnecessary call to unbind on the first bind. */
	obj->map_and_fenceable = true;

	i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
}

3994 3995 3996 3997 3998
static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
	.get_pages = i915_gem_object_get_pages_gtt,
	.put_pages = i915_gem_object_put_pages_gtt,
};

3999 4000
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size)
4001
{
4002
	struct drm_i915_gem_object *obj;
4003
	struct address_space *mapping;
D
Daniel Vetter 已提交
4004
	gfp_t mask;
4005

4006
	obj = i915_gem_object_alloc(dev);
4007 4008
	if (obj == NULL)
		return NULL;
4009

4010
	if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4011
		i915_gem_object_free(obj);
4012 4013
		return NULL;
	}
4014

4015 4016 4017 4018 4019 4020 4021
	mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
	if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
		/* 965gm cannot relocate objects above 4GiB. */
		mask &= ~__GFP_HIGHMEM;
		mask |= __GFP_DMA32;
	}

A
Al Viro 已提交
4022
	mapping = file_inode(obj->base.filp)->i_mapping;
4023
	mapping_set_gfp_mask(mapping, mask);
4024

4025
	i915_gem_object_init(obj, &i915_gem_object_ops);
4026

4027 4028
	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4029

4030 4031
	if (HAS_LLC(dev)) {
		/* On some devices, we can have the GPU use the LLC (the CPU
4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046
		 * cache) for about a 10% performance improvement
		 * compared to uncached.  Graphics requests other than
		 * display scanout are coherent with the CPU in
		 * accessing this cache.  This means in this mode we
		 * don't need to clflush on the CPU side, and on the
		 * GPU side we only need to flush internal caches to
		 * get data visible to the CPU.
		 *
		 * However, we maintain the display planes as UC, and so
		 * need to rebind when first used as such.
		 */
		obj->cache_level = I915_CACHE_LLC;
	} else
		obj->cache_level = I915_CACHE_NONE;

4047 4048
	trace_i915_gem_object_create(obj);

4049
	return obj;
4050 4051 4052 4053 4054
}

int i915_gem_init_object(struct drm_gem_object *obj)
{
	BUG();
4055

4056 4057 4058
	return 0;
}

4059
void i915_gem_free_object(struct drm_gem_object *gem_obj)
4060
{
4061
	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4062
	struct drm_device *dev = obj->base.dev;
4063
	drm_i915_private_t *dev_priv = dev->dev_private;
4064
	struct i915_vma *vma, *next;
4065

4066 4067
	trace_i915_gem_object_destroy(obj);

4068 4069 4070 4071
	if (obj->phys_obj)
		i915_gem_detach_phys_object(dev, obj);

	obj->pin_count = 0;
4072 4073 4074 4075 4076 4077 4078
	/* NB: 0 or 1 elements */
	WARN_ON(!list_empty(&obj->vma_list) &&
		!list_is_singular(&obj->vma_list));
	list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
		int ret = i915_vma_unbind(vma);
		if (WARN_ON(ret == -ERESTARTSYS)) {
			bool was_interruptible;
4079

4080 4081
			was_interruptible = dev_priv->mm.interruptible;
			dev_priv->mm.interruptible = false;
4082

4083
			WARN_ON(i915_vma_unbind(vma));
4084

4085 4086
			dev_priv->mm.interruptible = was_interruptible;
		}
4087 4088
	}

B
Ben Widawsky 已提交
4089 4090 4091 4092 4093
	/* Stolen objects don't hold a ref, but do hold pin count. Fix that up
	 * before progressing. */
	if (obj->stolen)
		i915_gem_object_unpin_pages(obj);

B
Ben Widawsky 已提交
4094 4095
	if (WARN_ON(obj->pages_pin_count))
		obj->pages_pin_count = 0;
4096
	i915_gem_object_put_pages(obj);
4097
	i915_gem_object_free_mmap_offset(obj);
4098
	i915_gem_object_release_stolen(obj);
4099

4100 4101
	BUG_ON(obj->pages);

4102 4103
	if (obj->base.import_attach)
		drm_prime_gem_destroy(&obj->base, NULL);
4104

4105 4106
	drm_gem_object_release(&obj->base);
	i915_gem_info_remove_obj(dev_priv, obj->base.size);
4107

4108
	kfree(obj->bit_17);
4109
	i915_gem_object_free(obj);
4110 4111
}

4112
struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
B
Ben Widawsky 已提交
4113
				     struct i915_address_space *vm)
4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124
{
	struct i915_vma *vma;
	list_for_each_entry(vma, &obj->vma_list, vma_link)
		if (vma->vm == vm)
			return vma;

	return NULL;
}

static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
					      struct i915_address_space *vm)
B
Ben Widawsky 已提交
4125 4126 4127 4128 4129 4130
{
	struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
	if (vma == NULL)
		return ERR_PTR(-ENOMEM);

	INIT_LIST_HEAD(&vma->vma_link);
B
Ben Widawsky 已提交
4131
	INIT_LIST_HEAD(&vma->mm_list);
4132
	INIT_LIST_HEAD(&vma->exec_list);
B
Ben Widawsky 已提交
4133 4134 4135
	vma->vm = vm;
	vma->obj = obj;

4136 4137 4138 4139 4140 4141
	/* Keep GGTT vmas first to make debug easier */
	if (i915_is_ggtt(vm))
		list_add(&vma->vma_link, &obj->vma_list);
	else
		list_add_tail(&vma->vma_link, &obj->vma_list);

B
Ben Widawsky 已提交
4142 4143 4144
	return vma;
}

4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
				  struct i915_address_space *vm)
{
	struct i915_vma *vma;

	vma = i915_gem_obj_to_vma(obj, vm);
	if (!vma)
		vma = __i915_gem_vma_create(obj, vm);

	return vma;
}

B
Ben Widawsky 已提交
4158 4159 4160
void i915_gem_vma_destroy(struct i915_vma *vma)
{
	WARN_ON(vma->node.allocated);
4161
	list_del(&vma->vma_link);
B
Ben Widawsky 已提交
4162 4163 4164
	kfree(vma);
}

4165 4166 4167 4168 4169
int
i915_gem_idle(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int ret;
4170

4171
	if (dev_priv->ums.mm_suspended) {
4172 4173
		mutex_unlock(&dev->struct_mutex);
		return 0;
4174 4175
	}

4176
	ret = i915_gpu_idle(dev);
4177 4178
	if (ret) {
		mutex_unlock(&dev->struct_mutex);
4179
		return ret;
4180
	}
4181
	i915_gem_retire_requests(dev);
4182

4183
	/* Under UMS, be paranoid and evict. */
4184
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
C
Chris Wilson 已提交
4185
		i915_gem_evict_everything(dev);
4186

4187
	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4188 4189

	i915_kernel_lost_context(dev);
4190
	i915_gem_cleanup_ringbuffer(dev);
4191 4192 4193 4194

	/* Cancel the retire work handler, which should be idle now. */
	cancel_delayed_work_sync(&dev_priv->mm.retire_work);

4195 4196 4197
	return 0;
}

B
Ben Widawsky 已提交
4198 4199 4200 4201 4202 4203
void i915_gem_l3_remap(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 misccpctl;
	int i;

4204
	if (!HAS_L3_GPU_CACHE(dev))
B
Ben Widawsky 已提交
4205 4206
		return;

4207
	if (!dev_priv->l3_parity.remap_info)
B
Ben Widawsky 已提交
4208 4209 4210 4211 4212 4213 4214 4215
		return;

	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

	for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
		u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4216
		if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
B
Ben Widawsky 已提交
4217 4218
			DRM_DEBUG("0x%x was already programmed to %x\n",
				  GEN7_L3LOG_BASE + i, remap);
4219
		if (remap && !dev_priv->l3_parity.remap_info[i/4])
B
Ben Widawsky 已提交
4220
			DRM_DEBUG_DRIVER("Clearing remapped register\n");
4221
		I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
B
Ben Widawsky 已提交
4222 4223 4224 4225 4226 4227 4228 4229
	}

	/* Make sure all the writes land before disabling dop clock gating */
	POSTING_READ(GEN7_L3LOG_BASE);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
}

4230 4231 4232 4233
void i915_gem_init_swizzling(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;

4234
	if (INTEL_INFO(dev)->gen < 5 ||
4235 4236 4237 4238 4239 4240
	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
		return;

	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
				 DISP_TILE_SURFACE_SWIZZLING);

4241 4242 4243
	if (IS_GEN5(dev))
		return;

4244 4245
	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
	if (IS_GEN6(dev))
4246
		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4247
	else if (IS_GEN7(dev))
4248
		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4249 4250
	else
		BUG();
4251
}
D
Daniel Vetter 已提交
4252

4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268
static bool
intel_enable_blt(struct drm_device *dev)
{
	if (!HAS_BLT(dev))
		return false;

	/* The blitter was dysfunctional on early prototypes */
	if (IS_GEN6(dev) && dev->pdev->revision < 8) {
		DRM_INFO("BLT not supported on this pre-production hardware;"
			 " graphics performance will be degraded.\n");
		return false;
	}

	return true;
}

4269
static int i915_gem_init_rings(struct drm_device *dev)
4270
{
4271
	struct drm_i915_private *dev_priv = dev->dev_private;
4272
	int ret;
4273

4274
	ret = intel_init_render_ring_buffer(dev);
4275
	if (ret)
4276
		return ret;
4277 4278

	if (HAS_BSD(dev)) {
4279
		ret = intel_init_bsd_ring_buffer(dev);
4280 4281
		if (ret)
			goto cleanup_render_ring;
4282
	}
4283

4284
	if (intel_enable_blt(dev)) {
4285 4286 4287 4288 4289
		ret = intel_init_blt_ring_buffer(dev);
		if (ret)
			goto cleanup_bsd_ring;
	}

B
Ben Widawsky 已提交
4290 4291 4292 4293 4294 4295 4296
	if (HAS_VEBOX(dev)) {
		ret = intel_init_vebox_ring_buffer(dev);
		if (ret)
			goto cleanup_blt_ring;
	}


4297
	ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4298
	if (ret)
B
Ben Widawsky 已提交
4299
		goto cleanup_vebox_ring;
4300 4301 4302

	return 0;

B
Ben Widawsky 已提交
4303 4304
cleanup_vebox_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323
cleanup_blt_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
cleanup_bsd_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
cleanup_render_ring:
	intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);

	return ret;
}

int
i915_gem_init_hw(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int ret;

	if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
		return -EIO;

B
Ben Widawsky 已提交
4324
	if (dev_priv->ellc_size)
4325
		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4326

4327 4328 4329 4330 4331 4332
	if (HAS_PCH_NOP(dev)) {
		u32 temp = I915_READ(GEN7_MSG_CTL);
		temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
		I915_WRITE(GEN7_MSG_CTL, temp);
	}

4333 4334 4335 4336 4337
	i915_gem_l3_remap(dev);

	i915_gem_init_swizzling(dev);

	ret = i915_gem_init_rings(dev);
4338 4339 4340
	if (ret)
		return ret;

4341 4342 4343 4344 4345
	/*
	 * XXX: There was some w/a described somewhere suggesting loading
	 * contexts before PPGTT.
	 */
	i915_gem_context_init(dev);
4346 4347 4348 4349 4350 4351 4352
	if (dev_priv->mm.aliasing_ppgtt) {
		ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
		if (ret) {
			i915_gem_cleanup_aliasing_ppgtt(dev);
			DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
		}
	}
D
Daniel Vetter 已提交
4353

4354
	return 0;
4355 4356
}

4357 4358 4359 4360 4361 4362
int i915_gem_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	mutex_lock(&dev->struct_mutex);
4363 4364 4365 4366 4367 4368 4369 4370

	if (IS_VALLEYVIEW(dev)) {
		/* VLVA0 (potential hack), BIOS isn't actually waking us */
		I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
		if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
			DRM_DEBUG_DRIVER("allow wake ack timed out\n");
	}

4371
	i915_gem_init_global_gtt(dev);
4372

4373 4374 4375 4376 4377 4378 4379
	ret = i915_gem_init_hw(dev);
	mutex_unlock(&dev->struct_mutex);
	if (ret) {
		i915_gem_cleanup_aliasing_ppgtt(dev);
		return ret;
	}

4380 4381 4382
	/* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		dev_priv->dri1.allow_batchbuffer = 1;
4383 4384 4385
	return 0;
}

4386 4387 4388 4389
void
i915_gem_cleanup_ringbuffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
4390
	struct intel_ring_buffer *ring;
4391
	int i;
4392

4393 4394
	for_each_ring(ring, dev_priv, i)
		intel_cleanup_ring_buffer(ring);
4395 4396
}

4397 4398 4399 4400
int
i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
4401
	struct drm_i915_private *dev_priv = dev->dev_private;
4402
	int ret;
4403

J
Jesse Barnes 已提交
4404 4405 4406
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return 0;

4407
	if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4408
		DRM_ERROR("Reenabling wedged hardware, good luck\n");
4409
		atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4410 4411 4412
	}

	mutex_lock(&dev->struct_mutex);
4413
	dev_priv->ums.mm_suspended = 0;
4414

4415
	ret = i915_gem_init_hw(dev);
4416 4417
	if (ret != 0) {
		mutex_unlock(&dev->struct_mutex);
4418
		return ret;
4419
	}
4420

4421
	BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4422
	mutex_unlock(&dev->struct_mutex);
4423

4424 4425 4426
	ret = drm_irq_install(dev);
	if (ret)
		goto cleanup_ringbuffer;
4427

4428
	return 0;
4429 4430 4431 4432

cleanup_ringbuffer:
	mutex_lock(&dev->struct_mutex);
	i915_gem_cleanup_ringbuffer(dev);
4433
	dev_priv->ums.mm_suspended = 1;
4434 4435 4436
	mutex_unlock(&dev->struct_mutex);

	return ret;
4437 4438 4439 4440 4441 4442
}

int
i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
4443 4444 4445
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

J
Jesse Barnes 已提交
4446 4447 4448
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return 0;

4449
	drm_irq_uninstall(dev);
4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462

	mutex_lock(&dev->struct_mutex);
	ret =  i915_gem_idle(dev);

	/* Hack!  Don't let anybody do execbuf while we don't control the chip.
	 * We need to replace this with a semaphore, or something.
	 * And not confound ums.mm_suspended!
	 */
	if (ret != 0)
		dev_priv->ums.mm_suspended = 1;
	mutex_unlock(&dev->struct_mutex);

	return ret;
4463 4464 4465 4466 4467 4468 4469
}

void
i915_gem_lastclose(struct drm_device *dev)
{
	int ret;

4470 4471 4472
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return;

4473
	mutex_lock(&dev->struct_mutex);
4474 4475 4476
	ret = i915_gem_idle(dev);
	if (ret)
		DRM_ERROR("failed to idle hardware: %d\n", ret);
4477
	mutex_unlock(&dev->struct_mutex);
4478 4479
}

4480 4481 4482 4483 4484 4485 4486
static void
init_ring_lists(struct intel_ring_buffer *ring)
{
	INIT_LIST_HEAD(&ring->active_list);
	INIT_LIST_HEAD(&ring->request_list);
}

B
Ben Widawsky 已提交
4487 4488 4489 4490 4491 4492 4493 4494 4495 4496
static void i915_init_vm(struct drm_i915_private *dev_priv,
			 struct i915_address_space *vm)
{
	vm->dev = dev_priv->dev;
	INIT_LIST_HEAD(&vm->active_list);
	INIT_LIST_HEAD(&vm->inactive_list);
	INIT_LIST_HEAD(&vm->global_link);
	list_add(&vm->global_link, &dev_priv->vm_list);
}

4497 4498 4499 4500
void
i915_gem_load(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
4501 4502 4503 4504 4505 4506 4507
	int i;

	dev_priv->slab =
		kmem_cache_create("i915_gem_object",
				  sizeof(struct drm_i915_gem_object), 0,
				  SLAB_HWCACHE_ALIGN,
				  NULL);
4508

B
Ben Widawsky 已提交
4509 4510 4511
	INIT_LIST_HEAD(&dev_priv->vm_list);
	i915_init_vm(dev_priv, &dev_priv->gtt.base);

C
Chris Wilson 已提交
4512 4513
	INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
	INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4514
	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4515 4516
	for (i = 0; i < I915_NUM_RINGS; i++)
		init_ring_lists(&dev_priv->ring[i]);
4517
	for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4518
		INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4519 4520
	INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
			  i915_gem_retire_work_handler);
4521
	init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4522

4523 4524
	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
	if (IS_GEN3(dev)) {
4525 4526
		I915_WRITE(MI_ARB_STATE,
			   _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4527 4528
	}

4529 4530
	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;

4531
	/* Old X drivers will take 0-2 for front, back, depth buffers */
4532 4533
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		dev_priv->fence_reg_start = 3;
4534

4535 4536 4537
	if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
		dev_priv->num_fence_regs = 32;
	else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4538 4539 4540 4541
		dev_priv->num_fence_regs = 16;
	else
		dev_priv->num_fence_regs = 8;

4542
	/* Initialize fence registers to zero */
4543 4544
	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
	i915_gem_restore_fences(dev);
4545

4546
	i915_gem_detect_bit_6_swizzle(dev);
4547
	init_waitqueue_head(&dev_priv->pending_flip_queue);
4548

4549 4550
	dev_priv->mm.interruptible = true;

4551 4552 4553
	dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
	dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
	register_shrinker(&dev_priv->mm.inactive_shrinker);
4554
}
4555 4556 4557 4558 4559

/*
 * Create a physically contiguous memory object for this object
 * e.g. for cursor + overlay regs
 */
4560 4561
static int i915_gem_init_phys_object(struct drm_device *dev,
				     int id, int size, int align)
4562 4563 4564 4565 4566 4567 4568 4569
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_phys_object *phys_obj;
	int ret;

	if (dev_priv->mm.phys_objs[id - 1] || !size)
		return 0;

4570
	phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4571 4572 4573 4574 4575
	if (!phys_obj)
		return -ENOMEM;

	phys_obj->id = id;

4576
	phys_obj->handle = drm_pci_alloc(dev, size, align);
4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588
	if (!phys_obj->handle) {
		ret = -ENOMEM;
		goto kfree_obj;
	}
#ifdef CONFIG_X86
	set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
#endif

	dev_priv->mm.phys_objs[id - 1] = phys_obj;

	return 0;
kfree_obj:
4589
	kfree(phys_obj);
4590 4591 4592
	return ret;
}

4593
static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_phys_object *phys_obj;

	if (!dev_priv->mm.phys_objs[id - 1])
		return;

	phys_obj = dev_priv->mm.phys_objs[id - 1];
	if (phys_obj->cur_obj) {
		i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
	}

#ifdef CONFIG_X86
	set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
#endif
	drm_pci_free(dev, phys_obj->handle);
	kfree(phys_obj);
	dev_priv->mm.phys_objs[id - 1] = NULL;
}

void i915_gem_free_all_phys_object(struct drm_device *dev)
{
	int i;

4618
	for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4619 4620 4621 4622
		i915_gem_free_phys_object(dev, i);
}

void i915_gem_detach_phys_object(struct drm_device *dev,
4623
				 struct drm_i915_gem_object *obj)
4624
{
A
Al Viro 已提交
4625
	struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4626
	char *vaddr;
4627 4628 4629
	int i;
	int page_count;

4630
	if (!obj->phys_obj)
4631
		return;
4632
	vaddr = obj->phys_obj->handle->vaddr;
4633

4634
	page_count = obj->base.size / PAGE_SIZE;
4635
	for (i = 0; i < page_count; i++) {
4636
		struct page *page = shmem_read_mapping_page(mapping, i);
4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647
		if (!IS_ERR(page)) {
			char *dst = kmap_atomic(page);
			memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
			kunmap_atomic(dst);

			drm_clflush_pages(&page, 1);

			set_page_dirty(page);
			mark_page_accessed(page);
			page_cache_release(page);
		}
4648
	}
4649
	i915_gem_chipset_flush(dev);
4650

4651 4652
	obj->phys_obj->cur_obj = NULL;
	obj->phys_obj = NULL;
4653 4654 4655 4656
}

int
i915_gem_attach_phys_object(struct drm_device *dev,
4657
			    struct drm_i915_gem_object *obj,
4658 4659
			    int id,
			    int align)
4660
{
A
Al Viro 已提交
4661
	struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4662 4663 4664 4665 4666 4667 4668 4669
	drm_i915_private_t *dev_priv = dev->dev_private;
	int ret = 0;
	int page_count;
	int i;

	if (id > I915_MAX_PHYS_OBJECT)
		return -EINVAL;

4670 4671
	if (obj->phys_obj) {
		if (obj->phys_obj->id == id)
4672 4673 4674 4675 4676 4677 4678
			return 0;
		i915_gem_detach_phys_object(dev, obj);
	}

	/* create a new object */
	if (!dev_priv->mm.phys_objs[id - 1]) {
		ret = i915_gem_init_phys_object(dev, id,
4679
						obj->base.size, align);
4680
		if (ret) {
4681 4682
			DRM_ERROR("failed to init phys object %d size: %zu\n",
				  id, obj->base.size);
4683
			return ret;
4684 4685 4686 4687
		}
	}

	/* bind to the object */
4688 4689
	obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
	obj->phys_obj->cur_obj = obj;
4690

4691
	page_count = obj->base.size / PAGE_SIZE;
4692 4693

	for (i = 0; i < page_count; i++) {
4694 4695 4696
		struct page *page;
		char *dst, *src;

4697
		page = shmem_read_mapping_page(mapping, i);
4698 4699
		if (IS_ERR(page))
			return PTR_ERR(page);
4700

4701
		src = kmap_atomic(page);
4702
		dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4703
		memcpy(dst, src, PAGE_SIZE);
P
Peter Zijlstra 已提交
4704
		kunmap_atomic(src);
4705

4706 4707 4708
		mark_page_accessed(page);
		page_cache_release(page);
	}
4709

4710 4711 4712 4713
	return 0;
}

static int
4714 4715
i915_gem_phys_pwrite(struct drm_device *dev,
		     struct drm_i915_gem_object *obj,
4716 4717 4718
		     struct drm_i915_gem_pwrite *args,
		     struct drm_file *file_priv)
{
4719
	void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
V
Ville Syrjälä 已提交
4720
	char __user *user_data = to_user_ptr(args->data_ptr);
4721

4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734
	if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
		unsigned long unwritten;

		/* The physical object once assigned is fixed for the lifetime
		 * of the obj, so we can safely drop the lock and continue
		 * to access vaddr.
		 */
		mutex_unlock(&dev->struct_mutex);
		unwritten = copy_from_user(vaddr, user_data, args->size);
		mutex_lock(&dev->struct_mutex);
		if (unwritten)
			return -EFAULT;
	}
4735

4736
	i915_gem_chipset_flush(dev);
4737 4738
	return 0;
}
4739

4740
void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4741
{
4742
	struct drm_i915_file_private *file_priv = file->driver_priv;
4743 4744 4745 4746 4747

	/* Clean up our request list when the client is going away, so that
	 * later retire_requests won't dereference our soon-to-be-gone
	 * file_priv.
	 */
4748
	spin_lock(&file_priv->mm.lock);
4749 4750 4751 4752 4753 4754 4755 4756 4757
	while (!list_empty(&file_priv->mm.request_list)) {
		struct drm_i915_gem_request *request;

		request = list_first_entry(&file_priv->mm.request_list,
					   struct drm_i915_gem_request,
					   client_list);
		list_del(&request->client_list);
		request->file_priv = NULL;
	}
4758
	spin_unlock(&file_priv->mm.lock);
4759
}
4760

4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773
static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
{
	if (!mutex_is_locked(mutex))
		return false;

#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
	return mutex->owner == task;
#else
	/* Since UP may be pre-empted, we cannot assume that we own the lock */
	return false;
#endif
}

4774
static int
4775
i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4776
{
4777 4778 4779 4780 4781
	struct drm_i915_private *dev_priv =
		container_of(shrinker,
			     struct drm_i915_private,
			     mm.inactive_shrinker);
	struct drm_device *dev = dev_priv->dev;
C
Chris Wilson 已提交
4782
	struct drm_i915_gem_object *obj;
4783
	int nr_to_scan = sc->nr_to_scan;
4784
	bool unlock = true;
4785 4786
	int cnt;

4787 4788 4789 4790
	if (!mutex_trylock(&dev->struct_mutex)) {
		if (!mutex_is_locked_by(&dev->struct_mutex, current))
			return 0;

4791 4792 4793
		if (dev_priv->mm.shrinker_no_lock_stealing)
			return 0;

4794 4795
		unlock = false;
	}
4796

C
Chris Wilson 已提交
4797 4798
	if (nr_to_scan) {
		nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4799 4800 4801
		if (nr_to_scan > 0)
			nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
							false);
C
Chris Wilson 已提交
4802 4803
		if (nr_to_scan > 0)
			i915_gem_shrink_all(dev_priv);
4804 4805
	}

4806
	cnt = 0;
4807
	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4808 4809
		if (obj->pages_pin_count == 0)
			cnt += obj->base.size >> PAGE_SHIFT;
4810 4811 4812 4813 4814

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
		if (obj->active)
			continue;

4815
		if (obj->pin_count == 0 && obj->pages_pin_count == 0)
C
Chris Wilson 已提交
4816
			cnt += obj->base.size >> PAGE_SHIFT;
4817
	}
4818

4819 4820
	if (unlock)
		mutex_unlock(&dev->struct_mutex);
C
Chris Wilson 已提交
4821
	return cnt;
4822
}
4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848

/* All the new VM stuff */
unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
				  struct i915_address_space *vm)
{
	struct drm_i915_private *dev_priv = o->base.dev->dev_private;
	struct i915_vma *vma;

	if (vm == &dev_priv->mm.aliasing_ppgtt->base)
		vm = &dev_priv->gtt.base;

	BUG_ON(list_empty(&o->vma_list));
	list_for_each_entry(vma, &o->vma_list, vma_link) {
		if (vma->vm == vm)
			return vma->node.start;

	}
	return -1;
}

bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
			struct i915_address_space *vm)
{
	struct i915_vma *vma;

	list_for_each_entry(vma, &o->vma_list, vma_link)
4849
		if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883
			return true;

	return false;
}

bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
{
	struct drm_i915_private *dev_priv = o->base.dev->dev_private;
	struct i915_address_space *vm;

	list_for_each_entry(vm, &dev_priv->vm_list, global_link)
		if (i915_gem_obj_bound(o, vm))
			return true;

	return false;
}

unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
				struct i915_address_space *vm)
{
	struct drm_i915_private *dev_priv = o->base.dev->dev_private;
	struct i915_vma *vma;

	if (vm == &dev_priv->mm.aliasing_ppgtt->base)
		vm = &dev_priv->gtt.base;

	BUG_ON(list_empty(&o->vma_list));

	list_for_each_entry(vma, &o->vma_list, vma_link)
		if (vma->vm == vm)
			return vma->node.size;

	return 0;
}