i40e_txrx.c 105.1 KB
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2013 - 2018 Intel Corporation. */
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Mitch Williams 已提交
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#include <linux/prefetch.h>
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#include <linux/bpf_trace.h>
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#include <net/xdp.h>
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#include "i40e.h"
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Scott Peterson 已提交
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#include "i40e_trace.h"
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#include "i40e_prototype.h"
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#include "i40e_txrx_common.h"
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#include "i40e_xsk.h"
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#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
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/**
 * i40e_fdir - Generate a Flow Director descriptor based on fdata
 * @tx_ring: Tx ring to send buffer on
 * @fdata: Flow director filter data
 * @add: Indicate if we are adding a rule or deleting one
 *
 **/
static void i40e_fdir(struct i40e_ring *tx_ring,
		      struct i40e_fdir_filter *fdata, bool add)
{
	struct i40e_filter_program_desc *fdir_desc;
	struct i40e_pf *pf = tx_ring->vsi->back;
	u32 flex_ptype, dtype_cmd;
	u16 i;

	/* grab the next descriptor */
	i = tx_ring->next_to_use;
	fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);

	i++;
	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;

	flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK &
		     (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT);

	flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK &
		      (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);

	flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
		      (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);

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	flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
		      (fdata->flex_offset << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);

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	/* Use LAN VSI Id if not programmed by user */
	flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK &
		      ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) <<
		       I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT);

	dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;

	dtype_cmd |= add ?
		     I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
		     I40E_TXD_FLTR_QW1_PCMD_SHIFT :
		     I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
		     I40E_TXD_FLTR_QW1_PCMD_SHIFT;

	dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK &
		     (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT);

	dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK &
		     (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT);

	if (fdata->cnt_index) {
		dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
		dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK &
			     ((u32)fdata->cnt_index <<
			      I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT);
	}

	fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
	fdir_desc->rsvd = cpu_to_le32(0);
	fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
	fdir_desc->fd_id = cpu_to_le32(fdata->fd_id);
}

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#define I40E_FD_CLEAN_DELAY 10
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/**
 * i40e_program_fdir_filter - Program a Flow Director filter
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 * @fdir_data: Packet data that will be filter parameters
 * @raw_packet: the pre-allocated packet buffer for FDir
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 * @pf: The PF pointer
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 * @add: True for add/update, False for remove
 **/
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static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data,
				    u8 *raw_packet, struct i40e_pf *pf,
				    bool add)
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{
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	struct i40e_tx_buffer *tx_buf, *first;
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	struct i40e_tx_desc *tx_desc;
	struct i40e_ring *tx_ring;
	struct i40e_vsi *vsi;
	struct device *dev;
	dma_addr_t dma;
	u32 td_cmd = 0;
	u16 i;

	/* find existing FDIR VSI */
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	vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
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	if (!vsi)
		return -ENOENT;

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	tx_ring = vsi->tx_rings[0];
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	dev = tx_ring->dev;

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	/* we need two descriptors to add/del a filter and we can wait */
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	for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) {
		if (!i)
			return -EAGAIN;
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		msleep_interruptible(1);
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	}
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	dma = dma_map_single(dev, raw_packet,
			     I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
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	if (dma_mapping_error(dev, dma))
		goto dma_fail;

	/* grab the next descriptor */
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	i = tx_ring->next_to_use;
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	first = &tx_ring->tx_bi[i];
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	i40e_fdir(tx_ring, fdir_data, add);
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	/* Now program a dummy descriptor */
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	i = tx_ring->next_to_use;
	tx_desc = I40E_TX_DESC(tx_ring, i);
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	tx_buf = &tx_ring->tx_bi[i];
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	tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;

	memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
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	/* record length, and DMA address */
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	dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
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	dma_unmap_addr_set(tx_buf, dma, dma);

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	tx_desc->buffer_addr = cpu_to_le64(dma);
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	td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
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	tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
	tx_buf->raw_buf = (void *)raw_packet;

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	tx_desc->cmd_type_offset_bsz =
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		build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
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	/* Force memory writes to complete before letting h/w
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	 * know there are new descriptors to fetch.
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	 */
	wmb();

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	/* Mark the data descriptor to be watched */
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	first->next_to_watch = tx_desc;
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	writel(tx_ring->next_to_use, tx_ring->tail);
	return 0;

dma_fail:
	return -1;
}

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#define IP_HEADER_OFFSET 14
#define I40E_UDPIP_DUMMY_PACKET_LEN 42
/**
 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
 * @vsi: pointer to the targeted VSI
 * @fd_data: the flow director data required for the FDir descriptor
 * @add: true adds a filter, false removes it
 *
 * Returns 0 if the filters were successfully added or removed
 **/
static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
				   struct i40e_fdir_filter *fd_data,
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				   bool add)
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{
	struct i40e_pf *pf = vsi->back;
	struct udphdr *udp;
	struct iphdr *ip;
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	u8 *raw_packet;
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	int ret;
	static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
		0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};

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	raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
	if (!raw_packet)
		return -ENOMEM;
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	memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);

	ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
	udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
	      + sizeof(struct iphdr));

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	ip->daddr = fd_data->dst_ip;
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	udp->dest = fd_data->dst_port;
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	ip->saddr = fd_data->src_ip;
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	udp->source = fd_data->src_port;

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	if (fd_data->flex_filter) {
		u8 *payload = raw_packet + I40E_UDPIP_DUMMY_PACKET_LEN;
		__be16 pattern = fd_data->flex_word;
		u16 off = fd_data->flex_offset;

		*((__force __be16 *)(payload + off)) = pattern;
	}

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	fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
	ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
	if (ret) {
		dev_info(&pf->pdev->dev,
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			 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
			 fd_data->pctype, fd_data->fd_id, ret);
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		/* Free the packet buffer since it wasn't added to the ring */
		kfree(raw_packet);
		return -EOPNOTSUPP;
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	} else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
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		if (add)
			dev_info(&pf->pdev->dev,
				 "Filter OK for PCTYPE %d loc = %d\n",
				 fd_data->pctype, fd_data->fd_id);
		else
			dev_info(&pf->pdev->dev,
				 "Filter deleted for PCTYPE %d loc = %d\n",
				 fd_data->pctype, fd_data->fd_id);
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	}
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	if (add)
		pf->fd_udp4_filter_cnt++;
	else
		pf->fd_udp4_filter_cnt--;

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	return 0;
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}

#define I40E_TCPIP_DUMMY_PACKET_LEN 54
/**
 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
 * @vsi: pointer to the targeted VSI
 * @fd_data: the flow director data required for the FDir descriptor
 * @add: true adds a filter, false removes it
 *
 * Returns 0 if the filters were successfully added or removed
 **/
static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
				   struct i40e_fdir_filter *fd_data,
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				   bool add)
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{
	struct i40e_pf *pf = vsi->back;
	struct tcphdr *tcp;
	struct iphdr *ip;
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	u8 *raw_packet;
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	int ret;
	/* Dummy packet */
	static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
		0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
		0x0, 0x72, 0, 0, 0, 0};

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	raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
	if (!raw_packet)
		return -ENOMEM;
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	memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);

	ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
	tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
	      + sizeof(struct iphdr));

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	ip->daddr = fd_data->dst_ip;
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	tcp->dest = fd_data->dst_port;
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	ip->saddr = fd_data->src_ip;
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	tcp->source = fd_data->src_port;

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	if (fd_data->flex_filter) {
		u8 *payload = raw_packet + I40E_TCPIP_DUMMY_PACKET_LEN;
		__be16 pattern = fd_data->flex_word;
		u16 off = fd_data->flex_offset;

		*((__force __be16 *)(payload + off)) = pattern;
	}

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	fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
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	ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
	if (ret) {
		dev_info(&pf->pdev->dev,
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			 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
			 fd_data->pctype, fd_data->fd_id, ret);
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		/* Free the packet buffer since it wasn't added to the ring */
		kfree(raw_packet);
		return -EOPNOTSUPP;
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	} else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
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		if (add)
			dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
				 fd_data->pctype, fd_data->fd_id);
		else
			dev_info(&pf->pdev->dev,
				 "Filter deleted for PCTYPE %d loc = %d\n",
				 fd_data->pctype, fd_data->fd_id);
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	}

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	if (add) {
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		pf->fd_tcp4_filter_cnt++;
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		if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
		    I40E_DEBUG_FD & pf->hw.debug_mask)
			dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
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		set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
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	} else {
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		pf->fd_tcp4_filter_cnt--;
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	}

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	return 0;
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}

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#define I40E_SCTPIP_DUMMY_PACKET_LEN 46
/**
 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
 * a specific flow spec
 * @vsi: pointer to the targeted VSI
 * @fd_data: the flow director data required for the FDir descriptor
 * @add: true adds a filter, false removes it
 *
 * Returns 0 if the filters were successfully added or removed
 **/
static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
				    struct i40e_fdir_filter *fd_data,
				    bool add)
{
	struct i40e_pf *pf = vsi->back;
	struct sctphdr *sctp;
	struct iphdr *ip;
	u8 *raw_packet;
	int ret;
	/* Dummy packet */
	static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
		0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0,
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};

	raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
	if (!raw_packet)
		return -ENOMEM;
	memcpy(raw_packet, packet, I40E_SCTPIP_DUMMY_PACKET_LEN);

	ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
	sctp = (struct sctphdr *)(raw_packet + IP_HEADER_OFFSET
	      + sizeof(struct iphdr));

	ip->daddr = fd_data->dst_ip;
	sctp->dest = fd_data->dst_port;
	ip->saddr = fd_data->src_ip;
	sctp->source = fd_data->src_port;

	if (fd_data->flex_filter) {
		u8 *payload = raw_packet + I40E_SCTPIP_DUMMY_PACKET_LEN;
		__be16 pattern = fd_data->flex_word;
		u16 off = fd_data->flex_offset;

		*((__force __be16 *)(payload + off)) = pattern;
	}

	fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
	ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
	if (ret) {
		dev_info(&pf->pdev->dev,
			 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
			 fd_data->pctype, fd_data->fd_id, ret);
		/* Free the packet buffer since it wasn't added to the ring */
		kfree(raw_packet);
		return -EOPNOTSUPP;
	} else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
		if (add)
			dev_info(&pf->pdev->dev,
				 "Filter OK for PCTYPE %d loc = %d\n",
				 fd_data->pctype, fd_data->fd_id);
		else
			dev_info(&pf->pdev->dev,
				 "Filter deleted for PCTYPE %d loc = %d\n",
				 fd_data->pctype, fd_data->fd_id);
	}

	if (add)
		pf->fd_sctp4_filter_cnt++;
	else
		pf->fd_sctp4_filter_cnt--;

	return 0;
}

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#define I40E_IP_DUMMY_PACKET_LEN 34
/**
 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
 * a specific flow spec
 * @vsi: pointer to the targeted VSI
 * @fd_data: the flow director data required for the FDir descriptor
 * @add: true adds a filter, false removes it
 *
 * Returns 0 if the filters were successfully added or removed
 **/
static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
				  struct i40e_fdir_filter *fd_data,
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				  bool add)
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{
	struct i40e_pf *pf = vsi->back;
	struct iphdr *ip;
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	u8 *raw_packet;
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	int ret;
	int i;
	static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
		0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
		0, 0, 0, 0};

	for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
	     i <= I40E_FILTER_PCTYPE_FRAG_IPV4;	i++) {
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		raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
		if (!raw_packet)
			return -ENOMEM;
		memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
		ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);

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		ip->saddr = fd_data->src_ip;
		ip->daddr = fd_data->dst_ip;
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		ip->protocol = 0;

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		if (fd_data->flex_filter) {
			u8 *payload = raw_packet + I40E_IP_DUMMY_PACKET_LEN;
			__be16 pattern = fd_data->flex_word;
			u16 off = fd_data->flex_offset;

			*((__force __be16 *)(payload + off)) = pattern;
		}

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		fd_data->pctype = i;
		ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
		if (ret) {
			dev_info(&pf->pdev->dev,
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				 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
				 fd_data->pctype, fd_data->fd_id, ret);
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			/* The packet buffer wasn't added to the ring so we
			 * need to free it now.
			 */
			kfree(raw_packet);
			return -EOPNOTSUPP;
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		} else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
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			if (add)
				dev_info(&pf->pdev->dev,
					 "Filter OK for PCTYPE %d loc = %d\n",
					 fd_data->pctype, fd_data->fd_id);
			else
				dev_info(&pf->pdev->dev,
					 "Filter deleted for PCTYPE %d loc = %d\n",
					 fd_data->pctype, fd_data->fd_id);
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		}
	}

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	if (add)
		pf->fd_ip4_filter_cnt++;
	else
		pf->fd_ip4_filter_cnt--;

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	return 0;
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}

/**
 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
 * @vsi: pointer to the targeted VSI
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 * @input: filter to add or delete
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 * @add: true adds a filter, false removes it
 *
 **/
int i40e_add_del_fdir(struct i40e_vsi *vsi,
		      struct i40e_fdir_filter *input, bool add)
{
	struct i40e_pf *pf = vsi->back;
	int ret;

	switch (input->flow_type & ~FLOW_EXT) {
	case TCP_V4_FLOW:
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		ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
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		break;
	case UDP_V4_FLOW:
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		ret = i40e_add_del_fdir_udpv4(vsi, input, add);
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		break;
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	case SCTP_V4_FLOW:
		ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
		break;
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	case IP_USER_FLOW:
		switch (input->ip4_proto) {
		case IPPROTO_TCP:
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			ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
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			break;
		case IPPROTO_UDP:
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			ret = i40e_add_del_fdir_udpv4(vsi, input, add);
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			break;
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		case IPPROTO_SCTP:
			ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
			break;
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		case IPPROTO_IP:
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			ret = i40e_add_del_fdir_ipv4(vsi, input, add);
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			break;
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		default:
			/* We cannot support masking based on protocol */
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			dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n",
				 input->ip4_proto);
			return -EINVAL;
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		}
		break;
	default:
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		dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n",
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			 input->flow_type);
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		return -EINVAL;
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	}

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	/* The buffer allocated here will be normally be freed by
	 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit
	 * completion. In the event of an error adding the buffer to the FDIR
	 * ring, it will immediately be freed. It may also be freed by
	 * i40e_clean_tx_ring() when closing the VSI.
	 */
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	return ret;
}

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/**
 * i40e_fd_handle_status - check the Programming Status for FD
 * @rx_ring: the Rx ring for this descriptor
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 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
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 * @prog_id: the id originally used for programming
 *
 * This is used to verify if the FD programming or invalidation
 * requested by SW to the HW is successful or not and take actions accordingly.
 **/
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void i40e_fd_handle_status(struct i40e_ring *rx_ring,
			   union i40e_rx_desc *rx_desc, u8 prog_id)
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{
533 534 535
	struct i40e_pf *pf = rx_ring->vsi->back;
	struct pci_dev *pdev = pf->pdev;
	u32 fcnt_prog, fcnt_avail;
536
	u32 error;
537
	u64 qw;
538

539
	qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
540 541 542
	error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
		I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;

543
	if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
544
		pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id);
545 546 547
		if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
		    (I40E_DEBUG_FD & pf->hw.debug_mask))
			dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
548
				 pf->fd_inv);
549

550 551 552 553 554 555
		/* Check if the programming error is for ATR.
		 * If so, auto disable ATR and set a state for
		 * flush in progress. Next time we come here if flush is in
		 * progress do nothing, once flush is complete the state will
		 * be cleared.
		 */
556
		if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
557 558
			return;

559 560 561 562
		pf->fd_add_err++;
		/* store the current atr filter count */
		pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);

563
		if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
564 565 566 567 568 569 570 571
		    test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) {
			/* These set_bit() calls aren't atomic with the
			 * test_bit() here, but worse case we potentially
			 * disable ATR and queue a flush right after SB
			 * support is re-enabled. That shouldn't cause an
			 * issue in practice
			 */
			set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
572
			set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
573 574
		}

575
		/* filter programming failed most likely due to table full */
576
		fcnt_prog = i40e_get_global_fd_count(pf);
577
		fcnt_avail = pf->fdir_pf_filter_count;
578 579 580 581 582
		/* If ATR is running fcnt_prog can quickly change,
		 * if we are very close to full, it makes sense to disable
		 * FD ATR/SB and then re-enable it when there is room.
		 */
		if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
583
			if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
584 585
			    !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED,
					      pf->state))
586 587
				if (I40E_DEBUG_FD & pf->hw.debug_mask)
					dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
588
		}
589
	} else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
590
		if (I40E_DEBUG_FD & pf->hw.debug_mask)
591
			dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
592
				 rx_desc->wb.qword0.hi_dword.fd_id);
593
	}
594 595 596
}

/**
A
Alexander Duyck 已提交
597
 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
598 599 600
 * @ring:      the ring that owns the buffer
 * @tx_buffer: the buffer to free
 **/
A
Alexander Duyck 已提交
601 602
static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
					    struct i40e_tx_buffer *tx_buffer)
603
{
A
Alexander Duyck 已提交
604
	if (tx_buffer->skb) {
605 606
		if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
			kfree(tx_buffer->raw_buf);
607
		else if (ring_is_xdp(ring))
608
			xdp_return_frame(tx_buffer->xdpf);
609 610
		else
			dev_kfree_skb_any(tx_buffer->skb);
A
Alexander Duyck 已提交
611
		if (dma_unmap_len(tx_buffer, len))
612
			dma_unmap_single(ring->dev,
613 614
					 dma_unmap_addr(tx_buffer, dma),
					 dma_unmap_len(tx_buffer, len),
615
					 DMA_TO_DEVICE);
A
Alexander Duyck 已提交
616 617 618 619 620
	} else if (dma_unmap_len(tx_buffer, len)) {
		dma_unmap_page(ring->dev,
			       dma_unmap_addr(tx_buffer, dma),
			       dma_unmap_len(tx_buffer, len),
			       DMA_TO_DEVICE);
621
	}
622

A
Alexander Duyck 已提交
623 624
	tx_buffer->next_to_watch = NULL;
	tx_buffer->skb = NULL;
625
	dma_unmap_len_set(tx_buffer, len, 0);
A
Alexander Duyck 已提交
626
	/* tx_buffer must be completely set up in the transmit path */
627 628 629 630 631 632 633 634 635 636 637
}

/**
 * i40e_clean_tx_ring - Free any empty Tx buffers
 * @tx_ring: ring to be cleaned
 **/
void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
{
	unsigned long bi_size;
	u16 i;

638 639 640 641 642 643
	if (ring_is_xdp(tx_ring) && tx_ring->xsk_umem) {
		i40e_xsk_clean_tx_ring(tx_ring);
	} else {
		/* ring already cleared, nothing to do */
		if (!tx_ring->tx_bi)
			return;
644

645 646 647 648 649
		/* Free all the Tx ring sk_buffs */
		for (i = 0; i < tx_ring->count; i++)
			i40e_unmap_and_free_tx_resource(tx_ring,
							&tx_ring->tx_bi[i]);
	}
650 651 652 653 654 655 656 657 658

	bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
	memset(tx_ring->tx_bi, 0, bi_size);

	/* Zero out the descriptor ring */
	memset(tx_ring->desc, 0, tx_ring->size);

	tx_ring->next_to_use = 0;
	tx_ring->next_to_clean = 0;
659 660 661 662 663

	if (!tx_ring->netdev)
		return;

	/* cleanup Tx queue statistics */
664
	netdev_tx_reset_queue(txring_txq(tx_ring));
665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687
}

/**
 * i40e_free_tx_resources - Free Tx resources per queue
 * @tx_ring: Tx descriptor ring for a specific queue
 *
 * Free all transmit software resources
 **/
void i40e_free_tx_resources(struct i40e_ring *tx_ring)
{
	i40e_clean_tx_ring(tx_ring);
	kfree(tx_ring->tx_bi);
	tx_ring->tx_bi = NULL;

	if (tx_ring->desc) {
		dma_free_coherent(tx_ring->dev, tx_ring->size,
				  tx_ring->desc, tx_ring->dma);
		tx_ring->desc = NULL;
	}
}

/**
 * i40e_get_tx_pending - how many tx descriptors not processed
688
 * @ring: the ring of descriptors
689
 * @in_sw: use SW variables
690 691 692 693
 *
 * Since there is no access to the ring head register
 * in XL710, we need to use our local copies
 **/
694
u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw)
695
{
J
Jesse Brandeburg 已提交
696 697
	u32 head, tail;

698 699 700 701 702 703 704
	if (!in_sw) {
		head = i40e_get_head(ring);
		tail = readl(ring->tail);
	} else {
		head = ring->next_to_clean;
		tail = ring->next_to_use;
	}
J
Jesse Brandeburg 已提交
705 706 707 708 709 710

	if (head != tail)
		return (head < tail) ?
			tail - head : (tail + ring->count - head);

	return 0;
711 712
}

713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760
/**
 * i40e_detect_recover_hung - Function to detect and recover hung_queues
 * @vsi:  pointer to vsi struct with tx queues
 *
 * VSI has netdev and netdev has TX queues. This function is to check each of
 * those TX queues if they are hung, trigger recovery by issuing SW interrupt.
 **/
void i40e_detect_recover_hung(struct i40e_vsi *vsi)
{
	struct i40e_ring *tx_ring = NULL;
	struct net_device *netdev;
	unsigned int i;
	int packets;

	if (!vsi)
		return;

	if (test_bit(__I40E_VSI_DOWN, vsi->state))
		return;

	netdev = vsi->netdev;
	if (!netdev)
		return;

	if (!netif_carrier_ok(netdev))
		return;

	for (i = 0; i < vsi->num_queue_pairs; i++) {
		tx_ring = vsi->tx_rings[i];
		if (tx_ring && tx_ring->desc) {
			/* If packet counter has not changed the queue is
			 * likely stalled, so force an interrupt for this
			 * queue.
			 *
			 * prev_pkt_ctr would be negative if there was no
			 * pending work.
			 */
			packets = tx_ring->stats.packets & INT_MAX;
			if (tx_ring->tx_stats.prev_pkt_ctr == packets) {
				i40e_force_wb(vsi, tx_ring->q_vector);
				continue;
			}

			/* Memory barrier between read of packet count and call
			 * to i40e_get_tx_pending()
			 */
			smp_rmb();
			tx_ring->tx_stats.prev_pkt_ctr =
761
			    i40e_get_tx_pending(tx_ring, true) ? packets : -1;
762 763 764 765
		}
	}
}

766 767
/**
 * i40e_clean_tx_irq - Reclaim resources after transmit completes
768 769 770
 * @vsi: the VSI we care about
 * @tx_ring: Tx ring to clean
 * @napi_budget: Used to determine if we are in netpoll
771 772 773
 *
 * Returns true if there's any budget left (e.g. the clean is finished)
 **/
774 775
static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
			      struct i40e_ring *tx_ring, int napi_budget)
776 777 778
{
	u16 i = tx_ring->next_to_clean;
	struct i40e_tx_buffer *tx_buf;
779
	struct i40e_tx_desc *tx_head;
780
	struct i40e_tx_desc *tx_desc;
781 782
	unsigned int total_bytes = 0, total_packets = 0;
	unsigned int budget = vsi->work_limit;
783 784 785

	tx_buf = &tx_ring->tx_bi[i];
	tx_desc = I40E_TX_DESC(tx_ring, i);
A
Alexander Duyck 已提交
786
	i -= tx_ring->count;
787

788 789
	tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));

A
Alexander Duyck 已提交
790 791
	do {
		struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
792 793 794 795 796

		/* if next_to_watch is not set then there is no work pending */
		if (!eop_desc)
			break;

A
Alexander Duyck 已提交
797
		/* prevent any other reads prior to eop_desc */
798
		smp_rmb();
A
Alexander Duyck 已提交
799

S
Scott Peterson 已提交
800
		i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
801 802
		/* we have caught up to head, no work left to do */
		if (tx_head == tx_desc)
803 804
			break;

A
Alexander Duyck 已提交
805
		/* clear next_to_watch to prevent false hangs */
806 807
		tx_buf->next_to_watch = NULL;

A
Alexander Duyck 已提交
808 809 810
		/* update the statistics for this packet */
		total_bytes += tx_buf->bytecount;
		total_packets += tx_buf->gso_segs;
811

812 813
		/* free the skb/XDP data */
		if (ring_is_xdp(tx_ring))
814
			xdp_return_frame(tx_buf->xdpf);
815 816
		else
			napi_consume_skb(tx_buf->skb, napi_budget);
817

A
Alexander Duyck 已提交
818 819 820 821 822
		/* unmap skb header data */
		dma_unmap_single(tx_ring->dev,
				 dma_unmap_addr(tx_buf, dma),
				 dma_unmap_len(tx_buf, len),
				 DMA_TO_DEVICE);
823

A
Alexander Duyck 已提交
824 825 826
		/* clear tx_buffer data */
		tx_buf->skb = NULL;
		dma_unmap_len_set(tx_buf, len, 0);
827

A
Alexander Duyck 已提交
828 829
		/* unmap remaining buffers */
		while (tx_desc != eop_desc) {
S
Scott Peterson 已提交
830 831
			i40e_trace(clean_tx_irq_unmap,
				   tx_ring, tx_desc, tx_buf);
832 833 834 835

			tx_buf++;
			tx_desc++;
			i++;
A
Alexander Duyck 已提交
836 837
			if (unlikely(!i)) {
				i -= tx_ring->count;
838 839 840 841
				tx_buf = tx_ring->tx_bi;
				tx_desc = I40E_TX_DESC(tx_ring, 0);
			}

A
Alexander Duyck 已提交
842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861
			/* unmap any remaining paged data */
			if (dma_unmap_len(tx_buf, len)) {
				dma_unmap_page(tx_ring->dev,
					       dma_unmap_addr(tx_buf, dma),
					       dma_unmap_len(tx_buf, len),
					       DMA_TO_DEVICE);
				dma_unmap_len_set(tx_buf, len, 0);
			}
		}

		/* move us one more past the eop_desc for start of next pkt */
		tx_buf++;
		tx_desc++;
		i++;
		if (unlikely(!i)) {
			i -= tx_ring->count;
			tx_buf = tx_ring->tx_bi;
			tx_desc = I40E_TX_DESC(tx_ring, 0);
		}

862 863
		prefetch(tx_desc);

A
Alexander Duyck 已提交
864 865 866 867 868
		/* update budget accounting */
		budget--;
	} while (likely(budget));

	i += tx_ring->count;
869
	tx_ring->next_to_clean = i;
870 871
	i40e_update_tx_stats(tx_ring, total_packets, total_bytes);
	i40e_arm_wb(tx_ring, vsi, budget);
872

873 874 875
	if (ring_is_xdp(tx_ring))
		return !!budget;

876 877
	/* notify netdev of completed buffers */
	netdev_tx_completed_queue(txring_txq(tx_ring),
878 879
				  total_packets, total_bytes);

880
#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
881 882 883 884 885 886 887 888
	if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
		     (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
		/* Make sure that anybody stopping the queue after this
		 * sees the new next_to_clean.
		 */
		smp_mb();
		if (__netif_subqueue_stopped(tx_ring->netdev,
					     tx_ring->queue_index) &&
889
		   !test_bit(__I40E_VSI_DOWN, vsi->state)) {
890 891 892 893 894 895
			netif_wake_subqueue(tx_ring->netdev,
					    tx_ring->queue_index);
			++tx_ring->tx_stats.restart_queue;
		}
	}

896 897 898 899
	return !!budget;
}

/**
900
 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
901
 * @vsi: the VSI we care about
902
 * @q_vector: the vector on which to enable writeback
903 904
 *
 **/
905 906
static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
				  struct i40e_q_vector *q_vector)
907
{
908
	u16 flags = q_vector->tx.ring[0].flags;
909
	u32 val;
910

911 912
	if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
		return;
913

914 915
	if (q_vector->arm_wb_state)
		return;
916

917 918 919
	if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
		val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
		      I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
920

921
		wr32(&vsi->back->hw,
922
		     I40E_PFINT_DYN_CTLN(q_vector->reg_idx),
923 924 925 926
		     val);
	} else {
		val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
		      I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
927

928 929 930 931 932 933 934 935 936 937 938 939 940 941
		wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
	}
	q_vector->arm_wb_state = true;
}

/**
 * i40e_force_wb - Issue SW Interrupt so HW does a wb
 * @vsi: the VSI we care about
 * @q_vector: the vector  on which to force writeback
 *
 **/
void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
{
	if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
942 943 944 945 946 947 948
		u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
			  I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
			  I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
			  I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
			  /* allow 00 to be written to the index */

		wr32(&vsi->back->hw,
949
		     I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val);
950 951 952 953 954 955 956 957 958
	} else {
		u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
			  I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
			  I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
			  I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
			/* allow 00 to be written to the index */

		wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
	}
959 960
}

961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991
static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector,
					struct i40e_ring_container *rc)
{
	return &q_vector->rx == rc;
}

static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector)
{
	unsigned int divisor;

	switch (q_vector->vsi->back->hw.phy.link_info.link_speed) {
	case I40E_LINK_SPEED_40GB:
		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024;
		break;
	case I40E_LINK_SPEED_25GB:
	case I40E_LINK_SPEED_20GB:
		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512;
		break;
	default:
	case I40E_LINK_SPEED_10GB:
		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256;
		break;
	case I40E_LINK_SPEED_1GB:
	case I40E_LINK_SPEED_100MB:
		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32;
		break;
	}

	return divisor;
}

992
/**
993 994
 * i40e_update_itr - update the dynamic ITR value based on statistics
 * @q_vector: structure containing interrupt and ring information
995 996
 * @rc: structure containing ring performance data
 *
997 998 999 1000 1001 1002
 * Stores a new ITR value based on packets and byte
 * counts during the last interrupt.  The advantage of per interrupt
 * computation is faster updates and more accurate ITR for the current
 * traffic pattern.  Constants in this function were computed
 * based on theoretical maximum wire speed and thresholds were set based
 * on testing data as well as attempting to minimize response time
1003 1004
 * while increasing bulk throughput.
 **/
1005 1006
static void i40e_update_itr(struct i40e_q_vector *q_vector,
			    struct i40e_ring_container *rc)
1007
{
1008 1009
	unsigned int avg_wire_size, packets, bytes, itr;
	unsigned long next_update = jiffies;
1010

1011 1012 1013
	/* If we don't have any rings just leave ourselves set for maximum
	 * possible latency so we take ourselves out of the equation.
	 */
1014
	if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
1015
		return;
1016

1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041
	/* For Rx we want to push the delay up and default to low latency.
	 * for Tx we want to pull the delay down and default to high latency.
	 */
	itr = i40e_container_is_rx(q_vector, rc) ?
	      I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY :
	      I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY;

	/* If we didn't update within up to 1 - 2 jiffies we can assume
	 * that either packets are coming in so slow there hasn't been
	 * any work, or that there is so much work that NAPI is dealing
	 * with interrupt moderation and we don't need to do anything.
	 */
	if (time_after(next_update, rc->next_update))
		goto clear_counts;

	/* If itr_countdown is set it means we programmed an ITR within
	 * the last 4 interrupt cycles. This has a side effect of us
	 * potentially firing an early interrupt. In order to work around
	 * this we need to throw out any data received for a few
	 * interrupts following the update.
	 */
	if (q_vector->itr_countdown) {
		itr = rc->target_itr;
		goto clear_counts;
	}
1042

1043 1044
	packets = rc->total_packets;
	bytes = rc->total_bytes;
1045

1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080
	if (i40e_container_is_rx(q_vector, rc)) {
		/* If Rx there are 1 to 4 packets and bytes are less than
		 * 9000 assume insufficient data to use bulk rate limiting
		 * approach unless Tx is already in bulk rate limiting. We
		 * are likely latency driven.
		 */
		if (packets && packets < 4 && bytes < 9000 &&
		    (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) {
			itr = I40E_ITR_ADAPTIVE_LATENCY;
			goto adjust_by_size;
		}
	} else if (packets < 4) {
		/* If we have Tx and Rx ITR maxed and Tx ITR is running in
		 * bulk mode and we are receiving 4 or fewer packets just
		 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
		 * that the Rx can relax.
		 */
		if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS &&
		    (q_vector->rx.target_itr & I40E_ITR_MASK) ==
		     I40E_ITR_ADAPTIVE_MAX_USECS)
			goto clear_counts;
	} else if (packets > 32) {
		/* If we have processed over 32 packets in a single interrupt
		 * for Tx assume we need to switch over to "bulk" mode.
		 */
		rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY;
	}

	/* We have no packets to actually measure against. This means
	 * either one of the other queues on this vector is active or
	 * we are a Tx queue doing TSO with too high of an interrupt rate.
	 *
	 * Between 4 and 56 we can assume that our current interrupt delay
	 * is only slightly too low. As such we should increase it by a small
	 * fixed amount.
1081
	 */
1082 1083 1084 1085 1086 1087 1088
	if (packets < 56) {
		itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC;
		if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
			itr &= I40E_ITR_ADAPTIVE_LATENCY;
			itr += I40E_ITR_ADAPTIVE_MAX_USECS;
		}
		goto clear_counts;
1089 1090
	}

1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134
	if (packets <= 256) {
		itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
		itr &= I40E_ITR_MASK;

		/* Between 56 and 112 is our "goldilocks" zone where we are
		 * working out "just right". Just report that our current
		 * ITR is good for us.
		 */
		if (packets <= 112)
			goto clear_counts;

		/* If packet count is 128 or greater we are likely looking
		 * at a slight overrun of the delay we want. Try halving
		 * our delay to see if that will cut the number of packets
		 * in half per interrupt.
		 */
		itr /= 2;
		itr &= I40E_ITR_MASK;
		if (itr < I40E_ITR_ADAPTIVE_MIN_USECS)
			itr = I40E_ITR_ADAPTIVE_MIN_USECS;

		goto clear_counts;
	}

	/* The paths below assume we are dealing with a bulk ITR since
	 * number of packets is greater than 256. We are just going to have
	 * to compute a value and try to bring the count under control,
	 * though for smaller packet sizes there isn't much we can do as
	 * NAPI polling will likely be kicking in sooner rather than later.
	 */
	itr = I40E_ITR_ADAPTIVE_BULK;

adjust_by_size:
	/* If packet counts are 256 or greater we can assume we have a gross
	 * overestimation of what the rate should be. Instead of trying to fine
	 * tune it just use the formula below to try and dial in an exact value
	 * give the current packet size of the frame.
	 */
	avg_wire_size = bytes / packets;

	/* The following is a crude approximation of:
	 *  wmem_default / (size + overhead) = desired_pkts_per_int
	 *  rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
	 *  (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1135
	 *
1136 1137 1138 1139 1140 1141 1142 1143 1144
	 * Assuming wmem_default is 212992 and overhead is 640 bytes per
	 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
	 * formula down to
	 *
	 *  (170 * (size + 24)) / (size + 640) = ITR
	 *
	 * We first do some math on the packet size and then finally bitshift
	 * by 8 after rounding up. We also have to account for PCIe link speed
	 * difference as ITR scales based on this.
1145
	 */
1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163
	if (avg_wire_size <= 60) {
		/* Start at 250k ints/sec */
		avg_wire_size = 4096;
	} else if (avg_wire_size <= 380) {
		/* 250K ints/sec to 60K ints/sec */
		avg_wire_size *= 40;
		avg_wire_size += 1696;
	} else if (avg_wire_size <= 1084) {
		/* 60K ints/sec to 36K ints/sec */
		avg_wire_size *= 15;
		avg_wire_size += 11452;
	} else if (avg_wire_size <= 1980) {
		/* 36K ints/sec to 30K ints/sec */
		avg_wire_size *= 5;
		avg_wire_size += 22420;
	} else {
		/* plateau at a limit of 30K ints/sec */
		avg_wire_size = 32256;
1164
	}
1165

1166 1167 1168 1169 1170
	/* If we are in low latency mode halve our delay which doubles the
	 * rate to somewhere between 100K to 16K ints/sec
	 */
	if (itr & I40E_ITR_ADAPTIVE_LATENCY)
		avg_wire_size /= 2;
1171

1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184
	/* Resultant value is 256 times larger than it needs to be. This
	 * gives us room to adjust the value as needed to either increase
	 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
	 *
	 * Use addition as we have already recorded the new latency flag
	 * for the ITR value.
	 */
	itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) *
	       I40E_ITR_ADAPTIVE_MIN_INC;

	if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
		itr &= I40E_ITR_ADAPTIVE_LATENCY;
		itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1185 1186
	}

1187 1188 1189 1190 1191 1192 1193
clear_counts:
	/* write back value */
	rc->target_itr = itr;

	/* next update should occur within next jiffy */
	rc->next_update = next_update + 1;

1194 1195 1196 1197
	rc->total_bytes = 0;
	rc->total_packets = 0;
}

1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221
/**
 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
 * @rx_ring: rx descriptor ring to store buffers on
 * @old_buff: donor buffer to have page reused
 *
 * Synchronizes page for reuse by the adapter
 **/
static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
			       struct i40e_rx_buffer *old_buff)
{
	struct i40e_rx_buffer *new_buff;
	u16 nta = rx_ring->next_to_alloc;

	new_buff = &rx_ring->rx_bi[nta];

	/* update, and store next to alloc */
	nta++;
	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;

	/* transfer page from old buffer to new buffer */
	new_buff->dma		= old_buff->dma;
	new_buff->page		= old_buff->page;
	new_buff->page_offset	= old_buff->page_offset;
	new_buff->pagecnt_bias	= old_buff->pagecnt_bias;
1222 1223 1224 1225 1226

	rx_ring->rx_stats.page_reuse_count++;

	/* clear contents of buffer_info */
	old_buff->page = NULL;
1227 1228
}

1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
/**
 * i40e_rx_is_programming_status - check for programming status descriptor
 * @qw: qword representing status_error_len in CPU ordering
 *
 * The value of in the descriptor length field indicate if this
 * is a programming status descriptor for flow director or FCoE
 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
 * it is a packet descriptor.
 **/
static inline bool i40e_rx_is_programming_status(u64 qw)
{
	/* The Rx filter programming status and SPH bit occupy the same
	 * spot in the descriptor. Since we don't support packet split we
	 * can just reuse the bit as an indication that this is a
	 * programming status descriptor.
	 */
	return qw & I40E_RXD_QW1_LENGTH_SPH_MASK;
}

1248
/**
1249
 * i40e_clean_programming_status - try clean the programming status descriptor
1250 1251
 * @rx_ring: the rx ring that has this descriptor
 * @rx_desc: the rx descriptor written back by HW
1252
 * @qw: qword representing status_error_len in CPU ordering
1253 1254 1255 1256 1257
 *
 * Flow director should handle FD_FILTER_STATUS to check its filter programming
 * status being successful or not and take actions accordingly. FCoE should
 * handle its context/filter programming/invalidation status and take actions.
 *
1258
 * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL.
1259
 **/
1260
struct i40e_rx_buffer *i40e_clean_programming_status(
1261 1262 1263
	struct i40e_ring *rx_ring,
	union i40e_rx_desc *rx_desc,
	u64 qw)
1264
{
1265
	struct i40e_rx_buffer *rx_buffer;
1266
	u32 ntc;
1267 1268
	u8 id;

1269 1270 1271 1272 1273
	if (!i40e_rx_is_programming_status(qw))
		return NULL;

	ntc = rx_ring->next_to_clean;

1274
	/* fetch, update, and store next to clean */
1275
	rx_buffer = &rx_ring->rx_bi[ntc++];
1276 1277 1278 1279 1280
	ntc = (ntc < rx_ring->count) ? ntc : 0;
	rx_ring->next_to_clean = ntc;

	prefetch(I40E_RX_DESC(rx_ring, ntc));

1281 1282 1283 1284
	id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
		  I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;

	if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
1285
		i40e_fd_handle_status(rx_ring, rx_desc, id);
1286 1287

	return rx_buffer;
1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303
}

/**
 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
 * @tx_ring: the tx ring to set up
 *
 * Return 0 on success, negative on error
 **/
int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
{
	struct device *dev = tx_ring->dev;
	int bi_size;

	if (!dev)
		return -ENOMEM;

J
Jesse Brandeburg 已提交
1304 1305
	/* warn if we are about to overwrite the pointer */
	WARN_ON(tx_ring->tx_bi);
1306 1307 1308 1309 1310
	bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
	tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
	if (!tx_ring->tx_bi)
		goto err;

1311 1312
	u64_stats_init(&tx_ring->syncp);

1313 1314
	/* round up to nearest 4K */
	tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1315 1316 1317 1318
	/* add u32 for head writeback, align after this takes care of
	 * guaranteeing this is at least one cache line in size
	 */
	tx_ring->size += sizeof(u32);
1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329
	tx_ring->size = ALIGN(tx_ring->size, 4096);
	tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
					   &tx_ring->dma, GFP_KERNEL);
	if (!tx_ring->desc) {
		dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
			 tx_ring->size);
		goto err;
	}

	tx_ring->next_to_use = 0;
	tx_ring->next_to_clean = 0;
1330
	tx_ring->tx_stats.prev_pkt_ctr = -1;
1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351
	return 0;

err:
	kfree(tx_ring->tx_bi);
	tx_ring->tx_bi = NULL;
	return -ENOMEM;
}

/**
 * i40e_clean_rx_ring - Free Rx buffers
 * @rx_ring: ring to be cleaned
 **/
void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
{
	unsigned long bi_size;
	u16 i;

	/* ring already cleared, nothing to do */
	if (!rx_ring->rx_bi)
		return;

1352 1353 1354 1355 1356
	if (rx_ring->skb) {
		dev_kfree_skb(rx_ring->skb);
		rx_ring->skb = NULL;
	}

1357 1358
	if (rx_ring->xsk_umem) {
		i40e_xsk_clean_rx_ring(rx_ring);
1359
		goto skip_free;
1360
	}
1361

1362 1363
	/* Free all the Rx ring sk_buffs */
	for (i = 0; i < rx_ring->count; i++) {
1364 1365 1366 1367 1368
		struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i];

		if (!rx_bi->page)
			continue;

1369 1370 1371 1372 1373 1374
		/* Invalidate cache lines that may have been written to by
		 * device so that we avoid corrupting memory.
		 */
		dma_sync_single_range_for_cpu(rx_ring->dev,
					      rx_bi->dma,
					      rx_bi->page_offset,
1375
					      rx_ring->rx_buf_len,
1376 1377 1378 1379
					      DMA_FROM_DEVICE);

		/* free resources associated with mapping */
		dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
1380
				     i40e_rx_pg_size(rx_ring),
1381 1382
				     DMA_FROM_DEVICE,
				     I40E_RX_DMA_ATTR);
1383

1384
		__page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
1385 1386 1387

		rx_bi->page = NULL;
		rx_bi->page_offset = 0;
1388 1389
	}

1390
skip_free:
1391 1392 1393 1394 1395 1396
	bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
	memset(rx_ring->rx_bi, 0, bi_size);

	/* Zero out the descriptor ring */
	memset(rx_ring->desc, 0, rx_ring->size);

1397
	rx_ring->next_to_alloc = 0;
1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410
	rx_ring->next_to_clean = 0;
	rx_ring->next_to_use = 0;
}

/**
 * i40e_free_rx_resources - Free Rx resources
 * @rx_ring: ring to clean the resources from
 *
 * Free all receive software resources
 **/
void i40e_free_rx_resources(struct i40e_ring *rx_ring)
{
	i40e_clean_rx_ring(rx_ring);
1411 1412
	if (rx_ring->vsi->type == I40E_VSI_MAIN)
		xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
1413
	rx_ring->xdp_prog = NULL;
1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432
	kfree(rx_ring->rx_bi);
	rx_ring->rx_bi = NULL;

	if (rx_ring->desc) {
		dma_free_coherent(rx_ring->dev, rx_ring->size,
				  rx_ring->desc, rx_ring->dma);
		rx_ring->desc = NULL;
	}
}

/**
 * i40e_setup_rx_descriptors - Allocate Rx descriptors
 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 *
 * Returns 0 on success, negative on failure
 **/
int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
{
	struct device *dev = rx_ring->dev;
1433
	int err = -ENOMEM;
1434 1435
	int bi_size;

J
Jesse Brandeburg 已提交
1436 1437
	/* warn if we are about to overwrite the pointer */
	WARN_ON(rx_ring->rx_bi);
1438 1439 1440 1441 1442
	bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
	rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
	if (!rx_ring->rx_bi)
		goto err;

1443
	u64_stats_init(&rx_ring->syncp);
1444

1445
	/* Round up to nearest 4K */
1446
	rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1447 1448 1449 1450 1451 1452 1453 1454 1455 1456
	rx_ring->size = ALIGN(rx_ring->size, 4096);
	rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
					   &rx_ring->dma, GFP_KERNEL);

	if (!rx_ring->desc) {
		dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
			 rx_ring->size);
		goto err;
	}

1457
	rx_ring->next_to_alloc = 0;
1458 1459 1460
	rx_ring->next_to_clean = 0;
	rx_ring->next_to_use = 0;

1461 1462 1463 1464 1465 1466 1467 1468
	/* XDP RX-queue info only needed for RX rings exposed to XDP */
	if (rx_ring->vsi->type == I40E_VSI_MAIN) {
		err = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
				       rx_ring->queue_index);
		if (err < 0)
			goto err;
	}

1469 1470
	rx_ring->xdp_prog = rx_ring->vsi->xdp_prog;

1471 1472 1473 1474
	return 0;
err:
	kfree(rx_ring->rx_bi);
	rx_ring->rx_bi = NULL;
1475
	return err;
1476 1477 1478 1479 1480 1481 1482
}

/**
 * i40e_release_rx_desc - Store the new tail and head values
 * @rx_ring: ring to bump
 * @val: new head index
 **/
1483
void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1484 1485
{
	rx_ring->next_to_use = val;
1486 1487 1488 1489

	/* update next to alloc since we have filled the ring */
	rx_ring->next_to_alloc = val;

1490 1491 1492 1493 1494 1495 1496 1497 1498
	/* Force memory writes to complete before letting h/w
	 * know there are new descriptors to fetch.  (Only
	 * applicable for weak-ordered memory model archs,
	 * such as IA-64).
	 */
	wmb();
	writel(val, rx_ring->tail);
}

1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509
/**
 * i40e_rx_offset - Return expected offset into page to access data
 * @rx_ring: Ring we are requesting offset of
 *
 * Returns the offset value for ring into the data buffer.
 */
static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring)
{
	return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0;
}

1510
/**
1511 1512 1513
 * i40e_alloc_mapped_page - recycle or make a new page
 * @rx_ring: ring to use
 * @bi: rx_buffer struct to modify
1514
 *
1515 1516
 * Returns true if the page was successfully allocated or
 * reused.
1517
 **/
1518 1519
static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
				   struct i40e_rx_buffer *bi)
1520
{
1521 1522
	struct page *page = bi->page;
	dma_addr_t dma;
1523

1524 1525 1526 1527 1528
	/* since we are recycling buffers we should seldom need to alloc */
	if (likely(page)) {
		rx_ring->rx_stats.page_reuse_count++;
		return true;
	}
1529

1530
	/* alloc new page for storage */
1531
	page = dev_alloc_pages(i40e_rx_pg_order(rx_ring));
1532 1533 1534 1535
	if (unlikely(!page)) {
		rx_ring->rx_stats.alloc_page_failed++;
		return false;
	}
1536

1537
	/* map page for use */
1538
	dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1539
				 i40e_rx_pg_size(rx_ring),
1540 1541
				 DMA_FROM_DEVICE,
				 I40E_RX_DMA_ATTR);
1542

1543 1544
	/* if mapping failed free memory back to system since
	 * there isn't much point in holding memory we can't use
1545
	 */
1546
	if (dma_mapping_error(rx_ring->dev, dma)) {
1547
		__free_pages(page, i40e_rx_pg_order(rx_ring));
1548 1549
		rx_ring->rx_stats.alloc_page_failed++;
		return false;
1550 1551
	}

1552 1553
	bi->dma = dma;
	bi->page = page;
1554
	bi->page_offset = i40e_rx_offset(rx_ring);
1555 1556
	page_ref_add(page, USHRT_MAX - 1);
	bi->pagecnt_bias = USHRT_MAX;
1557

1558 1559
	return true;
}
1560

1561
/**
1562
 * i40e_alloc_rx_buffers - Replace used receive buffers
1563 1564
 * @rx_ring: ring to place buffers on
 * @cleaned_count: number of buffers to replace
1565
 *
1566
 * Returns false if all allocations were successful, true if any fail
1567
 **/
1568
bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1569
{
1570
	u16 ntu = rx_ring->next_to_use;
1571 1572 1573 1574 1575
	union i40e_rx_desc *rx_desc;
	struct i40e_rx_buffer *bi;

	/* do nothing if no valid netdev defined */
	if (!rx_ring->netdev || !cleaned_count)
1576
		return false;
1577

1578 1579
	rx_desc = I40E_RX_DESC(rx_ring, ntu);
	bi = &rx_ring->rx_bi[ntu];
1580

1581 1582 1583
	do {
		if (!i40e_alloc_mapped_page(rx_ring, bi))
			goto no_buffers;
1584

1585 1586 1587
		/* sync the buffer for use by the device */
		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
						 bi->page_offset,
1588
						 rx_ring->rx_buf_len,
1589 1590
						 DMA_FROM_DEVICE);

1591 1592 1593 1594
		/* Refresh the desc even if buffer_addrs didn't change
		 * because each write-back erases this info.
		 */
		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1595

1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612
		rx_desc++;
		bi++;
		ntu++;
		if (unlikely(ntu == rx_ring->count)) {
			rx_desc = I40E_RX_DESC(rx_ring, 0);
			bi = rx_ring->rx_bi;
			ntu = 0;
		}

		/* clear the status bits for the next_to_use descriptor */
		rx_desc->wb.qword1.status_error_len = 0;

		cleaned_count--;
	} while (cleaned_count);

	if (rx_ring->next_to_use != ntu)
		i40e_release_rx_desc(rx_ring, ntu);
1613 1614 1615

	return false;

1616
no_buffers:
1617 1618
	if (rx_ring->next_to_use != ntu)
		i40e_release_rx_desc(rx_ring, ntu);
1619 1620 1621 1622 1623

	/* make sure to come back via polling to try again after
	 * allocation failure
	 */
	return true;
1624 1625 1626 1627 1628 1629
}

/**
 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 * @vsi: the VSI we care about
 * @skb: skb currently being received and modified
1630
 * @rx_desc: the receive descriptor
1631 1632 1633
 **/
static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
				    struct sk_buff *skb,
1634
				    union i40e_rx_desc *rx_desc)
1635
{
1636 1637
	struct i40e_rx_ptype_decoded decoded;
	u32 rx_error, rx_status;
1638
	bool ipv4, ipv6;
1639 1640 1641 1642 1643 1644 1645 1646 1647 1648
	u8 ptype;
	u64 qword;

	qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
	ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
	rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
		   I40E_RXD_QW1_ERROR_SHIFT;
	rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
		    I40E_RXD_QW1_STATUS_SHIFT;
	decoded = decode_rx_desc_ptype(ptype);
1649

1650 1651
	skb->ip_summed = CHECKSUM_NONE;

1652 1653
	skb_checksum_none_assert(skb);

1654
	/* Rx csum enabled and ip headers found? */
1655 1656 1657 1658
	if (!(vsi->netdev->features & NETIF_F_RXCSUM))
		return;

	/* did the hardware decode the packet and checksum? */
1659
	if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1660 1661 1662 1663
		return;

	/* both known and outer_ip must be set for the below code to work */
	if (!(decoded.known && decoded.outer_ip))
1664 1665
		return;

1666 1667 1668 1669
	ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
	       (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
	ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
	       (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
1670 1671

	if (ipv4 &&
1672 1673
	    (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
			 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1674 1675
		goto checksum_fail;

J
Jesse Brandeburg 已提交
1676
	/* likely incorrect csum if alternate IP extension headers found */
1677
	if (ipv6 &&
1678
	    rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1679
		/* don't increment checksum err here, non-fatal err */
1680 1681
		return;

1682
	/* there was some L4 error, count error and punt packet to the stack */
1683
	if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1684 1685 1686 1687 1688 1689
		goto checksum_fail;

	/* handle packets that were not able to be checksummed due
	 * to arrival speed, in this case the stack can compute
	 * the csum.
	 */
1690
	if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1691 1692
		return;

1693 1694 1695
	/* If there is an outer header present that might contain a checksum
	 * we need to bump the checksum level by 1 to reflect the fact that
	 * we are indicating we validated the inner checksum.
1696
	 */
1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709
	if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
		skb->csum_level = 1;

	/* Only report checksum unnecessary for TCP, UDP, or SCTP */
	switch (decoded.inner_prot) {
	case I40E_RX_PTYPE_INNER_PROT_TCP:
	case I40E_RX_PTYPE_INNER_PROT_UDP:
	case I40E_RX_PTYPE_INNER_PROT_SCTP:
		skb->ip_summed = CHECKSUM_UNNECESSARY;
		/* fall though */
	default:
		break;
	}
1710 1711 1712 1713 1714

	return;

checksum_fail:
	vsi->back->hw_csum_rx_error++;
1715 1716 1717
}

/**
1718
 * i40e_ptype_to_htype - get a hash type
1719 1720 1721 1722
 * @ptype: the ptype value from the descriptor
 *
 * Returns a hash type to be used by skb_set_hash
 **/
1723
static inline int i40e_ptype_to_htype(u8 ptype)
1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739
{
	struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);

	if (!decoded.known)
		return PKT_HASH_TYPE_NONE;

	if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
	    decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
		return PKT_HASH_TYPE_L4;
	else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
		 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
		return PKT_HASH_TYPE_L3;
	else
		return PKT_HASH_TYPE_L2;
}

1740 1741 1742 1743
/**
 * i40e_rx_hash - set the hash value in the skb
 * @ring: descriptor ring
 * @rx_desc: specific descriptor
1744 1745
 * @skb: skb currently being received and modified
 * @rx_ptype: Rx packet type
1746 1747 1748 1749 1750 1751 1752
 **/
static inline void i40e_rx_hash(struct i40e_ring *ring,
				union i40e_rx_desc *rx_desc,
				struct sk_buff *skb,
				u8 rx_ptype)
{
	u32 hash;
1753
	const __le64 rss_mask =
1754 1755 1756
		cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
			    I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);

1757
	if (!(ring->netdev->features & NETIF_F_RXHASH))
1758 1759 1760 1761 1762 1763 1764 1765
		return;

	if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
		hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
		skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
	}
}

1766
/**
1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777
 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor
 * @rx_ring: rx descriptor ring packet is being transacted on
 * @rx_desc: pointer to the EOP Rx descriptor
 * @skb: pointer to current skb being populated
 * @rx_ptype: the packet type decoded by hardware
 *
 * This function checks the ring, descriptor, and packet information in
 * order to populate the hash, checksum, VLAN, protocol, and
 * other fields within the skb.
 **/
void i40e_process_skb_fields(struct i40e_ring *rx_ring,
1778
			     union i40e_rx_desc *rx_desc, struct sk_buff *skb)
1779 1780 1781 1782
{
	u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
	u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
			I40E_RXD_QW1_STATUS_SHIFT;
1783 1784
	u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK;
	u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1785
		   I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT;
1786 1787
	u8 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
		      I40E_RXD_QW1_PTYPE_SHIFT;
1788

1789
	if (unlikely(tsynvalid))
1790
		i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn);
1791 1792 1793 1794 1795 1796

	i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);

	i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);

	skb_record_rx_queue(skb, rx_ring->queue_index);
1797

1798 1799 1800 1801 1802 1803 1804
	if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
		u16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1;

		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
				       le16_to_cpu(vlan_tag));
	}

1805 1806
	/* modifies the skb - consumes the enet header */
	skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1807 1808 1809 1810 1811 1812
}

/**
 * i40e_cleanup_headers - Correct empty headers
 * @rx_ring: rx descriptor ring packet is being transacted on
 * @skb: pointer to current skb being fixed
1813
 * @rx_desc: pointer to the EOP Rx descriptor
1814 1815 1816 1817 1818 1819 1820 1821 1822
 *
 * Also address the case where we are pulling data in on pages only
 * and as such no data is present in the skb header.
 *
 * In addition if skb is not at least 60 bytes we need to pad it so that
 * it is large enough to qualify as a valid Ethernet frame.
 *
 * Returns true if an error was encountered and skb was freed.
 **/
1823 1824 1825
static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb,
				 union i40e_rx_desc *rx_desc)

1826
{
1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841
	/* XDP packets use error pointer so abort at this point */
	if (IS_ERR(skb))
		return true;

	/* ERR_MASK will only have valid bits if EOP set, and
	 * what we are doing here is actually checking
	 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
	 * the error field
	 */
	if (unlikely(i40e_test_staterr(rx_desc,
				       BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
		dev_kfree_skb_any(skb);
		return true;
	}

1842 1843 1844 1845 1846 1847 1848 1849
	/* if eth_skb_pad returns an error the skb was freed */
	if (eth_skb_pad(skb))
		return true;

	return false;
}

/**
1850
 * i40e_page_is_reusable - check if any reuse is possible
1851
 * @page: page struct to check
1852 1853 1854
 *
 * A page is not reusable if it was allocated under low memory
 * conditions, or it's not in the same NUMA node as this CPU.
1855
 */
1856
static inline bool i40e_page_is_reusable(struct page *page)
1857
{
1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888
	return (page_to_nid(page) == numa_mem_id()) &&
		!page_is_pfmemalloc(page);
}

/**
 * i40e_can_reuse_rx_page - Determine if this page can be reused by
 * the adapter for another receive
 *
 * @rx_buffer: buffer containing the page
 *
 * If page is reusable, rx_buffer->page_offset is adjusted to point to
 * an unused region in the page.
 *
 * For small pages, @truesize will be a constant value, half the size
 * of the memory at page.  We'll attempt to alternate between high and
 * low halves of the page, with one half ready for use by the hardware
 * and the other half being consumed by the stack.  We use the page
 * ref count to determine whether the stack has finished consuming the
 * portion of this page that was passed up with a previous packet.  If
 * the page ref count is >1, we'll assume the "other" half page is
 * still busy, and this page cannot be reused.
 *
 * For larger pages, @truesize will be the actual space used by the
 * received packet (adjusted upward to an even multiple of the cache
 * line size).  This will advance through the page by the amount
 * actually consumed by the received packets while there is still
 * space for a buffer.  Each region of larger pages will be used at
 * most once, after which the page will not be reused.
 *
 * In either case, if the page is reusable its refcount is increased.
 **/
1889
static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer)
1890
{
1891 1892
	unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
	struct page *page = rx_buffer->page;
1893 1894 1895 1896 1897 1898 1899

	/* Is any reuse possible? */
	if (unlikely(!i40e_page_is_reusable(page)))
		return false;

#if (PAGE_SIZE < 8192)
	/* if we are only owner of page we can reuse it */
1900
	if (unlikely((page_count(page) - pagecnt_bias) > 1))
1901 1902
		return false;
#else
1903 1904 1905
#define I40E_LAST_OFFSET \
	(SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048)
	if (rx_buffer->page_offset > I40E_LAST_OFFSET)
1906 1907 1908
		return false;
#endif

1909 1910 1911 1912
	/* If we have drained the page fragment pool we need to update
	 * the pagecnt_bias and page count so that we fully restock the
	 * number of references the driver holds.
	 */
1913 1914
	if (unlikely(pagecnt_bias == 1)) {
		page_ref_add(page, USHRT_MAX - 1);
1915 1916
		rx_buffer->pagecnt_bias = USHRT_MAX;
	}
1917

1918
	return true;
1919 1920 1921 1922 1923 1924 1925
}

/**
 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
 * @rx_ring: rx descriptor ring to transact packets on
 * @rx_buffer: buffer containing page to add
 * @skb: sk_buff to place the data into
1926
 * @size: packet length from rx_desc
1927 1928
 *
 * This function will add the data contained in rx_buffer->page to the skb.
1929
 * It will just attach the page as a frag to the skb.
1930
 *
1931
 * The function will then update the page offset.
1932
 **/
1933
static void i40e_add_rx_frag(struct i40e_ring *rx_ring,
1934
			     struct i40e_rx_buffer *rx_buffer,
1935 1936
			     struct sk_buff *skb,
			     unsigned int size)
1937 1938
{
#if (PAGE_SIZE < 8192)
1939
	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1940
#else
1941
	unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring));
1942 1943
#endif

1944 1945
	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
			rx_buffer->page_offset, size, truesize);
1946

1947 1948 1949 1950 1951 1952
	/* page is being used so we must update the page offset */
#if (PAGE_SIZE < 8192)
	rx_buffer->page_offset ^= truesize;
#else
	rx_buffer->page_offset += truesize;
#endif
1953 1954
}

1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977
/**
 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use
 * @rx_ring: rx descriptor ring to transact packets on
 * @size: size of buffer to add to skb
 *
 * This function will pull an Rx buffer from the ring and synchronize it
 * for use by the CPU.
 */
static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring,
						 const unsigned int size)
{
	struct i40e_rx_buffer *rx_buffer;

	rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean];
	prefetchw(rx_buffer->page);

	/* we are reusing so sync this buffer for CPU use */
	dma_sync_single_range_for_cpu(rx_ring->dev,
				      rx_buffer->dma,
				      rx_buffer->page_offset,
				      size,
				      DMA_FROM_DEVICE);

1978 1979 1980
	/* We have pulled a buffer for use, so decrement pagecnt_bias */
	rx_buffer->pagecnt_bias--;

1981 1982 1983
	return rx_buffer;
}

1984
/**
1985
 * i40e_construct_skb - Allocate skb and populate it
1986
 * @rx_ring: rx descriptor ring to transact packets on
1987
 * @rx_buffer: rx buffer to pull data from
1988
 * @xdp: xdp_buff pointing to the data
1989
 *
1990 1991 1992
 * This function allocates an skb.  It then populates it with the page
 * data from the current receive descriptor, taking care to set up the
 * skb correctly.
1993
 */
1994 1995
static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring,
					  struct i40e_rx_buffer *rx_buffer,
1996
					  struct xdp_buff *xdp)
1997
{
1998
	unsigned int size = xdp->data_end - xdp->data;
1999
#if (PAGE_SIZE < 8192)
2000
	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2001 2002 2003 2004 2005
#else
	unsigned int truesize = SKB_DATA_ALIGN(size);
#endif
	unsigned int headlen;
	struct sk_buff *skb;
2006

2007
	/* prefetch first cache line of first page */
2008
	prefetch(xdp->data);
2009
#if L1_CACHE_BYTES < 128
2010
	prefetch(xdp->data + L1_CACHE_BYTES);
2011
#endif
2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026
	/* Note, we get here by enabling legacy-rx via:
	 *
	 *    ethtool --set-priv-flags <dev> legacy-rx on
	 *
	 * In this mode, we currently get 0 extra XDP headroom as
	 * opposed to having legacy-rx off, where we process XDP
	 * packets going to stack via i40e_build_skb(). The latter
	 * provides us currently with 192 bytes of headroom.
	 *
	 * For i40e_construct_skb() mode it means that the
	 * xdp->data_meta will always point to xdp->data, since
	 * the helper cannot expand the head. Should this ever
	 * change in future for legacy-rx mode on, then lets also
	 * add xdp->data_meta handling here.
	 */
2027

2028 2029 2030 2031 2032 2033 2034 2035 2036 2037
	/* allocate a skb to store the frags */
	skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
			       I40E_RX_HDR_SIZE,
			       GFP_ATOMIC | __GFP_NOWARN);
	if (unlikely(!skb))
		return NULL;

	/* Determine available headroom for copy */
	headlen = size;
	if (headlen > I40E_RX_HDR_SIZE)
2038
		headlen = eth_get_headlen(xdp->data, I40E_RX_HDR_SIZE);
2039

2040
	/* align pull length to size of long to optimize memcpy performance */
2041 2042
	memcpy(__skb_put(skb, headlen), xdp->data,
	       ALIGN(headlen, sizeof(long)));
2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060

	/* update all of the pointers */
	size -= headlen;
	if (size) {
		skb_add_rx_frag(skb, 0, rx_buffer->page,
				rx_buffer->page_offset + headlen,
				size, truesize);

		/* buffer is used by skb, update page_offset */
#if (PAGE_SIZE < 8192)
		rx_buffer->page_offset ^= truesize;
#else
		rx_buffer->page_offset += truesize;
#endif
	} else {
		/* buffer is unused, reset bias back to rx_buffer */
		rx_buffer->pagecnt_bias++;
	}
2061 2062 2063 2064

	return skb;
}

2065 2066 2067 2068
/**
 * i40e_build_skb - Build skb around an existing buffer
 * @rx_ring: Rx descriptor ring to transact packets on
 * @rx_buffer: Rx buffer to pull data from
2069
 * @xdp: xdp_buff pointing to the data
2070 2071 2072 2073 2074 2075
 *
 * This function builds an skb around an existing Rx buffer, taking care
 * to set up the skb correctly and avoid any memcpy overhead.
 */
static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring,
				      struct i40e_rx_buffer *rx_buffer,
2076
				      struct xdp_buff *xdp)
2077
{
2078
	unsigned int metasize = xdp->data - xdp->data_meta;
2079 2080 2081
#if (PAGE_SIZE < 8192)
	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
#else
2082
	unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2083 2084
				SKB_DATA_ALIGN(xdp->data_end -
					       xdp->data_hard_start);
2085 2086 2087
#endif
	struct sk_buff *skb;

2088 2089 2090 2091 2092 2093
	/* Prefetch first cache line of first page. If xdp->data_meta
	 * is unused, this points exactly as xdp->data, otherwise we
	 * likely have a consumer accessing first few bytes of meta
	 * data, and then actual data.
	 */
	prefetch(xdp->data_meta);
2094
#if L1_CACHE_BYTES < 128
2095
	prefetch(xdp->data_meta + L1_CACHE_BYTES);
2096 2097
#endif
	/* build an skb around the page buffer */
2098
	skb = build_skb(xdp->data_hard_start, truesize);
2099 2100 2101 2102
	if (unlikely(!skb))
		return NULL;

	/* update pointers within the skb to store the data */
2103
	skb_reserve(skb, xdp->data - xdp->data_hard_start);
2104 2105 2106
	__skb_put(skb, xdp->data_end - xdp->data);
	if (metasize)
		skb_metadata_set(skb, metasize);
2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117

	/* buffer is used by skb, update page_offset */
#if (PAGE_SIZE < 8192)
	rx_buffer->page_offset ^= truesize;
#else
	rx_buffer->page_offset += truesize;
#endif

	return skb;
}

2118 2119 2120 2121 2122 2123
/**
 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free
 * @rx_ring: rx descriptor ring to transact packets on
 * @rx_buffer: rx buffer to pull data from
 *
 * This function will clean up the contents of the rx_buffer.  It will
2124
 * either recycle the buffer or unmap it and free the associated resources.
2125 2126 2127 2128 2129
 */
static void i40e_put_rx_buffer(struct i40e_ring *rx_ring,
			       struct i40e_rx_buffer *rx_buffer)
{
	if (i40e_can_reuse_rx_page(rx_buffer)) {
2130 2131 2132 2133
		/* hand second half of page back to the ring */
		i40e_reuse_rx_page(rx_ring, rx_buffer);
	} else {
		/* we are not reusing the buffer so unmap it */
2134 2135
		dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
				     i40e_rx_pg_size(rx_ring),
2136
				     DMA_FROM_DEVICE, I40E_RX_DMA_ATTR);
2137 2138
		__page_frag_cache_drain(rx_buffer->page,
					rx_buffer->pagecnt_bias);
2139 2140
		/* clear contents of buffer_info */
		rx_buffer->page = NULL;
2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153
	}
}

/**
 * i40e_is_non_eop - process handling of non-EOP buffers
 * @rx_ring: Rx ring being processed
 * @rx_desc: Rx descriptor for current buffer
 * @skb: Current socket buffer containing buffer in progress
 *
 * This function updates next to clean.  If the buffer is an EOP buffer
 * this function exits returning false, otherwise it will place the
 * sk_buff in the next buffer to be chained and return true indicating
 * that this is in fact a non-EOP buffer.
2154
 **/
2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176
static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
			    union i40e_rx_desc *rx_desc,
			    struct sk_buff *skb)
{
	u32 ntc = rx_ring->next_to_clean + 1;

	/* fetch, update, and store next to clean */
	ntc = (ntc < rx_ring->count) ? ntc : 0;
	rx_ring->next_to_clean = ntc;

	prefetch(I40E_RX_DESC(rx_ring, ntc));

	/* if we are the last buffer then there is nothing else to do */
#define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
	if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
		return false;

	rx_ring->rx_stats.non_eop_descs++;

	return true;
}

2177
static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
2178
			      struct i40e_ring *xdp_ring);
2179

2180
int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring)
2181 2182 2183 2184 2185 2186 2187 2188 2189
{
	struct xdp_frame *xdpf = convert_to_xdp_frame(xdp);

	if (unlikely(!xdpf))
		return I40E_XDP_CONSUMED;

	return i40e_xmit_xdp_ring(xdpf, xdp_ring);
}

2190 2191 2192 2193 2194 2195 2196 2197
/**
 * i40e_run_xdp - run an XDP program
 * @rx_ring: Rx ring being processed
 * @xdp: XDP buffer containing the frame
 **/
static struct sk_buff *i40e_run_xdp(struct i40e_ring *rx_ring,
				    struct xdp_buff *xdp)
{
2198
	int err, result = I40E_XDP_PASS;
2199
	struct i40e_ring *xdp_ring;
2200 2201 2202 2203 2204 2205 2206 2207 2208
	struct bpf_prog *xdp_prog;
	u32 act;

	rcu_read_lock();
	xdp_prog = READ_ONCE(rx_ring->xdp_prog);

	if (!xdp_prog)
		goto xdp_out;

2209 2210
	prefetchw(xdp->data_hard_start); /* xdp_frame write */

2211 2212 2213 2214
	act = bpf_prog_run_xdp(xdp_prog, xdp);
	switch (act) {
	case XDP_PASS:
		break;
2215 2216
	case XDP_TX:
		xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2217
		result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring);
2218
		break;
2219 2220
	case XDP_REDIRECT:
		err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog);
2221
		result = !err ? I40E_XDP_REDIR : I40E_XDP_CONSUMED;
2222
		break;
2223 2224
	default:
		bpf_warn_invalid_xdp_action(act);
2225
		/* fall through */
2226 2227
	case XDP_ABORTED:
		trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2228
		/* fall through -- handle aborts by dropping packet */
2229 2230 2231 2232 2233 2234 2235 2236 2237
	case XDP_DROP:
		result = I40E_XDP_CONSUMED;
		break;
	}
xdp_out:
	rcu_read_unlock();
	return ERR_PTR(-result);
}

2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258
/**
 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region
 * @rx_ring: Rx ring
 * @rx_buffer: Rx buffer to adjust
 * @size: Size of adjustment
 **/
static void i40e_rx_buffer_flip(struct i40e_ring *rx_ring,
				struct i40e_rx_buffer *rx_buffer,
				unsigned int size)
{
#if (PAGE_SIZE < 8192)
	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;

	rx_buffer->page_offset ^= truesize;
#else
	unsigned int truesize = SKB_DATA_ALIGN(i40e_rx_offset(rx_ring) + size);

	rx_buffer->page_offset += truesize;
#endif
}

2259 2260 2261 2262 2263 2264
/**
 * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register
 * @xdp_ring: XDP Tx ring
 *
 * This function updates the XDP Tx ring tail register.
 **/
2265
void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring)
2266 2267 2268 2269 2270 2271 2272 2273
{
	/* Force memory writes to complete before letting h/w
	 * know there are new descriptors to fetch.
	 */
	wmb();
	writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
}

2274 2275 2276 2277 2278 2279 2280 2281
/**
 * i40e_update_rx_stats - Update Rx ring statistics
 * @rx_ring: rx descriptor ring
 * @total_rx_bytes: number of bytes received
 * @total_rx_packets: number of packets received
 *
 * This function updates the Rx ring statistics.
 **/
2282 2283 2284
void i40e_update_rx_stats(struct i40e_ring *rx_ring,
			  unsigned int total_rx_bytes,
			  unsigned int total_rx_packets)
2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302
{
	u64_stats_update_begin(&rx_ring->syncp);
	rx_ring->stats.packets += total_rx_packets;
	rx_ring->stats.bytes += total_rx_bytes;
	u64_stats_update_end(&rx_ring->syncp);
	rx_ring->q_vector->rx.total_packets += total_rx_packets;
	rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
}

/**
 * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map
 * @rx_ring: Rx ring
 * @xdp_res: Result of the receive batch
 *
 * This function bumps XDP Tx tail and/or flush redirect map, and
 * should be called when a batch of packets has been processed in the
 * napi loop.
 **/
2303
void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res)
2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315
{
	if (xdp_res & I40E_XDP_REDIR)
		xdp_do_flush_map();

	if (xdp_res & I40E_XDP_TX) {
		struct i40e_ring *xdp_ring =
			rx_ring->vsi->xdp_rings[rx_ring->queue_index];

		i40e_xdp_ring_update_tail(xdp_ring);
	}
}

2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328
/**
 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
 * @rx_ring: rx descriptor ring to transact packets on
 * @budget: Total limit on number of packets to process
 *
 * This function provides a "bounce buffer" approach to Rx interrupt
 * processing.  The advantage to this is that on systems that have
 * expensive overhead for IOMMU access this provides a means of avoiding
 * it by maintaining the mapping of the page to the system.
 *
 * Returns amount of work completed
 **/
static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
2329 2330
{
	unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2331
	struct sk_buff *skb = rx_ring->skb;
2332
	u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
2333 2334
	unsigned int xdp_xmit = 0;
	bool failure = false;
2335 2336 2337
	struct xdp_buff xdp;

	xdp.rxq = &rx_ring->xdp_rxq;
2338

2339
	while (likely(total_rx_packets < (unsigned int)budget)) {
2340
		struct i40e_rx_buffer *rx_buffer;
2341
		union i40e_rx_desc *rx_desc;
2342
		unsigned int size;
2343 2344
		u64 qword;

2345 2346
		/* return some buffers to hardware, one at a time is too slow */
		if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
2347
			failure = failure ||
2348
				  i40e_alloc_rx_buffers(rx_ring, cleaned_count);
2349 2350 2351
			cleaned_count = 0;
		}

2352 2353 2354 2355 2356
		rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);

		/* status_error_len will always be zero for unused descriptors
		 * because it's cleared in cleanup, and overlaps with hdr_addr
		 * which is always zero because packet split isn't used, if the
2357
		 * hardware wrote DD then the length will be non-zero
2358
		 */
2359
		qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
2360

2361
		/* This memory barrier is needed to keep us from reading
2362 2363
		 * any other fields out of the rx_desc until we have
		 * verified the descriptor has been written back.
2364
		 */
2365
		dma_rmb();
2366

2367 2368 2369 2370
		rx_buffer = i40e_clean_programming_status(rx_ring, rx_desc,
							  qword);
		if (unlikely(rx_buffer)) {
			i40e_reuse_rx_page(rx_ring, rx_buffer);
2371
			cleaned_count++;
2372 2373
			continue;
		}
2374

2375 2376 2377 2378 2379
		size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
		       I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
		if (!size)
			break;

S
Scott Peterson 已提交
2380
		i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb);
2381 2382
		rx_buffer = i40e_get_rx_buffer(rx_ring, size);

2383
		/* retrieve a buffer from the ring */
2384 2385 2386
		if (!skb) {
			xdp.data = page_address(rx_buffer->page) +
				   rx_buffer->page_offset;
2387
			xdp.data_meta = xdp.data;
2388 2389 2390 2391 2392 2393 2394 2395
			xdp.data_hard_start = xdp.data -
					      i40e_rx_offset(rx_ring);
			xdp.data_end = xdp.data + size;

			skb = i40e_run_xdp(rx_ring, &xdp);
		}

		if (IS_ERR(skb)) {
2396 2397 2398 2399
			unsigned int xdp_res = -PTR_ERR(skb);

			if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) {
				xdp_xmit |= xdp_res;
2400 2401 2402 2403
				i40e_rx_buffer_flip(rx_ring, rx_buffer, size);
			} else {
				rx_buffer->pagecnt_bias++;
			}
2404 2405 2406
			total_rx_bytes += size;
			total_rx_packets++;
		} else if (skb) {
2407
			i40e_add_rx_frag(rx_ring, rx_buffer, skb, size);
2408 2409 2410 2411 2412
		} else if (ring_uses_build_skb(rx_ring)) {
			skb = i40e_build_skb(rx_ring, rx_buffer, &xdp);
		} else {
			skb = i40e_construct_skb(rx_ring, rx_buffer, &xdp);
		}
2413 2414 2415 2416 2417

		/* exit if we failed to retrieve a buffer */
		if (!skb) {
			rx_ring->rx_stats.alloc_buff_failed++;
			rx_buffer->pagecnt_bias++;
2418
			break;
2419
		}
2420

2421
		i40e_put_rx_buffer(rx_ring, rx_buffer);
2422 2423
		cleaned_count++;

2424
		if (i40e_is_non_eop(rx_ring, rx_desc, skb))
2425 2426
			continue;

2427
		if (i40e_cleanup_headers(rx_ring, skb, rx_desc)) {
2428
			skb = NULL;
2429
			continue;
2430
		}
2431 2432 2433 2434

		/* probably a little skewed due to removing CRC */
		total_rx_bytes += skb->len;

2435
		/* populate checksum, VLAN, and protocol */
2436
		i40e_process_skb_fields(rx_ring, rx_desc, skb);
2437

S
Scott Peterson 已提交
2438
		i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
2439
		napi_gro_receive(&rx_ring->q_vector->napi, skb);
2440
		skb = NULL;
2441

2442 2443 2444
		/* update budget accounting */
		total_rx_packets++;
	}
2445

2446
	i40e_finalize_xdp_rx(rx_ring, xdp_xmit);
2447 2448
	rx_ring->skb = skb;

2449
	i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets);
2450

2451
	/* guarantee a trip back through this routine if there was a failure */
2452
	return failure ? budget : (int)total_rx_packets;
2453 2454
}

2455
static inline u32 i40e_buildreg_itr(const int type, u16 itr)
2456 2457 2458
{
	u32 val;

2459 2460 2461 2462 2463 2464 2465 2466 2467
	/* We don't bother with setting the CLEARPBA bit as the data sheet
	 * points out doing so is "meaningless since it was already
	 * auto-cleared". The auto-clearing happens when the interrupt is
	 * asserted.
	 *
	 * Hardware errata 28 for also indicates that writing to a
	 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
	 * an event in the PBA anyway so we need to rely on the automask
	 * to hold pending events for us until the interrupt is re-enabled
2468 2469 2470 2471 2472
	 *
	 * The itr value is reported in microseconds, and the register
	 * value is recorded in 2 microsecond units. For this reason we
	 * only need to shift by the interval shift - 1 instead of the
	 * full value.
2473
	 */
2474 2475
	itr &= I40E_ITR_MASK;

2476 2477
	val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
	      (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
2478
	      (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1));
2479 2480 2481 2482 2483 2484 2485

	return val;
}

/* a small macro to shorten up some long lines */
#define INTREG I40E_PFINT_DYN_CTLN

2486 2487 2488 2489 2490 2491 2492 2493 2494
/* The act of updating the ITR will cause it to immediately trigger. In order
 * to prevent this from throwing off adaptive update statistics we defer the
 * update so that it can only happen so often. So after either Tx or Rx are
 * updated we make the adaptive scheme wait until either the ITR completely
 * expires via the next_update expiration or we have been through at least
 * 3 interrupts.
 */
#define ITR_COUNTDOWN_START 3

2495 2496 2497 2498 2499 2500 2501 2502 2503 2504
/**
 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
 * @vsi: the VSI we care about
 * @q_vector: q_vector for which itr is being updated and interrupt enabled
 *
 **/
static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
					  struct i40e_q_vector *q_vector)
{
	struct i40e_hw *hw = &vsi->back->hw;
2505
	u32 intval;
2506

2507 2508
	/* If we don't have MSIX, then we only need to re-enable icr0 */
	if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {
2509
		i40e_irq_dynamic_enable_icr0(vsi->back);
2510 2511 2512
		return;
	}

2513 2514 2515
	/* These will do nothing if dynamic updates are not enabled */
	i40e_update_itr(q_vector, &q_vector->tx);
	i40e_update_itr(q_vector, &q_vector->rx);
2516

2517 2518 2519 2520 2521 2522 2523 2524 2525 2526
	/* This block of logic allows us to get away with only updating
	 * one ITR value with each interrupt. The idea is to perform a
	 * pseudo-lazy update with the following criteria.
	 *
	 * 1. Rx is given higher priority than Tx if both are in same state
	 * 2. If we must reduce an ITR that is given highest priority.
	 * 3. We then give priority to increasing ITR based on amount.
	 */
	if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
		/* Rx ITR needs to be reduced, this is highest priority */
2527 2528 2529
		intval = i40e_buildreg_itr(I40E_RX_ITR,
					   q_vector->rx.target_itr);
		q_vector->rx.current_itr = q_vector->rx.target_itr;
2530 2531 2532 2533 2534 2535 2536
		q_vector->itr_countdown = ITR_COUNTDOWN_START;
	} else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
		   ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
		    (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
		/* Tx ITR needs to be reduced, this is second priority
		 * Tx ITR needs to be increased more than Rx, fourth priority
		 */
2537 2538 2539
		intval = i40e_buildreg_itr(I40E_TX_ITR,
					   q_vector->tx.target_itr);
		q_vector->tx.current_itr = q_vector->tx.target_itr;
2540 2541 2542 2543 2544 2545 2546
		q_vector->itr_countdown = ITR_COUNTDOWN_START;
	} else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
		/* Rx ITR needs to be increased, third priority */
		intval = i40e_buildreg_itr(I40E_RX_ITR,
					   q_vector->rx.target_itr);
		q_vector->rx.current_itr = q_vector->rx.target_itr;
		q_vector->itr_countdown = ITR_COUNTDOWN_START;
2547
	} else {
2548
		/* No ITR update, lowest priority */
2549
		intval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
2550 2551
		if (q_vector->itr_countdown)
			q_vector->itr_countdown--;
2552 2553
	}

2554
	if (!test_bit(__I40E_VSI_DOWN, vsi->state))
2555
		wr32(hw, INTREG(q_vector->reg_idx), intval);
2556 2557
}

2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571
/**
 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
 * @napi: napi struct with our devices info in it
 * @budget: amount of work driver is allowed to do this pass, in packets
 *
 * This function will clean all queues associated with a q_vector.
 *
 * Returns the amount of work done
 **/
int i40e_napi_poll(struct napi_struct *napi, int budget)
{
	struct i40e_q_vector *q_vector =
			       container_of(napi, struct i40e_q_vector, napi);
	struct i40e_vsi *vsi = q_vector->vsi;
2572
	struct i40e_ring *ring;
2573
	bool clean_complete = true;
2574
	bool arm_wb = false;
2575
	int budget_per_ring;
2576
	int work_done = 0;
2577

2578
	if (test_bit(__I40E_VSI_DOWN, vsi->state)) {
2579 2580 2581 2582
		napi_complete(napi);
		return 0;
	}

2583 2584 2585
	/* Since the actual Tx work is minimal, we can give the Tx a larger
	 * budget and be more aggressive about cleaning up the Tx descriptors.
	 */
2586
	i40e_for_each_ring(ring, q_vector->tx) {
2587 2588 2589 2590 2591
		bool wd = ring->xsk_umem ?
			  i40e_clean_xdp_tx_irq(vsi, ring, budget) :
			  i40e_clean_tx_irq(vsi, ring, budget);

		if (!wd) {
2592 2593 2594 2595
			clean_complete = false;
			continue;
		}
		arm_wb |= ring->arm_wb;
2596
		ring->arm_wb = false;
2597
	}
2598

2599 2600 2601 2602
	/* Handle case where we are called by netpoll with a budget of 0 */
	if (budget <= 0)
		goto tx_only;

2603 2604 2605 2606
	/* We attempt to distribute budget to each Rx queue fairly, but don't
	 * allow the budget to go below 1 because that would exit polling early.
	 */
	budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
2607

2608
	i40e_for_each_ring(ring, q_vector->rx) {
2609 2610 2611
		int cleaned = ring->xsk_umem ?
			      i40e_clean_rx_irq_zc(ring, budget_per_ring) :
			      i40e_clean_rx_irq(ring, budget_per_ring);
2612 2613

		work_done += cleaned;
2614 2615 2616
		/* if we clean as many as budgeted, we must not be done */
		if (cleaned >= budget_per_ring)
			clean_complete = false;
2617
	}
2618 2619

	/* If work not completed, return budget and polling will return */
2620
	if (!clean_complete) {
2621 2622 2623 2624 2625 2626 2627 2628 2629
		int cpu_id = smp_processor_id();

		/* It is possible that the interrupt affinity has changed but,
		 * if the cpu is pegged at 100%, polling will never exit while
		 * traffic continues and the interrupt will be stuck on this
		 * cpu.  We check to make sure affinity is correct before we
		 * continue to poll, otherwise we must stop polling so the
		 * interrupt can move to the correct cpu.
		 */
2630 2631 2632 2633 2634 2635 2636 2637 2638 2639
		if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
			/* Tell napi that we are done polling */
			napi_complete_done(napi, work_done);

			/* Force an interrupt */
			i40e_force_wb(vsi, q_vector);

			/* Return budget-1 so that polling stops */
			return budget - 1;
		}
2640
tx_only:
2641 2642 2643
		if (arm_wb) {
			q_vector->tx.ring[0].tx_stats.tx_force_wb++;
			i40e_enable_wb_on_itr(vsi, q_vector);
2644
		}
2645
		return budget;
2646
	}
2647

2648 2649 2650
	if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
		q_vector->arm_wb_state = false;

2651 2652 2653 2654 2655
	/* Exit the polling mode, but don't re-enable interrupts if stack might
	 * poll us due to busy-polling
	 */
	if (likely(napi_complete_done(napi, work_done)))
		i40e_update_enable_itr(vsi, q_vector);
2656

2657
	return min(work_done, budget - 1);
2658 2659 2660 2661 2662 2663
}

/**
 * i40e_atr - Add a Flow Director ATR filter
 * @tx_ring:  ring to add programming descriptor to
 * @skb:      send buffer
2664
 * @tx_flags: send tx flags
2665 2666
 **/
static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2667
		     u32 tx_flags)
2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678
{
	struct i40e_filter_program_desc *fdir_desc;
	struct i40e_pf *pf = tx_ring->vsi->back;
	union {
		unsigned char *network;
		struct iphdr *ipv4;
		struct ipv6hdr *ipv6;
	} hdr;
	struct tcphdr *th;
	unsigned int hlen;
	u32 flex_ptype, dtype_cmd;
2679
	int l4_proto;
2680
	u16 i;
2681 2682

	/* make sure ATR is enabled */
J
Jesse Brandeburg 已提交
2683
	if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2684 2685
		return;

2686
	if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2687 2688
		return;

2689 2690 2691 2692
	/* if sampling is disabled do nothing */
	if (!tx_ring->atr_sample_rate)
		return;

2693
	/* Currently only IPv4/IPv6 with TCP is supported */
2694 2695
	if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
		return;
2696

2697 2698 2699
	/* snag network header to get L4 type and address */
	hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
		      skb_inner_network_header(skb) : skb_network_header(skb);
2700

2701 2702 2703 2704
	/* Note: tx_flags gets modified to reflect inner protocols in
	 * tx_enable_csum function if encap is enabled.
	 */
	if (tx_flags & I40E_TX_FLAGS_IPV4) {
2705
		/* access ihl as u8 to avoid unaligned access on ia64 */
2706 2707
		hlen = (hdr.network[0] & 0x0F) << 2;
		l4_proto = hdr.ipv4->protocol;
2708
	} else {
2709 2710 2711 2712 2713 2714 2715 2716 2717
		/* find the start of the innermost ipv6 header */
		unsigned int inner_hlen = hdr.network - skb->data;
		unsigned int h_offset = inner_hlen;

		/* this function updates h_offset to the end of the header */
		l4_proto =
		  ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL);
		/* hlen will contain our best estimate of the tcp header */
		hlen = h_offset - inner_hlen;
2718 2719
	}

2720
	if (l4_proto != IPPROTO_TCP)
2721 2722
		return;

2723 2724
	th = (struct tcphdr *)(hdr.network + hlen);

2725
	/* Due to lack of space, no more new filters can be programmed */
2726
	if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2727
		return;
2728
	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) {
2729 2730 2731 2732 2733 2734
		/* HW ATR eviction will take care of removing filters on FIN
		 * and RST packets.
		 */
		if (th->fin || th->rst)
			return;
	}
2735 2736 2737

	tx_ring->atr_count++;

2738 2739 2740 2741 2742
	/* sample on all syn/fin/rst packets or once every atr sample rate */
	if (!th->fin &&
	    !th->syn &&
	    !th->rst &&
	    (tx_ring->atr_count < tx_ring->atr_sample_rate))
2743 2744 2745 2746 2747
		return;

	tx_ring->atr_count = 0;

	/* grab the next descriptor */
2748 2749 2750 2751 2752
	i = tx_ring->next_to_use;
	fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);

	i++;
	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2753 2754 2755

	flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
		      I40E_TXD_FLTR_QW0_QINDEX_MASK;
2756
	flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2757 2758 2759 2760 2761 2762 2763 2764 2765
		      (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
		       I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
		      (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
		       I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);

	flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;

	dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;

2766
	dtype_cmd |= (th->fin || th->rst) ?
2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777
		     (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
		      I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
		     (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
		      I40E_TXD_FLTR_QW1_PCMD_SHIFT);

	dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
		     I40E_TXD_FLTR_QW1_DEST_SHIFT;

	dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
		     I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;

2778
	dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2779
	if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2780 2781 2782 2783 2784 2785 2786 2787 2788
		dtype_cmd |=
			((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
			I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
			I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
	else
		dtype_cmd |=
			((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
			I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
			I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2789

2790
	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED)
2791 2792
		dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;

2793
	fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
J
Jesse Brandeburg 已提交
2794
	fdir_desc->rsvd = cpu_to_le32(0);
2795
	fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
J
Jesse Brandeburg 已提交
2796
	fdir_desc->fd_id = cpu_to_le32(0);
2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810
}

/**
 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
 * @skb:     send buffer
 * @tx_ring: ring to send buffer on
 * @flags:   the tx flags to be set
 *
 * Checks the skb and set up correspondingly several generic transmit flags
 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
 *
 * Returns error code indicate the frame should be dropped upon error and the
 * otherwise  returns 0 to indicate the flags has been set properly.
 **/
2811 2812 2813
static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
					     struct i40e_ring *tx_ring,
					     u32 *flags)
2814 2815 2816 2817
{
	__be16 protocol = skb->protocol;
	u32  tx_flags = 0;

2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830
	if (protocol == htons(ETH_P_8021Q) &&
	    !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
		/* When HW VLAN acceleration is turned off by the user the
		 * stack sets the protocol to 8021q so that the driver
		 * can take any steps required to support the SW only
		 * VLAN handling.  In our case the driver doesn't need
		 * to take any further steps so just set the protocol
		 * to the encapsulated ethertype.
		 */
		skb->protocol = vlan_get_protocol(skb);
		goto out;
	}

2831
	/* if we have a HW VLAN tag being added, default to the HW one */
2832 2833
	if (skb_vlan_tag_present(skb)) {
		tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2834 2835
		tx_flags |= I40E_TX_FLAGS_HW_VLAN;
	/* else if it is a SW VLAN, check the next protocol and store the tag */
2836
	} else if (protocol == htons(ETH_P_8021Q)) {
2837
		struct vlan_hdr *vhdr, _vhdr;
J
Jesse Brandeburg 已提交
2838

2839 2840 2841 2842 2843 2844 2845 2846 2847
		vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
		if (!vhdr)
			return -EINVAL;

		protocol = vhdr->h_vlan_encapsulated_proto;
		tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
		tx_flags |= I40E_TX_FLAGS_SW_VLAN;
	}

2848 2849 2850
	if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
		goto out;

2851
	/* Insert 802.1p priority into VLAN header */
2852 2853
	if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
	    (skb->priority != TC_PRIO_CONTROL)) {
2854 2855 2856 2857 2858
		tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
		tx_flags |= (skb->priority & 0x7) <<
				I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
		if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
			struct vlan_ethhdr *vhdr;
2859 2860 2861 2862 2863
			int rc;

			rc = skb_cow_head(skb, 0);
			if (rc < 0)
				return rc;
2864 2865 2866 2867 2868 2869 2870
			vhdr = (struct vlan_ethhdr *)skb->data;
			vhdr->h_vlan_TCI = htons(tx_flags >>
						 I40E_TX_FLAGS_VLAN_SHIFT);
		} else {
			tx_flags |= I40E_TX_FLAGS_HW_VLAN;
		}
	}
2871 2872

out:
2873 2874 2875 2876 2877 2878
	*flags = tx_flags;
	return 0;
}

/**
 * i40e_tso - set up the tso context descriptor
2879
 * @first:    pointer to first Tx buffer for xmit
2880
 * @hdr_len:  ptr to the size of the packet header
2881
 * @cd_type_cmd_tso_mss: Quad Word 1
2882 2883 2884
 *
 * Returns 0 if no TSO can happen, 1 if tso is going, or error
 **/
2885 2886
static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len,
		    u64 *cd_type_cmd_tso_mss)
2887
{
2888
	struct sk_buff *skb = first->skb;
2889
	u64 cd_cmd, cd_tso_len, cd_mss;
2890 2891 2892 2893 2894
	union {
		struct iphdr *v4;
		struct ipv6hdr *v6;
		unsigned char *hdr;
	} ip;
2895 2896
	union {
		struct tcphdr *tcp;
2897
		struct udphdr *udp;
2898 2899 2900
		unsigned char *hdr;
	} l4;
	u32 paylen, l4_offset;
2901
	u16 gso_segs, gso_size;
2902 2903
	int err;

2904 2905 2906
	if (skb->ip_summed != CHECKSUM_PARTIAL)
		return 0;

2907 2908 2909
	if (!skb_is_gso(skb))
		return 0;

2910 2911 2912
	err = skb_cow_head(skb, 0);
	if (err < 0)
		return err;
2913

2914 2915
	ip.hdr = skb_network_header(skb);
	l4.hdr = skb_transport_header(skb);
2916

2917 2918 2919 2920
	/* initialize outer IP header fields */
	if (ip.v4->version == 4) {
		ip.v4->tot_len = 0;
		ip.v4->check = 0;
2921
	} else {
2922 2923 2924
		ip.v6->payload_len = 0;
	}

2925
	if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
2926
					 SKB_GSO_GRE_CSUM |
2927
					 SKB_GSO_IPXIP4 |
2928
					 SKB_GSO_IPXIP6 |
2929
					 SKB_GSO_UDP_TUNNEL |
2930
					 SKB_GSO_UDP_TUNNEL_CSUM)) {
2931 2932 2933 2934
		if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
			l4.udp->len = 0;

2935 2936 2937 2938
			/* determine offset of outer transport header */
			l4_offset = l4.hdr - skb->data;

			/* remove payload length from outer checksum */
2939
			paylen = skb->len - l4_offset;
2940 2941
			csum_replace_by_diff(&l4.udp->check,
					     (__force __wsum)htonl(paylen));
2942 2943
		}

2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954
		/* reset pointers to inner headers */
		ip.hdr = skb_inner_network_header(skb);
		l4.hdr = skb_inner_transport_header(skb);

		/* initialize inner IP header fields */
		if (ip.v4->version == 4) {
			ip.v4->tot_len = 0;
			ip.v4->check = 0;
		} else {
			ip.v6->payload_len = 0;
		}
2955 2956
	}

2957 2958 2959 2960
	/* determine offset of inner transport header */
	l4_offset = l4.hdr - skb->data;

	/* remove payload length from inner checksum */
2961
	paylen = skb->len - l4_offset;
2962
	csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
2963 2964 2965

	/* compute length of segmentation header */
	*hdr_len = (l4.tcp->doff * 4) + l4_offset;
2966

2967 2968 2969 2970 2971 2972 2973 2974
	/* pull values out of skb_shinfo */
	gso_size = skb_shinfo(skb)->gso_size;
	gso_segs = skb_shinfo(skb)->gso_segs;

	/* update GSO size and bytecount with header size */
	first->gso_segs = gso_segs;
	first->bytecount += (first->gso_segs - 1) * *hdr_len;

2975 2976 2977
	/* find the field values */
	cd_cmd = I40E_TX_CTX_DESC_TSO;
	cd_tso_len = skb->len - *hdr_len;
2978
	cd_mss = gso_size;
2979 2980 2981
	*cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
				(cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
				(cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
2982 2983 2984
	return 1;
}

J
Jacob Keller 已提交
2985 2986 2987 2988 2989
/**
 * i40e_tsyn - set up the tsyn context descriptor
 * @tx_ring:  ptr to the ring to send
 * @skb:      ptr to the skb we're sending
 * @tx_flags: the collected send information
2990
 * @cd_type_cmd_tso_mss: Quad Word 1
J
Jacob Keller 已提交
2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009
 *
 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
 **/
static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
		     u32 tx_flags, u64 *cd_type_cmd_tso_mss)
{
	struct i40e_pf *pf;

	if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
		return 0;

	/* Tx timestamps cannot be sampled when doing TSO */
	if (tx_flags & I40E_TX_FLAGS_TSO)
		return 0;

	/* only timestamp the outbound packet if the user has requested it and
	 * we are not already transmitting a packet to be timestamped
	 */
	pf = i40e_netdev_to_pf(tx_ring->netdev);
3010 3011 3012
	if (!(pf->flags & I40E_FLAG_PTP))
		return 0;

3013
	if (pf->ptp_tx &&
3014
	    !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) {
J
Jacob Keller 已提交
3015
		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3016
		pf->ptp_tx_start = jiffies;
J
Jacob Keller 已提交
3017 3018
		pf->ptp_tx_skb = skb_get(skb);
	} else {
3019
		pf->tx_hwtstamp_skipped++;
J
Jacob Keller 已提交
3020 3021 3022 3023 3024 3025 3026 3027 3028
		return 0;
	}

	*cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
				I40E_TXD_CTX_QW1_CMD_SHIFT;

	return 1;
}

3029 3030 3031
/**
 * i40e_tx_enable_csum - Enable Tx checksum offloads
 * @skb: send buffer
3032
 * @tx_flags: pointer to Tx flags currently set
3033 3034
 * @td_cmd: Tx descriptor command bits to set
 * @td_offset: Tx descriptor header offsets to set
3035
 * @tx_ring: Tx descriptor ring
3036 3037
 * @cd_tunneling: ptr to context desc bits
 **/
3038 3039 3040 3041
static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
			       u32 *td_cmd, u32 *td_offset,
			       struct i40e_ring *tx_ring,
			       u32 *cd_tunneling)
3042
{
3043 3044 3045 3046 3047 3048 3049 3050 3051 3052
	union {
		struct iphdr *v4;
		struct ipv6hdr *v6;
		unsigned char *hdr;
	} ip;
	union {
		struct tcphdr *tcp;
		struct udphdr *udp;
		unsigned char *hdr;
	} l4;
3053
	unsigned char *exthdr;
3054
	u32 offset, cmd = 0;
3055
	__be16 frag_off;
3056 3057
	u8 l4_proto = 0;

3058 3059 3060
	if (skb->ip_summed != CHECKSUM_PARTIAL)
		return 0;

3061 3062
	ip.hdr = skb_network_header(skb);
	l4.hdr = skb_transport_header(skb);
3063

3064 3065 3066
	/* compute outer L2 header size */
	offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;

3067
	if (skb->encapsulation) {
3068
		u32 tunnel = 0;
3069 3070
		/* define outer network header type */
		if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3071 3072 3073 3074
			tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
				  I40E_TX_CTX_EXT_IP_IPV4 :
				  I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;

3075 3076
			l4_proto = ip.v4->protocol;
		} else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3077
			tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
3078 3079

			exthdr = ip.hdr + sizeof(*ip.v6);
3080
			l4_proto = ip.v6->nexthdr;
3081 3082 3083
			if (l4.hdr != exthdr)
				ipv6_skip_exthdr(skb, exthdr - skb->data,
						 &l4_proto, &frag_off);
3084 3085 3086 3087
		}

		/* define outer transport */
		switch (l4_proto) {
3088
		case IPPROTO_UDP:
3089
			tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
3090
			*tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3091
			break;
3092
		case IPPROTO_GRE:
3093
			tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
3094
			*tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3095
			break;
3096 3097 3098 3099 3100
		case IPPROTO_IPIP:
		case IPPROTO_IPV6:
			*tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
			l4.hdr = skb_inner_network_header(skb);
			break;
3101
		default:
3102 3103 3104 3105 3106
			if (*tx_flags & I40E_TX_FLAGS_TSO)
				return -1;

			skb_checksum_help(skb);
			return 0;
3107
		}
3108

3109 3110 3111 3112 3113 3114 3115
		/* compute outer L3 header size */
		tunnel |= ((l4.hdr - ip.hdr) / 4) <<
			  I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;

		/* switch IP header pointer from outer to inner header */
		ip.hdr = skb_inner_network_header(skb);

3116 3117 3118 3119
		/* compute tunnel header size */
		tunnel |= ((ip.hdr - l4.hdr) / 2) <<
			  I40E_TXD_CTX_QW0_NATLEN_SHIFT;

3120 3121
		/* indicate if we need to offload outer UDP header */
		if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
3122
		    !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3123 3124 3125
		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
			tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;

3126 3127 3128
		/* record tunnel offload values */
		*cd_tunneling |= tunnel;

3129 3130
		/* switch L4 header pointer from outer to inner */
		l4.hdr = skb_inner_transport_header(skb);
3131
		l4_proto = 0;
3132

3133 3134 3135 3136 3137
		/* reset type as we transition from outer to inner headers */
		*tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
		if (ip.v4->version == 4)
			*tx_flags |= I40E_TX_FLAGS_IPV4;
		if (ip.v6->version == 6)
3138
			*tx_flags |= I40E_TX_FLAGS_IPV6;
3139 3140 3141
	}

	/* Enable IP checksum offloads */
3142
	if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3143
		l4_proto = ip.v4->protocol;
3144 3145 3146
		/* the stack computes the IP header already, the only time we
		 * need the hardware to recompute it is in the case of TSO.
		 */
3147 3148 3149
		cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
		       I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
		       I40E_TX_DESC_CMD_IIPT_IPV4;
3150
	} else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3151
		cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
3152 3153 3154 3155 3156 3157

		exthdr = ip.hdr + sizeof(*ip.v6);
		l4_proto = ip.v6->nexthdr;
		if (l4.hdr != exthdr)
			ipv6_skip_exthdr(skb, exthdr - skb->data,
					 &l4_proto, &frag_off);
3158
	}
3159

3160 3161
	/* compute inner L3 header size */
	offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
3162 3163

	/* Enable L4 checksum offloads */
3164
	switch (l4_proto) {
3165 3166
	case IPPROTO_TCP:
		/* enable checksum offloads */
3167 3168
		cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
		offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3169 3170 3171
		break;
	case IPPROTO_SCTP:
		/* enable SCTP checksum offload */
3172 3173 3174
		cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
		offset |= (sizeof(struct sctphdr) >> 2) <<
			  I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3175 3176 3177
		break;
	case IPPROTO_UDP:
		/* enable UDP checksum offload */
3178 3179 3180
		cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
		offset |= (sizeof(struct udphdr) >> 2) <<
			  I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3181 3182
		break;
	default:
3183 3184 3185 3186
		if (*tx_flags & I40E_TX_FLAGS_TSO)
			return -1;
		skb_checksum_help(skb);
		return 0;
3187
	}
3188 3189 3190

	*td_cmd |= cmd;
	*td_offset |= offset;
3191 3192

	return 1;
3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206
}

/**
 * i40e_create_tx_ctx Build the Tx context descriptor
 * @tx_ring:  ring to create the descriptor on
 * @cd_type_cmd_tso_mss: Quad Word 1
 * @cd_tunneling: Quad Word 0 - bits 0-31
 * @cd_l2tag2: Quad Word 0 - bits 32-63
 **/
static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
			       const u64 cd_type_cmd_tso_mss,
			       const u32 cd_tunneling, const u32 cd_l2tag2)
{
	struct i40e_tx_context_desc *context_desc;
3207
	int i = tx_ring->next_to_use;
3208

3209 3210
	if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
	    !cd_tunneling && !cd_l2tag2)
3211 3212 3213
		return;

	/* grab the next descriptor */
3214 3215 3216 3217
	context_desc = I40E_TX_CTXTDESC(tx_ring, i);

	i++;
	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3218 3219 3220 3221

	/* cpu_to_le32 and assign to struct fields */
	context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
	context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3222
	context_desc->rsvd = cpu_to_le16(0);
3223 3224 3225
	context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
}

E
Eric Dumazet 已提交
3226 3227 3228 3229 3230 3231 3232
/**
 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
 * @tx_ring: the ring to be checked
 * @size:    the size buffer we want to assure is available
 *
 * Returns -EBUSY if a stop is needed, else 0
 **/
3233
int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
E
Eric Dumazet 已提交
3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248
{
	netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
	/* Memory barrier before checking head and tail */
	smp_mb();

	/* Check again in a case another CPU has just made room available. */
	if (likely(I40E_DESC_UNUSED(tx_ring) < size))
		return -EBUSY;

	/* A reprieve! - use start_queue because it doesn't call schedule */
	netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
	++tx_ring->tx_stats.restart_queue;
	return 0;
}

3249
/**
3250
 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
3251 3252
 * @skb:      send buffer
 *
3253 3254 3255 3256 3257 3258 3259 3260
 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
 * and so we need to figure out the cases where we need to linearize the skb.
 *
 * For TSO we need to count the TSO header and segment payload separately.
 * As such we need to check cases where we have 7 fragments or more as we
 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
 * the segment payload in the first descriptor, and another 7 for the
 * fragments.
3261
 **/
3262
bool __i40e_chk_linearize(struct sk_buff *skb)
3263
{
3264
	const struct skb_frag_struct *frag, *stale;
3265
	int nr_frags, sum;
3266

3267
	/* no need to check if number of frags is less than 7 */
3268
	nr_frags = skb_shinfo(skb)->nr_frags;
3269
	if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
3270
		return false;
3271

3272
	/* We need to walk through the list and validate that each group
3273
	 * of 6 fragments totals at least gso_size.
3274
	 */
3275
	nr_frags -= I40E_MAX_BUFFER_TXD - 2;
3276 3277 3278 3279 3280 3281 3282 3283
	frag = &skb_shinfo(skb)->frags[0];

	/* Initialize size to the negative value of gso_size minus 1.  We
	 * use this as the worst case scenerio in which the frag ahead
	 * of us only provides one byte which is why we are limited to 6
	 * descriptors for a single transmit as the header and previous
	 * fragment are already consuming 2 descriptors.
	 */
3284
	sum = 1 - skb_shinfo(skb)->gso_size;
3285

3286 3287 3288 3289 3290 3291
	/* Add size of frags 0 through 4 to create our initial sum */
	sum += skb_frag_size(frag++);
	sum += skb_frag_size(frag++);
	sum += skb_frag_size(frag++);
	sum += skb_frag_size(frag++);
	sum += skb_frag_size(frag++);
3292 3293 3294 3295

	/* Walk through fragments adding latest fragment, testing it, and
	 * then removing stale fragments from the sum.
	 */
3296 3297 3298
	for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
		int stale_size = skb_frag_size(stale);

3299
		sum += skb_frag_size(frag++);
3300

3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319
		/* The stale fragment may present us with a smaller
		 * descriptor than the actual fragment size. To account
		 * for that we need to remove all the data on the front and
		 * figure out what the remainder would be in the last
		 * descriptor associated with the fragment.
		 */
		if (stale_size > I40E_MAX_DATA_PER_TXD) {
			int align_pad = -(stale->page_offset) &
					(I40E_MAX_READ_REQ_SIZE - 1);

			sum -= align_pad;
			stale_size -= align_pad;

			do {
				sum -= I40E_MAX_DATA_PER_TXD_ALIGNED;
				stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED;
			} while (stale_size > I40E_MAX_DATA_PER_TXD);
		}

3320 3321 3322 3323
		/* if sum is negative we failed to make sufficient progress */
		if (sum < 0)
			return true;

3324
		if (!nr_frags--)
3325 3326
			break;

3327
		sum -= stale_size;
3328 3329
	}

3330
	return false;
3331 3332
}

3333 3334 3335 3336 3337 3338 3339 3340 3341
/**
 * i40e_tx_map - Build the Tx descriptor
 * @tx_ring:  ring to send buffer on
 * @skb:      send buffer
 * @first:    first buffer info buffer to use
 * @tx_flags: collected send information
 * @hdr_len:  size of the packet header
 * @td_cmd:   the command field in the descriptor
 * @td_offset: offset for checksum or crc
3342 3343
 *
 * Returns 0 on success, -1 on failure to DMA
3344
 **/
3345 3346 3347
static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
			      struct i40e_tx_buffer *first, u32 tx_flags,
			      const u8 hdr_len, u32 td_cmd, u32 td_offset)
3348 3349 3350
{
	unsigned int data_len = skb->data_len;
	unsigned int size = skb_headlen(skb);
A
Alexander Duyck 已提交
3351
	struct skb_frag_struct *frag;
3352 3353
	struct i40e_tx_buffer *tx_bi;
	struct i40e_tx_desc *tx_desc;
A
Alexander Duyck 已提交
3354
	u16 i = tx_ring->next_to_use;
3355 3356
	u32 td_tag = 0;
	dma_addr_t dma;
3357
	u16 desc_count = 1;
3358 3359 3360 3361 3362 3363 3364

	if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
		td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
		td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
			 I40E_TX_FLAGS_VLAN_SHIFT;
	}

A
Alexander Duyck 已提交
3365 3366 3367 3368
	first->tx_flags = tx_flags;

	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);

3369
	tx_desc = I40E_TX_DESC(tx_ring, i);
A
Alexander Duyck 已提交
3370 3371 3372
	tx_bi = first;

	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
3373 3374
		unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;

A
Alexander Duyck 已提交
3375 3376 3377 3378 3379 3380 3381
		if (dma_mapping_error(tx_ring->dev, dma))
			goto dma_error;

		/* record length, and DMA address */
		dma_unmap_len_set(tx_bi, len, size);
		dma_unmap_addr_set(tx_bi, dma, dma);

3382 3383
		/* align size to end of page */
		max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
A
Alexander Duyck 已提交
3384 3385 3386
		tx_desc->buffer_addr = cpu_to_le64(dma);

		while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
3387 3388
			tx_desc->cmd_type_offset_bsz =
				build_ctob(td_cmd, td_offset,
3389
					   max_data, td_tag);
3390 3391 3392

			tx_desc++;
			i++;
3393 3394
			desc_count++;

3395 3396 3397 3398 3399
			if (i == tx_ring->count) {
				tx_desc = I40E_TX_DESC(tx_ring, 0);
				i = 0;
			}

3400 3401
			dma += max_data;
			size -= max_data;
3402

3403
			max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
A
Alexander Duyck 已提交
3404 3405
			tx_desc->buffer_addr = cpu_to_le64(dma);
		}
3406 3407 3408 3409

		if (likely(!data_len))
			break;

A
Alexander Duyck 已提交
3410 3411
		tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
							  size, td_tag);
3412 3413 3414

		tx_desc++;
		i++;
3415 3416
		desc_count++;

3417 3418 3419 3420 3421
		if (i == tx_ring->count) {
			tx_desc = I40E_TX_DESC(tx_ring, 0);
			i = 0;
		}

A
Alexander Duyck 已提交
3422 3423
		size = skb_frag_size(frag);
		data_len -= size;
3424

A
Alexander Duyck 已提交
3425 3426
		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
				       DMA_TO_DEVICE);
3427

A
Alexander Duyck 已提交
3428 3429
		tx_bi = &tx_ring->tx_bi[i];
	}
3430

3431
	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
A
Alexander Duyck 已提交
3432 3433 3434 3435 3436 3437 3438

	i++;
	if (i == tx_ring->count)
		i = 0;

	tx_ring->next_to_use = i;

E
Eric Dumazet 已提交
3439
	i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
3440

3441 3442 3443
	/* write last descriptor with EOP bit */
	td_cmd |= I40E_TX_DESC_CMD_EOP;

3444 3445
	/* We OR these values together to check both against 4 (WB_STRIDE)
	 * below. This is safe since we don't re-use desc_count afterwards.
3446 3447 3448
	 */
	desc_count |= ++tx_ring->packet_stride;

3449
	if (desc_count >= WB_STRIDE) {
3450 3451
		/* write last descriptor with RS bit set */
		td_cmd |= I40E_TX_DESC_CMD_RS;
3452 3453 3454 3455
		tx_ring->packet_stride = 0;
	}

	tx_desc->cmd_type_offset_bsz =
3456 3457
			build_ctob(td_cmd, td_offset, size, td_tag);

3458 3459
	skb_tx_timestamp(skb);

3460 3461 3462 3463 3464 3465 3466 3467 3468 3469
	/* Force memory writes to complete before letting h/w know there
	 * are new descriptors to fetch.
	 *
	 * We also use this memory barrier to make certain all of the
	 * status bits have been updated before next_to_watch is written.
	 */
	wmb();

	/* set next_to_watch value indicating a packet is present */
	first->next_to_watch = tx_desc;
3470

A
Alexander Duyck 已提交
3471
	/* notify HW of packet */
3472
	if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
3473
		writel(i, tx_ring->tail);
3474 3475 3476 3477 3478

		/* we need this if more than one processor can write to our tail
		 * at a time, it synchronizes IO on IA64/Altix systems
		 */
		mmiowb();
3479
	}
3480

3481
	return 0;
3482 3483

dma_error:
A
Alexander Duyck 已提交
3484
	dev_info(tx_ring->dev, "TX DMA map failed\n");
3485 3486 3487 3488

	/* clear dma mappings for failed tx_bi map */
	for (;;) {
		tx_bi = &tx_ring->tx_bi[i];
A
Alexander Duyck 已提交
3489
		i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
3490 3491 3492 3493 3494 3495 3496 3497
		if (tx_bi == first)
			break;
		if (i == 0)
			i = tx_ring->count;
		i--;
	}

	tx_ring->next_to_use = i;
3498 3499

	return -1;
3500 3501
}

3502 3503 3504 3505 3506
/**
 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring
 * @xdp: data to transmit
 * @xdp_ring: XDP Tx ring
 **/
3507
static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
3508 3509 3510 3511 3512
			      struct i40e_ring *xdp_ring)
{
	u16 i = xdp_ring->next_to_use;
	struct i40e_tx_buffer *tx_bi;
	struct i40e_tx_desc *tx_desc;
3513
	void *data = xdpf->data;
3514
	u32 size = xdpf->len;
3515 3516 3517 3518 3519 3520
	dma_addr_t dma;

	if (!unlikely(I40E_DESC_UNUSED(xdp_ring))) {
		xdp_ring->tx_stats.tx_busy++;
		return I40E_XDP_CONSUMED;
	}
3521
	dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE);
3522 3523 3524 3525 3526 3527
	if (dma_mapping_error(xdp_ring->dev, dma))
		return I40E_XDP_CONSUMED;

	tx_bi = &xdp_ring->tx_bi[i];
	tx_bi->bytecount = size;
	tx_bi->gso_segs = 1;
3528
	tx_bi->xdpf = xdpf;
3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554

	/* record length, and DMA address */
	dma_unmap_len_set(tx_bi, len, size);
	dma_unmap_addr_set(tx_bi, dma, dma);

	tx_desc = I40E_TX_DESC(xdp_ring, i);
	tx_desc->buffer_addr = cpu_to_le64(dma);
	tx_desc->cmd_type_offset_bsz = build_ctob(I40E_TX_DESC_CMD_ICRC
						  | I40E_TXD_CMD,
						  0, size, 0);

	/* Make certain all of the status bits have been updated
	 * before next_to_watch is written.
	 */
	smp_wmb();

	i++;
	if (i == xdp_ring->count)
		i = 0;

	tx_bi->next_to_watch = tx_desc;
	xdp_ring->next_to_use = i;

	return I40E_XDP_TX;
}

3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572
/**
 * i40e_xmit_frame_ring - Sends buffer on Tx ring
 * @skb:     send buffer
 * @tx_ring: ring to send buffer on
 *
 * Returns NETDEV_TX_OK if sent, else an error code
 **/
static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
					struct i40e_ring *tx_ring)
{
	u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
	u32 cd_tunneling = 0, cd_l2tag2 = 0;
	struct i40e_tx_buffer *first;
	u32 td_offset = 0;
	u32 tx_flags = 0;
	__be16 protocol;
	u32 td_cmd = 0;
	u8 hdr_len = 0;
3573
	int tso, count;
J
Jacob Keller 已提交
3574
	int tsyn;
J
Jesse Brandeburg 已提交
3575

3576 3577 3578
	/* prefetch the data, we'll need it later */
	prefetch(skb->data);

S
Scott Peterson 已提交
3579 3580
	i40e_trace(xmit_frame_ring, skb, tx_ring);

3581
	count = i40e_xmit_descriptor_count(skb);
3582
	if (i40e_chk_linearize(skb, count)) {
3583 3584 3585 3586
		if (__skb_linearize(skb)) {
			dev_kfree_skb_any(skb);
			return NETDEV_TX_OK;
		}
3587
		count = i40e_txd_use_count(skb->len);
3588 3589
		tx_ring->tx_stats.tx_linearize++;
	}
3590 3591 3592 3593 3594 3595 3596 3597 3598

	/* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
	 *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
	 *       + 4 desc gap to avoid the cache line where head is,
	 *       + 1 desc for context descriptor,
	 * otherwise try next time
	 */
	if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
		tx_ring->tx_stats.tx_busy++;
3599
		return NETDEV_TX_BUSY;
3600
	}
3601

3602 3603 3604 3605 3606 3607
	/* record the location of the first descriptor for this packet */
	first = &tx_ring->tx_bi[tx_ring->next_to_use];
	first->skb = skb;
	first->bytecount = skb->len;
	first->gso_segs = 1;

3608 3609 3610 3611 3612
	/* prepare the xmit flags */
	if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
		goto out_drop;

	/* obtain protocol of skb */
3613
	protocol = vlan_get_protocol(skb);
3614 3615

	/* setup IPv4/IPv6 offloads */
3616
	if (protocol == htons(ETH_P_IP))
3617
		tx_flags |= I40E_TX_FLAGS_IPV4;
3618
	else if (protocol == htons(ETH_P_IPV6))
3619 3620
		tx_flags |= I40E_TX_FLAGS_IPV6;

3621
	tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
3622 3623 3624 3625 3626 3627

	if (tso < 0)
		goto out_drop;
	else if (tso)
		tx_flags |= I40E_TX_FLAGS_TSO;

3628 3629 3630 3631 3632 3633
	/* Always offload the checksum, since it's in the data descriptor */
	tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
				  tx_ring, &cd_tunneling);
	if (tso < 0)
		goto out_drop;

J
Jacob Keller 已提交
3634 3635 3636 3637 3638
	tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);

	if (tsyn)
		tx_flags |= I40E_TX_FLAGS_TSYN;

3639 3640 3641
	/* always enable CRC insertion offload */
	td_cmd |= I40E_TX_DESC_CMD_ICRC;

3642 3643 3644 3645 3646 3647 3648
	i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
			   cd_tunneling, cd_l2tag2);

	/* Add Flow Director ATR if it's enabled.
	 *
	 * NOTE: this must always be directly before the data descriptor.
	 */
3649
	i40e_atr(tx_ring, skb, tx_flags);
3650

3651 3652 3653
	if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
			td_cmd, td_offset))
		goto cleanup_tx_tstamp;
3654 3655 3656 3657

	return NETDEV_TX_OK;

out_drop:
S
Scott Peterson 已提交
3658
	i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring);
3659 3660
	dev_kfree_skb_any(first->skb);
	first->skb = NULL;
3661 3662 3663 3664 3665 3666 3667 3668 3669
cleanup_tx_tstamp:
	if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) {
		struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev);

		dev_kfree_skb_any(pf->ptp_tx_skb);
		pf->ptp_tx_skb = NULL;
		clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
	}

3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683
	return NETDEV_TX_OK;
}

/**
 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
 * @skb:    send buffer
 * @netdev: network interface device structure
 *
 * Returns NETDEV_TX_OK if sent, else an error code
 **/
netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
{
	struct i40e_netdev_priv *np = netdev_priv(netdev);
	struct i40e_vsi *vsi = np->vsi;
3684
	struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
3685 3686 3687 3688

	/* hardware can't handle really short frames, hardware padding works
	 * beyond this point
	 */
3689 3690
	if (skb_put_padto(skb, I40E_MIN_TX_LEN))
		return NETDEV_TX_OK;
3691 3692 3693

	return i40e_xmit_frame_ring(skb, tx_ring);
}
3694 3695 3696 3697 3698 3699

/**
 * i40e_xdp_xmit - Implements ndo_xdp_xmit
 * @dev: netdev
 * @xdp: XDP buffer
 *
3700 3701 3702 3703 3704
 * Returns number of frames successfully sent. Frames that fail are
 * free'ed via XDP return API.
 *
 * For error cases, a negative errno code is returned and no-frames
 * are transmitted (caller must handle freeing frames).
3705
 **/
3706 3707
int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
		  u32 flags)
3708 3709 3710 3711
{
	struct i40e_netdev_priv *np = netdev_priv(dev);
	unsigned int queue_index = smp_processor_id();
	struct i40e_vsi *vsi = np->vsi;
3712
	struct i40e_pf *pf = vsi->back;
3713
	struct i40e_ring *xdp_ring;
3714 3715
	int drops = 0;
	int i;
3716 3717 3718 3719

	if (test_bit(__I40E_VSI_DOWN, vsi->state))
		return -ENETDOWN;

3720 3721
	if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs ||
	    test_bit(__I40E_CONFIG_BUSY, pf->state))
3722 3723
		return -ENXIO;

3724
	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3725 3726
		return -EINVAL;

3727 3728
	xdp_ring = vsi->xdp_rings[queue_index];

3729 3730 3731
	for (i = 0; i < n; i++) {
		struct xdp_frame *xdpf = frames[i];
		int err;
3732

3733
		err = i40e_xmit_xdp_ring(xdpf, xdp_ring);
3734 3735 3736 3737 3738 3739
		if (err != I40E_XDP_TX) {
			xdp_return_frame_rx_napi(xdpf);
			drops++;
		}
	}

3740 3741
	if (unlikely(flags & XDP_XMIT_FLUSH))
		i40e_xdp_ring_update_tail(xdp_ring);
3742

3743
	return n - drops;
3744
}