intel_device_info.c 31.2 KB
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/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

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#include <drm/drm_print.h>

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#include "intel_device_info.h"
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#include "i915_drv.h"

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#define PLATFORM_NAME(x) [INTEL_##x] = #x
static const char * const platform_names[] = {
	PLATFORM_NAME(I830),
	PLATFORM_NAME(I845G),
	PLATFORM_NAME(I85X),
	PLATFORM_NAME(I865G),
	PLATFORM_NAME(I915G),
	PLATFORM_NAME(I915GM),
	PLATFORM_NAME(I945G),
	PLATFORM_NAME(I945GM),
	PLATFORM_NAME(G33),
	PLATFORM_NAME(PINEVIEW),
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	PLATFORM_NAME(I965G),
	PLATFORM_NAME(I965GM),
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	PLATFORM_NAME(G45),
	PLATFORM_NAME(GM45),
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	PLATFORM_NAME(IRONLAKE),
	PLATFORM_NAME(SANDYBRIDGE),
	PLATFORM_NAME(IVYBRIDGE),
	PLATFORM_NAME(VALLEYVIEW),
	PLATFORM_NAME(HASWELL),
	PLATFORM_NAME(BROADWELL),
	PLATFORM_NAME(CHERRYVIEW),
	PLATFORM_NAME(SKYLAKE),
	PLATFORM_NAME(BROXTON),
	PLATFORM_NAME(KABYLAKE),
	PLATFORM_NAME(GEMINILAKE),
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	PLATFORM_NAME(COFFEELAKE),
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	PLATFORM_NAME(CANNONLAKE),
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	PLATFORM_NAME(ICELAKE),
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	PLATFORM_NAME(ELKHARTLAKE),
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	PLATFORM_NAME(TIGERLAKE),
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};
#undef PLATFORM_NAME

const char *intel_platform_name(enum intel_platform platform)
{
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	BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);

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	if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
			 platform_names[platform] == NULL))
		return "<unknown>";

	return platform_names[platform];
}

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void intel_device_info_dump_flags(const struct intel_device_info *info,
				  struct drm_printer *p)
{
#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
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#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
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}

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static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
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	int s;

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	drm_printf(p, "slice total: %u, mask=%04x\n",
		   hweight8(sseu->slice_mask), sseu->slice_mask);
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	drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
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	for (s = 0; s < sseu->max_slices; s++) {
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		drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
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			   s, intel_sseu_subslices_per_slice(sseu, s),
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			   intel_sseu_get_subslices(sseu, s));
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	}
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	drm_printf(p, "EU total: %u\n", sseu->eu_total);
	drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
	drm_printf(p, "has slice power gating: %s\n",
		   yesno(sseu->has_slice_pg));
	drm_printf(p, "has subslice power gating: %s\n",
		   yesno(sseu->has_subslice_pg));
	drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
}

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void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
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				    struct drm_printer *p)
{
	sseu_dump(&info->sseu, p);

	drm_printf(p, "CS timestamp frequency: %u kHz\n",
		   info->cs_timestamp_frequency_khz);
}

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static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
		       int subslice)
{
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	int slice_stride = sseu->max_subslices * sseu->eu_stride;
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	return slice * slice_stride + subslice * sseu->eu_stride;
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}

static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
			int subslice)
{
	int i, offset = sseu_eu_idx(sseu, slice, subslice);
	u16 eu_mask = 0;

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	for (i = 0; i < sseu->eu_stride; i++) {
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		eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
			(i * BITS_PER_BYTE);
	}

	return eu_mask;
}

static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
			 u16 eu_mask)
{
	int i, offset = sseu_eu_idx(sseu, slice, subslice);

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	for (i = 0; i < sseu->eu_stride; i++) {
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		sseu->eu_mask[offset + i] =
			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
	}
}

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void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
				     struct drm_printer *p)
{
	int s, ss;

	if (sseu->max_slices == 0) {
		drm_printf(p, "Unavailable\n");
		return;
	}

	for (s = 0; s < sseu->max_slices; s++) {
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		drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
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			   s, intel_sseu_subslices_per_slice(sseu, s),
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			   intel_sseu_get_subslices(sseu, s));
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		for (ss = 0; ss < sseu->max_subslices; ss++) {
			u16 enabled_eus = sseu_get_eus(sseu, s, ss);

			drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n",
				   ss, hweight16(enabled_eus), enabled_eus);
		}
	}
}

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static u16 compute_eu_total(const struct sseu_dev_info *sseu)
{
	u16 i, total = 0;

	for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
		total += hweight8(sseu->eu_mask[i]);

	return total;
}

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static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
				    u8 s_en, u32 ss_en, u16 eu_en)
{
	int s, ss;

	/* ss_en represents entire subslice mask across all slices */
	GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
		   sizeof(ss_en) * BITS_PER_BYTE);

	for (s = 0; s < sseu->max_slices; s++) {
		if ((s_en & BIT(s)) == 0)
			continue;

		sseu->slice_mask |= BIT(s);

		intel_sseu_set_subslices(sseu, s, ss_en);

		for (ss = 0; ss < sseu->max_subslices; ss++)
			if (intel_sseu_has_subslice(sseu, s, ss))
				sseu_set_eus(sseu, s, ss, eu_en);
	}
	sseu->eu_per_subslice = hweight16(eu_en);
	sseu->eu_total = compute_eu_total(sseu);
}

static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
{
	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
	u8 s_en;
	u32 dss_en;
	u16 eu_en = 0;
	u8 eu_en_fuse;
	int eu;

	/*
	 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
	 * Instead of splitting these, provide userspace with an array
	 * of DSS to more closely represent the hardware resource.
	 */
	intel_sseu_set_info(sseu, 1, 6, 16);

	s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;

	dss_en = I915_READ(GEN12_GT_DSS_ENABLE);

	/* one bit per pair of EUs */
	eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
	for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
		if (eu_en_fuse & BIT(eu))
			eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);

	gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);

	/* TGL only supports slice-level power gating */
	sseu->has_slice_pg = 1;
}

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static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
{
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	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
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	u8 s_en;
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	u32 ss_en;
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	u8 eu_en;

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	if (IS_ELKHARTLAKE(dev_priv))
		intel_sseu_set_info(sseu, 1, 4, 8);
	else
		intel_sseu_set_info(sseu, 1, 8, 8);
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	s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
	ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
	eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);

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	gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
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	/* ICL has no power gating restrictions. */
	sseu->has_slice_pg = 1;
	sseu->has_subslice_pg = 1;
	sseu->has_eu_pg = 1;
}

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static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
{
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	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
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	const u32 fuse2 = I915_READ(GEN8_FUSE2);
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	int s, ss;
	const int eu_mask = 0xff;
	u32 subslice_mask, eu_en;
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	intel_sseu_set_info(sseu, 6, 4, 8);

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	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
			    GEN10_F2_S_ENA_SHIFT;
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	/* Slice0 */
	eu_en = ~I915_READ(GEN8_EU_DISABLE0);
	for (ss = 0; ss < sseu->max_subslices; ss++)
		sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
	/* Slice1 */
	sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
	eu_en = ~I915_READ(GEN8_EU_DISABLE1);
	sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
	/* Slice2 */
	sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
	sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
	/* Slice3 */
	sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
	eu_en = ~I915_READ(GEN8_EU_DISABLE2);
	sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
	/* Slice4 */
	sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
	sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
	/* Slice5 */
	sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
	eu_en = ~I915_READ(GEN10_EU_DISABLE3);
	sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);

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	subslice_mask = (1 << 4) - 1;
	subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
			   GEN10_F2_SS_DIS_SHIFT);

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	for (s = 0; s < sseu->max_slices; s++) {
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		u32 subslice_mask_with_eus = subslice_mask;

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		for (ss = 0; ss < sseu->max_subslices; ss++) {
			if (sseu_get_eus(sseu, s, ss) == 0)
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				subslice_mask_with_eus &= ~BIT(ss);
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		}
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		/*
		 * Slice0 can have up to 3 subslices, but there are only 2 in
		 * slice1/2.
		 */
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		intel_sseu_set_subslices(sseu, s, s == 0 ?
						  subslice_mask_with_eus :
						  subslice_mask_with_eus & 0x3);
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	}

	sseu->eu_total = compute_eu_total(sseu);
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	/*
	 * CNL is expected to always have a uniform distribution
	 * of EU across subslices with the exception that any one
	 * EU in any one subslice may be fused off for die
	 * recovery.
	 */
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	sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
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				DIV_ROUND_UP(sseu->eu_total,
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					     intel_sseu_subslice_total(sseu)) :
				0;
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	/* No restrictions on Power Gating */
	sseu->has_slice_pg = 1;
	sseu->has_subslice_pg = 1;
	sseu->has_eu_pg = 1;
}

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static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
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	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
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	u32 fuse;
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	u8 subslice_mask = 0;
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	fuse = I915_READ(CHV_FUSE_GT);

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	sseu->slice_mask = BIT(0);
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	intel_sseu_set_info(sseu, 1, 2, 8);
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	if (!(fuse & CHV_FGT_DISABLE_SS0)) {
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		u8 disabled_mask =
			((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
			 CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
			(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
			  CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);

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		subslice_mask |= BIT(0);
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		sseu_set_eus(sseu, 0, 0, ~disabled_mask);
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	}

	if (!(fuse & CHV_FGT_DISABLE_SS1)) {
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		u8 disabled_mask =
			((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
			 CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
			(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
			  CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);

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		subslice_mask |= BIT(1);
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		sseu_set_eus(sseu, 0, 1, ~disabled_mask);
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	}

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	intel_sseu_set_subslices(sseu, 0, subslice_mask);
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	sseu->eu_total = compute_eu_total(sseu);

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	/*
	 * CHV expected to always have a uniform distribution of EU
	 * across subslices.
	*/
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	sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
				sseu->eu_total /
					intel_sseu_subslice_total(sseu) :
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				0;
	/*
	 * CHV supports subslice power gating on devices with more than
	 * one subslice, and supports EU power gating on devices with
	 * more than one EU pair per subslice.
	*/
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	sseu->has_slice_pg = 0;
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	sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1;
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	sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
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}

static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
{
	struct intel_device_info *info = mkwrite_device_info(dev_priv);
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	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
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	int s, ss;
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	u32 fuse2, eu_disable, subslice_mask;
	const u8 eu_mask = 0xff;
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	fuse2 = I915_READ(GEN8_FUSE2);
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	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
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	/* BXT has a single slice and at most 3 subslices. */
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	intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
			    IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
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	/*
	 * The subslice disable field is global, i.e. it applies
	 * to each of the enabled slices.
	*/
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	subslice_mask = (1 << sseu->max_subslices) - 1;
	subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
			   GEN9_F2_SS_DIS_SHIFT);
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	/*
	 * Iterate through enabled slices and subslices to
	 * count the total enabled EU.
	*/
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	for (s = 0; s < sseu->max_slices; s++) {
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		if (!(sseu->slice_mask & BIT(s)))
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			/* skip disabled slice */
			continue;

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		intel_sseu_set_subslices(sseu, s, subslice_mask);
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		eu_disable = I915_READ(GEN9_EU_DISABLE(s));
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		for (ss = 0; ss < sseu->max_subslices; ss++) {
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			int eu_per_ss;
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			u8 eu_disabled_mask;
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			if (!intel_sseu_has_subslice(sseu, s, ss))
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				/* skip disabled subslice */
				continue;

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			eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
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			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);

			eu_per_ss = sseu->max_eus_per_subslice -
				hweight8(eu_disabled_mask);
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			/*
			 * Record which subslice(s) has(have) 7 EUs. we
			 * can tune the hash used to spread work among
			 * subslices if they are unbalanced.
			 */
			if (eu_per_ss == 7)
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				sseu->subslice_7eu[s] |= BIT(ss);
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		}
	}

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	sseu->eu_total = compute_eu_total(sseu);

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	/*
	 * SKL is expected to always have a uniform distribution
	 * of EU across subslices with the exception that any one
	 * EU in any one subslice may be fused off for die
	 * recovery. BXT is expected to be perfectly uniform in EU
	 * distribution.
	*/
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	sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
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				DIV_ROUND_UP(sseu->eu_total,
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					     intel_sseu_subslice_total(sseu)) :
				0;
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	/*
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	 * SKL+ supports slice power gating on devices with more than
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	 * one slice, and supports EU power gating on devices with
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	 * more than one EU pair per subslice. BXT+ supports subslice
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	 * power gating on devices with more than one subslice, and
	 * supports EU power gating on devices with more than one EU
	 * pair per subslice.
	*/
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	sseu->has_slice_pg =
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		!IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
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	sseu->has_subslice_pg =
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		IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1;
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	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
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	if (IS_GEN9_LP(dev_priv)) {
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#define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask[0] & BIT(ss)))
		info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
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		sseu->min_eu_in_pool = 0;
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		if (info->has_pooled_eu) {
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			if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
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				sseu->min_eu_in_pool = 3;
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			else if (IS_SS_DISABLED(1))
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				sseu->min_eu_in_pool = 6;
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			else
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				sseu->min_eu_in_pool = 9;
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		}
#undef IS_SS_DISABLED
	}
}

static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
{
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	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
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	int s, ss;
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	u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
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	fuse2 = I915_READ(GEN8_FUSE2);
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	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
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	intel_sseu_set_info(sseu, 3, 3, 8);
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	/*
	 * The subslice disable field is global, i.e. it applies
	 * to each of the enabled slices.
	 */
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	subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
	subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
			   GEN8_F2_SS_DIS_SHIFT);
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	eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
	eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
			((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
			 (32 - GEN8_EU_DIS0_S1_SHIFT));
	eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
			((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
			 (32 - GEN8_EU_DIS1_S2_SHIFT));

	/*
	 * Iterate through enabled slices and subslices to
	 * count the total enabled EU.
	 */
531
	for (s = 0; s < sseu->max_slices; s++) {
532
		if (!(sseu->slice_mask & BIT(s)))
533 534 535
			/* skip disabled slice */
			continue;

536
		intel_sseu_set_subslices(sseu, s, subslice_mask);
537 538 539

		for (ss = 0; ss < sseu->max_subslices; ss++) {
			u8 eu_disabled_mask;
540 541
			u32 n_disabled;

542
			if (!intel_sseu_has_subslice(sseu, s, ss))
543 544 545
				/* skip disabled subslice */
				continue;

546
			eu_disabled_mask =
547
				eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
548 549 550 551

			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);

			n_disabled = hweight8(eu_disabled_mask);
552 553 554 555

			/*
			 * Record which subslices have 7 EUs.
			 */
556
			if (sseu->max_eus_per_subslice - n_disabled == 7)
557
				sseu->subslice_7eu[s] |= 1 << ss;
558 559 560
		}
	}

561 562
	sseu->eu_total = compute_eu_total(sseu);

563 564 565 566 567
	/*
	 * BDW is expected to always have a uniform distribution of EU across
	 * subslices with the exception that any one EU in any one subslice may
	 * be fused off for die recovery.
	 */
568
	sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
569
				DIV_ROUND_UP(sseu->eu_total,
570 571
					     intel_sseu_subslice_total(sseu)) :
				0;
572 573 574 575 576

	/*
	 * BDW supports slice power gating on devices with more than
	 * one slice.
	 */
577
	sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
578 579
	sseu->has_subslice_pg = 0;
	sseu->has_eu_pg = 0;
580 581
}

582 583
static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
{
584
	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
585
	u32 fuse1;
586
	u8 subslice_mask = 0;
587
	int s, ss;
588 589 590 591 592

	/*
	 * There isn't a register to tell us how many slices/subslices. We
	 * work off the PCI-ids here.
	 */
593
	switch (INTEL_INFO(dev_priv)->gt) {
594
	default:
595
		MISSING_CASE(INTEL_INFO(dev_priv)->gt);
596 597 598
		/* fall through */
	case 1:
		sseu->slice_mask = BIT(0);
599
		subslice_mask = BIT(0);
600 601 602
		break;
	case 2:
		sseu->slice_mask = BIT(0);
603
		subslice_mask = BIT(0) | BIT(1);
604 605 606
		break;
	case 3:
		sseu->slice_mask = BIT(0) | BIT(1);
607
		subslice_mask = BIT(0) | BIT(1);
608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626
		break;
	}

	fuse1 = I915_READ(HSW_PAVP_FUSE1);
	switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
	default:
		MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
			     HSW_F1_EU_DIS_SHIFT);
		/* fall through */
	case HSW_F1_EU_DIS_10EUS:
		sseu->eu_per_subslice = 10;
		break;
	case HSW_F1_EU_DIS_8EUS:
		sseu->eu_per_subslice = 8;
		break;
	case HSW_F1_EU_DIS_6EUS:
		sseu->eu_per_subslice = 6;
		break;
	}
627 628

	intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
629
			    hweight8(subslice_mask),
630
			    sseu->eu_per_subslice);
631 632

	for (s = 0; s < sseu->max_slices; s++) {
633
		intel_sseu_set_subslices(sseu, s, subslice_mask);
634

635 636 637 638 639
		for (ss = 0; ss < sseu->max_subslices; ss++) {
			sseu_set_eus(sseu, s, ss,
				     (1UL << sseu->eu_per_subslice) - 1);
		}
	}
640

641
	sseu->eu_total = compute_eu_total(sseu);
642 643 644 645 646 647 648

	/* No powergating for you. */
	sseu->has_slice_pg = 0;
	sseu->has_subslice_pg = 0;
	sseu->has_eu_pg = 0;
}

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static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
650 651
{
	u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
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	u32 base_freq, frac_freq;
653 654 655

	base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
		     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
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	base_freq *= 1000;
657 658 659 660

	frac_freq = ((ts_override &
		      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
		     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
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	frac_freq = 1000 / (frac_freq + 1);
662 663 664 665

	return base_freq + frac_freq;
}

666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711
static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
					u32 rpm_config_reg)
{
	u32 f19_2_mhz = 19200;
	u32 f24_mhz = 24000;
	u32 crystal_clock = (rpm_config_reg &
			     GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
			    GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;

	switch (crystal_clock) {
	case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
		return f19_2_mhz;
	case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
		return f24_mhz;
	default:
		MISSING_CASE(crystal_clock);
		return 0;
	}
}

static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
					u32 rpm_config_reg)
{
	u32 f19_2_mhz = 19200;
	u32 f24_mhz = 24000;
	u32 f25_mhz = 25000;
	u32 f38_4_mhz = 38400;
	u32 crystal_clock = (rpm_config_reg &
			     GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
			    GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;

	switch (crystal_clock) {
	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
		return f24_mhz;
	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
		return f19_2_mhz;
	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
		return f38_4_mhz;
	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
		return f25_mhz;
	default:
		MISSING_CASE(crystal_clock);
		return 0;
	}
}

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static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
713
{
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714 715 716
	u32 f12_5_mhz = 12500;
	u32 f19_2_mhz = 19200;
	u32 f24_mhz = 24000;
717 718 719 720 721 722 723 724

	if (INTEL_GEN(dev_priv) <= 4) {
		/* PRMs say:
		 *
		 *     "The value in this register increments once every 16
		 *      hclks." (through the “Clocking Configuration”
		 *      (“CLKCFG”) MCHBAR register)
		 */
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		return dev_priv->rawclk_freq / 16;
726 727 728 729 730 731 732 733 734 735
	} else if (INTEL_GEN(dev_priv) <= 8) {
		/* PRMs say:
		 *
		 *     "The PCU TSC counts 10ns increments; this timestamp
		 *      reflects bits 38:3 of the TSC (i.e. 80ns granularity,
		 *      rolling over every 1.5 hours).
		 */
		return f12_5_mhz;
	} else if (INTEL_GEN(dev_priv) <= 9) {
		u32 ctc_reg = I915_READ(CTC_MODE);
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736
		u32 freq = 0;
737 738 739 740 741 742 743 744 745 746 747 748 749 750 751

		if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
			freq = read_reference_ts_freq(dev_priv);
		} else {
			freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;

			/* Now figure out how the command stream's timestamp
			 * register increments from this frequency (it might
			 * increment only every few clock cycle).
			 */
			freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
				      CTC_SHIFT_PARAMETER_SHIFT);
		}

		return freq;
752
	} else if (INTEL_GEN(dev_priv) <= 12) {
753
		u32 ctc_reg = I915_READ(CTC_MODE);
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Lionel Landwerlin 已提交
754
		u32 freq = 0;
755 756 757 758 759 760 761 762 763

		/* First figure out the reference frequency. There are 2 ways
		 * we can compute the frequency, either through the
		 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
		 * tells us which one we should use.
		 */
		if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
			freq = read_reference_ts_freq(dev_priv);
		} else {
764 765 766 767 768 769 770 771
			u32 rpm_config_reg = I915_READ(RPM_CONFIG0);

			if (INTEL_GEN(dev_priv) <= 10)
				freq = gen10_get_crystal_clock_freq(dev_priv,
								rpm_config_reg);
			else
				freq = gen11_get_crystal_clock_freq(dev_priv,
								rpm_config_reg);
772

773 774 775 776 777 778 779 780
			/* Now figure out how the command stream's timestamp
			 * register increments from this frequency (it might
			 * increment only every few clock cycle).
			 */
			freq >>= 3 - ((rpm_config_reg &
				       GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
				      GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
		}
781 782 783 784

		return freq;
	}

785
	MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
786 787 788
	return 0;
}

789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809
#undef INTEL_VGA_DEVICE
#define INTEL_VGA_DEVICE(id, info) (id)

static const u16 subplatform_ult_ids[] = {
	INTEL_HSW_ULT_GT1_IDS(0),
	INTEL_HSW_ULT_GT2_IDS(0),
	INTEL_HSW_ULT_GT3_IDS(0),
	INTEL_BDW_ULT_GT1_IDS(0),
	INTEL_BDW_ULT_GT2_IDS(0),
	INTEL_BDW_ULT_GT3_IDS(0),
	INTEL_BDW_ULT_RSVD_IDS(0),
	INTEL_SKL_ULT_GT1_IDS(0),
	INTEL_SKL_ULT_GT2_IDS(0),
	INTEL_SKL_ULT_GT3_IDS(0),
	INTEL_KBL_ULT_GT1_IDS(0),
	INTEL_KBL_ULT_GT2_IDS(0),
	INTEL_KBL_ULT_GT3_IDS(0),
	INTEL_CFL_U_GT2_IDS(0),
	INTEL_CFL_U_GT3_IDS(0),
	INTEL_WHL_U_GT1_IDS(0),
	INTEL_WHL_U_GT2_IDS(0),
810
	INTEL_WHL_U_GT3_IDS(0),
811 812 813 814 815 816 817 818 819 820 821 822
};

static const u16 subplatform_ulx_ids[] = {
	INTEL_HSW_ULX_GT1_IDS(0),
	INTEL_HSW_ULX_GT2_IDS(0),
	INTEL_BDW_ULX_GT1_IDS(0),
	INTEL_BDW_ULX_GT2_IDS(0),
	INTEL_BDW_ULX_GT3_IDS(0),
	INTEL_BDW_ULX_RSVD_IDS(0),
	INTEL_SKL_ULX_GT1_IDS(0),
	INTEL_SKL_ULX_GT2_IDS(0),
	INTEL_KBL_ULX_GT1_IDS(0),
823
	INTEL_KBL_ULX_GT2_IDS(0),
824
	INTEL_AML_KBL_GT2_IDS(0),
825
	INTEL_AML_CFL_GT2_IDS(0),
826 827 828 829
};

static const u16 subplatform_portf_ids[] = {
	INTEL_CNL_PORT_F_IDS(0),
830
	INTEL_ICL_PORT_F_IDS(0),
831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849
};

static bool find_devid(u16 id, const u16 *p, unsigned int num)
{
	for (; num; num--, p++) {
		if (*p == id)
			return true;
	}

	return false;
}

void intel_device_info_subplatform_init(struct drm_i915_private *i915)
{
	const struct intel_device_info *info = INTEL_INFO(i915);
	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
	u16 devid = INTEL_DEVID(i915);
850
	u32 mask = 0;
851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875

	/* Make sure IS_<platform> checks are working. */
	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);

	/* Find and mark subplatform bits based on the PCI device id. */
	if (find_devid(devid, subplatform_ult_ids,
		       ARRAY_SIZE(subplatform_ult_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_ULT);
	} else if (find_devid(devid, subplatform_ulx_ids,
			      ARRAY_SIZE(subplatform_ulx_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_ULX);
		if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
			/* ULX machines are also considered ULT. */
			mask |= BIT(INTEL_SUBPLATFORM_ULT);
		}
	} else if (find_devid(devid, subplatform_portf_ids,
			      ARRAY_SIZE(subplatform_portf_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_PORTF);
	}

	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);

	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
}

876 877
/**
 * intel_device_info_runtime_init - initialize runtime info
878
 * @dev_priv: the i915 device
879
 *
880 881 882 883 884 885 886 887 888 889 890 891
 * Determine various intel_device_info fields at runtime.
 *
 * Use it when either:
 *   - it's judged too laborious to fill n static structures with the limit
 *     when a simple if statement does the job,
 *   - run-time checks (eg read fuse/strap registers) are needed.
 *
 * This function needs to be called:
 *   - after the MMIO has been setup as we are reading registers,
 *   - after the PCH has been detected,
 *   - before the first usage of the fields it can tweak.
 */
892
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
893
{
894
	struct intel_device_info *info = mkwrite_device_info(dev_priv);
895
	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
896 897
	enum pipe pipe;

898 899
	if (INTEL_GEN(dev_priv) >= 10) {
		for_each_pipe(dev_priv, pipe)
900
			runtime->num_scalers[pipe] = 2;
901
	} else if (IS_GEN(dev_priv, 9)) {
902 903 904
		runtime->num_scalers[PIPE_A] = 2;
		runtime->num_scalers[PIPE_B] = 2;
		runtime->num_scalers[PIPE_C] = 1;
905 906
	}

907
	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
908

909
	if (INTEL_GEN(dev_priv) >= 11)
910
		for_each_pipe(dev_priv, pipe)
911
			runtime->num_sprites[pipe] = 6;
912
	else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
913
		for_each_pipe(dev_priv, pipe)
914
			runtime->num_sprites[pipe] = 3;
915
	else if (IS_BROXTON(dev_priv)) {
916 917 918 919 920 921 922 923 924
		/*
		 * Skylake and Broxton currently don't expose the topmost plane as its
		 * use is exclusive with the legacy cursor and we only want to expose
		 * one of those, not both. Until we can safely expose the topmost plane
		 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
		 * we don't expose the topmost plane at all to prevent ABI breakage
		 * down the line.
		 */

925 926 927
		runtime->num_sprites[PIPE_A] = 2;
		runtime->num_sprites[PIPE_B] = 2;
		runtime->num_sprites[PIPE_C] = 1;
928
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
929
		for_each_pipe(dev_priv, pipe)
930
			runtime->num_sprites[pipe] = 2;
931
	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
932
		for_each_pipe(dev_priv, pipe)
933
			runtime->num_sprites[pipe] = 1;
934
	}
935

936 937
	if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) &&
	    HAS_PCH_SPLIT(dev_priv)) {
938 939 940 941 942 943 944 945 946 947 948 949 950 951
		u32 fuse_strap = I915_READ(FUSE_STRAP);
		u32 sfuse_strap = I915_READ(SFUSE_STRAP);

		/*
		 * SFUSE_STRAP is supposed to have a bit signalling the display
		 * is fused off. Unfortunately it seems that, at least in
		 * certain cases, fused off display means that PCH display
		 * reads don't land anywhere. In that case, we read 0s.
		 *
		 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
		 * should be set when taking over after the firmware.
		 */
		if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
		    sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
952
		    (HAS_PCH_CPT(dev_priv) &&
953 954
		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
			DRM_INFO("Display fused off, disabling\n");
955
			info->pipe_mask = 0;
956 957
		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
			DRM_INFO("PipeC fused off\n");
958
			info->pipe_mask &= ~BIT(PIPE_C);
959
		}
960
	} else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
961
		u32 dfsm = I915_READ(SKL_DFSM);
962
		u8 enabled_mask = info->pipe_mask;
963 964

		if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
965
			enabled_mask &= ~BIT(PIPE_A);
966
		if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
967
			enabled_mask &= ~BIT(PIPE_B);
968
		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
969
			enabled_mask &= ~BIT(PIPE_C);
970 971 972
		if (INTEL_GEN(dev_priv) >= 12 &&
		    (dfsm & TGL_DFSM_PIPE_D_DISABLE))
			enabled_mask &= ~BIT(PIPE_D);
973

974 975 976 977 978 979 980 981
		/*
		 * At least one pipe should be enabled and if there are
		 * disabled pipes, they should be the last ones, with no holes
		 * in the mask.
		 */
		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
			DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
				  enabled_mask);
982
		else
983
			info->pipe_mask = enabled_mask;
984 985 986

		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
			info->display.has_hdcp = 0;
987 988 989

		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
			info->display.has_fbc = 0;
990 991 992

		if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
			info->display.has_csr = 0;
993 994 995 996

		if (INTEL_GEN(dev_priv) >= 10 &&
		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
			info->display.has_dsc = 0;
997 998 999
	}

	/* Initialize slice/subslice/EU info */
1000 1001 1002
	if (IS_HASWELL(dev_priv))
		haswell_sseu_info_init(dev_priv);
	else if (IS_CHERRYVIEW(dev_priv))
1003 1004 1005
		cherryview_sseu_info_init(dev_priv);
	else if (IS_BROADWELL(dev_priv))
		broadwell_sseu_info_init(dev_priv);
1006
	else if (IS_GEN(dev_priv, 9))
1007
		gen9_sseu_info_init(dev_priv);
1008
	else if (IS_GEN(dev_priv, 10))
1009
		gen10_sseu_info_init(dev_priv);
1010
	else if (IS_GEN(dev_priv, 11))
1011
		gen11_sseu_info_init(dev_priv);
1012 1013
	else if (INTEL_GEN(dev_priv) >= 12)
		gen12_sseu_info_init(dev_priv);
1014

1015
	if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
1016
		DRM_INFO("Disabling ppGTT for VT-d support\n");
1017
		info->ppgtt_type = INTEL_PPGTT_NONE;
1018 1019
	}

1020
	/* Initialize command stream timestamp frequency */
1021
	runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
1022
}
1023 1024 1025 1026

void intel_driver_caps_print(const struct intel_driver_caps *caps,
			     struct drm_printer *p)
{
1027 1028
	drm_printf(p, "Has logical contexts? %s\n",
		   yesno(caps->has_logical_contexts));
1029 1030
	drm_printf(p, "scheduler: %x\n", caps->scheduler);
}
1031 1032 1033 1034 1035 1036 1037 1038 1039 1040

/*
 * Determine which engines are fused off in our particular hardware. Since the
 * fuse register is in the blitter powerwell, we need forcewake to be ready at
 * this point (but later we need to prune the forcewake domains for engines that
 * are indeed fused off).
 */
void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
{
	struct intel_device_info *info = mkwrite_device_info(dev_priv);
1041
	unsigned int logical_vdbox = 0;
1042
	unsigned int i;
1043
	u32 media_fuse;
1044 1045
	u16 vdbox_mask;
	u16 vebox_mask;
1046 1047 1048 1049

	if (INTEL_GEN(dev_priv) < 11)
		return;

1050
	media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
1051

1052 1053 1054
	vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
	vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
		      GEN11_GT_VEBOX_DISABLE_SHIFT;
1055 1056

	for (i = 0; i < I915_MAX_VCS; i++) {
1057 1058
		if (!HAS_ENGINE(dev_priv, _VCS(i))) {
			vdbox_mask &= ~BIT(i);
1059
			continue;
1060
		}
1061

1062
		if (!(BIT(i) & vdbox_mask)) {
1063
			info->engine_mask &= ~BIT(_VCS(i));
1064
			DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
1065
			continue;
1066
		}
1067 1068 1069 1070

		/*
		 * In Gen11, only even numbered logical VDBOXes are
		 * hooked up to an SFC (Scaler & Format Converter) unit.
1071
		 * In TGL each VDBOX has access to an SFC.
1072
		 */
1073
		if (IS_TIGERLAKE(dev_priv) || logical_vdbox++ % 2 == 0)
1074
			RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
1075
	}
1076 1077 1078
	DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n",
			 vdbox_mask, VDBOX_MASK(dev_priv));
	GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv));
1079 1080

	for (i = 0; i < I915_MAX_VECS; i++) {
1081 1082
		if (!HAS_ENGINE(dev_priv, _VECS(i))) {
			vebox_mask &= ~BIT(i);
1083
			continue;
1084
		}
1085

1086
		if (!(BIT(i) & vebox_mask)) {
1087
			info->engine_mask &= ~BIT(_VECS(i));
1088 1089
			DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
		}
1090
	}
1091 1092 1093
	DRM_DEBUG_DRIVER("vebox enable: %04x, instances: %04lx\n",
			 vebox_mask, VEBOX_MASK(dev_priv));
	GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv));
1094
}