i915_debugfs.c 152.0 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/seq_file.h>
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#include <linux/circ_buf.h>
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#include <linux/ctype.h>
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#include <linux/debugfs.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/list_sort.h>
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#include <asm/msr-index.h>
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include "intel_ringbuffer.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

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static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
	return to_i915(node->minor->dev);
}

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/* As the drm_debugfs_init() routines are called before dev->dev_private is
 * allocated we need to hook into the minor for release. */
static int
drm_add_fake_info_node(struct drm_minor *minor,
		       struct dentry *ent,
		       const void *key)
{
	struct drm_info_node *node;

	node = kmalloc(sizeof(*node), GFP_KERNEL);
	if (node == NULL) {
		debugfs_remove(ent);
		return -ENOMEM;
	}

	node->minor = minor;
	node->dent = ent;
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	node->info_ent = (void *)key;
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	mutex_lock(&minor->debugfs_lock);
	list_add(&node->list, &minor->debugfs_list);
	mutex_unlock(&minor->debugfs_lock);

	return 0;
}

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static int i915_capabilities(struct seq_file *m, void *data)
{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	const struct intel_device_info *info = INTEL_INFO(dev_priv);
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	seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
	seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
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#define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
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	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
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#undef PRINT_FLAG
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	return 0;
}
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static char get_active_flag(struct drm_i915_gem_object *obj)
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{
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	return i915_gem_object_is_active(obj) ? '*' : ' ';
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}

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static char get_pin_flag(struct drm_i915_gem_object *obj)
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{
	return obj->pin_display ? 'p' : ' ';
}

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static char get_tiling_flag(struct drm_i915_gem_object *obj)
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{
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	switch (i915_gem_object_get_tiling(obj)) {
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	default:
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	case I915_TILING_NONE: return ' ';
	case I915_TILING_X: return 'X';
	case I915_TILING_Y: return 'Y';
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	}
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}

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static char get_global_flag(struct drm_i915_gem_object *obj)
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{
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	return !list_empty(&obj->userfault_link) ? 'g' : ' ';
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}

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static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
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{
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	return obj->mm.mapping ? 'M' : ' ';
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}

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static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
{
	u64 size = 0;
	struct i915_vma *vma;

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	list_for_each_entry(vma, &obj->vma_list, obj_link) {
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		if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
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			size += vma->node.size;
	}

	return size;
}

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static void
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
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	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
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	struct intel_engine_cs *engine;
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	struct i915_vma *vma;
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	unsigned int frontbuffer_bits;
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	int pin_count = 0;

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	lockdep_assert_held(&obj->base.dev->struct_mutex);

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	seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
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		   &obj->base,
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		   get_active_flag(obj),
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		   get_pin_flag(obj),
		   get_tiling_flag(obj),
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		   get_global_flag(obj),
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		   get_pin_mapped_flag(obj),
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		   obj->base.size / 1024,
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		   obj->base.read_domains,
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		   obj->base.write_domain,
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		   i915_cache_level_str(dev_priv, obj->cache_level),
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		   obj->mm.dirty ? " dirty" : "",
		   obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
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	if (obj->base.name)
		seq_printf(m, " (name: %d)", obj->base.name);
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	list_for_each_entry(vma, &obj->vma_list, obj_link) {
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		if (i915_vma_is_pinned(vma))
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			pin_count++;
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	}
	seq_printf(m, " (pinned x %d)", pin_count);
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	if (obj->pin_display)
		seq_printf(m, " (display)");
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	list_for_each_entry(vma, &obj->vma_list, obj_link) {
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		if (!drm_mm_node_allocated(&vma->node))
			continue;

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		seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
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			   i915_vma_is_ggtt(vma) ? "g" : "pp",
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			   vma->node.start, vma->node.size);
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		if (i915_vma_is_ggtt(vma))
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			seq_printf(m, ", type: %u", vma->ggtt_view.type);
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		if (vma->fence)
			seq_printf(m, " , fence: %d%s",
				   vma->fence->id,
				   i915_gem_active_isset(&vma->last_fence) ? "*" : "");
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		seq_puts(m, ")");
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	}
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	if (obj->stolen)
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		seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
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	engine = i915_gem_object_last_write_engine(obj);
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	if (engine)
		seq_printf(m, " (%s)", engine->name);

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	frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
	if (frontbuffer_bits)
		seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
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}

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static int obj_rank_by_stolen(void *priv,
			      struct list_head *A, struct list_head *B)
{
	struct drm_i915_gem_object *a =
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		container_of(A, struct drm_i915_gem_object, obj_exec_link);
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	struct drm_i915_gem_object *b =
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		container_of(B, struct drm_i915_gem_object, obj_exec_link);
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	if (a->stolen->start < b->stolen->start)
		return -1;
	if (a->stolen->start > b->stolen->start)
		return 1;
	return 0;
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}

static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
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	struct drm_i915_gem_object *obj;
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	u64 total_obj_size, total_gtt_size;
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	LIST_HEAD(stolen);
	int count, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	total_obj_size = total_gtt_size = count = 0;
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	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
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		if (obj->stolen == NULL)
			continue;

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		list_add(&obj->obj_exec_link, &stolen);
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		total_obj_size += obj->base.size;
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		total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
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		count++;
	}
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	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
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		if (obj->stolen == NULL)
			continue;

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		list_add(&obj->obj_exec_link, &stolen);
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		total_obj_size += obj->base.size;
		count++;
	}
	list_sort(NULL, &stolen, obj_rank_by_stolen);
	seq_puts(m, "Stolen:\n");
	while (!list_empty(&stolen)) {
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		obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
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		seq_puts(m, "   ");
		describe_obj(m, obj);
		seq_putc(m, '\n');
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		list_del_init(&obj->obj_exec_link);
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	}
	mutex_unlock(&dev->struct_mutex);

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	seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
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		   count, total_obj_size, total_gtt_size);
	return 0;
}

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struct file_stats {
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	struct drm_i915_file_private *file_priv;
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	unsigned long count;
	u64 total, unbound;
	u64 global, shared;
	u64 active, inactive;
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};

static int per_file_stats(int id, void *ptr, void *data)
{
	struct drm_i915_gem_object *obj = ptr;
	struct file_stats *stats = data;
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	struct i915_vma *vma;
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	stats->count++;
	stats->total += obj->base.size;
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	if (!obj->bind_count)
		stats->unbound += obj->base.size;
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	if (obj->base.name || obj->base.dma_buf)
		stats->shared += obj->base.size;

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	list_for_each_entry(vma, &obj->vma_list, obj_link) {
		if (!drm_mm_node_allocated(&vma->node))
			continue;
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		if (i915_vma_is_ggtt(vma)) {
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			stats->global += vma->node.size;
		} else {
			struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
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			if (ppgtt->base.file != stats->file_priv)
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				continue;
		}
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		if (i915_vma_is_active(vma))
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			stats->active += vma->node.size;
		else
			stats->inactive += vma->node.size;
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	}

	return 0;
}

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#define print_file_stats(m, name, stats) do { \
	if (stats.count) \
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		seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
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			   name, \
			   stats.count, \
			   stats.total, \
			   stats.active, \
			   stats.inactive, \
			   stats.global, \
			   stats.shared, \
			   stats.unbound); \
} while (0)
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static void print_batch_pool_stats(struct seq_file *m,
				   struct drm_i915_private *dev_priv)
{
	struct drm_i915_gem_object *obj;
	struct file_stats stats;
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	struct intel_engine_cs *engine;
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	enum intel_engine_id id;
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	int j;
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	memset(&stats, 0, sizeof(stats));

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	for_each_engine(engine, dev_priv, id) {
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		for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
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			list_for_each_entry(obj,
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					    &engine->batch_pool.cache_list[j],
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					    batch_pool_link)
				per_file_stats(0, obj, &stats);
		}
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	}
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	print_file_stats(m, "[k]batch pool", stats);
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}

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static int per_file_ctx_stats(int id, void *ptr, void *data)
{
	struct i915_gem_context *ctx = ptr;
	int n;

	for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
		if (ctx->engine[n].state)
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			per_file_stats(0, ctx->engine[n].state->obj, data);
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		if (ctx->engine[n].ring)
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			per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
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	}

	return 0;
}

static void print_context_stats(struct seq_file *m,
				struct drm_i915_private *dev_priv)
{
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	struct drm_device *dev = &dev_priv->drm;
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	struct file_stats stats;
	struct drm_file *file;

	memset(&stats, 0, sizeof(stats));

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	mutex_lock(&dev->struct_mutex);
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	if (dev_priv->kernel_context)
		per_file_ctx_stats(0, dev_priv->kernel_context, &stats);

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	list_for_each_entry(file, &dev->filelist, lhead) {
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		struct drm_i915_file_private *fpriv = file->driver_priv;
		idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
	}
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	mutex_unlock(&dev->struct_mutex);
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	print_file_stats(m, "[k]contexts", stats);
}

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static int i915_gem_object_info(struct seq_file *m, void *data)
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{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
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	struct i915_ggtt *ggtt = &dev_priv->ggtt;
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	u32 count, mapped_count, purgeable_count, dpy_count;
	u64 size, mapped_size, purgeable_size, dpy_size;
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	struct drm_i915_gem_object *obj;
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	struct drm_file *file;
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	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

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	seq_printf(m, "%u objects, %llu bytes\n",
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		   dev_priv->mm.object_count,
		   dev_priv->mm.object_memory);

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	size = count = 0;
	mapped_size = mapped_count = 0;
	purgeable_size = purgeable_count = 0;
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	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
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		size += obj->base.size;
		++count;

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		if (obj->mm.madv == I915_MADV_DONTNEED) {
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			purgeable_size += obj->base.size;
			++purgeable_count;
		}

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		if (obj->mm.mapping) {
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			mapped_count++;
			mapped_size += obj->base.size;
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		}
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	}
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	seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
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	size = count = dpy_size = dpy_count = 0;
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	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
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		size += obj->base.size;
		++count;

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		if (obj->pin_display) {
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			dpy_size += obj->base.size;
			++dpy_count;
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		}
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		if (obj->mm.madv == I915_MADV_DONTNEED) {
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			purgeable_size += obj->base.size;
			++purgeable_count;
		}
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		if (obj->mm.mapping) {
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			mapped_count++;
			mapped_size += obj->base.size;
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		}
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	}
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	seq_printf(m, "%u bound objects, %llu bytes\n",
		   count, size);
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	seq_printf(m, "%u purgeable objects, %llu bytes\n",
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		   purgeable_count, purgeable_size);
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	seq_printf(m, "%u mapped objects, %llu bytes\n",
		   mapped_count, mapped_size);
	seq_printf(m, "%u display objects (pinned), %llu bytes\n",
		   dpy_count, dpy_size);
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	seq_printf(m, "%llu [%llu] gtt total\n",
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		   ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
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	seq_putc(m, '\n');
	print_batch_pool_stats(m, dev_priv);
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	mutex_unlock(&dev->struct_mutex);

	mutex_lock(&dev->filelist_mutex);
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	print_context_stats(m, dev_priv);
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	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct file_stats stats;
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		struct drm_i915_file_private *file_priv = file->driver_priv;
		struct drm_i915_gem_request *request;
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		struct task_struct *task;
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		memset(&stats, 0, sizeof(stats));
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		stats.file_priv = file->driver_priv;
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		spin_lock(&file->table_lock);
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		idr_for_each(&file->object_idr, per_file_stats, &stats);
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		spin_unlock(&file->table_lock);
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		/*
		 * Although we have a valid reference on file->pid, that does
		 * not guarantee that the task_struct who called get_pid() is
		 * still alive (e.g. get_pid(current) => fork() => exit()).
		 * Therefore, we need to protect this ->comm access using RCU.
		 */
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		mutex_lock(&dev->struct_mutex);
		request = list_first_entry_or_null(&file_priv->mm.request_list,
						   struct drm_i915_gem_request,
						   client_list);
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		rcu_read_lock();
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		task = pid_task(request && request->ctx->pid ?
				request->ctx->pid : file->pid,
				PIDTYPE_PID);
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		print_file_stats(m, task ? task->comm : "<unknown>", stats);
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		rcu_read_unlock();
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		mutex_unlock(&dev->struct_mutex);
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	}
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	mutex_unlock(&dev->filelist_mutex);
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	return 0;
}

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static int i915_gem_gtt_info(struct seq_file *m, void *data)
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{
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	struct drm_info_node *node = m->private;
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	struct drm_i915_private *dev_priv = node_to_i915(node);
	struct drm_device *dev = &dev_priv->drm;
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	bool show_pin_display_only = !!node->info_ent->data;
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	struct drm_i915_gem_object *obj;
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	u64 total_obj_size, total_gtt_size;
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	int count, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	total_obj_size = total_gtt_size = count = 0;
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	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
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		if (show_pin_display_only && !obj->pin_display)
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			continue;

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		seq_puts(m, "   ");
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		describe_obj(m, obj);
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		seq_putc(m, '\n');
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		total_obj_size += obj->base.size;
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		total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
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		count++;
	}

	mutex_unlock(&dev->struct_mutex);

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	seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
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		   count, total_obj_size, total_gtt_size);

	return 0;
}

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static int i915_gem_pageflip_info(struct seq_file *m, void *data)
{
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	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
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	struct intel_crtc *crtc;
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	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
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	for_each_intel_crtc(dev, crtc) {
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		const char pipe = pipe_name(crtc->pipe);
		const char plane = plane_name(crtc->plane);
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		struct intel_flip_work *work;
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		spin_lock_irq(&dev->event_lock);
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		work = crtc->flip_work;
		if (work == NULL) {
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			seq_printf(m, "No flip due on pipe %c (plane %c)\n",
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				   pipe, plane);
		} else {
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			u32 pending;
			u32 addr;

			pending = atomic_read(&work->pending);
			if (pending) {
				seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
					   pipe, plane);
			} else {
				seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
					   pipe, plane);
			}
			if (work->flip_queued_req) {
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				struct intel_engine_cs *engine = work->flip_queued_req->engine;
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				seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
					   engine->name,
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					   work->flip_queued_req->global_seqno,
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					   atomic_read(&dev_priv->gt.global_timeline.next_seqno),
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					   intel_engine_get_seqno(engine),
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					   i915_gem_request_completed(work->flip_queued_req));
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			} else
				seq_printf(m, "Flip not associated with any ring\n");
			seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
				   work->flip_queued_vblank,
				   work->flip_ready_vblank,
				   intel_crtc_get_vblank_counter(crtc));
			seq_printf(m, "%d prepares\n", atomic_read(&work->pending));

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			if (INTEL_GEN(dev_priv) >= 4)
567 568 569 570 571 572 573 574
				addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
			else
				addr = I915_READ(DSPADDR(crtc->plane));
			seq_printf(m, "Current scanout address 0x%08x\n", addr);

			if (work->pending_flip_obj) {
				seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
				seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
575 576
			}
		}
577
		spin_unlock_irq(&dev->event_lock);
578 579
	}

580 581
	mutex_unlock(&dev->struct_mutex);

582 583 584
	return 0;
}

585 586
static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
{
587 588
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
589
	struct drm_i915_gem_object *obj;
590
	struct intel_engine_cs *engine;
591
	enum intel_engine_id id;
592
	int total = 0;
593
	int ret, j;
594 595 596 597 598

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

599
	for_each_engine(engine, dev_priv, id) {
600
		for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
601 602 603 604
			int count;

			count = 0;
			list_for_each_entry(obj,
605
					    &engine->batch_pool.cache_list[j],
606 607 608
					    batch_pool_link)
				count++;
			seq_printf(m, "%s cache[%d]: %d objects\n",
609
				   engine->name, j, count);
610 611

			list_for_each_entry(obj,
612
					    &engine->batch_pool.cache_list[j],
613 614 615 616 617 618 619
					    batch_pool_link) {
				seq_puts(m, "   ");
				describe_obj(m, obj);
				seq_putc(m, '\n');
			}

			total += count;
620
		}
621 622
	}

623
	seq_printf(m, "total: %d\n", total);
624 625 626 627 628 629

	mutex_unlock(&dev->struct_mutex);

	return 0;
}

630 631 632 633
static void print_request(struct seq_file *m,
			  struct drm_i915_gem_request *rq,
			  const char *prefix)
{
634
	seq_printf(m, "%s%x [%x:%x] @ %d: %s\n", prefix,
635
		   rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
636
		   jiffies_to_msecs(jiffies - rq->emitted_jiffies),
637
		   rq->timeline->common->name);
638 639
}

640 641
static int i915_gem_request_info(struct seq_file *m, void *data)
{
642 643
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
D
Daniel Vetter 已提交
644
	struct drm_i915_gem_request *req;
645 646
	struct intel_engine_cs *engine;
	enum intel_engine_id id;
647
	int ret, any;
648 649 650 651

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
652

653
	any = 0;
654
	for_each_engine(engine, dev_priv, id) {
655 656 657
		int count;

		count = 0;
658
		list_for_each_entry(req, &engine->timeline->requests, link)
659 660
			count++;
		if (count == 0)
661 662
			continue;

663
		seq_printf(m, "%s requests: %d\n", engine->name, count);
664
		list_for_each_entry(req, &engine->timeline->requests, link)
665
			print_request(m, req, "    ");
666 667

		any++;
668
	}
669 670
	mutex_unlock(&dev->struct_mutex);

671
	if (any == 0)
672
		seq_puts(m, "No requests\n");
673

674 675 676
	return 0;
}

677
static void i915_ring_seqno_info(struct seq_file *m,
678
				 struct intel_engine_cs *engine)
679
{
680 681 682
	struct intel_breadcrumbs *b = &engine->breadcrumbs;
	struct rb_node *rb;

683
	seq_printf(m, "Current sequence (%s): %x\n",
684
		   engine->name, intel_engine_get_seqno(engine));
685

686
	spin_lock_irq(&b->lock);
687 688 689 690 691 692
	for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
		struct intel_wait *w = container_of(rb, typeof(*w), node);

		seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
			   engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
	}
693
	spin_unlock_irq(&b->lock);
694 695
}

696 697
static int i915_gem_seqno_info(struct seq_file *m, void *data)
{
698
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
699
	struct intel_engine_cs *engine;
700
	enum intel_engine_id id;
701

702
	for_each_engine(engine, dev_priv, id)
703
		i915_ring_seqno_info(m, engine);
704

705 706 707 708 709 710
	return 0;
}


static int i915_interrupt_info(struct seq_file *m, void *data)
{
711
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
712
	struct intel_engine_cs *engine;
713
	enum intel_engine_id id;
714
	int i, pipe;
715

716
	intel_runtime_pm_get(dev_priv);
717

718
	if (IS_CHERRYVIEW(dev_priv)) {
719 720 721 722 723 724 725 726 727 728 729
		seq_printf(m, "Master Interrupt Control:\t%08x\n",
			   I915_READ(GEN8_MASTER_IRQ));

		seq_printf(m, "Display IER:\t%08x\n",
			   I915_READ(VLV_IER));
		seq_printf(m, "Display IIR:\t%08x\n",
			   I915_READ(VLV_IIR));
		seq_printf(m, "Display IIR_RW:\t%08x\n",
			   I915_READ(VLV_IIR_RW));
		seq_printf(m, "Display IMR:\t%08x\n",
			   I915_READ(VLV_IMR));
730 731 732 733 734 735 736 737 738 739 740
		for_each_pipe(dev_priv, pipe) {
			enum intel_display_power_domain power_domain;

			power_domain = POWER_DOMAIN_PIPE(pipe);
			if (!intel_display_power_get_if_enabled(dev_priv,
								power_domain)) {
				seq_printf(m, "Pipe %c power disabled\n",
					   pipe_name(pipe));
				continue;
			}

741 742 743 744
			seq_printf(m, "Pipe %c stat:\t%08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));

745 746 747 748
			intel_display_power_put(dev_priv, power_domain);
		}

		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
749 750 751 752 753 754
		seq_printf(m, "Port hotplug:\t%08x\n",
			   I915_READ(PORT_HOTPLUG_EN));
		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
			   I915_READ(VLV_DPFLIPSTAT));
		seq_printf(m, "DPINVGTT:\t%08x\n",
			   I915_READ(DPINVGTT));
755
		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771

		for (i = 0; i < 4; i++) {
			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IMR(i)));
			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IIR(i)));
			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IER(i)));
		}

		seq_printf(m, "PCU interrupt mask:\t%08x\n",
			   I915_READ(GEN8_PCU_IMR));
		seq_printf(m, "PCU interrupt identity:\t%08x\n",
			   I915_READ(GEN8_PCU_IIR));
		seq_printf(m, "PCU interrupt enable:\t%08x\n",
			   I915_READ(GEN8_PCU_IER));
772
	} else if (INTEL_GEN(dev_priv) >= 8) {
773 774 775 776 777 778 779 780 781 782 783 784
		seq_printf(m, "Master Interrupt Control:\t%08x\n",
			   I915_READ(GEN8_MASTER_IRQ));

		for (i = 0; i < 4; i++) {
			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IMR(i)));
			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IIR(i)));
			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IER(i)));
		}

785
		for_each_pipe(dev_priv, pipe) {
786 787 788 789 790
			enum intel_display_power_domain power_domain;

			power_domain = POWER_DOMAIN_PIPE(pipe);
			if (!intel_display_power_get_if_enabled(dev_priv,
								power_domain)) {
791 792 793 794
				seq_printf(m, "Pipe %c power disabled\n",
					   pipe_name(pipe));
				continue;
			}
795
			seq_printf(m, "Pipe %c IMR:\t%08x\n",
796 797
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
798
			seq_printf(m, "Pipe %c IIR:\t%08x\n",
799 800
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
801
			seq_printf(m, "Pipe %c IER:\t%08x\n",
802 803
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IER(pipe)));
804 805

			intel_display_power_put(dev_priv, power_domain);
806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827
		}

		seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IMR));
		seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IIR));
		seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IER));

		seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IMR));
		seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IIR));
		seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IER));

		seq_printf(m, "PCU interrupt mask:\t%08x\n",
			   I915_READ(GEN8_PCU_IMR));
		seq_printf(m, "PCU interrupt identity:\t%08x\n",
			   I915_READ(GEN8_PCU_IIR));
		seq_printf(m, "PCU interrupt enable:\t%08x\n",
			   I915_READ(GEN8_PCU_IER));
828
	} else if (IS_VALLEYVIEW(dev_priv)) {
J
Jesse Barnes 已提交
829 830 831 832 833 834 835 836
		seq_printf(m, "Display IER:\t%08x\n",
			   I915_READ(VLV_IER));
		seq_printf(m, "Display IIR:\t%08x\n",
			   I915_READ(VLV_IIR));
		seq_printf(m, "Display IIR_RW:\t%08x\n",
			   I915_READ(VLV_IIR_RW));
		seq_printf(m, "Display IMR:\t%08x\n",
			   I915_READ(VLV_IMR));
837
		for_each_pipe(dev_priv, pipe)
J
Jesse Barnes 已提交
838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865
			seq_printf(m, "Pipe %c stat:\t%08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));

		seq_printf(m, "Master IER:\t%08x\n",
			   I915_READ(VLV_MASTER_IER));

		seq_printf(m, "Render IER:\t%08x\n",
			   I915_READ(GTIER));
		seq_printf(m, "Render IIR:\t%08x\n",
			   I915_READ(GTIIR));
		seq_printf(m, "Render IMR:\t%08x\n",
			   I915_READ(GTIMR));

		seq_printf(m, "PM IER:\t\t%08x\n",
			   I915_READ(GEN6_PMIER));
		seq_printf(m, "PM IIR:\t\t%08x\n",
			   I915_READ(GEN6_PMIIR));
		seq_printf(m, "PM IMR:\t\t%08x\n",
			   I915_READ(GEN6_PMIMR));

		seq_printf(m, "Port hotplug:\t%08x\n",
			   I915_READ(PORT_HOTPLUG_EN));
		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
			   I915_READ(VLV_DPFLIPSTAT));
		seq_printf(m, "DPINVGTT:\t%08x\n",
			   I915_READ(DPINVGTT));

866
	} else if (!HAS_PCH_SPLIT(dev_priv)) {
867 868 869 870 871 872
		seq_printf(m, "Interrupt enable:    %08x\n",
			   I915_READ(IER));
		seq_printf(m, "Interrupt identity:  %08x\n",
			   I915_READ(IIR));
		seq_printf(m, "Interrupt mask:      %08x\n",
			   I915_READ(IMR));
873
		for_each_pipe(dev_priv, pipe)
874 875 876
			seq_printf(m, "Pipe %c stat:         %08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));
877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896
	} else {
		seq_printf(m, "North Display Interrupt enable:		%08x\n",
			   I915_READ(DEIER));
		seq_printf(m, "North Display Interrupt identity:	%08x\n",
			   I915_READ(DEIIR));
		seq_printf(m, "North Display Interrupt mask:		%08x\n",
			   I915_READ(DEIMR));
		seq_printf(m, "South Display Interrupt enable:		%08x\n",
			   I915_READ(SDEIER));
		seq_printf(m, "South Display Interrupt identity:	%08x\n",
			   I915_READ(SDEIIR));
		seq_printf(m, "South Display Interrupt mask:		%08x\n",
			   I915_READ(SDEIMR));
		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
			   I915_READ(GTIER));
		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
			   I915_READ(GTIIR));
		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
			   I915_READ(GTIMR));
	}
897
	for_each_engine(engine, dev_priv, id) {
898
		if (INTEL_GEN(dev_priv) >= 6) {
899 900
			seq_printf(m,
				   "Graphics Interrupt mask (%s):	%08x\n",
901
				   engine->name, I915_READ_IMR(engine));
902
		}
903
		i915_ring_seqno_info(m, engine);
904
	}
905
	intel_runtime_pm_put(dev_priv);
906

907 908 909
	return 0;
}

910 911
static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
{
912 913
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
914 915 916 917 918
	int i, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
919 920 921

	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
	for (i = 0; i < dev_priv->num_fence_regs; i++) {
922
		struct i915_vma *vma = dev_priv->fence_regs[i].vma;
923

C
Chris Wilson 已提交
924 925
		seq_printf(m, "Fence %d, pin count = %d, object = ",
			   i, dev_priv->fence_regs[i].pin_count);
926
		if (!vma)
927
			seq_puts(m, "unused");
928
		else
929
			describe_obj(m, vma->obj);
930
		seq_putc(m, '\n');
931 932
	}

933
	mutex_unlock(&dev->struct_mutex);
934 935 936
	return 0;
}

937 938
static int i915_hws_info(struct seq_file *m, void *data)
{
939
	struct drm_info_node *node = m->private;
940
	struct drm_i915_private *dev_priv = node_to_i915(node);
941
	struct intel_engine_cs *engine;
D
Daniel Vetter 已提交
942
	const u32 *hws;
943 944
	int i;

945
	engine = dev_priv->engine[(uintptr_t)node->info_ent->data];
946
	hws = engine->status_page.page_addr;
947 948 949 950 951 952 953 954 955 956 957
	if (hws == NULL)
		return 0;

	for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
		seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
			   i * 4,
			   hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
	}
	return 0;
}

958 959
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

960 961 962 963 964 965
static ssize_t
i915_error_state_write(struct file *filp,
		       const char __user *ubuf,
		       size_t cnt,
		       loff_t *ppos)
{
966
	struct i915_error_state_file_priv *error_priv = filp->private_data;
967 968

	DRM_DEBUG_DRIVER("Resetting error state\n");
969
	i915_destroy_error_state(error_priv->dev);
970 971 972 973 974 975

	return cnt;
}

static int i915_error_state_open(struct inode *inode, struct file *file)
{
976
	struct drm_i915_private *dev_priv = inode->i_private;
977 978 979 980 981 982
	struct i915_error_state_file_priv *error_priv;

	error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
	if (!error_priv)
		return -ENOMEM;

983
	error_priv->dev = &dev_priv->drm;
984

985
	i915_error_state_get(&dev_priv->drm, error_priv);
986

987 988 989
	file->private_data = error_priv;

	return 0;
990 991 992 993
}

static int i915_error_state_release(struct inode *inode, struct file *file)
{
994
	struct i915_error_state_file_priv *error_priv = file->private_data;
995

996
	i915_error_state_put(error_priv);
997 998
	kfree(error_priv);

999 1000 1001
	return 0;
}

1002 1003 1004 1005 1006 1007 1008 1009 1010
static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
				     size_t count, loff_t *pos)
{
	struct i915_error_state_file_priv *error_priv = file->private_data;
	struct drm_i915_error_state_buf error_str;
	loff_t tmp_pos = 0;
	ssize_t ret_count = 0;
	int ret;

1011 1012
	ret = i915_error_state_buf_init(&error_str,
					to_i915(error_priv->dev), count, *pos);
1013 1014
	if (ret)
		return ret;
1015

1016
	ret = i915_error_state_to_str(&error_str, error_priv);
1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028
	if (ret)
		goto out;

	ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
					    error_str.buf,
					    error_str.bytes);

	if (ret_count < 0)
		ret = ret_count;
	else
		*pos = error_str.start + ret_count;
out:
1029
	i915_error_state_buf_release(&error_str);
1030
	return ret ?: ret_count;
1031 1032 1033 1034 1035
}

static const struct file_operations i915_error_state_fops = {
	.owner = THIS_MODULE,
	.open = i915_error_state_open,
1036
	.read = i915_error_state_read,
1037 1038 1039 1040 1041
	.write = i915_error_state_write,
	.llseek = default_llseek,
	.release = i915_error_state_release,
};

1042 1043
#endif

1044 1045
static int
i915_next_seqno_get(void *data, u64 *val)
1046
{
1047
	struct drm_i915_private *dev_priv = data;
1048

1049
	*val = atomic_read(&dev_priv->gt.global_timeline.next_seqno);
1050
	return 0;
1051 1052
}

1053 1054 1055
static int
i915_next_seqno_set(void *data, u64 val)
{
1056 1057
	struct drm_i915_private *dev_priv = data;
	struct drm_device *dev = &dev_priv->drm;
1058 1059 1060 1061 1062 1063
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

1064
	ret = i915_gem_set_global_seqno(dev, val);
1065 1066
	mutex_unlock(&dev->struct_mutex);

1067
	return ret;
1068 1069
}

1070 1071
DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
			i915_next_seqno_get, i915_next_seqno_set,
1072
			"0x%llx\n");
1073

1074
static int i915_frequency_info(struct seq_file *m, void *unused)
1075
{
1076 1077
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1078 1079 1080
	int ret = 0;

	intel_runtime_pm_get(dev_priv);
1081

1082
	if (IS_GEN5(dev_priv)) {
1083 1084 1085 1086 1087 1088 1089 1090 1091
		u16 rgvswctl = I915_READ16(MEMSWCTL);
		u16 rgvstat = I915_READ16(MEMSTAT_ILK);

		seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
		seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
		seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
			   MEMSTAT_VID_SHIFT);
		seq_printf(m, "Current P-state: %d\n",
			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1092
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118
		u32 freq_sts;

		mutex_lock(&dev_priv->rps.hw_lock);
		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);

		seq_printf(m, "actual GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));

		seq_printf(m, "current GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));

		seq_printf(m, "max GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));

		seq_printf(m, "min GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));

		seq_printf(m, "idle GPU freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));

		seq_printf(m,
			   "efficient (RPe) frequency: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
		mutex_unlock(&dev_priv->rps.hw_lock);
1119
	} else if (INTEL_GEN(dev_priv) >= 6) {
1120 1121 1122
		u32 rp_state_limits;
		u32 gt_perf_status;
		u32 rp_state_cap;
1123
		u32 rpmodectl, rpinclimit, rpdeclimit;
1124
		u32 rpstat, cagf, reqf;
1125 1126
		u32 rpupei, rpcurup, rpprevup;
		u32 rpdownei, rpcurdown, rpprevdown;
1127
		u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1128 1129
		int max_freq;

1130
		rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1131
		if (IS_BROXTON(dev_priv)) {
1132 1133 1134 1135 1136 1137 1138
			rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
			gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
		} else {
			rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
			gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
		}

1139
		/* RPSTAT1 is in the GT power well */
1140 1141
		ret = mutex_lock_interruptible(&dev->struct_mutex);
		if (ret)
1142
			goto out;
1143

1144
		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1145

1146
		reqf = I915_READ(GEN6_RPNSWREQ);
1147
		if (IS_GEN9(dev_priv))
1148 1149 1150
			reqf >>= 23;
		else {
			reqf &= ~GEN6_TURBO_DISABLE;
1151
			if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1152 1153 1154 1155
				reqf >>= 24;
			else
				reqf >>= 25;
		}
1156
		reqf = intel_gpu_freq(dev_priv, reqf);
1157

1158 1159 1160 1161
		rpmodectl = I915_READ(GEN6_RP_CONTROL);
		rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
		rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);

1162
		rpstat = I915_READ(GEN6_RPSTAT1);
1163 1164 1165 1166 1167 1168
		rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
		rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
		rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1169
		if (IS_GEN9(dev_priv))
1170
			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1171
		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
B
Ben Widawsky 已提交
1172 1173 1174
			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
		else
			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1175
		cagf = intel_gpu_freq(dev_priv, cagf);
1176

1177
		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1178 1179
		mutex_unlock(&dev->struct_mutex);

1180
		if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192
			pm_ier = I915_READ(GEN6_PMIER);
			pm_imr = I915_READ(GEN6_PMIMR);
			pm_isr = I915_READ(GEN6_PMISR);
			pm_iir = I915_READ(GEN6_PMIIR);
			pm_mask = I915_READ(GEN6_PMINTRMSK);
		} else {
			pm_ier = I915_READ(GEN8_GT_IER(2));
			pm_imr = I915_READ(GEN8_GT_IMR(2));
			pm_isr = I915_READ(GEN8_GT_ISR(2));
			pm_iir = I915_READ(GEN8_GT_IIR(2));
			pm_mask = I915_READ(GEN6_PMINTRMSK);
		}
1193
		seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1194
			   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1195
		seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1196 1197
		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
		seq_printf(m, "Render p-state ratio: %d\n",
1198
			   (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1199 1200 1201 1202
		seq_printf(m, "Render p-state VID: %d\n",
			   gt_perf_status & 0xff);
		seq_printf(m, "Render p-state limit: %d\n",
			   rp_state_limits & 0xff);
1203 1204 1205 1206
		seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
		seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
		seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
		seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1207
		seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
B
Ben Widawsky 已提交
1208
		seq_printf(m, "CAGF: %dMHz\n", cagf);
1209 1210 1211 1212 1213 1214
		seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
			   rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
		seq_printf(m, "RP CUR UP: %d (%dus)\n",
			   rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
		seq_printf(m, "RP PREV UP: %d (%dus)\n",
			   rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1215 1216 1217
		seq_printf(m, "Up threshold: %d%%\n",
			   dev_priv->rps.up_threshold);

1218 1219 1220 1221 1222 1223
		seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
			   rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
		seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
			   rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
		seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
			   rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1224 1225
		seq_printf(m, "Down threshold: %d%%\n",
			   dev_priv->rps.down_threshold);
1226

1227
		max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1228
			    rp_state_cap >> 16) & 0xff;
1229
		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1230
			     GEN9_FREQ_SCALER : 1);
1231
		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1232
			   intel_gpu_freq(dev_priv, max_freq));
1233 1234

		max_freq = (rp_state_cap & 0xff00) >> 8;
1235
		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1236
			     GEN9_FREQ_SCALER : 1);
1237
		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1238
			   intel_gpu_freq(dev_priv, max_freq));
1239

1240
		max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1241
			    rp_state_cap >> 0) & 0xff;
1242
		max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1243
			     GEN9_FREQ_SCALER : 1);
1244
		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1245
			   intel_gpu_freq(dev_priv, max_freq));
1246
		seq_printf(m, "Max overclocked frequency: %dMHz\n",
1247
			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1248

1249 1250 1251
		seq_printf(m, "Current freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
		seq_printf(m, "Actual freq: %d MHz\n", cagf);
1252 1253
		seq_printf(m, "Idle freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1254 1255
		seq_printf(m, "Min freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1256 1257
		seq_printf(m, "Boost freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1258 1259 1260 1261 1262
		seq_printf(m, "Max freq: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
		seq_printf(m,
			   "efficient (RPe) frequency: %d MHz\n",
			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1263
	} else {
1264
		seq_puts(m, "no P-state info available\n");
1265
	}
1266

1267 1268 1269 1270
	seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
	seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
	seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);

1271 1272 1273
out:
	intel_runtime_pm_put(dev_priv);
	return ret;
1274 1275
}

1276 1277 1278 1279
static void i915_instdone_info(struct drm_i915_private *dev_priv,
			       struct seq_file *m,
			       struct intel_instdone *instdone)
{
1280 1281 1282
	int slice;
	int subslice;

1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294
	seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
		   instdone->instdone);

	if (INTEL_GEN(dev_priv) <= 3)
		return;

	seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
		   instdone->slice_common);

	if (INTEL_GEN(dev_priv) <= 6)
		return;

1295 1296 1297 1298 1299 1300 1301
	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
		seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
			   slice, subslice, instdone->sampler[slice][subslice]);

	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
		seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
			   slice, subslice, instdone->row[slice][subslice]);
1302 1303
}

1304 1305
static int i915_hangcheck_info(struct seq_file *m, void *unused)
{
1306
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1307
	struct intel_engine_cs *engine;
1308 1309
	u64 acthd[I915_NUM_ENGINES];
	u32 seqno[I915_NUM_ENGINES];
1310
	struct intel_instdone instdone;
1311
	enum intel_engine_id id;
1312

1313 1314 1315 1316 1317 1318 1319 1320 1321
	if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
		seq_printf(m, "Wedged\n");
	if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
		seq_printf(m, "Reset in progress\n");
	if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
		seq_printf(m, "Waiter holding struct mutex\n");
	if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
		seq_printf(m, "struct_mutex blocked for reset\n");

1322 1323 1324 1325 1326
	if (!i915.enable_hangcheck) {
		seq_printf(m, "Hangcheck disabled\n");
		return 0;
	}

1327 1328
	intel_runtime_pm_get(dev_priv);

1329
	for_each_engine(engine, dev_priv, id) {
1330
		acthd[id] = intel_engine_get_active_head(engine);
1331
		seqno[id] = intel_engine_get_seqno(engine);
1332 1333
	}

1334
	intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1335

1336 1337
	intel_runtime_pm_put(dev_priv);

1338 1339 1340 1341 1342 1343 1344
	if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
		seq_printf(m, "Hangcheck active, fires in %dms\n",
			   jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
					    jiffies));
	} else
		seq_printf(m, "Hangcheck inactive\n");

1345
	for_each_engine(engine, dev_priv, id) {
1346 1347 1348
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
		struct rb_node *rb;

1349
		seq_printf(m, "%s:\n", engine->name);
1350
		seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1351 1352
			   engine->hangcheck.seqno, seqno[id],
			   intel_engine_last_submit(engine));
1353 1354 1355 1356
		seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
			   yesno(intel_engine_has_waiter(engine)),
			   yesno(test_bit(engine->id,
					  &dev_priv->gpu_error.missed_irq_rings)));
1357
		spin_lock_irq(&b->lock);
1358 1359 1360 1361 1362 1363
		for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
			struct intel_wait *w = container_of(rb, typeof(*w), node);

			seq_printf(m, "\t%s [%d] waiting for %x\n",
				   w->tsk->comm, w->tsk->pid, w->seqno);
		}
1364
		spin_unlock_irq(&b->lock);
1365

1366
		seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1367
			   (long long)engine->hangcheck.acthd,
1368
			   (long long)acthd[id]);
1369 1370
		seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
		seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1371

1372
		if (engine->id == RCS) {
1373
			seq_puts(m, "\tinstdone read =\n");
1374

1375
			i915_instdone_info(dev_priv, m, &instdone);
1376

1377
			seq_puts(m, "\tinstdone accu =\n");
1378

1379 1380
			i915_instdone_info(dev_priv, m,
					   &engine->hangcheck.instdone);
1381
		}
1382 1383 1384 1385 1386
	}

	return 0;
}

1387
static int ironlake_drpc_info(struct seq_file *m)
1388
{
1389
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1390 1391 1392
	u32 rgvmodectl, rstdbyctl;
	u16 crstandvid;

1393
	intel_runtime_pm_get(dev_priv);
1394 1395 1396 1397 1398

	rgvmodectl = I915_READ(MEMMODECTL);
	rstdbyctl = I915_READ(RSTDBYCTL);
	crstandvid = I915_READ16(CRSTANDVID);

1399
	intel_runtime_pm_put(dev_priv);
1400

1401
	seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1402 1403 1404 1405
	seq_printf(m, "Boost freq: %d\n",
		   (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
		   MEMMODE_BOOST_FREQ_SHIFT);
	seq_printf(m, "HW control enabled: %s\n",
1406
		   yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1407
	seq_printf(m, "SW control enabled: %s\n",
1408
		   yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1409
	seq_printf(m, "Gated voltage change: %s\n",
1410
		   yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1411 1412
	seq_printf(m, "Starting frequency: P%d\n",
		   (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1413
	seq_printf(m, "Max P-state: P%d\n",
1414
		   (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1415 1416 1417 1418
	seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
	seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
	seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
	seq_printf(m, "Render standby enabled: %s\n",
1419
		   yesno(!(rstdbyctl & RCX_SW_EXIT)));
1420
	seq_puts(m, "Current RS state: ");
1421 1422
	switch (rstdbyctl & RSX_STATUS_MASK) {
	case RSX_STATUS_ON:
1423
		seq_puts(m, "on\n");
1424 1425
		break;
	case RSX_STATUS_RC1:
1426
		seq_puts(m, "RC1\n");
1427 1428
		break;
	case RSX_STATUS_RC1E:
1429
		seq_puts(m, "RC1E\n");
1430 1431
		break;
	case RSX_STATUS_RS1:
1432
		seq_puts(m, "RS1\n");
1433 1434
		break;
	case RSX_STATUS_RS2:
1435
		seq_puts(m, "RS2 (RC6)\n");
1436 1437
		break;
	case RSX_STATUS_RS3:
1438
		seq_puts(m, "RC3 (RC6+)\n");
1439 1440
		break;
	default:
1441
		seq_puts(m, "unknown\n");
1442 1443
		break;
	}
1444 1445 1446 1447

	return 0;
}

1448
static int i915_forcewake_domains(struct seq_file *m, void *data)
1449
{
1450
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1451 1452 1453
	struct intel_uncore_forcewake_domain *fw_domain;

	spin_lock_irq(&dev_priv->uncore.lock);
1454
	for_each_fw_domain(fw_domain, dev_priv) {
1455
		seq_printf(m, "%s.wake_count = %u\n",
1456
			   intel_uncore_forcewake_domain_to_str(fw_domain->id),
1457 1458 1459
			   fw_domain->wake_count);
	}
	spin_unlock_irq(&dev_priv->uncore.lock);
1460

1461 1462 1463 1464 1465
	return 0;
}

static int vlv_drpc_info(struct seq_file *m)
{
1466
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1467
	u32 rpmodectl1, rcctl1, pw_status;
1468

1469 1470
	intel_runtime_pm_get(dev_priv);

1471
	pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1472 1473 1474
	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
	rcctl1 = I915_READ(GEN6_RC_CONTROL);

1475 1476
	intel_runtime_pm_put(dev_priv);

1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489
	seq_printf(m, "Video Turbo Mode: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
	seq_printf(m, "Turbo enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "HW control enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "SW control enabled: %s\n",
		   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
			  GEN6_RP_MEDIA_SW_MODE));
	seq_printf(m, "RC6 Enabled: %s\n",
		   yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
					GEN6_RC_CTL_EI_MODE(1))));
	seq_printf(m, "Render Power Well: %s\n",
1490
		   (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1491
	seq_printf(m, "Media Power Well: %s\n",
1492
		   (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1493

1494 1495 1496 1497 1498
	seq_printf(m, "Render RC6 residency since boot: %u\n",
		   I915_READ(VLV_GT_RENDER_RC6));
	seq_printf(m, "Media RC6 residency since boot: %u\n",
		   I915_READ(VLV_GT_MEDIA_RC6));

1499
	return i915_forcewake_domains(m, NULL);
1500 1501
}

1502 1503
static int gen6_drpc_info(struct seq_file *m)
{
1504 1505
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
B
Ben Widawsky 已提交
1506
	u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1507
	u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1508
	unsigned forcewake_count;
1509
	int count = 0, ret;
1510 1511 1512 1513

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1514
	intel_runtime_pm_get(dev_priv);
1515

1516
	spin_lock_irq(&dev_priv->uncore.lock);
1517
	forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1518
	spin_unlock_irq(&dev_priv->uncore.lock);
1519 1520

	if (forcewake_count) {
1521 1522
		seq_puts(m, "RC information inaccurate because somebody "
			    "holds a forcewake reference \n");
1523 1524 1525 1526 1527 1528 1529
	} else {
		/* NB: we cannot use forcewake, else we read the wrong values */
		while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
			udelay(10);
		seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
	}

1530
	gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1531
	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1532 1533 1534

	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
	rcctl1 = I915_READ(GEN6_RC_CONTROL);
1535
	if (INTEL_GEN(dev_priv) >= 9) {
1536 1537 1538
		gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
		gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
	}
1539
	mutex_unlock(&dev->struct_mutex);
1540 1541 1542
	mutex_lock(&dev_priv->rps.hw_lock);
	sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
	mutex_unlock(&dev_priv->rps.hw_lock);
1543

1544 1545
	intel_runtime_pm_put(dev_priv);

1546 1547 1548 1549 1550 1551 1552
	seq_printf(m, "Video Turbo Mode: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
	seq_printf(m, "HW control enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "SW control enabled: %s\n",
		   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
			  GEN6_RP_MEDIA_SW_MODE));
1553
	seq_printf(m, "RC1e Enabled: %s\n",
1554 1555 1556
		   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
	seq_printf(m, "RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1557
	if (INTEL_GEN(dev_priv) >= 9) {
1558 1559 1560 1561 1562
		seq_printf(m, "Render Well Gating Enabled: %s\n",
			yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
		seq_printf(m, "Media Well Gating Enabled: %s\n",
			yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
	}
1563 1564 1565 1566
	seq_printf(m, "Deep RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
	seq_printf(m, "Deepest RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1567
	seq_puts(m, "Current RC state: ");
1568 1569 1570
	switch (gt_core_status & GEN6_RCn_MASK) {
	case GEN6_RC0:
		if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1571
			seq_puts(m, "Core Power Down\n");
1572
		else
1573
			seq_puts(m, "on\n");
1574 1575
		break;
	case GEN6_RC3:
1576
		seq_puts(m, "RC3\n");
1577 1578
		break;
	case GEN6_RC6:
1579
		seq_puts(m, "RC6\n");
1580 1581
		break;
	case GEN6_RC7:
1582
		seq_puts(m, "RC7\n");
1583 1584
		break;
	default:
1585
		seq_puts(m, "Unknown\n");
1586 1587 1588 1589 1590
		break;
	}

	seq_printf(m, "Core Power Down: %s\n",
		   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1591
	if (INTEL_GEN(dev_priv) >= 9) {
1592 1593 1594 1595 1596 1597 1598
		seq_printf(m, "Render Power Well: %s\n",
			(gen9_powergate_status &
			 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
		seq_printf(m, "Media Power Well: %s\n",
			(gen9_powergate_status &
			 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
	}
1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609

	/* Not exactly sure what this is */
	seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6_LOCKED));
	seq_printf(m, "RC6 residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6));
	seq_printf(m, "RC6+ residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6p));
	seq_printf(m, "RC6++ residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6pp));

B
Ben Widawsky 已提交
1610 1611 1612 1613 1614 1615
	seq_printf(m, "RC6   voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
	seq_printf(m, "RC6+  voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
	seq_printf(m, "RC6++ voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1616
	return i915_forcewake_domains(m, NULL);
1617 1618 1619 1620
}

static int i915_drpc_info(struct seq_file *m, void *unused)
{
1621
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1622

1623
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1624
		return vlv_drpc_info(m);
1625
	else if (INTEL_GEN(dev_priv) >= 6)
1626 1627 1628 1629 1630
		return gen6_drpc_info(m);
	else
		return ironlake_drpc_info(m);
}

1631 1632
static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
{
1633
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1634 1635 1636 1637 1638 1639 1640 1641 1642 1643

	seq_printf(m, "FB tracking busy bits: 0x%08x\n",
		   dev_priv->fb_tracking.busy_bits);

	seq_printf(m, "FB tracking flip bits: 0x%08x\n",
		   dev_priv->fb_tracking.flip_bits);

	return 0;
}

1644 1645
static int i915_fbc_status(struct seq_file *m, void *unused)
{
1646
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1647

1648
	if (!HAS_FBC(dev_priv)) {
1649
		seq_puts(m, "FBC unsupported on this chipset\n");
1650 1651 1652
		return 0;
	}

1653
	intel_runtime_pm_get(dev_priv);
P
Paulo Zanoni 已提交
1654
	mutex_lock(&dev_priv->fbc.lock);
1655

1656
	if (intel_fbc_is_active(dev_priv))
1657
		seq_puts(m, "FBC enabled\n");
1658 1659
	else
		seq_printf(m, "FBC disabled: %s\n",
1660
			   dev_priv->fbc.no_fbc_reason);
1661

1662 1663 1664 1665
	if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
		uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
				BDW_FBC_COMPRESSION_MASK :
				IVB_FBC_COMPRESSION_MASK;
1666
		seq_printf(m, "Compressing: %s\n",
1667 1668
			   yesno(I915_READ(FBC_STATUS2) & mask));
	}
1669

P
Paulo Zanoni 已提交
1670
	mutex_unlock(&dev_priv->fbc.lock);
1671 1672
	intel_runtime_pm_put(dev_priv);

1673 1674 1675
	return 0;
}

1676 1677
static int i915_fbc_fc_get(void *data, u64 *val)
{
1678
	struct drm_i915_private *dev_priv = data;
1679

1680
	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1681 1682 1683 1684 1685 1686 1687 1688 1689
		return -ENODEV;

	*val = dev_priv->fbc.false_color;

	return 0;
}

static int i915_fbc_fc_set(void *data, u64 val)
{
1690
	struct drm_i915_private *dev_priv = data;
1691 1692
	u32 reg;

1693
	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1694 1695
		return -ENODEV;

P
Paulo Zanoni 已提交
1696
	mutex_lock(&dev_priv->fbc.lock);
1697 1698 1699 1700 1701 1702 1703 1704

	reg = I915_READ(ILK_DPFC_CONTROL);
	dev_priv->fbc.false_color = val;

	I915_WRITE(ILK_DPFC_CONTROL, val ?
		   (reg | FBC_CTL_FALSE_COLOR) :
		   (reg & ~FBC_CTL_FALSE_COLOR));

P
Paulo Zanoni 已提交
1705
	mutex_unlock(&dev_priv->fbc.lock);
1706 1707 1708 1709 1710 1711 1712
	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
			i915_fbc_fc_get, i915_fbc_fc_set,
			"%llu\n");

1713 1714
static int i915_ips_status(struct seq_file *m, void *unused)
{
1715
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1716

1717
	if (!HAS_IPS(dev_priv)) {
1718 1719 1720 1721
		seq_puts(m, "not supported\n");
		return 0;
	}

1722 1723
	intel_runtime_pm_get(dev_priv);

1724 1725 1726
	seq_printf(m, "Enabled by kernel parameter: %s\n",
		   yesno(i915.enable_ips));

1727
	if (INTEL_GEN(dev_priv) >= 8) {
1728 1729 1730 1731 1732 1733 1734
		seq_puts(m, "Currently: unknown\n");
	} else {
		if (I915_READ(IPS_CTL) & IPS_ENABLE)
			seq_puts(m, "Currently: enabled\n");
		else
			seq_puts(m, "Currently: disabled\n");
	}
1735

1736 1737
	intel_runtime_pm_put(dev_priv);

1738 1739 1740
	return 0;
}

1741 1742
static int i915_sr_status(struct seq_file *m, void *unused)
{
1743
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1744 1745
	bool sr_enabled = false;

1746
	intel_runtime_pm_get(dev_priv);
1747
	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1748

1749
	if (HAS_PCH_SPLIT(dev_priv))
1750
		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1751 1752
	else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1753
		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1754
	else if (IS_I915GM(dev_priv))
1755
		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1756
	else if (IS_PINEVIEW(dev_priv))
1757
		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1758
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1759
		sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1760

1761
	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1762 1763
	intel_runtime_pm_put(dev_priv);

1764 1765
	seq_printf(m, "self-refresh: %s\n",
		   sr_enabled ? "enabled" : "disabled");
1766 1767 1768 1769

	return 0;
}

1770 1771
static int i915_emon_status(struct seq_file *m, void *unused)
{
1772 1773
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1774
	unsigned long temp, chipset, gfx;
1775 1776
	int ret;

1777
	if (!IS_GEN5(dev_priv))
1778 1779
		return -ENODEV;

1780 1781 1782
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1783 1784 1785 1786

	temp = i915_mch_val(dev_priv);
	chipset = i915_chipset_val(dev_priv);
	gfx = i915_gfx_val(dev_priv);
1787
	mutex_unlock(&dev->struct_mutex);
1788 1789 1790 1791 1792 1793 1794 1795 1796

	seq_printf(m, "GMCH temp: %ld\n", temp);
	seq_printf(m, "Chipset power: %ld\n", chipset);
	seq_printf(m, "GFX power: %ld\n", gfx);
	seq_printf(m, "Total power: %ld\n", chipset + gfx);

	return 0;
}

1797 1798
static int i915_ring_freq_table(struct seq_file *m, void *unused)
{
1799
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
1800
	int ret = 0;
1801
	int gpu_freq, ia_freq;
1802
	unsigned int max_gpu_freq, min_gpu_freq;
1803

1804
	if (!HAS_LLC(dev_priv)) {
1805
		seq_puts(m, "unsupported on this chipset\n");
1806 1807 1808
		return 0;
	}

1809 1810
	intel_runtime_pm_get(dev_priv);

1811
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1812
	if (ret)
1813
		goto out;
1814

1815
	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1816 1817 1818 1819 1820 1821 1822 1823 1824 1825
		/* Convert GT frequency to 50 HZ units */
		min_gpu_freq =
			dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
		max_gpu_freq =
			dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
	} else {
		min_gpu_freq = dev_priv->rps.min_freq_softlimit;
		max_gpu_freq = dev_priv->rps.max_freq_softlimit;
	}

1826
	seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1827

1828
	for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
B
Ben Widawsky 已提交
1829 1830 1831 1832
		ia_freq = gpu_freq;
		sandybridge_pcode_read(dev_priv,
				       GEN6_PCODE_READ_MIN_FREQ_TABLE,
				       &ia_freq);
1833
		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1834
			   intel_gpu_freq(dev_priv, (gpu_freq *
1835
				(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1836
				 GEN9_FREQ_SCALER : 1))),
1837 1838
			   ((ia_freq >> 0) & 0xff) * 100,
			   ((ia_freq >> 8) & 0xff) * 100);
1839 1840
	}

1841
	mutex_unlock(&dev_priv->rps.hw_lock);
1842

1843 1844 1845
out:
	intel_runtime_pm_put(dev_priv);
	return ret;
1846 1847
}

1848 1849
static int i915_opregion(struct seq_file *m, void *unused)
{
1850 1851
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1852 1853 1854 1855 1856
	struct intel_opregion *opregion = &dev_priv->opregion;
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
1857
		goto out;
1858

1859 1860
	if (opregion->header)
		seq_write(m, opregion->header, OPREGION_SIZE);
1861 1862 1863

	mutex_unlock(&dev->struct_mutex);

1864
out:
1865 1866 1867
	return 0;
}

1868 1869
static int i915_vbt(struct seq_file *m, void *unused)
{
1870
	struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1871 1872 1873 1874 1875 1876 1877

	if (opregion->vbt)
		seq_write(m, opregion->vbt, opregion->vbt_size);

	return 0;
}

1878 1879
static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
{
1880 1881
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1882
	struct intel_framebuffer *fbdev_fb = NULL;
1883
	struct drm_framebuffer *drm_fb;
1884 1885 1886 1887 1888
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1889

1890
#ifdef CONFIG_DRM_FBDEV_EMULATION
1891 1892
	if (dev_priv->fbdev) {
		fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903

		seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
			   fbdev_fb->base.width,
			   fbdev_fb->base.height,
			   fbdev_fb->base.depth,
			   fbdev_fb->base.bits_per_pixel,
			   fbdev_fb->base.modifier[0],
			   drm_framebuffer_read_refcount(&fbdev_fb->base));
		describe_obj(m, fbdev_fb->obj);
		seq_putc(m, '\n');
	}
1904
#endif
1905

1906
	mutex_lock(&dev->mode_config.fb_lock);
1907
	drm_for_each_fb(drm_fb, dev) {
1908 1909
		struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
		if (fb == fbdev_fb)
1910 1911
			continue;

1912
		seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1913 1914 1915
			   fb->base.width,
			   fb->base.height,
			   fb->base.depth,
1916
			   fb->base.bits_per_pixel,
1917
			   fb->base.modifier[0],
1918
			   drm_framebuffer_read_refcount(&fb->base));
1919
		describe_obj(m, fb->obj);
1920
		seq_putc(m, '\n');
1921
	}
1922
	mutex_unlock(&dev->mode_config.fb_lock);
1923
	mutex_unlock(&dev->struct_mutex);
1924 1925 1926 1927

	return 0;
}

1928
static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1929 1930
{
	seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1931 1932
		   ring->space, ring->head, ring->tail,
		   ring->last_retired_head);
1933 1934
}

1935 1936
static int i915_context_status(struct seq_file *m, void *unused)
{
1937 1938
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
1939
	struct intel_engine_cs *engine;
1940
	struct i915_gem_context *ctx;
1941
	enum intel_engine_id id;
1942
	int ret;
1943

1944
	ret = mutex_lock_interruptible(&dev->struct_mutex);
1945 1946 1947
	if (ret)
		return ret;

1948
	list_for_each_entry(ctx, &dev_priv->context_list, link) {
1949
		seq_printf(m, "HW context %u ", ctx->hw_id);
1950
		if (ctx->pid) {
1951 1952
			struct task_struct *task;

1953
			task = get_pid_task(ctx->pid, PIDTYPE_PID);
1954 1955 1956 1957 1958
			if (task) {
				seq_printf(m, "(%s [%d]) ",
					   task->comm, task->pid);
				put_task_struct(task);
			}
1959 1960
		} else if (IS_ERR(ctx->file_priv)) {
			seq_puts(m, "(deleted) ");
1961 1962 1963 1964
		} else {
			seq_puts(m, "(kernel) ");
		}

1965 1966
		seq_putc(m, ctx->remap_slice ? 'R' : 'r');
		seq_putc(m, '\n');
1967

1968
		for_each_engine(engine, dev_priv, id) {
1969 1970 1971 1972 1973
			struct intel_context *ce = &ctx->engine[engine->id];

			seq_printf(m, "%s: ", engine->name);
			seq_putc(m, ce->initialised ? 'I' : 'i');
			if (ce->state)
1974
				describe_obj(m, ce->state->obj);
1975
			if (ce->ring)
1976
				describe_ctx_ring(m, ce->ring);
1977 1978
			seq_putc(m, '\n');
		}
1979 1980

		seq_putc(m, '\n');
1981 1982
	}

1983
	mutex_unlock(&dev->struct_mutex);
1984 1985 1986 1987

	return 0;
}

1988
static void i915_dump_lrc_obj(struct seq_file *m,
1989
			      struct i915_gem_context *ctx,
1990
			      struct intel_engine_cs *engine)
1991
{
1992
	struct i915_vma *vma = ctx->engine[engine->id].state;
1993 1994 1995
	struct page *page;
	int j;

1996 1997
	seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);

1998 1999
	if (!vma) {
		seq_puts(m, "\tFake context\n");
2000 2001 2002
		return;
	}

2003 2004
	if (vma->flags & I915_VMA_GLOBAL_BIND)
		seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2005
			   i915_ggtt_offset(vma));
2006

C
Chris Wilson 已提交
2007
	if (i915_gem_object_pin_pages(vma->obj)) {
2008
		seq_puts(m, "\tFailed to get pages for context object\n\n");
2009 2010 2011
		return;
	}

2012 2013 2014
	page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
	if (page) {
		u32 *reg_state = kmap_atomic(page);
2015 2016

		for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2017 2018 2019
			seq_printf(m,
				   "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
				   j * 4,
2020 2021 2022 2023 2024 2025
				   reg_state[j], reg_state[j + 1],
				   reg_state[j + 2], reg_state[j + 3]);
		}
		kunmap_atomic(reg_state);
	}

C
Chris Wilson 已提交
2026
	i915_gem_object_unpin_pages(vma->obj);
2027 2028 2029
	seq_putc(m, '\n');
}

2030 2031
static int i915_dump_lrc(struct seq_file *m, void *unused)
{
2032 2033
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2034
	struct intel_engine_cs *engine;
2035
	struct i915_gem_context *ctx;
2036
	enum intel_engine_id id;
2037
	int ret;
2038 2039 2040 2041 2042 2043 2044 2045 2046 2047

	if (!i915.enable_execlists) {
		seq_printf(m, "Logical Ring Contexts are disabled\n");
		return 0;
	}

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

D
Dave Gordon 已提交
2048
	list_for_each_entry(ctx, &dev_priv->context_list, link)
2049
		for_each_engine(engine, dev_priv, id)
2050
			i915_dump_lrc_obj(m, ctx, engine);
2051 2052 2053 2054 2055 2056

	mutex_unlock(&dev->struct_mutex);

	return 0;
}

2057 2058
static const char *swizzle_string(unsigned swizzle)
{
2059
	switch (swizzle) {
2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074
	case I915_BIT_6_SWIZZLE_NONE:
		return "none";
	case I915_BIT_6_SWIZZLE_9:
		return "bit9";
	case I915_BIT_6_SWIZZLE_9_10:
		return "bit9/bit10";
	case I915_BIT_6_SWIZZLE_9_11:
		return "bit9/bit11";
	case I915_BIT_6_SWIZZLE_9_10_11:
		return "bit9/bit10/bit11";
	case I915_BIT_6_SWIZZLE_9_17:
		return "bit9/bit17";
	case I915_BIT_6_SWIZZLE_9_10_17:
		return "bit9/bit10/bit17";
	case I915_BIT_6_SWIZZLE_UNKNOWN:
2075
		return "unknown";
2076 2077 2078 2079 2080 2081 2082
	}

	return "bug";
}

static int i915_swizzle_info(struct seq_file *m, void *data)
{
2083
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2084

2085
	intel_runtime_pm_get(dev_priv);
2086 2087 2088 2089 2090 2091

	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
		   swizzle_string(dev_priv->mm.bit_6_swizzle_x));
	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
		   swizzle_string(dev_priv->mm.bit_6_swizzle_y));

2092
	if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2093 2094
		seq_printf(m, "DDC = 0x%08x\n",
			   I915_READ(DCC));
2095 2096
		seq_printf(m, "DDC2 = 0x%08x\n",
			   I915_READ(DCC2));
2097 2098 2099 2100
		seq_printf(m, "C0DRB3 = 0x%04x\n",
			   I915_READ16(C0DRB3));
		seq_printf(m, "C1DRB3 = 0x%04x\n",
			   I915_READ16(C1DRB3));
2101
	} else if (INTEL_GEN(dev_priv) >= 6) {
2102 2103 2104 2105 2106 2107 2108 2109
		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C0));
		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C1));
		seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C2));
		seq_printf(m, "TILECTL = 0x%08x\n",
			   I915_READ(TILECTL));
2110
		if (INTEL_GEN(dev_priv) >= 8)
B
Ben Widawsky 已提交
2111 2112 2113 2114 2115
			seq_printf(m, "GAMTARBMODE = 0x%08x\n",
				   I915_READ(GAMTARBMODE));
		else
			seq_printf(m, "ARB_MODE = 0x%08x\n",
				   I915_READ(ARB_MODE));
2116 2117
		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
			   I915_READ(DISP_ARB_CTL));
2118
	}
2119 2120 2121 2122

	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
		seq_puts(m, "L-shaped memory detected\n");

2123
	intel_runtime_pm_put(dev_priv);
2124 2125 2126 2127

	return 0;
}

B
Ben Widawsky 已提交
2128 2129
static int per_file_ctx(int id, void *ptr, void *data)
{
2130
	struct i915_gem_context *ctx = ptr;
B
Ben Widawsky 已提交
2131
	struct seq_file *m = data;
2132 2133 2134 2135 2136 2137 2138
	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;

	if (!ppgtt) {
		seq_printf(m, "  no ppgtt for context %d\n",
			   ctx->user_handle);
		return 0;
	}
B
Ben Widawsky 已提交
2139

2140 2141 2142
	if (i915_gem_context_is_default(ctx))
		seq_puts(m, "  default context:\n");
	else
2143
		seq_printf(m, "  context %d:\n", ctx->user_handle);
B
Ben Widawsky 已提交
2144 2145 2146 2147 2148
	ppgtt->debug_dump(ppgtt, m);

	return 0;
}

2149 2150
static void gen8_ppgtt_info(struct seq_file *m,
			    struct drm_i915_private *dev_priv)
D
Daniel Vetter 已提交
2151
{
B
Ben Widawsky 已提交
2152
	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2153 2154
	struct intel_engine_cs *engine;
	enum intel_engine_id id;
2155
	int i;
D
Daniel Vetter 已提交
2156

B
Ben Widawsky 已提交
2157 2158 2159
	if (!ppgtt)
		return;

2160
	for_each_engine(engine, dev_priv, id) {
2161
		seq_printf(m, "%s\n", engine->name);
B
Ben Widawsky 已提交
2162
		for (i = 0; i < 4; i++) {
2163
			u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
B
Ben Widawsky 已提交
2164
			pdp <<= 32;
2165
			pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2166
			seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
B
Ben Widawsky 已提交
2167 2168 2169 2170
		}
	}
}

2171 2172
static void gen6_ppgtt_info(struct seq_file *m,
			    struct drm_i915_private *dev_priv)
B
Ben Widawsky 已提交
2173
{
2174
	struct intel_engine_cs *engine;
2175
	enum intel_engine_id id;
D
Daniel Vetter 已提交
2176

2177
	if (IS_GEN6(dev_priv))
D
Daniel Vetter 已提交
2178 2179
		seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));

2180
	for_each_engine(engine, dev_priv, id) {
2181
		seq_printf(m, "%s\n", engine->name);
2182
		if (IS_GEN7(dev_priv))
2183 2184 2185 2186 2187 2188 2189 2190
			seq_printf(m, "GFX_MODE: 0x%08x\n",
				   I915_READ(RING_MODE_GEN7(engine)));
		seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
			   I915_READ(RING_PP_DIR_BASE(engine)));
		seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
			   I915_READ(RING_PP_DIR_BASE_READ(engine)));
		seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
			   I915_READ(RING_PP_DIR_DCLV(engine)));
D
Daniel Vetter 已提交
2191 2192 2193 2194
	}
	if (dev_priv->mm.aliasing_ppgtt) {
		struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;

2195
		seq_puts(m, "aliasing PPGTT:\n");
2196
		seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
B
Ben Widawsky 已提交
2197

B
Ben Widawsky 已提交
2198
		ppgtt->debug_dump(ppgtt, m);
2199
	}
B
Ben Widawsky 已提交
2200

D
Daniel Vetter 已提交
2201
	seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
B
Ben Widawsky 已提交
2202 2203 2204 2205
}

static int i915_ppgtt_info(struct seq_file *m, void *data)
{
2206 2207
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2208
	struct drm_file *file;
2209
	int ret;
B
Ben Widawsky 已提交
2210

2211 2212
	mutex_lock(&dev->filelist_mutex);
	ret = mutex_lock_interruptible(&dev->struct_mutex);
B
Ben Widawsky 已提交
2213
	if (ret)
2214 2215
		goto out_unlock;

2216
	intel_runtime_pm_get(dev_priv);
B
Ben Widawsky 已提交
2217

2218 2219 2220 2221
	if (INTEL_GEN(dev_priv) >= 8)
		gen8_ppgtt_info(m, dev_priv);
	else if (INTEL_GEN(dev_priv) >= 6)
		gen6_ppgtt_info(m, dev_priv);
B
Ben Widawsky 已提交
2222

2223 2224
	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct drm_i915_file_private *file_priv = file->driver_priv;
2225
		struct task_struct *task;
2226

2227
		task = get_pid_task(file->pid, PIDTYPE_PID);
2228 2229
		if (!task) {
			ret = -ESRCH;
2230
			goto out_rpm;
2231
		}
2232 2233
		seq_printf(m, "\nproc: %s\n", task->comm);
		put_task_struct(task);
2234 2235 2236 2237
		idr_for_each(&file_priv->context_idr, per_file_ctx,
			     (void *)(unsigned long)m);
	}

2238
out_rpm:
2239
	intel_runtime_pm_put(dev_priv);
D
Daniel Vetter 已提交
2240
	mutex_unlock(&dev->struct_mutex);
2241 2242
out_unlock:
	mutex_unlock(&dev->filelist_mutex);
2243
	return ret;
D
Daniel Vetter 已提交
2244 2245
}

2246 2247
static int count_irq_waiters(struct drm_i915_private *i915)
{
2248
	struct intel_engine_cs *engine;
2249
	enum intel_engine_id id;
2250 2251
	int count = 0;

2252
	for_each_engine(engine, i915, id)
2253
		count += intel_engine_has_waiter(engine);
2254 2255 2256 2257

	return count;
}

2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271
static const char *rps_power_to_str(unsigned int power)
{
	static const char * const strings[] = {
		[LOW_POWER] = "low power",
		[BETWEEN] = "mixed",
		[HIGH_POWER] = "high power",
	};

	if (power >= ARRAY_SIZE(strings) || !strings[power])
		return "unknown";

	return strings[power];
}

2272 2273
static int i915_rps_boost_info(struct seq_file *m, void *data)
{
2274 2275
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2276 2277
	struct drm_file *file;

2278
	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2279 2280
	seq_printf(m, "GPU busy? %s [%d requests]\n",
		   yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2281
	seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2282 2283 2284
	seq_printf(m, "Frequency requested %d\n",
		   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
	seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2285 2286 2287 2288
		   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
		   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
		   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
		   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2289 2290 2291 2292
	seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
		   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
		   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
		   intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2293 2294

	mutex_lock(&dev->filelist_mutex);
2295
	spin_lock(&dev_priv->rps.client_lock);
2296 2297 2298 2299 2300 2301 2302 2303 2304
	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct drm_i915_file_private *file_priv = file->driver_priv;
		struct task_struct *task;

		rcu_read_lock();
		task = pid_task(file->pid, PIDTYPE_PID);
		seq_printf(m, "%s [%d]: %d boosts%s\n",
			   task ? task->comm : "<unknown>",
			   task ? task->pid : -1,
2305 2306
			   file_priv->rps.boosts,
			   list_empty(&file_priv->rps.link) ? "" : ", active");
2307 2308
		rcu_read_unlock();
	}
2309
	seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2310
	spin_unlock(&dev_priv->rps.client_lock);
2311
	mutex_unlock(&dev->filelist_mutex);
2312

2313 2314
	if (INTEL_GEN(dev_priv) >= 6 &&
	    dev_priv->rps.enabled &&
2315
	    dev_priv->gt.active_requests) {
2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337
		u32 rpup, rpupei;
		u32 rpdown, rpdownei;

		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
		rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
		rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
		rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
		rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

		seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
			   rps_power_to_str(dev_priv->rps.power));
		seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
			   100 * rpup / rpupei,
			   dev_priv->rps.up_threshold);
		seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
			   100 * rpdown / rpdownei,
			   dev_priv->rps.down_threshold);
	} else {
		seq_puts(m, "\nRPS Autotuning inactive\n");
	}

2338
	return 0;
2339 2340
}

2341 2342
static int i915_llc(struct seq_file *m, void *data)
{
2343
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2344
	const bool edram = INTEL_GEN(dev_priv) > 8;
2345

2346
	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2347 2348
	seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
		   intel_uncore_edram_size(dev_priv)/1024/1024);
2349 2350 2351 2352

	return 0;
}

2353 2354
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
2355
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2356 2357 2358
	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
	u32 tmp, i;

2359
	if (!HAS_GUC_UCODE(dev_priv))
2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372
		return 0;

	seq_printf(m, "GuC firmware status:\n");
	seq_printf(m, "\tpath: %s\n",
		guc_fw->guc_fw_path);
	seq_printf(m, "\tfetch: %s\n",
		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
	seq_printf(m, "\tload: %s\n",
		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
	seq_printf(m, "\tversion wanted: %d.%d\n",
		guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
	seq_printf(m, "\tversion found: %d.%d\n",
		guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
A
Alex Dai 已提交
2373 2374 2375 2376 2377 2378
	seq_printf(m, "\theader: offset is %d; size = %d\n",
		guc_fw->header_offset, guc_fw->header_size);
	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
		guc_fw->ucode_offset, guc_fw->ucode_size);
	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
		guc_fw->rsa_offset, guc_fw->rsa_size);
2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395

	tmp = I915_READ(GUC_STATUS);

	seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
	seq_printf(m, "\tBootrom status = 0x%x\n",
		(tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
	seq_printf(m, "\tuKernel status = 0x%x\n",
		(tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
	seq_printf(m, "\tMIA Core status = 0x%x\n",
		(tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
	seq_puts(m, "\nScratch registers:\n");
	for (i = 0; i < 16; i++)
		seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));

	return 0;
}

2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421
static void i915_guc_log_info(struct seq_file *m,
			      struct drm_i915_private *dev_priv)
{
	struct intel_guc *guc = &dev_priv->guc;

	seq_puts(m, "\nGuC logging stats:\n");

	seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
		   guc->log.flush_count[GUC_ISR_LOG_BUFFER],
		   guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);

	seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
		   guc->log.flush_count[GUC_DPC_LOG_BUFFER],
		   guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);

	seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
		   guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
		   guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);

	seq_printf(m, "\tTotal flush interrupt count: %u\n",
		   guc->log.flush_interrupt_count);

	seq_printf(m, "\tCapture miss count: %u\n",
		   guc->log.capture_miss_count);
}

2422 2423 2424 2425
static void i915_guc_client_info(struct seq_file *m,
				 struct drm_i915_private *dev_priv,
				 struct i915_guc_client *client)
{
2426
	struct intel_engine_cs *engine;
2427
	enum intel_engine_id id;
2428 2429 2430 2431 2432 2433 2434 2435 2436
	uint64_t tot = 0;

	seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
		client->priority, client->ctx_index, client->proc_desc_offset);
	seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
		client->doorbell_id, client->doorbell_offset, client->cookie);
	seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
		client->wq_size, client->wq_offset, client->wq_tail);

2437
	seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2438 2439 2440
	seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
	seq_printf(m, "\tLast submission result: %d\n", client->retcode);

2441
	for_each_engine(engine, dev_priv, id) {
2442 2443
		u64 submissions = client->submissions[id];
		tot += submissions;
2444
		seq_printf(m, "\tSubmissions: %llu %s\n",
2445
				submissions, engine->name);
2446 2447 2448 2449 2450 2451
	}
	seq_printf(m, "\tTotal: %llu\n", tot);
}

static int i915_guc_info(struct seq_file *m, void *data)
{
2452 2453
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2454
	struct intel_guc guc;
2455
	struct i915_guc_client client = {};
2456
	struct intel_engine_cs *engine;
2457
	enum intel_engine_id id;
2458 2459
	u64 total = 0;

2460
	if (!HAS_GUC_SCHED(dev_priv))
2461 2462
		return 0;

A
Alex Dai 已提交
2463 2464 2465
	if (mutex_lock_interruptible(&dev->struct_mutex))
		return 0;

2466 2467
	/* Take a local copy of the GuC data, so we can dump it at leisure */
	guc = dev_priv->guc;
A
Alex Dai 已提交
2468
	if (guc.execbuf_client)
2469
		client = *guc.execbuf_client;
A
Alex Dai 已提交
2470 2471

	mutex_unlock(&dev->struct_mutex);
2472

2473 2474 2475 2476
	seq_printf(m, "Doorbell map:\n");
	seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
	seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);

2477 2478 2479 2480 2481 2482 2483
	seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
	seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
	seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
	seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
	seq_printf(m, "GuC last action error code: %d\n", guc.action_err);

	seq_printf(m, "\nGuC submissions:\n");
2484
	for_each_engine(engine, dev_priv, id) {
2485 2486
		u64 submissions = guc.submissions[id];
		total += submissions;
2487
		seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2488
			engine->name, submissions, guc.last_seqno[id]);
2489 2490 2491 2492 2493 2494
	}
	seq_printf(m, "\t%s: %llu\n", "Total", total);

	seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
	i915_guc_client_info(m, dev_priv, &client);

2495 2496
	i915_guc_log_info(m, dev_priv);

2497 2498 2499 2500 2501
	/* Add more as required ... */

	return 0;
}

A
Alex Dai 已提交
2502 2503
static int i915_guc_log_dump(struct seq_file *m, void *data)
{
2504
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2505
	struct drm_i915_gem_object *obj;
A
Alex Dai 已提交
2506 2507
	int i = 0, pg;

2508
	if (!dev_priv->guc.log.vma)
A
Alex Dai 已提交
2509 2510
		return 0;

2511
	obj = dev_priv->guc.log.vma->obj;
2512 2513
	for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
		u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
A
Alex Dai 已提交
2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527

		for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
			seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
				   *(log + i), *(log + i + 1),
				   *(log + i + 2), *(log + i + 3));

		kunmap_atomic(log);
	}

	seq_putc(m, '\n');

	return 0;
}

2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565
static int i915_guc_log_control_get(void *data, u64 *val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = to_i915(dev);

	if (!dev_priv->guc.log.vma)
		return -EINVAL;

	*val = i915.guc_log_level;

	return 0;
}

static int i915_guc_log_control_set(void *data, u64 val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = to_i915(dev);
	int ret;

	if (!dev_priv->guc.log.vma)
		return -EINVAL;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	intel_runtime_pm_get(dev_priv);
	ret = i915_guc_log_control(dev_priv, val);
	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);
	return ret;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
			i915_guc_log_control_get, i915_guc_log_control_set,
			"%lld\n");

2566 2567
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
2568
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
R
Rodrigo Vivi 已提交
2569
	u32 psrperf = 0;
R
Rodrigo Vivi 已提交
2570 2571
	u32 stat[3];
	enum pipe pipe;
R
Rodrigo Vivi 已提交
2572
	bool enabled = false;
2573

2574
	if (!HAS_PSR(dev_priv)) {
2575 2576 2577 2578
		seq_puts(m, "PSR not supported\n");
		return 0;
	}

2579 2580
	intel_runtime_pm_get(dev_priv);

2581
	mutex_lock(&dev_priv->psr.lock);
R
Rodrigo Vivi 已提交
2582 2583
	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
	seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2584
	seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2585
	seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2586 2587 2588 2589
	seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
		   dev_priv->psr.busy_frontbuffer_bits);
	seq_printf(m, "Re-enable work scheduled: %s\n",
		   yesno(work_busy(&dev_priv->psr.work.work)));
2590

2591
	if (HAS_DDI(dev_priv))
2592
		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2593 2594
	else {
		for_each_pipe(dev_priv, pipe) {
2595 2596 2597 2598 2599 2600 2601 2602 2603
			enum transcoder cpu_transcoder =
				intel_pipe_to_cpu_transcoder(dev_priv, pipe);
			enum intel_display_power_domain power_domain;

			power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
			if (!intel_display_power_get_if_enabled(dev_priv,
								power_domain))
				continue;

2604 2605 2606 2607 2608
			stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
				VLV_EDP_PSR_CURR_STATE_MASK;
			if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
			    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
				enabled = true;
2609 2610

			intel_display_power_put(dev_priv, power_domain);
R
Rodrigo Vivi 已提交
2611 2612
		}
	}
2613 2614 2615 2616

	seq_printf(m, "Main link in standby mode: %s\n",
		   yesno(dev_priv->psr.link_standby));

R
Rodrigo Vivi 已提交
2617 2618
	seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));

2619
	if (!HAS_DDI(dev_priv))
R
Rodrigo Vivi 已提交
2620 2621 2622 2623 2624 2625
		for_each_pipe(dev_priv, pipe) {
			if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
			    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
				seq_printf(m, " pipe %c", pipe_name(pipe));
		}
	seq_puts(m, "\n");
2626

2627 2628 2629 2630
	/*
	 * VLV/CHV PSR has no kind of performance counter
	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
	 */
2631
	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2632
		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
R
Rodrigo Vivi 已提交
2633
			EDP_PSR_PERF_CNT_MASK;
R
Rodrigo Vivi 已提交
2634 2635 2636

		seq_printf(m, "Performance_Counter: %u\n", psrperf);
	}
2637
	mutex_unlock(&dev_priv->psr.lock);
2638

2639
	intel_runtime_pm_put(dev_priv);
2640 2641 2642
	return 0;
}

2643 2644
static int i915_sink_crc(struct seq_file *m, void *data)
{
2645 2646
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2647 2648 2649 2650 2651 2652
	struct intel_connector *connector;
	struct intel_dp *intel_dp = NULL;
	int ret;
	u8 crc[6];

	drm_modeset_lock_all(dev);
2653
	for_each_intel_connector(dev, connector) {
2654
		struct drm_crtc *crtc;
2655

2656
		if (!connector->base.state->best_encoder)
2657 2658
			continue;

2659 2660
		crtc = connector->base.state->crtc;
		if (!crtc->state->active)
2661 2662
			continue;

2663
		if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2664 2665
			continue;

2666
		intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682

		ret = intel_dp_sink_crc(intel_dp, crc);
		if (ret)
			goto out;

		seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
			   crc[0], crc[1], crc[2],
			   crc[3], crc[4], crc[5]);
		goto out;
	}
	ret = -ENODEV;
out:
	drm_modeset_unlock_all(dev);
	return ret;
}

2683 2684
static int i915_energy_uJ(struct seq_file *m, void *data)
{
2685
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2686 2687 2688
	u64 power;
	u32 units;

2689
	if (INTEL_GEN(dev_priv) < 6)
2690 2691
		return -ENODEV;

2692 2693
	intel_runtime_pm_get(dev_priv);

2694 2695 2696 2697 2698 2699
	rdmsrl(MSR_RAPL_POWER_UNIT, power);
	power = (power & 0x1f00) >> 8;
	units = 1000000 / (1 << power); /* convert to uJ */
	power = I915_READ(MCH_SECP_NRG_STTS);
	power *= units;

2700 2701
	intel_runtime_pm_put(dev_priv);

2702
	seq_printf(m, "%llu", (long long unsigned)power);
2703 2704 2705 2706

	return 0;
}

2707
static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2708
{
2709
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
D
David Weinehall 已提交
2710
	struct pci_dev *pdev = dev_priv->drm.pdev;
2711

2712 2713
	if (!HAS_RUNTIME_PM(dev_priv))
		seq_puts(m, "Runtime power management not supported\n");
2714

2715
	seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2716
	seq_printf(m, "IRQs disabled: %s\n",
2717
		   yesno(!intel_irqs_enabled(dev_priv)));
2718
#ifdef CONFIG_PM
2719
	seq_printf(m, "Usage count: %d\n",
2720
		   atomic_read(&dev_priv->drm.dev->power.usage_count));
2721 2722 2723
#else
	seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
#endif
2724
	seq_printf(m, "PCI device power state: %s [%d]\n",
D
David Weinehall 已提交
2725 2726
		   pci_power_name(pdev->current_state),
		   pdev->current_state);
2727

2728 2729 2730
	return 0;
}

2731 2732
static int i915_power_domain_info(struct seq_file *m, void *unused)
{
2733
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753
	struct i915_power_domains *power_domains = &dev_priv->power_domains;
	int i;

	mutex_lock(&power_domains->lock);

	seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
	for (i = 0; i < power_domains->power_well_count; i++) {
		struct i915_power_well *power_well;
		enum intel_display_power_domain power_domain;

		power_well = &power_domains->power_wells[i];
		seq_printf(m, "%-25s %d\n", power_well->name,
			   power_well->count);

		for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
		     power_domain++) {
			if (!(BIT(power_domain) & power_well->domains))
				continue;

			seq_printf(m, "  %-23s %d\n",
2754
				 intel_display_power_domain_str(power_domain),
2755 2756 2757 2758 2759 2760 2761 2762 2763
				 power_domains->domain_use_count[power_domain]);
		}
	}

	mutex_unlock(&power_domains->lock);

	return 0;
}

2764 2765
static int i915_dmc_info(struct seq_file *m, void *unused)
{
2766
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
2767 2768
	struct intel_csr *csr;

2769
	if (!HAS_CSR(dev_priv)) {
2770 2771 2772 2773 2774 2775
		seq_puts(m, "not supported\n");
		return 0;
	}

	csr = &dev_priv->csr;

2776 2777
	intel_runtime_pm_get(dev_priv);

2778 2779 2780 2781
	seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
	seq_printf(m, "path: %s\n", csr->fw_path);

	if (!csr->dmc_payload)
2782
		goto out;
2783 2784 2785 2786

	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
		   CSR_VERSION_MINOR(csr->version));

2787
	if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2788 2789 2790 2791
		seq_printf(m, "DC3 -> DC5 count: %d\n",
			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
		seq_printf(m, "DC5 -> DC6 count: %d\n",
			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
2792
	} else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2793 2794
		seq_printf(m, "DC3 -> DC5 count: %d\n",
			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
2795 2796
	}

2797 2798 2799 2800 2801
out:
	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));

2802 2803
	intel_runtime_pm_put(dev_priv);

2804 2805 2806
	return 0;
}

2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828
static void intel_seq_print_mode(struct seq_file *m, int tabs,
				 struct drm_display_mode *mode)
{
	int i;

	for (i = 0; i < tabs; i++)
		seq_putc(m, '\t');

	seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
		   mode->base.id, mode->name,
		   mode->vrefresh, mode->clock,
		   mode->hdisplay, mode->hsync_start,
		   mode->hsync_end, mode->htotal,
		   mode->vdisplay, mode->vsync_start,
		   mode->vsync_end, mode->vtotal,
		   mode->type, mode->flags);
}

static void intel_encoder_info(struct seq_file *m,
			       struct intel_crtc *intel_crtc,
			       struct intel_encoder *intel_encoder)
{
2829 2830
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2831 2832 2833 2834 2835 2836
	struct drm_crtc *crtc = &intel_crtc->base;
	struct intel_connector *intel_connector;
	struct drm_encoder *encoder;

	encoder = &intel_encoder->base;
	seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2837
		   encoder->base.id, encoder->name);
2838 2839 2840 2841
	for_each_connector_on_encoder(dev, encoder, intel_connector) {
		struct drm_connector *connector = &intel_connector->base;
		seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
			   connector->base.id,
2842
			   connector->name,
2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855
			   drm_get_connector_status_name(connector->status));
		if (connector->status == connector_status_connected) {
			struct drm_display_mode *mode = &crtc->mode;
			seq_printf(m, ", mode:\n");
			intel_seq_print_mode(m, 2, mode);
		} else {
			seq_putc(m, '\n');
		}
	}
}

static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
2856 2857
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
2858 2859
	struct drm_crtc *crtc = &intel_crtc->base;
	struct intel_encoder *intel_encoder;
2860 2861
	struct drm_plane_state *plane_state = crtc->primary->state;
	struct drm_framebuffer *fb = plane_state->fb;
2862

2863
	if (fb)
2864
		seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2865 2866
			   fb->base.id, plane_state->src_x >> 16,
			   plane_state->src_y >> 16, fb->width, fb->height);
2867 2868
	else
		seq_puts(m, "\tprimary plane disabled\n");
2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887
	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		intel_encoder_info(m, intel_crtc, intel_encoder);
}

static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
{
	struct drm_display_mode *mode = panel->fixed_mode;

	seq_printf(m, "\tfixed mode:\n");
	intel_seq_print_mode(m, 2, mode);
}

static void intel_dp_info(struct seq_file *m,
			  struct intel_connector *intel_connector)
{
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2888
	seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2889
	if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2890
		intel_panel_info(m, &intel_connector->panel);
2891 2892 2893

	drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
				&intel_dp->aux);
2894 2895 2896 2897 2898 2899 2900 2901
}

static void intel_hdmi_info(struct seq_file *m,
			    struct intel_connector *intel_connector)
{
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);

2902
	seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915
}

static void intel_lvds_info(struct seq_file *m,
			    struct intel_connector *intel_connector)
{
	intel_panel_info(m, &intel_connector->panel);
}

static void intel_connector_info(struct seq_file *m,
				 struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct intel_encoder *intel_encoder = intel_connector->encoder;
2916
	struct drm_display_mode *mode;
2917 2918

	seq_printf(m, "connector %d: type %s, status: %s\n",
2919
		   connector->base.id, connector->name,
2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930
		   drm_get_connector_status_name(connector->status));
	if (connector->status == connector_status_connected) {
		seq_printf(m, "\tname: %s\n", connector->display_info.name);
		seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
			   connector->display_info.width_mm,
			   connector->display_info.height_mm);
		seq_printf(m, "\tsubpixel order: %s\n",
			   drm_get_subpixel_order_name(connector->display_info.subpixel_order));
		seq_printf(m, "\tCEA rev: %d\n",
			   connector->display_info.cea_rev);
	}
2931 2932 2933 2934 2935 2936 2937

	if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
		return;

	switch (connector->connector_type) {
	case DRM_MODE_CONNECTOR_DisplayPort:
	case DRM_MODE_CONNECTOR_eDP:
2938
		intel_dp_info(m, intel_connector);
2939 2940 2941
		break;
	case DRM_MODE_CONNECTOR_LVDS:
		if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2942
			intel_lvds_info(m, intel_connector);
2943 2944 2945 2946 2947 2948 2949 2950
		break;
	case DRM_MODE_CONNECTOR_HDMIA:
		if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
		    intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
			intel_hdmi_info(m, intel_connector);
		break;
	default:
		break;
2951
	}
2952

2953 2954 2955
	seq_printf(m, "\tmodes:\n");
	list_for_each_entry(mode, &connector->modes, head)
		intel_seq_print_mode(m, 2, mode);
2956 2957
}

2958
static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2959 2960 2961
{
	u32 state;

2962
	if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2963
		state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2964
	else
2965
		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2966 2967 2968 2969

	return state;
}

2970 2971
static bool cursor_position(struct drm_i915_private *dev_priv,
			    int pipe, int *x, int *y)
2972 2973 2974
{
	u32 pos;

2975
	pos = I915_READ(CURPOS(pipe));
2976 2977 2978 2979 2980 2981 2982 2983 2984

	*x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
	if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
		*x = -*x;

	*y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
	if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
		*y = -*y;

2985
	return cursor_active(dev_priv, pipe);
2986 2987
}

2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014
static const char *plane_type(enum drm_plane_type type)
{
	switch (type) {
	case DRM_PLANE_TYPE_OVERLAY:
		return "OVL";
	case DRM_PLANE_TYPE_PRIMARY:
		return "PRI";
	case DRM_PLANE_TYPE_CURSOR:
		return "CUR";
	/*
	 * Deliberately omitting default: to generate compiler warnings
	 * when a new drm_plane_type gets added.
	 */
	}

	return "unknown";
}

static const char *plane_rotation(unsigned int rotation)
{
	static char buf[48];
	/*
	 * According to doc only one DRM_ROTATE_ is allowed but this
	 * will print them all to visualize if the values are misused
	 */
	snprintf(buf, sizeof(buf),
		 "%s%s%s%s%s%s(0x%08x)",
3015 3016 3017 3018 3019 3020
		 (rotation & DRM_ROTATE_0) ? "0 " : "",
		 (rotation & DRM_ROTATE_90) ? "90 " : "",
		 (rotation & DRM_ROTATE_180) ? "180 " : "",
		 (rotation & DRM_ROTATE_270) ? "270 " : "",
		 (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
		 (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3021 3022 3023 3024 3025 3026 3027
		 rotation);

	return buf;
}

static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
3028 3029
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3030 3031 3032 3033 3034
	struct intel_plane *intel_plane;

	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
		struct drm_plane_state *state;
		struct drm_plane *plane = &intel_plane->base;
3035
		char *format_name;
3036 3037 3038 3039 3040 3041 3042 3043

		if (!plane->state) {
			seq_puts(m, "plane->state is NULL!\n");
			continue;
		}

		state = plane->state;

3044 3045 3046 3047 3048 3049
		if (state->fb) {
			format_name = drm_get_format_name(state->fb->pixel_format);
		} else {
			format_name = kstrdup("N/A", GFP_KERNEL);
		}

3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062
		seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
			   plane->base.id,
			   plane_type(intel_plane->base.type),
			   state->crtc_x, state->crtc_y,
			   state->crtc_w, state->crtc_h,
			   (state->src_x >> 16),
			   ((state->src_x & 0xffff) * 15625) >> 10,
			   (state->src_y >> 16),
			   ((state->src_y & 0xffff) * 15625) >> 10,
			   (state->src_w >> 16),
			   ((state->src_w & 0xffff) * 15625) >> 10,
			   (state->src_h >> 16),
			   ((state->src_h & 0xffff) * 15625) >> 10,
3063
			   format_name,
3064
			   plane_rotation(state->rotation));
3065 3066

		kfree(format_name);
3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097
	}
}

static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
	struct intel_crtc_state *pipe_config;
	int num_scalers = intel_crtc->num_scalers;
	int i;

	pipe_config = to_intel_crtc_state(intel_crtc->base.state);

	/* Not all platformas have a scaler */
	if (num_scalers) {
		seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
			   num_scalers,
			   pipe_config->scaler_state.scaler_users,
			   pipe_config->scaler_state.scaler_id);

		for (i = 0; i < SKL_NUM_SCALERS; i++) {
			struct intel_scaler *sc =
					&pipe_config->scaler_state.scalers[i];

			seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
				   i, yesno(sc->in_use), sc->mode);
		}
		seq_puts(m, "\n");
	} else {
		seq_puts(m, "\tNo scalers available on this platform\n");
	}
}

3098 3099
static int i915_display_info(struct seq_file *m, void *unused)
{
3100 3101
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3102
	struct intel_crtc *crtc;
3103 3104
	struct drm_connector *connector;

3105
	intel_runtime_pm_get(dev_priv);
3106 3107 3108
	drm_modeset_lock_all(dev);
	seq_printf(m, "CRTC info\n");
	seq_printf(m, "---------\n");
3109
	for_each_intel_crtc(dev, crtc) {
3110
		bool active;
3111
		struct intel_crtc_state *pipe_config;
3112
		int x, y;
3113

3114 3115
		pipe_config = to_intel_crtc_state(crtc->base.state);

3116
		seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3117
			   crtc->base.base.id, pipe_name(crtc->pipe),
3118
			   yesno(pipe_config->base.active),
3119 3120 3121
			   pipe_config->pipe_src_w, pipe_config->pipe_src_h,
			   yesno(pipe_config->dither), pipe_config->pipe_bpp);

3122
		if (pipe_config->base.active) {
3123 3124
			intel_crtc_info(m, crtc);

3125
			active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3126
			seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3127
				   yesno(crtc->cursor_base),
3128 3129
				   x, y, crtc->base.cursor->state->crtc_w,
				   crtc->base.cursor->state->crtc_h,
3130
				   crtc->cursor_addr, yesno(active));
3131 3132
			intel_scaler_info(m, crtc);
			intel_plane_info(m, crtc);
3133
		}
3134 3135 3136 3137

		seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
			   yesno(!crtc->cpu_fifo_underrun_disabled),
			   yesno(!crtc->pch_fifo_underrun_disabled));
3138 3139 3140 3141 3142 3143 3144 3145 3146
	}

	seq_printf(m, "\n");
	seq_printf(m, "Connector info\n");
	seq_printf(m, "--------------\n");
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		intel_connector_info(m, connector);
	}
	drm_modeset_unlock_all(dev);
3147
	intel_runtime_pm_put(dev_priv);
3148 3149 3150 3151

	return 0;
}

3152 3153 3154 3155
static int i915_engine_info(struct seq_file *m, void *unused)
{
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct intel_engine_cs *engine;
3156
	enum intel_engine_id id;
3157

3158 3159
	intel_runtime_pm_get(dev_priv);

3160
	for_each_engine(engine, dev_priv, id) {
3161 3162 3163 3164 3165 3166 3167 3168
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
		struct drm_i915_gem_request *rq;
		struct rb_node *rb;
		u64 addr;

		seq_printf(m, "%s\n", engine->name);
		seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
			   intel_engine_get_seqno(engine),
3169
			   intel_engine_last_submit(engine),
3170 3171 3172 3173 3174 3175 3176
			   engine->hangcheck.seqno,
			   engine->hangcheck.score);

		rcu_read_lock();

		seq_printf(m, "\tRequests:\n");

3177 3178 3179
		rq = list_first_entry(&engine->timeline->requests,
				      struct drm_i915_gem_request, link);
		if (&rq->link != &engine->timeline->requests)
3180 3181
			print_request(m, rq, "\t\tfirst  ");

3182 3183 3184
		rq = list_last_entry(&engine->timeline->requests,
				     struct drm_i915_gem_request, link);
		if (&rq->link != &engine->timeline->requests)
3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257
			print_request(m, rq, "\t\tlast   ");

		rq = i915_gem_find_active_request(engine);
		if (rq) {
			print_request(m, rq, "\t\tactive ");
			seq_printf(m,
				   "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
				   rq->head, rq->postfix, rq->tail,
				   rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
				   rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
		}

		seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
			   I915_READ(RING_START(engine->mmio_base)),
			   rq ? i915_ggtt_offset(rq->ring->vma) : 0);
		seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
			   I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
			   rq ? rq->ring->head : 0);
		seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
			   I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
			   rq ? rq->ring->tail : 0);
		seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
			   I915_READ(RING_CTL(engine->mmio_base)),
			   I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");

		rcu_read_unlock();

		addr = intel_engine_get_active_head(engine);
		seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
			   upper_32_bits(addr), lower_32_bits(addr));
		addr = intel_engine_get_last_batch_head(engine);
		seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
			   upper_32_bits(addr), lower_32_bits(addr));

		if (i915.enable_execlists) {
			u32 ptr, read, write;

			seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
				   I915_READ(RING_EXECLIST_STATUS_LO(engine)),
				   I915_READ(RING_EXECLIST_STATUS_HI(engine)));

			ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
			read = GEN8_CSB_READ_PTR(ptr);
			write = GEN8_CSB_WRITE_PTR(ptr);
			seq_printf(m, "\tExeclist CSB read %d, write %d\n",
				   read, write);
			if (read >= GEN8_CSB_ENTRIES)
				read = 0;
			if (write >= GEN8_CSB_ENTRIES)
				write = 0;
			if (read > write)
				write += GEN8_CSB_ENTRIES;
			while (read < write) {
				unsigned int idx = ++read % GEN8_CSB_ENTRIES;

				seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
					   idx,
					   I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
					   I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
			}

			rcu_read_lock();
			rq = READ_ONCE(engine->execlist_port[0].request);
			if (rq)
				print_request(m, rq, "\t\tELSP[0] ");
			else
				seq_printf(m, "\t\tELSP[0] idle\n");
			rq = READ_ONCE(engine->execlist_port[1].request);
			if (rq)
				print_request(m, rq, "\t\tELSP[1] ");
			else
				seq_printf(m, "\t\tELSP[1] idle\n");
			rcu_read_unlock();
3258

3259
			spin_lock_irq(&engine->timeline->lock);
3260 3261 3262
			list_for_each_entry(rq, &engine->execlist_queue, execlist_link) {
				print_request(m, rq, "\t\tQ ");
			}
3263
			spin_unlock_irq(&engine->timeline->lock);
3264 3265 3266 3267 3268 3269 3270 3271 3272
		} else if (INTEL_GEN(dev_priv) > 6) {
			seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
				   I915_READ(RING_PP_DIR_BASE(engine)));
			seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
				   I915_READ(RING_PP_DIR_BASE_READ(engine)));
			seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
				   I915_READ(RING_PP_DIR_DCLV(engine)));
		}

3273
		spin_lock_irq(&b->lock);
3274 3275 3276 3277 3278 3279
		for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
			struct intel_wait *w = container_of(rb, typeof(*w), node);

			seq_printf(m, "\t%s [%d] waiting for %x\n",
				   w->tsk->comm, w->tsk->pid, w->seqno);
		}
3280
		spin_unlock_irq(&b->lock);
3281 3282 3283 3284

		seq_puts(m, "\n");
	}

3285 3286
	intel_runtime_pm_put(dev_priv);

3287 3288 3289
	return 0;
}

B
Ben Widawsky 已提交
3290 3291
static int i915_semaphore_status(struct seq_file *m, void *unused)
{
3292 3293
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3294
	struct intel_engine_cs *engine;
3295
	int num_rings = INTEL_INFO(dev_priv)->num_rings;
3296 3297
	enum intel_engine_id id;
	int j, ret;
B
Ben Widawsky 已提交
3298

3299
	if (!i915.semaphores) {
B
Ben Widawsky 已提交
3300 3301 3302 3303 3304 3305 3306
		seq_puts(m, "Semaphores are disabled\n");
		return 0;
	}

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
3307
	intel_runtime_pm_get(dev_priv);
B
Ben Widawsky 已提交
3308

3309
	if (IS_BROADWELL(dev_priv)) {
B
Ben Widawsky 已提交
3310 3311 3312
		struct page *page;
		uint64_t *seqno;

3313
		page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
B
Ben Widawsky 已提交
3314 3315

		seqno = (uint64_t *)kmap_atomic(page);
3316
		for_each_engine(engine, dev_priv, id) {
B
Ben Widawsky 已提交
3317 3318
			uint64_t offset;

3319
			seq_printf(m, "%s\n", engine->name);
B
Ben Widawsky 已提交
3320 3321 3322

			seq_puts(m, "  Last signal:");
			for (j = 0; j < num_rings; j++) {
3323
				offset = id * I915_NUM_ENGINES + j;
B
Ben Widawsky 已提交
3324 3325 3326 3327 3328 3329 3330
				seq_printf(m, "0x%08llx (0x%02llx) ",
					   seqno[offset], offset * 8);
			}
			seq_putc(m, '\n');

			seq_puts(m, "  Last wait:  ");
			for (j = 0; j < num_rings; j++) {
3331
				offset = id + (j * I915_NUM_ENGINES);
B
Ben Widawsky 已提交
3332 3333 3334 3335 3336 3337 3338 3339 3340
				seq_printf(m, "0x%08llx (0x%02llx) ",
					   seqno[offset], offset * 8);
			}
			seq_putc(m, '\n');

		}
		kunmap_atomic(seqno);
	} else {
		seq_puts(m, "  Last signal:");
3341
		for_each_engine(engine, dev_priv, id)
B
Ben Widawsky 已提交
3342 3343
			for (j = 0; j < num_rings; j++)
				seq_printf(m, "0x%08x\n",
3344
					   I915_READ(engine->semaphore.mbox.signal[j]));
B
Ben Widawsky 已提交
3345 3346 3347
		seq_putc(m, '\n');
	}

3348
	intel_runtime_pm_put(dev_priv);
B
Ben Widawsky 已提交
3349 3350 3351 3352
	mutex_unlock(&dev->struct_mutex);
	return 0;
}

3353 3354
static int i915_shared_dplls_info(struct seq_file *m, void *unused)
{
3355 3356
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3357 3358 3359 3360 3361 3362 3363
	int i;

	drm_modeset_lock_all(dev);
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];

		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3364 3365
		seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
			   pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3366
		seq_printf(m, " tracked hardware state:\n");
3367 3368 3369 3370 3371 3372
		seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
		seq_printf(m, " dpll_md: 0x%08x\n",
			   pll->config.hw_state.dpll_md);
		seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
		seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
		seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3373 3374 3375 3376 3377 3378
	}
	drm_modeset_unlock_all(dev);

	return 0;
}

3379
static int i915_wa_registers(struct seq_file *m, void *unused)
3380 3381 3382
{
	int i;
	int ret;
3383
	struct intel_engine_cs *engine;
3384 3385
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3386
	struct i915_workarounds *workarounds = &dev_priv->workarounds;
3387
	enum intel_engine_id id;
3388 3389 3390 3391 3392 3393 3394

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	intel_runtime_pm_get(dev_priv);

3395
	seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3396
	for_each_engine(engine, dev_priv, id)
3397
		seq_printf(m, "HW whitelist count for %s: %d\n",
3398
			   engine->name, workarounds->hw_whitelist_count[id]);
3399
	for (i = 0; i < workarounds->count; ++i) {
3400 3401
		i915_reg_t addr;
		u32 mask, value, read;
3402
		bool ok;
3403

3404 3405 3406
		addr = workarounds->reg[i].addr;
		mask = workarounds->reg[i].mask;
		value = workarounds->reg[i].value;
3407 3408 3409
		read = I915_READ(addr);
		ok = (value & mask) == (read & mask);
		seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3410
			   i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3411 3412 3413 3414 3415 3416 3417 3418
	}

	intel_runtime_pm_put(dev_priv);
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

3419 3420
static int i915_ddb_info(struct seq_file *m, void *unused)
{
3421 3422
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3423 3424 3425 3426 3427
	struct skl_ddb_allocation *ddb;
	struct skl_ddb_entry *entry;
	enum pipe pipe;
	int plane;

3428
	if (INTEL_GEN(dev_priv) < 9)
3429 3430
		return 0;

3431 3432 3433 3434 3435 3436 3437 3438 3439
	drm_modeset_lock_all(dev);

	ddb = &dev_priv->wm.skl_hw.ddb;

	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");

	for_each_pipe(dev_priv, pipe) {
		seq_printf(m, "Pipe %c\n", pipe_name(pipe));

3440
		for_each_universal_plane(dev_priv, pipe, plane) {
3441 3442 3443 3444 3445 3446
			entry = &ddb->plane[pipe][plane];
			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
				   entry->start, entry->end,
				   skl_ddb_entry_size(entry));
		}

3447
		entry = &ddb->plane[pipe][PLANE_CURSOR];
3448 3449 3450 3451 3452 3453 3454 3455 3456
		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
			   entry->end, skl_ddb_entry_size(entry));
	}

	drm_modeset_unlock_all(dev);

	return 0;
}

3457
static void drrs_status_per_crtc(struct seq_file *m,
3458 3459
				 struct drm_device *dev,
				 struct intel_crtc *intel_crtc)
3460
{
3461
	struct drm_i915_private *dev_priv = to_i915(dev);
3462 3463
	struct i915_drrs *drrs = &dev_priv->drrs;
	int vrefresh = 0;
3464
	struct drm_connector *connector;
3465

3466 3467 3468 3469 3470
	drm_for_each_connector(connector, dev) {
		if (connector->state->crtc != &intel_crtc->base)
			continue;

		seq_printf(m, "%s:\n", connector->name);
3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483
	}

	if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
		seq_puts(m, "\tVBT: DRRS_type: Static");
	else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
		seq_puts(m, "\tVBT: DRRS_type: Seamless");
	else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
		seq_puts(m, "\tVBT: DRRS_type: None");
	else
		seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");

	seq_puts(m, "\n\n");

3484
	if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527
		struct intel_panel *panel;

		mutex_lock(&drrs->mutex);
		/* DRRS Supported */
		seq_puts(m, "\tDRRS Supported: Yes\n");

		/* disable_drrs() will make drrs->dp NULL */
		if (!drrs->dp) {
			seq_puts(m, "Idleness DRRS: Disabled");
			mutex_unlock(&drrs->mutex);
			return;
		}

		panel = &drrs->dp->attached_connector->panel;
		seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
					drrs->busy_frontbuffer_bits);

		seq_puts(m, "\n\t\t");
		if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
			seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
			vrefresh = panel->fixed_mode->vrefresh;
		} else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
			seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
			vrefresh = panel->downclock_mode->vrefresh;
		} else {
			seq_printf(m, "DRRS_State: Unknown(%d)\n",
						drrs->refresh_rate_type);
			mutex_unlock(&drrs->mutex);
			return;
		}
		seq_printf(m, "\t\tVrefresh: %d", vrefresh);

		seq_puts(m, "\n\t\t");
		mutex_unlock(&drrs->mutex);
	} else {
		/* DRRS not supported. Print the VBT parameter*/
		seq_puts(m, "\tDRRS Supported : No");
	}
	seq_puts(m, "\n");
}

static int i915_drrs_status(struct seq_file *m, void *unused)
{
3528 3529
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3530 3531 3532
	struct intel_crtc *intel_crtc;
	int active_crtc_cnt = 0;

3533
	drm_modeset_lock_all(dev);
3534
	for_each_intel_crtc(dev, intel_crtc) {
3535
		if (intel_crtc->base.state->active) {
3536 3537 3538 3539 3540 3541
			active_crtc_cnt++;
			seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);

			drrs_status_per_crtc(m, dev, intel_crtc);
		}
	}
3542
	drm_modeset_unlock_all(dev);
3543 3544 3545 3546 3547 3548 3549

	if (!active_crtc_cnt)
		seq_puts(m, "No active crtc found\n");

	return 0;
}

3550 3551
struct pipe_crc_info {
	const char *name;
3552
	struct drm_i915_private *dev_priv;
3553 3554 3555
	enum pipe pipe;
};

3556 3557
static int i915_dp_mst_info(struct seq_file *m, void *unused)
{
3558 3559
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	struct drm_device *dev = &dev_priv->drm;
3560 3561
	struct intel_encoder *intel_encoder;
	struct intel_digital_port *intel_dig_port;
3562 3563
	struct drm_connector *connector;

3564
	drm_modeset_lock_all(dev);
3565 3566
	drm_for_each_connector(connector, dev) {
		if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3567
			continue;
3568 3569 3570 3571 3572 3573

		intel_encoder = intel_attached_encoder(connector);
		if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
			continue;

		intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3574 3575
		if (!intel_dig_port->dp.can_mst)
			continue;
3576

3577 3578
		seq_printf(m, "MST Source Port %c\n",
			   port_name(intel_dig_port->port));
3579 3580 3581 3582 3583 3584
		drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
	}
	drm_modeset_unlock_all(dev);
	return 0;
}

3585 3586
static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
{
3587
	struct pipe_crc_info *info = inode->i_private;
3588
	struct drm_i915_private *dev_priv = info->dev_priv;
3589 3590
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];

3591
	if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3592 3593
		return -ENODEV;

3594 3595 3596 3597
	spin_lock_irq(&pipe_crc->lock);

	if (pipe_crc->opened) {
		spin_unlock_irq(&pipe_crc->lock);
3598 3599 3600
		return -EBUSY; /* already open */
	}

3601
	pipe_crc->opened = true;
3602 3603
	filep->private_data = inode->i_private;

3604 3605
	spin_unlock_irq(&pipe_crc->lock);

3606 3607 3608 3609 3610
	return 0;
}

static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
{
3611
	struct pipe_crc_info *info = inode->i_private;
3612
	struct drm_i915_private *dev_priv = info->dev_priv;
3613 3614
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];

3615 3616 3617
	spin_lock_irq(&pipe_crc->lock);
	pipe_crc->opened = false;
	spin_unlock_irq(&pipe_crc->lock);
3618

3619 3620 3621 3622 3623 3624 3625 3626 3627
	return 0;
}

/* (6 fields, 8 chars each, space separated (5) + '\n') */
#define PIPE_CRC_LINE_LEN	(6 * 8 + 5 + 1)
/* account for \'0' */
#define PIPE_CRC_BUFFER_LEN	(PIPE_CRC_LINE_LEN + 1)

static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3628
{
3629 3630 3631
	assert_spin_locked(&pipe_crc->lock);
	return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
			INTEL_PIPE_CRC_ENTRIES_NR);
3632 3633 3634 3635 3636 3637 3638
}

static ssize_t
i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
		   loff_t *pos)
{
	struct pipe_crc_info *info = filep->private_data;
3639
	struct drm_i915_private *dev_priv = info->dev_priv;
3640 3641
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
	char buf[PIPE_CRC_BUFFER_LEN];
3642
	int n_entries;
3643 3644 3645 3646 3647 3648 3649 3650 3651 3652
	ssize_t bytes_read;

	/*
	 * Don't allow user space to provide buffers not big enough to hold
	 * a line of data.
	 */
	if (count < PIPE_CRC_LINE_LEN)
		return -EINVAL;

	if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3653
		return 0;
3654 3655

	/* nothing to read */
3656
	spin_lock_irq(&pipe_crc->lock);
3657
	while (pipe_crc_data_count(pipe_crc) == 0) {
3658 3659 3660 3661
		int ret;

		if (filep->f_flags & O_NONBLOCK) {
			spin_unlock_irq(&pipe_crc->lock);
3662
			return -EAGAIN;
3663
		}
3664

3665 3666 3667 3668 3669 3670
		ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
				pipe_crc_data_count(pipe_crc), pipe_crc->lock);
		if (ret) {
			spin_unlock_irq(&pipe_crc->lock);
			return ret;
		}
3671 3672
	}

3673
	/* We now have one or more entries to read */
3674
	n_entries = count / PIPE_CRC_LINE_LEN;
3675

3676
	bytes_read = 0;
3677 3678 3679
	while (n_entries > 0) {
		struct intel_pipe_crc_entry *entry =
			&pipe_crc->entries[pipe_crc->tail];
3680

3681 3682 3683 3684 3685 3686 3687
		if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
			     INTEL_PIPE_CRC_ENTRIES_NR) < 1)
			break;

		BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
		pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);

3688 3689 3690 3691 3692 3693
		bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
				       "%8u %8x %8x %8x %8x %8x\n",
				       entry->frame, entry->crc[0],
				       entry->crc[1], entry->crc[2],
				       entry->crc[3], entry->crc[4]);

3694 3695
		spin_unlock_irq(&pipe_crc->lock);

3696
		if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3697
			return -EFAULT;
3698

3699 3700 3701 3702 3703
		user_buf += PIPE_CRC_LINE_LEN;
		n_entries--;

		spin_lock_irq(&pipe_crc->lock);
	}
3704

3705 3706
	spin_unlock_irq(&pipe_crc->lock);

3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734
	return bytes_read;
}

static const struct file_operations i915_pipe_crc_fops = {
	.owner = THIS_MODULE,
	.open = i915_pipe_crc_open,
	.read = i915_pipe_crc_read,
	.release = i915_pipe_crc_release,
};

static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
	{
		.name = "i915_pipe_A_crc",
		.pipe = PIPE_A,
	},
	{
		.name = "i915_pipe_B_crc",
		.pipe = PIPE_B,
	},
	{
		.name = "i915_pipe_C_crc",
		.pipe = PIPE_C,
	},
};

static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
				enum pipe pipe)
{
3735
	struct drm_i915_private *dev_priv = to_i915(minor->dev);
3736 3737 3738
	struct dentry *ent;
	struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];

3739
	info->dev_priv = dev_priv;
3740 3741
	ent = debugfs_create_file(info->name, S_IRUGO, root, info,
				  &i915_pipe_crc_fops);
3742 3743
	if (!ent)
		return -ENOMEM;
3744 3745

	return drm_add_fake_info_node(minor, ent, info);
3746 3747
}

D
Daniel Vetter 已提交
3748
static const char * const pipe_crc_sources[] = {
3749 3750 3751 3752
	"none",
	"plane1",
	"plane2",
	"pf",
3753
	"pipe",
D
Daniel Vetter 已提交
3754 3755 3756 3757
	"TV",
	"DP-B",
	"DP-C",
	"DP-D",
3758
	"auto",
3759 3760 3761 3762 3763 3764 3765 3766
};

static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
{
	BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
	return pipe_crc_sources[source];
}

3767
static int display_crc_ctl_show(struct seq_file *m, void *data)
3768
{
3769
	struct drm_i915_private *dev_priv = m->private;
3770 3771 3772 3773 3774 3775 3776 3777 3778
	int i;

	for (i = 0; i < I915_MAX_PIPES; i++)
		seq_printf(m, "%c %s\n", pipe_name(i),
			   pipe_crc_source_name(dev_priv->pipe_crc[i].source));

	return 0;
}

3779
static int display_crc_ctl_open(struct inode *inode, struct file *file)
3780
{
3781
	return single_open(file, display_crc_ctl_show, inode->i_private);
3782 3783
}

3784
static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
D
Daniel Vetter 已提交
3785 3786
				 uint32_t *val)
{
3787 3788 3789 3790
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PIPE;

	switch (*source) {
D
Daniel Vetter 已提交
3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
		break;
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

3804 3805
static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
				     enum pipe pipe,
3806 3807
				     enum intel_pipe_crc_source *source)
{
3808
	struct drm_device *dev = &dev_priv->drm;
3809 3810
	struct intel_encoder *encoder;
	struct intel_crtc *crtc;
3811
	struct intel_digital_port *dig_port;
3812 3813 3814 3815
	int ret = 0;

	*source = INTEL_PIPE_CRC_SOURCE_PIPE;

3816
	drm_modeset_lock_all(dev);
3817
	for_each_intel_encoder(dev, encoder) {
3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829
		if (!encoder->base.crtc)
			continue;

		crtc = to_intel_crtc(encoder->base.crtc);

		if (crtc->pipe != pipe)
			continue;

		switch (encoder->type) {
		case INTEL_OUTPUT_TVOUT:
			*source = INTEL_PIPE_CRC_SOURCE_TV;
			break;
3830
		case INTEL_OUTPUT_DP:
3831
		case INTEL_OUTPUT_EDP:
3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847
			dig_port = enc_to_dig_port(&encoder->base);
			switch (dig_port->port) {
			case PORT_B:
				*source = INTEL_PIPE_CRC_SOURCE_DP_B;
				break;
			case PORT_C:
				*source = INTEL_PIPE_CRC_SOURCE_DP_C;
				break;
			case PORT_D:
				*source = INTEL_PIPE_CRC_SOURCE_DP_D;
				break;
			default:
				WARN(1, "nonexisting DP port %c\n",
				     port_name(dig_port->port));
				break;
			}
3848
			break;
3849 3850
		default:
			break;
3851 3852
		}
	}
3853
	drm_modeset_unlock_all(dev);
3854 3855 3856 3857

	return ret;
}

3858
static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3859 3860
				enum pipe pipe,
				enum intel_pipe_crc_source *source,
D
Daniel Vetter 已提交
3861 3862
				uint32_t *val)
{
3863 3864
	bool need_stable_symbols = false;

3865
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3866
		int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3867 3868 3869 3870 3871
		if (ret)
			return ret;
	}

	switch (*source) {
D
Daniel Vetter 已提交
3872 3873 3874 3875 3876
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_B:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3877
		need_stable_symbols = true;
D
Daniel Vetter 已提交
3878 3879 3880
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_C:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3881
		need_stable_symbols = true;
D
Daniel Vetter 已提交
3882
		break;
3883
	case INTEL_PIPE_CRC_SOURCE_DP_D:
3884
		if (!IS_CHERRYVIEW(dev_priv))
3885 3886 3887 3888
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
		need_stable_symbols = true;
		break;
D
Daniel Vetter 已提交
3889 3890 3891 3892 3893 3894 3895
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908
	/*
	 * When the pipe CRC tap point is after the transcoders we need
	 * to tweak symbol-level features to produce a deterministic series of
	 * symbols for a given frame. We need to reset those features only once
	 * a frame (instead of every nth symbol):
	 *   - DC-balance: used to ensure a better clock recovery from the data
	 *     link (SDVO)
	 *   - DisplayPort scrambling: used for EMI reduction
	 */
	if (need_stable_symbols) {
		uint32_t tmp = I915_READ(PORT_DFT2_G4X);

		tmp |= DC_BALANCE_RESET_VLV;
3909 3910
		switch (pipe) {
		case PIPE_A:
3911
			tmp |= PIPE_A_SCRAMBLE_RESET;
3912 3913
			break;
		case PIPE_B:
3914
			tmp |= PIPE_B_SCRAMBLE_RESET;
3915 3916 3917 3918 3919 3920 3921
			break;
		case PIPE_C:
			tmp |= PIPE_C_SCRAMBLE_RESET;
			break;
		default:
			return -EINVAL;
		}
3922 3923 3924
		I915_WRITE(PORT_DFT2_G4X, tmp);
	}

D
Daniel Vetter 已提交
3925 3926 3927
	return 0;
}

3928
static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3929 3930
				 enum pipe pipe,
				 enum intel_pipe_crc_source *source,
3931 3932
				 uint32_t *val)
{
3933 3934
	bool need_stable_symbols = false;

3935
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3936
		int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3937 3938 3939 3940 3941
		if (ret)
			return ret;
	}

	switch (*source) {
3942 3943 3944 3945
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
		break;
	case INTEL_PIPE_CRC_SOURCE_TV:
3946
		if (!SUPPORTS_TV(dev_priv))
3947 3948 3949 3950
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_B:
3951
		if (!IS_G4X(dev_priv))
3952 3953
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3954
		need_stable_symbols = true;
3955 3956
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_C:
3957
		if (!IS_G4X(dev_priv))
3958 3959
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3960
		need_stable_symbols = true;
3961 3962
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_D:
3963
		if (!IS_G4X(dev_priv))
3964 3965
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3966
		need_stable_symbols = true;
3967 3968 3969 3970 3971 3972 3973 3974
		break;
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986
	/*
	 * When the pipe CRC tap point is after the transcoders we need
	 * to tweak symbol-level features to produce a deterministic series of
	 * symbols for a given frame. We need to reset those features only once
	 * a frame (instead of every nth symbol):
	 *   - DC-balance: used to ensure a better clock recovery from the data
	 *     link (SDVO)
	 *   - DisplayPort scrambling: used for EMI reduction
	 */
	if (need_stable_symbols) {
		uint32_t tmp = I915_READ(PORT_DFT2_G4X);

3987
		WARN_ON(!IS_G4X(dev_priv));
3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999

		I915_WRITE(PORT_DFT_I9XX,
			   I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);

		if (pipe == PIPE_A)
			tmp |= PIPE_A_SCRAMBLE_RESET;
		else
			tmp |= PIPE_B_SCRAMBLE_RESET;

		I915_WRITE(PORT_DFT2_G4X, tmp);
	}

4000 4001 4002
	return 0;
}

4003
static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4004 4005 4006 4007
					 enum pipe pipe)
{
	uint32_t tmp = I915_READ(PORT_DFT2_G4X);

4008 4009
	switch (pipe) {
	case PIPE_A:
4010
		tmp &= ~PIPE_A_SCRAMBLE_RESET;
4011 4012
		break;
	case PIPE_B:
4013
		tmp &= ~PIPE_B_SCRAMBLE_RESET;
4014 4015 4016 4017 4018 4019 4020
		break;
	case PIPE_C:
		tmp &= ~PIPE_C_SCRAMBLE_RESET;
		break;
	default:
		return;
	}
4021 4022 4023 4024 4025 4026
	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
		tmp &= ~DC_BALANCE_RESET_VLV;
	I915_WRITE(PORT_DFT2_G4X, tmp);

}

4027
static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043
					 enum pipe pipe)
{
	uint32_t tmp = I915_READ(PORT_DFT2_G4X);

	if (pipe == PIPE_A)
		tmp &= ~PIPE_A_SCRAMBLE_RESET;
	else
		tmp &= ~PIPE_B_SCRAMBLE_RESET;
	I915_WRITE(PORT_DFT2_G4X, tmp);

	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
		I915_WRITE(PORT_DFT_I9XX,
			   I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
	}
}

4044
static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
4045 4046
				uint32_t *val)
{
4047 4048 4049 4050
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PIPE;

	switch (*source) {
4051 4052 4053 4054 4055 4056 4057 4058 4059
	case INTEL_PIPE_CRC_SOURCE_PLANE1:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
		break;
	case INTEL_PIPE_CRC_SOURCE_PLANE2:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
		break;
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
		break;
D
Daniel Vetter 已提交
4060
	case INTEL_PIPE_CRC_SOURCE_NONE:
4061 4062
		*val = 0;
		break;
D
Daniel Vetter 已提交
4063 4064
	default:
		return -EINVAL;
4065 4066 4067 4068 4069
	}

	return 0;
}

4070 4071
static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
					bool enable)
4072
{
4073
	struct drm_device *dev = &dev_priv->drm;
4074
	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
4075
	struct intel_crtc_state *pipe_config;
4076 4077
	struct drm_atomic_state *state;
	int ret = 0;
4078 4079

	drm_modeset_lock_all(dev);
4080 4081 4082 4083
	state = drm_atomic_state_alloc(dev);
	if (!state) {
		ret = -ENOMEM;
		goto out;
4084 4085
	}

4086 4087 4088 4089 4090 4091
	state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
	pipe_config = intel_atomic_get_crtc_state(state, crtc);
	if (IS_ERR(pipe_config)) {
		ret = PTR_ERR(pipe_config);
		goto out;
	}
4092

4093 4094 4095 4096
	pipe_config->pch_pfit.force_thru = enable;
	if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
	    pipe_config->pch_pfit.enabled != enable)
		pipe_config->base.connectors_changed = true;
4097

4098 4099 4100
	ret = drm_atomic_commit(state);
out:
	WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4101 4102
	drm_modeset_unlock_all(dev);
	drm_atomic_state_put(state);
4103 4104
}

4105
static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4106 4107
				enum pipe pipe,
				enum intel_pipe_crc_source *source,
4108 4109
				uint32_t *val)
{
4110 4111 4112 4113
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PF;

	switch (*source) {
4114 4115 4116 4117 4118 4119 4120
	case INTEL_PIPE_CRC_SOURCE_PLANE1:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
		break;
	case INTEL_PIPE_CRC_SOURCE_PLANE2:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
		break;
	case INTEL_PIPE_CRC_SOURCE_PF:
4121 4122
		if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
			hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4123

4124 4125
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
		break;
D
Daniel Vetter 已提交
4126
	case INTEL_PIPE_CRC_SOURCE_NONE:
4127 4128
		*val = 0;
		break;
D
Daniel Vetter 已提交
4129 4130
	default:
		return -EINVAL;
4131 4132 4133 4134 4135
	}

	return 0;
}

4136 4137
static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
			       enum pipe pipe,
4138 4139
			       enum intel_pipe_crc_source source)
{
4140
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4141
	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
4142
	enum intel_display_power_domain power_domain;
4143
	u32 val = 0; /* shut up gcc */
4144
	int ret;
4145

4146 4147 4148
	if (pipe_crc->source == source)
		return 0;

4149 4150 4151 4152
	/* forbid changing the source without going back to 'none' */
	if (pipe_crc->source && source)
		return -EINVAL;

4153 4154
	power_domain = POWER_DOMAIN_PIPE(pipe);
	if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4155 4156 4157 4158
		DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
		return -EIO;
	}

4159
	if (IS_GEN2(dev_priv))
4160
		ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4161 4162 4163 4164 4165
	else if (INTEL_GEN(dev_priv) < 5)
		ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
	else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4166
		ret = ilk_pipe_crc_ctl_reg(&source, &val);
4167
	else
4168
		ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4169 4170

	if (ret != 0)
4171
		goto out;
4172

4173 4174
	/* none -> real source transition */
	if (source) {
4175 4176
		struct intel_pipe_crc_entry *entries;

4177 4178 4179
		DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
				 pipe_name(pipe), pipe_crc_source_name(source));

4180 4181
		entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
				  sizeof(pipe_crc->entries[0]),
4182
				  GFP_KERNEL);
4183 4184 4185 4186
		if (!entries) {
			ret = -ENOMEM;
			goto out;
		}
4187

4188 4189 4190 4191 4192 4193 4194 4195
		/*
		 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
		 * enabled and disabled dynamically based on package C states,
		 * user space can't make reliable use of the CRCs, so let's just
		 * completely disable it.
		 */
		hsw_disable_ips(crtc);

4196
		spin_lock_irq(&pipe_crc->lock);
4197
		kfree(pipe_crc->entries);
4198
		pipe_crc->entries = entries;
4199 4200 4201
		pipe_crc->head = 0;
		pipe_crc->tail = 0;
		spin_unlock_irq(&pipe_crc->lock);
4202 4203
	}

4204
	pipe_crc->source = source;
4205 4206 4207 4208

	I915_WRITE(PIPE_CRC_CTL(pipe), val);
	POSTING_READ(PIPE_CRC_CTL(pipe));

4209 4210
	/* real source -> none transition */
	if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4211
		struct intel_pipe_crc_entry *entries;
4212 4213
		struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
								  pipe);
4214

4215 4216 4217
		DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
				 pipe_name(pipe));

4218
		drm_modeset_lock(&crtc->base.mutex, NULL);
4219
		if (crtc->base.state->active)
4220
			intel_wait_for_vblank(dev_priv, pipe);
4221
		drm_modeset_unlock(&crtc->base.mutex);
4222

4223 4224
		spin_lock_irq(&pipe_crc->lock);
		entries = pipe_crc->entries;
4225
		pipe_crc->entries = NULL;
4226 4227
		pipe_crc->head = 0;
		pipe_crc->tail = 0;
4228 4229 4230
		spin_unlock_irq(&pipe_crc->lock);

		kfree(entries);
4231

4232 4233 4234 4235 4236 4237
		if (IS_G4X(dev_priv))
			g4x_undo_pipe_scramble_reset(dev_priv, pipe);
		else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
			vlv_undo_pipe_scramble_reset(dev_priv, pipe);
		else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
			hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4238 4239

		hsw_enable_ips(crtc);
4240 4241
	}

4242 4243 4244 4245 4246 4247
	ret = 0;

out:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
4248 4249 4250 4251
}

/*
 * Parse pipe CRC command strings:
4252 4253 4254
 *   command: wsp* object wsp+ name wsp+ source wsp*
 *   object: 'pipe'
 *   name: (A | B | C)
4255 4256 4257 4258
 *   source: (none | plane1 | plane2 | pf)
 *   wsp: (#0x20 | #0x9 | #0xA)+
 *
 * eg.:
4259 4260
 *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
 *  "pipe A none"    ->  Stop CRC
4261
 */
4262
static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292
{
	int n_words = 0;

	while (*buf) {
		char *end;

		/* skip leading white space */
		buf = skip_spaces(buf);
		if (!*buf)
			break;	/* end of buffer */

		/* find end of word */
		for (end = buf; *end && !isspace(*end); end++)
			;

		if (n_words == max_words) {
			DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
					 max_words);
			return -EINVAL;	/* ran out of words[] before bytes */
		}

		if (*end)
			*end++ = '\0';
		words[n_words++] = buf;
		buf = end;
	}

	return n_words;
}

4293 4294 4295 4296
enum intel_pipe_crc_object {
	PIPE_CRC_OBJECT_PIPE,
};

D
Daniel Vetter 已提交
4297
static const char * const pipe_crc_objects[] = {
4298 4299 4300 4301
	"pipe",
};

static int
4302
display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4303 4304 4305 4306 4307
{
	int i;

	for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
		if (!strcmp(buf, pipe_crc_objects[i])) {
4308
			*o = i;
4309 4310 4311 4312 4313 4314
			return 0;
		    }

	return -EINVAL;
}

4315
static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327
{
	const char name = buf[0];

	if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
		return -EINVAL;

	*pipe = name - 'A';

	return 0;
}

static int
4328
display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4329 4330 4331 4332 4333
{
	int i;

	for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
		if (!strcmp(buf, pipe_crc_sources[i])) {
4334
			*s = i;
4335 4336 4337 4338 4339 4340
			return 0;
		    }

	return -EINVAL;
}

4341 4342
static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
				 char *buf, size_t len)
4343
{
4344
#define N_WORDS 3
4345
	int n_words;
4346
	char *words[N_WORDS];
4347
	enum pipe pipe;
4348
	enum intel_pipe_crc_object object;
4349 4350
	enum intel_pipe_crc_source source;

4351
	n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4352 4353 4354 4355 4356 4357
	if (n_words != N_WORDS) {
		DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
				 N_WORDS);
		return -EINVAL;
	}

4358
	if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4359
		DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4360 4361 4362
		return -EINVAL;
	}

4363
	if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4364
		DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4365 4366 4367
		return -EINVAL;
	}

4368
	if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4369
		DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4370 4371 4372
		return -EINVAL;
	}

4373
	return pipe_crc_set_source(dev_priv, pipe, source);
4374 4375
}

4376 4377
static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
				     size_t len, loff_t *offp)
4378 4379
{
	struct seq_file *m = file->private_data;
4380
	struct drm_i915_private *dev_priv = m->private;
4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402
	char *tmpbuf;
	int ret;

	if (len == 0)
		return 0;

	if (len > PAGE_SIZE - 1) {
		DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
				 PAGE_SIZE);
		return -E2BIG;
	}

	tmpbuf = kmalloc(len + 1, GFP_KERNEL);
	if (!tmpbuf)
		return -ENOMEM;

	if (copy_from_user(tmpbuf, ubuf, len)) {
		ret = -EFAULT;
		goto out;
	}
	tmpbuf[len] = '\0';

4403
	ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4404 4405 4406 4407 4408 4409 4410 4411 4412 4413

out:
	kfree(tmpbuf);
	if (ret < 0)
		return ret;

	*offp += len;
	return len;
}

4414
static const struct file_operations i915_display_crc_ctl_fops = {
4415
	.owner = THIS_MODULE,
4416
	.open = display_crc_ctl_open,
4417 4418 4419
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
4420
	.write = display_crc_ctl_write
4421 4422
};

4423
static ssize_t i915_displayport_test_active_write(struct file *file,
4424 4425
						  const char __user *ubuf,
						  size_t len, loff_t *offp)
4426 4427 4428 4429 4430 4431 4432 4433 4434
{
	char *input_buffer;
	int status = 0;
	struct drm_device *dev;
	struct drm_connector *connector;
	struct list_head *connector_list;
	struct intel_dp *intel_dp;
	int val = 0;

4435
	dev = ((struct seq_file *)file->private_data)->private;
4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458

	connector_list = &dev->mode_config.connector_list;

	if (len == 0)
		return 0;

	input_buffer = kmalloc(len + 1, GFP_KERNEL);
	if (!input_buffer)
		return -ENOMEM;

	if (copy_from_user(input_buffer, ubuf, len)) {
		status = -EFAULT;
		goto out;
	}

	input_buffer[len] = '\0';
	DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);

	list_for_each_entry(connector, connector_list, head) {
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

4459
		if (connector->status == connector_status_connected &&
4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			status = kstrtoint(input_buffer, 10, &val);
			if (status < 0)
				goto out;
			DRM_DEBUG_DRIVER("Got %d for test active\n", val);
			/* To prevent erroneous activation of the compliance
			 * testing code, only accept an actual value of 1 here
			 */
			if (val == 1)
				intel_dp->compliance_test_active = 1;
			else
				intel_dp->compliance_test_active = 0;
		}
	}
out:
	kfree(input_buffer);
	if (status < 0)
		return status;

	*offp += len;
	return len;
}

static int i915_displayport_test_active_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
	struct drm_connector *connector;
	struct list_head *connector_list = &dev->mode_config.connector_list;
	struct intel_dp *intel_dp;

	list_for_each_entry(connector, connector_list, head) {
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

		if (connector->status == connector_status_connected &&
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			if (intel_dp->compliance_test_active)
				seq_puts(m, "1");
			else
				seq_puts(m, "0");
		} else
			seq_puts(m, "0");
	}

	return 0;
}

static int i915_displayport_test_active_open(struct inode *inode,
4511
					     struct file *file)
4512
{
4513
	struct drm_i915_private *dev_priv = inode->i_private;
4514

4515 4516
	return single_open(file, i915_displayport_test_active_show,
			   &dev_priv->drm);
4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550
}

static const struct file_operations i915_displayport_test_active_fops = {
	.owner = THIS_MODULE,
	.open = i915_displayport_test_active_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = i915_displayport_test_active_write
};

static int i915_displayport_test_data_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
	struct drm_connector *connector;
	struct list_head *connector_list = &dev->mode_config.connector_list;
	struct intel_dp *intel_dp;

	list_for_each_entry(connector, connector_list, head) {
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

		if (connector->status == connector_status_connected &&
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			seq_printf(m, "%lx", intel_dp->compliance_test_data);
		} else
			seq_puts(m, "0");
	}

	return 0;
}
static int i915_displayport_test_data_open(struct inode *inode,
4551
					   struct file *file)
4552
{
4553
	struct drm_i915_private *dev_priv = inode->i_private;
4554

4555 4556
	return single_open(file, i915_displayport_test_data_show,
			   &dev_priv->drm);
4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592
}

static const struct file_operations i915_displayport_test_data_fops = {
	.owner = THIS_MODULE,
	.open = i915_displayport_test_data_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release
};

static int i915_displayport_test_type_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;
	struct drm_connector *connector;
	struct list_head *connector_list = &dev->mode_config.connector_list;
	struct intel_dp *intel_dp;

	list_for_each_entry(connector, connector_list, head) {
		if (connector->connector_type !=
		    DRM_MODE_CONNECTOR_DisplayPort)
			continue;

		if (connector->status == connector_status_connected &&
		    connector->encoder != NULL) {
			intel_dp = enc_to_intel_dp(connector->encoder);
			seq_printf(m, "%02lx", intel_dp->compliance_test_type);
		} else
			seq_puts(m, "0");
	}

	return 0;
}

static int i915_displayport_test_type_open(struct inode *inode,
				       struct file *file)
{
4593
	struct drm_i915_private *dev_priv = inode->i_private;
4594

4595 4596
	return single_open(file, i915_displayport_test_type_show,
			   &dev_priv->drm);
4597 4598 4599 4600 4601 4602 4603 4604 4605 4606
}

static const struct file_operations i915_displayport_test_type_fops = {
	.owner = THIS_MODULE,
	.open = i915_displayport_test_type_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release
};

4607
static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4608
{
4609 4610
	struct drm_i915_private *dev_priv = m->private;
	struct drm_device *dev = &dev_priv->drm;
4611
	int level;
4612 4613
	int num_levels;

4614
	if (IS_CHERRYVIEW(dev_priv))
4615
		num_levels = 3;
4616
	else if (IS_VALLEYVIEW(dev_priv))
4617 4618
		num_levels = 1;
	else
4619
		num_levels = ilk_wm_max_level(dev_priv) + 1;
4620 4621 4622 4623 4624 4625

	drm_modeset_lock_all(dev);

	for (level = 0; level < num_levels; level++) {
		unsigned int latency = wm[level];

4626 4627
		/*
		 * - WM1+ latency values in 0.5us units
4628
		 * - latencies are in us on gen9/vlv/chv
4629
		 */
4630 4631
		if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
		    IS_CHERRYVIEW(dev_priv))
4632 4633
			latency *= 10;
		else if (level > 0)
4634 4635 4636
			latency *= 5;

		seq_printf(m, "WM%d %u (%u.%u usec)\n",
4637
			   level, wm[level], latency / 10, latency % 10);
4638 4639 4640 4641 4642 4643 4644
	}

	drm_modeset_unlock_all(dev);
}

static int pri_wm_latency_show(struct seq_file *m, void *data)
{
4645
	struct drm_i915_private *dev_priv = m->private;
4646 4647
	const uint16_t *latencies;

4648
	if (INTEL_GEN(dev_priv) >= 9)
4649 4650
		latencies = dev_priv->wm.skl_latency;
	else
4651
		latencies = dev_priv->wm.pri_latency;
4652

4653
	wm_latency_show(m, latencies);
4654 4655 4656 4657 4658 4659

	return 0;
}

static int spr_wm_latency_show(struct seq_file *m, void *data)
{
4660
	struct drm_i915_private *dev_priv = m->private;
4661 4662
	const uint16_t *latencies;

4663
	if (INTEL_GEN(dev_priv) >= 9)
4664 4665
		latencies = dev_priv->wm.skl_latency;
	else
4666
		latencies = dev_priv->wm.spr_latency;
4667

4668
	wm_latency_show(m, latencies);
4669 4670 4671 4672 4673 4674

	return 0;
}

static int cur_wm_latency_show(struct seq_file *m, void *data)
{
4675
	struct drm_i915_private *dev_priv = m->private;
4676 4677
	const uint16_t *latencies;

4678
	if (INTEL_GEN(dev_priv) >= 9)
4679 4680
		latencies = dev_priv->wm.skl_latency;
	else
4681
		latencies = dev_priv->wm.cur_latency;
4682

4683
	wm_latency_show(m, latencies);
4684 4685 4686 4687 4688 4689

	return 0;
}

static int pri_wm_latency_open(struct inode *inode, struct file *file)
{
4690
	struct drm_i915_private *dev_priv = inode->i_private;
4691

4692
	if (INTEL_GEN(dev_priv) < 5)
4693 4694
		return -ENODEV;

4695
	return single_open(file, pri_wm_latency_show, dev_priv);
4696 4697 4698 4699
}

static int spr_wm_latency_open(struct inode *inode, struct file *file)
{
4700
	struct drm_i915_private *dev_priv = inode->i_private;
4701

4702
	if (HAS_GMCH_DISPLAY(dev_priv))
4703 4704
		return -ENODEV;

4705
	return single_open(file, spr_wm_latency_show, dev_priv);
4706 4707 4708 4709
}

static int cur_wm_latency_open(struct inode *inode, struct file *file)
{
4710
	struct drm_i915_private *dev_priv = inode->i_private;
4711

4712
	if (HAS_GMCH_DISPLAY(dev_priv))
4713 4714
		return -ENODEV;

4715
	return single_open(file, cur_wm_latency_show, dev_priv);
4716 4717 4718
}

static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4719
				size_t len, loff_t *offp, uint16_t wm[8])
4720 4721
{
	struct seq_file *m = file->private_data;
4722 4723
	struct drm_i915_private *dev_priv = m->private;
	struct drm_device *dev = &dev_priv->drm;
4724
	uint16_t new[8] = { 0 };
4725
	int num_levels;
4726 4727 4728 4729
	int level;
	int ret;
	char tmp[32];

4730
	if (IS_CHERRYVIEW(dev_priv))
4731
		num_levels = 3;
4732
	else if (IS_VALLEYVIEW(dev_priv))
4733 4734
		num_levels = 1;
	else
4735
		num_levels = ilk_wm_max_level(dev_priv) + 1;
4736

4737 4738 4739 4740 4741 4742 4743 4744
	if (len >= sizeof(tmp))
		return -EINVAL;

	if (copy_from_user(tmp, ubuf, len))
		return -EFAULT;

	tmp[len] = '\0';

4745 4746 4747
	ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
		     &new[0], &new[1], &new[2], &new[3],
		     &new[4], &new[5], &new[6], &new[7]);
4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765
	if (ret != num_levels)
		return -EINVAL;

	drm_modeset_lock_all(dev);

	for (level = 0; level < num_levels; level++)
		wm[level] = new[level];

	drm_modeset_unlock_all(dev);

	return len;
}


static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
4766
	struct drm_i915_private *dev_priv = m->private;
4767
	uint16_t *latencies;
4768

4769
	if (INTEL_GEN(dev_priv) >= 9)
4770 4771
		latencies = dev_priv->wm.skl_latency;
	else
4772
		latencies = dev_priv->wm.pri_latency;
4773 4774

	return wm_latency_write(file, ubuf, len, offp, latencies);
4775 4776 4777 4778 4779 4780
}

static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
4781
	struct drm_i915_private *dev_priv = m->private;
4782
	uint16_t *latencies;
4783

4784
	if (INTEL_GEN(dev_priv) >= 9)
4785 4786
		latencies = dev_priv->wm.skl_latency;
	else
4787
		latencies = dev_priv->wm.spr_latency;
4788 4789

	return wm_latency_write(file, ubuf, len, offp, latencies);
4790 4791 4792 4793 4794 4795
}

static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
4796
	struct drm_i915_private *dev_priv = m->private;
4797 4798
	uint16_t *latencies;

4799
	if (INTEL_GEN(dev_priv) >= 9)
4800 4801
		latencies = dev_priv->wm.skl_latency;
	else
4802
		latencies = dev_priv->wm.cur_latency;
4803

4804
	return wm_latency_write(file, ubuf, len, offp, latencies);
4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833
}

static const struct file_operations i915_pri_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = pri_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = pri_wm_latency_write
};

static const struct file_operations i915_spr_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = spr_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = spr_wm_latency_write
};

static const struct file_operations i915_cur_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = cur_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = cur_wm_latency_write
};

4834 4835
static int
i915_wedged_get(void *data, u64 *val)
4836
{
4837
	struct drm_i915_private *dev_priv = data;
4838

4839
	*val = i915_terminally_wedged(&dev_priv->gpu_error);
4840

4841
	return 0;
4842 4843
}

4844 4845
static int
i915_wedged_set(void *data, u64 val)
4846
{
4847
	struct drm_i915_private *dev_priv = data;
4848

4849 4850 4851 4852 4853 4854 4855 4856
	/*
	 * There is no safeguard against this debugfs entry colliding
	 * with the hangcheck calling same i915_handle_error() in
	 * parallel, causing an explosion. For now we assume that the
	 * test harness is responsible enough not to inject gpu hangs
	 * while it is writing to 'i915_wedged'
	 */

4857
	if (i915_reset_in_progress(&dev_priv->gpu_error))
4858 4859
		return -EAGAIN;

4860
	i915_handle_error(dev_priv, val,
4861
			  "Manually setting wedged to %llu", val);
4862

4863
	return 0;
4864 4865
}

4866 4867
DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
			i915_wedged_get, i915_wedged_set,
4868
			"%llu\n");
4869

4870 4871 4872
static int
i915_ring_missed_irq_get(void *data, u64 *val)
{
4873
	struct drm_i915_private *dev_priv = data;
4874 4875 4876 4877 4878 4879 4880 4881

	*val = dev_priv->gpu_error.missed_irq_rings;
	return 0;
}

static int
i915_ring_missed_irq_set(void *data, u64 val)
{
4882 4883
	struct drm_i915_private *dev_priv = data;
	struct drm_device *dev = &dev_priv->drm;
4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902
	int ret;

	/* Lock against concurrent debugfs callers */
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
	dev_priv->gpu_error.missed_irq_rings = val;
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
			i915_ring_missed_irq_get, i915_ring_missed_irq_set,
			"0x%08llx\n");

static int
i915_ring_test_irq_get(void *data, u64 *val)
{
4903
	struct drm_i915_private *dev_priv = data;
4904 4905 4906 4907 4908 4909 4910 4911 4912

	*val = dev_priv->gpu_error.test_irq_rings;

	return 0;
}

static int
i915_ring_test_irq_set(void *data, u64 val)
{
4913
	struct drm_i915_private *dev_priv = data;
4914

4915
	val &= INTEL_INFO(dev_priv)->ring_mask;
4916 4917 4918 4919 4920 4921 4922 4923 4924 4925
	DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
	dev_priv->gpu_error.test_irq_rings = val;

	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
			i915_ring_test_irq_get, i915_ring_test_irq_set,
			"0x%08llx\n");

4926 4927 4928 4929
#define DROP_UNBOUND 0x1
#define DROP_BOUND 0x2
#define DROP_RETIRE 0x4
#define DROP_ACTIVE 0x8
4930 4931 4932 4933 4934 4935
#define DROP_FREED 0x10
#define DROP_ALL (DROP_UNBOUND	| \
		  DROP_BOUND	| \
		  DROP_RETIRE	| \
		  DROP_ACTIVE	| \
		  DROP_FREED)
4936 4937
static int
i915_drop_caches_get(void *data, u64 *val)
4938
{
4939
	*val = DROP_ALL;
4940

4941
	return 0;
4942 4943
}

4944 4945
static int
i915_drop_caches_set(void *data, u64 val)
4946
{
4947 4948
	struct drm_i915_private *dev_priv = data;
	struct drm_device *dev = &dev_priv->drm;
4949
	int ret;
4950

4951
	DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4952 4953 4954 4955 4956 4957 4958 4959

	/* No need to check and wait for gpu resets, only libdrm auto-restarts
	 * on ioctls on -EAGAIN. */
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	if (val & DROP_ACTIVE) {
4960 4961 4962
		ret = i915_gem_wait_for_idle(dev_priv,
					     I915_WAIT_INTERRUPTIBLE |
					     I915_WAIT_LOCKED);
4963 4964 4965 4966 4967
		if (ret)
			goto unlock;
	}

	if (val & (DROP_RETIRE | DROP_ACTIVE))
4968
		i915_gem_retire_requests(dev_priv);
4969

4970 4971
	if (val & DROP_BOUND)
		i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4972

4973 4974
	if (val & DROP_UNBOUND)
		i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4975 4976 4977 4978

unlock:
	mutex_unlock(&dev->struct_mutex);

4979 4980 4981 4982 4983
	if (val & DROP_FREED) {
		synchronize_rcu();
		flush_work(&dev_priv->mm.free_work);
	}

4984
	return ret;
4985 4986
}

4987 4988 4989
DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
			i915_drop_caches_get, i915_drop_caches_set,
			"0x%08llx\n");
4990

4991 4992
static int
i915_max_freq_get(void *data, u64 *val)
4993
{
4994
	struct drm_i915_private *dev_priv = data;
4995

4996
	if (INTEL_GEN(dev_priv) < 6)
4997 4998
		return -ENODEV;

4999
	*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
5000
	return 0;
5001 5002
}

5003 5004
static int
i915_max_freq_set(void *data, u64 val)
5005
{
5006
	struct drm_i915_private *dev_priv = data;
5007
	u32 hw_max, hw_min;
5008
	int ret;
5009

5010
	if (INTEL_GEN(dev_priv) < 6)
5011
		return -ENODEV;
5012

5013
	DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
5014

5015
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5016 5017 5018
	if (ret)
		return ret;

5019 5020 5021
	/*
	 * Turbo will still be enabled, but won't go above the set value.
	 */
5022
	val = intel_freq_opcode(dev_priv, val);
J
Jeff McGee 已提交
5023

5024 5025
	hw_max = dev_priv->rps.max_freq;
	hw_min = dev_priv->rps.min_freq;
J
Jeff McGee 已提交
5026

5027
	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
J
Jeff McGee 已提交
5028 5029
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
5030 5031
	}

5032
	dev_priv->rps.max_freq_softlimit = val;
J
Jeff McGee 已提交
5033

5034
	intel_set_rps(dev_priv, val);
J
Jeff McGee 已提交
5035

5036
	mutex_unlock(&dev_priv->rps.hw_lock);
5037

5038
	return 0;
5039 5040
}

5041 5042
DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
			i915_max_freq_get, i915_max_freq_set,
5043
			"%llu\n");
5044

5045 5046
static int
i915_min_freq_get(void *data, u64 *val)
5047
{
5048
	struct drm_i915_private *dev_priv = data;
5049

5050
	if (INTEL_GEN(dev_priv) < 6)
5051 5052
		return -ENODEV;

5053
	*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5054
	return 0;
5055 5056
}

5057 5058
static int
i915_min_freq_set(void *data, u64 val)
5059
{
5060
	struct drm_i915_private *dev_priv = data;
5061
	u32 hw_max, hw_min;
5062
	int ret;
5063

5064
	if (INTEL_GEN(dev_priv) < 6)
5065
		return -ENODEV;
5066

5067
	DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5068

5069
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5070 5071 5072
	if (ret)
		return ret;

5073 5074 5075
	/*
	 * Turbo will still be enabled, but won't go below the set value.
	 */
5076
	val = intel_freq_opcode(dev_priv, val);
J
Jeff McGee 已提交
5077

5078 5079
	hw_max = dev_priv->rps.max_freq;
	hw_min = dev_priv->rps.min_freq;
J
Jeff McGee 已提交
5080

5081 5082
	if (val < hw_min ||
	    val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
J
Jeff McGee 已提交
5083 5084
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
5085
	}
J
Jeff McGee 已提交
5086

5087
	dev_priv->rps.min_freq_softlimit = val;
J
Jeff McGee 已提交
5088

5089
	intel_set_rps(dev_priv, val);
J
Jeff McGee 已提交
5090

5091
	mutex_unlock(&dev_priv->rps.hw_lock);
5092

5093
	return 0;
5094 5095
}

5096 5097
DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
			i915_min_freq_get, i915_min_freq_set,
5098
			"%llu\n");
5099

5100 5101
static int
i915_cache_sharing_get(void *data, u64 *val)
5102
{
5103
	struct drm_i915_private *dev_priv = data;
5104 5105
	u32 snpcr;

5106
	if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5107 5108
		return -ENODEV;

5109
	intel_runtime_pm_get(dev_priv);
5110

5111
	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5112 5113

	intel_runtime_pm_put(dev_priv);
5114

5115
	*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5116

5117
	return 0;
5118 5119
}

5120 5121
static int
i915_cache_sharing_set(void *data, u64 val)
5122
{
5123
	struct drm_i915_private *dev_priv = data;
5124 5125
	u32 snpcr;

5126
	if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5127 5128
		return -ENODEV;

5129
	if (val > 3)
5130 5131
		return -EINVAL;

5132
	intel_runtime_pm_get(dev_priv);
5133
	DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5134 5135 5136 5137 5138 5139 5140

	/* Update the cache sharing policy here as well */
	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
	snpcr &= ~GEN6_MBC_SNPCR_MASK;
	snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);

5141
	intel_runtime_pm_put(dev_priv);
5142
	return 0;
5143 5144
}

5145 5146 5147
DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
			i915_cache_sharing_get, i915_cache_sharing_set,
			"%llu\n");
5148

5149
static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5150
					  struct sseu_dev_info *sseu)
5151
{
5152
	int ss_max = 2;
5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167
	int ss;
	u32 sig1[ss_max], sig2[ss_max];

	sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
	sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
	sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
	sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);

	for (ss = 0; ss < ss_max; ss++) {
		unsigned int eu_cnt;

		if (sig1[ss] & CHV_SS_PG_ENABLE)
			/* skip disabled subslice */
			continue;

5168
		sseu->slice_mask = BIT(0);
5169
		sseu->subslice_mask |= BIT(ss);
5170 5171 5172 5173
		eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
			 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
			 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
			 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5174 5175 5176
		sseu->eu_total += eu_cnt;
		sseu->eu_per_subslice = max_t(unsigned int,
					      sseu->eu_per_subslice, eu_cnt);
5177 5178 5179
	}
}

5180
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5181
				    struct sseu_dev_info *sseu)
5182
{
5183
	int s_max = 3, ss_max = 4;
5184 5185 5186
	int s, ss;
	u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];

5187
	/* BXT has a single slice and at most 3 subslices. */
5188
	if (IS_BROXTON(dev_priv)) {
5189 5190 5191 5192 5193 5194 5195 5196 5197 5198
		s_max = 1;
		ss_max = 3;
	}

	for (s = 0; s < s_max; s++) {
		s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
		eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
		eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
	}

5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212
	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
		     GEN9_PGCTL_SSA_EU19_ACK |
		     GEN9_PGCTL_SSA_EU210_ACK |
		     GEN9_PGCTL_SSA_EU311_ACK;
	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
		     GEN9_PGCTL_SSB_EU19_ACK |
		     GEN9_PGCTL_SSB_EU210_ACK |
		     GEN9_PGCTL_SSB_EU311_ACK;

	for (s = 0; s < s_max; s++) {
		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
			/* skip disabled slice */
			continue;

5213
		sseu->slice_mask |= BIT(s);
5214

5215
		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5216 5217
			sseu->subslice_mask =
				INTEL_INFO(dev_priv)->sseu.subslice_mask;
5218

5219 5220 5221
		for (ss = 0; ss < ss_max; ss++) {
			unsigned int eu_cnt;

5222 5223 5224 5225
			if (IS_BROXTON(dev_priv)) {
				if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
					/* skip disabled subslice */
					continue;
5226

5227 5228
				sseu->subslice_mask |= BIT(ss);
			}
5229

5230 5231
			eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
					       eu_mask[ss%2]);
5232 5233 5234 5235
			sseu->eu_total += eu_cnt;
			sseu->eu_per_subslice = max_t(unsigned int,
						      sseu->eu_per_subslice,
						      eu_cnt);
5236 5237 5238 5239
		}
	}
}

5240
static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5241
					 struct sseu_dev_info *sseu)
5242 5243
{
	u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5244
	int s;
5245

5246
	sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5247

5248
	if (sseu->slice_mask) {
5249
		sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5250 5251
		sseu->eu_per_subslice =
				INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5252 5253
		sseu->eu_total = sseu->eu_per_subslice *
				 sseu_subslice_total(sseu);
5254 5255

		/* subtract fused off EU(s) from enabled slice(s) */
5256
		for (s = 0; s < fls(sseu->slice_mask); s++) {
5257 5258
			u8 subslice_7eu =
				INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5259

5260
			sseu->eu_total -= hweight8(subslice_7eu);
5261 5262 5263 5264
		}
	}
}

5265 5266 5267 5268 5269 5270
static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
				 const struct sseu_dev_info *sseu)
{
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
	const char *type = is_available_info ? "Available" : "Enabled";

5271 5272
	seq_printf(m, "  %s Slice Mask: %04x\n", type,
		   sseu->slice_mask);
5273
	seq_printf(m, "  %s Slice Total: %u\n", type,
5274
		   hweight8(sseu->slice_mask));
5275
	seq_printf(m, "  %s Subslice Total: %u\n", type,
5276
		   sseu_subslice_total(sseu));
5277 5278
	seq_printf(m, "  %s Subslice Mask: %04x\n", type,
		   sseu->subslice_mask);
5279
	seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5280
		   hweight8(sseu->subslice_mask));
5281 5282 5283 5284 5285 5286 5287 5288 5289 5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300
	seq_printf(m, "  %s EU Total: %u\n", type,
		   sseu->eu_total);
	seq_printf(m, "  %s EU Per Subslice: %u\n", type,
		   sseu->eu_per_subslice);

	if (!is_available_info)
		return;

	seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
	if (HAS_POOLED_EU(dev_priv))
		seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);

	seq_printf(m, "  Has Slice Power Gating: %s\n",
		   yesno(sseu->has_slice_pg));
	seq_printf(m, "  Has Subslice Power Gating: %s\n",
		   yesno(sseu->has_subslice_pg));
	seq_printf(m, "  Has EU Power Gating: %s\n",
		   yesno(sseu->has_eu_pg));
}

5301 5302
static int i915_sseu_status(struct seq_file *m, void *unused)
{
5303
	struct drm_i915_private *dev_priv = node_to_i915(m->private);
5304
	struct sseu_dev_info sseu;
5305

5306
	if (INTEL_GEN(dev_priv) < 8)
5307 5308 5309
		return -ENODEV;

	seq_puts(m, "SSEU Device Info\n");
5310
	i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5311

5312
	seq_puts(m, "SSEU Device Status\n");
5313
	memset(&sseu, 0, sizeof(sseu));
5314 5315 5316

	intel_runtime_pm_get(dev_priv);

5317
	if (IS_CHERRYVIEW(dev_priv)) {
5318
		cherryview_sseu_device_status(dev_priv, &sseu);
5319
	} else if (IS_BROADWELL(dev_priv)) {
5320
		broadwell_sseu_device_status(dev_priv, &sseu);
5321
	} else if (INTEL_GEN(dev_priv) >= 9) {
5322
		gen9_sseu_device_status(dev_priv, &sseu);
5323
	}
5324 5325 5326

	intel_runtime_pm_put(dev_priv);

5327
	i915_print_sseu_info(m, false, &sseu);
5328

5329 5330 5331
	return 0;
}

5332 5333
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
5334
	struct drm_i915_private *dev_priv = inode->i_private;
5335

5336
	if (INTEL_GEN(dev_priv) < 6)
5337 5338
		return 0;

5339
	intel_runtime_pm_get(dev_priv);
5340
	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5341 5342 5343 5344

	return 0;
}

5345
static int i915_forcewake_release(struct inode *inode, struct file *file)
5346
{
5347
	struct drm_i915_private *dev_priv = inode->i_private;
5348

5349
	if (INTEL_GEN(dev_priv) < 6)
5350 5351
		return 0;

5352
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5353
	intel_runtime_pm_put(dev_priv);
5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368

	return 0;
}

static const struct file_operations i915_forcewake_fops = {
	.owner = THIS_MODULE,
	.open = i915_forcewake_open,
	.release = i915_forcewake_release,
};

static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
{
	struct dentry *ent;

	ent = debugfs_create_file("i915_forcewake_user",
B
Ben Widawsky 已提交
5369
				  S_IRUSR,
5370
				  root, to_i915(minor->dev),
5371
				  &i915_forcewake_fops);
5372 5373
	if (!ent)
		return -ENOMEM;
5374

B
Ben Widawsky 已提交
5375
	return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5376 5377
}

5378 5379 5380 5381
static int i915_debugfs_create(struct dentry *root,
			       struct drm_minor *minor,
			       const char *name,
			       const struct file_operations *fops)
5382 5383 5384
{
	struct dentry *ent;

5385
	ent = debugfs_create_file(name,
5386
				  S_IRUGO | S_IWUSR,
5387
				  root, to_i915(minor->dev),
5388
				  fops);
5389 5390
	if (!ent)
		return -ENOMEM;
5391

5392
	return drm_add_fake_info_node(minor, ent, fops);
5393 5394
}

5395
static const struct drm_info_list i915_debugfs_list[] = {
C
Chris Wilson 已提交
5396
	{"i915_capabilities", i915_capabilities, 0},
5397
	{"i915_gem_objects", i915_gem_object_info, 0},
5398
	{"i915_gem_gtt", i915_gem_gtt_info, 0},
5399
	{"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5400
	{"i915_gem_stolen", i915_gem_stolen_list_info },
5401
	{"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5402 5403
	{"i915_gem_request", i915_gem_request_info, 0},
	{"i915_gem_seqno", i915_gem_seqno_info, 0},
5404
	{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5405
	{"i915_gem_interrupt", i915_interrupt_info, 0},
5406 5407 5408
	{"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
	{"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
	{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
X
Xiang, Haihao 已提交
5409
	{"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5410
	{"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5411
	{"i915_guc_info", i915_guc_info, 0},
5412
	{"i915_guc_load_status", i915_guc_load_status_info, 0},
A
Alex Dai 已提交
5413
	{"i915_guc_log_dump", i915_guc_log_dump, 0},
5414
	{"i915_frequency_info", i915_frequency_info, 0},
5415
	{"i915_hangcheck_info", i915_hangcheck_info, 0},
5416
	{"i915_drpc_info", i915_drpc_info, 0},
5417
	{"i915_emon_status", i915_emon_status, 0},
5418
	{"i915_ring_freq_table", i915_ring_freq_table, 0},
5419
	{"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5420
	{"i915_fbc_status", i915_fbc_status, 0},
5421
	{"i915_ips_status", i915_ips_status, 0},
5422
	{"i915_sr_status", i915_sr_status, 0},
5423
	{"i915_opregion", i915_opregion, 0},
5424
	{"i915_vbt", i915_vbt, 0},
5425
	{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5426
	{"i915_context_status", i915_context_status, 0},
5427
	{"i915_dump_lrc", i915_dump_lrc, 0},
5428
	{"i915_forcewake_domains", i915_forcewake_domains, 0},
5429
	{"i915_swizzle_info", i915_swizzle_info, 0},
D
Daniel Vetter 已提交
5430
	{"i915_ppgtt_info", i915_ppgtt_info, 0},
5431
	{"i915_llc", i915_llc, 0},
5432
	{"i915_edp_psr_status", i915_edp_psr_status, 0},
5433
	{"i915_sink_crc_eDP1", i915_sink_crc, 0},
5434
	{"i915_energy_uJ", i915_energy_uJ, 0},
5435
	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5436
	{"i915_power_domain_info", i915_power_domain_info, 0},
5437
	{"i915_dmc_info", i915_dmc_info, 0},
5438
	{"i915_display_info", i915_display_info, 0},
5439
	{"i915_engine_info", i915_engine_info, 0},
B
Ben Widawsky 已提交
5440
	{"i915_semaphore_status", i915_semaphore_status, 0},
5441
	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5442
	{"i915_dp_mst_info", i915_dp_mst_info, 0},
5443
	{"i915_wa_registers", i915_wa_registers, 0},
5444
	{"i915_ddb_info", i915_ddb_info, 0},
5445
	{"i915_sseu_status", i915_sseu_status, 0},
5446
	{"i915_drrs_status", i915_drrs_status, 0},
5447
	{"i915_rps_boost_info", i915_rps_boost_info, 0},
5448
};
5449
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5450

5451
static const struct i915_debugfs_files {
5452 5453 5454 5455 5456 5457 5458
	const char *name;
	const struct file_operations *fops;
} i915_debugfs_files[] = {
	{"i915_wedged", &i915_wedged_fops},
	{"i915_max_freq", &i915_max_freq_fops},
	{"i915_min_freq", &i915_min_freq_fops},
	{"i915_cache_sharing", &i915_cache_sharing_fops},
5459 5460
	{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
	{"i915_ring_test_irq", &i915_ring_test_irq_fops},
5461
	{"i915_gem_drop_caches", &i915_drop_caches_fops},
5462
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
5463
	{"i915_error_state", &i915_error_state_fops},
5464
#endif
5465
	{"i915_next_seqno", &i915_next_seqno_fops},
5466
	{"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5467 5468 5469
	{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
	{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
	{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5470
	{"i915_fbc_false_color", &i915_fbc_fc_fops},
5471 5472
	{"i915_dp_test_data", &i915_displayport_test_data_fops},
	{"i915_dp_test_type", &i915_displayport_test_type_fops},
5473 5474
	{"i915_dp_test_active", &i915_displayport_test_active_fops},
	{"i915_guc_log_control", &i915_guc_log_control_fops}
5475 5476
};

5477
void intel_display_crc_init(struct drm_i915_private *dev_priv)
5478
{
5479
	enum pipe pipe;
5480

5481
	for_each_pipe(dev_priv, pipe) {
5482
		struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5483

5484 5485
		pipe_crc->opened = false;
		spin_lock_init(&pipe_crc->lock);
5486 5487 5488 5489
		init_waitqueue_head(&pipe_crc->wq);
	}
}

5490
int i915_debugfs_register(struct drm_i915_private *dev_priv)
5491
{
5492
	struct drm_minor *minor = dev_priv->drm.primary;
5493
	int ret, i;
5494

5495
	ret = i915_forcewake_create(minor->debugfs_root, minor);
5496 5497
	if (ret)
		return ret;
5498

5499 5500 5501 5502 5503 5504
	for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
		ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
		if (ret)
			return ret;
	}

5505 5506 5507 5508 5509 5510 5511
	for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
		ret = i915_debugfs_create(minor->debugfs_root, minor,
					  i915_debugfs_files[i].name,
					  i915_debugfs_files[i].fops);
		if (ret)
			return ret;
	}
5512

5513 5514
	return drm_debugfs_create_files(i915_debugfs_list,
					I915_DEBUGFS_ENTRIES,
5515 5516 5517
					minor->debugfs_root, minor);
}

5518
void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5519
{
5520
	struct drm_minor *minor = dev_priv->drm.primary;
5521 5522
	int i;

5523 5524
	drm_debugfs_remove_files(i915_debugfs_list,
				 I915_DEBUGFS_ENTRIES, minor);
5525

5526
	drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5527
				 1, minor);
5528

D
Daniel Vetter 已提交
5529
	for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5530 5531 5532 5533 5534 5535
		struct drm_info_list *info_list =
			(struct drm_info_list *)&i915_pipe_crc_data[i];

		drm_debugfs_remove_files(info_list, 1, minor);
	}

5536 5537
	for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
		struct drm_info_list *info_list =
5538
			(struct drm_info_list *)i915_debugfs_files[i].fops;
5539 5540 5541

		drm_debugfs_remove_files(info_list, 1, minor);
	}
5542
}
5543 5544 5545 5546 5547 5548 5549 5550 5551 5552 5553 5554 5555 5556 5557 5558 5559 5560 5561 5562 5563 5564 5565 5566 5567 5568 5569 5570 5571 5572 5573 5574 5575 5576

struct dpcd_block {
	/* DPCD dump start address. */
	unsigned int offset;
	/* DPCD dump end address, inclusive. If unset, .size will be used. */
	unsigned int end;
	/* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
	size_t size;
	/* Only valid for eDP. */
	bool edp;
};

static const struct dpcd_block i915_dpcd_debug[] = {
	{ .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
	{ .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
	{ .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
	{ .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
	{ .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
	{ .offset = DP_SET_POWER },
	{ .offset = DP_EDP_DPCD_REV },
	{ .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
	{ .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
	{ .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
};

static int i915_dpcd_show(struct seq_file *m, void *data)
{
	struct drm_connector *connector = m->private;
	struct intel_dp *intel_dp =
		enc_to_intel_dp(&intel_attached_encoder(connector)->base);
	uint8_t buf[16];
	ssize_t err;
	int i;

5577 5578 5579
	if (connector->status != connector_status_connected)
		return -ENODEV;

5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592 5593 5594 5595 5596 5597 5598 5599
	for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
		const struct dpcd_block *b = &i915_dpcd_debug[i];
		size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);

		if (b->edp &&
		    connector->connector_type != DRM_MODE_CONNECTOR_eDP)
			continue;

		/* low tech for now */
		if (WARN_ON(size > sizeof(buf)))
			continue;

		err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
		if (err <= 0) {
			DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
				  size, b->offset, err);
			continue;
		}

		seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5600
	}
5601 5602 5603 5604 5605 5606 5607 5608 5609 5610 5611 5612 5613 5614 5615 5616 5617

	return 0;
}

static int i915_dpcd_open(struct inode *inode, struct file *file)
{
	return single_open(file, i915_dpcd_show, inode->i_private);
}

static const struct file_operations i915_dpcd_fops = {
	.owner = THIS_MODULE,
	.open = i915_dpcd_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
};

5618 5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651
static int i915_panel_show(struct seq_file *m, void *data)
{
	struct drm_connector *connector = m->private;
	struct intel_dp *intel_dp =
		enc_to_intel_dp(&intel_attached_encoder(connector)->base);

	if (connector->status != connector_status_connected)
		return -ENODEV;

	seq_printf(m, "Panel power up delay: %d\n",
		   intel_dp->panel_power_up_delay);
	seq_printf(m, "Panel power down delay: %d\n",
		   intel_dp->panel_power_down_delay);
	seq_printf(m, "Backlight on delay: %d\n",
		   intel_dp->backlight_on_delay);
	seq_printf(m, "Backlight off delay: %d\n",
		   intel_dp->backlight_off_delay);

	return 0;
}

static int i915_panel_open(struct inode *inode, struct file *file)
{
	return single_open(file, i915_panel_show, inode->i_private);
}

static const struct file_operations i915_panel_fops = {
	.owner = THIS_MODULE,
	.open = i915_panel_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
};

5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670
/**
 * i915_debugfs_connector_add - add i915 specific connector debugfs files
 * @connector: pointer to a registered drm_connector
 *
 * Cleanup will be done by drm_connector_unregister() through a call to
 * drm_debugfs_connector_remove().
 *
 * Returns 0 on success, negative error codes on error.
 */
int i915_debugfs_connector_add(struct drm_connector *connector)
{
	struct dentry *root = connector->debugfs_entry;

	/* The connector must have been registered beforehands. */
	if (!root)
		return -ENODEV;

	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
	    connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5671 5672 5673 5674 5675 5676
		debugfs_create_file("i915_dpcd", S_IRUGO, root,
				    connector, &i915_dpcd_fops);

	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
		debugfs_create_file("i915_panel_timings", S_IRUGO, root,
				    connector, &i915_panel_fops);
5677 5678 5679

	return 0;
}