intel_dp.c 89.4 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
29
#include <linux/slab.h>
30
#include <linux/export.h>
31 32 33 34
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
35
#include "intel_drv.h"
36
#include <drm/i915_drm.h>
37 38 39 40
#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

41 42 43 44 45 46 47 48 49
/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
50 51 52
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53 54
}

55 56 57 58 59 60 61
static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
}

A
Adam Jackson 已提交
62 63 64 65 66 67 68 69
/**
 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
 * @intel_dp: DP struct
 *
 * Returns true if the given DP struct corresponds to a CPU eDP port.
 */
static bool is_cpu_edp(struct intel_dp *intel_dp)
{
70
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
71
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
72
	enum port port = intel_dig_port->port;
73

74 75
	return is_edp(intel_dp) &&
		(port == PORT_A || (port == PORT_C && IS_VALLEYVIEW(dev)));
C
Chris Wilson 已提交
76
}
77

78 79
static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
80
	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
81 82
}

C
Chris Wilson 已提交
83
static void intel_dp_link_down(struct intel_dp *intel_dp);
84 85

static int
C
Chris Wilson 已提交
86
intel_dp_max_link_bw(struct intel_dp *intel_dp)
87
{
88
	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
89 90 91 92 93 94 95 96 97 98 99 100

	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
	default:
		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117
/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

118
static int
119
intel_dp_link_required(int pixel_clock, int bpp)
120
{
121
	return (pixel_clock * bpp + 9) / 10;
122 123
}

124 125 126 127 128 129
static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

130 131 132 133
static int
intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
134
	struct intel_dp *intel_dp = intel_attached_dp(connector);
135 136
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
137 138
	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
139

140 141
	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
142 143
			return MODE_PANEL;

144
		if (mode->vdisplay > fixed_mode->vdisplay)
145
			return MODE_PANEL;
146 147

		target_clock = fixed_mode->clock;
148 149
	}

150 151 152 153 154 155 156
	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);

	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
157
		return MODE_CLOCK_HIGH;
158 159 160 161

	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

162 163 164
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190
	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

191 192 193 194 195 196 197
/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

198 199 200 201
	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224
	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

225 226
static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
{
227
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
228
	struct drm_i915_private *dev_priv = dev->dev_private;
229
	u32 pp_stat_reg;
230

231 232
	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
	return (I915_READ(pp_stat_reg) & PP_ON) != 0;
233 234 235 236
}

static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
{
237
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
238
	struct drm_i915_private *dev_priv = dev->dev_private;
239
	u32 pp_ctrl_reg;
240

241 242
	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
	return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
243 244
}

245 246 247
static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
248
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
249
	struct drm_i915_private *dev_priv = dev->dev_private;
250
	u32 pp_stat_reg, pp_ctrl_reg;
251

252 253
	if (!is_edp(intel_dp))
		return;
254 255 256 257

	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

258
	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
259 260
		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
261 262
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
263 264 265
	}
}

266 267 268 269 270 271
static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
272
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
273 274 275
	uint32_t status;
	bool done;

276
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
277
	if (has_aux_irq)
278 279
		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
					  msecs_to_jiffies(10));
280 281 282 283 284 285 286 287 288 289
	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

290
static int
C
Chris Wilson 已提交
291
intel_dp_aux_ch(struct intel_dp *intel_dp,
292 293 294
		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
295 296
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
297
	struct drm_i915_private *dev_priv = dev->dev_private;
298
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
299
	uint32_t ch_data = ch_ctl + 4;
300
	int i, ret, recv_bytes;
301
	uint32_t status;
302
	uint32_t aux_clock_divider;
303
	int try, precharge;
304 305 306 307 308 309 310
	bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);
311

312
	intel_dp_check_edp(intel_dp);
313
	/* The clock divider is based off the hrawclk,
314 315
	 * and would like to run at 2MHz. So, take the
	 * hrawclk value and divide by 2 and use that
316 317 318
	 *
	 * Note that PCH attached eDP panels should use a 125MHz input
	 * clock divider.
319
	 */
A
Adam Jackson 已提交
320
	if (is_cpu_edp(intel_dp)) {
P
Paulo Zanoni 已提交
321
		if (HAS_DDI(dev))
322 323
			aux_clock_divider = DIV_ROUND_CLOSEST(
				intel_ddi_get_cdclk_freq(dev_priv), 2000);
324
		else if (IS_VALLEYVIEW(dev))
325 326
			aux_clock_divider = 100;
		else if (IS_GEN6(dev) || IS_GEN7(dev))
K
Keith Packard 已提交
327
			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
328 329
		else
			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
330 331 332 333
	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
		aux_clock_divider = 74;
	} else if (HAS_PCH_SPLIT(dev)) {
334
		aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
335
	} else {
336
		aux_clock_divider = intel_hrawclk(dev) / 2;
337
	}
338

339 340 341 342 343
	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

344 345
	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
346
		status = I915_READ_NOTRACE(ch_ctl);
347 348 349 350 351 352 353 354
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
355 356
		ret = -EBUSY;
		goto out;
357 358
	}

359 360 361
	/* Must try at least 3 times according to DP spec */
	for (try = 0; try < 5; try++) {
		/* Load the send data into the aux channel data registers */
362 363 364
		for (i = 0; i < send_bytes; i += 4)
			I915_WRITE(ch_data + i,
				   pack_aux(send + i, send_bytes - i));
365

366
		/* Send the command and wait for it to complete */
367 368
		I915_WRITE(ch_ctl,
			   DP_AUX_CH_CTL_SEND_BUSY |
369
			   (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
370 371 372 373 374 375 376
			   DP_AUX_CH_CTL_TIME_OUT_400us |
			   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
			   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
			   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
			   DP_AUX_CH_CTL_DONE |
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
377 378

		status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
379

380
		/* Clear done status and any errors */
381 382 383 384 385
		I915_WRITE(ch_ctl,
			   status |
			   DP_AUX_CH_CTL_DONE |
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
386 387 388 389

		if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
			      DP_AUX_CH_CTL_RECEIVE_ERROR))
			continue;
390
		if (status & DP_AUX_CH_CTL_DONE)
391 392 393 394
			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
395
		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
396 397
		ret = -EBUSY;
		goto out;
398 399 400 401 402
	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
403
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
404
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
405 406
		ret = -EIO;
		goto out;
407
	}
408 409 410

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
411
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
412
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
413 414
		ret = -ETIMEDOUT;
		goto out;
415 416 417 418 419 420 421
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
422

423 424 425
	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
426

427 428 429 430 431
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);

	return ret;
432 433 434 435
}

/* Write data to the aux channel in native mode */
static int
C
Chris Wilson 已提交
436
intel_dp_aux_native_write(struct intel_dp *intel_dp,
437 438 439 440 441 442 443
			  uint16_t address, uint8_t *send, int send_bytes)
{
	int ret;
	uint8_t	msg[20];
	int msg_bytes;
	uint8_t	ack;

444
	intel_dp_check_edp(intel_dp);
445 446 447 448
	if (send_bytes > 16)
		return -1;
	msg[0] = AUX_NATIVE_WRITE << 4;
	msg[1] = address >> 8;
449
	msg[2] = address & 0xff;
450 451 452 453
	msg[3] = send_bytes - 1;
	memcpy(&msg[4], send, send_bytes);
	msg_bytes = send_bytes + 4;
	for (;;) {
C
Chris Wilson 已提交
454
		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
455 456 457 458 459 460 461
		if (ret < 0)
			return ret;
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
			break;
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
462
			return -EIO;
463 464 465 466 467 468
	}
	return send_bytes;
}

/* Write a single byte to the aux channel in native mode */
static int
C
Chris Wilson 已提交
469
intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
470 471
			    uint16_t address, uint8_t byte)
{
C
Chris Wilson 已提交
472
	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
473 474 475 476
}

/* read bytes from a native aux channel */
static int
C
Chris Wilson 已提交
477
intel_dp_aux_native_read(struct intel_dp *intel_dp,
478 479 480 481 482 483 484 485 486
			 uint16_t address, uint8_t *recv, int recv_bytes)
{
	uint8_t msg[4];
	int msg_bytes;
	uint8_t reply[20];
	int reply_bytes;
	uint8_t ack;
	int ret;

487
	intel_dp_check_edp(intel_dp);
488 489 490 491 492 493 494 495 496
	msg[0] = AUX_NATIVE_READ << 4;
	msg[1] = address >> 8;
	msg[2] = address & 0xff;
	msg[3] = recv_bytes - 1;

	msg_bytes = 4;
	reply_bytes = recv_bytes + 1;

	for (;;) {
C
Chris Wilson 已提交
497
		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
498
				      reply, reply_bytes);
499 500 501
		if (ret == 0)
			return -EPROTO;
		if (ret < 0)
502 503 504 505 506 507 508 509 510
			return ret;
		ack = reply[0];
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
			memcpy(recv, reply + 1, ret - 1);
			return ret - 1;
		}
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
511
			return -EIO;
512 513 514 515
	}
}

static int
516 517
intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		    uint8_t write_byte, uint8_t *read_byte)
518
{
519
	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
C
Chris Wilson 已提交
520 521 522
	struct intel_dp *intel_dp = container_of(adapter,
						struct intel_dp,
						adapter);
523 524 525
	uint16_t address = algo_data->address;
	uint8_t msg[5];
	uint8_t reply[2];
526
	unsigned retry;
527 528 529 530
	int msg_bytes;
	int reply_bytes;
	int ret;

531
	intel_dp_check_edp(intel_dp);
532 533 534 535 536 537 538 539
	/* Set up the command byte */
	if (mode & MODE_I2C_READ)
		msg[0] = AUX_I2C_READ << 4;
	else
		msg[0] = AUX_I2C_WRITE << 4;

	if (!(mode & MODE_I2C_STOP))
		msg[0] |= AUX_I2C_MOT << 4;
540

541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561
	msg[1] = address >> 8;
	msg[2] = address;

	switch (mode) {
	case MODE_I2C_WRITE:
		msg[3] = 0;
		msg[4] = write_byte;
		msg_bytes = 5;
		reply_bytes = 1;
		break;
	case MODE_I2C_READ:
		msg[3] = 0;
		msg_bytes = 4;
		reply_bytes = 2;
		break;
	default:
		msg_bytes = 3;
		reply_bytes = 1;
		break;
	}

562 563 564 565
	for (retry = 0; retry < 5; retry++) {
		ret = intel_dp_aux_ch(intel_dp,
				      msg, msg_bytes,
				      reply, reply_bytes);
566
		if (ret < 0) {
567
			DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
568 569
			return ret;
		}
570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588

		switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
		case AUX_NATIVE_REPLY_ACK:
			/* I2C-over-AUX Reply field is only valid
			 * when paired with AUX ACK.
			 */
			break;
		case AUX_NATIVE_REPLY_NACK:
			DRM_DEBUG_KMS("aux_ch native nack\n");
			return -EREMOTEIO;
		case AUX_NATIVE_REPLY_DEFER:
			udelay(100);
			continue;
		default:
			DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
				  reply[0]);
			return -EREMOTEIO;
		}

589 590 591 592 593 594 595
		switch (reply[0] & AUX_I2C_REPLY_MASK) {
		case AUX_I2C_REPLY_ACK:
			if (mode == MODE_I2C_READ) {
				*read_byte = reply[1];
			}
			return reply_bytes - 1;
		case AUX_I2C_REPLY_NACK:
596
			DRM_DEBUG_KMS("aux_i2c nack\n");
597 598
			return -EREMOTEIO;
		case AUX_I2C_REPLY_DEFER:
599
			DRM_DEBUG_KMS("aux_i2c defer\n");
600 601 602
			udelay(100);
			break;
		default:
603
			DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
604 605 606
			return -EREMOTEIO;
		}
	}
607 608 609

	DRM_ERROR("too many retries, giving up\n");
	return -EREMOTEIO;
610 611 612
}

static int
C
Chris Wilson 已提交
613
intel_dp_i2c_init(struct intel_dp *intel_dp,
614
		  struct intel_connector *intel_connector, const char *name)
615
{
616 617
	int	ret;

Z
Zhenyu Wang 已提交
618
	DRM_DEBUG_KMS("i2c_init %s\n", name);
C
Chris Wilson 已提交
619 620 621 622
	intel_dp->algo.running = false;
	intel_dp->algo.address = 0;
	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;

623
	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
C
Chris Wilson 已提交
624 625
	intel_dp->adapter.owner = THIS_MODULE;
	intel_dp->adapter.class = I2C_CLASS_DDC;
626
	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
C
Chris Wilson 已提交
627 628 629 630
	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
	intel_dp->adapter.algo_data = &intel_dp->algo;
	intel_dp->adapter.dev.parent = &intel_connector->base.kdev;

631 632
	ironlake_edp_panel_vdd_on(intel_dp);
	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
633
	ironlake_edp_panel_vdd_off(intel_dp, false);
634
	return ret;
635 636
}

637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679
static void
intel_dp_set_clock(struct intel_encoder *encoder,
		   struct intel_crtc_config *pipe_config, int link_bw)
{
	struct drm_device *dev = encoder->base.dev;

	if (IS_G4X(dev)) {
		if (link_bw == DP_LINK_BW_1_62) {
			pipe_config->dpll.p1 = 2;
			pipe_config->dpll.p2 = 10;
			pipe_config->dpll.n = 2;
			pipe_config->dpll.m1 = 23;
			pipe_config->dpll.m2 = 8;
		} else {
			pipe_config->dpll.p1 = 1;
			pipe_config->dpll.p2 = 10;
			pipe_config->dpll.n = 1;
			pipe_config->dpll.m1 = 14;
			pipe_config->dpll.m2 = 2;
		}
		pipe_config->clock_set = true;
	} else if (IS_HASWELL(dev)) {
		/* Haswell has special-purpose DP DDI clocks. */
	} else if (HAS_PCH_SPLIT(dev)) {
		if (link_bw == DP_LINK_BW_1_62) {
			pipe_config->dpll.n = 1;
			pipe_config->dpll.p1 = 2;
			pipe_config->dpll.p2 = 10;
			pipe_config->dpll.m1 = 12;
			pipe_config->dpll.m2 = 9;
		} else {
			pipe_config->dpll.n = 2;
			pipe_config->dpll.p1 = 1;
			pipe_config->dpll.p2 = 10;
			pipe_config->dpll.m1 = 14;
			pipe_config->dpll.m2 = 8;
		}
		pipe_config->clock_set = true;
	} else if (IS_VALLEYVIEW(dev)) {
		/* FIXME: Need to figure out optimized DP clocks for vlv. */
	}
}

P
Paulo Zanoni 已提交
680
bool
681 682
intel_dp_compute_config(struct intel_encoder *encoder,
			struct intel_crtc_config *pipe_config)
683
{
684
	struct drm_device *dev = encoder->base.dev;
685
	struct drm_i915_private *dev_priv = dev->dev_private;
686 687
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
688
	struct intel_crtc *intel_crtc = encoder->new_crtc;
689
	struct intel_connector *intel_connector = intel_dp->attached_connector;
690
	int lane_count, clock;
691
	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
C
Chris Wilson 已提交
692
	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
693
	int bpp, mode_rate;
694
	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
695
	int target_clock, link_avail, link_clock;
696

697 698 699
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
		pipe_config->has_pch_encoder = true;

700 701
	pipe_config->has_dp_encoder = true;

702 703 704
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
705 706 707 708
		if (!HAS_PCH_SPLIT(dev))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
709 710
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
711
	}
712 713
	/* We need to take the panel's fixed mode into account. */
	target_clock = adjusted_mode->clock;
714

715
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
716 717
		return false;

718 719
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max bw %02x pixel clock %iKHz\n",
720
		      max_lane_count, bws[max_clock], adjusted_mode->clock);
721

722 723
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
724
	bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
725 726
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
		bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
727

728 729 730 731 732 733 734 735 736 737 738 739 740 741 742
	for (; bpp >= 6*3; bpp -= 2*3) {
		mode_rate = intel_dp_link_required(target_clock, bpp);

		for (clock = 0; clock <= max_clock; clock++) {
			for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
743

744
	return false;
745

746
found:
747 748 749 750 751 752
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
753
		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
754 755 756 757 758
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
		else
			intel_dp->color_range = 0;
	}

759
	if (intel_dp->color_range)
760
		pipe_config->limited_color_range = true;
761

762 763 764
	intel_dp->link_bw = bws[clock];
	intel_dp->lane_count = lane_count;
	adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
765
	pipe_config->pipe_bpp = bpp;
766
	pipe_config->pixel_target_clock = target_clock;
767

768 769 770 771 772 773
	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
		      intel_dp->link_bw, intel_dp->lane_count,
		      adjusted_mode->clock, bpp);
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);

774 775 776
	intel_link_compute_m_n(bpp, lane_count,
			       target_clock, adjusted_mode->clock,
			       &pipe_config->dp_m_n);
777

778 779
	intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);

780
	return true;
781 782
}

783 784 785 786 787 788 789 790 791 792 793 794 795 796 797
void intel_dp_init_link_config(struct intel_dp *intel_dp)
{
	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
	intel_dp->link_configuration[0] = intel_dp->link_bw;
	intel_dp->link_configuration[1] = intel_dp->lane_count;
	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
	/*
	 * Check for DPCD version > 1.1 and enhanced framing support
	 */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
		intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	}
}

798 799 800 801 802 803 804 805 806 807 808
static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

	if (clock < 200000) {
809 810 811 812
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
813 814 815 816
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
	}
817

818 819 820 821 822 823
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

824 825 826 827
static void
intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
		  struct drm_display_mode *adjusted_mode)
{
828
	struct drm_device *dev = encoder->dev;
829
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
830
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
831
	struct drm_crtc *crtc = encoder->crtc;
832 833
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

834
	/*
K
Keith Packard 已提交
835
	 * There are four kinds of DP registers:
836 837
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
838 839
	 * 	SNB CPU
	 *	IVB CPU
840 841 842 843 844 845 846 847 848 849
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
850

851 852 853 854
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
855

856 857
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
858
	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
859

860 861 862
	if (intel_dp->has_audio) {
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
				 pipe_name(intel_crtc->pipe));
C
Chris Wilson 已提交
863
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
864 865
		intel_write_eld(encoder, adjusted_mode);
	}
866 867

	intel_dp_init_link_config(intel_dp);
868

869
	/* Split out the IBX/CPU vs CPT settings */
870

871
	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
			intel_dp->DP |= DP_ENHANCED_FRAMING;

		intel_dp->DP |= intel_crtc->pipe << 29;

		/* don't miss out required setting for eDP */
		if (adjusted_mode->clock < 200000)
			intel_dp->DP |= DP_PLL_FREQ_160MHZ;
		else
			intel_dp->DP |= DP_PLL_FREQ_270MHZ;
	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
889
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
890
			intel_dp->DP |= intel_dp->color_range;
891 892 893 894 895 896 897 898 899 900 901 902 903

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
			intel_dp->DP |= DP_ENHANCED_FRAMING;

		if (intel_crtc->pipe == 1)
			intel_dp->DP |= DP_PIPEB_SELECT;

904
		if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
905 906 907 908 909 910 911 912
			/* don't miss out required setting for eDP */
			if (adjusted_mode->clock < 200000)
				intel_dp->DP |= DP_PLL_FREQ_160MHZ;
			else
				intel_dp->DP |= DP_PLL_FREQ_270MHZ;
		}
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
913
	}
914

915
	if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
916
		ironlake_set_pll_edp(crtc, adjusted_mode->clock);
917 918
}

919 920 921 922 923 924 925 926 927 928 929 930
#define IDLE_ON_MASK		(PP_ON | 0 	  | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | 0 	  | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)

#define IDLE_OFF_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_OFF_VALUE		(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

#define IDLE_CYCLE_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
				       u32 mask,
				       u32 value)
931
{
932
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
933
	struct drm_i915_private *dev_priv = dev->dev_private;
934 935 936 937
	u32 pp_stat_reg, pp_ctrl_reg;

	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
938

939
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
940 941 942
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
943

944
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
945
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
946 947
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
948
	}
949
}
950

951 952 953 954
static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
	ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
955 956
}

957 958 959 960 961 962 963 964 965 966 967 968 969
static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
	ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
}

static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
	ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}


970 971 972 973
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

974
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
975
{
976 977 978 979 980 981 982
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
	u32 pp_ctrl_reg;

	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
	control = I915_READ(pp_ctrl_reg);
983 984 985 986

	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
987 988
}

989
void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
990
{
991
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
992 993
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
994
	u32 pp_stat_reg, pp_ctrl_reg;
995

996 997
	if (!is_edp(intel_dp))
		return;
998
	DRM_DEBUG_KMS("Turn eDP VDD on\n");
999

1000 1001 1002 1003
	WARN(intel_dp->want_panel_vdd,
	     "eDP VDD already requested on\n");

	intel_dp->want_panel_vdd = true;
1004

1005 1006 1007 1008 1009
	if (ironlake_edp_have_panel_vdd(intel_dp)) {
		DRM_DEBUG_KMS("eDP VDD already on\n");
		return;
	}

1010 1011 1012
	if (!ironlake_edp_have_panel_power(intel_dp))
		ironlake_wait_panel_power_cycle(intel_dp);

1013
	pp = ironlake_get_pp_control(intel_dp);
1014
	pp |= EDP_FORCE_VDD;
1015

1016 1017 1018 1019 1020 1021 1022
	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1023 1024 1025 1026
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
	if (!ironlake_edp_have_panel_power(intel_dp)) {
1027
		DRM_DEBUG_KMS("eDP was not running\n");
1028 1029
		msleep(intel_dp->panel_power_up_delay);
	}
1030 1031
}

1032
static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1033
{
1034
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1035 1036
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1037
	u32 pp_stat_reg, pp_ctrl_reg;
1038

1039 1040
	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));

1041
	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1042
		pp = ironlake_get_pp_control(intel_dp);
1043 1044
		pp &= ~EDP_FORCE_VDD;

1045 1046 1047 1048 1049
		pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
		pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1050

1051 1052 1053
		/* Make sure sequencer is idle before allowing subsequent activity */
		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1054
		msleep(intel_dp->panel_power_down_delay);
1055 1056
	}
}
1057

1058 1059 1060 1061
static void ironlake_panel_vdd_work(struct work_struct *__work)
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);
1062
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1063

1064
	mutex_lock(&dev->mode_config.mutex);
1065
	ironlake_panel_vdd_off_sync(intel_dp);
1066
	mutex_unlock(&dev->mode_config.mutex);
1067 1068
}

1069
void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1070
{
1071 1072
	if (!is_edp(intel_dp))
		return;
1073

1074 1075
	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1076

1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089
	intel_dp->want_panel_vdd = false;

	if (sync) {
		ironlake_panel_vdd_off_sync(intel_dp);
	} else {
		/*
		 * Queue the timer to fire a long
		 * time from now (relative to the power down delay)
		 * to keep the panel power up across a sequence of operations
		 */
		schedule_delayed_work(&intel_dp->panel_vdd_work,
				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
	}
1090 1091
}

1092
void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1093
{
1094
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1095
	struct drm_i915_private *dev_priv = dev->dev_private;
1096
	u32 pp;
1097
	u32 pp_ctrl_reg;
1098

1099
	if (!is_edp(intel_dp))
1100
		return;
1101 1102 1103 1104 1105

	DRM_DEBUG_KMS("Turn eDP power on\n");

	if (ironlake_edp_have_panel_power(intel_dp)) {
		DRM_DEBUG_KMS("eDP power already on\n");
1106
		return;
1107
	}
1108

1109
	ironlake_wait_panel_power_cycle(intel_dp);
1110

1111
	pp = ironlake_get_pp_control(intel_dp);
1112 1113 1114 1115 1116 1117
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);
	}
1118

1119
	pp |= POWER_TARGET_ON;
1120 1121 1122
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1123 1124 1125 1126
	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1127

1128
	ironlake_wait_panel_on(intel_dp);
1129

1130 1131 1132 1133 1134
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);
	}
1135 1136
}

1137
void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1138
{
1139
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1140
	struct drm_i915_private *dev_priv = dev->dev_private;
1141
	u32 pp;
1142
	u32 pp_ctrl_reg;
1143

1144 1145
	if (!is_edp(intel_dp))
		return;
1146

1147
	DRM_DEBUG_KMS("Turn eDP power off\n");
1148

1149
	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1150

1151
	pp = ironlake_get_pp_control(intel_dp);
1152 1153 1154
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1155 1156 1157 1158 1159

	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1160

1161 1162
	intel_dp->want_panel_vdd = false;

1163
	ironlake_wait_panel_off(intel_dp);
1164 1165
}

1166
void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1167
{
1168 1169
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1170
	struct drm_i915_private *dev_priv = dev->dev_private;
1171
	int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1172
	u32 pp;
1173
	u32 pp_ctrl_reg;
1174

1175 1176 1177
	if (!is_edp(intel_dp))
		return;

1178
	DRM_DEBUG_KMS("\n");
1179 1180 1181 1182 1183 1184
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1185
	msleep(intel_dp->backlight_on_delay);
1186
	pp = ironlake_get_pp_control(intel_dp);
1187
	pp |= EDP_BLC_ENABLE;
1188 1189 1190 1191 1192

	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1193 1194

	intel_panel_enable_backlight(dev, pipe);
1195 1196
}

1197
void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1198
{
1199
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1200 1201
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1202
	u32 pp_ctrl_reg;
1203

1204 1205 1206
	if (!is_edp(intel_dp))
		return;

1207 1208
	intel_panel_disable_backlight(dev);

1209
	DRM_DEBUG_KMS("\n");
1210
	pp = ironlake_get_pp_control(intel_dp);
1211
	pp &= ~EDP_BLC_ENABLE;
1212 1213 1214 1215 1216

	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1217
	msleep(intel_dp->backlight_off_delay);
1218
}
1219

1220
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1221
{
1222 1223 1224
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1225 1226 1227
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1228 1229 1230
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1231 1232
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1233 1234 1235 1236 1237 1238 1239 1240 1241
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
1242 1243
	POSTING_READ(DP_A);
	udelay(200);
1244 1245
}

1246
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1247
{
1248 1249 1250
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1251 1252 1253
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1254 1255 1256
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1257
	dpa_ctl = I915_READ(DP_A);
1258 1259 1260 1261 1262 1263 1264
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
1265
	dpa_ctl &= ~DP_PLL_ENABLE;
1266
	I915_WRITE(DP_A, dpa_ctl);
1267
	POSTING_READ(DP_A);
1268 1269 1270
	udelay(200);
}

1271
/* If the sink supports it, try to set the power state appropriately */
1272
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
		ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
						  DP_SET_POWER_D3);
		if (ret != 1)
			DRM_DEBUG_DRIVER("failed to write sink power state\n");
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
			ret = intel_dp_aux_native_write_1(intel_dp,
							  DP_SET_POWER,
							  DP_SET_POWER_D0);
			if (ret == 1)
				break;
			msleep(1);
		}
	}
}

1301 1302
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
1303
{
1304 1305 1306 1307 1308 1309 1310 1311
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 tmp = I915_READ(intel_dp->output_reg);

	if (!(tmp & DP_PORT_EN))
		return false;

1312
	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342
		*pipe = PORT_TO_PIPE_CPT(tmp);
	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
		*pipe = PORT_TO_PIPE(tmp);
	} else {
		u32 trans_sel;
		u32 trans_dp;
		int i;

		switch (intel_dp->output_reg) {
		case PCH_DP_B:
			trans_sel = TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			trans_sel = TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			trans_sel = TRANS_DP_PORT_SEL_D;
			break;
		default:
			return true;
		}

		for_each_pipe(i) {
			trans_dp = I915_READ(TRANS_DP_CTL(i));
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
				*pipe = i;
				return true;
			}
		}

1343 1344 1345
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
	}
1346

1347
	return true;
1348
}
1349

1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
static void intel_dp_get_config(struct intel_encoder *encoder,
				struct intel_crtc_config *pipe_config)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	u32 tmp, flags = 0;

	tmp = I915_READ(intel_dp->output_reg);

	if (tmp & DP_SYNC_HS_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;

	if (tmp & DP_SYNC_VS_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

	pipe_config->adjusted_mode.flags |= flags;
}

1372
static void intel_disable_dp(struct intel_encoder *encoder)
1373
{
1374
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1375 1376
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct drm_device *dev = encoder->base.dev;
1377 1378 1379 1380

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
	ironlake_edp_panel_vdd_on(intel_dp);
1381
	ironlake_edp_backlight_off(intel_dp);
1382
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1383
	ironlake_edp_panel_off(intel_dp);
1384 1385

	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1386
	if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1387
		intel_dp_link_down(intel_dp);
1388 1389
}

1390
static void intel_post_disable_dp(struct intel_encoder *encoder)
1391
{
1392
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1393
	enum port port = dp_to_dig_port(intel_dp)->port;
1394
	struct drm_device *dev = encoder->base.dev;
1395

1396
	if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1397
		intel_dp_link_down(intel_dp);
1398 1399
		if (!IS_VALLEYVIEW(dev))
			ironlake_edp_pll_off(intel_dp);
1400
	}
1401 1402
}

1403
static void intel_enable_dp(struct intel_encoder *encoder)
1404
{
1405 1406 1407 1408
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1409

1410 1411
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
1412

1413
	ironlake_edp_panel_vdd_on(intel_dp);
1414
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1415
	intel_dp_start_link_train(intel_dp);
1416
	ironlake_edp_panel_on(intel_dp);
1417
	ironlake_edp_panel_vdd_off(intel_dp, true);
1418
	intel_dp_complete_link_train(intel_dp);
1419
	intel_dp_stop_link_train(intel_dp);
1420
	ironlake_edp_backlight_on(intel_dp);
1421 1422 1423 1424 1425 1426 1427 1428

	if (IS_VALLEYVIEW(dev)) {
		struct intel_digital_port *dport =
			enc_to_dig_port(&encoder->base);
		int channel = vlv_dport_to_channel(dport);

		vlv_wait_port_ready(dev_priv, channel);
	}
1429 1430
}

1431
static void intel_pre_enable_dp(struct intel_encoder *encoder)
1432
{
1433
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1434
	struct drm_device *dev = encoder->base.dev;
1435
	struct drm_i915_private *dev_priv = dev->dev_private;
1436

1437
	if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1438
		ironlake_edp_pll_on(intel_dp);
1439 1440 1441 1442 1443 1444 1445 1446 1447

	if (IS_VALLEYVIEW(dev)) {
		struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
		struct intel_crtc *intel_crtc =
			to_intel_crtc(encoder->base.crtc);
		int port = vlv_dport_to_channel(dport);
		int pipe = intel_crtc->pipe;
		u32 val;

1448
		val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1449 1450 1451 1452 1453 1454
		val = 0;
		if (pipe)
			val |= (1<<21);
		else
			val &= ~(1<<21);
		val |= 0x001000c4;
1455
		vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1456

1457
		vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1458
				 0x00760018);
1459
		vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474
				 0x00400888);
	}
}

static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int port = vlv_dport_to_channel(dport);

	if (!IS_VALLEYVIEW(dev))
		return;

	/* Program Tx lane resets to default */
1475
	vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1476 1477
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
1478
	vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1479 1480 1481 1482 1483 1484
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
1485 1486 1487
	vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
	vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
	vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1488 1489 1490
}

/*
1491 1492
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
1493 1494
 */
static bool
1495 1496
intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
			       uint8_t *recv, int recv_bytes)
1497
{
1498 1499
	int ret, i;

1500 1501 1502 1503
	/*
	 * Sinks are *supposed* to come up within 1ms from an off state,
	 * but we're also supposed to retry 3 times per the spec.
	 */
1504
	for (i = 0; i < 3; i++) {
1505 1506 1507
		ret = intel_dp_aux_native_read(intel_dp, address, recv,
					       recv_bytes);
		if (ret == recv_bytes)
1508 1509 1510
			return true;
		msleep(1);
	}
1511

1512
	return false;
1513 1514 1515 1516 1517 1518 1519
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
1520
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1521
{
1522 1523
	return intel_dp_aux_native_read_retry(intel_dp,
					      DP_LANE0_1_STATUS,
1524
					      link_status,
1525
					      DP_LINK_STATUS_SIZE);
1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545
}

#if 0
static char	*voltage_names[] = {
	"0.4V", "0.6V", "0.8V", "1.2V"
};
static char	*pre_emph_names[] = {
	"0dB", "3.5dB", "6dB", "9.5dB"
};
static char	*link_train_names[] = {
	"pattern 1", "pattern 2", "idle", "off"
};
#endif

/*
 * These are source-specific values; current Intel hardware supports
 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 */

static uint8_t
K
Keith Packard 已提交
1546
intel_dp_voltage_max(struct intel_dp *intel_dp)
1547
{
1548
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
K
Keith Packard 已提交
1549

1550 1551 1552
	if (IS_VALLEYVIEW(dev))
		return DP_TRAIN_VOLTAGE_SWING_1200;
	else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
K
Keith Packard 已提交
1553 1554 1555 1556 1557 1558 1559 1560 1561 1562
		return DP_TRAIN_VOLTAGE_SWING_800;
	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
		return DP_TRAIN_VOLTAGE_SWING_1200;
	else
		return DP_TRAIN_VOLTAGE_SWING_800;
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
1563
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
K
Keith Packard 已提交
1564

1565
	if (HAS_DDI(dev)) {
1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
K
Keith Packard 已提交
1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
1611 1612 1613
	}
}

1614 1615 1616 1617 1618 1619 1620 1621
static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
1622
	int port = vlv_dport_to_channel(dport);
1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
	case DP_TRAIN_PRE_EMPHASIS_0:
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_1200:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

1697 1698 1699
	vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
	vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1700
			 uniqtranscale_reg_value);
1701 1702 1703 1704
	vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
	vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1705 1706 1707 1708

	return 0;
}

1709
static void
1710
intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1711 1712 1713 1714
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
1715 1716
	uint8_t voltage_max;
	uint8_t preemph_max;
1717

1718
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
1719 1720
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1721 1722 1723 1724 1725 1726 1727

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
1728
	voltage_max = intel_dp_voltage_max(intel_dp);
1729 1730
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1731

K
Keith Packard 已提交
1732 1733 1734
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1735 1736

	for (lane = 0; lane < 4; lane++)
1737
		intel_dp->train_set[lane] = v | p;
1738 1739 1740
}

static uint32_t
1741
intel_gen4_signal_levels(uint8_t train_set)
1742
{
1743
	uint32_t	signal_levels = 0;
1744

1745
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
1760
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

1778 1779 1780 1781
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
1782 1783 1784
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
1785
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1786 1787 1788 1789
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1790
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1791 1792
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1793
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1794 1795
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1796
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1797 1798
	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1799
	default:
1800 1801 1802
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1803 1804 1805
	}
}

K
Keith Packard 已提交
1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

1837 1838
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
static uint32_t
1839
intel_hsw_signal_levels(uint8_t train_set)
1840
{
1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
		return DDI_BUF_EMP_400MV_9_5DB_HSW;
1852

1853 1854 1855 1856 1857 1858
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_HSW;
1859

1860 1861 1862 1863 1864 1865 1866 1867
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_HSW;
	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_HSW;
1868 1869 1870
	}
}

1871 1872 1873 1874 1875 1876 1877 1878 1879
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t signal_levels, mask;
	uint8_t train_set = intel_dp->train_set[0];

1880
	if (HAS_DDI(dev)) {
1881 1882
		signal_levels = intel_hsw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
1883 1884 1885 1886
	} else if (IS_VALLEYVIEW(dev)) {
		signal_levels = intel_vlv_signal_levels(intel_dp);
		mask = 0;
	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901
		signal_levels = intel_gen7_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
	} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
		signal_levels = intel_gen6_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
		signal_levels = intel_gen4_signal_levels(train_set);
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	*DP = (*DP & ~mask) | signal_levels;
}

1902
static bool
C
Chris Wilson 已提交
1903
intel_dp_set_link_train(struct intel_dp *intel_dp,
1904
			uint32_t dp_reg_value,
1905
			uint8_t dp_train_pat)
1906
{
1907 1908
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1909
	struct drm_i915_private *dev_priv = dev->dev_private;
1910
	enum port port = intel_dig_port->port;
1911 1912
	int ret;

1913
	if (HAS_DDI(dev)) {
1914
		uint32_t temp = I915_READ(DP_TP_CTL(port));
1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
1937
		I915_WRITE(DP_TP_CTL(port), temp);
1938 1939 1940

	} else if (HAS_PCH_CPT(dev) &&
		   (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978
		dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
			break;
		case DP_TRAINING_PATTERN_1:
			dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
			break;
		case DP_TRAINING_PATTERN_2:
			dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		}

	} else {
		dp_reg_value &= ~DP_LINK_TRAIN_MASK;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			dp_reg_value |= DP_LINK_TRAIN_OFF;
			break;
		case DP_TRAINING_PATTERN_1:
			dp_reg_value |= DP_LINK_TRAIN_PAT_1;
			break;
		case DP_TRAINING_PATTERN_2:
			dp_reg_value |= DP_LINK_TRAIN_PAT_2;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			dp_reg_value |= DP_LINK_TRAIN_PAT_2;
			break;
		}
	}

C
Chris Wilson 已提交
1979 1980
	I915_WRITE(intel_dp->output_reg, dp_reg_value);
	POSTING_READ(intel_dp->output_reg);
1981

C
Chris Wilson 已提交
1982
	intel_dp_aux_native_write_1(intel_dp,
1983 1984 1985
				    DP_TRAINING_PATTERN_SET,
				    dp_train_pat);

1986 1987 1988 1989 1990 1991 1992 1993 1994
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
	    DP_TRAINING_PATTERN_DISABLE) {
		ret = intel_dp_aux_native_write(intel_dp,
						DP_TRAINING_LANE0_SET,
						intel_dp->train_set,
						intel_dp->lane_count);
		if (ret != intel_dp->lane_count)
			return false;
	}
1995 1996 1997 1998

	return true;
}

1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

2030
/* Enable corresponding port and start training pattern 1 */
2031
void
2032
intel_dp_start_link_train(struct intel_dp *intel_dp)
2033
{
2034
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2035
	struct drm_device *dev = encoder->dev;
2036 2037 2038
	int i;
	uint8_t voltage;
	bool clock_recovery = false;
2039
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
2040
	uint32_t DP = intel_dp->DP;
2041

P
Paulo Zanoni 已提交
2042
	if (HAS_DDI(dev))
2043 2044
		intel_ddi_prepare_link_retrain(encoder);

2045 2046 2047 2048
	/* Write the link configuration data */
	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
				  intel_dp->link_configuration,
				  DP_LINK_CONFIGURATION_SIZE);
2049 2050

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
2051

2052
	memset(intel_dp->train_set, 0, 4);
2053
	voltage = 0xff;
2054 2055
	voltage_tries = 0;
	loop_tries = 0;
2056 2057
	clock_recovery = false;
	for (;;) {
2058
		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2059
		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
2060 2061

		intel_dp_set_signal_levels(intel_dp, &DP);
2062

2063
		/* Set training pattern 1 */
2064
		if (!intel_dp_set_link_train(intel_dp, DP,
2065 2066
					     DP_TRAINING_PATTERN_1 |
					     DP_LINK_SCRAMBLING_DISABLE))
2067 2068
			break;

2069
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2070 2071
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
2072
			break;
2073
		}
2074

2075
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2076
			DRM_DEBUG_KMS("clock recovery OK\n");
2077 2078 2079 2080 2081 2082 2083
			clock_recovery = true;
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2084
				break;
2085
		if (i == intel_dp->lane_count) {
2086 2087
			++loop_tries;
			if (loop_tries == 5) {
2088 2089 2090 2091 2092 2093 2094
				DRM_DEBUG_KMS("too many full retries, give up\n");
				break;
			}
			memset(intel_dp->train_set, 0, 4);
			voltage_tries = 0;
			continue;
		}
2095

2096
		/* Check to see if we've tried the same voltage 5 times */
2097
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2098
			++voltage_tries;
2099 2100 2101 2102 2103 2104 2105
			if (voltage_tries == 5) {
				DRM_DEBUG_KMS("too many voltage retries, give up\n");
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2106

2107
		/* Compute new intel_dp->train_set as requested by target */
2108
		intel_get_adjust_train(intel_dp, link_status);
2109 2110
	}

2111 2112 2113
	intel_dp->DP = DP;
}

2114
void
2115 2116 2117
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
2118
	int tries, cr_tries;
2119 2120
	uint32_t DP = intel_dp->DP;

2121 2122
	/* channel equalization */
	tries = 0;
2123
	cr_tries = 0;
2124 2125
	channel_eq = false;
	for (;;) {
2126
		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
2127

2128 2129 2130 2131 2132 2133
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			intel_dp_link_down(intel_dp);
			break;
		}

2134
		intel_dp_set_signal_levels(intel_dp, &DP);
2135

2136
		/* channel eq pattern */
2137
		if (!intel_dp_set_link_train(intel_dp, DP,
2138 2139
					     DP_TRAINING_PATTERN_2 |
					     DP_LINK_SCRAMBLING_DISABLE))
2140 2141
			break;

2142
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2143
		if (!intel_dp_get_link_status(intel_dp, link_status))
2144 2145
			break;

2146
		/* Make sure clock is still ok */
2147
		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2148 2149 2150 2151 2152
			intel_dp_start_link_train(intel_dp);
			cr_tries++;
			continue;
		}

2153
		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2154 2155 2156
			channel_eq = true;
			break;
		}
2157

2158 2159 2160 2161 2162 2163 2164 2165
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
			tries = 0;
			cr_tries++;
			continue;
		}
2166

2167
		/* Compute new intel_dp->train_set as requested by target */
2168
		intel_get_adjust_train(intel_dp, link_status);
2169
		++tries;
2170
	}
2171

2172 2173 2174 2175
	intel_dp_set_idle_link_train(intel_dp);

	intel_dp->DP = DP;

2176
	if (channel_eq)
M
Masanari Iida 已提交
2177
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2178

2179 2180 2181 2182 2183 2184
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
	intel_dp_set_link_train(intel_dp, intel_dp->DP,
				DP_TRAINING_PATTERN_DISABLE);
2185 2186 2187
}

static void
C
Chris Wilson 已提交
2188
intel_dp_link_down(struct intel_dp *intel_dp)
2189
{
2190 2191
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2192
	struct drm_i915_private *dev_priv = dev->dev_private;
2193 2194
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
C
Chris Wilson 已提交
2195
	uint32_t DP = intel_dp->DP;
2196

2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211
	/*
	 * DDI code has a strict mode set sequence and we should try to respect
	 * it, otherwise we might hang the machine in many different ways. So we
	 * really should be disabling the port only on a complete crtc_disable
	 * sequence. This function is just called under two conditions on DDI
	 * code:
	 * - Link train failed while doing crtc_enable, and on this case we
	 *   really should respect the mode set sequence and wait for a
	 *   crtc_disable.
	 * - Someone turned the monitor off and intel_dp_check_link_status
	 *   called us. We don't need to disable the whole port on this case, so
	 *   when someone turns the monitor on again,
	 *   intel_ddi_prepare_link_retrain will take care of redoing the link
	 *   train.
	 */
P
Paulo Zanoni 已提交
2212
	if (HAS_DDI(dev))
2213 2214
		return;

2215
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2216 2217
		return;

2218
	DRM_DEBUG_KMS("\n");
2219

K
Keith Packard 已提交
2220
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2221
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
2222
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2223 2224
	} else {
		DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
2225
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2226
	}
2227
	POSTING_READ(intel_dp->output_reg);
2228

2229 2230
	/* We don't really know why we're doing this */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
2231

2232
	if (HAS_PCH_IBX(dev) &&
2233
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2234
		struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2235

2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
2250 2251 2252 2253
		if (WARN_ON(crtc == NULL)) {
			/* We should never try to disable a port without a crtc
			 * attached. For paranoia keep the code around for a
			 * bit. */
2254 2255 2256
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
2257
			intel_wait_for_vblank(dev, intel_crtc->pipe);
2258 2259
	}

2260
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
2261 2262
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
2263
	msleep(intel_dp->panel_power_down_delay);
2264 2265
}

2266 2267
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
2268
{
2269 2270
	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];

2271
	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2272 2273
					   sizeof(intel_dp->dpcd)) == 0)
		return false; /* aux transfer failed */
2274

2275 2276 2277 2278
	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
			   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);

2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

	if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
					   intel_dp->downstream_ports,
					   DP_MAX_DOWNSTREAM_PORTS) == 0)
		return false; /* downstream port status fetch failed */

	return true;
2295 2296
}

2297 2298 2299 2300 2301 2302 2303 2304
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

D
Daniel Vetter 已提交
2305 2306
	ironlake_edp_panel_vdd_on(intel_dp);

2307 2308 2309 2310 2311 2312 2313
	if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

	if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
D
Daniel Vetter 已提交
2314 2315

	ironlake_edp_panel_vdd_off(intel_dp, false);
2316 2317
}

2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_aux_native_read_retry(intel_dp,
					     DP_DEVICE_SERVICE_IRQ_VECTOR,
					     sink_irq_vector, 1);
	if (!ret)
		return false;

	return true;
}

static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
2336
	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2337 2338
}

2339 2340 2341 2342 2343 2344 2345 2346 2347
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */

P
Paulo Zanoni 已提交
2348
void
C
Chris Wilson 已提交
2349
intel_dp_check_link_status(struct intel_dp *intel_dp)
2350
{
2351
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2352
	u8 sink_irq_vector;
2353
	u8 link_status[DP_LINK_STATUS_SIZE];
2354

2355
	if (!intel_encoder->connectors_active)
2356
		return;
2357

2358
	if (WARN_ON(!intel_encoder->base.crtc))
2359 2360
		return;

2361
	/* Try to read receiver status if the link appears to be up */
2362
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
C
Chris Wilson 已提交
2363
		intel_dp_link_down(intel_dp);
2364 2365 2366
		return;
	}

2367
	/* Now read the DPCD to see if it's actually running */
2368
	if (!intel_dp_get_dpcd(intel_dp)) {
2369 2370 2371 2372
		intel_dp_link_down(intel_dp);
		return;
	}

2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		intel_dp_aux_native_write_1(intel_dp,
					    DP_DEVICE_SERVICE_IRQ_VECTOR,
					    sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

2387
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2388
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2389
			      drm_get_encoder_name(&intel_encoder->base));
2390 2391
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
2392
		intel_dp_stop_link_train(intel_dp);
2393
	}
2394 2395
}

2396
/* XXX this is probably wrong for multiple downstream ports */
2397
static enum drm_connector_status
2398
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2399
{
2400 2401 2402 2403 2404 2405 2406 2407 2408
	uint8_t *dpcd = intel_dp->dpcd;
	bool hpd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2409
		return connector_status_connected;
2410 2411 2412 2413

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
	hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
	if (hpd) {
2414
		uint8_t reg;
2415
		if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2416
						    &reg, 1))
2417
			return connector_status_unknown;
2418 2419
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
2420 2421 2422 2423
	}

	/* If no HPD, poke DDC gently */
	if (drm_probe_ddc(&intel_dp->adapter))
2424
		return connector_status_connected;
2425 2426 2427 2428 2429 2430 2431 2432

	/* Well we tried, say unknown for unreliable port types */
	type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
	if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
		return connector_status_unknown;

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2433
	return connector_status_disconnected;
2434 2435
}

2436
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2437
ironlake_dp_detect(struct intel_dp *intel_dp)
2438
{
2439
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2440 2441
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2442 2443
	enum drm_connector_status status;

2444 2445
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
2446
		status = intel_panel_detect(dev);
2447 2448 2449 2450
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}
2451

2452 2453 2454
	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		return connector_status_disconnected;

2455
	return intel_dp_detect_dpcd(intel_dp);
2456 2457
}

2458
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2459
g4x_dp_detect(struct intel_dp *intel_dp)
2460
{
2461
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2462
	struct drm_i915_private *dev_priv = dev->dev_private;
2463
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2464
	uint32_t bit;
2465

2466 2467 2468 2469 2470 2471 2472 2473 2474 2475
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

2476 2477
	switch (intel_dig_port->port) {
	case PORT_B:
2478
		bit = PORTB_HOTPLUG_LIVE_STATUS;
2479
		break;
2480
	case PORT_C:
2481
		bit = PORTC_HOTPLUG_LIVE_STATUS;
2482
		break;
2483
	case PORT_D:
2484
		bit = PORTD_HOTPLUG_LIVE_STATUS;
2485 2486 2487 2488 2489
		break;
	default:
		return connector_status_unknown;
	}

2490
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2491 2492
		return connector_status_disconnected;

2493
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
2494 2495
}

2496 2497 2498
static struct edid *
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
{
2499
	struct intel_connector *intel_connector = to_intel_connector(connector);
2500

2501 2502 2503 2504 2505 2506 2507
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		struct edid *edid;
		int size;

		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
2508 2509
			return NULL;

2510
		size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2511
		edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2512 2513 2514 2515 2516
		if (!edid)
			return NULL;

		return edid;
	}
2517

2518
	return drm_get_edid(connector, adapter);
2519 2520 2521 2522 2523
}

static int
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
{
2524
	struct intel_connector *intel_connector = to_intel_connector(connector);
2525

2526 2527 2528 2529 2530 2531 2532 2533
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
			return 0;

		return intel_connector_update_modes(connector,
						    intel_connector->edid);
2534 2535
	}

2536
	return intel_ddc_get_modes(connector, adapter);
2537 2538
}

Z
Zhenyu Wang 已提交
2539 2540 2541 2542
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2543 2544
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
2545
	struct drm_device *dev = connector->dev;
Z
Zhenyu Wang 已提交
2546 2547 2548 2549 2550 2551 2552 2553 2554
	enum drm_connector_status status;
	struct edid *edid = NULL;

	intel_dp->has_audio = false;

	if (HAS_PCH_SPLIT(dev))
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
2555

Z
Zhenyu Wang 已提交
2556 2557 2558
	if (status != connector_status_connected)
		return status;

2559 2560
	intel_dp_probe_oui(intel_dp);

2561 2562
	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2563
	} else {
2564
		edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2565 2566 2567 2568
		if (edid) {
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
			kfree(edid);
		}
Z
Zhenyu Wang 已提交
2569 2570
	}

2571 2572
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Z
Zhenyu Wang 已提交
2573
	return connector_status_connected;
2574 2575 2576 2577
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
2578
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2579
	struct intel_connector *intel_connector = to_intel_connector(connector);
2580
	struct drm_device *dev = connector->dev;
2581
	int ret;
2582 2583 2584 2585

	/* We should parse the EDID data and find out if it has an audio sink
	 */

2586
	ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2587
	if (ret)
2588 2589
		return ret;

2590
	/* if eDP has no EDID, fall back to fixed mode */
2591
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2592
		struct drm_display_mode *mode;
2593 2594
		mode = drm_mode_duplicate(dev,
					  intel_connector->panel.fixed_mode);
2595
		if (mode) {
2596 2597 2598 2599 2600
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
2601 2602
}

2603 2604 2605 2606 2607 2608 2609
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct edid *edid;
	bool has_audio = false;

2610
	edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2611 2612 2613 2614 2615 2616 2617 2618
	if (edid) {
		has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}

	return has_audio;
}

2619 2620 2621 2622 2623
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
2624
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
2625
	struct intel_connector *intel_connector = to_intel_connector(connector);
2626 2627
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2628 2629
	int ret;

2630
	ret = drm_object_property_set_value(&connector->base, property, val);
2631 2632 2633
	if (ret)
		return ret;

2634
	if (property == dev_priv->force_audio_property) {
2635 2636 2637 2638
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
2639 2640
			return 0;

2641
		intel_dp->force_audio = i;
2642

2643
		if (i == HDMI_AUDIO_AUTO)
2644 2645
			has_audio = intel_dp_detect_audio(connector);
		else
2646
			has_audio = (i == HDMI_AUDIO_ON);
2647 2648

		if (has_audio == intel_dp->has_audio)
2649 2650
			return 0;

2651
		intel_dp->has_audio = has_audio;
2652 2653 2654
		goto done;
	}

2655
	if (property == dev_priv->broadcast_rgb_property) {
2656 2657 2658
		bool old_auto = intel_dp->color_range_auto;
		uint32_t old_range = intel_dp->color_range;

2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
			break;
		default:
			return -EINVAL;
		}
2674 2675 2676 2677 2678

		if (old_auto == intel_dp->color_range_auto &&
		    old_range == intel_dp->color_range)
			return 0;

2679 2680 2681
		goto done;
	}

2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

2698 2699 2700
	return -EINVAL;

done:
2701 2702
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
2703 2704 2705 2706

	return 0;
}

2707
static void
2708
intel_dp_destroy(struct drm_connector *connector)
2709
{
2710
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2711
	struct intel_connector *intel_connector = to_intel_connector(connector);
2712

2713 2714 2715
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

2716
	if (is_edp(intel_dp))
2717
		intel_panel_fini(&intel_connector->panel);
2718

2719 2720
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
2721
	kfree(connector);
2722 2723
}

P
Paulo Zanoni 已提交
2724
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2725
{
2726 2727
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
2728
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2729 2730 2731

	i2c_del_adapter(&intel_dp->adapter);
	drm_encoder_cleanup(encoder);
2732 2733
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2734
		mutex_lock(&dev->mode_config.mutex);
2735
		ironlake_panel_vdd_off_sync(intel_dp);
2736
		mutex_unlock(&dev->mode_config.mutex);
2737
	}
2738
	kfree(intel_dig_port);
2739 2740
}

2741 2742 2743 2744 2745
static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
	.mode_set = intel_dp_mode_set,
};

static const struct drm_connector_funcs intel_dp_connector_funcs = {
2746
	.dpms = intel_connector_dpms,
2747 2748
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
2749
	.set_property = intel_dp_set_property,
2750 2751 2752 2753 2754 2755
	.destroy = intel_dp_destroy,
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
2756
	.best_encoder = intel_best_encoder,
2757 2758 2759
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2760
	.destroy = intel_dp_encoder_destroy,
2761 2762
};

2763
static void
2764
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2765
{
2766
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2767

2768
	intel_dp_check_link_status(intel_dp);
2769
}
2770

2771 2772
/* Return which DP Port should be selected for Transcoder DP control */
int
2773
intel_trans_dp_port_sel(struct drm_crtc *crtc)
2774 2775
{
	struct drm_device *dev = crtc->dev;
2776 2777
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
2778

2779 2780
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
2781

2782 2783
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
2784
			return intel_dp->output_reg;
2785
	}
C
Chris Wilson 已提交
2786

2787 2788 2789
	return -1;
}

2790
/* check the VBT to see whether the eDP is on DP-D port */
2791
bool intel_dpd_is_edp(struct drm_device *dev)
2792 2793 2794 2795 2796
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct child_device_config *p_child;
	int i;

2797
	if (!dev_priv->vbt.child_dev_num)
2798 2799
		return false;

2800 2801
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
2802 2803 2804 2805 2806 2807 2808 2809

		if (p_child->dvo_port == PORT_IDPD &&
		    p_child->device_type == DEVICE_TYPE_eDP)
			return true;
	}
	return false;
}

2810 2811 2812
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
2813 2814
	struct intel_connector *intel_connector = to_intel_connector(connector);

2815
	intel_attach_force_audio_property(connector);
2816
	intel_attach_broadcast_rgb_property(connector);
2817
	intel_dp->color_range_auto = true;
2818 2819 2820

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
2821 2822
		drm_object_attach_property(
			&connector->base,
2823
			connector->dev->mode_config.scaling_mode_property,
2824 2825
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2826
	}
2827 2828
}

2829 2830
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2831 2832
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out)
2833 2834 2835 2836
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_power_seq cur, vbt, spec, final;
	u32 pp_on, pp_off, pp_div, pp;
2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849
	int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;

	if (HAS_PCH_SPLIT(dev)) {
		pp_control_reg = PCH_PP_CONTROL;
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
		pp_control_reg = PIPEA_PP_CONTROL;
		pp_on_reg = PIPEA_PP_ON_DELAYS;
		pp_off_reg = PIPEA_PP_OFF_DELAYS;
		pp_div_reg = PIPEA_PP_DIVISOR;
	}
2850 2851 2852

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
2853 2854
	pp = ironlake_get_pp_control(intel_dp);
	I915_WRITE(pp_control_reg, pp);
2855

2856 2857 2858
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
	pp_div = I915_READ(pp_div_reg);
2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

2879
	vbt = dev_priv->vbt.edp_pps;
2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
#define assign_final(field)	final.field = (max(cur.field, vbt.field) == 0 ? \
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

#define get_delay(field)	(DIV_ROUND_UP(final.field, 10))
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);

	if (out)
		*out = final;
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *seq)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
	int pp_on_reg, pp_off_reg, pp_div_reg;

	if (HAS_PCH_SPLIT(dev)) {
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
		pp_on_reg = PIPEA_PP_ON_DELAYS;
		pp_off_reg = PIPEA_PP_OFF_DELAYS;
		pp_div_reg = PIPEA_PP_DIVISOR;
	}

	if (IS_VALLEYVIEW(dev))
		port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2949

2950
	/* And finally store the new values in the power sequencer. */
2951 2952 2953 2954
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
		(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2955 2956
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
2957
	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2958
	pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2959 2960 2961 2962 2963 2964
			<< PANEL_POWER_CYCLE_DELAY_SHIFT);

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
		if (is_cpu_edp(intel_dp))
2965
			port_sel = PANEL_POWER_PORT_DP_A;
2966
		else
2967
			port_sel = PANEL_POWER_PORT_DP_D;
2968 2969
	}

2970 2971 2972 2973 2974
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
	I915_WRITE(pp_div_reg, pp_div);
2975 2976

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2977 2978 2979
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
		      I915_READ(pp_div_reg));
2980 2981
}

2982
void
2983 2984
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
2985
{
2986 2987 2988 2989
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
2990
	struct drm_i915_private *dev_priv = dev->dev_private;
2991
	struct drm_display_mode *fixed_mode = NULL;
2992
	struct edp_power_seq power_seq = { 0 };
2993
	enum port port = intel_dig_port->port;
2994
	const char *name = NULL;
2995
	int type;
2996

2997 2998
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
2999
	intel_dp->attached_connector = intel_connector;
3000

3001
	type = DRM_MODE_CONNECTOR_DisplayPort;
3002 3003 3004 3005
	/*
	 * FIXME : We need to initialize built-in panels before external panels.
	 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
	 */
3006 3007
	switch (port) {
	case PORT_A:
3008
		type = DRM_MODE_CONNECTOR_eDP;
3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019
		break;
	case PORT_C:
		if (IS_VALLEYVIEW(dev))
			type = DRM_MODE_CONNECTOR_eDP;
		break;
	case PORT_D:
		if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
			type = DRM_MODE_CONNECTOR_eDP;
		break;
	default:	/* silence GCC warning */
		break;
3020 3021
	}

3022 3023 3024 3025 3026 3027 3028 3029
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

3030 3031 3032 3033
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

3034
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3035 3036 3037 3038 3039
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

3040 3041
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
			  ironlake_panel_vdd_work);
3042

3043
	intel_connector_attach_encoder(intel_connector, intel_encoder);
3044 3045
	drm_sysfs_connector_add(connector);

P
Paulo Zanoni 已提交
3046
	if (HAS_DDI(dev))
3047 3048 3049 3050
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;

3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069
	intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
	if (HAS_DDI(dev)) {
		switch (intel_dig_port->port) {
		case PORT_A:
			intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
			break;
		case PORT_B:
			intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
			break;
		case PORT_C:
			intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
			break;
		case PORT_D:
			intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
			break;
		default:
			BUG();
		}
	}
3070

3071
	/* Set up the DDC bus. */
3072 3073
	switch (port) {
	case PORT_A:
3074
		intel_encoder->hpd_pin = HPD_PORT_A;
3075 3076 3077
		name = "DPDDC-A";
		break;
	case PORT_B:
3078
		intel_encoder->hpd_pin = HPD_PORT_B;
3079 3080 3081
		name = "DPDDC-B";
		break;
	case PORT_C:
3082
		intel_encoder->hpd_pin = HPD_PORT_C;
3083 3084 3085
		name = "DPDDC-C";
		break;
	case PORT_D:
3086
		intel_encoder->hpd_pin = HPD_PORT_D;
3087 3088 3089
		name = "DPDDC-D";
		break;
	default:
3090
		BUG();
3091 3092
	}

3093
	if (is_edp(intel_dp))
3094
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3095 3096 3097

	intel_dp_i2c_init(intel_dp, intel_connector, name);

3098
	/* Cache DPCD and EDID for edp. */
3099 3100
	if (is_edp(intel_dp)) {
		bool ret;
3101
		struct drm_display_mode *scan;
3102
		struct edid *edid;
3103 3104

		ironlake_edp_panel_vdd_on(intel_dp);
3105
		ret = intel_dp_get_dpcd(intel_dp);
3106
		ironlake_edp_panel_vdd_off(intel_dp, false);
3107

3108
		if (ret) {
3109 3110 3111
			if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
				dev_priv->no_aux_handshake =
					intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
J
Jesse Barnes 已提交
3112 3113
					DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
		} else {
3114
			/* if this fails, presume the device is a ghost */
3115
			DRM_INFO("failed to retrieve link info, disabling eDP\n");
3116 3117
			intel_dp_encoder_destroy(&intel_encoder->base);
			intel_dp_destroy(connector);
3118
			return;
J
Jesse Barnes 已提交
3119 3120
		}

3121 3122 3123 3124
		/* We now know it's not a ghost, init power sequence regs. */
		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
							      &power_seq);

3125 3126 3127
		ironlake_edp_panel_vdd_on(intel_dp);
		edid = drm_get_edid(connector, &intel_dp->adapter);
		if (edid) {
3128 3129 3130 3131 3132 3133 3134 3135 3136
			if (drm_add_edid_modes(connector, edid)) {
				drm_mode_connector_update_edid_property(connector, edid);
				drm_edid_to_eld(connector, edid);
			} else {
				kfree(edid);
				edid = ERR_PTR(-EINVAL);
			}
		} else {
			edid = ERR_PTR(-ENOENT);
3137
		}
3138
		intel_connector->edid = edid;
3139 3140 3141 3142 3143 3144 3145

		/* prefer fixed mode from EDID if available */
		list_for_each_entry(scan, &connector->probed_modes, head) {
			if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
				fixed_mode = drm_mode_duplicate(dev, scan);
				break;
			}
3146
		}
3147 3148

		/* fallback to VBT if available for eDP */
3149 3150
		if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
			fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
3151 3152 3153 3154
			if (fixed_mode)
				fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
		}

3155 3156
		ironlake_edp_panel_vdd_off(intel_dp, false);
	}
3157

3158
	if (is_edp(intel_dp)) {
3159
		intel_panel_init(&intel_connector->panel, fixed_mode);
3160
		intel_panel_setup_backlight(connector);
3161 3162
	}

3163 3164
	intel_dp_add_properties(intel_dp, connector);

3165 3166 3167 3168 3169 3170 3171 3172 3173
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}
3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

	intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
	if (!intel_dig_port)
		return;

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);
P
Paulo Zanoni 已提交
3198
	drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3199

3200
	intel_encoder->compute_config = intel_dp_compute_config;
P
Paulo Zanoni 已提交
3201 3202 3203 3204 3205
	intel_encoder->enable = intel_enable_dp;
	intel_encoder->pre_enable = intel_pre_enable_dp;
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->post_disable = intel_post_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
3206
	intel_encoder->get_config = intel_dp_get_config;
3207 3208
	if (IS_VALLEYVIEW(dev))
		intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3209

3210
	intel_dig_port->port = port;
3211 3212
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
3213
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3214 3215 3216 3217 3218 3219
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	intel_encoder->cloneable = false;
	intel_encoder->hot_plug = intel_dp_hot_plug;

	intel_dp_init_connector(intel_dig_port, intel_connector);
}