i915_drv.h 114.3 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include "i915_params.h"
#include "i915_reg.h"

#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_guc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20161108"
#define DRIVER_TIMESTAMP	1478587895
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
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#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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#endif

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#undef WARN_ON_ONCE
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#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
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#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
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 */
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enum plane {
	PLANE_A = 0,
	PLANE_B,
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	PLANE_C,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
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enum port {
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	PORT_NONE = -1,
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	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1
};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_universal_plane(__dev_priv, __pipe, __p)		\
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	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
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			    &(dev)->mode_config.connector_list,	\
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			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if ((1 << (domain)) & (mask))
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	unsigned int bsd_engine;
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};

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
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	struct opregion_asle *asle;
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	void *rvda;
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	const void *vbt;
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	u32 vbt_size;
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	u32 *lid_state;
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	struct work_struct asle_work;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_connector;
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struct intel_encoder;
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struct intel_atomic_state;
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struct intel_crtc_state;
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struct intel_initial_plane_config;
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struct intel_crtc;
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struct intel_limit;
struct dpll;
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struct drm_i915_display_funcs {
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	int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
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	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
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	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
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	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
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	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
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	int (*compute_global_watermarks)(struct drm_atomic_state *state);
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	void (*update_wm)(struct intel_crtc *crtc);
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	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
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	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
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				struct intel_crtc_state *);
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	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
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	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
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	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
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	void (*update_crtcs)(struct drm_atomic_state *state,
			     unsigned int *crtc_vblank_mask);
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	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
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				   const struct drm_display_mode *adjusted_mode);
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	void (*audio_codec_disable)(struct intel_encoder *encoder);
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	void (*fdi_link_train)(struct drm_crtc *crtc);
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	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
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	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
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	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
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	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
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	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
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};

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enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

554 555 556 557 558 559 560
#define FW_REG_READ  (1)
#define FW_REG_WRITE (2)

enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op);

561
struct intel_uncore_funcs {
562
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
563
							enum forcewake_domains domains);
564
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
565
							enum forcewake_domains domains);
566

567 568 569 570
	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
571

572
	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
573
				uint8_t val, bool trace);
574
	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
575
				uint16_t val, bool trace);
576
	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
577
				uint32_t val, bool trace);
578 579
};

580 581 582 583 584 585 586
struct intel_forcewake_range {
	u32 start;
	u32 end;

	enum forcewake_domains domains;
};

587 588 589
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

590 591 592
	const struct intel_forcewake_range *fw_domains_table;
	unsigned int fw_domains_table_entries;

593 594 595
	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
596

597
	enum forcewake_domains fw_domains;
598
	enum forcewake_domains fw_domains_active;
599 600 601

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
602
		enum forcewake_domain_id id;
603
		enum forcewake_domains mask;
604
		unsigned wake_count;
605
		struct hrtimer timer;
606
		i915_reg_t reg_set;
607 608
		u32 val_set;
		u32 val_clear;
609 610
		i915_reg_t reg_ack;
		i915_reg_t reg_post;
611
		u32 val_reset;
612
	} fw_domain[FW_DOMAIN_ID_COUNT];
613 614

	int unclaimed_mmio_check;
615 616 617
};

/* Iterate over initialised fw domains */
618 619 620 621 622 623 624 625
#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
	for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
	     (domain__)++) \
		for_each_if ((mask__) & (domain__)->mask)

#define for_each_fw_domain(domain__, dev_priv__) \
	for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
626

627 628 629 630
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

631
struct intel_csr {
632
	struct work_struct work;
633
	const char *fw_path;
634
	uint32_t *dmc_payload;
635
	uint32_t dmc_fw_size;
636
	uint32_t version;
637
	uint32_t mmio_count;
638
	i915_reg_t mmioaddr[8];
639
	uint32_t mmiodata[8];
640
	uint32_t dc_state;
641
	uint32_t allowed_dc_mask;
642 643
};

644
#define DEV_INFO_FOR_EACH_FLAG(func) \
645
	/* Keep is_* in chronological order */ \
646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662
	func(is_mobile); \
	func(is_i85x); \
	func(is_i915g); \
	func(is_i945gm); \
	func(is_g33); \
	func(is_g4x); \
	func(is_pineview); \
	func(is_broadwater); \
	func(is_crestline); \
	func(is_ivybridge); \
	func(is_valleyview); \
	func(is_cherryview); \
	func(is_haswell); \
	func(is_broadwell); \
	func(is_skylake); \
	func(is_broxton); \
	func(is_kabylake); \
663
	func(is_alpha_support); \
664
	/* Keep has_* in alphabetical order */ \
665
	func(has_64bit_reloc); \
666
	func(has_csr); \
667
	func(has_ddi); \
668
	func(has_dp_mst); \
669 670
	func(has_fbc); \
	func(has_fpga_dbg); \
671 672 673 674
	func(has_gmbus_irq); \
	func(has_gmch_display); \
	func(has_guc); \
	func(has_hotplug); \
675 676
	func(has_hw_contexts); \
	func(has_l3_dpf); \
677
	func(has_llc); \
678 679 680 681 682 683 684 685 686
	func(has_logical_ring_contexts); \
	func(has_overlay); \
	func(has_pipe_cxsr); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
687
	func(has_snoop); \
688 689 690 691
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
	func(supports_tv)
D
Daniel Vetter 已提交
692

693
struct sseu_dev_info {
694
	u8 slice_mask;
695
	u8 subslice_mask;
696 697
	u8 eu_total;
	u8 eu_per_subslice;
698 699 700 701 702 703
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
704 705
};

706 707 708 709 710
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

711
struct intel_device_info {
712
	u32 display_mmio_offset;
713
	u16 device_id;
714
	u8 num_pipes;
715
	u8 num_sprites[I915_MAX_PIPES];
716
	u8 gen;
717
	u16 gen_mask;
718
	u8 ring_mask; /* Rings supported by the HW */
719
	u8 num_rings;
720 721 722
#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
723
	u16 ddb_size; /* in blocks */
724 725 726 727
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
728
	int cursor_offsets[I915_MAX_PIPES];
729 730

	/* Slice/subslice/EU info */
731
	struct sseu_dev_info sseu;
732 733 734 735 736

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
737 738
};

739 740 741 742 743
struct intel_display_error_state;

struct drm_i915_error_state {
	struct kref ref;
	struct timeval time;
744 745
	struct timeval boottime;
	struct timeval uptime;
746

747 748
	struct drm_i915_private *i915;

749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772
	char error_msg[128];
	bool simulated;
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
	u32 gtier[4];
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
773

774 775 776
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
777
	struct drm_i915_error_object *semaphore;
778
	struct drm_i915_error_object *guc_log;
779 780 781 782 783 784 785 786 787 788 789

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
		int hangcheck_score;
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;

790 791 792
		/* position of active request inside the ring */
		u32 rq_head, rq_post, rq_tail;

793 794 795 796 797 798 799 800 801 802 803
		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
804
		u32 mode;
805 806 807 808 809 810 811 812 813 814 815 816 817
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
818
		struct intel_instdone instdone;
819 820 821

		struct drm_i915_error_object {
			u64 gtt_offset;
822
			u64 gtt_size;
823 824
			int page_count;
			int unused;
825 826 827 828 829 830 831
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
832
			pid_t pid;
833
			u32 context;
834 835 836
			u32 seqno;
			u32 head;
			u32 tail;
837
		} *requests, execlist[2];
838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;

		pid_t pid;
		char comm[TASK_COMM_LEN];
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

876 877
enum i915_cache_level {
	I915_CACHE_NONE = 0,
878 879 880 881 882
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
883
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
884 885
};

886 887 888 889 890 891
struct i915_ctx_hang_stats {
	/* This context had batch pending when hang was declared */
	unsigned batch_pending;

	/* This context had batch active when hang was declared */
	unsigned batch_active;
892 893 894 895

	/* Time when this context was last blamed for a GPU reset */
	unsigned long guilty_ts;

896 897 898 899 900
	/* If the contexts causes a second GPU hang within this time,
	 * it is permanently banned from submitting any more work.
	 */
	unsigned long ban_period_seconds;

901 902
	/* This context is banned to submit more work */
	bool banned;
903
};
904 905

/* This must match up with the value previously used for execbuf2.rsvd1. */
906
#define DEFAULT_CONTEXT_HANDLE 0
907

908
/**
909
 * struct i915_gem_context - as the name implies, represents a context.
910 911 912
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
913 914
 * @flags: context specific flags:
 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
915 916 917 918
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
919
 * @ppgtt: virtual memory space used by this context.
920 921 922 923 924 925 926
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
927
struct i915_gem_context {
928
	struct kref ref;
929
	struct drm_i915_private *i915;
930
	struct drm_i915_file_private *file_priv;
931
	struct i915_hw_ppgtt *ppgtt;
932
	struct pid *pid;
933
	const char *name;
934

935 936 937
	struct i915_ctx_hang_stats hang_stats;

	unsigned long flags;
938 939
#define CONTEXT_NO_ZEROMAP		BIT(0)
#define CONTEXT_NO_ERROR_CAPTURE	BIT(1)
940 941 942

	/* Unique identifier for this context, used by the hw for tracking */
	unsigned int hw_id;
943
	u32 user_handle;
944
	int priority; /* greater priorities are serviced first */
945

946 947
	u32 ggtt_alignment;

948
	struct intel_context {
949
		struct i915_vma *state;
950
		struct intel_ring *ring;
951
		uint32_t *lrc_reg_state;
952 953
		u64 lrc_desc;
		int pin_count;
954
		bool initialised;
955
	} engine[I915_NUM_ENGINES];
956
	u32 ring_size;
957
	u32 desc_template;
958
	struct atomic_notifier_head status_notifier;
959
	bool execlists_force_single_submission;
960

961
	struct list_head link;
962 963

	u8 remap_slice;
964
	bool closed:1;
965 966
};

967 968 969 970 971
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
972
	ORIGIN_DIRTYFB,
973 974
};

975
struct intel_fbc {
P
Paulo Zanoni 已提交
976 977 978
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
979
	unsigned threshold;
980 981
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
982
	unsigned int visible_pipes_mask;
983
	struct intel_crtc *crtc;
984

985
	struct drm_mm_node compressed_fb;
986 987
	struct drm_mm_node *compressed_llb;

988 989
	bool false_color;

990
	bool enabled;
991
	bool active;
992

993 994 995
	bool underrun_detected;
	struct work_struct underrun_work;

996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017
	struct intel_fbc_state_cache {
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
			u64 ilk_ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
			unsigned int tiling_mode;
		} fb;
	} state_cache;

1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034
	struct intel_fbc_reg_params {
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
			u64 ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
		} fb;

		int cfb_size;
	} params;

1035
	struct intel_fbc_work {
1036
		bool scheduled;
1037
		u32 scheduled_vblank;
1038 1039
		struct work_struct work;
	} work;
1040

1041
	const char *no_fbc_reason;
1042 1043
};

1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1059 1060
};

1061
struct intel_dp;
1062 1063 1064 1065 1066 1067 1068 1069 1070
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1071
struct i915_psr {
1072
	struct mutex lock;
R
Rodrigo Vivi 已提交
1073 1074
	bool sink_support;
	bool source_ok;
1075
	struct intel_dp *enabled;
1076 1077
	bool active;
	struct delayed_work work;
1078
	unsigned busy_frontbuffer_bits;
1079 1080
	bool psr2_support;
	bool aux_frame_sync;
1081
	bool link_standby;
1082
};
1083

1084
enum intel_pch {
1085
	PCH_NONE = 0,	/* No PCH present */
1086 1087
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1088
	PCH_LPT,	/* Lynxpoint PCH */
1089
	PCH_SPT,        /* Sunrisepoint PCH */
1090
	PCH_KBP,        /* Kabypoint PCH */
B
Ben Widawsky 已提交
1091
	PCH_NOP,
1092 1093
};

1094 1095 1096 1097 1098
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1099
#define QUIRK_PIPEA_FORCE (1<<0)
1100
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1101
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1102
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1103
#define QUIRK_PIPEB_FORCE (1<<4)
1104
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1105

1106
struct intel_fbdev;
1107
struct intel_fbc_work;
1108

1109 1110
struct intel_gmbus {
	struct i2c_adapter adapter;
1111
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1112
	u32 force_bit;
1113
	u32 reg0;
1114
	i915_reg_t gpio_reg;
1115
	struct i2c_algo_bit_data bit_algo;
1116 1117 1118
	struct drm_i915_private *dev_priv;
};

1119
struct i915_suspend_saved_registers {
1120
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1121
	u32 saveFBC_CONTROL;
1122 1123
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1124 1125
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1126
	u32 saveSWF3[3];
1127
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1128
	u32 savePCH_PORT_HOTPLUG;
1129
	u16 saveGCDGMBUS;
1130
};
1131

1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1190
	u32 pcbr;
1191 1192 1193
	u32 clock_gate_dis2;
};

1194 1195 1196 1197
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1198 1199
};

1200
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1201 1202 1203 1204
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1205
	struct work_struct work;
I
Imre Deak 已提交
1206
	bool interrupts_enabled;
1207
	u32 pm_iir;
1208

1209
	/* PM interrupt bits that should never be masked */
1210 1211
	u32 pm_intr_keep;

1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1227
	u8 boost_freq;		/* Frequency to request when wait boosting */
1228
	u8 idle_freq;		/* Frequency to request when we are idle */
1229 1230 1231
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1232
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1233

1234 1235 1236
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1237 1238 1239
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1240 1241 1242 1243
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1244
	bool enabled;
1245
	struct delayed_work autoenable_work;
1246
	unsigned boosts;
1247

1248 1249 1250
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1251 1252
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1253 1254 1255
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1256 1257
	 */
	struct mutex hw_lock;
1258 1259
};

D
Daniel Vetter 已提交
1260 1261 1262
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1274
	u64 last_time2;
1275 1276 1277 1278 1279 1280 1281
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1312 1313
/* Power well structure for haswell */
struct i915_power_well {
1314
	const char *name;
1315
	bool always_on;
1316 1317
	/* power well enable/disable usage count */
	int count;
1318 1319
	/* cached hw enabled state */
	bool hw_enabled;
1320
	unsigned long domains;
1321 1322
	/* unique identifier for this power well */
	unsigned long id;
1323 1324 1325 1326 1327
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
	unsigned long data;
1328
	const struct i915_power_well_ops *ops;
1329 1330
};

1331
struct i915_power_domains {
1332 1333 1334 1335 1336
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1337
	bool initializing;
1338
	int power_well_count;
1339

1340
	struct mutex lock;
1341
	int domain_use_count[POWER_DOMAIN_NUM];
1342
	struct i915_power_well *power_wells;
1343 1344
};

1345
#define MAX_L3_SLICES 2
1346
struct intel_l3_parity {
1347
	u32 *remap_info[MAX_L3_SLICES];
1348
	struct work_struct error_work;
1349
	int which_slice;
1350 1351
};

1352 1353 1354
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1355 1356 1357 1358
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1359 1360 1361 1362 1363
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
1364 1365
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
1366 1367 1368
	 */
	struct list_head unbound_list;

1369 1370 1371 1372 1373
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

1374 1375 1376 1377 1378 1379
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;

1380 1381 1382 1383 1384 1385
	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1386
	struct notifier_block oom_notifier;
1387
	struct notifier_block vmap_notifier;
1388
	struct shrinker shrinker;
1389 1390 1391 1392 1393 1394 1395 1396 1397 1398

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1399
	/* the indicator for dispatch video commands on two BSD rings */
1400
	atomic_t bsd_engine_dispatch_index;
1401

1402 1403 1404 1405 1406 1407
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1408
	spinlock_t object_stat_lock;
1409
	u64 object_memory;
1410 1411 1412
	u32 object_count;
};

1413
struct drm_i915_error_state_buf {
1414
	struct drm_i915_private *i915;
1415 1416 1417 1418 1419 1420 1421 1422
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1423 1424 1425 1426 1427
struct i915_error_state_file_priv {
	struct drm_device *dev;
	struct drm_i915_error_state *error;
};

1428 1429 1430
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

1431 1432 1433 1434
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1435 1436 1437
	/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)

1438
	struct delayed_work hangcheck_work;
1439 1440 1441 1442 1443

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1444 1445 1446

	unsigned long missed_irq_rings;

1447
	/**
M
Mika Kuoppala 已提交
1448
	 * State variable controlling the reset flow and count
1449
	 *
M
Mika Kuoppala 已提交
1450
	 * This is a counter which gets incremented when reset is triggered,
1451 1452 1453 1454
	 *
	 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
M
Mika Kuoppala 已提交
1455 1456 1457 1458 1459 1460 1461 1462 1463
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1464 1465 1466 1467
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1468
	 */
1469
	unsigned long reset_count;
1470

1471 1472 1473
	unsigned long flags;
#define I915_RESET_IN_PROGRESS	0
#define I915_WEDGED		(BITS_PER_LONG - 1)
1474

1475 1476 1477 1478 1479 1480
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1481 1482 1483 1484 1485
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1486

1487
	/* For missed irq/seqno simulation. */
1488
	unsigned long test_irq_rings;
1489 1490
};

1491 1492 1493 1494 1495 1496
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1497 1498 1499 1500 1501
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1502 1503 1504 1505
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1506
struct ddi_vbt_port_info {
1507 1508 1509 1510 1511 1512
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1513
	uint8_t hdmi_level_shift;
1514 1515 1516 1517

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1518 1519

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1520
	uint8_t alternate_ddc_pin;
1521 1522 1523

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1524 1525
};

R
Rodrigo Vivi 已提交
1526 1527 1528 1529 1530
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1531 1532
};

1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1545
	unsigned int panel_type:4;
1546 1547 1548
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1549 1550
	enum drrs_support_type drrs_type;

1551 1552 1553 1554 1555
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1556
		bool low_vswing;
1557 1558 1559 1560 1561
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1562

R
Rodrigo Vivi 已提交
1563 1564 1565 1566 1567 1568 1569 1570 1571
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1572 1573
	struct {
		u16 pwm_freq_hz;
1574
		bool present;
1575
		bool active_low_pwm;
1576
		u8 min_brightness;	/* min_brightness/255 of max */
1577
		enum intel_backlight_type type;
1578 1579
	} backlight;

1580 1581 1582
	/* MIPI DSI */
	struct {
		u16 panel_id;
1583 1584 1585 1586 1587
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1588
		const u8 *sequence[MIPI_SEQ_MAX];
1589 1590
	} dsi;

1591 1592 1593
	int crt_ddc_pin;

	int child_dev_num;
1594
	union child_device_config *child_dev;
1595 1596

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1597
	struct sdvo_device_mapping sdvo_mappings[2];
1598 1599
};

1600 1601 1602 1603 1604
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1605 1606 1607 1608 1609 1610 1611 1612
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1613
struct ilk_wm_values {
1614 1615 1616 1617 1618 1619 1620 1621
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1622 1623 1624 1625 1626
struct vlv_pipe_wm {
	uint16_t primary;
	uint16_t sprite[2];
	uint8_t cursor;
};
1627

1628 1629 1630 1631
struct vlv_sr_wm {
	uint16_t plane;
	uint8_t cursor;
};
1632

1633 1634 1635
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1636 1637 1638 1639 1640
	struct {
		uint8_t cursor;
		uint8_t sprite[2];
		uint8_t primary;
	} ddl[3];
1641 1642
	uint8_t level;
	bool cxsr;
1643 1644
};

1645
struct skl_ddb_entry {
1646
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1647 1648 1649 1650
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1651
	return entry->end - entry->start;
1652 1653
}

1654 1655 1656 1657 1658 1659 1660 1661 1662
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1663
struct skl_ddb_allocation {
1664
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1665
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1666 1667
};

1668
struct skl_wm_values {
1669
	unsigned dirty_pipes;
1670
	struct skl_ddb_allocation ddb;
1671 1672 1673
};

struct skl_wm_level {
L
Lyude 已提交
1674 1675 1676
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1677 1678
};

1679
/*
1680 1681 1682 1683
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1684
 *
1685 1686 1687
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1688
 *
1689 1690
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1691
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1692
 * it can be changed with the standard runtime PM files from sysfs.
1693 1694 1695 1696 1697
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1698
 * case it happens.
1699
 *
1700
 * For more, read the Documentation/power/runtime_pm.txt.
1701
 */
1702
struct i915_runtime_pm {
1703
	atomic_t wakeref_count;
1704
	bool suspended;
1705
	bool irqs_enabled;
1706 1707
};

1708 1709 1710 1711 1712
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1713
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1714 1715 1716 1717 1718
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1719
	INTEL_PIPE_CRC_SOURCE_AUTO,
1720 1721 1722
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1723
struct intel_pipe_crc_entry {
1724
	uint32_t frame;
1725 1726 1727
	uint32_t crc[5];
};

1728
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1729
struct intel_pipe_crc {
1730 1731
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1732
	struct intel_pipe_crc_entry *entries;
1733
	enum intel_pipe_crc_source source;
1734
	int head, tail;
1735
	wait_queue_head_t wq;
1736 1737
};

1738
struct i915_frontbuffer_tracking {
1739
	spinlock_t lock;
1740 1741 1742 1743 1744 1745 1746 1747 1748

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1749
struct i915_wa_reg {
1750
	i915_reg_t addr;
1751 1752 1753 1754 1755
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1756 1757 1758 1759 1760 1761 1762
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1763 1764 1765 1766

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1767
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1768 1769
};

1770 1771 1772 1773
struct i915_virtual_gpu {
	bool active;
};

1774 1775 1776 1777 1778 1779 1780
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1781
struct drm_i915_private {
1782 1783
	struct drm_device drm;

1784
	struct kmem_cache *objects;
1785
	struct kmem_cache *vmas;
1786
	struct kmem_cache *requests;
1787
	struct kmem_cache *dependencies;
1788

1789
	const struct intel_device_info info;
1790 1791 1792 1793 1794

	int relative_constants_mode;

	void __iomem *regs;

1795
	struct intel_uncore uncore;
1796

1797 1798
	struct i915_virtual_gpu vgpu;

1799
	struct intel_gvt *gvt;
1800

1801 1802
	struct intel_guc guc;

1803 1804
	struct intel_csr csr;

1805
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1806

1807 1808 1809 1810 1811 1812 1813 1814 1815
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1816 1817 1818
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1819 1820
	uint32_t psr_mmio_base;

1821 1822
	uint32_t pps_mmio_base;

1823 1824
	wait_queue_head_t gmbus_wait_queue;

1825
	struct pci_dev *bridge_dev;
1826
	struct i915_gem_context *kernel_context;
1827
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
1828
	struct i915_vma *semaphore;
1829

1830
	struct drm_dma_handle *status_page_dmah;
1831 1832 1833 1834 1835
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1836 1837 1838
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1839 1840
	bool display_irqs_enabled;

1841 1842 1843
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1844 1845
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1846 1847

	/** Cached value of IMR to avoid reads in updating the bitfield */
1848 1849 1850 1851
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1852
	u32 gt_irq_mask;
1853 1854
	u32 pm_imr;
	u32 pm_ier;
1855
	u32 pm_rps_events;
1856
	u32 pm_guc_events;
1857
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1858

1859
	struct i915_hotplug hotplug;
1860
	struct intel_fbc fbc;
1861
	struct i915_drrs drrs;
1862
	struct intel_opregion opregion;
1863
	struct intel_vbt_data vbt;
1864

1865 1866
	bool preserve_bios_swizzle;

1867 1868 1869
	/* overlay */
	struct intel_overlay *overlay;

1870
	/* backlight registers and fields in struct intel_panel */
1871
	struct mutex backlight_lock;
1872

1873 1874 1875
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1876 1877 1878
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1879 1880 1881 1882
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1883
	unsigned int skl_preferred_vco_freq;
1884
	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
M
Mika Kahola 已提交
1885
	unsigned int max_dotclk_freq;
1886
	unsigned int rawclk_freq;
1887
	unsigned int hpll_freq;
1888
	unsigned int czclk_freq;
1889

1890
	struct {
1891
		unsigned int vco, ref;
1892 1893
	} cdclk_pll;

1894 1895 1896 1897 1898 1899 1900
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1901 1902 1903 1904 1905 1906 1907
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1908
	unsigned short pch_id;
1909 1910 1911

	unsigned long quirks;

1912 1913
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1914
	struct drm_atomic_state *modeset_restore_state;
1915
	struct drm_modeset_acquire_ctx reset_ctx;
1916

1917
	struct list_head vm_list; /* Global list of all address spaces */
1918
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1919

1920
	struct i915_gem_mm mm;
1921 1922
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1923

1924 1925 1926 1927 1928 1929 1930
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

1931 1932
	/* Kernel Modesetting */

1933 1934
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1935 1936
	wait_queue_head_t pending_flip_queue;

1937 1938 1939 1940
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

1941
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
1942 1943
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1944
	const struct intel_dpll_mgr *dpll_mgr;
1945

1946 1947 1948 1949 1950 1951 1952
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

1953 1954 1955
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

1956
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1957

1958
	struct i915_workarounds workarounds;
1959

1960 1961
	struct i915_frontbuffer_tracking fb_tracking;

1962
	u16 orig_clock;
1963

1964
	bool mchbar_need_disable;
1965

1966 1967
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1968
	/* Cannot be determined by PCIID. You must always read a register. */
1969
	u32 edram_cap;
B
Ben Widawsky 已提交
1970

1971
	/* gen6+ rps state */
1972
	struct intel_gen6_power_mgmt rps;
1973

1974 1975
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1976
	struct intel_ilk_power_mgmt ips;
1977

1978
	struct i915_power_domains power_domains;
1979

R
Rodrigo Vivi 已提交
1980
	struct i915_psr psr;
1981

1982
	struct i915_gpu_error gpu_error;
1983

1984 1985
	struct drm_i915_gem_object *vlv_pctx;

1986
#ifdef CONFIG_DRM_FBDEV_EMULATION
1987 1988
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1989
	struct work_struct fbdev_suspend_work;
1990
#endif
1991 1992

	struct drm_property *broadcast_rgb_property;
1993
	struct drm_property *force_audio_property;
1994

I
Imre Deak 已提交
1995
	/* hda/i915 audio component */
1996
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1997
	bool audio_component_registered;
1998 1999 2000 2001 2002
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
2003

2004
	uint32_t hw_context_size;
2005
	struct list_head context_list;
2006

2007
	u32 fdi_rx_config;
2008

2009
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2010
	u32 chv_phy_control;
2011 2012 2013 2014 2015 2016
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
2017
	u32 bxt_phy_grc;
2018

2019
	u32 suspend_count;
2020
	bool suspended_to_idle;
2021
	struct i915_suspend_saved_registers regfile;
2022
	struct vlv_s0ix_state vlv_s0ix_state;
2023

2024
	enum {
2025 2026 2027 2028 2029
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
2030

2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2043 2044 2045 2046 2047 2048
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2049 2050

		/* current hardware state */
2051 2052 2053
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2054
			struct vlv_wm_values vlv;
2055
		};
2056 2057

		uint8_t max_level;
2058 2059 2060 2061 2062 2063 2064

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2065 2066 2067 2068 2069 2070 2071

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2072 2073
	} wm;

2074 2075
	struct i915_runtime_pm pm;

2076 2077
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2078
		void (*resume)(struct drm_i915_private *);
2079
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2080

2081 2082
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2083
		u32 active_requests;
2084

2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2111 2112

		ktime_t last_init_time;
2113 2114
	} gt;

2115 2116 2117
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

2118 2119
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2120

2121 2122 2123 2124
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2125
};
L
Linus Torvalds 已提交
2126

2127 2128
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2129
	return container_of(dev, struct drm_i915_private, drm);
2130 2131
}

2132
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2133
{
2134
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2135 2136
}

2137 2138 2139 2140 2141
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

2142
/* Simple iterator over all initialised engines */
2143 2144 2145 2146 2147
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2148

2149 2150 2151 2152 2153 2154
#define __mask_next_bit(mask) ({					\
	int __idx = ffs(mask) - 1;					\
	mask &= ~BIT(__idx);						\
	__idx;								\
})

2155
/* Iterator over subset of engines selected by mask */
2156 2157
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
2158
	     tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2159

2160 2161 2162 2163 2164 2165 2166
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2167
#define I915_GTT_OFFSET_NONE ((u32)-1)
2168

2169 2170
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2171
 * considered to be the frontbuffer for the given plane interface-wise. This
2172 2173 2174 2175 2176
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2177 2178
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2179 2180 2181
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2182 2183 2184
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2185
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2186
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2187
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2188
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2189

2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2216 2217 2218 2219 2220 2221 2222 2223
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2238
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2239 2240
}

2241 2242 2243 2244 2245 2246 2247 2248 2249 2250
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2251
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2264
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2265

2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317
/*
 * A command that requires special handling by the command parser.
 */
struct drm_i915_cmd_descriptor {
	/*
	 * Flags describing how the command parser processes the command.
	 *
	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
	 *                 a length mask if not set
	 * CMD_DESC_SKIP: The command is allowed but does not follow the
	 *                standard length encoding for the opcode range in
	 *                which it falls
	 * CMD_DESC_REJECT: The command is never allowed
	 * CMD_DESC_REGISTER: The command should be checked against the
	 *                    register whitelist for the appropriate ring
	 * CMD_DESC_MASTER: The command is allowed if the submitting process
	 *                  is the DRM master
	 */
	u32 flags;
#define CMD_DESC_FIXED    (1<<0)
#define CMD_DESC_SKIP     (1<<1)
#define CMD_DESC_REJECT   (1<<2)
#define CMD_DESC_REGISTER (1<<3)
#define CMD_DESC_BITMASK  (1<<4)
#define CMD_DESC_MASTER   (1<<5)

	/*
	 * The command's unique identification bits and the bitmask to get them.
	 * This isn't strictly the opcode field as defined in the spec and may
	 * also include type, subtype, and/or subop fields.
	 */
	struct {
		u32 value;
		u32 mask;
	} cmd;

	/*
	 * The command's length. The command is either fixed length (i.e. does
	 * not include a length field) or has a length field mask. The flag
	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
	 * a length mask. All command entries in a command table must include
	 * length information.
	 */
	union {
		u32 fixed;
		u32 mask;
	} length;

	/*
	 * Describes where to find a register address in the command to check
	 * against the ring's register whitelist. Only valid if flags has the
	 * CMD_DESC_REGISTER bit set.
2318 2319 2320 2321
	 *
	 * A non-zero step value implies that the command may access multiple
	 * registers in sequence (e.g. LRI), in that case step gives the
	 * distance in dwords between individual offset fields.
2322 2323 2324 2325
	 */
	struct {
		u32 offset;
		u32 mask;
2326
		u32 step;
2327 2328 2329 2330 2331 2332 2333 2334 2335
	} reg;

#define MAX_CMD_DESC_BITMASKS 3
	/*
	 * Describes command checks where a particular dword is masked and
	 * compared against an expected value. If the command does not match
	 * the expected value, the parser rejects it. Only valid if flags has
	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
	 * are valid.
2336 2337 2338 2339
	 *
	 * If the check specifies a non-zero condition_mask then the parser
	 * only performs the check when the bits specified by condition_mask
	 * are non-zero.
2340 2341 2342 2343 2344
	 */
	struct {
		u32 offset;
		u32 mask;
		u32 expected;
2345 2346
		u32 condition_offset;
		u32 condition_mask;
2347 2348 2349 2350 2351 2352
	} bits[MAX_CMD_DESC_BITMASKS];
};

/*
 * A table of commands requiring special handling by the command parser.
 *
2353 2354 2355
 * Each engine has an array of tables. Each table consists of an array of
 * command descriptors, which must be sorted with command opcodes in
 * ascending order.
2356 2357 2358 2359 2360 2361
 */
struct drm_i915_cmd_table {
	const struct drm_i915_cmd_descriptor *table;
	int count;
};

C
Chris Wilson 已提交
2362
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2363 2364 2365 2366 2367 2368 2369 2370 2371 2372
#define __I915__(p) ({ \
	struct drm_i915_private *__p; \
	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		__p = (struct drm_i915_private *)p; \
	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		__p = to_i915((struct drm_device *)p); \
	else \
		BUILD_BUG(); \
	__p; \
})
2373
#define INTEL_INFO(p)	(&__I915__(p)->info)
2374

2375
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2376
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2377

2378
#define REVID_FOREVER		0xff
2379
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2380 2381 2382 2383 2384 2385 2386

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2387
#define IS_GEN(dev_priv, s, e) ({ \
2388 2389 2390 2391 2392 2393 2394 2395 2396
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
2397
	!!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2398 2399
})

2400 2401 2402 2403 2404 2405 2406 2407
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2408 2409
#define IS_I830(dev_priv)	(INTEL_DEVID(dev_priv) == 0x3577)
#define IS_845G(dev_priv)	(INTEL_DEVID(dev_priv) == 0x2562)
2410
#define IS_I85X(dev_priv)	((dev_priv)->info.is_i85x)
2411
#define IS_I865G(dev_priv)	(INTEL_DEVID(dev_priv) == 0x2572)
2412
#define IS_I915G(dev_priv)	((dev_priv)->info.is_i915g)
2413 2414
#define IS_I915GM(dev_priv)	(INTEL_DEVID(dev_priv) == 0x2592)
#define IS_I945G(dev_priv)	(INTEL_DEVID(dev_priv) == 0x2772)
2415
#define IS_I945GM(dev_priv)	((dev_priv)->info.is_i945gm)
2416 2417
#define IS_BROADWATER(dev_priv)	((dev_priv)->info.is_broadwater)
#define IS_CRESTLINE(dev_priv)	((dev_priv)->info.is_crestline)
2418
#define IS_GM45(dev_priv)	(INTEL_DEVID(dev_priv) == 0x2A42)
2419
#define IS_G4X(dev_priv)	((dev_priv)->info.is_g4x)
2420 2421
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
2422
#define IS_PINEVIEW(dev_priv)	((dev_priv)->info.is_pineview)
2423
#define IS_G33(dev_priv)	((dev_priv)->info.is_g33)
2424
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
2425
#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.is_ivybridge)
2426 2427 2428
#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
				 INTEL_DEVID(dev_priv) == 0x0152 || \
				 INTEL_DEVID(dev_priv) == 0x015a)
2429
#define IS_VALLEYVIEW(dev_priv)	((dev_priv)->info.is_valleyview)
2430
#define IS_CHERRYVIEW(dev_priv)	((dev_priv)->info.is_cherryview)
2431
#define IS_HASWELL(dev_priv)	((dev_priv)->info.is_haswell)
2432
#define IS_BROADWELL(dev_priv)	((dev_priv)->info.is_broadwell)
2433
#define IS_SKYLAKE(dev_priv)	((dev_priv)->info.is_skylake)
2434
#define IS_BROXTON(dev_priv)	((dev_priv)->info.is_broxton)
2435
#define IS_KABYLAKE(dev_priv)	((dev_priv)->info.is_kabylake)
2436
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2437 2438 2439 2440 2441 2442
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2443
/* ULX machines are also considered ULT. */
2444 2445 2446 2447 2448 2449 2450 2451
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2452
/* ULX machines are also considered ULT. */
2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2475

2476
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2477

2478 2479 2480 2481 2482 2483
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2484 2485
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2486

2487 2488
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2489
#define BXT_REVID_A0		0x0
2490
#define BXT_REVID_A1		0x1
2491 2492
#define BXT_REVID_B0		0x3
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2493

2494 2495
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2496

M
Mika Kuoppala 已提交
2497 2498
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2499 2500 2501
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2502

2503 2504
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2505

2506 2507 2508 2509 2510 2511
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2512 2513 2514 2515 2516 2517 2518 2519
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2520

2521 2522 2523 2524 2525 2526 2527 2528 2529
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2530
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2531 2532 2533 2534 2535 2536

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2537 2538 2539
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2540 2541
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2542

2543
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2544

2545 2546 2547 2548 2549 2550 2551 2552 2553 2554
#define HAS_HW_CONTEXTS(dev_priv)	    ((dev_priv)->info.has_hw_contexts)
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2555

2556
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2557
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_845G(dev_priv))
2558 2559

/* WaRsDisableCoarsePowerGating:skl,bxt */
2560 2561 2562 2563
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
	(IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
	 IS_SKL_GT3(dev_priv) || \
	 IS_SKL_GT4(dev_priv))
2564

2565 2566 2567 2568 2569 2570
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
2571 2572
#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2573

2574 2575 2576
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2577 2578 2579
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2580 2581
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2582

2583 2584 2585
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2586

2587
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2588

2589
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2590

2591 2592 2593 2594 2595
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
P
Paulo Zanoni 已提交
2596

2597
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2598

2599
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2600 2601
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2602 2603 2604 2605 2606
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2607 2608 2609
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2610

2611
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2612

2613
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2614

2615 2616 2617 2618 2619 2620
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2621 2622
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2623
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2624
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2625
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2626
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2627

2628 2629 2630 2631
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2632 2633 2634 2635
#define HAS_PCH_LPT_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2636 2637 2638 2639
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2640

2641
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2642

2643 2644
#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))

2645
/* DPF == dynamic parity feature */
2646
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2647 2648
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
2649

2650
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2651
#define GEN9_FREQ_SCALER 3
2652

2653 2654
#include "i915_trace.h"

2655 2656 2657 2658 2659 2660 2661 2662 2663
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

2664 2665
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
extern int i915_resume_switcheroo(struct drm_device *dev);
2666

2667
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2668
				int enable_ppgtt);
2669

2670 2671
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

2672
/* i915_drv.c */
2673 2674 2675 2676 2677 2678 2679
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2680
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2681 2682
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2683
#endif
2684 2685 2686 2687 2688
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
2689 2690
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2691
extern void i915_reset(struct drm_i915_private *dev_priv);
2692
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2693
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2694
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2695 2696 2697 2698
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2699
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2700

2701
/* intel_hotplug.c */
2702 2703
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
2704 2705 2706
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2707
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2708 2709
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2710

L
Linus Torvalds 已提交
2711
/* i915_irq.c */
2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2729
__printf(3, 4)
2730 2731
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2732
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2733

2734
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2735 2736
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2737

2738 2739
extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2740
					bool restore_forcewake);
2741
extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2742
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2743
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2744 2745 2746
extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
					 bool restore);
2747
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2748
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2749
				enum forcewake_domains domains);
2750
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2751
				enum forcewake_domains domains);
2752 2753 2754 2755 2756 2757 2758
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
2759 2760
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

2761
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2762

2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773
int intel_wait_for_register(struct drm_i915_private *dev_priv,
			    i915_reg_t reg,
			    const u32 mask,
			    const u32 value,
			    const unsigned long timeout_ms);
int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
			       i915_reg_t reg,
			       const u32 mask,
			       const u32 value,
			       const unsigned long timeout_ms);

2774 2775
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
2776
	return dev_priv->gvt;
2777 2778
}

2779
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2780
{
2781
	return dev_priv->vgpu.active;
2782
}
2783

2784
void
2785
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2786
		     u32 status_mask);
2787 2788

void
2789
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2790
		      u32 status_mask);
2791

2792 2793
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2794 2795 2796
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
2824 2825 2826
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

2838 2839 2840 2841 2842 2843 2844 2845 2846
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2847 2848
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2849 2850 2851 2852 2853 2854
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
2855 2856
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
2857 2858
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
2859 2860 2861 2862
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2863 2864
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
2865 2866
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
2867 2868 2869 2870
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2871
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2872 2873
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
2874 2875
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
2876 2877
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2878
int i915_gem_load_init(struct drm_device *dev);
2879
void i915_gem_load_cleanup(struct drm_device *dev);
2880
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2881
int i915_gem_freeze(struct drm_i915_private *dev_priv);
2882 2883
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

2884 2885
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
2886 2887
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
2888
struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
2889
						   u64 size);
2890 2891
struct drm_i915_gem_object *i915_gem_object_create_from_data(
		struct drm_device *dev, const void *data, size_t size);
2892
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2893
void i915_gem_free_object(struct drm_gem_object *obj);
2894

C
Chris Wilson 已提交
2895
struct i915_vma * __must_check
2896 2897
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
2898
			 u64 size,
2899 2900
			 u64 alignment,
			 u64 flags);
2901

2902
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2903
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2904

2905 2906
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
2907
static inline int __sg_page_count(const struct scatterlist *sg)
2908
{
2909 2910
	return sg->length >> PAGE_SHIFT;
}
2911

2912 2913 2914
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
2915

2916 2917 2918
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
2919

2920 2921 2922
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
2923

2924 2925 2926
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
2927

2928 2929
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
				 struct sg_table *pages);
C
Chris Wilson 已提交
2930 2931 2932 2933 2934
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
2935
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
2936

2937
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
2938 2939 2940 2941 2942 2943 2944
		return 0;

	return __i915_gem_object_get_pages(obj);
}

static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2945
{
C
Chris Wilson 已提交
2946 2947
	GEM_BUG_ON(!obj->mm.pages);

2948
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
2949 2950 2951 2952 2953
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
2954
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
2955 2956 2957 2958 2959 2960 2961 2962
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
	GEM_BUG_ON(!obj->mm.pages);

2963 2964
	atomic_dec(&obj->mm.pages_pin_count);
	GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count);
2965
}
2966

2967 2968
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2969
{
C
Chris Wilson 已提交
2970
	__i915_gem_object_unpin_pages(obj);
2971 2972
}

2973 2974 2975 2976 2977 2978 2979
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
2980
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
2981

2982 2983 2984 2985 2986
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
};

2987 2988 2989
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
 * @obj - the object to map into kernel address space
2990
 * @type - the type of mapping, used to select pgprot_t
2991 2992 2993
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
2994 2995
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
2996
 *
2997 2998
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
2999
 *
3000 3001
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3002
 */
3003 3004
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
 * @obj - the object to unmap
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
#define CLFLUSH_BEFORE 0x1
#define CLFLUSH_AFTER 0x2
#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3034
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3035
void i915_vma_move_to_active(struct i915_vma *vma,
3036 3037
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3038 3039 3040
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3041 3042
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3043
int i915_gem_mmap_gtt_version(void);
3044 3045 3046 3047 3048

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3049
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3050

3051
struct drm_i915_gem_request *
3052
i915_gem_find_active_request(struct intel_engine_cs *engine);
3053

3054
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3055

3056 3057
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
3058
	return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3059 3060
}

3061
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3062
{
3063
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3064 3065
}

3066
static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3067
{
3068
	return i915_reset_in_progress(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3069 3070 3071 3072
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3073
	return READ_ONCE(error->reset_count);
3074
}
3075

3076 3077
void i915_gem_reset(struct drm_i915_private *dev_priv);
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3078
void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3079
int __must_check i915_gem_init(struct drm_device *dev);
3080 3081
int __must_check i915_gem_init_hw(struct drm_device *dev);
void i915_gem_init_swizzling(struct drm_device *dev);
3082
void i915_gem_cleanup_engines(struct drm_device *dev);
3083
int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3084
					unsigned int flags);
3085
int __must_check i915_gem_suspend(struct drm_device *dev);
3086
void i915_gem_resume(struct drm_device *dev);
3087
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3088 3089 3090 3091
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3092 3093 3094 3095 3096
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3097
int __must_check
3098 3099 3100
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3101
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3102
struct i915_vma * __must_check
3103 3104
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3105
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3106
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3107
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3108
				int align);
3109
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3110
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3111

3112 3113 3114
u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
			   int tiling_mode);
u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3115
				int tiling_mode, bool fenced);
3116

3117 3118 3119
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3120 3121 3122 3123 3124 3125
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3126
struct i915_vma *
3127
i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
C
Chris Wilson 已提交
3128 3129
		     struct i915_address_space *vm,
		     const struct i915_ggtt_view *view);
3130

3131 3132
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
C
Chris Wilson 已提交
3133 3134
				  struct i915_address_space *vm,
				  const struct i915_ggtt_view *view);
3135

3136 3137 3138 3139 3140 3141
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

C
Chris Wilson 已提交
3142 3143 3144
static inline struct i915_vma *
i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
			const struct i915_ggtt_view *view)
3145
{
C
Chris Wilson 已提交
3146
	return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3147 3148
}

C
Chris Wilson 已提交
3149 3150 3151
static inline unsigned long
i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
			    const struct i915_ggtt_view *view)
3152
{
3153
	return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3154
}
3155

J
Joonas Lahtinen 已提交
3156
/* i915_gem_fence_reg.c */
3157 3158 3159
int __must_check i915_vma_get_fence(struct i915_vma *vma);
int __must_check i915_vma_put_fence(struct i915_vma *vma);

3160 3161
void i915_gem_restore_fences(struct drm_device *dev);

3162
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3163 3164 3165 3166
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3167

3168
/* i915_gem_context.c */
3169
int __must_check i915_gem_context_init(struct drm_device *dev);
3170
void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3171
void i915_gem_context_fini(struct drm_device *dev);
3172
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3173
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3174
int i915_switch_context(struct drm_i915_gem_request *req);
3175
int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3176 3177 3178
struct i915_vma *
i915_gem_context_pin_legacy(struct i915_gem_context *ctx,
			    unsigned int flags);
3179
void i915_gem_context_free(struct kref *ctx_ref);
3180 3181
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3182 3183
struct i915_gem_context *
i915_gem_context_create_gvt(struct drm_device *dev);
3184 3185 3186 3187 3188 3189

static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3190
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3191 3192 3193 3194 3195 3196 3197 3198

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3199 3200
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3201
{
3202
	kref_get(&ctx->ref);
3203
	return ctx;
3204 3205
}

3206
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3207
{
3208
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3209
	kref_put(&ctx->ref, i915_gem_context_free);
3210 3211
}

C
Chris Wilson 已提交
3212 3213 3214 3215 3216 3217 3218 3219 3220 3221
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3222
static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3223
{
3224
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3225 3226
}

3227 3228 3229 3230
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
3231 3232 3233 3234
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3235 3236
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
				       struct drm_file *file);
3237

3238
/* i915_gem_evict.c */
3239
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3240
					  u64 min_size, u64 alignment,
3241
					  unsigned cache_level,
3242
					  u64 start, u64 end,
3243
					  unsigned flags);
3244
int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3245
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3246

3247
/* belongs in i915_gem_gtt.h */
3248
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3249
{
3250
	wmb();
3251
	if (INTEL_GEN(dev_priv) < 6)
3252 3253
		intel_gtt_chipset_flush();
}
3254

3255
/* i915_gem_stolen.c */
3256 3257 3258
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3259 3260 3261 3262
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3263 3264
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3265 3266
int i915_gem_init_stolen(struct drm_device *dev);
void i915_gem_cleanup_stolen(struct drm_device *dev);
3267 3268
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3269 3270 3271 3272 3273
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3274

3275 3276 3277 3278 3279
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
				unsigned int size);

3280 3281
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3282
			      unsigned long target,
3283 3284 3285 3286
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3287
#define I915_SHRINK_ACTIVE 0x8
3288
#define I915_SHRINK_VMAPS 0x10
3289 3290
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3291
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3292 3293


3294
/* i915_gem_tiling.c */
3295
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3296
{
3297
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3298 3299

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3300
		i915_gem_object_is_tiled(obj);
3301 3302
}

3303
/* i915_debugfs.c */
3304
#ifdef CONFIG_DEBUG_FS
3305 3306
int i915_debugfs_register(struct drm_i915_private *dev_priv);
void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3307
int i915_debugfs_connector_add(struct drm_connector *connector);
3308
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3309
#else
3310 3311
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3312 3313
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3314
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3315
#endif
3316 3317

/* i915_gpu_error.c */
3318 3319
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

3320 3321
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3322 3323
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3324
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3325
			      struct drm_i915_private *i915,
3326 3327 3328 3329 3330 3331
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3332 3333
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3334
			      const char *error_msg);
3335 3336 3337 3338 3339
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);

3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353
#else

static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
					    u32 engine_mask,
					    const char *error_msg)
{
}

static inline void i915_destroy_error_state(struct drm_device *dev)
{
}

#endif

3354
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3355

3356
/* i915_cmd_parser.c */
3357
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3358
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3359 3360 3361 3362 3363 3364 3365 3366
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3367

3368 3369 3370
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
3371

B
Ben Widawsky 已提交
3372
/* i915_sysfs.c */
D
David Weinehall 已提交
3373 3374
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3375

3376 3377 3378
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
3379 3380
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3381

3382 3383
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3384 3385
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3386
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3387 3388 3389
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3390 3391
extern void intel_i2c_reset(struct drm_device *dev);

3392
/* intel_bios.c */
3393
int intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3394
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3395
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3396
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3397
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3398
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3399
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3400
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3401 3402
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3403 3404 3405
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

3406

3407
/* intel_opregion.c */
3408
#ifdef CONFIG_ACPI
3409
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3410 3411
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3412
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3413 3414
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3415
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3416
					 pci_power_t state);
3417
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3418
#else
3419
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3420 3421
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3422 3423 3424
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3425 3426 3427 3428 3429
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3430
static inline int
3431
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3432 3433 3434
{
	return 0;
}
3435
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3436 3437 3438
{
	return -ENODEV;
}
3439
#endif
3440

J
Jesse Barnes 已提交
3441 3442 3443 3444 3445 3446 3447 3448 3449
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3450 3451 3452 3453 3454 3455 3456 3457 3458 3459
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3460
/* modesetting */
3461
extern void intel_modeset_init_hw(struct drm_device *dev);
3462
extern int intel_modeset_init(struct drm_device *dev);
3463
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3464
extern void intel_modeset_cleanup(struct drm_device *dev);
3465
extern int intel_connector_register(struct drm_connector *);
3466
extern void intel_connector_unregister(struct drm_connector *);
3467
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3468
extern void intel_display_resume(struct drm_device *dev);
3469
extern void i915_redisable_vga(struct drm_device *dev);
3470
extern void i915_redisable_vga_power_on(struct drm_device *dev);
3471
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
P
Paulo Zanoni 已提交
3472
extern void intel_init_pch_refclk(struct drm_device *dev);
3473
extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3474 3475
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
				  bool enable);
3476

B
Ben Widawsky 已提交
3477 3478
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3479

3480
/* overlay */
3481 3482
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3483 3484
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3485

3486 3487
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3488
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3489 3490
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
3491

3492 3493
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3494 3495

/* intel_sideband.c */
3496 3497
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3498
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3499 3500
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3501 3502 3503 3504
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3505 3506
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3507 3508
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3509 3510 3511 3512
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3513 3514
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3515

3516
/* intel_dpio_phy.c */
3517 3518
void bxt_port_to_phy_channel(enum port port,
			     enum dpio_phy *phy, enum dpio_channel *ch);
3519 3520 3521
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
					     uint8_t lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3534 3535 3536
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3537 3538
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3539
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3540 3541
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3542
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3543

3544 3545 3546
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3547
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3548
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3549
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3550

3551 3552
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3553

3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3567 3568 3569 3570
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3571 3572 3573 3574 3575 3576 3577 3578 3579
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3580
 */
3581
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3582

3583
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3584 3585
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3586
	do {								\
3587
		old_upper = upper;					\
3588
		lower = I915_READ(lower_reg);				\
3589 3590
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3591
	(u64)upper << 32 | lower; })
3592

3593 3594 3595
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3596 3597
#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3598
					     i915_reg_t reg) \
3599
{ \
3600
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3601 3602 3603 3604
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3605
				       i915_reg_t reg, uint##x##_t val) \
3606
{ \
3607
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3622
/* These are untraced mmio-accessors that are only valid to be used inside
3623
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3624
 * controlled.
3625
 *
3626
 * Think twice, and think again, before using these.
3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
3647
 */
3648 3649
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3650
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3651 3652
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3653 3654 3655 3656
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3657

3658
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3659
{
3660
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3661
		return VLV_VGACNTRL;
3662
	else if (INTEL_GEN(dev_priv) >= 5)
3663
		return CPU_VGACNTRL;
3664 3665 3666 3667
	else
		return VGACNTRL;
}

3668 3669 3670 3671 3672 3673 3674
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3675 3676 3677 3678 3679
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3680 3681 3682 3683 3684 3685 3686 3687
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3688 3689 3690 3691 3692 3693 3694 3695 3696
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3697
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3698 3699 3700 3701 3702 3703 3704 3705 3706 3707

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3708 3709 3710 3711
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3712 3713
	}
}
3714 3715 3716

static inline bool
__i915_request_irq_complete(struct drm_i915_gem_request *req)
3717
{
3718 3719
	struct intel_engine_cs *engine = req->engine;

3720 3721 3722
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
3723
	if (__i915_gem_request_completed(req))
3724 3725
		return true;

3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
3737
	if (engine->irq_seqno_barrier &&
3738
	    rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3739
	    cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3740 3741
		struct task_struct *tsk;

3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
3754
		engine->irq_seqno_barrier(engine);
3755 3756 3757 3758 3759 3760 3761 3762

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
		rcu_read_lock();
3763
		tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3764 3765 3766 3767 3768 3769 3770 3771 3772 3773
		if (tsk && tsk != current)
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
			wake_up_process(tsk);
		rcu_read_unlock();

3774
		if (__i915_gem_request_completed(req))
3775 3776
			return true;
	}
3777 3778 3779 3780

	return false;
}

3781 3782 3783
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

3784 3785 3786 3787 3788
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

3789 3790 3791 3792 3793
#define ptr_mask_bits(ptr) ({						\
	unsigned long __v = (unsigned long)(ptr);			\
	(typeof(ptr))(__v & PAGE_MASK);					\
})

3794 3795 3796 3797 3798 3799 3800 3801 3802
#define ptr_unpack_bits(ptr, bits) ({					\
	unsigned long __v = (unsigned long)(ptr);			\
	(bits) = __v & ~PAGE_MASK;					\
	(typeof(ptr))(__v & PAGE_MASK);					\
})

#define ptr_pack_bits(ptr, bits)					\
	((typeof(ptr))((unsigned long)(ptr) | (bits)))

3803 3804 3805 3806 3807 3808
#define fetch_and_zero(ptr) ({						\
	typeof(*ptr) __T = *(ptr);					\
	*(ptr) = (typeof(*ptr))0;					\
	__T;								\
})

L
Linus Torvalds 已提交
3809
#endif