perf_event.c 48.2 KB
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/*
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 * Performance events x86 architecture code
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 *
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 *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
 *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
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 *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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 *  Copyright (C) 2009 Google, Inc., Stephane Eranian
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 *
 *  For licencing details see kernel-base/COPYING
 */

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#include <linux/perf_event.h>
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#include <linux/capability.h>
#include <linux/notifier.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
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#include <linux/module.h>
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#include <linux/kdebug.h>
#include <linux/sched.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/cpu.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <asm/apic.h>
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#include <asm/stacktrace.h>
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#include <asm/nmi.h>
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#include <asm/smp.h>
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#include <asm/alternative.h>
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#include <asm/timer.h>
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#include <asm/desc.h>
#include <asm/ldt.h>
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#include "perf_event.h"

struct x86_pmu x86_pmu __read_mostly;
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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
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	.enabled = 1,
};
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u64 __read_mostly hw_cache_event_ids
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				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
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u64 __read_mostly hw_cache_extra_regs
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				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
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/*
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 * Propagate event elapsed time into the generic event.
 * Can only be executed on the CPU where the event is active.
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 * Returns the delta events processed.
 */
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u64 x86_perf_event_update(struct perf_event *event)
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{
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	struct hw_perf_event *hwc = &event->hw;
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	int shift = 64 - x86_pmu.cntval_bits;
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	u64 prev_raw_count, new_raw_count;
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	int idx = hwc->idx;
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	s64 delta;
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68
	if (idx == INTEL_PMC_IDX_FIXED_BTS)
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		return 0;

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	/*
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	 * Careful: an NMI might modify the previous event value.
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	 *
	 * Our tactic to handle this is to first atomically read and
	 * exchange a new raw count - then add that new-prev delta
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	 * count to the generic event atomically:
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	 */
again:
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	prev_raw_count = local64_read(&hwc->prev_count);
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	rdpmcl(hwc->event_base_rdpmc, new_raw_count);
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	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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					new_raw_count) != prev_raw_count)
		goto again;

	/*
	 * Now we have the new raw value and have updated the prev
	 * timestamp already. We can now calculate the elapsed delta
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	 * (event-)time and add that to the generic event.
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	 *
	 * Careful, not all hw sign-extends above the physical width
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	 * of the count.
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	 */
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	delta = (new_raw_count << shift) - (prev_raw_count << shift);
	delta >>= shift;
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	local64_add(delta, &event->count);
	local64_sub(delta, &hwc->period_left);
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	return new_raw_count;
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}

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/*
 * Find and validate any extra registers to set up.
 */
static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
{
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	struct hw_perf_event_extra *reg;
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	struct extra_reg *er;

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	reg = &event->hw.extra_reg;
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	if (!x86_pmu.extra_regs)
		return 0;

	for (er = x86_pmu.extra_regs; er->msr; er++) {
		if (er->event != (config & er->config_mask))
			continue;
		if (event->attr.config1 & ~er->valid_mask)
			return -EINVAL;
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		reg->idx = er->idx;
		reg->config = event->attr.config1;
		reg->reg = er->msr;
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		break;
	}
	return 0;
}

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static atomic_t active_events;
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static DEFINE_MUTEX(pmc_reserve_mutex);

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#ifdef CONFIG_X86_LOCAL_APIC

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static bool reserve_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
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			goto perfctr_fail;
	}

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
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			goto eventsel_fail;
	}

	return true;

eventsel_fail:
	for (i--; i >= 0; i--)
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		release_evntsel_nmi(x86_pmu_config_addr(i));
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	i = x86_pmu.num_counters;
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perfctr_fail:
	for (i--; i >= 0; i--)
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		release_perfctr_nmi(x86_pmu_event_addr(i));
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	return false;
}

static void release_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		release_perfctr_nmi(x86_pmu_event_addr(i));
		release_evntsel_nmi(x86_pmu_config_addr(i));
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	}
}

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#else

static bool reserve_pmc_hardware(void) { return true; }
static void release_pmc_hardware(void) {}

#endif

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static bool check_hw_exists(void)
{
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	u64 val, val_fail, val_new= ~0;
	int i, reg, reg_fail, ret = 0;
	int bios_fail = 0;
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	/*
	 * Check to see if the BIOS enabled any of the counters, if so
	 * complain and bail.
	 */
	for (i = 0; i < x86_pmu.num_counters; i++) {
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		reg = x86_pmu_config_addr(i);
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		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
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		if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
			bios_fail = 1;
			val_fail = val;
			reg_fail = reg;
		}
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	}

	if (x86_pmu.num_counters_fixed) {
		reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
		for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
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			if (val & (0x03 << i*4)) {
				bios_fail = 1;
				val_fail = val;
				reg_fail = reg;
			}
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		}
	}

	/*
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	 * Read the current value, change it and read it back to see if it
	 * matches, this is needed to detect certain hardware emulators
	 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
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	 */
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	reg = x86_pmu_event_addr(0);
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	if (rdmsrl_safe(reg, &val))
		goto msr_fail;
	val ^= 0xffffUL;
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	ret = wrmsrl_safe(reg, val);
	ret |= rdmsrl_safe(reg, &val_new);
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	if (ret || val != val_new)
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		goto msr_fail;
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	/*
	 * We still allow the PMU driver to operate:
	 */
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	if (bios_fail) {
		printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
		printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
	}
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	return true;
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msr_fail:
	printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
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	printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new);
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	return false;
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}

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static void hw_perf_event_destroy(struct perf_event *event)
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{
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	if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
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		release_pmc_hardware();
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		release_ds_buffers();
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		mutex_unlock(&pmc_reserve_mutex);
	}
}

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static inline int x86_pmu_initialized(void)
{
	return x86_pmu.handle_irq != NULL;
}

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static inline int
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set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
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{
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	struct perf_event_attr *attr = &event->attr;
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	unsigned int cache_type, cache_op, cache_result;
	u64 config, val;

	config = attr->config;

	cache_type = (config >>  0) & 0xff;
	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
		return -EINVAL;

	cache_op = (config >>  8) & 0xff;
	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
		return -EINVAL;

	cache_result = (config >> 16) & 0xff;
	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
		return -EINVAL;

	val = hw_cache_event_ids[cache_type][cache_op][cache_result];

	if (val == 0)
		return -ENOENT;

	if (val == -1)
		return -EINVAL;

	hwc->config |= val;
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	attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
	return x86_pmu_extra_regs(val, event);
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}

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int x86_setup_perfctr(struct perf_event *event)
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{
	struct perf_event_attr *attr = &event->attr;
	struct hw_perf_event *hwc = &event->hw;
	u64 config;

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	if (!is_sampling_event(event)) {
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		hwc->sample_period = x86_pmu.max_period;
		hwc->last_period = hwc->sample_period;
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		local64_set(&hwc->period_left, hwc->sample_period);
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	} else {
		/*
		 * If we have a PMU initialized but no APIC
		 * interrupts, we cannot sample hardware
		 * events (user-space has to fall back and
		 * sample via a hrtimer based software event):
		 */
		if (!x86_pmu.apic)
			return -EOPNOTSUPP;
	}

	if (attr->type == PERF_TYPE_RAW)
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		return x86_pmu_extra_regs(event->attr.config, event);
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	if (attr->type == PERF_TYPE_HW_CACHE)
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		return set_ext_hw_attr(hwc, event);
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	if (attr->config >= x86_pmu.max_events)
		return -EINVAL;

	/*
	 * The generic map:
	 */
	config = x86_pmu.event_map(attr->config);

	if (config == 0)
		return -ENOENT;

	if (config == -1LL)
		return -EINVAL;

	/*
	 * Branch tracing:
	 */
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	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
	    !attr->freq && hwc->sample_period == 1) {
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		/* BTS is not supported by this architecture. */
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		if (!x86_pmu.bts_active)
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			return -EOPNOTSUPP;

		/* BTS is currently only allowed for user-mode. */
		if (!attr->exclude_kernel)
			return -EOPNOTSUPP;
	}

	hwc->config |= config;

	return 0;
}
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/*
 * check that branch_sample_type is compatible with
 * settings needed for precise_ip > 1 which implies
 * using the LBR to capture ALL taken branches at the
 * priv levels of the measurement
 */
static inline int precise_br_compat(struct perf_event *event)
{
	u64 m = event->attr.branch_sample_type;
	u64 b = 0;

	/* must capture all branches */
	if (!(m & PERF_SAMPLE_BRANCH_ANY))
		return 0;

	m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_user)
		b |= PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_kernel)
		b |= PERF_SAMPLE_BRANCH_KERNEL;

	/*
	 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
	 */

	return m == b;
}

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int x86_pmu_hw_config(struct perf_event *event)
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{
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	if (event->attr.precise_ip) {
		int precise = 0;

		/* Support for constant skid */
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		if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
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			precise++;

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			/* Support for IP fixup */
			if (x86_pmu.lbr_nr)
				precise++;
		}
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		if (event->attr.precise_ip > precise)
			return -EOPNOTSUPP;
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		/*
		 * check that PEBS LBR correction does not conflict with
		 * whatever the user is asking with attr->branch_sample_type
		 */
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		if (event->attr.precise_ip > 1 &&
		    x86_pmu.intel_cap.pebs_format < 2) {
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			u64 *br_type = &event->attr.branch_sample_type;

			if (has_branch_stack(event)) {
				if (!precise_br_compat(event))
					return -EOPNOTSUPP;

				/* branch_sample_type is compatible */

			} else {
				/*
				 * user did not specify  branch_sample_type
				 *
				 * For PEBS fixups, we capture all
				 * the branches at the priv level of the
				 * event.
				 */
				*br_type = PERF_SAMPLE_BRANCH_ANY;

				if (!event->attr.exclude_user)
					*br_type |= PERF_SAMPLE_BRANCH_USER;

				if (!event->attr.exclude_kernel)
					*br_type |= PERF_SAMPLE_BRANCH_KERNEL;
			}
		}
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	}

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	/*
	 * Generate PMC IRQs:
	 * (keep 'enabled' bit clear for now)
	 */
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	event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
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	/*
	 * Count user and OS events unless requested not to
	 */
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	if (!event->attr.exclude_user)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
	if (!event->attr.exclude_kernel)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
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	if (event->attr.type == PERF_TYPE_RAW)
		event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
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	return x86_setup_perfctr(event);
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}

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/*
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 * Setup the hardware configuration for a given attr_type
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 */
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static int __x86_pmu_event_init(struct perf_event *event)
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{
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	int err;
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	if (!x86_pmu_initialized())
		return -ENODEV;
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	err = 0;
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	if (!atomic_inc_not_zero(&active_events)) {
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		mutex_lock(&pmc_reserve_mutex);
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		if (atomic_read(&active_events) == 0) {
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			if (!reserve_pmc_hardware())
				err = -EBUSY;
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			else
				reserve_ds_buffers();
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		}
		if (!err)
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			atomic_inc(&active_events);
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		mutex_unlock(&pmc_reserve_mutex);
	}
	if (err)
		return err;

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	event->destroy = hw_perf_event_destroy;
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	event->hw.idx = -1;
	event->hw.last_cpu = -1;
	event->hw.last_tag = ~0ULL;
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	/* mark unused */
	event->hw.extra_reg.idx = EXTRA_REG_NONE;
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	event->hw.branch_reg.idx = EXTRA_REG_NONE;

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	return x86_pmu.hw_config(event);
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}

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void x86_pmu_disable_all(void)
495
{
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	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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	int idx;

499
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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		u64 val;

502
		if (!test_bit(idx, cpuc->active_mask))
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			continue;
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		rdmsrl(x86_pmu_config_addr(idx), val);
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		if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
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			continue;
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		val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
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		wrmsrl(x86_pmu_config_addr(idx), val);
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	}
}

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static void x86_pmu_disable(struct pmu *pmu)
513
{
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	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);

516
	if (!x86_pmu_initialized())
517
		return;
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	if (!cpuc->enabled)
		return;

	cpuc->n_added = 0;
	cpuc->enabled = 0;
	barrier();
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	x86_pmu.disable_all();
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}
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void x86_pmu_enable_all(int added)
530
{
531
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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	int idx;

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	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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		struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
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		if (!test_bit(idx, cpuc->active_mask))
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			continue;
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		__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
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	}
}

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static struct pmu pmu;
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static inline int is_x86_event(struct perf_event *event)
{
	return event->pmu == &pmu;
}

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/*
 * Event scheduler state:
 *
 * Assign events iterating over all events and counters, beginning
 * with events with least weights first. Keep the current iterator
 * state in struct sched_state.
 */
struct sched_state {
	int	weight;
	int	event;		/* event index */
	int	counter;	/* counter index */
	int	unassigned;	/* number of events to be assigned left */
	unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
};

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/* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
#define	SCHED_STATES_MAX	2

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struct perf_sched {
	int			max_weight;
	int			max_events;
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	struct perf_event	**events;
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	struct sched_state	state;
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	int			saved_states;
	struct sched_state	saved[SCHED_STATES_MAX];
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};

/*
 * Initialize interator that runs through all events and counters.
 */
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static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
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			    int num, int wmin, int wmax)
{
	int idx;

	memset(sched, 0, sizeof(*sched));
	sched->max_events	= num;
	sched->max_weight	= wmax;
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	sched->events		= events;
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	for (idx = 0; idx < num; idx++) {
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		if (events[idx]->hw.constraint->weight == wmin)
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			break;
	}

	sched->state.event	= idx;		/* start with min weight */
	sched->state.weight	= wmin;
	sched->state.unassigned	= num;
}

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static void perf_sched_save_state(struct perf_sched *sched)
{
	if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
		return;

	sched->saved[sched->saved_states] = sched->state;
	sched->saved_states++;
}

static bool perf_sched_restore_state(struct perf_sched *sched)
{
	if (!sched->saved_states)
		return false;

	sched->saved_states--;
	sched->state = sched->saved[sched->saved_states];

	/* continue with next counter: */
	clear_bit(sched->state.counter++, sched->state.used);

	return true;
}

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/*
 * Select a counter for the current event to schedule. Return true on
 * success.
 */
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static bool __perf_sched_find_counter(struct perf_sched *sched)
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{
	struct event_constraint *c;
	int idx;

	if (!sched->state.unassigned)
		return false;

	if (sched->state.event >= sched->max_events)
		return false;

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	c = sched->events[sched->state.event]->hw.constraint;
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	/* Prefer fixed purpose counters */
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	if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
		idx = INTEL_PMC_IDX_FIXED;
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		for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
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			if (!__test_and_set_bit(idx, sched->state.used))
				goto done;
		}
	}
648 649
	/* Grab the first unused counter starting with idx */
	idx = sched->state.counter;
650
	for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
651
		if (!__test_and_set_bit(idx, sched->state.used))
652
			goto done;
653 654
	}

655 656 657 658
	return false;

done:
	sched->state.counter = idx;
659

660 661 662 663 664 665 666 667 668 669 670 671 672
	if (c->overlap)
		perf_sched_save_state(sched);

	return true;
}

static bool perf_sched_find_counter(struct perf_sched *sched)
{
	while (!__perf_sched_find_counter(sched)) {
		if (!perf_sched_restore_state(sched))
			return false;
	}

673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696
	return true;
}

/*
 * Go through all unassigned events and find the next one to schedule.
 * Take events with the least weight first. Return true on success.
 */
static bool perf_sched_next_event(struct perf_sched *sched)
{
	struct event_constraint *c;

	if (!sched->state.unassigned || !--sched->state.unassigned)
		return false;

	do {
		/* next event */
		sched->state.event++;
		if (sched->state.event >= sched->max_events) {
			/* next weight */
			sched->state.event = 0;
			sched->state.weight++;
			if (sched->state.weight > sched->max_weight)
				return false;
		}
697
		c = sched->events[sched->state.event]->hw.constraint;
698 699 700 701 702 703 704 705 706 707
	} while (c->weight != sched->state.weight);

	sched->state.counter = 0;	/* start with first counter */

	return true;
}

/*
 * Assign a counter for each event.
 */
708
int perf_assign_events(struct perf_event **events, int n,
Y
Yan, Zheng 已提交
709
			int wmin, int wmax, int *assign)
710 711 712
{
	struct perf_sched sched;

713
	perf_sched_init(&sched, events, n, wmin, wmax);
714 715 716 717 718 719 720 721 722 723 724

	do {
		if (!perf_sched_find_counter(&sched))
			break;	/* failed */
		if (assign)
			assign[sched.state.event] = sched.state.counter;
	} while (perf_sched_next_event(&sched));

	return sched.state.unassigned;
}

725
int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
726
{
727
	struct event_constraint *c;
728
	unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
729
	struct perf_event *e;
730
	int i, wmin, wmax, num = 0;
731 732 733 734
	struct hw_perf_event *hwc;

	bitmap_zero(used_mask, X86_PMC_IDX_MAX);

735
	for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
736
		hwc = &cpuc->event_list[i]->hw;
737
		c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
738 739
		hwc->constraint = c;

740 741
		wmin = min(wmin, c->weight);
		wmax = max(wmax, c->weight);
742 743
	}

744 745 746
	/*
	 * fastpath, try to reuse previous register
	 */
747
	for (i = 0; i < n; i++) {
748
		hwc = &cpuc->event_list[i]->hw;
749
		c = hwc->constraint;
750 751 752 753 754 755

		/* never assigned */
		if (hwc->idx == -1)
			break;

		/* constraint still honored */
756
		if (!test_bit(hwc->idx, c->idxmsk))
757 758 759 760 761 762
			break;

		/* not already used */
		if (test_bit(hwc->idx, used_mask))
			break;

P
Peter Zijlstra 已提交
763
		__set_bit(hwc->idx, used_mask);
764 765 766 767
		if (assign)
			assign[i] = hwc->idx;
	}

768 769
	/* slow path */
	if (i != n)
770 771
		num = perf_assign_events(cpuc->event_list, n, wmin,
					 wmax, assign);
772

773 774 775 776 777 778 779 780 781 782
	/*
	 * Mark the event as committed, so we do not put_constraint()
	 * in case new events are added and fail scheduling.
	 */
	if (!num && assign) {
		for (i = 0; i < n; i++) {
			e = cpuc->event_list[i];
			e->hw.flags |= PERF_X86_EVENT_COMMITTED;
		}
	}
783 784 785 786 787 788
	/*
	 * scheduling failed or is just a simulation,
	 * free resources if necessary
	 */
	if (!assign || num) {
		for (i = 0; i < n; i++) {
789 790 791 792 793 794 795 796
			e = cpuc->event_list[i];
			/*
			 * do not put_constraint() on comitted events,
			 * because they are good to go
			 */
			if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
				continue;

797
			if (x86_pmu.put_event_constraints)
798
				x86_pmu.put_event_constraints(cpuc, e);
799 800
		}
	}
801
	return num ? -EINVAL : 0;
802 803 804 805 806 807 808 809 810 811 812
}

/*
 * dogrp: true if must collect siblings events (group)
 * returns total number of events and error code
 */
static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
{
	struct perf_event *event;
	int n, max_count;

813
	max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
814 815 816 817 818 819

	/* current number of events already accepted */
	n = cpuc->n_events;

	if (is_x86_event(leader)) {
		if (n >= max_count)
820
			return -EINVAL;
821 822 823 824 825 826 827 828
		cpuc->event_list[n] = leader;
		n++;
	}
	if (!dogrp)
		return n;

	list_for_each_entry(event, &leader->sibling_list, group_entry) {
		if (!is_x86_event(event) ||
829
		    event->state <= PERF_EVENT_STATE_OFF)
830 831 832
			continue;

		if (n >= max_count)
833
			return -EINVAL;
834 835 836 837 838 839 840 841

		cpuc->event_list[n] = event;
		n++;
	}
	return n;
}

static inline void x86_assign_hw_event(struct perf_event *event,
842
				struct cpu_hw_events *cpuc, int i)
843
{
844 845 846 847 848
	struct hw_perf_event *hwc = &event->hw;

	hwc->idx = cpuc->assign[i];
	hwc->last_cpu = smp_processor_id();
	hwc->last_tag = ++cpuc->tags[i];
849

850
	if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
851 852
		hwc->config_base = 0;
		hwc->event_base	= 0;
853
	} else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
854
		hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
855 856
		hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
		hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
857
	} else {
858 859
		hwc->config_base = x86_pmu_config_addr(hwc->idx);
		hwc->event_base  = x86_pmu_event_addr(hwc->idx);
860
		hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
861 862 863
	}
}

864 865 866 867 868 869 870 871 872
static inline int match_prev_assignment(struct hw_perf_event *hwc,
					struct cpu_hw_events *cpuc,
					int i)
{
	return hwc->idx == cpuc->assign[i] &&
		hwc->last_cpu == smp_processor_id() &&
		hwc->last_tag == cpuc->tags[i];
}

P
Peter Zijlstra 已提交
873
static void x86_pmu_start(struct perf_event *event, int flags);
874

P
Peter Zijlstra 已提交
875
static void x86_pmu_enable(struct pmu *pmu)
876
{
877 878 879
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	struct perf_event *event;
	struct hw_perf_event *hwc;
880
	int i, added = cpuc->n_added;
881

882
	if (!x86_pmu_initialized())
883
		return;
884 885 886 887

	if (cpuc->enabled)
		return;

888
	if (cpuc->n_added) {
889
		int n_running = cpuc->n_events - cpuc->n_added;
890 891 892 893 894 895 896
		/*
		 * apply assignment obtained either from
		 * hw_perf_group_sched_in() or x86_pmu_enable()
		 *
		 * step1: save events moving to new counters
		 * step2: reprogram moved events into new counters
		 */
897
		for (i = 0; i < n_running; i++) {
898 899 900
			event = cpuc->event_list[i];
			hwc = &event->hw;

901 902 903 904 905 906 907 908
			/*
			 * we can avoid reprogramming counter if:
			 * - assigned same counter as last time
			 * - running on same CPU as last time
			 * - no other event has used the counter since
			 */
			if (hwc->idx == -1 ||
			    match_prev_assignment(hwc, cpuc, i))
909 910
				continue;

P
Peter Zijlstra 已提交
911 912 913 914 915 916 917 918
			/*
			 * Ensure we don't accidentally enable a stopped
			 * counter simply because we rescheduled.
			 */
			if (hwc->state & PERF_HES_STOPPED)
				hwc->state |= PERF_HES_ARCH;

			x86_pmu_stop(event, PERF_EF_UPDATE);
919 920 921 922 923 924
		}

		for (i = 0; i < cpuc->n_events; i++) {
			event = cpuc->event_list[i];
			hwc = &event->hw;

925
			if (!match_prev_assignment(hwc, cpuc, i))
926
				x86_assign_hw_event(event, cpuc, i);
927 928
			else if (i < n_running)
				continue;
929

P
Peter Zijlstra 已提交
930 931 932 933
			if (hwc->state & PERF_HES_ARCH)
				continue;

			x86_pmu_start(event, PERF_EF_RELOAD);
934 935 936 937
		}
		cpuc->n_added = 0;
		perf_events_lapic_init();
	}
938 939 940 941

	cpuc->enabled = 1;
	barrier();

942
	x86_pmu.enable_all(added);
943 944
}

945
static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
I
Ingo Molnar 已提交
946

947 948
/*
 * Set the next IRQ period, based on the hwc->period_left value.
949
 * To be called with the event disabled in hw:
950
 */
951
int x86_perf_event_set_period(struct perf_event *event)
I
Ingo Molnar 已提交
952
{
953
	struct hw_perf_event *hwc = &event->hw;
954
	s64 left = local64_read(&hwc->period_left);
955
	s64 period = hwc->sample_period;
956
	int ret = 0, idx = hwc->idx;
957

958
	if (idx == INTEL_PMC_IDX_FIXED_BTS)
959 960
		return 0;

961
	/*
962
	 * If we are way outside a reasonable range then just skip forward:
963 964 965
	 */
	if (unlikely(left <= -period)) {
		left = period;
966
		local64_set(&hwc->period_left, left);
967
		hwc->last_period = period;
968
		ret = 1;
969 970 971 972
	}

	if (unlikely(left <= 0)) {
		left += period;
973
		local64_set(&hwc->period_left, left);
974
		hwc->last_period = period;
975
		ret = 1;
976
	}
977
	/*
978
	 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
979 980 981
	 */
	if (unlikely(left < 2))
		left = 2;
I
Ingo Molnar 已提交
982

983 984 985
	if (left > x86_pmu.max_period)
		left = x86_pmu.max_period;

986
	per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
987 988

	/*
989
	 * The hw event starts counting from this event offset,
990 991
	 * mark it to be able to extra future deltas:
	 */
992
	local64_set(&hwc->prev_count, (u64)-left);
993

994
	wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
995 996 997 998 999 1000 1001

	/*
	 * Due to erratum on certan cpu we need
	 * a second write to be sure the register
	 * is updated properly
	 */
	if (x86_pmu.perfctr_second_write) {
1002
		wrmsrl(hwc->event_base,
1003
			(u64)(-left) & x86_pmu.cntval_mask);
1004
	}
1005

1006
	perf_event_update_userpage(event);
1007

1008
	return ret;
1009 1010
}

1011
void x86_pmu_enable_event(struct perf_event *event)
1012
{
T
Tejun Heo 已提交
1013
	if (__this_cpu_read(cpu_hw_events.enabled))
1014 1015
		__x86_pmu_enable_event(&event->hw,
				       ARCH_PERFMON_EVENTSEL_ENABLE);
I
Ingo Molnar 已提交
1016 1017
}

1018
/*
P
Peter Zijlstra 已提交
1019
 * Add a single event to the PMU.
1020 1021 1022
 *
 * The event is added to the group of enabled events
 * but only if it can be scehduled with existing events.
1023
 */
P
Peter Zijlstra 已提交
1024
static int x86_pmu_add(struct perf_event *event, int flags)
1025 1026
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1027 1028 1029
	struct hw_perf_event *hwc;
	int assign[X86_PMC_IDX_MAX];
	int n, n0, ret;
1030

1031
	hwc = &event->hw;
1032

P
Peter Zijlstra 已提交
1033
	perf_pmu_disable(event->pmu);
1034
	n0 = cpuc->n_events;
1035 1036 1037
	ret = n = collect_events(cpuc, event, false);
	if (ret < 0)
		goto out;
1038

P
Peter Zijlstra 已提交
1039 1040 1041 1042
	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
	if (!(flags & PERF_EF_START))
		hwc->state |= PERF_HES_ARCH;

1043 1044
	/*
	 * If group events scheduling transaction was started,
L
Lucas De Marchi 已提交
1045
	 * skip the schedulability test here, it will be performed
P
Peter Zijlstra 已提交
1046
	 * at commit time (->commit_txn) as a whole
1047
	 */
1048
	if (cpuc->group_flag & PERF_EVENT_TXN)
1049
		goto done_collect;
1050

1051
	ret = x86_pmu.schedule_events(cpuc, n, assign);
1052
	if (ret)
1053
		goto out;
1054 1055 1056 1057 1058
	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));
1059

1060
done_collect:
1061
	cpuc->n_events = n;
1062
	cpuc->n_added += n - n0;
1063
	cpuc->n_txn += n - n0;
1064

1065 1066
	ret = 0;
out:
P
Peter Zijlstra 已提交
1067
	perf_pmu_enable(event->pmu);
1068
	return ret;
I
Ingo Molnar 已提交
1069 1070
}

P
Peter Zijlstra 已提交
1071
static void x86_pmu_start(struct perf_event *event, int flags)
1072
{
P
Peter Zijlstra 已提交
1073 1074 1075
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int idx = event->hw.idx;

P
Peter Zijlstra 已提交
1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087
	if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
		return;

	if (WARN_ON_ONCE(idx == -1))
		return;

	if (flags & PERF_EF_RELOAD) {
		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
		x86_perf_event_set_period(event);
	}

	event->hw.state = 0;
1088

P
Peter Zijlstra 已提交
1089 1090
	cpuc->events[idx] = event;
	__set_bit(idx, cpuc->active_mask);
1091
	__set_bit(idx, cpuc->running);
1092
	x86_pmu.enable(event);
P
Peter Zijlstra 已提交
1093
	perf_event_update_userpage(event);
1094 1095
}

1096
void perf_event_print_debug(void)
I
Ingo Molnar 已提交
1097
{
1098
	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1099
	u64 pebs;
1100
	struct cpu_hw_events *cpuc;
1101
	unsigned long flags;
1102 1103
	int cpu, idx;

1104
	if (!x86_pmu.num_counters)
1105
		return;
I
Ingo Molnar 已提交
1106

1107
	local_irq_save(flags);
I
Ingo Molnar 已提交
1108 1109

	cpu = smp_processor_id();
1110
	cpuc = &per_cpu(cpu_hw_events, cpu);
I
Ingo Molnar 已提交
1111

1112
	if (x86_pmu.version >= 2) {
1113 1114 1115 1116
		rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
		rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
		rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1117
		rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1118 1119 1120 1121 1122 1123

		pr_info("\n");
		pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
		pr_info("CPU#%d: status:     %016llx\n", cpu, status);
		pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
		pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1124
		pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1125
	}
1126
	pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
I
Ingo Molnar 已提交
1127

1128
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1129 1130
		rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
		rdmsrl(x86_pmu_event_addr(idx), pmc_count);
I
Ingo Molnar 已提交
1131

1132
		prev_left = per_cpu(pmc_prev_left[idx], cpu);
I
Ingo Molnar 已提交
1133

1134
		pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
I
Ingo Molnar 已提交
1135
			cpu, idx, pmc_ctrl);
1136
		pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
I
Ingo Molnar 已提交
1137
			cpu, idx, pmc_count);
1138
		pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1139
			cpu, idx, prev_left);
I
Ingo Molnar 已提交
1140
	}
1141
	for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1142 1143
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);

1144
		pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1145 1146
			cpu, idx, pmc_count);
	}
1147
	local_irq_restore(flags);
I
Ingo Molnar 已提交
1148 1149
}

1150
void x86_pmu_stop(struct perf_event *event, int flags)
I
Ingo Molnar 已提交
1151
{
1152
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1153
	struct hw_perf_event *hwc = &event->hw;
I
Ingo Molnar 已提交
1154

P
Peter Zijlstra 已提交
1155 1156 1157 1158 1159 1160
	if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
		x86_pmu.disable(event);
		cpuc->events[hwc->idx] = NULL;
		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
		hwc->state |= PERF_HES_STOPPED;
	}
1161

P
Peter Zijlstra 已提交
1162 1163 1164 1165 1166 1167 1168 1169
	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
		/*
		 * Drain the remaining delta count out of a event
		 * that we are disabling:
		 */
		x86_perf_event_update(event);
		hwc->state |= PERF_HES_UPTODATE;
	}
1170 1171
}

P
Peter Zijlstra 已提交
1172
static void x86_pmu_del(struct perf_event *event, int flags)
1173 1174 1175 1176
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int i;

1177 1178 1179 1180 1181
	/*
	 * event is descheduled
	 */
	event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;

1182 1183 1184 1185 1186
	/*
	 * If we're called during a txn, we don't need to do anything.
	 * The events never got scheduled and ->cancel_txn will truncate
	 * the event_list.
	 */
1187
	if (cpuc->group_flag & PERF_EVENT_TXN)
1188 1189
		return;

P
Peter Zijlstra 已提交
1190
	x86_pmu_stop(event, PERF_EF_UPDATE);
1191

1192 1193 1194 1195 1196 1197 1198 1199 1200 1201
	for (i = 0; i < cpuc->n_events; i++) {
		if (event == cpuc->event_list[i]) {

			if (x86_pmu.put_event_constraints)
				x86_pmu.put_event_constraints(cpuc, event);

			while (++i < cpuc->n_events)
				cpuc->event_list[i-1] = cpuc->event_list[i];

			--cpuc->n_events;
1202
			break;
1203 1204
		}
	}
1205
	perf_event_update_userpage(event);
I
Ingo Molnar 已提交
1206 1207
}

1208
int x86_pmu_handle_irq(struct pt_regs *regs)
1209
{
1210
	struct perf_sample_data data;
1211 1212
	struct cpu_hw_events *cpuc;
	struct perf_event *event;
V
Vince Weaver 已提交
1213
	int idx, handled = 0;
1214 1215
	u64 val;

1216
	cpuc = &__get_cpu_var(cpu_hw_events);
1217

1218 1219 1220 1221 1222 1223 1224 1225 1226 1227
	/*
	 * Some chipsets need to unmask the LVTPC in a particular spot
	 * inside the nmi handler.  As a result, the unmasking was pushed
	 * into all the nmi handlers.
	 *
	 * This generic handler doesn't seem to have any issues where the
	 * unmasking occurs so it was left at the top.
	 */
	apic_write(APIC_LVTPC, APIC_DM_NMI);

1228
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1229 1230 1231 1232 1233 1234 1235 1236
		if (!test_bit(idx, cpuc->active_mask)) {
			/*
			 * Though we deactivated the counter some cpus
			 * might still deliver spurious interrupts still
			 * in flight. Catch them:
			 */
			if (__test_and_clear_bit(idx, cpuc->running))
				handled++;
1237
			continue;
1238
		}
1239

1240
		event = cpuc->events[idx];
1241

1242
		val = x86_perf_event_update(event);
1243
		if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1244
			continue;
1245

1246
		/*
1247
		 * event overflow
1248
		 */
1249
		handled++;
1250
		perf_sample_data_init(&data, 0, event->hw.last_period);
1251

1252
		if (!x86_perf_event_set_period(event))
1253 1254
			continue;

1255
		if (perf_event_overflow(event, &data, regs))
P
Peter Zijlstra 已提交
1256
			x86_pmu_stop(event, 0);
1257
	}
1258

1259 1260 1261
	if (handled)
		inc_irq_stat(apic_perf_irqs);

1262 1263
	return handled;
}
1264

1265
void perf_events_lapic_init(void)
I
Ingo Molnar 已提交
1266
{
1267
	if (!x86_pmu.apic || !x86_pmu_initialized())
I
Ingo Molnar 已提交
1268
		return;
1269

I
Ingo Molnar 已提交
1270
	/*
1271
	 * Always use NMI for PMU
I
Ingo Molnar 已提交
1272
	 */
1273
	apic_write(APIC_LVTPC, APIC_DM_NMI);
I
Ingo Molnar 已提交
1274 1275 1276
}

static int __kprobes
1277
perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
I
Ingo Molnar 已提交
1278
{
1279 1280
	u64 start_clock;
	u64 finish_clock;
P
Peter Zijlstra 已提交
1281
	int ret;
1282

1283
	if (!atomic_read(&active_events))
1284
		return NMI_DONE;
1285

P
Peter Zijlstra 已提交
1286
	start_clock = sched_clock();
1287
	ret = x86_pmu.handle_irq(regs);
P
Peter Zijlstra 已提交
1288
	finish_clock = sched_clock();
1289 1290 1291 1292

	perf_sample_event_took(finish_clock - start_clock);

	return ret;
I
Ingo Molnar 已提交
1293 1294
}

1295 1296
struct event_constraint emptyconstraint;
struct event_constraint unconstrained;
1297

1298
static int
1299 1300 1301
x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
{
	unsigned int cpu = (long)hcpu;
1302
	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1303
	int ret = NOTIFY_OK;
1304 1305 1306

	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_UP_PREPARE:
1307
		cpuc->kfree_on_online = NULL;
1308
		if (x86_pmu.cpu_prepare)
1309
			ret = x86_pmu.cpu_prepare(cpu);
1310 1311 1312
		break;

	case CPU_STARTING:
1313 1314
		if (x86_pmu.attr_rdpmc)
			set_in_cr4(X86_CR4_PCE);
1315 1316 1317 1318
		if (x86_pmu.cpu_starting)
			x86_pmu.cpu_starting(cpu);
		break;

1319 1320 1321 1322
	case CPU_ONLINE:
		kfree(cpuc->kfree_on_online);
		break;

1323 1324 1325 1326 1327
	case CPU_DYING:
		if (x86_pmu.cpu_dying)
			x86_pmu.cpu_dying(cpu);
		break;

1328
	case CPU_UP_CANCELED:
1329 1330 1331 1332 1333 1334 1335 1336 1337
	case CPU_DEAD:
		if (x86_pmu.cpu_dead)
			x86_pmu.cpu_dead(cpu);
		break;

	default:
		break;
	}

1338
	return ret;
1339 1340
}

1341 1342 1343 1344 1345 1346 1347 1348 1349 1350
static void __init pmu_check_apic(void)
{
	if (cpu_has_apic)
		return;

	x86_pmu.apic = 0;
	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
	pr_info("no hardware sampling interrupt available.\n");
}

1351 1352 1353 1354 1355
static struct attribute_group x86_pmu_format_group = {
	.name = "format",
	.attrs = NULL,
};

1356 1357 1358 1359 1360 1361
/*
 * Remove all undefined events (x86_pmu.event_map(id) == 0)
 * out of events_attr attributes.
 */
static void __init filter_events(struct attribute **attrs)
{
1362 1363
	struct device_attribute *d;
	struct perf_pmu_events_attr *pmu_attr;
1364 1365 1366
	int i, j;

	for (i = 0; attrs[i]; i++) {
1367 1368 1369 1370 1371
		d = (struct device_attribute *)attrs[i];
		pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
		/* str trumps id */
		if (pmu_attr->event_str)
			continue;
1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382
		if (x86_pmu.event_map(i))
			continue;

		for (j = i; attrs[j]; j++)
			attrs[j] = attrs[j + 1];

		/* Check the shifted attr. */
		i--;
	}
}

1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408
/* Merge two pointer arrays */
static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
{
	struct attribute **new;
	int j, i;

	for (j = 0; a[j]; j++)
		;
	for (i = 0; b[i]; i++)
		j++;
	j++;

	new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
	if (!new)
		return NULL;

	j = 0;
	for (i = 0; a[i]; i++)
		new[j++] = a[i];
	for (i = 0; b[i]; i++)
		new[j++] = b[i];
	new[j] = NULL;

	return new;
}

1409
ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1410 1411 1412 1413 1414 1415
			  char *page)
{
	struct perf_pmu_events_attr *pmu_attr = \
		container_of(attr, struct perf_pmu_events_attr, attr);
	u64 config = x86_pmu.event_map(pmu_attr->id);

1416 1417 1418
	/* string trumps id */
	if (pmu_attr->event_str)
		return sprintf(page, "%s", pmu_attr->event_str);
1419

1420 1421
	return x86_pmu.events_sysfs_show(page, config);
}
1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435

EVENT_ATTR(cpu-cycles,			CPU_CYCLES		);
EVENT_ATTR(instructions,		INSTRUCTIONS		);
EVENT_ATTR(cache-references,		CACHE_REFERENCES	);
EVENT_ATTR(cache-misses, 		CACHE_MISSES		);
EVENT_ATTR(branch-instructions,		BRANCH_INSTRUCTIONS	);
EVENT_ATTR(branch-misses,		BRANCH_MISSES		);
EVENT_ATTR(bus-cycles,			BUS_CYCLES		);
EVENT_ATTR(stalled-cycles-frontend,	STALLED_CYCLES_FRONTEND	);
EVENT_ATTR(stalled-cycles-backend,	STALLED_CYCLES_BACKEND	);
EVENT_ATTR(ref-cycles,			REF_CPU_CYCLES		);

static struct attribute *empty_attrs;

P
Peter Huewe 已提交
1436
static struct attribute *events_attr[] = {
1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454
	EVENT_PTR(CPU_CYCLES),
	EVENT_PTR(INSTRUCTIONS),
	EVENT_PTR(CACHE_REFERENCES),
	EVENT_PTR(CACHE_MISSES),
	EVENT_PTR(BRANCH_INSTRUCTIONS),
	EVENT_PTR(BRANCH_MISSES),
	EVENT_PTR(BUS_CYCLES),
	EVENT_PTR(STALLED_CYCLES_FRONTEND),
	EVENT_PTR(STALLED_CYCLES_BACKEND),
	EVENT_PTR(REF_CPU_CYCLES),
	NULL,
};

static struct attribute_group x86_pmu_events_group = {
	.name = "events",
	.attrs = events_attr,
};

1455
ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493
{
	u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
	u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
	bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
	bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
	bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
	bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
	ssize_t ret;

	/*
	* We have whole page size to spend and just little data
	* to write, so we can safely use sprintf.
	*/
	ret = sprintf(page, "event=0x%02llx", event);

	if (umask)
		ret += sprintf(page + ret, ",umask=0x%02llx", umask);

	if (edge)
		ret += sprintf(page + ret, ",edge");

	if (pc)
		ret += sprintf(page + ret, ",pc");

	if (any)
		ret += sprintf(page + ret, ",any");

	if (inv)
		ret += sprintf(page + ret, ",inv");

	if (cmask)
		ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);

	ret += sprintf(page + ret, "\n");

	return ret;
}

1494
static int __init init_hw_perf_events(void)
1495
{
1496
	struct x86_pmu_quirk *quirk;
1497 1498
	int err;

1499
	pr_info("Performance Events: ");
1500

1501 1502
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_INTEL:
1503
		err = intel_pmu_init();
1504
		break;
1505
	case X86_VENDOR_AMD:
1506
		err = amd_pmu_init();
1507
		break;
1508
	default:
1509
		err = -ENOTSUPP;
1510
	}
1511
	if (err != 0) {
1512
		pr_cont("no PMU driver, software events only.\n");
1513
		return 0;
1514
	}
1515

1516 1517
	pmu_check_apic();

1518
	/* sanity check that the hardware exists or is emulated */
1519
	if (!check_hw_exists())
1520
		return 0;
1521

1522
	pr_cont("%s PMU driver.\n", x86_pmu.name);
1523

1524 1525
	x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */

1526 1527
	for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
		quirk->func();
1528

1529 1530
	if (!x86_pmu.intel_ctrl)
		x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
I
Ingo Molnar 已提交
1531

1532
	perf_events_lapic_init();
1533
	register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1534

1535
	unconstrained = (struct event_constraint)
1536
		__EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1537
				   0, x86_pmu.num_counters, 0, 0);
1538

1539
	x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1540

1541 1542 1543
	if (x86_pmu.event_attrs)
		x86_pmu_events_group.attrs = x86_pmu.event_attrs;

1544 1545
	if (!x86_pmu.events_sysfs_show)
		x86_pmu_events_group.attrs = &empty_attrs;
1546 1547
	else
		filter_events(x86_pmu_events_group.attrs);
1548

1549 1550 1551 1552 1553 1554 1555 1556
	if (x86_pmu.cpu_events) {
		struct attribute **tmp;

		tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
		if (!WARN_ON(!tmp))
			x86_pmu_events_group.attrs = tmp;
	}

I
Ingo Molnar 已提交
1557
	pr_info("... version:                %d\n",     x86_pmu.version);
1558 1559 1560
	pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
	pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
	pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
I
Ingo Molnar 已提交
1561
	pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1562
	pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1563
	pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1564

P
Peter Zijlstra 已提交
1565
	perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1566
	perf_cpu_notifier(x86_pmu_notifier);
1567 1568

	return 0;
I
Ingo Molnar 已提交
1569
}
1570
early_initcall(init_hw_perf_events);
I
Ingo Molnar 已提交
1571

1572
static inline void x86_pmu_read(struct perf_event *event)
1573
{
1574
	x86_perf_event_update(event);
1575 1576
}

1577 1578 1579 1580 1581
/*
 * Start group events scheduling transaction
 * Set the flag to make pmu::enable() not perform the
 * schedulability test, it will be performed at commit time
 */
P
Peter Zijlstra 已提交
1582
static void x86_pmu_start_txn(struct pmu *pmu)
1583
{
P
Peter Zijlstra 已提交
1584
	perf_pmu_disable(pmu);
T
Tejun Heo 已提交
1585 1586
	__this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
	__this_cpu_write(cpu_hw_events.n_txn, 0);
1587 1588 1589 1590 1591 1592 1593
}

/*
 * Stop group events scheduling transaction
 * Clear the flag and pmu::enable() will perform the
 * schedulability test.
 */
P
Peter Zijlstra 已提交
1594
static void x86_pmu_cancel_txn(struct pmu *pmu)
1595
{
T
Tejun Heo 已提交
1596
	__this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1597 1598 1599
	/*
	 * Truncate the collected events.
	 */
T
Tejun Heo 已提交
1600 1601
	__this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
	__this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
P
Peter Zijlstra 已提交
1602
	perf_pmu_enable(pmu);
1603 1604 1605 1606 1607 1608 1609
}

/*
 * Commit group events scheduling transaction
 * Perform the group schedulability test as a whole
 * Return 0 if success
 */
P
Peter Zijlstra 已提交
1610
static int x86_pmu_commit_txn(struct pmu *pmu)
1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int assign[X86_PMC_IDX_MAX];
	int n, ret;

	n = cpuc->n_events;

	if (!x86_pmu_initialized())
		return -EAGAIN;

	ret = x86_pmu.schedule_events(cpuc, n, assign);
	if (ret)
		return ret;

	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));

1631
	cpuc->group_flag &= ~PERF_EVENT_TXN;
P
Peter Zijlstra 已提交
1632
	perf_pmu_enable(pmu);
1633 1634
	return 0;
}
1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663
/*
 * a fake_cpuc is used to validate event groups. Due to
 * the extra reg logic, we need to also allocate a fake
 * per_core and per_cpu structure. Otherwise, group events
 * using extra reg may conflict without the kernel being
 * able to catch this when the last event gets added to
 * the group.
 */
static void free_fake_cpuc(struct cpu_hw_events *cpuc)
{
	kfree(cpuc->shared_regs);
	kfree(cpuc);
}

static struct cpu_hw_events *allocate_fake_cpuc(void)
{
	struct cpu_hw_events *cpuc;
	int cpu = raw_smp_processor_id();

	cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
	if (!cpuc)
		return ERR_PTR(-ENOMEM);

	/* only needed, if we have extra_regs */
	if (x86_pmu.extra_regs) {
		cpuc->shared_regs = allocate_shared_regs(cpu);
		if (!cpuc->shared_regs)
			goto error;
	}
1664
	cpuc->is_fake = 1;
1665 1666 1667 1668 1669
	return cpuc;
error:
	free_fake_cpuc(cpuc);
	return ERR_PTR(-ENOMEM);
}
1670

1671 1672 1673 1674 1675 1676 1677 1678 1679
/*
 * validate that we can schedule this event
 */
static int validate_event(struct perf_event *event)
{
	struct cpu_hw_events *fake_cpuc;
	struct event_constraint *c;
	int ret = 0;

1680 1681 1682
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1683 1684 1685 1686

	c = x86_pmu.get_event_constraints(fake_cpuc, event);

	if (!c || !c->weight)
1687
		ret = -EINVAL;
1688 1689 1690 1691

	if (x86_pmu.put_event_constraints)
		x86_pmu.put_event_constraints(fake_cpuc, event);

1692
	free_fake_cpuc(fake_cpuc);
1693 1694 1695 1696

	return ret;
}

1697 1698 1699 1700
/*
 * validate a single event group
 *
 * validation include:
1701 1702 1703
 *	- check events are compatible which each other
 *	- events do not compete for the same counter
 *	- number of events <= number of counters
1704 1705 1706 1707
 *
 * validation ensures the group can be loaded onto the
 * PMU if it was the only group available.
 */
1708 1709
static int validate_group(struct perf_event *event)
{
1710
	struct perf_event *leader = event->group_leader;
1711
	struct cpu_hw_events *fake_cpuc;
1712
	int ret = -EINVAL, n;
1713

1714 1715 1716
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1717 1718 1719 1720 1721 1722
	/*
	 * the event is not yet connected with its
	 * siblings therefore we must first collect
	 * existing siblings, then add the new event
	 * before we can simulate the scheduling
	 */
1723
	n = collect_events(fake_cpuc, leader, true);
1724
	if (n < 0)
1725
		goto out;
1726

1727 1728
	fake_cpuc->n_events = n;
	n = collect_events(fake_cpuc, event, false);
1729
	if (n < 0)
1730
		goto out;
1731

1732
	fake_cpuc->n_events = n;
1733

1734
	ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1735 1736

out:
1737
	free_fake_cpuc(fake_cpuc);
1738
	return ret;
1739 1740
}

1741
static int x86_pmu_event_init(struct perf_event *event)
I
Ingo Molnar 已提交
1742
{
P
Peter Zijlstra 已提交
1743
	struct pmu *tmp;
I
Ingo Molnar 已提交
1744 1745
	int err;

1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756
	switch (event->attr.type) {
	case PERF_TYPE_RAW:
	case PERF_TYPE_HARDWARE:
	case PERF_TYPE_HW_CACHE:
		break;

	default:
		return -ENOENT;
	}

	err = __x86_pmu_event_init(event);
1757
	if (!err) {
1758 1759 1760 1761 1762 1763 1764 1765
		/*
		 * we temporarily connect event to its pmu
		 * such that validate_group() can classify
		 * it as an x86 event using is_x86_event()
		 */
		tmp = event->pmu;
		event->pmu = &pmu;

1766 1767
		if (event->group_leader != event)
			err = validate_group(event);
1768 1769
		else
			err = validate_event(event);
1770 1771

		event->pmu = tmp;
1772
	}
1773
	if (err) {
1774 1775
		if (event->destroy)
			event->destroy(event);
1776
	}
I
Ingo Molnar 已提交
1777

1778
	return err;
I
Ingo Molnar 已提交
1779
}
1780

1781 1782 1783 1784
static int x86_pmu_event_idx(struct perf_event *event)
{
	int idx = event->hw.idx;

1785 1786 1787
	if (!x86_pmu.attr_rdpmc)
		return 0;

1788 1789
	if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
		idx -= INTEL_PMC_IDX_FIXED;
1790 1791 1792 1793 1794 1795
		idx |= 1 << 30;
	}

	return idx + 1;
}

1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816
static ssize_t get_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      char *buf)
{
	return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
}

static void change_rdpmc(void *info)
{
	bool enable = !!(unsigned long)info;

	if (enable)
		set_in_cr4(X86_CR4_PCE);
	else
		clear_in_cr4(X86_CR4_PCE);
}

static ssize_t set_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      const char *buf, size_t count)
{
1817 1818 1819 1820 1821 1822
	unsigned long val;
	ssize_t ret;

	ret = kstrtoul(buf, 0, &val);
	if (ret)
		return ret;
1823 1824 1825

	if (x86_pmu.attr_rdpmc_broken)
		return -ENOTSUPP;
1826 1827 1828

	if (!!val != !!x86_pmu.attr_rdpmc) {
		x86_pmu.attr_rdpmc = !!val;
1829
		on_each_cpu(change_rdpmc, (void *)val, 1);
1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847
	}

	return count;
}

static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);

static struct attribute *x86_pmu_attrs[] = {
	&dev_attr_rdpmc.attr,
	NULL,
};

static struct attribute_group x86_pmu_attr_group = {
	.attrs = x86_pmu_attrs,
};

static const struct attribute_group *x86_pmu_attr_groups[] = {
	&x86_pmu_attr_group,
1848
	&x86_pmu_format_group,
1849
	&x86_pmu_events_group,
1850 1851 1852
	NULL,
};

1853 1854 1855 1856 1857 1858
static void x86_pmu_flush_branch_stack(void)
{
	if (x86_pmu.flush_branch_stack)
		x86_pmu.flush_branch_stack();
}

1859 1860 1861 1862 1863 1864 1865
void perf_check_microcode(void)
{
	if (x86_pmu.check_microcode)
		x86_pmu.check_microcode();
}
EXPORT_SYMBOL_GPL(perf_check_microcode);

1866
static struct pmu pmu = {
1867 1868
	.pmu_enable		= x86_pmu_enable,
	.pmu_disable		= x86_pmu_disable,
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Peter Zijlstra 已提交
1869

1870
	.attr_groups		= x86_pmu_attr_groups,
1871

1872
	.event_init		= x86_pmu_event_init,
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Peter Zijlstra 已提交
1873

1874 1875 1876 1877 1878
	.add			= x86_pmu_add,
	.del			= x86_pmu_del,
	.start			= x86_pmu_start,
	.stop			= x86_pmu_stop,
	.read			= x86_pmu_read,
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Peter Zijlstra 已提交
1879

1880 1881 1882
	.start_txn		= x86_pmu_start_txn,
	.cancel_txn		= x86_pmu_cancel_txn,
	.commit_txn		= x86_pmu_commit_txn,
1883

1884
	.event_idx		= x86_pmu_event_idx,
1885
	.flush_branch_stack	= x86_pmu_flush_branch_stack,
1886 1887
};

1888
void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1889
{
1890 1891
	struct cyc2ns_data *data;

1892 1893 1894
	userpg->cap_user_time = 0;
	userpg->cap_user_time_zero = 0;
	userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc;
1895 1896
	userpg->pmc_width = x86_pmu.cntval_bits;

1897
	if (!sched_clock_stable())
1898 1899
		return;

1900 1901
	data = cyc2ns_read_begin();

1902
	userpg->cap_user_time = 1;
1903 1904 1905
	userpg->time_mult = data->cyc2ns_mul;
	userpg->time_shift = data->cyc2ns_shift;
	userpg->time_offset = data->cyc2ns_offset - now;
1906

1907
	userpg->cap_user_time_zero = 1;
1908 1909 1910
	userpg->time_zero = data->cyc2ns_offset;

	cyc2ns_read_end(data);
1911 1912
}

1913 1914 1915 1916 1917 1918
/*
 * callchain support
 */

static int backtrace_stack(void *data, char *name)
{
1919
	return 0;
1920 1921 1922 1923 1924 1925
}

static void backtrace_address(void *data, unsigned long addr, int reliable)
{
	struct perf_callchain_entry *entry = data;

1926
	perf_callchain_store(entry, addr);
1927 1928 1929 1930 1931
}

static const struct stacktrace_ops backtrace_ops = {
	.stack			= backtrace_stack,
	.address		= backtrace_address,
1932
	.walk_stack		= print_context_stack_bp,
1933 1934
};

1935 1936
void
perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1937
{
1938 1939
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
1940
		return;
1941 1942
	}

1943
	perf_callchain_store(entry, regs->ip);
1944

1945
	dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1946 1947
}

1948 1949 1950 1951 1952 1953
static inline int
valid_user_frame(const void __user *fp, unsigned long size)
{
	return (__range_not_ok(fp, size, TASK_SIZE) == 0);
}

1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976
static unsigned long get_segment_base(unsigned int segment)
{
	struct desc_struct *desc;
	int idx = segment >> 3;

	if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
		if (idx > LDT_ENTRIES)
			return 0;

		if (idx > current->active_mm->context.size)
			return 0;

		desc = current->active_mm->context.ldt;
	} else {
		if (idx > GDT_ENTRIES)
			return 0;

		desc = __this_cpu_ptr(&gdt_page.gdt[0]);
	}

	return get_desc_base(desc + idx);
}

1977
#ifdef CONFIG_COMPAT
H
H. Peter Anvin 已提交
1978 1979 1980

#include <asm/compat.h>

1981 1982
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1983
{
1984
	/* 32-bit process in 64-bit kernel. */
1985
	unsigned long ss_base, cs_base;
1986 1987
	struct stack_frame_ia32 frame;
	const void __user *fp;
1988

1989 1990 1991
	if (!test_thread_flag(TIF_IA32))
		return 0;

1992 1993 1994 1995
	cs_base = get_segment_base(regs->cs);
	ss_base = get_segment_base(regs->ss);

	fp = compat_ptr(ss_base + regs->bp);
1996 1997 1998 1999 2000 2001
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
		unsigned long bytes;
		frame.next_frame     = 0;
		frame.return_address = 0;

		bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2002
		if (bytes != 0)
2003
			break;
2004

2005 2006 2007
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

2008 2009
		perf_callchain_store(entry, cs_base + frame.return_address);
		fp = compat_ptr(ss_base + frame.next_frame);
2010 2011
	}
	return 1;
2012
}
2013 2014 2015 2016 2017 2018 2019
#else
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
{
    return 0;
}
#endif
2020

2021 2022
void
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2023 2024 2025 2026
{
	struct stack_frame frame;
	const void __user *fp;

2027 2028
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
2029
		return;
2030
	}
2031

2032 2033 2034 2035 2036 2037
	/*
	 * We don't know what to do with VM86 stacks.. ignore them for now.
	 */
	if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
		return;

2038
	fp = (void __user *)regs->bp;
2039

2040
	perf_callchain_store(entry, regs->ip);
2041

2042 2043 2044
	if (!current->mm)
		return;

2045 2046 2047
	if (perf_callchain_user32(regs, entry))
		return;

2048
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
2049
		unsigned long bytes;
2050
		frame.next_frame	     = NULL;
2051 2052
		frame.return_address = 0;

2053
		bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2054
		if (bytes != 0)
2055 2056
			break;

2057 2058 2059
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

2060
		perf_callchain_store(entry, frame.return_address);
2061
		fp = frame.next_frame;
2062 2063 2064
	}
}

2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078
/*
 * Deal with code segment offsets for the various execution modes:
 *
 *   VM86 - the good olde 16 bit days, where the linear address is
 *          20 bits and we use regs->ip + 0x10 * regs->cs.
 *
 *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
 *          to figure out what the 32bit base address is.
 *
 *    X32 - has TIF_X32 set, but is running in x86_64
 *
 * X86_64 - CS,DS,SS,ES are all zero based.
 */
static unsigned long code_segment_base(struct pt_regs *regs)
2079
{
2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101
	/*
	 * If we are in VM86 mode, add the segment offset to convert to a
	 * linear address.
	 */
	if (regs->flags & X86_VM_MASK)
		return 0x10 * regs->cs;

	/*
	 * For IA32 we look at the GDT/LDT segment base to convert the
	 * effective IP to a linear address.
	 */
#ifdef CONFIG_X86_32
	if (user_mode(regs) && regs->cs != __USER_CS)
		return get_segment_base(regs->cs);
#else
	if (test_thread_flag(TIF_IA32)) {
		if (user_mode(regs) && regs->cs != __USER32_CS)
			return get_segment_base(regs->cs);
	}
#endif
	return 0;
}
2102

2103 2104
unsigned long perf_instruction_pointer(struct pt_regs *regs)
{
2105
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2106
		return perf_guest_cbs->get_guest_ip();
2107

2108
	return regs->ip + code_segment_base(regs);
2109 2110 2111 2112 2113
}

unsigned long perf_misc_flags(struct pt_regs *regs)
{
	int misc = 0;
2114

2115
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2116 2117 2118 2119 2120
		if (perf_guest_cbs->is_user_mode())
			misc |= PERF_RECORD_MISC_GUEST_USER;
		else
			misc |= PERF_RECORD_MISC_GUEST_KERNEL;
	} else {
2121
		if (user_mode(regs))
2122 2123 2124 2125 2126
			misc |= PERF_RECORD_MISC_USER;
		else
			misc |= PERF_RECORD_MISC_KERNEL;
	}

2127
	if (regs->flags & PERF_EFLAGS_EXACT)
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Peter Zijlstra 已提交
2128
		misc |= PERF_RECORD_MISC_EXACT_IP;
2129 2130 2131

	return misc;
}
2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143

void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
{
	cap->version		= x86_pmu.version;
	cap->num_counters_gp	= x86_pmu.num_counters;
	cap->num_counters_fixed	= x86_pmu.num_counters_fixed;
	cap->bit_width_gp	= x86_pmu.cntval_bits;
	cap->bit_width_fixed	= x86_pmu.cntval_bits;
	cap->events_mask	= (unsigned int)x86_pmu.events_maskl;
	cap->events_mask_len	= x86_pmu.events_mask_len;
}
EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);