perf_event.c 42.9 KB
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/*
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 * Performance events x86 architecture code
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 *
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 *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
 *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
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 *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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 *  Copyright (C) 2009 Google, Inc., Stephane Eranian
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 *
 *  For licencing details see kernel-base/COPYING
 */

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#include <linux/perf_event.h>
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#include <linux/capability.h>
#include <linux/notifier.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
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#include <linux/module.h>
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#include <linux/kdebug.h>
#include <linux/sched.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/highmem.h>
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#include <linux/cpu.h>
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#include <linux/bitops.h>
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#include <asm/apic.h>
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#include <asm/stacktrace.h>
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#include <asm/nmi.h>
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#include <asm/compat.h>
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#include <asm/smp.h>
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#include <asm/alternative.h>
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#if 0
#undef wrmsrl
#define wrmsrl(msr, val) 					\
do {								\
	trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
			(unsigned long)(val));			\
	native_write_msr((msr), (u32)((u64)(val)), 		\
			(u32)((u64)(val) >> 32));		\
} while (0)
#endif

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/*
 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
 */
static unsigned long
copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
{
	unsigned long offset, addr = (unsigned long)from;
	unsigned long size, len = 0;
	struct page *page;
	void *map;
	int ret;

	do {
		ret = __get_user_pages_fast(addr, 1, 0, &page);
		if (!ret)
			break;

		offset = addr & (PAGE_SIZE - 1);
		size = min(PAGE_SIZE - offset, n - len);

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		map = kmap_atomic(page);
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		memcpy(to, map+offset, size);
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		kunmap_atomic(map);
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		put_page(page);

		len  += size;
		to   += size;
		addr += size;

	} while (len < n);

	return len;
}

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struct event_constraint {
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	union {
		unsigned long	idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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		u64		idxmsk64;
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	};
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	u64	code;
	u64	cmask;
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	int	weight;
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};

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struct amd_nb {
	int nb_id;  /* NorthBridge id */
	int refcnt; /* reference count */
	struct perf_event *owners[X86_PMC_IDX_MAX];
	struct event_constraint event_constraints[X86_PMC_IDX_MAX];
};

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struct intel_percore;

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#define MAX_LBR_ENTRIES		16

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struct cpu_hw_events {
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	/*
	 * Generic x86 PMC bits
	 */
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	struct perf_event	*events[X86_PMC_IDX_MAX]; /* in counter order */
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	unsigned long		active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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	unsigned long		running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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	int			enabled;
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	int			n_events;
	int			n_added;
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	int			n_txn;
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	int			assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
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	u64			tags[X86_PMC_IDX_MAX];
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	struct perf_event	*event_list[X86_PMC_IDX_MAX]; /* in enabled order */
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	unsigned int		group_flag;

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	/*
	 * Intel DebugStore bits
	 */
	struct debug_store	*ds;
	u64			pebs_enabled;

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	/*
	 * Intel LBR bits
	 */
	int				lbr_users;
	void				*lbr_context;
	struct perf_branch_stack	lbr_stack;
	struct perf_branch_entry	lbr_entries[MAX_LBR_ENTRIES];

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	/*
	 * Intel percore register state.
	 * Coordinate shared resources between HT threads.
	 */
	int				percore_used; /* Used by this CPU? */
	struct intel_percore		*per_core;

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	/*
	 * AMD specific bits
	 */
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	struct amd_nb		*amd_nb;
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};

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#define __EVENT_CONSTRAINT(c, n, m, w) {\
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	{ .idxmsk64 = (n) },		\
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	.code = (c),			\
	.cmask = (m),			\
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	.weight = (w),			\
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}
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#define EVENT_CONSTRAINT(c, n, m)	\
	__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))

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/*
 * Constraint on the Event code.
 */
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#define INTEL_EVENT_CONSTRAINT(c, n)	\
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	EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
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/*
 * Constraint on the Event code + UMask + fixed-mask
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 *
 * filter mask to validate fixed counter events.
 * the following filters disqualify for fixed counters:
 *  - inv
 *  - edge
 *  - cnt-mask
 *  The other filters are supported by fixed counters.
 *  The any-thread option is supported starting with v3.
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 */
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#define FIXED_EVENT_CONSTRAINT(c, n)	\
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	EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
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/*
 * Constraint on the Event code + UMask
 */
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#define INTEL_UEVENT_CONSTRAINT(c, n)	\
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	EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)

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#define EVENT_CONSTRAINT_END		\
	EVENT_CONSTRAINT(0, 0, 0)

#define for_each_event_constraint(e, c)	\
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	for ((e) = (c); (e)->weight; (e)++)
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/*
 * Extra registers for specific events.
 * Some events need large masks and require external MSRs.
 * Define a mapping to these extra registers.
 */
struct extra_reg {
	unsigned int		event;
	unsigned int		msr;
	u64			config_mask;
	u64			valid_mask;
};

#define EVENT_EXTRA_REG(e, ms, m, vm) {	\
	.event = (e),		\
	.msr = (ms),		\
	.config_mask = (m),	\
	.valid_mask = (vm),	\
	}
#define INTEL_EVENT_EXTRA_REG(event, msr, vm)	\
	EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm)
#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0)

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union perf_capabilities {
	struct {
		u64	lbr_format    : 6;
		u64	pebs_trap     : 1;
		u64	pebs_arch_reg : 1;
		u64	pebs_format   : 4;
		u64	smm_freeze    : 1;
	};
	u64	capabilities;
};

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/*
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 * struct x86_pmu - generic x86 pmu
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 */
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struct x86_pmu {
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	/*
	 * Generic x86 PMC bits
	 */
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	const char	*name;
	int		version;
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	int		(*handle_irq)(struct pt_regs *);
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	void		(*disable_all)(void);
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	void		(*enable_all)(int added);
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	void		(*enable)(struct perf_event *);
	void		(*disable)(struct perf_event *);
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	void		(*hw_watchdog_set_attr)(struct perf_event_attr *attr);
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	int		(*hw_config)(struct perf_event *event);
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	int		(*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
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	unsigned	eventsel;
	unsigned	perfctr;
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	u64		(*event_map)(int);
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	int		max_events;
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	int		num_counters;
	int		num_counters_fixed;
	int		cntval_bits;
	u64		cntval_mask;
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	int		apic;
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	u64		max_period;
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	struct event_constraint *
			(*get_event_constraints)(struct cpu_hw_events *cpuc,
						 struct perf_event *event);

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	void		(*put_event_constraints)(struct cpu_hw_events *cpuc,
						 struct perf_event *event);
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	struct event_constraint *event_constraints;
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	struct event_constraint *percore_constraints;
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	void		(*quirks)(void);
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	int		perfctr_second_write;
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	int		(*cpu_prepare)(int cpu);
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	void		(*cpu_starting)(int cpu);
	void		(*cpu_dying)(int cpu);
	void		(*cpu_dead)(int cpu);
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	/*
	 * Intel Arch Perfmon v2+
	 */
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	u64			intel_ctrl;
	union perf_capabilities intel_cap;
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	/*
	 * Intel DebugStore bits
	 */
	int		bts, pebs;
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	int		bts_active, pebs_active;
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	int		pebs_record_size;
	void		(*drain_pebs)(struct pt_regs *regs);
	struct event_constraint *pebs_constraints;
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	/*
	 * Intel LBR
	 */
	unsigned long	lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
	int		lbr_nr;			   /* hardware stack size */
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	/*
	 * Extra registers for events
	 */
	struct extra_reg *extra_regs;
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};

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static struct x86_pmu x86_pmu __read_mostly;
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static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
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	.enabled = 1,
};
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static int x86_perf_event_set_period(struct perf_event *event);
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/*
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 * Generalized hw caching related hw_event table, filled
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 * in on a per model basis. A value of 0 means
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 * 'not supported', -1 means 'hw_event makes no sense on
 * this CPU', any other value means the raw hw_event
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 * ID.
 */

#define C(x) PERF_COUNT_HW_CACHE_##x

static u64 __read_mostly hw_cache_event_ids
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
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static u64 __read_mostly hw_cache_extra_regs
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
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void hw_nmi_watchdog_set_attr(struct perf_event_attr *wd_attr)
{
	if (x86_pmu.hw_watchdog_set_attr)
		x86_pmu.hw_watchdog_set_attr(wd_attr);
}

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/*
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 * Propagate event elapsed time into the generic event.
 * Can only be executed on the CPU where the event is active.
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 * Returns the delta events processed.
 */
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static u64
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x86_perf_event_update(struct perf_event *event)
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{
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	struct hw_perf_event *hwc = &event->hw;
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	int shift = 64 - x86_pmu.cntval_bits;
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	u64 prev_raw_count, new_raw_count;
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	int idx = hwc->idx;
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	s64 delta;
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	if (idx == X86_PMC_IDX_FIXED_BTS)
		return 0;

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	/*
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	 * Careful: an NMI might modify the previous event value.
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	 *
	 * Our tactic to handle this is to first atomically read and
	 * exchange a new raw count - then add that new-prev delta
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	 * count to the generic event atomically:
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	 */
again:
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	prev_raw_count = local64_read(&hwc->prev_count);
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	rdmsrl(hwc->event_base, new_raw_count);
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	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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					new_raw_count) != prev_raw_count)
		goto again;

	/*
	 * Now we have the new raw value and have updated the prev
	 * timestamp already. We can now calculate the elapsed delta
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	 * (event-)time and add that to the generic event.
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	 *
	 * Careful, not all hw sign-extends above the physical width
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	 * of the count.
364
	 */
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	delta = (new_raw_count << shift) - (prev_raw_count << shift);
	delta >>= shift;
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	local64_add(delta, &event->count);
	local64_sub(delta, &hwc->period_left);
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	return new_raw_count;
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}

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static inline int x86_pmu_addr_offset(int index)
{
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	int offset;

	/* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
	alternative_io(ASM_NOP2,
		       "shll $1, %%eax",
		       X86_FEATURE_PERFCTR_CORE,
		       "=a" (offset),
		       "a"  (index));

	return offset;
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}

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static inline unsigned int x86_pmu_config_addr(int index)
{
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	return x86_pmu.eventsel + x86_pmu_addr_offset(index);
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}

static inline unsigned int x86_pmu_event_addr(int index)
{
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	return x86_pmu.perfctr + x86_pmu_addr_offset(index);
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}

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/*
 * Find and validate any extra registers to set up.
 */
static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
{
	struct extra_reg *er;

	event->hw.extra_reg = 0;
	event->hw.extra_config = 0;

	if (!x86_pmu.extra_regs)
		return 0;

	for (er = x86_pmu.extra_regs; er->msr; er++) {
		if (er->event != (config & er->config_mask))
			continue;
		if (event->attr.config1 & ~er->valid_mask)
			return -EINVAL;
		event->hw.extra_reg = er->msr;
		event->hw.extra_config = event->attr.config1;
		break;
	}
	return 0;
}

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static atomic_t active_events;
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static DEFINE_MUTEX(pmc_reserve_mutex);

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#ifdef CONFIG_X86_LOCAL_APIC

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static bool reserve_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
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			goto perfctr_fail;
	}

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
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			goto eventsel_fail;
	}

	return true;

eventsel_fail:
	for (i--; i >= 0; i--)
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		release_evntsel_nmi(x86_pmu_config_addr(i));
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	i = x86_pmu.num_counters;
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perfctr_fail:
	for (i--; i >= 0; i--)
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		release_perfctr_nmi(x86_pmu_event_addr(i));
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	return false;
}

static void release_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		release_perfctr_nmi(x86_pmu_event_addr(i));
		release_evntsel_nmi(x86_pmu_config_addr(i));
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	}
}

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#else

static bool reserve_pmc_hardware(void) { return true; }
static void release_pmc_hardware(void) {}

#endif

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static bool check_hw_exists(void)
{
	u64 val, val_new = 0;
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	int i, reg, ret = 0;
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	/*
	 * Check to see if the BIOS enabled any of the counters, if so
	 * complain and bail.
	 */
	for (i = 0; i < x86_pmu.num_counters; i++) {
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		reg = x86_pmu_config_addr(i);
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		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
		if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
			goto bios_fail;
	}

	if (x86_pmu.num_counters_fixed) {
		reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
		for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
			if (val & (0x03 << i*4))
				goto bios_fail;
		}
	}

	/*
	 * Now write a value and read it back to see if it matches,
	 * this is needed to detect certain hardware emulators (qemu/kvm)
	 * that don't trap on the MSR access and always return 0s.
	 */
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	val = 0xabcdUL;
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	ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
	ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
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	if (ret || val != val_new)
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		goto msr_fail;
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	return true;
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bios_fail:
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	/*
	 * We still allow the PMU driver to operate:
	 */
	printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
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	printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
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	return true;
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msr_fail:
	printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
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	return false;
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}

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static void reserve_ds_buffers(void);
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static void release_ds_buffers(void);
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static void hw_perf_event_destroy(struct perf_event *event)
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{
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	if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
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		release_pmc_hardware();
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		release_ds_buffers();
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		mutex_unlock(&pmc_reserve_mutex);
	}
}

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static inline int x86_pmu_initialized(void)
{
	return x86_pmu.handle_irq != NULL;
}

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static inline int
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set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
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{
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	struct perf_event_attr *attr = &event->attr;
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	unsigned int cache_type, cache_op, cache_result;
	u64 config, val;

	config = attr->config;

	cache_type = (config >>  0) & 0xff;
	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
		return -EINVAL;

	cache_op = (config >>  8) & 0xff;
	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
		return -EINVAL;

	cache_result = (config >> 16) & 0xff;
	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
		return -EINVAL;

	val = hw_cache_event_ids[cache_type][cache_op][cache_result];

	if (val == 0)
		return -ENOENT;

	if (val == -1)
		return -EINVAL;

	hwc->config |= val;
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	attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
	return x86_pmu_extra_regs(val, event);
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}

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static int x86_setup_perfctr(struct perf_event *event)
{
	struct perf_event_attr *attr = &event->attr;
	struct hw_perf_event *hwc = &event->hw;
	u64 config;

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	if (!is_sampling_event(event)) {
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		hwc->sample_period = x86_pmu.max_period;
		hwc->last_period = hwc->sample_period;
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		local64_set(&hwc->period_left, hwc->sample_period);
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	} else {
		/*
		 * If we have a PMU initialized but no APIC
		 * interrupts, we cannot sample hardware
		 * events (user-space has to fall back and
		 * sample via a hrtimer based software event):
		 */
		if (!x86_pmu.apic)
			return -EOPNOTSUPP;
	}

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	/*
	 * Do not allow config1 (extended registers) to propagate,
	 * there's no sane user-space generalization yet:
	 */
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	if (attr->type == PERF_TYPE_RAW)
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		return 0;
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	if (attr->type == PERF_TYPE_HW_CACHE)
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		return set_ext_hw_attr(hwc, event);
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	if (attr->config >= x86_pmu.max_events)
		return -EINVAL;

	/*
	 * The generic map:
	 */
	config = x86_pmu.event_map(attr->config);

	if (config == 0)
		return -ENOENT;

	if (config == -1LL)
		return -EINVAL;

	/*
	 * Branch tracing:
	 */
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	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
	    !attr->freq && hwc->sample_period == 1) {
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		/* BTS is not supported by this architecture. */
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		if (!x86_pmu.bts_active)
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			return -EOPNOTSUPP;

		/* BTS is currently only allowed for user-mode. */
		if (!attr->exclude_kernel)
			return -EOPNOTSUPP;
	}

	hwc->config |= config;

	return 0;
}
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static int x86_pmu_hw_config(struct perf_event *event)
647
{
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	if (event->attr.precise_ip) {
		int precise = 0;

		/* Support for constant skid */
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		if (x86_pmu.pebs_active) {
P
Peter Zijlstra 已提交
653 654
			precise++;

655 656 657 658
			/* Support for IP fixup */
			if (x86_pmu.lbr_nr)
				precise++;
		}
P
Peter Zijlstra 已提交
659 660 661 662 663

		if (event->attr.precise_ip > precise)
			return -EOPNOTSUPP;
	}

664 665 666 667
	/*
	 * Generate PMC IRQs:
	 * (keep 'enabled' bit clear for now)
	 */
668
	event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
669 670 671 672

	/*
	 * Count user and OS events unless requested not to
	 */
673 674 675 676
	if (!event->attr.exclude_user)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
	if (!event->attr.exclude_kernel)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
677

678 679
	if (event->attr.type == PERF_TYPE_RAW)
		event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
680

681
	return x86_setup_perfctr(event);
682 683
}

I
Ingo Molnar 已提交
684
/*
685
 * Setup the hardware configuration for a given attr_type
I
Ingo Molnar 已提交
686
 */
687
static int __x86_pmu_event_init(struct perf_event *event)
I
Ingo Molnar 已提交
688
{
P
Peter Zijlstra 已提交
689
	int err;
I
Ingo Molnar 已提交
690

691 692
	if (!x86_pmu_initialized())
		return -ENODEV;
I
Ingo Molnar 已提交
693

P
Peter Zijlstra 已提交
694
	err = 0;
695
	if (!atomic_inc_not_zero(&active_events)) {
P
Peter Zijlstra 已提交
696
		mutex_lock(&pmc_reserve_mutex);
697
		if (atomic_read(&active_events) == 0) {
698 699
			if (!reserve_pmc_hardware())
				err = -EBUSY;
700 701
			else
				reserve_ds_buffers();
702 703
		}
		if (!err)
704
			atomic_inc(&active_events);
P
Peter Zijlstra 已提交
705 706 707 708 709
		mutex_unlock(&pmc_reserve_mutex);
	}
	if (err)
		return err;

710
	event->destroy = hw_perf_event_destroy;
711

712 713 714
	event->hw.idx = -1;
	event->hw.last_cpu = -1;
	event->hw.last_tag = ~0ULL;
715

716
	return x86_pmu.hw_config(event);
717 718
}

719
static void x86_pmu_disable_all(void)
720
{
721
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
722 723
	int idx;

724
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
725 726
		u64 val;

727
		if (!test_bit(idx, cpuc->active_mask))
728
			continue;
729
		rdmsrl(x86_pmu_config_addr(idx), val);
730
		if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
731
			continue;
732
		val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
733
		wrmsrl(x86_pmu_config_addr(idx), val);
734 735 736
	}
}

P
Peter Zijlstra 已提交
737
static void x86_pmu_disable(struct pmu *pmu)
738
{
739 740
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);

741
	if (!x86_pmu_initialized())
742
		return;
743

744 745 746 747 748 749
	if (!cpuc->enabled)
		return;

	cpuc->n_added = 0;
	cpuc->enabled = 0;
	barrier();
750 751

	x86_pmu.disable_all();
752
}
I
Ingo Molnar 已提交
753

754 755 756
static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
					  u64 enable_mask)
{
757 758
	if (hwc->extra_reg)
		wrmsrl(hwc->extra_reg, hwc->extra_config);
759
	wrmsrl(hwc->config_base, hwc->config | enable_mask);
760 761
}

762
static void x86_pmu_enable_all(int added)
763
{
764
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
765 766
	int idx;

767
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
768
		struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
769

770
		if (!test_bit(idx, cpuc->active_mask))
771
			continue;
772

773
		__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
774 775 776
	}
}

P
Peter Zijlstra 已提交
777
static struct pmu pmu;
778 779 780 781 782 783 784 785

static inline int is_x86_event(struct perf_event *event)
{
	return event->pmu == &pmu;
}

static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
{
786
	struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
787
	unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
788
	int i, j, w, wmax, num = 0;
789 790 791 792 793
	struct hw_perf_event *hwc;

	bitmap_zero(used_mask, X86_PMC_IDX_MAX);

	for (i = 0; i < n; i++) {
794 795
		c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
		constraints[i] = c;
796 797
	}

798 799 800
	/*
	 * fastpath, try to reuse previous register
	 */
801
	for (i = 0; i < n; i++) {
802
		hwc = &cpuc->event_list[i]->hw;
803
		c = constraints[i];
804 805 806 807 808 809

		/* never assigned */
		if (hwc->idx == -1)
			break;

		/* constraint still honored */
810
		if (!test_bit(hwc->idx, c->idxmsk))
811 812 813 814 815 816
			break;

		/* not already used */
		if (test_bit(hwc->idx, used_mask))
			break;

P
Peter Zijlstra 已提交
817
		__set_bit(hwc->idx, used_mask);
818 819 820
		if (assign)
			assign[i] = hwc->idx;
	}
821
	if (i == n)
822 823 824 825 826 827 828 829
		goto done;

	/*
	 * begin slow path
	 */

	bitmap_zero(used_mask, X86_PMC_IDX_MAX);

830 831 832 833 834 835 836 837 838
	/*
	 * weight = number of possible counters
	 *
	 * 1    = most constrained, only works on one counter
	 * wmax = least constrained, works on any counter
	 *
	 * assign events to counters starting with most
	 * constrained events.
	 */
839
	wmax = x86_pmu.num_counters;
840 841 842 843 844 845

	/*
	 * when fixed event counters are present,
	 * wmax is incremented by 1 to account
	 * for one more choice
	 */
846
	if (x86_pmu.num_counters_fixed)
847 848
		wmax++;

849
	for (w = 1, num = n; num && w <= wmax; w++) {
850
		/* for each event */
851
		for (i = 0; num && i < n; i++) {
852
			c = constraints[i];
853 854
			hwc = &cpuc->event_list[i]->hw;

855
			if (c->weight != w)
856 857
				continue;

858
			for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
859 860 861 862 863 864 865
				if (!test_bit(j, used_mask))
					break;
			}

			if (j == X86_PMC_IDX_MAX)
				break;

P
Peter Zijlstra 已提交
866
			__set_bit(j, used_mask);
867

868 869 870 871 872
			if (assign)
				assign[i] = j;
			num--;
		}
	}
873
done:
874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895
	/*
	 * scheduling failed or is just a simulation,
	 * free resources if necessary
	 */
	if (!assign || num) {
		for (i = 0; i < n; i++) {
			if (x86_pmu.put_event_constraints)
				x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
		}
	}
	return num ? -ENOSPC : 0;
}

/*
 * dogrp: true if must collect siblings events (group)
 * returns total number of events and error code
 */
static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
{
	struct perf_event *event;
	int n, max_count;

896
	max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
897 898 899 900 901 902 903 904 905 906 907 908 909 910 911

	/* current number of events already accepted */
	n = cpuc->n_events;

	if (is_x86_event(leader)) {
		if (n >= max_count)
			return -ENOSPC;
		cpuc->event_list[n] = leader;
		n++;
	}
	if (!dogrp)
		return n;

	list_for_each_entry(event, &leader->sibling_list, group_entry) {
		if (!is_x86_event(event) ||
912
		    event->state <= PERF_EVENT_STATE_OFF)
913 914 915 916 917 918 919 920 921 922 923 924
			continue;

		if (n >= max_count)
			return -ENOSPC;

		cpuc->event_list[n] = event;
		n++;
	}
	return n;
}

static inline void x86_assign_hw_event(struct perf_event *event,
925
				struct cpu_hw_events *cpuc, int i)
926
{
927 928 929 930 931
	struct hw_perf_event *hwc = &event->hw;

	hwc->idx = cpuc->assign[i];
	hwc->last_cpu = smp_processor_id();
	hwc->last_tag = ++cpuc->tags[i];
932 933 934 935 936 937

	if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
		hwc->config_base = 0;
		hwc->event_base	= 0;
	} else if (hwc->idx >= X86_PMC_IDX_FIXED) {
		hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
938
		hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
939
	} else {
940 941
		hwc->config_base = x86_pmu_config_addr(hwc->idx);
		hwc->event_base  = x86_pmu_event_addr(hwc->idx);
942 943 944
	}
}

945 946 947 948 949 950 951 952 953
static inline int match_prev_assignment(struct hw_perf_event *hwc,
					struct cpu_hw_events *cpuc,
					int i)
{
	return hwc->idx == cpuc->assign[i] &&
		hwc->last_cpu == smp_processor_id() &&
		hwc->last_tag == cpuc->tags[i];
}

P
Peter Zijlstra 已提交
954 955
static void x86_pmu_start(struct perf_event *event, int flags);
static void x86_pmu_stop(struct perf_event *event, int flags);
956

P
Peter Zijlstra 已提交
957
static void x86_pmu_enable(struct pmu *pmu)
958
{
959 960 961
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	struct perf_event *event;
	struct hw_perf_event *hwc;
962
	int i, added = cpuc->n_added;
963

964
	if (!x86_pmu_initialized())
965
		return;
966 967 968 969

	if (cpuc->enabled)
		return;

970
	if (cpuc->n_added) {
971
		int n_running = cpuc->n_events - cpuc->n_added;
972 973 974 975 976 977 978
		/*
		 * apply assignment obtained either from
		 * hw_perf_group_sched_in() or x86_pmu_enable()
		 *
		 * step1: save events moving to new counters
		 * step2: reprogram moved events into new counters
		 */
979
		for (i = 0; i < n_running; i++) {
980 981 982
			event = cpuc->event_list[i];
			hwc = &event->hw;

983 984 985 986 987 988 989 990
			/*
			 * we can avoid reprogramming counter if:
			 * - assigned same counter as last time
			 * - running on same CPU as last time
			 * - no other event has used the counter since
			 */
			if (hwc->idx == -1 ||
			    match_prev_assignment(hwc, cpuc, i))
991 992
				continue;

P
Peter Zijlstra 已提交
993 994 995 996 997 998 999 1000
			/*
			 * Ensure we don't accidentally enable a stopped
			 * counter simply because we rescheduled.
			 */
			if (hwc->state & PERF_HES_STOPPED)
				hwc->state |= PERF_HES_ARCH;

			x86_pmu_stop(event, PERF_EF_UPDATE);
1001 1002 1003 1004 1005 1006
		}

		for (i = 0; i < cpuc->n_events; i++) {
			event = cpuc->event_list[i];
			hwc = &event->hw;

1007
			if (!match_prev_assignment(hwc, cpuc, i))
1008
				x86_assign_hw_event(event, cpuc, i);
1009 1010
			else if (i < n_running)
				continue;
1011

P
Peter Zijlstra 已提交
1012 1013 1014 1015
			if (hwc->state & PERF_HES_ARCH)
				continue;

			x86_pmu_start(event, PERF_EF_RELOAD);
1016 1017 1018 1019
		}
		cpuc->n_added = 0;
		perf_events_lapic_init();
	}
1020 1021 1022 1023

	cpuc->enabled = 1;
	barrier();

1024
	x86_pmu.enable_all(added);
1025 1026
}

1027
static inline void x86_pmu_disable_event(struct perf_event *event)
1028
{
1029
	struct hw_perf_event *hwc = &event->hw;
1030

1031
	wrmsrl(hwc->config_base, hwc->config);
1032 1033
}

1034
static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
I
Ingo Molnar 已提交
1035

1036 1037
/*
 * Set the next IRQ period, based on the hwc->period_left value.
1038
 * To be called with the event disabled in hw:
1039
 */
1040
static int
1041
x86_perf_event_set_period(struct perf_event *event)
I
Ingo Molnar 已提交
1042
{
1043
	struct hw_perf_event *hwc = &event->hw;
1044
	s64 left = local64_read(&hwc->period_left);
1045
	s64 period = hwc->sample_period;
1046
	int ret = 0, idx = hwc->idx;
1047

1048 1049 1050
	if (idx == X86_PMC_IDX_FIXED_BTS)
		return 0;

1051
	/*
1052
	 * If we are way outside a reasonable range then just skip forward:
1053 1054 1055
	 */
	if (unlikely(left <= -period)) {
		left = period;
1056
		local64_set(&hwc->period_left, left);
1057
		hwc->last_period = period;
1058
		ret = 1;
1059 1060 1061 1062
	}

	if (unlikely(left <= 0)) {
		left += period;
1063
		local64_set(&hwc->period_left, left);
1064
		hwc->last_period = period;
1065
		ret = 1;
1066
	}
1067
	/*
1068
	 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1069 1070 1071
	 */
	if (unlikely(left < 2))
		left = 2;
I
Ingo Molnar 已提交
1072

1073 1074 1075
	if (left > x86_pmu.max_period)
		left = x86_pmu.max_period;

1076
	per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1077 1078

	/*
1079
	 * The hw event starts counting from this event offset,
1080 1081
	 * mark it to be able to extra future deltas:
	 */
1082
	local64_set(&hwc->prev_count, (u64)-left);
1083

1084
	wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1085 1086 1087 1088 1089 1090 1091

	/*
	 * Due to erratum on certan cpu we need
	 * a second write to be sure the register
	 * is updated properly
	 */
	if (x86_pmu.perfctr_second_write) {
1092
		wrmsrl(hwc->event_base,
1093
			(u64)(-left) & x86_pmu.cntval_mask);
1094
	}
1095

1096
	perf_event_update_userpage(event);
1097

1098
	return ret;
1099 1100
}

1101
static void x86_pmu_enable_event(struct perf_event *event)
1102
{
T
Tejun Heo 已提交
1103
	if (__this_cpu_read(cpu_hw_events.enabled))
1104 1105
		__x86_pmu_enable_event(&event->hw,
				       ARCH_PERFMON_EVENTSEL_ENABLE);
I
Ingo Molnar 已提交
1106 1107
}

1108
/*
P
Peter Zijlstra 已提交
1109
 * Add a single event to the PMU.
1110 1111 1112
 *
 * The event is added to the group of enabled events
 * but only if it can be scehduled with existing events.
1113
 */
P
Peter Zijlstra 已提交
1114
static int x86_pmu_add(struct perf_event *event, int flags)
1115 1116
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1117 1118 1119
	struct hw_perf_event *hwc;
	int assign[X86_PMC_IDX_MAX];
	int n, n0, ret;
1120

1121
	hwc = &event->hw;
1122

P
Peter Zijlstra 已提交
1123
	perf_pmu_disable(event->pmu);
1124
	n0 = cpuc->n_events;
1125 1126 1127
	ret = n = collect_events(cpuc, event, false);
	if (ret < 0)
		goto out;
1128

P
Peter Zijlstra 已提交
1129 1130 1131 1132
	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
	if (!(flags & PERF_EF_START))
		hwc->state |= PERF_HES_ARCH;

1133 1134
	/*
	 * If group events scheduling transaction was started,
L
Lucas De Marchi 已提交
1135
	 * skip the schedulability test here, it will be performed
P
Peter Zijlstra 已提交
1136
	 * at commit time (->commit_txn) as a whole
1137
	 */
1138
	if (cpuc->group_flag & PERF_EVENT_TXN)
1139
		goto done_collect;
1140

1141
	ret = x86_pmu.schedule_events(cpuc, n, assign);
1142
	if (ret)
1143
		goto out;
1144 1145 1146 1147 1148
	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));
1149

1150
done_collect:
1151
	cpuc->n_events = n;
1152
	cpuc->n_added += n - n0;
1153
	cpuc->n_txn += n - n0;
1154

1155 1156
	ret = 0;
out:
P
Peter Zijlstra 已提交
1157
	perf_pmu_enable(event->pmu);
1158
	return ret;
I
Ingo Molnar 已提交
1159 1160
}

P
Peter Zijlstra 已提交
1161
static void x86_pmu_start(struct perf_event *event, int flags)
1162
{
P
Peter Zijlstra 已提交
1163 1164 1165
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int idx = event->hw.idx;

P
Peter Zijlstra 已提交
1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177
	if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
		return;

	if (WARN_ON_ONCE(idx == -1))
		return;

	if (flags & PERF_EF_RELOAD) {
		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
		x86_perf_event_set_period(event);
	}

	event->hw.state = 0;
1178

P
Peter Zijlstra 已提交
1179 1180
	cpuc->events[idx] = event;
	__set_bit(idx, cpuc->active_mask);
1181
	__set_bit(idx, cpuc->running);
1182
	x86_pmu.enable(event);
P
Peter Zijlstra 已提交
1183
	perf_event_update_userpage(event);
1184 1185
}

1186
void perf_event_print_debug(void)
I
Ingo Molnar 已提交
1187
{
1188
	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1189
	u64 pebs;
1190
	struct cpu_hw_events *cpuc;
1191
	unsigned long flags;
1192 1193
	int cpu, idx;

1194
	if (!x86_pmu.num_counters)
1195
		return;
I
Ingo Molnar 已提交
1196

1197
	local_irq_save(flags);
I
Ingo Molnar 已提交
1198 1199

	cpu = smp_processor_id();
1200
	cpuc = &per_cpu(cpu_hw_events, cpu);
I
Ingo Molnar 已提交
1201

1202
	if (x86_pmu.version >= 2) {
1203 1204 1205 1206
		rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
		rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
		rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1207
		rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1208 1209 1210 1211 1212 1213

		pr_info("\n");
		pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
		pr_info("CPU#%d: status:     %016llx\n", cpu, status);
		pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
		pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1214
		pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1215
	}
1216
	pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
I
Ingo Molnar 已提交
1217

1218
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1219 1220
		rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
		rdmsrl(x86_pmu_event_addr(idx), pmc_count);
I
Ingo Molnar 已提交
1221

1222
		prev_left = per_cpu(pmc_prev_left[idx], cpu);
I
Ingo Molnar 已提交
1223

1224
		pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
I
Ingo Molnar 已提交
1225
			cpu, idx, pmc_ctrl);
1226
		pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
I
Ingo Molnar 已提交
1227
			cpu, idx, pmc_count);
1228
		pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1229
			cpu, idx, prev_left);
I
Ingo Molnar 已提交
1230
	}
1231
	for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1232 1233
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);

1234
		pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1235 1236
			cpu, idx, pmc_count);
	}
1237
	local_irq_restore(flags);
I
Ingo Molnar 已提交
1238 1239
}

P
Peter Zijlstra 已提交
1240
static void x86_pmu_stop(struct perf_event *event, int flags)
I
Ingo Molnar 已提交
1241
{
1242
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1243
	struct hw_perf_event *hwc = &event->hw;
I
Ingo Molnar 已提交
1244

P
Peter Zijlstra 已提交
1245 1246 1247 1248 1249 1250
	if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
		x86_pmu.disable(event);
		cpuc->events[hwc->idx] = NULL;
		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
		hwc->state |= PERF_HES_STOPPED;
	}
1251

P
Peter Zijlstra 已提交
1252 1253 1254 1255 1256 1257 1258 1259
	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
		/*
		 * Drain the remaining delta count out of a event
		 * that we are disabling:
		 */
		x86_perf_event_update(event);
		hwc->state |= PERF_HES_UPTODATE;
	}
1260 1261
}

P
Peter Zijlstra 已提交
1262
static void x86_pmu_del(struct perf_event *event, int flags)
1263 1264 1265 1266
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int i;

1267 1268 1269 1270 1271
	/*
	 * If we're called during a txn, we don't need to do anything.
	 * The events never got scheduled and ->cancel_txn will truncate
	 * the event_list.
	 */
1272
	if (cpuc->group_flag & PERF_EVENT_TXN)
1273 1274
		return;

P
Peter Zijlstra 已提交
1275
	x86_pmu_stop(event, PERF_EF_UPDATE);
1276

1277 1278 1279 1280 1281 1282 1283 1284 1285 1286
	for (i = 0; i < cpuc->n_events; i++) {
		if (event == cpuc->event_list[i]) {

			if (x86_pmu.put_event_constraints)
				x86_pmu.put_event_constraints(cpuc, event);

			while (++i < cpuc->n_events)
				cpuc->event_list[i-1] = cpuc->event_list[i];

			--cpuc->n_events;
1287
			break;
1288 1289
		}
	}
1290
	perf_event_update_userpage(event);
I
Ingo Molnar 已提交
1291 1292
}

1293
static int x86_pmu_handle_irq(struct pt_regs *regs)
1294
{
1295
	struct perf_sample_data data;
1296 1297
	struct cpu_hw_events *cpuc;
	struct perf_event *event;
V
Vince Weaver 已提交
1298
	int idx, handled = 0;
1299 1300
	u64 val;

1301
	perf_sample_data_init(&data, 0);
1302

1303
	cpuc = &__get_cpu_var(cpu_hw_events);
1304

1305 1306 1307 1308 1309 1310 1311 1312 1313 1314
	/*
	 * Some chipsets need to unmask the LVTPC in a particular spot
	 * inside the nmi handler.  As a result, the unmasking was pushed
	 * into all the nmi handlers.
	 *
	 * This generic handler doesn't seem to have any issues where the
	 * unmasking occurs so it was left at the top.
	 */
	apic_write(APIC_LVTPC, APIC_DM_NMI);

1315
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1316 1317 1318 1319 1320 1321 1322 1323
		if (!test_bit(idx, cpuc->active_mask)) {
			/*
			 * Though we deactivated the counter some cpus
			 * might still deliver spurious interrupts still
			 * in flight. Catch them:
			 */
			if (__test_and_clear_bit(idx, cpuc->running))
				handled++;
1324
			continue;
1325
		}
1326

1327
		event = cpuc->events[idx];
1328

1329
		val = x86_perf_event_update(event);
1330
		if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1331
			continue;
1332

1333
		/*
1334
		 * event overflow
1335
		 */
1336
		handled++;
1337
		data.period	= event->hw.last_period;
1338

1339
		if (!x86_perf_event_set_period(event))
1340 1341
			continue;

1342
		if (perf_event_overflow(event, &data, regs))
P
Peter Zijlstra 已提交
1343
			x86_pmu_stop(event, 0);
1344
	}
1345

1346 1347 1348
	if (handled)
		inc_irq_stat(apic_perf_irqs);

1349 1350
	return handled;
}
1351

1352
void perf_events_lapic_init(void)
I
Ingo Molnar 已提交
1353
{
1354
	if (!x86_pmu.apic || !x86_pmu_initialized())
I
Ingo Molnar 已提交
1355
		return;
1356

I
Ingo Molnar 已提交
1357
	/*
1358
	 * Always use NMI for PMU
I
Ingo Molnar 已提交
1359
	 */
1360
	apic_write(APIC_LVTPC, APIC_DM_NMI);
I
Ingo Molnar 已提交
1361 1362
}

1363 1364 1365 1366 1367 1368 1369
struct pmu_nmi_state {
	unsigned int	marked;
	int		handled;
};

static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);

I
Ingo Molnar 已提交
1370
static int __kprobes
1371
perf_event_nmi_handler(struct notifier_block *self,
I
Ingo Molnar 已提交
1372 1373 1374
			 unsigned long cmd, void *__args)
{
	struct die_args *args = __args;
1375 1376
	unsigned int this_nmi;
	int handled;
1377

1378
	if (!atomic_read(&active_events))
1379 1380
		return NOTIFY_DONE;

1381 1382 1383
	switch (cmd) {
	case DIE_NMI:
		break;
1384 1385
	case DIE_NMIUNKNOWN:
		this_nmi = percpu_read(irq_stat.__nmi_count);
T
Tejun Heo 已提交
1386
		if (this_nmi != __this_cpu_read(pmu_nmi.marked))
1387 1388 1389 1390 1391 1392 1393 1394 1395 1396
			/* let the kernel handle the unknown nmi */
			return NOTIFY_DONE;
		/*
		 * This one is a PMU back-to-back nmi. Two events
		 * trigger 'simultaneously' raising two back-to-back
		 * NMIs. If the first NMI handles both, the latter
		 * will be empty and daze the CPU. So, we drop it to
		 * avoid false-positive 'unknown nmi' messages.
		 */
		return NOTIFY_STOP;
1397
	default:
I
Ingo Molnar 已提交
1398
		return NOTIFY_DONE;
1399
	}
I
Ingo Molnar 已提交
1400

1401 1402 1403 1404 1405 1406 1407
	handled = x86_pmu.handle_irq(args->regs);
	if (!handled)
		return NOTIFY_DONE;

	this_nmi = percpu_read(irq_stat.__nmi_count);
	if ((handled > 1) ||
		/* the next nmi could be a back-to-back nmi */
T
Tejun Heo 已提交
1408 1409
	    ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
	     (__this_cpu_read(pmu_nmi.handled) > 1))) {
1410 1411 1412 1413 1414 1415 1416 1417 1418 1419
		/*
		 * We could have two subsequent back-to-back nmis: The
		 * first handles more than one counter, the 2nd
		 * handles only one counter and the 3rd handles no
		 * counter.
		 *
		 * This is the 2nd nmi because the previous was
		 * handling more than one counter. We will mark the
		 * next (3rd) and then drop it if unhandled.
		 */
T
Tejun Heo 已提交
1420 1421
		__this_cpu_write(pmu_nmi.marked, this_nmi + 1);
		__this_cpu_write(pmu_nmi.handled, handled);
1422
	}
I
Ingo Molnar 已提交
1423

1424
	return NOTIFY_STOP;
I
Ingo Molnar 已提交
1425 1426
}

1427 1428 1429
static __read_mostly struct notifier_block perf_event_nmi_notifier = {
	.notifier_call		= perf_event_nmi_handler,
	.next			= NULL,
1430
	.priority		= NMI_LOCAL_LOW_PRIOR,
1431 1432
};

1433
static struct event_constraint unconstrained;
1434
static struct event_constraint emptyconstraint;
1435 1436

static struct event_constraint *
1437
x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1438
{
1439
	struct event_constraint *c;
1440 1441 1442

	if (x86_pmu.event_constraints) {
		for_each_event_constraint(c, x86_pmu.event_constraints) {
1443 1444
			if ((event->hw.config & c->cmask) == c->code)
				return c;
1445 1446
		}
	}
1447 1448

	return &unconstrained;
1449 1450
}

1451 1452
#include "perf_event_amd.c"
#include "perf_event_p6.c"
1453
#include "perf_event_p4.c"
1454
#include "perf_event_intel_lbr.c"
1455
#include "perf_event_intel_ds.c"
1456
#include "perf_event_intel.c"
1457

1458 1459 1460 1461
static int __cpuinit
x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
{
	unsigned int cpu = (long)hcpu;
1462
	int ret = NOTIFY_OK;
1463 1464 1465 1466

	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_UP_PREPARE:
		if (x86_pmu.cpu_prepare)
1467
			ret = x86_pmu.cpu_prepare(cpu);
1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479
		break;

	case CPU_STARTING:
		if (x86_pmu.cpu_starting)
			x86_pmu.cpu_starting(cpu);
		break;

	case CPU_DYING:
		if (x86_pmu.cpu_dying)
			x86_pmu.cpu_dying(cpu);
		break;

1480
	case CPU_UP_CANCELED:
1481 1482 1483 1484 1485 1486 1487 1488 1489
	case CPU_DEAD:
		if (x86_pmu.cpu_dead)
			x86_pmu.cpu_dead(cpu);
		break;

	default:
		break;
	}

1490
	return ret;
1491 1492
}

1493 1494 1495 1496 1497 1498 1499 1500 1501 1502
static void __init pmu_check_apic(void)
{
	if (cpu_has_apic)
		return;

	x86_pmu.apic = 0;
	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
	pr_info("no hardware sampling interrupt available.\n");
}

1503
static int __init init_hw_perf_events(void)
1504
{
1505
	struct event_constraint *c;
1506 1507
	int err;

1508
	pr_info("Performance Events: ");
1509

1510 1511
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_INTEL:
1512
		err = intel_pmu_init();
1513
		break;
1514
	case X86_VENDOR_AMD:
1515
		err = amd_pmu_init();
1516
		break;
1517
	default:
1518
		return 0;
1519
	}
1520
	if (err != 0) {
1521
		pr_cont("no PMU driver, software events only.\n");
1522
		return 0;
1523
	}
1524

1525 1526
	pmu_check_apic();

1527
	/* sanity check that the hardware exists or is emulated */
1528
	if (!check_hw_exists())
1529
		return 0;
1530

1531
	pr_cont("%s PMU driver.\n", x86_pmu.name);
1532

1533 1534 1535
	if (x86_pmu.quirks)
		x86_pmu.quirks();

1536
	if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1537
		WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1538 1539
		     x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
		x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
I
Ingo Molnar 已提交
1540
	}
1541
	x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
I
Ingo Molnar 已提交
1542

1543
	if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1544
		WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1545 1546
		     x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
		x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1547
	}
1548

1549
	x86_pmu.intel_ctrl |=
1550
		((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
I
Ingo Molnar 已提交
1551

1552 1553
	perf_events_lapic_init();
	register_die_notifier(&perf_event_nmi_notifier);
1554

1555
	unconstrained = (struct event_constraint)
1556 1557
		__EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
				   0, x86_pmu.num_counters);
1558

1559 1560
	if (x86_pmu.event_constraints) {
		for_each_event_constraint(c, x86_pmu.event_constraints) {
1561
			if (c->cmask != X86_RAW_EVENT_MASK)
1562 1563
				continue;

1564 1565
			c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
			c->weight += x86_pmu.num_counters;
1566 1567 1568
		}
	}

I
Ingo Molnar 已提交
1569
	pr_info("... version:                %d\n",     x86_pmu.version);
1570 1571 1572
	pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
	pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
	pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
I
Ingo Molnar 已提交
1573
	pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1574
	pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1575
	pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1576

P
Peter Zijlstra 已提交
1577
	perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1578
	perf_cpu_notifier(x86_pmu_notifier);
1579 1580

	return 0;
I
Ingo Molnar 已提交
1581
}
1582
early_initcall(init_hw_perf_events);
I
Ingo Molnar 已提交
1583

1584
static inline void x86_pmu_read(struct perf_event *event)
1585
{
1586
	x86_perf_event_update(event);
1587 1588
}

1589 1590 1591 1592 1593
/*
 * Start group events scheduling transaction
 * Set the flag to make pmu::enable() not perform the
 * schedulability test, it will be performed at commit time
 */
P
Peter Zijlstra 已提交
1594
static void x86_pmu_start_txn(struct pmu *pmu)
1595
{
P
Peter Zijlstra 已提交
1596
	perf_pmu_disable(pmu);
T
Tejun Heo 已提交
1597 1598
	__this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
	__this_cpu_write(cpu_hw_events.n_txn, 0);
1599 1600 1601 1602 1603 1604 1605
}

/*
 * Stop group events scheduling transaction
 * Clear the flag and pmu::enable() will perform the
 * schedulability test.
 */
P
Peter Zijlstra 已提交
1606
static void x86_pmu_cancel_txn(struct pmu *pmu)
1607
{
T
Tejun Heo 已提交
1608
	__this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1609 1610 1611
	/*
	 * Truncate the collected events.
	 */
T
Tejun Heo 已提交
1612 1613
	__this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
	__this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
P
Peter Zijlstra 已提交
1614
	perf_pmu_enable(pmu);
1615 1616 1617 1618 1619 1620 1621
}

/*
 * Commit group events scheduling transaction
 * Perform the group schedulability test as a whole
 * Return 0 if success
 */
P
Peter Zijlstra 已提交
1622
static int x86_pmu_commit_txn(struct pmu *pmu)
1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int assign[X86_PMC_IDX_MAX];
	int n, ret;

	n = cpuc->n_events;

	if (!x86_pmu_initialized())
		return -EAGAIN;

	ret = x86_pmu.schedule_events(cpuc, n, assign);
	if (ret)
		return ret;

	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));

1643
	cpuc->group_flag &= ~PERF_EVENT_TXN;
P
Peter Zijlstra 已提交
1644
	perf_pmu_enable(pmu);
1645 1646 1647
	return 0;
}

1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673
/*
 * validate that we can schedule this event
 */
static int validate_event(struct perf_event *event)
{
	struct cpu_hw_events *fake_cpuc;
	struct event_constraint *c;
	int ret = 0;

	fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
	if (!fake_cpuc)
		return -ENOMEM;

	c = x86_pmu.get_event_constraints(fake_cpuc, event);

	if (!c || !c->weight)
		ret = -ENOSPC;

	if (x86_pmu.put_event_constraints)
		x86_pmu.put_event_constraints(fake_cpuc, event);

	kfree(fake_cpuc);

	return ret;
}

1674 1675 1676 1677
/*
 * validate a single event group
 *
 * validation include:
1678 1679 1680
 *	- check events are compatible which each other
 *	- events do not compete for the same counter
 *	- number of events <= number of counters
1681 1682 1683 1684
 *
 * validation ensures the group can be loaded onto the
 * PMU if it was the only group available.
 */
1685 1686
static int validate_group(struct perf_event *event)
{
1687
	struct perf_event *leader = event->group_leader;
1688 1689
	struct cpu_hw_events *fake_cpuc;
	int ret, n;
1690

1691 1692 1693 1694
	ret = -ENOMEM;
	fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
	if (!fake_cpuc)
		goto out;
1695

1696 1697 1698 1699 1700 1701
	/*
	 * the event is not yet connected with its
	 * siblings therefore we must first collect
	 * existing siblings, then add the new event
	 * before we can simulate the scheduling
	 */
1702 1703
	ret = -ENOSPC;
	n = collect_events(fake_cpuc, leader, true);
1704
	if (n < 0)
1705
		goto out_free;
1706

1707 1708
	fake_cpuc->n_events = n;
	n = collect_events(fake_cpuc, event, false);
1709
	if (n < 0)
1710
		goto out_free;
1711

1712
	fake_cpuc->n_events = n;
1713

1714
	ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1715 1716 1717 1718 1719

out_free:
	kfree(fake_cpuc);
out:
	return ret;
1720 1721
}

1722
static int x86_pmu_event_init(struct perf_event *event)
I
Ingo Molnar 已提交
1723
{
P
Peter Zijlstra 已提交
1724
	struct pmu *tmp;
I
Ingo Molnar 已提交
1725 1726
	int err;

1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737
	switch (event->attr.type) {
	case PERF_TYPE_RAW:
	case PERF_TYPE_HARDWARE:
	case PERF_TYPE_HW_CACHE:
		break;

	default:
		return -ENOENT;
	}

	err = __x86_pmu_event_init(event);
1738
	if (!err) {
1739 1740 1741 1742 1743 1744 1745 1746
		/*
		 * we temporarily connect event to its pmu
		 * such that validate_group() can classify
		 * it as an x86 event using is_x86_event()
		 */
		tmp = event->pmu;
		event->pmu = &pmu;

1747 1748
		if (event->group_leader != event)
			err = validate_group(event);
1749 1750
		else
			err = validate_event(event);
1751 1752

		event->pmu = tmp;
1753
	}
1754
	if (err) {
1755 1756
		if (event->destroy)
			event->destroy(event);
1757
	}
I
Ingo Molnar 已提交
1758

1759
	return err;
I
Ingo Molnar 已提交
1760
}
1761

1762
static struct pmu pmu = {
P
Peter Zijlstra 已提交
1763 1764 1765
	.pmu_enable	= x86_pmu_enable,
	.pmu_disable	= x86_pmu_disable,

1766
	.event_init	= x86_pmu_event_init,
P
Peter Zijlstra 已提交
1767 1768 1769

	.add		= x86_pmu_add,
	.del		= x86_pmu_del,
1770 1771 1772
	.start		= x86_pmu_start,
	.stop		= x86_pmu_stop,
	.read		= x86_pmu_read,
P
Peter Zijlstra 已提交
1773

1774 1775 1776 1777 1778
	.start_txn	= x86_pmu_start_txn,
	.cancel_txn	= x86_pmu_cancel_txn,
	.commit_txn	= x86_pmu_commit_txn,
};

1779 1780 1781 1782 1783 1784
/*
 * callchain support
 */

static int backtrace_stack(void *data, char *name)
{
1785
	return 0;
1786 1787 1788 1789 1790 1791
}

static void backtrace_address(void *data, unsigned long addr, int reliable)
{
	struct perf_callchain_entry *entry = data;

1792
	perf_callchain_store(entry, addr);
1793 1794 1795 1796 1797
}

static const struct stacktrace_ops backtrace_ops = {
	.stack			= backtrace_stack,
	.address		= backtrace_address,
1798
	.walk_stack		= print_context_stack_bp,
1799 1800
};

1801 1802
void
perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1803
{
1804 1805
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
1806
		return;
1807 1808
	}

1809
	perf_callchain_store(entry, regs->ip);
1810

1811
	dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1812 1813
}

1814 1815 1816
#ifdef CONFIG_COMPAT
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1817
{
1818 1819 1820
	/* 32-bit process in 64-bit kernel. */
	struct stack_frame_ia32 frame;
	const void __user *fp;
1821

1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833
	if (!test_thread_flag(TIF_IA32))
		return 0;

	fp = compat_ptr(regs->bp);
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
		unsigned long bytes;
		frame.next_frame     = 0;
		frame.return_address = 0;

		bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
		if (bytes != sizeof(frame))
			break;
1834

1835 1836
		if (fp < compat_ptr(regs->sp))
			break;
1837

1838
		perf_callchain_store(entry, frame.return_address);
1839 1840 1841
		fp = compat_ptr(frame.next_frame);
	}
	return 1;
1842
}
1843 1844 1845 1846 1847 1848 1849
#else
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
{
    return 0;
}
#endif
1850

1851 1852
void
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1853 1854 1855 1856
{
	struct stack_frame frame;
	const void __user *fp;

1857 1858
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
1859
		return;
1860
	}
1861

1862
	fp = (void __user *)regs->bp;
1863

1864
	perf_callchain_store(entry, regs->ip);
1865

1866 1867 1868
	if (perf_callchain_user32(regs, entry))
		return;

1869
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
1870
		unsigned long bytes;
1871
		frame.next_frame	     = NULL;
1872 1873
		frame.return_address = 0;

1874 1875
		bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
		if (bytes != sizeof(frame))
1876 1877
			break;

1878
		if ((unsigned long)fp < regs->sp)
1879 1880
			break;

1881
		perf_callchain_store(entry, frame.return_address);
1882
		fp = frame.next_frame;
1883 1884 1885
	}
}

1886 1887 1888
unsigned long perf_instruction_pointer(struct pt_regs *regs)
{
	unsigned long ip;
1889

1890 1891 1892 1893
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
		ip = perf_guest_cbs->get_guest_ip();
	else
		ip = instruction_pointer(regs);
1894

1895 1896 1897 1898 1899 1900
	return ip;
}

unsigned long perf_misc_flags(struct pt_regs *regs)
{
	int misc = 0;
1901

1902
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913
		if (perf_guest_cbs->is_user_mode())
			misc |= PERF_RECORD_MISC_GUEST_USER;
		else
			misc |= PERF_RECORD_MISC_GUEST_KERNEL;
	} else {
		if (user_mode(regs))
			misc |= PERF_RECORD_MISC_USER;
		else
			misc |= PERF_RECORD_MISC_KERNEL;
	}

1914
	if (regs->flags & PERF_EFLAGS_EXACT)
P
Peter Zijlstra 已提交
1915
		misc |= PERF_RECORD_MISC_EXACT_IP;
1916 1917 1918

	return misc;
}