perf_event.c 43.6 KB
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/*
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 * Performance events x86 architecture code
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 *
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 *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
 *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
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 *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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 *  Copyright (C) 2009 Google, Inc., Stephane Eranian
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 *
 *  For licencing details see kernel-base/COPYING
 */

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#include <linux/perf_event.h>
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#include <linux/capability.h>
#include <linux/notifier.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
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#include <linux/module.h>
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#include <linux/kdebug.h>
#include <linux/sched.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/cpu.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <asm/apic.h>
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#include <asm/stacktrace.h>
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#include <asm/nmi.h>
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#include <asm/smp.h>
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#include <asm/alternative.h>
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#include <asm/timer.h>
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#include <asm/desc.h>
#include <asm/ldt.h>
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#include "perf_event.h"

struct x86_pmu x86_pmu __read_mostly;
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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
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	.enabled = 1,
};
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u64 __read_mostly hw_cache_event_ids
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				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
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u64 __read_mostly hw_cache_extra_regs
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				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
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/*
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 * Propagate event elapsed time into the generic event.
 * Can only be executed on the CPU where the event is active.
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 * Returns the delta events processed.
 */
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u64 x86_perf_event_update(struct perf_event *event)
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{
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	struct hw_perf_event *hwc = &event->hw;
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	int shift = 64 - x86_pmu.cntval_bits;
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	u64 prev_raw_count, new_raw_count;
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	int idx = hwc->idx;
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	s64 delta;
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	if (idx == INTEL_PMC_IDX_FIXED_BTS)
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		return 0;

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	/*
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	 * Careful: an NMI might modify the previous event value.
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	 *
	 * Our tactic to handle this is to first atomically read and
	 * exchange a new raw count - then add that new-prev delta
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	 * count to the generic event atomically:
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	 */
again:
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	prev_raw_count = local64_read(&hwc->prev_count);
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	rdpmcl(hwc->event_base_rdpmc, new_raw_count);
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	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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					new_raw_count) != prev_raw_count)
		goto again;

	/*
	 * Now we have the new raw value and have updated the prev
	 * timestamp already. We can now calculate the elapsed delta
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	 * (event-)time and add that to the generic event.
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	 *
	 * Careful, not all hw sign-extends above the physical width
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	 * of the count.
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	 */
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	delta = (new_raw_count << shift) - (prev_raw_count << shift);
	delta >>= shift;
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	local64_add(delta, &event->count);
	local64_sub(delta, &hwc->period_left);
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	return new_raw_count;
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}

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/*
 * Find and validate any extra registers to set up.
 */
static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
{
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	struct hw_perf_event_extra *reg;
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	struct extra_reg *er;

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	reg = &event->hw.extra_reg;
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	if (!x86_pmu.extra_regs)
		return 0;

	for (er = x86_pmu.extra_regs; er->msr; er++) {
		if (er->event != (config & er->config_mask))
			continue;
		if (event->attr.config1 & ~er->valid_mask)
			return -EINVAL;
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		reg->idx = er->idx;
		reg->config = event->attr.config1;
		reg->reg = er->msr;
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		break;
	}
	return 0;
}

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static atomic_t active_events;
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static DEFINE_MUTEX(pmc_reserve_mutex);

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#ifdef CONFIG_X86_LOCAL_APIC

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static bool reserve_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
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			goto perfctr_fail;
	}

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
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			goto eventsel_fail;
	}

	return true;

eventsel_fail:
	for (i--; i >= 0; i--)
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		release_evntsel_nmi(x86_pmu_config_addr(i));
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	i = x86_pmu.num_counters;
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perfctr_fail:
	for (i--; i >= 0; i--)
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		release_perfctr_nmi(x86_pmu_event_addr(i));
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	return false;
}

static void release_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		release_perfctr_nmi(x86_pmu_event_addr(i));
		release_evntsel_nmi(x86_pmu_config_addr(i));
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	}
}

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#else

static bool reserve_pmc_hardware(void) { return true; }
static void release_pmc_hardware(void) {}

#endif

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static bool check_hw_exists(void)
{
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	u64 val, val_new = ~0;
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	int i, reg, ret = 0;
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	/*
	 * Check to see if the BIOS enabled any of the counters, if so
	 * complain and bail.
	 */
	for (i = 0; i < x86_pmu.num_counters; i++) {
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		reg = x86_pmu_config_addr(i);
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		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
		if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
			goto bios_fail;
	}

	if (x86_pmu.num_counters_fixed) {
		reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
		for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
			if (val & (0x03 << i*4))
				goto bios_fail;
		}
	}

	/*
	 * Now write a value and read it back to see if it matches,
	 * this is needed to detect certain hardware emulators (qemu/kvm)
	 * that don't trap on the MSR access and always return 0s.
	 */
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	val = 0xabcdUL;
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	reg = x86_pmu_event_addr(0);
	ret = wrmsrl_safe(reg, val);
	ret |= rdmsrl_safe(reg, &val_new);
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	if (ret || val != val_new)
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		goto msr_fail;
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	return true;
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bios_fail:
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	/*
	 * We still allow the PMU driver to operate:
	 */
	printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
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	printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
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	return true;
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msr_fail:
	printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
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	printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new);
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	return false;
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}

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static void hw_perf_event_destroy(struct perf_event *event)
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{
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	if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
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		release_pmc_hardware();
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		release_ds_buffers();
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		mutex_unlock(&pmc_reserve_mutex);
	}
}

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static inline int x86_pmu_initialized(void)
{
	return x86_pmu.handle_irq != NULL;
}

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static inline int
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set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
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{
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	struct perf_event_attr *attr = &event->attr;
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	unsigned int cache_type, cache_op, cache_result;
	u64 config, val;

	config = attr->config;

	cache_type = (config >>  0) & 0xff;
	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
		return -EINVAL;

	cache_op = (config >>  8) & 0xff;
	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
		return -EINVAL;

	cache_result = (config >> 16) & 0xff;
	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
		return -EINVAL;

	val = hw_cache_event_ids[cache_type][cache_op][cache_result];

	if (val == 0)
		return -ENOENT;

	if (val == -1)
		return -EINVAL;

	hwc->config |= val;
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	attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
	return x86_pmu_extra_regs(val, event);
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}

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int x86_setup_perfctr(struct perf_event *event)
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{
	struct perf_event_attr *attr = &event->attr;
	struct hw_perf_event *hwc = &event->hw;
	u64 config;

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	if (!is_sampling_event(event)) {
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		hwc->sample_period = x86_pmu.max_period;
		hwc->last_period = hwc->sample_period;
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		local64_set(&hwc->period_left, hwc->sample_period);
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	} else {
		/*
		 * If we have a PMU initialized but no APIC
		 * interrupts, we cannot sample hardware
		 * events (user-space has to fall back and
		 * sample via a hrtimer based software event):
		 */
		if (!x86_pmu.apic)
			return -EOPNOTSUPP;
	}

	if (attr->type == PERF_TYPE_RAW)
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		return x86_pmu_extra_regs(event->attr.config, event);
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	if (attr->type == PERF_TYPE_HW_CACHE)
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		return set_ext_hw_attr(hwc, event);
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	if (attr->config >= x86_pmu.max_events)
		return -EINVAL;

	/*
	 * The generic map:
	 */
	config = x86_pmu.event_map(attr->config);

	if (config == 0)
		return -ENOENT;

	if (config == -1LL)
		return -EINVAL;

	/*
	 * Branch tracing:
	 */
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	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
	    !attr->freq && hwc->sample_period == 1) {
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		/* BTS is not supported by this architecture. */
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		if (!x86_pmu.bts_active)
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			return -EOPNOTSUPP;

		/* BTS is currently only allowed for user-mode. */
		if (!attr->exclude_kernel)
			return -EOPNOTSUPP;
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		if (!attr->exclude_guest)
			return -EOPNOTSUPP;
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	}

	hwc->config |= config;

	return 0;
}
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/*
 * check that branch_sample_type is compatible with
 * settings needed for precise_ip > 1 which implies
 * using the LBR to capture ALL taken branches at the
 * priv levels of the measurement
 */
static inline int precise_br_compat(struct perf_event *event)
{
	u64 m = event->attr.branch_sample_type;
	u64 b = 0;

	/* must capture all branches */
	if (!(m & PERF_SAMPLE_BRANCH_ANY))
		return 0;

	m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_user)
		b |= PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_kernel)
		b |= PERF_SAMPLE_BRANCH_KERNEL;

	/*
	 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
	 */

	return m == b;
}

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int x86_pmu_hw_config(struct perf_event *event)
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{
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	if (event->attr.precise_ip) {
		int precise = 0;

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		if (!event->attr.exclude_guest)
			return -EOPNOTSUPP;

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		/* Support for constant skid */
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		if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
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			precise++;

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			/* Support for IP fixup */
			if (x86_pmu.lbr_nr)
				precise++;
		}
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		if (event->attr.precise_ip > precise)
			return -EOPNOTSUPP;
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		/*
		 * check that PEBS LBR correction does not conflict with
		 * whatever the user is asking with attr->branch_sample_type
		 */
		if (event->attr.precise_ip > 1) {
			u64 *br_type = &event->attr.branch_sample_type;

			if (has_branch_stack(event)) {
				if (!precise_br_compat(event))
					return -EOPNOTSUPP;

				/* branch_sample_type is compatible */

			} else {
				/*
				 * user did not specify  branch_sample_type
				 *
				 * For PEBS fixups, we capture all
				 * the branches at the priv level of the
				 * event.
				 */
				*br_type = PERF_SAMPLE_BRANCH_ANY;

				if (!event->attr.exclude_user)
					*br_type |= PERF_SAMPLE_BRANCH_USER;

				if (!event->attr.exclude_kernel)
					*br_type |= PERF_SAMPLE_BRANCH_KERNEL;
			}
		}
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	}

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	/*
	 * Generate PMC IRQs:
	 * (keep 'enabled' bit clear for now)
	 */
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	event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
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	/*
	 * Count user and OS events unless requested not to
	 */
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	if (!event->attr.exclude_user)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
	if (!event->attr.exclude_kernel)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
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	if (event->attr.type == PERF_TYPE_RAW)
		event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
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	return x86_setup_perfctr(event);
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}

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/*
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 * Setup the hardware configuration for a given attr_type
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 */
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static int __x86_pmu_event_init(struct perf_event *event)
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{
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	int err;
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	if (!x86_pmu_initialized())
		return -ENODEV;
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	err = 0;
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	if (!atomic_inc_not_zero(&active_events)) {
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		mutex_lock(&pmc_reserve_mutex);
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		if (atomic_read(&active_events) == 0) {
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			if (!reserve_pmc_hardware())
				err = -EBUSY;
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			else
				reserve_ds_buffers();
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		}
		if (!err)
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			atomic_inc(&active_events);
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		mutex_unlock(&pmc_reserve_mutex);
	}
	if (err)
		return err;

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	event->destroy = hw_perf_event_destroy;
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	event->hw.idx = -1;
	event->hw.last_cpu = -1;
	event->hw.last_tag = ~0ULL;
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	/* mark unused */
	event->hw.extra_reg.idx = EXTRA_REG_NONE;
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	event->hw.branch_reg.idx = EXTRA_REG_NONE;

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	return x86_pmu.hw_config(event);
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}

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void x86_pmu_disable_all(void)
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{
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	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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	int idx;

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	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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		u64 val;

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		if (!test_bit(idx, cpuc->active_mask))
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			continue;
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		rdmsrl(x86_pmu_config_addr(idx), val);
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		if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
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			continue;
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		val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
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		wrmsrl(x86_pmu_config_addr(idx), val);
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	}
}

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static void x86_pmu_disable(struct pmu *pmu)
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{
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	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);

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	if (!x86_pmu_initialized())
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		return;
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	if (!cpuc->enabled)
		return;

	cpuc->n_added = 0;
	cpuc->enabled = 0;
	barrier();
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	x86_pmu.disable_all();
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}
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void x86_pmu_enable_all(int added)
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{
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	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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	int idx;

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	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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		struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
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		if (!test_bit(idx, cpuc->active_mask))
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			continue;
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		__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
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	}
}

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static struct pmu pmu;
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static inline int is_x86_event(struct perf_event *event)
{
	return event->pmu == &pmu;
}

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/*
 * Event scheduler state:
 *
 * Assign events iterating over all events and counters, beginning
 * with events with least weights first. Keep the current iterator
 * state in struct sched_state.
 */
struct sched_state {
	int	weight;
	int	event;		/* event index */
	int	counter;	/* counter index */
	int	unassigned;	/* number of events to be assigned left */
	unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
};

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/* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
#define	SCHED_STATES_MAX	2

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struct perf_sched {
	int			max_weight;
	int			max_events;
	struct event_constraint	**constraints;
	struct sched_state	state;
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	int			saved_states;
	struct sched_state	saved[SCHED_STATES_MAX];
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};

/*
 * Initialize interator that runs through all events and counters.
 */
static void perf_sched_init(struct perf_sched *sched, struct event_constraint **c,
			    int num, int wmin, int wmax)
{
	int idx;

	memset(sched, 0, sizeof(*sched));
	sched->max_events	= num;
	sched->max_weight	= wmax;
	sched->constraints	= c;

	for (idx = 0; idx < num; idx++) {
		if (c[idx]->weight == wmin)
			break;
	}

	sched->state.event	= idx;		/* start with min weight */
	sched->state.weight	= wmin;
	sched->state.unassigned	= num;
}

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static void perf_sched_save_state(struct perf_sched *sched)
{
	if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
		return;

	sched->saved[sched->saved_states] = sched->state;
	sched->saved_states++;
}

static bool perf_sched_restore_state(struct perf_sched *sched)
{
	if (!sched->saved_states)
		return false;

	sched->saved_states--;
	sched->state = sched->saved[sched->saved_states];

	/* continue with next counter: */
	clear_bit(sched->state.counter++, sched->state.used);

	return true;
}

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/*
 * Select a counter for the current event to schedule. Return true on
 * success.
 */
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static bool __perf_sched_find_counter(struct perf_sched *sched)
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{
	struct event_constraint *c;
	int idx;

	if (!sched->state.unassigned)
		return false;

	if (sched->state.event >= sched->max_events)
		return false;

	c = sched->constraints[sched->state.event];

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	/* Prefer fixed purpose counters */
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	if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
		idx = INTEL_PMC_IDX_FIXED;
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		for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
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			if (!__test_and_set_bit(idx, sched->state.used))
				goto done;
		}
	}
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	/* Grab the first unused counter starting with idx */
	idx = sched->state.counter;
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	for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
649
		if (!__test_and_set_bit(idx, sched->state.used))
650
			goto done;
651 652
	}

653 654 655 656
	return false;

done:
	sched->state.counter = idx;
657

658 659 660 661 662 663 664 665 666 667 668 669 670
	if (c->overlap)
		perf_sched_save_state(sched);

	return true;
}

static bool perf_sched_find_counter(struct perf_sched *sched)
{
	while (!__perf_sched_find_counter(sched)) {
		if (!perf_sched_restore_state(sched))
			return false;
	}

671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705
	return true;
}

/*
 * Go through all unassigned events and find the next one to schedule.
 * Take events with the least weight first. Return true on success.
 */
static bool perf_sched_next_event(struct perf_sched *sched)
{
	struct event_constraint *c;

	if (!sched->state.unassigned || !--sched->state.unassigned)
		return false;

	do {
		/* next event */
		sched->state.event++;
		if (sched->state.event >= sched->max_events) {
			/* next weight */
			sched->state.event = 0;
			sched->state.weight++;
			if (sched->state.weight > sched->max_weight)
				return false;
		}
		c = sched->constraints[sched->state.event];
	} while (c->weight != sched->state.weight);

	sched->state.counter = 0;	/* start with first counter */

	return true;
}

/*
 * Assign a counter for each event.
 */
Y
Yan, Zheng 已提交
706 707
int perf_assign_events(struct event_constraint **constraints, int n,
			int wmin, int wmax, int *assign)
708 709 710 711 712 713 714 715 716 717 718 719 720 721 722
{
	struct perf_sched sched;

	perf_sched_init(&sched, constraints, n, wmin, wmax);

	do {
		if (!perf_sched_find_counter(&sched))
			break;	/* failed */
		if (assign)
			assign[sched.state.event] = sched.state.counter;
	} while (perf_sched_next_event(&sched));

	return sched.state.unassigned;
}

723
int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
724
{
725
	struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
726
	unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
727
	int i, wmin, wmax, num = 0;
728 729 730 731
	struct hw_perf_event *hwc;

	bitmap_zero(used_mask, X86_PMC_IDX_MAX);

732
	for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
733 734
		c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
		constraints[i] = c;
735 736
		wmin = min(wmin, c->weight);
		wmax = max(wmax, c->weight);
737 738
	}

739 740 741
	/*
	 * fastpath, try to reuse previous register
	 */
742
	for (i = 0; i < n; i++) {
743
		hwc = &cpuc->event_list[i]->hw;
744
		c = constraints[i];
745 746 747 748 749 750

		/* never assigned */
		if (hwc->idx == -1)
			break;

		/* constraint still honored */
751
		if (!test_bit(hwc->idx, c->idxmsk))
752 753 754 755 756 757
			break;

		/* not already used */
		if (test_bit(hwc->idx, used_mask))
			break;

P
Peter Zijlstra 已提交
758
		__set_bit(hwc->idx, used_mask);
759 760 761 762
		if (assign)
			assign[i] = hwc->idx;
	}

763 764 765
	/* slow path */
	if (i != n)
		num = perf_assign_events(constraints, n, wmin, wmax, assign);
766

767 768 769 770 771 772 773 774 775 776
	/*
	 * scheduling failed or is just a simulation,
	 * free resources if necessary
	 */
	if (!assign || num) {
		for (i = 0; i < n; i++) {
			if (x86_pmu.put_event_constraints)
				x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
		}
	}
777
	return num ? -EINVAL : 0;
778 779 780 781 782 783 784 785 786 787 788
}

/*
 * dogrp: true if must collect siblings events (group)
 * returns total number of events and error code
 */
static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
{
	struct perf_event *event;
	int n, max_count;

789
	max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
790 791 792 793 794 795

	/* current number of events already accepted */
	n = cpuc->n_events;

	if (is_x86_event(leader)) {
		if (n >= max_count)
796
			return -EINVAL;
797 798 799 800 801 802 803 804
		cpuc->event_list[n] = leader;
		n++;
	}
	if (!dogrp)
		return n;

	list_for_each_entry(event, &leader->sibling_list, group_entry) {
		if (!is_x86_event(event) ||
805
		    event->state <= PERF_EVENT_STATE_OFF)
806 807 808
			continue;

		if (n >= max_count)
809
			return -EINVAL;
810 811 812 813 814 815 816 817

		cpuc->event_list[n] = event;
		n++;
	}
	return n;
}

static inline void x86_assign_hw_event(struct perf_event *event,
818
				struct cpu_hw_events *cpuc, int i)
819
{
820 821 822 823 824
	struct hw_perf_event *hwc = &event->hw;

	hwc->idx = cpuc->assign[i];
	hwc->last_cpu = smp_processor_id();
	hwc->last_tag = ++cpuc->tags[i];
825

826
	if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
827 828
		hwc->config_base = 0;
		hwc->event_base	= 0;
829
	} else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
830
		hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
831 832
		hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
		hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
833
	} else {
834 835
		hwc->config_base = x86_pmu_config_addr(hwc->idx);
		hwc->event_base  = x86_pmu_event_addr(hwc->idx);
836
		hwc->event_base_rdpmc = hwc->idx;
837 838 839
	}
}

840 841 842 843 844 845 846 847 848
static inline int match_prev_assignment(struct hw_perf_event *hwc,
					struct cpu_hw_events *cpuc,
					int i)
{
	return hwc->idx == cpuc->assign[i] &&
		hwc->last_cpu == smp_processor_id() &&
		hwc->last_tag == cpuc->tags[i];
}

P
Peter Zijlstra 已提交
849
static void x86_pmu_start(struct perf_event *event, int flags);
850

P
Peter Zijlstra 已提交
851
static void x86_pmu_enable(struct pmu *pmu)
852
{
853 854 855
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	struct perf_event *event;
	struct hw_perf_event *hwc;
856
	int i, added = cpuc->n_added;
857

858
	if (!x86_pmu_initialized())
859
		return;
860 861 862 863

	if (cpuc->enabled)
		return;

864
	if (cpuc->n_added) {
865
		int n_running = cpuc->n_events - cpuc->n_added;
866 867 868 869 870 871 872
		/*
		 * apply assignment obtained either from
		 * hw_perf_group_sched_in() or x86_pmu_enable()
		 *
		 * step1: save events moving to new counters
		 * step2: reprogram moved events into new counters
		 */
873
		for (i = 0; i < n_running; i++) {
874 875 876
			event = cpuc->event_list[i];
			hwc = &event->hw;

877 878 879 880 881 882 883 884
			/*
			 * we can avoid reprogramming counter if:
			 * - assigned same counter as last time
			 * - running on same CPU as last time
			 * - no other event has used the counter since
			 */
			if (hwc->idx == -1 ||
			    match_prev_assignment(hwc, cpuc, i))
885 886
				continue;

P
Peter Zijlstra 已提交
887 888 889 890 891 892 893 894
			/*
			 * Ensure we don't accidentally enable a stopped
			 * counter simply because we rescheduled.
			 */
			if (hwc->state & PERF_HES_STOPPED)
				hwc->state |= PERF_HES_ARCH;

			x86_pmu_stop(event, PERF_EF_UPDATE);
895 896 897 898 899 900
		}

		for (i = 0; i < cpuc->n_events; i++) {
			event = cpuc->event_list[i];
			hwc = &event->hw;

901
			if (!match_prev_assignment(hwc, cpuc, i))
902
				x86_assign_hw_event(event, cpuc, i);
903 904
			else if (i < n_running)
				continue;
905

P
Peter Zijlstra 已提交
906 907 908 909
			if (hwc->state & PERF_HES_ARCH)
				continue;

			x86_pmu_start(event, PERF_EF_RELOAD);
910 911 912 913
		}
		cpuc->n_added = 0;
		perf_events_lapic_init();
	}
914 915 916 917

	cpuc->enabled = 1;
	barrier();

918
	x86_pmu.enable_all(added);
919 920
}

921
static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
I
Ingo Molnar 已提交
922

923 924
/*
 * Set the next IRQ period, based on the hwc->period_left value.
925
 * To be called with the event disabled in hw:
926
 */
927
int x86_perf_event_set_period(struct perf_event *event)
I
Ingo Molnar 已提交
928
{
929
	struct hw_perf_event *hwc = &event->hw;
930
	s64 left = local64_read(&hwc->period_left);
931
	s64 period = hwc->sample_period;
932
	int ret = 0, idx = hwc->idx;
933

934
	if (idx == INTEL_PMC_IDX_FIXED_BTS)
935 936
		return 0;

937
	/*
938
	 * If we are way outside a reasonable range then just skip forward:
939 940 941
	 */
	if (unlikely(left <= -period)) {
		left = period;
942
		local64_set(&hwc->period_left, left);
943
		hwc->last_period = period;
944
		ret = 1;
945 946 947 948
	}

	if (unlikely(left <= 0)) {
		left += period;
949
		local64_set(&hwc->period_left, left);
950
		hwc->last_period = period;
951
		ret = 1;
952
	}
953
	/*
954
	 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
955 956 957
	 */
	if (unlikely(left < 2))
		left = 2;
I
Ingo Molnar 已提交
958

959 960 961
	if (left > x86_pmu.max_period)
		left = x86_pmu.max_period;

962
	per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
963 964

	/*
965
	 * The hw event starts counting from this event offset,
966 967
	 * mark it to be able to extra future deltas:
	 */
968
	local64_set(&hwc->prev_count, (u64)-left);
969

970
	wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
971 972 973 974 975 976 977

	/*
	 * Due to erratum on certan cpu we need
	 * a second write to be sure the register
	 * is updated properly
	 */
	if (x86_pmu.perfctr_second_write) {
978
		wrmsrl(hwc->event_base,
979
			(u64)(-left) & x86_pmu.cntval_mask);
980
	}
981

982
	perf_event_update_userpage(event);
983

984
	return ret;
985 986
}

987
void x86_pmu_enable_event(struct perf_event *event)
988
{
T
Tejun Heo 已提交
989
	if (__this_cpu_read(cpu_hw_events.enabled))
990 991
		__x86_pmu_enable_event(&event->hw,
				       ARCH_PERFMON_EVENTSEL_ENABLE);
I
Ingo Molnar 已提交
992 993
}

994
/*
P
Peter Zijlstra 已提交
995
 * Add a single event to the PMU.
996 997 998
 *
 * The event is added to the group of enabled events
 * but only if it can be scehduled with existing events.
999
 */
P
Peter Zijlstra 已提交
1000
static int x86_pmu_add(struct perf_event *event, int flags)
1001 1002
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1003 1004 1005
	struct hw_perf_event *hwc;
	int assign[X86_PMC_IDX_MAX];
	int n, n0, ret;
1006

1007
	hwc = &event->hw;
1008

P
Peter Zijlstra 已提交
1009
	perf_pmu_disable(event->pmu);
1010
	n0 = cpuc->n_events;
1011 1012 1013
	ret = n = collect_events(cpuc, event, false);
	if (ret < 0)
		goto out;
1014

P
Peter Zijlstra 已提交
1015 1016 1017 1018
	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
	if (!(flags & PERF_EF_START))
		hwc->state |= PERF_HES_ARCH;

1019 1020
	/*
	 * If group events scheduling transaction was started,
L
Lucas De Marchi 已提交
1021
	 * skip the schedulability test here, it will be performed
P
Peter Zijlstra 已提交
1022
	 * at commit time (->commit_txn) as a whole
1023
	 */
1024
	if (cpuc->group_flag & PERF_EVENT_TXN)
1025
		goto done_collect;
1026

1027
	ret = x86_pmu.schedule_events(cpuc, n, assign);
1028
	if (ret)
1029
		goto out;
1030 1031 1032 1033 1034
	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));
1035

1036
done_collect:
1037
	cpuc->n_events = n;
1038
	cpuc->n_added += n - n0;
1039
	cpuc->n_txn += n - n0;
1040

1041 1042
	ret = 0;
out:
P
Peter Zijlstra 已提交
1043
	perf_pmu_enable(event->pmu);
1044
	return ret;
I
Ingo Molnar 已提交
1045 1046
}

P
Peter Zijlstra 已提交
1047
static void x86_pmu_start(struct perf_event *event, int flags)
1048
{
P
Peter Zijlstra 已提交
1049 1050 1051
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int idx = event->hw.idx;

P
Peter Zijlstra 已提交
1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063
	if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
		return;

	if (WARN_ON_ONCE(idx == -1))
		return;

	if (flags & PERF_EF_RELOAD) {
		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
		x86_perf_event_set_period(event);
	}

	event->hw.state = 0;
1064

P
Peter Zijlstra 已提交
1065 1066
	cpuc->events[idx] = event;
	__set_bit(idx, cpuc->active_mask);
1067
	__set_bit(idx, cpuc->running);
1068
	x86_pmu.enable(event);
P
Peter Zijlstra 已提交
1069
	perf_event_update_userpage(event);
1070 1071
}

1072
void perf_event_print_debug(void)
I
Ingo Molnar 已提交
1073
{
1074
	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1075
	u64 pebs;
1076
	struct cpu_hw_events *cpuc;
1077
	unsigned long flags;
1078 1079
	int cpu, idx;

1080
	if (!x86_pmu.num_counters)
1081
		return;
I
Ingo Molnar 已提交
1082

1083
	local_irq_save(flags);
I
Ingo Molnar 已提交
1084 1085

	cpu = smp_processor_id();
1086
	cpuc = &per_cpu(cpu_hw_events, cpu);
I
Ingo Molnar 已提交
1087

1088
	if (x86_pmu.version >= 2) {
1089 1090 1091 1092
		rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
		rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
		rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1093
		rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1094 1095 1096 1097 1098 1099

		pr_info("\n");
		pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
		pr_info("CPU#%d: status:     %016llx\n", cpu, status);
		pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
		pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1100
		pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1101
	}
1102
	pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
I
Ingo Molnar 已提交
1103

1104
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1105 1106
		rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
		rdmsrl(x86_pmu_event_addr(idx), pmc_count);
I
Ingo Molnar 已提交
1107

1108
		prev_left = per_cpu(pmc_prev_left[idx], cpu);
I
Ingo Molnar 已提交
1109

1110
		pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
I
Ingo Molnar 已提交
1111
			cpu, idx, pmc_ctrl);
1112
		pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
I
Ingo Molnar 已提交
1113
			cpu, idx, pmc_count);
1114
		pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1115
			cpu, idx, prev_left);
I
Ingo Molnar 已提交
1116
	}
1117
	for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1118 1119
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);

1120
		pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1121 1122
			cpu, idx, pmc_count);
	}
1123
	local_irq_restore(flags);
I
Ingo Molnar 已提交
1124 1125
}

1126
void x86_pmu_stop(struct perf_event *event, int flags)
I
Ingo Molnar 已提交
1127
{
1128
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1129
	struct hw_perf_event *hwc = &event->hw;
I
Ingo Molnar 已提交
1130

P
Peter Zijlstra 已提交
1131 1132 1133 1134 1135 1136
	if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
		x86_pmu.disable(event);
		cpuc->events[hwc->idx] = NULL;
		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
		hwc->state |= PERF_HES_STOPPED;
	}
1137

P
Peter Zijlstra 已提交
1138 1139 1140 1141 1142 1143 1144 1145
	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
		/*
		 * Drain the remaining delta count out of a event
		 * that we are disabling:
		 */
		x86_perf_event_update(event);
		hwc->state |= PERF_HES_UPTODATE;
	}
1146 1147
}

P
Peter Zijlstra 已提交
1148
static void x86_pmu_del(struct perf_event *event, int flags)
1149 1150 1151 1152
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int i;

1153 1154 1155 1156 1157
	/*
	 * If we're called during a txn, we don't need to do anything.
	 * The events never got scheduled and ->cancel_txn will truncate
	 * the event_list.
	 */
1158
	if (cpuc->group_flag & PERF_EVENT_TXN)
1159 1160
		return;

P
Peter Zijlstra 已提交
1161
	x86_pmu_stop(event, PERF_EF_UPDATE);
1162

1163 1164 1165 1166 1167 1168 1169 1170 1171 1172
	for (i = 0; i < cpuc->n_events; i++) {
		if (event == cpuc->event_list[i]) {

			if (x86_pmu.put_event_constraints)
				x86_pmu.put_event_constraints(cpuc, event);

			while (++i < cpuc->n_events)
				cpuc->event_list[i-1] = cpuc->event_list[i];

			--cpuc->n_events;
1173
			break;
1174 1175
		}
	}
1176
	perf_event_update_userpage(event);
I
Ingo Molnar 已提交
1177 1178
}

1179
int x86_pmu_handle_irq(struct pt_regs *regs)
1180
{
1181
	struct perf_sample_data data;
1182 1183
	struct cpu_hw_events *cpuc;
	struct perf_event *event;
V
Vince Weaver 已提交
1184
	int idx, handled = 0;
1185 1186
	u64 val;

1187
	cpuc = &__get_cpu_var(cpu_hw_events);
1188

1189 1190 1191 1192 1193 1194 1195 1196 1197 1198
	/*
	 * Some chipsets need to unmask the LVTPC in a particular spot
	 * inside the nmi handler.  As a result, the unmasking was pushed
	 * into all the nmi handlers.
	 *
	 * This generic handler doesn't seem to have any issues where the
	 * unmasking occurs so it was left at the top.
	 */
	apic_write(APIC_LVTPC, APIC_DM_NMI);

1199
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1200 1201 1202 1203 1204 1205 1206 1207
		if (!test_bit(idx, cpuc->active_mask)) {
			/*
			 * Though we deactivated the counter some cpus
			 * might still deliver spurious interrupts still
			 * in flight. Catch them:
			 */
			if (__test_and_clear_bit(idx, cpuc->running))
				handled++;
1208
			continue;
1209
		}
1210

1211
		event = cpuc->events[idx];
1212

1213
		val = x86_perf_event_update(event);
1214
		if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1215
			continue;
1216

1217
		/*
1218
		 * event overflow
1219
		 */
1220
		handled++;
1221
		perf_sample_data_init(&data, 0, event->hw.last_period);
1222

1223
		if (!x86_perf_event_set_period(event))
1224 1225
			continue;

1226
		if (perf_event_overflow(event, &data, regs))
P
Peter Zijlstra 已提交
1227
			x86_pmu_stop(event, 0);
1228
	}
1229

1230 1231 1232
	if (handled)
		inc_irq_stat(apic_perf_irqs);

1233 1234
	return handled;
}
1235

1236
void perf_events_lapic_init(void)
I
Ingo Molnar 已提交
1237
{
1238
	if (!x86_pmu.apic || !x86_pmu_initialized())
I
Ingo Molnar 已提交
1239
		return;
1240

I
Ingo Molnar 已提交
1241
	/*
1242
	 * Always use NMI for PMU
I
Ingo Molnar 已提交
1243
	 */
1244
	apic_write(APIC_LVTPC, APIC_DM_NMI);
I
Ingo Molnar 已提交
1245 1246 1247
}

static int __kprobes
1248
perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
I
Ingo Molnar 已提交
1249
{
1250
	if (!atomic_read(&active_events))
1251
		return NMI_DONE;
1252

1253
	return x86_pmu.handle_irq(regs);
I
Ingo Molnar 已提交
1254 1255
}

1256 1257
struct event_constraint emptyconstraint;
struct event_constraint unconstrained;
1258

1259 1260 1261 1262
static int __cpuinit
x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
{
	unsigned int cpu = (long)hcpu;
1263
	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1264
	int ret = NOTIFY_OK;
1265 1266 1267

	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_UP_PREPARE:
1268
		cpuc->kfree_on_online = NULL;
1269
		if (x86_pmu.cpu_prepare)
1270
			ret = x86_pmu.cpu_prepare(cpu);
1271 1272 1273
		break;

	case CPU_STARTING:
1274 1275
		if (x86_pmu.attr_rdpmc)
			set_in_cr4(X86_CR4_PCE);
1276 1277 1278 1279
		if (x86_pmu.cpu_starting)
			x86_pmu.cpu_starting(cpu);
		break;

1280 1281 1282 1283
	case CPU_ONLINE:
		kfree(cpuc->kfree_on_online);
		break;

1284 1285 1286 1287 1288
	case CPU_DYING:
		if (x86_pmu.cpu_dying)
			x86_pmu.cpu_dying(cpu);
		break;

1289
	case CPU_UP_CANCELED:
1290 1291 1292 1293 1294 1295 1296 1297 1298
	case CPU_DEAD:
		if (x86_pmu.cpu_dead)
			x86_pmu.cpu_dead(cpu);
		break;

	default:
		break;
	}

1299
	return ret;
1300 1301
}

1302 1303 1304 1305 1306 1307 1308 1309 1310 1311
static void __init pmu_check_apic(void)
{
	if (cpu_has_apic)
		return;

	x86_pmu.apic = 0;
	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
	pr_info("no hardware sampling interrupt available.\n");
}

1312 1313 1314 1315 1316
static struct attribute_group x86_pmu_format_group = {
	.name = "format",
	.attrs = NULL,
};

1317
static int __init init_hw_perf_events(void)
1318
{
1319
	struct x86_pmu_quirk *quirk;
1320 1321
	int err;

1322
	pr_info("Performance Events: ");
1323

1324 1325
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_INTEL:
1326
		err = intel_pmu_init();
1327
		break;
1328
	case X86_VENDOR_AMD:
1329
		err = amd_pmu_init();
1330
		break;
1331
	default:
1332
		return 0;
1333
	}
1334
	if (err != 0) {
1335
		pr_cont("no PMU driver, software events only.\n");
1336
		return 0;
1337
	}
1338

1339 1340
	pmu_check_apic();

1341
	/* sanity check that the hardware exists or is emulated */
1342
	if (!check_hw_exists())
1343
		return 0;
1344

1345
	pr_cont("%s PMU driver.\n", x86_pmu.name);
1346

1347 1348
	for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
		quirk->func();
1349

1350 1351
	if (!x86_pmu.intel_ctrl)
		x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
I
Ingo Molnar 已提交
1352

1353
	perf_events_lapic_init();
1354
	register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1355

1356
	unconstrained = (struct event_constraint)
1357
		__EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1358
				   0, x86_pmu.num_counters, 0);
1359

1360
	x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1361
	x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1362

I
Ingo Molnar 已提交
1363
	pr_info("... version:                %d\n",     x86_pmu.version);
1364 1365 1366
	pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
	pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
	pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
I
Ingo Molnar 已提交
1367
	pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1368
	pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1369
	pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1370

P
Peter Zijlstra 已提交
1371
	perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1372
	perf_cpu_notifier(x86_pmu_notifier);
1373 1374

	return 0;
I
Ingo Molnar 已提交
1375
}
1376
early_initcall(init_hw_perf_events);
I
Ingo Molnar 已提交
1377

1378
static inline void x86_pmu_read(struct perf_event *event)
1379
{
1380
	x86_perf_event_update(event);
1381 1382
}

1383 1384 1385 1386 1387
/*
 * Start group events scheduling transaction
 * Set the flag to make pmu::enable() not perform the
 * schedulability test, it will be performed at commit time
 */
P
Peter Zijlstra 已提交
1388
static void x86_pmu_start_txn(struct pmu *pmu)
1389
{
P
Peter Zijlstra 已提交
1390
	perf_pmu_disable(pmu);
T
Tejun Heo 已提交
1391 1392
	__this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
	__this_cpu_write(cpu_hw_events.n_txn, 0);
1393 1394 1395 1396 1397 1398 1399
}

/*
 * Stop group events scheduling transaction
 * Clear the flag and pmu::enable() will perform the
 * schedulability test.
 */
P
Peter Zijlstra 已提交
1400
static void x86_pmu_cancel_txn(struct pmu *pmu)
1401
{
T
Tejun Heo 已提交
1402
	__this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1403 1404 1405
	/*
	 * Truncate the collected events.
	 */
T
Tejun Heo 已提交
1406 1407
	__this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
	__this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
P
Peter Zijlstra 已提交
1408
	perf_pmu_enable(pmu);
1409 1410 1411 1412 1413 1414 1415
}

/*
 * Commit group events scheduling transaction
 * Perform the group schedulability test as a whole
 * Return 0 if success
 */
P
Peter Zijlstra 已提交
1416
static int x86_pmu_commit_txn(struct pmu *pmu)
1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	int assign[X86_PMC_IDX_MAX];
	int n, ret;

	n = cpuc->n_events;

	if (!x86_pmu_initialized())
		return -EAGAIN;

	ret = x86_pmu.schedule_events(cpuc, n, assign);
	if (ret)
		return ret;

	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));

1437
	cpuc->group_flag &= ~PERF_EVENT_TXN;
P
Peter Zijlstra 已提交
1438
	perf_pmu_enable(pmu);
1439 1440
	return 0;
}
1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469
/*
 * a fake_cpuc is used to validate event groups. Due to
 * the extra reg logic, we need to also allocate a fake
 * per_core and per_cpu structure. Otherwise, group events
 * using extra reg may conflict without the kernel being
 * able to catch this when the last event gets added to
 * the group.
 */
static void free_fake_cpuc(struct cpu_hw_events *cpuc)
{
	kfree(cpuc->shared_regs);
	kfree(cpuc);
}

static struct cpu_hw_events *allocate_fake_cpuc(void)
{
	struct cpu_hw_events *cpuc;
	int cpu = raw_smp_processor_id();

	cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
	if (!cpuc)
		return ERR_PTR(-ENOMEM);

	/* only needed, if we have extra_regs */
	if (x86_pmu.extra_regs) {
		cpuc->shared_regs = allocate_shared_regs(cpu);
		if (!cpuc->shared_regs)
			goto error;
	}
1470
	cpuc->is_fake = 1;
1471 1472 1473 1474 1475
	return cpuc;
error:
	free_fake_cpuc(cpuc);
	return ERR_PTR(-ENOMEM);
}
1476

1477 1478 1479 1480 1481 1482 1483 1484 1485
/*
 * validate that we can schedule this event
 */
static int validate_event(struct perf_event *event)
{
	struct cpu_hw_events *fake_cpuc;
	struct event_constraint *c;
	int ret = 0;

1486 1487 1488
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1489 1490 1491 1492

	c = x86_pmu.get_event_constraints(fake_cpuc, event);

	if (!c || !c->weight)
1493
		ret = -EINVAL;
1494 1495 1496 1497

	if (x86_pmu.put_event_constraints)
		x86_pmu.put_event_constraints(fake_cpuc, event);

1498
	free_fake_cpuc(fake_cpuc);
1499 1500 1501 1502

	return ret;
}

1503 1504 1505 1506
/*
 * validate a single event group
 *
 * validation include:
1507 1508 1509
 *	- check events are compatible which each other
 *	- events do not compete for the same counter
 *	- number of events <= number of counters
1510 1511 1512 1513
 *
 * validation ensures the group can be loaded onto the
 * PMU if it was the only group available.
 */
1514 1515
static int validate_group(struct perf_event *event)
{
1516
	struct perf_event *leader = event->group_leader;
1517
	struct cpu_hw_events *fake_cpuc;
1518
	int ret = -EINVAL, n;
1519

1520 1521 1522
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1523 1524 1525 1526 1527 1528
	/*
	 * the event is not yet connected with its
	 * siblings therefore we must first collect
	 * existing siblings, then add the new event
	 * before we can simulate the scheduling
	 */
1529
	n = collect_events(fake_cpuc, leader, true);
1530
	if (n < 0)
1531
		goto out;
1532

1533 1534
	fake_cpuc->n_events = n;
	n = collect_events(fake_cpuc, event, false);
1535
	if (n < 0)
1536
		goto out;
1537

1538
	fake_cpuc->n_events = n;
1539

1540
	ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1541 1542

out:
1543
	free_fake_cpuc(fake_cpuc);
1544
	return ret;
1545 1546
}

1547
static int x86_pmu_event_init(struct perf_event *event)
I
Ingo Molnar 已提交
1548
{
P
Peter Zijlstra 已提交
1549
	struct pmu *tmp;
I
Ingo Molnar 已提交
1550 1551
	int err;

1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562
	switch (event->attr.type) {
	case PERF_TYPE_RAW:
	case PERF_TYPE_HARDWARE:
	case PERF_TYPE_HW_CACHE:
		break;

	default:
		return -ENOENT;
	}

	err = __x86_pmu_event_init(event);
1563
	if (!err) {
1564 1565 1566 1567 1568 1569 1570 1571
		/*
		 * we temporarily connect event to its pmu
		 * such that validate_group() can classify
		 * it as an x86 event using is_x86_event()
		 */
		tmp = event->pmu;
		event->pmu = &pmu;

1572 1573
		if (event->group_leader != event)
			err = validate_group(event);
1574 1575
		else
			err = validate_event(event);
1576 1577

		event->pmu = tmp;
1578
	}
1579
	if (err) {
1580 1581
		if (event->destroy)
			event->destroy(event);
1582
	}
I
Ingo Molnar 已提交
1583

1584
	return err;
I
Ingo Molnar 已提交
1585
}
1586

1587 1588 1589 1590
static int x86_pmu_event_idx(struct perf_event *event)
{
	int idx = event->hw.idx;

1591 1592 1593
	if (!x86_pmu.attr_rdpmc)
		return 0;

1594 1595
	if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
		idx -= INTEL_PMC_IDX_FIXED;
1596 1597 1598 1599 1600 1601
		idx |= 1 << 30;
	}

	return idx + 1;
}

1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622
static ssize_t get_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      char *buf)
{
	return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
}

static void change_rdpmc(void *info)
{
	bool enable = !!(unsigned long)info;

	if (enable)
		set_in_cr4(X86_CR4_PCE);
	else
		clear_in_cr4(X86_CR4_PCE);
}

static ssize_t set_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      const char *buf, size_t count)
{
1623 1624 1625 1626 1627 1628
	unsigned long val;
	ssize_t ret;

	ret = kstrtoul(buf, 0, &val);
	if (ret)
		return ret;
1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650

	if (!!val != !!x86_pmu.attr_rdpmc) {
		x86_pmu.attr_rdpmc = !!val;
		smp_call_function(change_rdpmc, (void *)val, 1);
	}

	return count;
}

static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);

static struct attribute *x86_pmu_attrs[] = {
	&dev_attr_rdpmc.attr,
	NULL,
};

static struct attribute_group x86_pmu_attr_group = {
	.attrs = x86_pmu_attrs,
};

static const struct attribute_group *x86_pmu_attr_groups[] = {
	&x86_pmu_attr_group,
1651
	&x86_pmu_format_group,
1652 1653 1654
	NULL,
};

1655 1656 1657 1658 1659 1660
static void x86_pmu_flush_branch_stack(void)
{
	if (x86_pmu.flush_branch_stack)
		x86_pmu.flush_branch_stack();
}

1661 1662 1663 1664 1665 1666 1667
void perf_check_microcode(void)
{
	if (x86_pmu.check_microcode)
		x86_pmu.check_microcode();
}
EXPORT_SYMBOL_GPL(perf_check_microcode);

1668
static struct pmu pmu = {
1669 1670
	.pmu_enable		= x86_pmu_enable,
	.pmu_disable		= x86_pmu_disable,
P
Peter Zijlstra 已提交
1671

1672
	.attr_groups		= x86_pmu_attr_groups,
1673

1674
	.event_init		= x86_pmu_event_init,
P
Peter Zijlstra 已提交
1675

1676 1677 1678 1679 1680
	.add			= x86_pmu_add,
	.del			= x86_pmu_del,
	.start			= x86_pmu_start,
	.stop			= x86_pmu_stop,
	.read			= x86_pmu_read,
P
Peter Zijlstra 已提交
1681

1682 1683 1684
	.start_txn		= x86_pmu_start_txn,
	.cancel_txn		= x86_pmu_cancel_txn,
	.commit_txn		= x86_pmu_commit_txn,
1685

1686
	.event_idx		= x86_pmu_event_idx,
1687
	.flush_branch_stack	= x86_pmu_flush_branch_stack,
1688 1689
};

1690
void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1691
{
1692 1693 1694 1695
	userpg->cap_usr_time = 0;
	userpg->cap_usr_rdpmc = x86_pmu.attr_rdpmc;
	userpg->pmc_width = x86_pmu.cntval_bits;

1696 1697 1698 1699 1700 1701
	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
		return;

	if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
		return;

1702
	userpg->cap_usr_time = 1;
1703 1704 1705 1706 1707
	userpg->time_mult = this_cpu_read(cyc2ns);
	userpg->time_shift = CYC2NS_SCALE_FACTOR;
	userpg->time_offset = this_cpu_read(cyc2ns_offset) - now;
}

1708 1709 1710 1711 1712 1713
/*
 * callchain support
 */

static int backtrace_stack(void *data, char *name)
{
1714
	return 0;
1715 1716 1717 1718 1719 1720
}

static void backtrace_address(void *data, unsigned long addr, int reliable)
{
	struct perf_callchain_entry *entry = data;

1721
	perf_callchain_store(entry, addr);
1722 1723 1724 1725 1726
}

static const struct stacktrace_ops backtrace_ops = {
	.stack			= backtrace_stack,
	.address		= backtrace_address,
1727
	.walk_stack		= print_context_stack_bp,
1728 1729
};

1730 1731
void
perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1732
{
1733 1734
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
1735
		return;
1736 1737
	}

1738
	perf_callchain_store(entry, regs->ip);
1739

1740
	dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1741 1742
}

1743 1744 1745 1746 1747 1748
static inline int
valid_user_frame(const void __user *fp, unsigned long size)
{
	return (__range_not_ok(fp, size, TASK_SIZE) == 0);
}

1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771
static unsigned long get_segment_base(unsigned int segment)
{
	struct desc_struct *desc;
	int idx = segment >> 3;

	if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
		if (idx > LDT_ENTRIES)
			return 0;

		if (idx > current->active_mm->context.size)
			return 0;

		desc = current->active_mm->context.ldt;
	} else {
		if (idx > GDT_ENTRIES)
			return 0;

		desc = __this_cpu_ptr(&gdt_page.gdt[0]);
	}

	return get_desc_base(desc + idx);
}

1772
#ifdef CONFIG_COMPAT
H
H. Peter Anvin 已提交
1773 1774 1775

#include <asm/compat.h>

1776 1777
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1778
{
1779
	/* 32-bit process in 64-bit kernel. */
1780
	unsigned long ss_base, cs_base;
1781 1782
	struct stack_frame_ia32 frame;
	const void __user *fp;
1783

1784 1785 1786
	if (!test_thread_flag(TIF_IA32))
		return 0;

1787 1788 1789 1790
	cs_base = get_segment_base(regs->cs);
	ss_base = get_segment_base(regs->ss);

	fp = compat_ptr(ss_base + regs->bp);
1791 1792 1793 1794 1795 1796 1797 1798
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
		unsigned long bytes;
		frame.next_frame     = 0;
		frame.return_address = 0;

		bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
		if (bytes != sizeof(frame))
			break;
1799

1800 1801 1802
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

1803 1804
		perf_callchain_store(entry, cs_base + frame.return_address);
		fp = compat_ptr(ss_base + frame.next_frame);
1805 1806
	}
	return 1;
1807
}
1808 1809 1810 1811 1812 1813 1814
#else
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
{
    return 0;
}
#endif
1815

1816 1817
void
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1818 1819 1820 1821
{
	struct stack_frame frame;
	const void __user *fp;

1822 1823
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
1824
		return;
1825
	}
1826

1827 1828 1829 1830 1831 1832
	/*
	 * We don't know what to do with VM86 stacks.. ignore them for now.
	 */
	if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
		return;

1833
	fp = (void __user *)regs->bp;
1834

1835
	perf_callchain_store(entry, regs->ip);
1836

1837 1838 1839
	if (!current->mm)
		return;

1840 1841 1842
	if (perf_callchain_user32(regs, entry))
		return;

1843
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
1844
		unsigned long bytes;
1845
		frame.next_frame	     = NULL;
1846 1847
		frame.return_address = 0;

1848 1849
		bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
		if (bytes != sizeof(frame))
1850 1851
			break;

1852 1853 1854
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

1855
		perf_callchain_store(entry, frame.return_address);
1856
		fp = frame.next_frame;
1857 1858 1859
	}
}

1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873
/*
 * Deal with code segment offsets for the various execution modes:
 *
 *   VM86 - the good olde 16 bit days, where the linear address is
 *          20 bits and we use regs->ip + 0x10 * regs->cs.
 *
 *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
 *          to figure out what the 32bit base address is.
 *
 *    X32 - has TIF_X32 set, but is running in x86_64
 *
 * X86_64 - CS,DS,SS,ES are all zero based.
 */
static unsigned long code_segment_base(struct pt_regs *regs)
1874
{
1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896
	/*
	 * If we are in VM86 mode, add the segment offset to convert to a
	 * linear address.
	 */
	if (regs->flags & X86_VM_MASK)
		return 0x10 * regs->cs;

	/*
	 * For IA32 we look at the GDT/LDT segment base to convert the
	 * effective IP to a linear address.
	 */
#ifdef CONFIG_X86_32
	if (user_mode(regs) && regs->cs != __USER_CS)
		return get_segment_base(regs->cs);
#else
	if (test_thread_flag(TIF_IA32)) {
		if (user_mode(regs) && regs->cs != __USER32_CS)
			return get_segment_base(regs->cs);
	}
#endif
	return 0;
}
1897

1898 1899
unsigned long perf_instruction_pointer(struct pt_regs *regs)
{
1900
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1901
		return perf_guest_cbs->get_guest_ip();
1902

1903
	return regs->ip + code_segment_base(regs);
1904 1905 1906 1907 1908
}

unsigned long perf_misc_flags(struct pt_regs *regs)
{
	int misc = 0;
1909

1910
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1911 1912 1913 1914 1915
		if (perf_guest_cbs->is_user_mode())
			misc |= PERF_RECORD_MISC_GUEST_USER;
		else
			misc |= PERF_RECORD_MISC_GUEST_KERNEL;
	} else {
1916
		if (user_mode(regs))
1917 1918 1919 1920 1921
			misc |= PERF_RECORD_MISC_USER;
		else
			misc |= PERF_RECORD_MISC_KERNEL;
	}

1922
	if (regs->flags & PERF_EFLAGS_EXACT)
P
Peter Zijlstra 已提交
1923
		misc |= PERF_RECORD_MISC_EXACT_IP;
1924 1925 1926

	return misc;
}
1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938

void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
{
	cap->version		= x86_pmu.version;
	cap->num_counters_gp	= x86_pmu.num_counters;
	cap->num_counters_fixed	= x86_pmu.num_counters_fixed;
	cap->bit_width_gp	= x86_pmu.cntval_bits;
	cap->bit_width_fixed	= x86_pmu.cntval_bits;
	cap->events_mask	= (unsigned int)x86_pmu.events_maskl;
	cap->events_mask_len	= x86_pmu.events_mask_len;
}
EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);