i915_irq.c 127.3 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/circ_buf.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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/**
 * DOC: interrupt handling
 *
 * These functions provide the basic support for enabling and disabling the
 * interrupt handling support. There's a lot more functionality in i915_irq.c
 * and related files, but that will be described in separate chapters.
 */

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static const u32 hpd_ibx[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

static const u32 hpd_cpt[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

static const u32 hpd_mask_i915[] = {
	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

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static const u32 hpd_status_g4x[] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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/* IIR can theoretically queue up two events. Be paranoid. */
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#define GEN8_IRQ_RESET_NDX(type, which) do { \
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	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
	I915_WRITE(GEN8_##type##_IER(which), 0); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
} while (0)

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#define GEN5_IRQ_RESET(type) do { \
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	I915_WRITE(type##IMR, 0xffffffff); \
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	POSTING_READ(type##IMR); \
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	I915_WRITE(type##IER, 0); \
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	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
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} while (0)

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/*
 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 */
#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
	u32 val = I915_READ(reg); \
	if (val) { \
		WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
		     (reg), val); \
		I915_WRITE((reg), 0xffffffff); \
		POSTING_READ(reg); \
		I915_WRITE((reg), 0xffffffff); \
		POSTING_READ(reg); \
	} \
} while (0)

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#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
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	GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
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	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
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	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
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} while (0)

#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
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	GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
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	I915_WRITE(type##IER, (ier_val)); \
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	I915_WRITE(type##IMR, (imr_val)); \
	POSTING_READ(type##IMR); \
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} while (0)

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static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

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/* For display hotplug interrupt */
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void
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ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	if ((dev_priv->irq_mask & mask) != 0) {
		dev_priv->irq_mask &= ~mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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void
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ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	if ((dev_priv->irq_mask & mask) != mask) {
		dev_priv->irq_mask |= mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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/**
 * ilk_update_gt_irq - update GTIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	dev_priv->gt_irq_mask &= ~interrupt_mask;
	dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}

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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, mask);
}

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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, 0);
}

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static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
}

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static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
}

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static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
}

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/**
  * snb_update_pm_irq - update GEN6_PMIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
  */
static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
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	uint32_t new_val;
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	assert_spin_locked(&dev_priv->irq_lock);

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	new_val = dev_priv->pm_irq_mask;
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	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

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	if (new_val != dev_priv->pm_irq_mask) {
		dev_priv->pm_irq_mask = new_val;
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		I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
		POSTING_READ(gen6_pm_imr(dev_priv));
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	}
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}

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void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

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	snb_update_pm_irq(dev_priv, mask, mask);
}

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static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
				  uint32_t mask)
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{
	snb_update_pm_irq(dev_priv, mask, 0);
}

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void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	__gen6_disable_pm_irq(dev_priv, mask);
}

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void gen6_reset_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t reg = gen6_pm_iir(dev_priv);

	spin_lock_irq(&dev_priv->irq_lock);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	POSTING_READ(reg);
	spin_unlock_irq(&dev_priv->irq_lock);
}

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void gen6_enable_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	spin_lock_irq(&dev_priv->irq_lock);
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	WARN_ON(dev_priv->rps.pm_iir);
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	WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
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	dev_priv->rps.interrupts_enabled = true;
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
				dev_priv->pm_rps_events);
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	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);
}

void gen6_disable_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

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	spin_lock_irq(&dev_priv->irq_lock);
	dev_priv->rps.interrupts_enabled = false;
	spin_unlock_irq(&dev_priv->irq_lock);

	cancel_work_sync(&dev_priv->rps.work);

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	spin_lock_irq(&dev_priv->irq_lock);

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	I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ?
		   ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0);
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	__gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
				~dev_priv->pm_rps_events);
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	I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
	I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
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	dev_priv->rps.pm_iir = 0;

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	spin_unlock_irq(&dev_priv->irq_lock);
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}

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/**
 * ibx_display_interrupt_update - update SDEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask)
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{
	uint32_t sdeimr = I915_READ(SDEIMR);
	sdeimr &= ~interrupt_mask;
	sdeimr |= (~enabled_irq_mask & interrupt_mask);

	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	I915_WRITE(SDEIMR, sdeimr);
	POSTING_READ(SDEIMR);
}
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static void
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__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		       u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

	if ((pipestat & enable_mask) == enable_mask)
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		return;

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	dev_priv->pipestat_irq_mask[pipe] |= status_mask;

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	/* Enable the interrupt, clear any pending status */
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	pipestat |= enable_mask | status_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static void
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__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		        u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

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	if ((pipestat & enable_mask) == 0)
		return;

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	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;

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	pipestat &= ~enable_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
{
	u32 enable_mask = status_mask << 16;

	/*
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	 * On pipe A we don't support the PSR interrupt yet,
	 * on pipe B and C the same bit MBZ.
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	 */
	if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
		return 0;
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	/*
	 * On pipe B and C we don't support the PSR interrupt yet, on pipe
	 * A the same bit is for perf counters which we don't use either.
	 */
	if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
		return 0;
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	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
			 SPRITE0_FLIP_DONE_INT_EN_VLV |
			 SPRITE1_FLIP_DONE_INT_EN_VLV);
	if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
	if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;

	return enable_mask;
}

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void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		     u32 status_mask)
{
	u32 enable_mask;

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	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
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	__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

void
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		      u32 status_mask)
{
	u32 enable_mask;

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	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
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	__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

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/**
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 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
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 */
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static void i915_enable_asle_pipestat(struct drm_device *dev)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
		return;

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	spin_lock_irq(&dev_priv->irq_lock);
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	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
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	if (INTEL_INFO(dev)->gen >= 4)
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		i915_enable_pipestat(dev_priv, PIPE_A,
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				     PIPE_LEGACY_BLC_EVENT_STATUS);
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	spin_unlock_irq(&dev_priv->irq_lock);
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}

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/**
 * i915_pipe_enabled - check if a pipe is enabled
 * @dev: DRM device
 * @pipe: pipe to check
 *
 * Reading certain registers when the pipe is disabled can hang the chip.
 * Use this routine to make sure the PLL is running and the pipe is active
 * before reading such registers if unsure.
 */
static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		/* Locking is horribly broken here, but whatever. */
		struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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		return intel_crtc->active;
	} else {
		return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
	}
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}

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/*
 * This timing diagram depicts the video signal in and
 * around the vertical blanking period.
 *
 * Assumptions about the fictitious mode used in this example:
 *  vblank_start >= 3
 *  vsync_start = vblank_start + 1
 *  vsync_end = vblank_start + 2
 *  vtotal = vblank_start + 3
 *
 *           start of vblank:
 *           latch double buffered registers
 *           increment frame counter (ctg+)
 *           generate start of vblank interrupt (gen4+)
 *           |
 *           |          frame start:
 *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 *           |          may be shifted forward 1-3 extra lines via PIPECONF
 *           |          |
 *           |          |  start of vsync:
 *           |          |  generate vsync interrupt
 *           |          |  |
 * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 * ----va---> <-----------------vb--------------------> <--------va-------------
 *       |          |       <----vs----->                     |
 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 *       |          |                                         |
 *       last visible pixel                                   first visible pixel
 *                  |                                         increment frame counter (gen3/4)
 *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 *
 * x  = horizontal active
 * _  = horizontal blanking
 * hs = horizontal sync
 * va = vertical active
 * vb = vertical blanking
 * vs = vertical sync
 * vbs = vblank_start (number)
 *
 * Summary:
 * - most events happen at the start of horizontal sync
 * - frame start happens at the start of horizontal blank, 1-4 lines
 *   (depending on PIPECONF settings) after the start of vblank
 * - gen3/4 pixel and frame counter are synchronized with the start
 *   of horizontal active on the first line of vertical active
 */

548 549 550 551 552 553
static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
{
	/* Gen2 doesn't have a hardware frame counter */
	return 0;
}

554 555 556
/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
557
static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
558
{
559
	struct drm_i915_private *dev_priv = dev->dev_private;
560 561
	unsigned long high_frame;
	unsigned long low_frame;
562
	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
563 564

	if (!i915_pipe_enabled(dev, pipe)) {
565
		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
566
				"pipe %c\n", pipe_name(pipe));
567 568 569
		return 0;
	}

570 571 572 573 574 575
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		struct intel_crtc *intel_crtc =
			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		const struct drm_display_mode *mode =
			&intel_crtc->config.adjusted_mode;

576 577 578 579 580
		htotal = mode->crtc_htotal;
		hsync_start = mode->crtc_hsync_start;
		vbl_start = mode->crtc_vblank_start;
		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
			vbl_start = DIV_ROUND_UP(vbl_start, 2);
581
	} else {
582
		enum transcoder cpu_transcoder = (enum transcoder) pipe;
583 584

		htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
585
		hsync_start = (I915_READ(HSYNC(cpu_transcoder))  & 0x1fff) + 1;
586
		vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
587 588 589
		if ((I915_READ(PIPECONF(cpu_transcoder)) &
		     PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
			vbl_start = DIV_ROUND_UP(vbl_start, 2);
590 591
	}

592 593 594 595 596 597
	/* Convert to pixel count */
	vbl_start *= htotal;

	/* Start of vblank event occurs at start of hsync */
	vbl_start -= htotal - hsync_start;

598 599
	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
600

601 602 603 604 605 606
	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
607
		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
608
		low   = I915_READ(low_frame);
609
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
610 611
	} while (high1 != high2);

612
	high1 >>= PIPE_FRAME_HIGH_SHIFT;
613
	pixel = low & PIPE_PIXEL_MASK;
614
	low >>= PIPE_FRAME_LOW_SHIFT;
615 616 617 618 619 620

	/*
	 * The frame counter increments at beginning of active.
	 * Cook up a vblank counter by also checking the pixel
	 * counter against vblank start.
	 */
621
	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
622 623
}

624
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
625
{
626
	struct drm_i915_private *dev_priv = dev->dev_private;
627
	int reg = PIPE_FRMCOUNT_GM45(pipe);
628 629

	if (!i915_pipe_enabled(dev, pipe)) {
630
		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
631
				 "pipe %c\n", pipe_name(pipe));
632 633 634 635 636 637
		return 0;
	}

	return I915_READ(reg);
}

638 639 640
/* raw reads, only for fast reads of display block, no need for forcewake etc. */
#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))

641 642 643 644 645 646
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
	enum pipe pipe = crtc->pipe;
647
	int position, vtotal;
648

649
	vtotal = mode->crtc_vtotal;
650 651 652 653 654 655 656 657 658
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vtotal /= 2;

	if (IS_GEN2(dev))
		position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
	else
		position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;

	/*
659 660
	 * See update_scanline_offset() for the details on the
	 * scanline_offset adjustment.
661
	 */
662
	return (position + crtc->scanline_offset) % vtotal;
663 664
}

665
static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
666 667
				    unsigned int flags, int *vpos, int *hpos,
				    ktime_t *stime, ktime_t *etime)
668
{
669 670 671 672
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
673
	int position;
674
	int vbl_start, vbl_end, hsync_start, htotal, vtotal;
675 676
	bool in_vbl = true;
	int ret = 0;
677
	unsigned long irqflags;
678

679
	if (!intel_crtc->active) {
680
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
681
				 "pipe %c\n", pipe_name(pipe));
682 683 684
		return 0;
	}

685
	htotal = mode->crtc_htotal;
686
	hsync_start = mode->crtc_hsync_start;
687 688 689
	vtotal = mode->crtc_vtotal;
	vbl_start = mode->crtc_vblank_start;
	vbl_end = mode->crtc_vblank_end;
690

691 692 693 694 695 696
	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
		vbl_end /= 2;
		vtotal /= 2;
	}

697 698
	ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

699 700 701 702 703 704
	/*
	 * Lock uncore.lock, as we will do multiple timing critical raw
	 * register reads, potentially with preemption disabled, so the
	 * following code must not block on uncore.lock.
	 */
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
705

706 707 708 709 710 711
	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */

	/* Get optional system timestamp before query. */
	if (stime)
		*stime = ktime_get();

712
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
713 714 715
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
716
		position = __intel_get_crtc_scanline(intel_crtc);
717 718 719 720 721
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
722
		position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
723

724 725 726 727
		/* convert to pixel counts */
		vbl_start *= htotal;
		vbl_end *= htotal;
		vtotal *= htotal;
728

729 730 731 732 733 734 735 736 737 738 739 740
		/*
		 * In interlaced modes, the pixel counter counts all pixels,
		 * so one field will have htotal more pixels. In order to avoid
		 * the reported position from jumping backwards when the pixel
		 * counter is beyond the length of the shorter field, just
		 * clamp the position the length of the shorter field. This
		 * matches how the scanline counter based position works since
		 * the scanline counter doesn't count the two half lines.
		 */
		if (position >= vtotal)
			position = vtotal - 1;

741 742 743 744 745 746 747 748 749 750
		/*
		 * Start of vblank interrupt is triggered at start of hsync,
		 * just prior to the first active line of vblank. However we
		 * consider lines to start at the leading edge of horizontal
		 * active. So, should we get here before we've crossed into
		 * the horizontal active of the first line in vblank, we would
		 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
		 * always add htotal-hsync_start to the current pixel position.
		 */
		position = (position + htotal - hsync_start) % vtotal;
751 752
	}

753 754 755 756 757 758 759 760
	/* Get optional system timestamp after query. */
	if (etime)
		*etime = ktime_get();

	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

761 762 763 764 765 766 767 768 769 770 771 772
	in_vbl = position >= vbl_start && position < vbl_end;

	/*
	 * While in vblank, position will be negative
	 * counting up towards 0 at vbl_end. And outside
	 * vblank, position will be positive counting
	 * up since vbl_end.
	 */
	if (position >= vbl_start)
		position -= vbl_end;
	else
		position += vtotal - vbl_end;
773

774
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
775 776 777 778 779 780
		*vpos = position;
		*hpos = 0;
	} else {
		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}
781 782 783

	/* In vblank? */
	if (in_vbl)
784
		ret |= DRM_SCANOUTPOS_IN_VBLANK;
785 786 787 788

	return ret;
}

789 790 791 792 793 794 795 796 797 798 799 800 801
int intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
	unsigned long irqflags;
	int position;

	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
	position = __intel_get_crtc_scanline(crtc);
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

	return position;
}

802
static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
803 804 805 806
			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
807
	struct drm_crtc *crtc;
808

809
	if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
810
		DRM_ERROR("Invalid crtc %d\n", pipe);
811 812 813 814
		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
815 816 817 818 819 820 821 822 823 824
	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
		DRM_ERROR("Invalid crtc %d\n", pipe);
		return -EINVAL;
	}

	if (!crtc->enabled) {
		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
		return -EBUSY;
	}
825 826

	/* Helper routine in DRM core does all the work: */
827 828
	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
829 830
						     crtc,
						     &to_intel_crtc(crtc)->config.adjusted_mode);
831 832
}

833 834
static bool intel_hpd_irq_event(struct drm_device *dev,
				struct drm_connector *connector)
835 836 837 838 839 840 841
{
	enum drm_connector_status old_status;

	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
	old_status = connector->status;

	connector->status = connector->funcs->detect(connector, false);
842 843 844 845
	if (old_status == connector->status)
		return false;

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
846
		      connector->base.id,
847
		      connector->name,
848 849 850 851
		      drm_get_connector_status_name(old_status),
		      drm_get_connector_status_name(connector->status));

	return true;
852 853
}

854 855 856 857 858 859 860 861 862
static void i915_digport_work_func(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, dig_port_work);
	u32 long_port_mask, short_port_mask;
	struct intel_digital_port *intel_dig_port;
	int i, ret;
	u32 old_bits = 0;

863
	spin_lock_irq(&dev_priv->irq_lock);
864 865 866 867
	long_port_mask = dev_priv->long_hpd_port_mask;
	dev_priv->long_hpd_port_mask = 0;
	short_port_mask = dev_priv->short_hpd_port_mask;
	dev_priv->short_hpd_port_mask = 0;
868
	spin_unlock_irq(&dev_priv->irq_lock);
869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892

	for (i = 0; i < I915_MAX_PORTS; i++) {
		bool valid = false;
		bool long_hpd = false;
		intel_dig_port = dev_priv->hpd_irq_port[i];
		if (!intel_dig_port || !intel_dig_port->hpd_pulse)
			continue;

		if (long_port_mask & (1 << i))  {
			valid = true;
			long_hpd = true;
		} else if (short_port_mask & (1 << i))
			valid = true;

		if (valid) {
			ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
			if (ret == true) {
				/* if we get true fallback to old school hpd */
				old_bits |= (1 << intel_dig_port->base.hpd_pin);
			}
		}
	}

	if (old_bits) {
893
		spin_lock_irq(&dev_priv->irq_lock);
894
		dev_priv->hpd_event_bits |= old_bits;
895
		spin_unlock_irq(&dev_priv->irq_lock);
896 897 898 899
		schedule_work(&dev_priv->hotplug_work);
	}
}

900 901 902
/*
 * Handle hotplug events outside the interrupt handler proper.
 */
903 904
#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)

905 906
static void i915_hotplug_work_func(struct work_struct *work)
{
907 908
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, hotplug_work);
909
	struct drm_device *dev = dev_priv->dev;
910
	struct drm_mode_config *mode_config = &dev->mode_config;
911 912 913 914
	struct intel_connector *intel_connector;
	struct intel_encoder *intel_encoder;
	struct drm_connector *connector;
	bool hpd_disabled = false;
915
	bool changed = false;
916
	u32 hpd_event_bits;
917

918
	mutex_lock(&mode_config->mutex);
919 920
	DRM_DEBUG_KMS("running encoder hotplug functions\n");

921
	spin_lock_irq(&dev_priv->irq_lock);
922 923 924

	hpd_event_bits = dev_priv->hpd_event_bits;
	dev_priv->hpd_event_bits = 0;
925 926
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
927 928
		if (!intel_connector->encoder)
			continue;
929 930 931 932 933 934
		intel_encoder = intel_connector->encoder;
		if (intel_encoder->hpd_pin > HPD_NONE &&
		    dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
		    connector->polled == DRM_CONNECTOR_POLL_HPD) {
			DRM_INFO("HPD interrupt storm detected on connector %s: "
				 "switching from hotplug detection to polling\n",
935
				connector->name);
936 937 938 939 940
			dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
			connector->polled = DRM_CONNECTOR_POLL_CONNECT
				| DRM_CONNECTOR_POLL_DISCONNECT;
			hpd_disabled = true;
		}
941 942
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
943
				      connector->name, intel_encoder->hpd_pin);
944
		}
945 946 947 948
	}
	 /* if there were no outputs to poll, poll was disabled,
	  * therefore make sure it's enabled when disabling HPD on
	  * some connectors */
949
	if (hpd_disabled) {
950
		drm_kms_helper_poll_enable(dev);
951 952
		mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
				 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
953
	}
954

955
	spin_unlock_irq(&dev_priv->irq_lock);
956

957 958
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
959 960
		if (!intel_connector->encoder)
			continue;
961 962 963 964 965 966 967 968
		intel_encoder = intel_connector->encoder;
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			if (intel_encoder->hot_plug)
				intel_encoder->hot_plug(intel_encoder);
			if (intel_hpd_irq_event(dev, connector))
				changed = true;
		}
	}
969 970
	mutex_unlock(&mode_config->mutex);

971 972
	if (changed)
		drm_kms_helper_hotplug_event(dev);
973 974
}

975
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
976
{
977
	struct drm_i915_private *dev_priv = dev->dev_private;
978
	u32 busy_up, busy_down, max_avg, min_avg;
979 980
	u8 new_delay;

981
	spin_lock(&mchdev_lock);
982

983 984
	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

985
	new_delay = dev_priv->ips.cur_delay;
986

987
	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
988 989
	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
990 991 992 993
	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
994
	if (busy_up > max_avg) {
995 996 997 998
		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
999
	} else if (busy_down < min_avg) {
1000 1001 1002 1003
		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
1004 1005
	}

1006
	if (ironlake_set_drps(dev, new_delay))
1007
		dev_priv->ips.cur_delay = new_delay;
1008

1009
	spin_unlock(&mchdev_lock);
1010

1011 1012 1013
	return;
}

1014
static void notify_ring(struct drm_device *dev,
1015
			struct intel_engine_cs *ring)
1016
{
1017
	if (!intel_ring_initialized(ring))
1018 1019
		return;

1020
	trace_i915_gem_request_complete(ring);
1021

1022 1023 1024
	wake_up_all(&ring->irq_queue);
}

1025
static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
1026
			    struct intel_rps_ei *rps_ei)
1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038
{
	u32 cz_ts, cz_freq_khz;
	u32 render_count, media_count;
	u32 elapsed_render, elapsed_media, elapsed_time;
	u32 residency = 0;

	cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
	cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);

	render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
	media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);

1039 1040 1041 1042
	if (rps_ei->cz_clock == 0) {
		rps_ei->cz_clock = cz_ts;
		rps_ei->render_c0 = render_count;
		rps_ei->media_c0 = media_count;
1043 1044 1045 1046

		return dev_priv->rps.cur_freq;
	}

1047 1048
	elapsed_time = cz_ts - rps_ei->cz_clock;
	rps_ei->cz_clock = cz_ts;
1049

1050 1051
	elapsed_render = render_count - rps_ei->render_c0;
	rps_ei->render_c0 = render_count;
1052

1053 1054
	elapsed_media = media_count - rps_ei->media_c0;
	rps_ei->media_c0 = media_count;
1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079

	/* Convert all the counters into common unit of milli sec */
	elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
	elapsed_render /=  cz_freq_khz;
	elapsed_media /= cz_freq_khz;

	/*
	 * Calculate overall C0 residency percentage
	 * only if elapsed time is non zero
	 */
	if (elapsed_time) {
		residency =
			((max(elapsed_render, elapsed_media) * 100)
				/ elapsed_time);
	}

	return residency;
}

/**
 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
 * busy-ness calculated from C0 counters of render & media power wells
 * @dev_priv: DRM device private
 *
 */
1080
static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1081 1082
{
	u32 residency_C0_up = 0, residency_C0_down = 0;
1083
	int new_delay, adj;
1084 1085 1086 1087 1088 1089

	dev_priv->rps.ei_interrupt_count++;

	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));


1090 1091 1092
	if (dev_priv->rps.up_ei.cz_clock == 0) {
		vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
		vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106
		return dev_priv->rps.cur_freq;
	}


	/*
	 * To down throttle, C0 residency should be less than down threshold
	 * for continous EI intervals. So calculate down EI counters
	 * once in VLV_INT_COUNT_FOR_DOWN_EI
	 */
	if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {

		dev_priv->rps.ei_interrupt_count = 0;

		residency_C0_down = vlv_c0_residency(dev_priv,
1107
						     &dev_priv->rps.down_ei);
1108 1109
	} else {
		residency_C0_up = vlv_c0_residency(dev_priv,
1110
						   &dev_priv->rps.up_ei);
1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149
	}

	new_delay = dev_priv->rps.cur_freq;

	adj = dev_priv->rps.last_adj;
	/* C0 residency is greater than UP threshold. Increase Frequency */
	if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
		if (adj > 0)
			adj *= 2;
		else
			adj = 1;

		if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
			new_delay = dev_priv->rps.cur_freq + adj;

		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
		if (new_delay < dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;

	} else if (!dev_priv->rps.ei_interrupt_count &&
			(residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
		if (adj < 0)
			adj *= 2;
		else
			adj = -1;
		/*
		 * This means, C0 residency is less than down threshold over
		 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
		 */
		if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
			new_delay = dev_priv->rps.cur_freq + adj;
	}

	return new_delay;
}

1150
static void gen6_pm_rps_work(struct work_struct *work)
1151
{
1152 1153
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, rps.work);
P
Paulo Zanoni 已提交
1154
	u32 pm_iir;
1155
	int new_delay, adj;
1156

1157
	spin_lock_irq(&dev_priv->irq_lock);
I
Imre Deak 已提交
1158 1159 1160 1161 1162
	/* Speed up work cancelation during disabling rps interrupts. */
	if (!dev_priv->rps.interrupts_enabled) {
		spin_unlock_irq(&dev_priv->irq_lock);
		return;
	}
1163 1164
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
1165 1166
	/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1167
	spin_unlock_irq(&dev_priv->irq_lock);
1168

1169
	/* Make sure we didn't queue anything we're not going to process. */
1170
	WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1171

1172
	if ((pm_iir & dev_priv->pm_rps_events) == 0)
1173 1174
		return;

1175
	mutex_lock(&dev_priv->rps.hw_lock);
1176

1177
	adj = dev_priv->rps.last_adj;
1178
	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1179 1180
		if (adj > 0)
			adj *= 2;
1181 1182 1183 1184
		else {
			/* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
		}
1185
		new_delay = dev_priv->rps.cur_freq + adj;
1186 1187 1188 1189 1190

		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
1191 1192
		if (new_delay < dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;
1193
	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1194 1195
		if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;
1196
		else
1197
			new_delay = dev_priv->rps.min_freq_softlimit;
1198
		adj = 0;
1199 1200
	} else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
		new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1201 1202 1203
	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
		if (adj < 0)
			adj *= 2;
1204 1205 1206 1207
		else {
			/* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
		}
1208
		new_delay = dev_priv->rps.cur_freq + adj;
1209
	} else { /* unknown event */
1210
		new_delay = dev_priv->rps.cur_freq;
1211
	}
1212

1213 1214 1215
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
1216
	new_delay = clamp_t(int, new_delay,
1217 1218
			    dev_priv->rps.min_freq_softlimit,
			    dev_priv->rps.max_freq_softlimit);
1219

1220
	dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1221 1222 1223 1224 1225

	if (IS_VALLEYVIEW(dev_priv->dev))
		valleyview_set_rps(dev_priv->dev, new_delay);
	else
		gen6_set_rps(dev_priv->dev, new_delay);
1226

1227
	mutex_unlock(&dev_priv->rps.hw_lock);
1228 1229
}

1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241

/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
1242 1243
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, l3_parity.error_work);
1244
	u32 error_status, row, bank, subbank;
1245
	char *parity_event[6];
1246
	uint32_t misccpctl;
1247
	uint8_t slice = 0;
1248 1249 1250 1251 1252 1253 1254

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);

1255 1256 1257 1258
	/* If we've screwed up tracking, just let the interrupt fire again */
	if (WARN_ON(!dev_priv->l3_parity.which_slice))
		goto out;

1259 1260 1261 1262
	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

1263 1264
	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
		u32 reg;
1265

1266 1267 1268
		slice--;
		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
			break;
1269

1270
		dev_priv->l3_parity.which_slice &= ~(1<<slice);
1271

1272
		reg = GEN7_L3CDERRST1 + (slice * 0x200);
1273

1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288
		error_status = I915_READ(reg);
		row = GEN7_PARITY_ERROR_ROW(error_status);
		bank = GEN7_PARITY_ERROR_BANK(error_status);
		subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
		POSTING_READ(reg);

		parity_event[0] = I915_L3_PARITY_UEVENT "=1";
		parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
		parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
		parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
		parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
		parity_event[5] = NULL;

1289
		kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1290
				   KOBJ_CHANGE, parity_event);
1291

1292 1293
		DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
			  slice, row, bank, subbank);
1294

1295 1296 1297 1298 1299
		kfree(parity_event[4]);
		kfree(parity_event[3]);
		kfree(parity_event[2]);
		kfree(parity_event[1]);
	}
1300

1301
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1302

1303 1304
out:
	WARN_ON(dev_priv->l3_parity.which_slice);
1305
	spin_lock_irq(&dev_priv->irq_lock);
1306
	gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1307
	spin_unlock_irq(&dev_priv->irq_lock);
1308 1309

	mutex_unlock(&dev_priv->dev->struct_mutex);
1310 1311
}

1312
static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1313
{
1314
	struct drm_i915_private *dev_priv = dev->dev_private;
1315

1316
	if (!HAS_L3_DPF(dev))
1317 1318
		return;

1319
	spin_lock(&dev_priv->irq_lock);
1320
	gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1321
	spin_unlock(&dev_priv->irq_lock);
1322

1323 1324 1325 1326 1327 1328 1329
	iir &= GT_PARITY_ERROR(dev);
	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
		dev_priv->l3_parity.which_slice |= 1 << 1;

	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
		dev_priv->l3_parity.which_slice |= 1 << 0;

1330
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1331 1332
}

1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
		notify_ring(dev, &dev_priv->ring[RCS]);
	if (gt_iir & ILK_BSD_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[VCS]);
}

1344 1345 1346 1347 1348
static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{

1349 1350
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1351
		notify_ring(dev, &dev_priv->ring[RCS]);
1352
	if (gt_iir & GT_BSD_USER_INTERRUPT)
1353
		notify_ring(dev, &dev_priv->ring[VCS]);
1354
	if (gt_iir & GT_BLT_USER_INTERRUPT)
1355 1356
		notify_ring(dev, &dev_priv->ring[BCS]);

1357 1358
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
		      GT_BSD_CS_ERROR_INTERRUPT |
1359 1360
		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
		DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1361

1362 1363
	if (gt_iir & GT_PARITY_ERROR(dev))
		ivybridge_parity_error_irq_handler(dev, gt_iir);
1364 1365
}

1366 1367 1368 1369
static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
				       struct drm_i915_private *dev_priv,
				       u32 master_ctl)
{
1370
	struct intel_engine_cs *ring;
1371 1372 1373 1374 1375 1376 1377
	u32 rcs, bcs, vcs;
	uint32_t tmp = 0;
	irqreturn_t ret = IRQ_NONE;

	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
		tmp = I915_READ(GEN8_GT_IIR(0));
		if (tmp) {
1378
			I915_WRITE(GEN8_GT_IIR(0), tmp);
1379
			ret = IRQ_HANDLED;
1380

1381
			rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1382
			ring = &dev_priv->ring[RCS];
1383
			if (rcs & GT_RENDER_USER_INTERRUPT)
1384 1385 1386 1387 1388 1389
				notify_ring(dev, ring);
			if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
				intel_execlists_handle_ctx_events(ring);

			bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
			ring = &dev_priv->ring[BCS];
1390
			if (bcs & GT_RENDER_USER_INTERRUPT)
1391 1392 1393
				notify_ring(dev, ring);
			if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
				intel_execlists_handle_ctx_events(ring);
1394 1395 1396 1397
		} else
			DRM_ERROR("The master control interrupt lied (GT0)!\n");
	}

1398
	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1399 1400
		tmp = I915_READ(GEN8_GT_IIR(1));
		if (tmp) {
1401
			I915_WRITE(GEN8_GT_IIR(1), tmp);
1402
			ret = IRQ_HANDLED;
1403

1404
			vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1405
			ring = &dev_priv->ring[VCS];
1406
			if (vcs & GT_RENDER_USER_INTERRUPT)
1407
				notify_ring(dev, ring);
1408
			if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1409 1410
				intel_execlists_handle_ctx_events(ring);

1411
			vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1412
			ring = &dev_priv->ring[VCS2];
1413
			if (vcs & GT_RENDER_USER_INTERRUPT)
1414
				notify_ring(dev, ring);
1415
			if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1416
				intel_execlists_handle_ctx_events(ring);
1417 1418 1419 1420
		} else
			DRM_ERROR("The master control interrupt lied (GT1)!\n");
	}

1421 1422 1423 1424 1425
	if (master_ctl & GEN8_GT_PM_IRQ) {
		tmp = I915_READ(GEN8_GT_IIR(2));
		if (tmp & dev_priv->pm_rps_events) {
			I915_WRITE(GEN8_GT_IIR(2),
				   tmp & dev_priv->pm_rps_events);
1426
			ret = IRQ_HANDLED;
1427
			gen6_rps_irq_handler(dev_priv, tmp);
1428 1429 1430 1431
		} else
			DRM_ERROR("The master control interrupt lied (PM)!\n");
	}

1432 1433 1434
	if (master_ctl & GEN8_GT_VECS_IRQ) {
		tmp = I915_READ(GEN8_GT_IIR(3));
		if (tmp) {
1435
			I915_WRITE(GEN8_GT_IIR(3), tmp);
1436
			ret = IRQ_HANDLED;
1437

1438
			vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1439
			ring = &dev_priv->ring[VECS];
1440
			if (vcs & GT_RENDER_USER_INTERRUPT)
1441
				notify_ring(dev, ring);
1442
			if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1443
				intel_execlists_handle_ctx_events(ring);
1444 1445 1446 1447 1448 1449 1450
		} else
			DRM_ERROR("The master control interrupt lied (GT3)!\n");
	}

	return ret;
}

1451 1452 1453
#define HPD_STORM_DETECT_PERIOD 1000
#define HPD_STORM_THRESHOLD 5

1454
static int pch_port_to_hotplug_shift(enum port port)
1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469
{
	switch (port) {
	case PORT_A:
	case PORT_E:
	default:
		return -1;
	case PORT_B:
		return 0;
	case PORT_C:
		return 8;
	case PORT_D:
		return 16;
	}
}

1470
static int i915_port_to_hotplug_shift(enum port port)
1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499
{
	switch (port) {
	case PORT_A:
	case PORT_E:
	default:
		return -1;
	case PORT_B:
		return 17;
	case PORT_C:
		return 19;
	case PORT_D:
		return 21;
	}
}

static inline enum port get_port_from_pin(enum hpd_pin pin)
{
	switch (pin) {
	case HPD_PORT_B:
		return PORT_B;
	case HPD_PORT_C:
		return PORT_C;
	case HPD_PORT_D:
		return PORT_D;
	default:
		return PORT_A; /* no hpd */
	}
}

1500
static inline void intel_hpd_irq_handler(struct drm_device *dev,
1501
					 u32 hotplug_trigger,
1502
					 u32 dig_hotplug_reg,
1503
					 const u32 *hpd)
1504
{
1505
	struct drm_i915_private *dev_priv = dev->dev_private;
1506
	int i;
1507
	enum port port;
1508
	bool storm_detected = false;
1509 1510 1511
	bool queue_dig = false, queue_hp = false;
	u32 dig_shift;
	u32 dig_port_mask = 0;
1512

1513 1514 1515
	if (!hotplug_trigger)
		return;

1516 1517
	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
			 hotplug_trigger, dig_hotplug_reg);
1518

1519
	spin_lock(&dev_priv->irq_lock);
1520
	for (i = 1; i < HPD_NUM_PINS; i++) {
1521 1522 1523 1524 1525 1526 1527
		if (!(hpd[i] & hotplug_trigger))
			continue;

		port = get_port_from_pin(i);
		if (port && dev_priv->hpd_irq_port[port]) {
			bool long_hpd;

1528 1529
			if (HAS_PCH_SPLIT(dev)) {
				dig_shift = pch_port_to_hotplug_shift(port);
1530
				long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1531 1532 1533
			} else {
				dig_shift = i915_port_to_hotplug_shift(port);
				long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1534 1535
			}

1536 1537 1538
			DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
					 port_name(port),
					 long_hpd ? "long" : "short");
1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551
			/* for long HPD pulses we want to have the digital queue happen,
			   but we still want HPD storm detection to function. */
			if (long_hpd) {
				dev_priv->long_hpd_port_mask |= (1 << port);
				dig_port_mask |= hpd[i];
			} else {
				/* for short HPD just trigger the digital queue */
				dev_priv->short_hpd_port_mask |= (1 << port);
				hotplug_trigger &= ~hpd[i];
			}
			queue_dig = true;
		}
	}
1552

1553
	for (i = 1; i < HPD_NUM_PINS; i++) {
1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567
		if (hpd[i] & hotplug_trigger &&
		    dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
			/*
			 * On GMCH platforms the interrupt mask bits only
			 * prevent irq generation, not the setting of the
			 * hotplug bits itself. So only WARN about unexpected
			 * interrupts on saner platforms.
			 */
			WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
				  "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
				  hotplug_trigger, i, hpd[i]);

			continue;
		}
1568

1569 1570 1571 1572
		if (!(hpd[i] & hotplug_trigger) ||
		    dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
			continue;

1573 1574 1575 1576 1577
		if (!(dig_port_mask & hpd[i])) {
			dev_priv->hpd_event_bits |= (1 << i);
			queue_hp = true;
		}

1578 1579 1580 1581 1582
		if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
				   dev_priv->hpd_stats[i].hpd_last_jiffies
				   + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
			dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
			dev_priv->hpd_stats[i].hpd_cnt = 0;
1583
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1584 1585
		} else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
			dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1586
			dev_priv->hpd_event_bits &= ~(1 << i);
1587
			DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1588
			storm_detected = true;
1589 1590
		} else {
			dev_priv->hpd_stats[i].hpd_cnt++;
1591 1592
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
				      dev_priv->hpd_stats[i].hpd_cnt);
1593 1594 1595
		}
	}

1596 1597
	if (storm_detected)
		dev_priv->display.hpd_irq_setup(dev);
1598
	spin_unlock(&dev_priv->irq_lock);
1599

1600 1601 1602 1603 1604 1605
	/*
	 * Our hotplug handler can grab modeset locks (by calling down into the
	 * fb helpers). Hence it must not be run on our own dev-priv->wq work
	 * queue for otherwise the flush_work in the pageflip code will
	 * deadlock.
	 */
1606
	if (queue_dig)
1607
		queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1608 1609
	if (queue_hp)
		schedule_work(&dev_priv->hotplug_work);
1610 1611
}

1612 1613
static void gmbus_irq_handler(struct drm_device *dev)
{
1614
	struct drm_i915_private *dev_priv = dev->dev_private;
1615 1616

	wake_up_all(&dev_priv->gmbus_wait_queue);
1617 1618
}

1619 1620
static void dp_aux_irq_handler(struct drm_device *dev)
{
1621
	struct drm_i915_private *dev_priv = dev->dev_private;
1622 1623

	wake_up_all(&dev_priv->gmbus_wait_queue);
1624 1625
}

1626
#if defined(CONFIG_DEBUG_FS)
1627 1628 1629 1630
static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
					 uint32_t crc0, uint32_t crc1,
					 uint32_t crc2, uint32_t crc3,
					 uint32_t crc4)
1631 1632 1633 1634
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
	struct intel_pipe_crc_entry *entry;
1635
	int head, tail;
1636

1637 1638
	spin_lock(&pipe_crc->lock);

1639
	if (!pipe_crc->entries) {
1640
		spin_unlock(&pipe_crc->lock);
1641
		DRM_DEBUG_KMS("spurious interrupt\n");
1642 1643 1644
		return;
	}

1645 1646
	head = pipe_crc->head;
	tail = pipe_crc->tail;
1647 1648

	if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1649
		spin_unlock(&pipe_crc->lock);
1650 1651 1652 1653 1654
		DRM_ERROR("CRC buffer overflowing\n");
		return;
	}

	entry = &pipe_crc->entries[head];
1655

1656
	entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1657 1658 1659 1660 1661
	entry->crc[0] = crc0;
	entry->crc[1] = crc1;
	entry->crc[2] = crc2;
	entry->crc[3] = crc3;
	entry->crc[4] = crc4;
1662 1663

	head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1664 1665 1666
	pipe_crc->head = head;

	spin_unlock(&pipe_crc->lock);
1667 1668

	wake_up_interruptible(&pipe_crc->wq);
1669
}
1670 1671 1672 1673 1674 1675 1676 1677
#else
static inline void
display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
			     uint32_t crc0, uint32_t crc1,
			     uint32_t crc2, uint32_t crc3,
			     uint32_t crc4) {}
#endif

1678

1679
static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
D
Daniel Vetter 已提交
1680 1681 1682
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1683 1684 1685
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     0, 0, 0, 0);
D
Daniel Vetter 已提交
1686 1687
}

1688
static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1689 1690 1691
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1692 1693 1694 1695 1696 1697
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1698
}
1699

1700
static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1701 1702
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713
	uint32_t res1, res2;

	if (INTEL_INFO(dev)->gen >= 3)
		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
	else
		res1 = 0;

	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
	else
		res2 = 0;
1714

1715 1716 1717 1718 1719
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_RED(pipe)),
				     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
				     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
				     res1, res2);
1720
}
1721

1722 1723 1724 1725
/* The RPS events need forcewake, so we add them to a work queue and mask their
 * IMR bits until the work is done. Other interrupts can be processed without
 * the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1726
{
1727 1728 1729
	/* TODO: RPS on GEN9+ is not supported yet. */
	if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
		      "GEN9+: unexpected RPS IRQ\n"))
1730 1731
		return;

1732
	if (pm_iir & dev_priv->pm_rps_events) {
1733
		spin_lock(&dev_priv->irq_lock);
1734
		gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
I
Imre Deak 已提交
1735 1736 1737 1738
		if (dev_priv->rps.interrupts_enabled) {
			dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
			queue_work(dev_priv->wq, &dev_priv->rps.work);
		}
1739
		spin_unlock(&dev_priv->irq_lock);
1740 1741
	}

1742 1743 1744
	if (INTEL_INFO(dev_priv)->gen >= 8)
		return;

1745 1746 1747
	if (HAS_VEBOX(dev_priv->dev)) {
		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
			notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
B
Ben Widawsky 已提交
1748

1749 1750
		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
			DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
B
Ben Widawsky 已提交
1751
	}
1752 1753
}

1754 1755 1756 1757 1758 1759 1760 1761
static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
{
	if (!drm_handle_vblank(dev, pipe))
		return false;

	return true;
}

1762 1763 1764
static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1765
	u32 pipe_stats[I915_MAX_PIPES] = { };
1766 1767
	int pipe;

1768
	spin_lock(&dev_priv->irq_lock);
1769
	for_each_pipe(dev_priv, pipe) {
1770
		int reg;
1771
		u32 mask, iir_bit = 0;
1772

1773 1774 1775 1776 1777 1778 1779
		/*
		 * PIPESTAT bits get signalled even when the interrupt is
		 * disabled with the mask bits, and some of the status bits do
		 * not generate interrupts at all (like the underrun bit). Hence
		 * we need to be careful that we only handle what we want to
		 * handle.
		 */
1780 1781 1782

		/* fifo underruns are filterered in the underrun handler. */
		mask = PIPE_FIFO_UNDERRUN_STATUS;
1783 1784 1785 1786 1787 1788 1789 1790

		switch (pipe) {
		case PIPE_A:
			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
			break;
		case PIPE_B:
			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
			break;
1791 1792 1793
		case PIPE_C:
			iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
			break;
1794 1795 1796 1797 1798
		}
		if (iir & iir_bit)
			mask |= dev_priv->pipestat_irq_mask[pipe];

		if (!mask)
1799 1800 1801
			continue;

		reg = PIPESTAT(pipe);
1802 1803
		mask |= PIPESTAT_INT_ENABLE_MASK;
		pipe_stats[pipe] = I915_READ(reg) & mask;
1804 1805 1806 1807

		/*
		 * Clear the PIPE*STAT regs before the IIR
		 */
1808 1809
		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
					PIPESTAT_INT_STATUS_MASK))
1810 1811
			I915_WRITE(reg, pipe_stats[pipe]);
	}
1812
	spin_unlock(&dev_priv->irq_lock);
1813

1814
	for_each_pipe(dev_priv, pipe) {
1815 1816 1817
		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
1818

1819
		if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1820 1821 1822 1823 1824 1825 1826
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip(dev, pipe);
		}

		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
			i9xx_pipe_crc_irq_handler(dev, pipe);

1827 1828
		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1829 1830 1831 1832 1833 1834
	}

	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
		gmbus_irq_handler(dev);
}

1835 1836 1837 1838 1839
static void i9xx_hpd_irq_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

1840 1841 1842 1843 1844 1845 1846
	if (hotplug_status) {
		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
		/*
		 * Make sure hotplug status is cleared before we clear IIR, or else we
		 * may miss hotplug events.
		 */
		POSTING_READ(PORT_HOTPLUG_STAT);
1847

1848 1849
		if (IS_G4X(dev)) {
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1850

1851
			intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1852 1853
		} else {
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1854

1855
			intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1856
		}
1857

1858 1859 1860 1861
		if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
		    hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
			dp_aux_irq_handler(dev);
	}
1862 1863
}

1864
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
1865
{
1866
	struct drm_device *dev = arg;
1867
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
1868 1869 1870 1871
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;

	while (true) {
1872 1873
		/* Find, clear, then process each source of interrupt */

J
Jesse Barnes 已提交
1874
		gt_iir = I915_READ(GTIIR);
1875 1876 1877
		if (gt_iir)
			I915_WRITE(GTIIR, gt_iir);

J
Jesse Barnes 已提交
1878
		pm_iir = I915_READ(GEN6_PMIIR);
1879 1880 1881 1882 1883 1884 1885 1886 1887 1888
		if (pm_iir)
			I915_WRITE(GEN6_PMIIR, pm_iir);

		iir = I915_READ(VLV_IIR);
		if (iir) {
			/* Consume port before clearing IIR or we'll miss events */
			if (iir & I915_DISPLAY_PORT_INTERRUPT)
				i9xx_hpd_irq_handler(dev);
			I915_WRITE(VLV_IIR, iir);
		}
J
Jesse Barnes 已提交
1889 1890 1891 1892 1893 1894

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;

		ret = IRQ_HANDLED;

1895 1896
		if (gt_iir)
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
1897
		if (pm_iir)
1898
			gen6_rps_irq_handler(dev_priv, pm_iir);
1899 1900 1901
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
		valleyview_pipestat_irq_handler(dev, iir);
J
Jesse Barnes 已提交
1902 1903 1904 1905 1906 1907
	}

out:
	return ret;
}

1908 1909
static irqreturn_t cherryview_irq_handler(int irq, void *arg)
{
1910
	struct drm_device *dev = arg;
1911 1912 1913 1914
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl, iir;
	irqreturn_t ret = IRQ_NONE;

1915 1916 1917
	for (;;) {
		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
		iir = I915_READ(VLV_IIR);
1918

1919 1920
		if (master_ctl == 0 && iir == 0)
			break;
1921

1922 1923
		ret = IRQ_HANDLED;

1924
		I915_WRITE(GEN8_MASTER_IRQ, 0);
1925

1926
		/* Find, clear, then process each source of interrupt */
1927

1928 1929 1930 1931 1932 1933
		if (iir) {
			/* Consume port before clearing IIR or we'll miss events */
			if (iir & I915_DISPLAY_PORT_INTERRUPT)
				i9xx_hpd_irq_handler(dev);
			I915_WRITE(VLV_IIR, iir);
		}
1934

1935
		gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1936

1937 1938 1939
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
		valleyview_pipestat_irq_handler(dev, iir);
1940

1941 1942 1943
		I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
		POSTING_READ(GEN8_MASTER_IRQ);
	}
1944

1945 1946 1947
	return ret;
}

1948
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1949
{
1950
	struct drm_i915_private *dev_priv = dev->dev_private;
1951
	int pipe;
1952
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1953 1954 1955 1956
	u32 dig_hotplug_reg;

	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1957

1958
	intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1959

1960 1961 1962
	if (pch_iir & SDE_AUDIO_POWER_MASK) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
			       SDE_AUDIO_POWER_SHIFT);
1963
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1964 1965
				 port_name(port));
	}
1966

1967 1968 1969
	if (pch_iir & SDE_AUX_MASK)
		dp_aux_irq_handler(dev);

1970
	if (pch_iir & SDE_GMBUS)
1971
		gmbus_irq_handler(dev);
1972 1973 1974 1975 1976 1977 1978 1979 1980 1981

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1982
	if (pch_iir & SDE_FDI_MASK)
1983
		for_each_pipe(dev_priv, pipe)
1984 1985 1986
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1987 1988 1989 1990 1991 1992 1993 1994

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1995
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1996 1997

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1998
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1999 2000 2001 2002 2003 2004
}

static void ivb_err_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 err_int = I915_READ(GEN7_ERR_INT);
D
Daniel Vetter 已提交
2005
	enum pipe pipe;
2006

2007 2008 2009
	if (err_int & ERR_INT_POISON)
		DRM_ERROR("Poison interrupt\n");

2010
	for_each_pipe(dev_priv, pipe) {
2011 2012
		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2013

D
Daniel Vetter 已提交
2014 2015
		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
			if (IS_IVYBRIDGE(dev))
2016
				ivb_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
2017
			else
2018
				hsw_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
2019 2020
		}
	}
2021

2022 2023 2024 2025 2026 2027 2028 2029
	I915_WRITE(GEN7_ERR_INT, err_int);
}

static void cpt_serr_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 serr_int = I915_READ(SERR_INT);

2030 2031 2032
	if (serr_int & SERR_INT_POISON)
		DRM_ERROR("PCH poison interrupt\n");

2033
	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2034
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2035 2036

	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2037
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2038 2039

	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2040
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2041 2042

	I915_WRITE(SERR_INT, serr_int);
2043 2044
}

2045 2046
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
2047
	struct drm_i915_private *dev_priv = dev->dev_private;
2048
	int pipe;
2049
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2050 2051 2052 2053
	u32 dig_hotplug_reg;

	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2054

2055
	intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2056

2057 2058 2059 2060 2061 2062
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
			       SDE_AUDIO_POWER_SHIFT_CPT);
		DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
				 port_name(port));
	}
2063 2064

	if (pch_iir & SDE_AUX_MASK_CPT)
2065
		dp_aux_irq_handler(dev);
2066 2067

	if (pch_iir & SDE_GMBUS_CPT)
2068
		gmbus_irq_handler(dev);
2069 2070 2071 2072 2073 2074 2075 2076

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
2077
		for_each_pipe(dev_priv, pipe)
2078 2079 2080
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
2081 2082 2083

	if (pch_iir & SDE_ERROR_CPT)
		cpt_serr_int_handler(dev);
2084 2085
}

2086 2087 2088
static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2089
	enum pipe pipe;
2090 2091 2092 2093 2094 2095 2096 2097 2098 2099

	if (de_iir & DE_AUX_CHANNEL_A)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE)
		intel_opregion_asle_intr(dev);

	if (de_iir & DE_POISON)
		DRM_ERROR("Poison interrupt\n");

2100
	for_each_pipe(dev_priv, pipe) {
2101 2102 2103
		if (de_iir & DE_PIPE_VBLANK(pipe) &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
2104

2105
		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2106
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2107

2108 2109
		if (de_iir & DE_PIPE_CRC_DONE(pipe))
			i9xx_pipe_crc_irq_handler(dev, pipe);
2110

2111 2112 2113 2114 2115
		/* plane/pipes map 1:1 on ilk+ */
		if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
		}
2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134
	}

	/* check event from PCH */
	if (de_iir & DE_PCH_EVENT) {
		u32 pch_iir = I915_READ(SDEIIR);

		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}

	if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
		ironlake_rps_change_irq_handler(dev);
}

2135 2136 2137
static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2138
	enum pipe pipe;
2139 2140 2141 2142 2143 2144 2145 2146 2147 2148

	if (de_iir & DE_ERR_INT_IVB)
		ivb_err_int_handler(dev);

	if (de_iir & DE_AUX_CHANNEL_A_IVB)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE_IVB)
		intel_opregion_asle_intr(dev);

2149
	for_each_pipe(dev_priv, pipe) {
2150 2151 2152
		if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
2153 2154

		/* plane/pipes map 1:1 on ilk+ */
2155 2156 2157
		if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171
		}
	}

	/* check event from PCH */
	if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
		u32 pch_iir = I915_READ(SDEIIR);

		cpt_irq_handler(dev, pch_iir);

		/* clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}
}

2172 2173 2174 2175 2176 2177 2178 2179
/*
 * To handle irqs with the minimum potential races with fresh interrupts, we:
 * 1 - Disable Master Interrupt Control.
 * 2 - Find the source(s) of the interrupt.
 * 3 - Clear the Interrupt Identity bits (IIR).
 * 4 - Process the interrupt(s) that had bits set in the IIRs.
 * 5 - Re-enable Master Interrupt Control.
 */
2180
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2181
{
2182
	struct drm_device *dev = arg;
2183
	struct drm_i915_private *dev_priv = dev->dev_private;
2184
	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2185
	irqreturn_t ret = IRQ_NONE;
2186

2187 2188
	/* We get interrupts on unclaimed registers, so check for this before we
	 * do any I915_{READ,WRITE}. */
2189
	intel_uncore_check_errors(dev);
2190

2191 2192 2193
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2194
	POSTING_READ(DEIER);
2195

2196 2197 2198 2199 2200
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
2201 2202 2203 2204 2205
	if (!HAS_PCH_NOP(dev)) {
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
2206

2207 2208
	/* Find, clear, then process each source of interrupt */

2209
	gt_iir = I915_READ(GTIIR);
2210
	if (gt_iir) {
2211 2212
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
2213
		if (INTEL_INFO(dev)->gen >= 6)
2214
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
2215 2216
		else
			ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2217 2218
	}

2219 2220
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
2221 2222
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
2223 2224 2225 2226
		if (INTEL_INFO(dev)->gen >= 7)
			ivb_display_irq_handler(dev, de_iir);
		else
			ilk_display_irq_handler(dev, de_iir);
2227 2228
	}

2229 2230 2231 2232 2233
	if (INTEL_INFO(dev)->gen >= 6) {
		u32 pm_iir = I915_READ(GEN6_PMIIR);
		if (pm_iir) {
			I915_WRITE(GEN6_PMIIR, pm_iir);
			ret = IRQ_HANDLED;
2234
			gen6_rps_irq_handler(dev_priv, pm_iir);
2235
		}
2236
	}
2237 2238 2239

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
2240 2241 2242 2243
	if (!HAS_PCH_NOP(dev)) {
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
2244 2245 2246 2247

	return ret;
}

2248 2249 2250 2251 2252 2253 2254
static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl;
	irqreturn_t ret = IRQ_NONE;
	uint32_t tmp = 0;
2255
	enum pipe pipe;
J
Jesse Barnes 已提交
2256 2257 2258 2259 2260
	u32 aux_mask = GEN8_AUX_CHANNEL_A;

	if (IS_GEN9(dev))
		aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
			GEN9_AUX_CHANNEL_D;
2261 2262 2263 2264 2265 2266 2267 2268 2269

	master_ctl = I915_READ(GEN8_MASTER_IRQ);
	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
	if (!master_ctl)
		return IRQ_NONE;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

2270 2271
	/* Find, clear, then process each source of interrupt */

2272 2273 2274 2275 2276 2277 2278
	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);

	if (master_ctl & GEN8_DE_MISC_IRQ) {
		tmp = I915_READ(GEN8_DE_MISC_IIR);
		if (tmp) {
			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
			ret = IRQ_HANDLED;
2279 2280 2281 2282
			if (tmp & GEN8_DE_MISC_GSE)
				intel_opregion_asle_intr(dev);
			else
				DRM_ERROR("Unexpected DE Misc interrupt\n");
2283
		}
2284 2285
		else
			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2286 2287
	}

2288 2289 2290 2291 2292
	if (master_ctl & GEN8_DE_PORT_IRQ) {
		tmp = I915_READ(GEN8_DE_PORT_IIR);
		if (tmp) {
			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
			ret = IRQ_HANDLED;
J
Jesse Barnes 已提交
2293 2294

			if (tmp & aux_mask)
2295 2296 2297
				dp_aux_irq_handler(dev);
			else
				DRM_ERROR("Unexpected DE Port interrupt\n");
2298
		}
2299 2300
		else
			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2301 2302
	}

2303
	for_each_pipe(dev_priv, pipe) {
2304
		uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2305

2306 2307
		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
			continue;
2308

2309 2310 2311 2312
		pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
		if (pipe_iir) {
			ret = IRQ_HANDLED;
			I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2313

2314 2315 2316
			if (pipe_iir & GEN8_PIPE_VBLANK &&
			    intel_pipe_handle_vblank(dev, pipe))
				intel_check_page_flip(dev, pipe);
2317

2318 2319 2320 2321 2322 2323
			if (IS_GEN9(dev))
				flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
			else
				flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;

			if (flip_done) {
2324 2325 2326 2327 2328 2329 2330
				intel_prepare_page_flip(dev, pipe);
				intel_finish_page_flip_plane(dev, pipe);
			}

			if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
				hsw_pipe_crc_irq_handler(dev, pipe);

2331 2332 2333
			if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
2334

2335 2336 2337 2338 2339 2340 2341

			if (IS_GEN9(dev))
				fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
			else
				fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;

			if (fault_errors)
2342 2343 2344
				DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
					  pipe_name(pipe),
					  pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2345
		} else
2346 2347 2348
			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
	}

2349 2350 2351 2352 2353 2354 2355 2356 2357 2358
	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
		/*
		 * FIXME(BDW): Assume for now that the new interrupt handling
		 * scheme also closed the SDE interrupt handling race we've seen
		 * on older pch-split platforms. But this needs testing.
		 */
		u32 pch_iir = I915_READ(SDEIIR);
		if (pch_iir) {
			I915_WRITE(SDEIIR, pch_iir);
			ret = IRQ_HANDLED;
2359 2360 2361 2362
			cpt_irq_handler(dev, pch_iir);
		} else
			DRM_ERROR("The master control interrupt lied (SDE)!\n");

2363 2364
	}

2365 2366 2367 2368 2369 2370
	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
	POSTING_READ(GEN8_MASTER_IRQ);

	return ret;
}

2371 2372 2373
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
			       bool reset_completed)
{
2374
	struct intel_engine_cs *ring;
2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398
	int i;

	/*
	 * Notify all waiters for GPU completion events that reset state has
	 * been changed, and that they need to restart their wait after
	 * checking for potential errors (and bail out to drop locks if there is
	 * a gpu reset pending so that i915_error_work_func can acquire them).
	 */

	/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
	for_each_ring(ring, dev_priv, i)
		wake_up_all(&ring->irq_queue);

	/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
	wake_up_all(&dev_priv->pending_flip_queue);

	/*
	 * Signal tasks blocked in i915_gem_wait_for_error that the pending
	 * reset state is cleared.
	 */
	if (reset_completed)
		wake_up_all(&dev_priv->gpu_error.reset_queue);
}

2399 2400 2401 2402 2403 2404 2405 2406 2407
/**
 * i915_error_work_func - do process context error handling work
 * @work: work struct
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
static void i915_error_work_func(struct work_struct *work)
{
2408 2409
	struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
						    work);
2410 2411
	struct drm_i915_private *dev_priv =
		container_of(error, struct drm_i915_private, gpu_error);
2412
	struct drm_device *dev = dev_priv->dev;
2413 2414 2415
	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2416
	int ret;
2417

2418
	kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2419

2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2431
		DRM_DEBUG_DRIVER("resetting chip\n");
2432
		kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2433
				   reset_event);
2434

2435 2436 2437 2438 2439 2440 2441 2442
		/*
		 * In most cases it's guaranteed that we get here with an RPM
		 * reference held, for example because there is a pending GPU
		 * request that won't finish until the reset is done. This
		 * isn't the case at least when we get here by doing a
		 * simulated reset via debugs, so get an RPM reference.
		 */
		intel_runtime_pm_get(dev_priv);
2443 2444 2445

		intel_prepare_reset(dev);

2446 2447 2448 2449 2450 2451
		/*
		 * All state reset _must_ be completed before we update the
		 * reset counter, for otherwise waiters might miss the reset
		 * pending state and not properly drop locks, resulting in
		 * deadlocks with the reset work.
		 */
2452 2453
		ret = i915_reset(dev);

2454
		intel_finish_reset(dev);
2455

2456 2457
		intel_runtime_pm_put(dev_priv);

2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468
		if (ret == 0) {
			/*
			 * After all the gem state is reset, increment the reset
			 * counter and wake up everyone waiting for the reset to
			 * complete.
			 *
			 * Since unlock operations are a one-sided barrier only,
			 * we need to insert a barrier here to order any seqno
			 * updates before
			 * the counter increment.
			 */
2469
			smp_mb__before_atomic();
2470 2471
			atomic_inc(&dev_priv->gpu_error.reset_counter);

2472
			kobject_uevent_env(&dev->primary->kdev->kobj,
2473
					   KOBJ_CHANGE, reset_done_event);
2474
		} else {
M
Mika Kuoppala 已提交
2475
			atomic_set_mask(I915_WEDGED, &error->reset_counter);
2476
		}
2477

2478 2479 2480 2481 2482
		/*
		 * Note: The wake_up also serves as a memory barrier so that
		 * waiters see the update value of the reset counter atomic_t.
		 */
		i915_error_wake_up(dev_priv, true);
2483
	}
2484 2485
}

2486
static void i915_report_and_clear_eir(struct drm_device *dev)
2487 2488
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2489
	uint32_t instdone[I915_NUM_INSTDONE_REG];
2490
	u32 eir = I915_READ(EIR);
2491
	int pipe, i;
2492

2493 2494
	if (!eir)
		return;
2495

2496
	pr_err("render error detected, EIR: 0x%08x\n", eir);
2497

2498 2499
	i915_get_extra_instdone(dev, instdone);

2500 2501 2502 2503
	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

2504 2505
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2506 2507
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2508 2509
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2510
			I915_WRITE(IPEIR_I965, ipeir);
2511
			POSTING_READ(IPEIR_I965);
2512 2513 2514
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2515 2516
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2517
			I915_WRITE(PGTBL_ER, pgtbl_err);
2518
			POSTING_READ(PGTBL_ER);
2519 2520 2521
		}
	}

2522
	if (!IS_GEN2(dev)) {
2523 2524
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2525 2526
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2527
			I915_WRITE(PGTBL_ER, pgtbl_err);
2528
			POSTING_READ(PGTBL_ER);
2529 2530 2531 2532
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
2533
		pr_err("memory refresh error:\n");
2534
		for_each_pipe(dev_priv, pipe)
2535
			pr_err("pipe %c stat: 0x%08x\n",
2536
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2537 2538 2539
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
2540 2541
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2542 2543
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2544
		if (INTEL_INFO(dev)->gen < 4) {
2545 2546
			u32 ipeir = I915_READ(IPEIR);

2547 2548 2549
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2550
			I915_WRITE(IPEIR, ipeir);
2551
			POSTING_READ(IPEIR);
2552 2553 2554
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

2555 2556 2557 2558
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2559
			I915_WRITE(IPEIR_I965, ipeir);
2560
			POSTING_READ(IPEIR_I965);
2561 2562 2563 2564
		}
	}

	I915_WRITE(EIR, eir);
2565
	POSTING_READ(EIR);
2566 2567 2568 2569 2570 2571 2572 2573 2574 2575
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587
}

/**
 * i915_handle_error - handle an error interrupt
 * @dev: drm device
 *
 * Do some basic checking of regsiter state at error interrupt time and
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
2588 2589
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...)
2590 2591
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2592 2593
	va_list args;
	char error_msg[80];
2594

2595 2596 2597 2598 2599
	va_start(args, fmt);
	vscnprintf(error_msg, sizeof(error_msg), fmt, args);
	va_end(args);

	i915_capture_error_state(dev, wedged, error_msg);
2600
	i915_report_and_clear_eir(dev);
2601

2602
	if (wedged) {
2603 2604
		atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
				&dev_priv->gpu_error.reset_counter);
2605

2606
		/*
2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617
		 * Wakeup waiting processes so that the reset work function
		 * i915_error_work_func doesn't deadlock trying to grab various
		 * locks. By bumping the reset counter first, the woken
		 * processes will see a reset in progress and back off,
		 * releasing their locks and then wait for the reset completion.
		 * We must do this for _all_ gpu waiters that might hold locks
		 * that the reset work needs to acquire.
		 *
		 * Note: The wake_up serves as the required memory barrier to
		 * ensure that the waiters see the updated value of the reset
		 * counter atomic_t.
2618
		 */
2619
		i915_error_wake_up(dev_priv, false);
2620 2621
	}

2622 2623 2624 2625 2626 2627 2628
	/*
	 * Our reset work can grab modeset locks (since it needs to reset the
	 * state of outstanding pagelips). Hence it must not be run on our own
	 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
	 * code will deadlock.
	 */
	schedule_work(&dev_priv->gpu_error.work);
2629 2630
}

2631 2632 2633
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2634
static int i915_enable_vblank(struct drm_device *dev, int pipe)
2635
{
2636
	struct drm_i915_private *dev_priv = dev->dev_private;
2637
	unsigned long irqflags;
2638

2639
	if (!i915_pipe_enabled(dev, pipe))
2640
		return -EINVAL;
2641

2642
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2643
	if (INTEL_INFO(dev)->gen >= 4)
2644
		i915_enable_pipestat(dev_priv, pipe,
2645
				     PIPE_START_VBLANK_INTERRUPT_STATUS);
2646
	else
2647
		i915_enable_pipestat(dev_priv, pipe,
2648
				     PIPE_VBLANK_INTERRUPT_STATUS);
2649
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2650

2651 2652 2653
	return 0;
}

2654
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2655
{
2656
	struct drm_i915_private *dev_priv = dev->dev_private;
2657
	unsigned long irqflags;
2658
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2659
						     DE_PIPE_VBLANK(pipe);
2660 2661 2662 2663 2664

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2665
	ironlake_enable_display_irq(dev_priv, bit);
2666 2667 2668 2669 2670
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

J
Jesse Barnes 已提交
2671 2672
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
{
2673
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2674 2675 2676 2677 2678 2679
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2680
	i915_enable_pipestat(dev_priv, pipe,
2681
			     PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2682 2683 2684 2685 2686
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2687 2688 2689 2690 2691 2692 2693 2694 2695
static int gen8_enable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2696 2697 2698
	dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2699 2700 2701 2702
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
	return 0;
}

2703 2704 2705
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2706
static void i915_disable_vblank(struct drm_device *dev, int pipe)
2707
{
2708
	struct drm_i915_private *dev_priv = dev->dev_private;
2709
	unsigned long irqflags;
2710

2711
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2712
	i915_disable_pipestat(dev_priv, pipe,
2713 2714
			      PIPE_VBLANK_INTERRUPT_STATUS |
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
2715 2716 2717
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2718
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2719
{
2720
	struct drm_i915_private *dev_priv = dev->dev_private;
2721
	unsigned long irqflags;
2722
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2723
						     DE_PIPE_VBLANK(pipe);
2724 2725

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2726
	ironlake_disable_display_irq(dev_priv, bit);
2727 2728 2729
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

J
Jesse Barnes 已提交
2730 2731
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
{
2732
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2733 2734 2735
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2736
	i915_disable_pipestat(dev_priv, pipe,
2737
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2738 2739 2740
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2741 2742 2743 2744 2745 2746 2747 2748 2749
static void gen8_disable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2750 2751 2752
	dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2753 2754 2755
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2756
static u32
2757
ring_last_seqno(struct intel_engine_cs *ring)
2758
{
2759 2760 2761 2762
	return list_entry(ring->request_list.prev,
			  struct drm_i915_gem_request, list)->seqno;
}

2763
static bool
2764
ring_idle(struct intel_engine_cs *ring, u32 seqno)
2765 2766 2767
{
	return (list_empty(&ring->request_list) ||
		i915_seqno_passed(seqno, ring_last_seqno(ring)));
B
Ben Gamari 已提交
2768 2769
}

2770 2771 2772 2773
static bool
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
{
	if (INTEL_INFO(dev)->gen >= 8) {
2774
		return (ipehr >> 23) == 0x1c;
2775 2776 2777 2778 2779 2780 2781
	} else {
		ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
		return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
				 MI_SEMAPHORE_REGISTER);
	}
}

2782
static struct intel_engine_cs *
2783
semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2784 2785
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2786
	struct intel_engine_cs *signaller;
2787 2788 2789
	int i;

	if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2790 2791 2792 2793 2794 2795 2796
		for_each_ring(signaller, dev_priv, i) {
			if (ring == signaller)
				continue;

			if (offset == signaller->semaphore.signal_ggtt[ring->id])
				return signaller;
		}
2797 2798 2799 2800 2801 2802 2803
	} else {
		u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;

		for_each_ring(signaller, dev_priv, i) {
			if(ring == signaller)
				continue;

2804
			if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2805 2806 2807 2808
				return signaller;
		}
	}

2809 2810
	DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
		  ring->id, ipehr, offset);
2811 2812 2813 2814

	return NULL;
}

2815 2816
static struct intel_engine_cs *
semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2817 2818
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2819
	u32 cmd, ipehr, head;
2820 2821
	u64 offset = 0;
	int i, backwards;
2822 2823

	ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2824
	if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2825
		return NULL;
2826

2827 2828 2829
	/*
	 * HEAD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX. But limit it to just 3
2830 2831
	 * or 4 dwords depending on the semaphore wait command size.
	 * Note that we don't care about ACTHD here since that might
2832 2833
	 * point at at batch, and semaphores are always emitted into the
	 * ringbuffer itself.
2834
	 */
2835
	head = I915_READ_HEAD(ring) & HEAD_ADDR;
2836
	backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2837

2838
	for (i = backwards; i; --i) {
2839 2840 2841 2842 2843
		/*
		 * Be paranoid and presume the hw has gone off into the wild -
		 * our ring is smaller than what the hardware (and hence
		 * HEAD_ADDR) allows. Also handles wrap-around.
		 */
2844
		head &= ring->buffer->size - 1;
2845 2846

		/* This here seems to blow up */
2847
		cmd = ioread32(ring->buffer->virtual_start + head);
2848 2849 2850
		if (cmd == ipehr)
			break;

2851 2852
		head -= 4;
	}
2853

2854 2855
	if (!i)
		return NULL;
2856

2857
	*seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2858 2859 2860 2861 2862 2863
	if (INTEL_INFO(ring->dev)->gen >= 8) {
		offset = ioread32(ring->buffer->virtual_start + head + 12);
		offset <<= 32;
		offset = ioread32(ring->buffer->virtual_start + head + 8);
	}
	return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2864 2865
}

2866
static int semaphore_passed(struct intel_engine_cs *ring)
2867 2868
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2869
	struct intel_engine_cs *signaller;
2870
	u32 seqno;
2871

2872
	ring->hangcheck.deadlock++;
2873 2874

	signaller = semaphore_waits_for(ring, &seqno);
2875 2876 2877 2878 2879
	if (signaller == NULL)
		return -1;

	/* Prevent pathological recursion due to driver bugs */
	if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2880 2881
		return -1;

2882 2883 2884
	if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
		return 1;

2885 2886 2887
	/* cursory check for an unkickable deadlock */
	if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
	    semaphore_passed(signaller) < 0)
2888 2889 2890
		return -1;

	return 0;
2891 2892 2893 2894
}

static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
{
2895
	struct intel_engine_cs *ring;
2896 2897 2898
	int i;

	for_each_ring(ring, dev_priv, i)
2899
		ring->hangcheck.deadlock = 0;
2900 2901
}

2902
static enum intel_ring_hangcheck_action
2903
ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2904 2905 2906
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2907 2908
	u32 tmp;

2909 2910 2911 2912 2913 2914 2915 2916
	if (acthd != ring->hangcheck.acthd) {
		if (acthd > ring->hangcheck.max_acthd) {
			ring->hangcheck.max_acthd = acthd;
			return HANGCHECK_ACTIVE;
		}

		return HANGCHECK_ACTIVE_LOOP;
	}
2917

2918
	if (IS_GEN2(dev))
2919
		return HANGCHECK_HUNG;
2920 2921 2922 2923 2924 2925 2926

	/* Is the chip hanging on a WAIT_FOR_EVENT?
	 * If so we can simply poke the RB_WAIT bit
	 * and break the hang. This should work on
	 * all but the second generation chipsets.
	 */
	tmp = I915_READ_CTL(ring);
2927
	if (tmp & RING_WAIT) {
2928 2929 2930
		i915_handle_error(dev, false,
				  "Kicking stuck wait on %s",
				  ring->name);
2931
		I915_WRITE_CTL(ring, tmp);
2932
		return HANGCHECK_KICK;
2933 2934 2935 2936 2937
	}

	if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
		switch (semaphore_passed(ring)) {
		default:
2938
			return HANGCHECK_HUNG;
2939
		case 1:
2940 2941 2942
			i915_handle_error(dev, false,
					  "Kicking stuck semaphore on %s",
					  ring->name);
2943
			I915_WRITE_CTL(ring, tmp);
2944
			return HANGCHECK_KICK;
2945
		case 0:
2946
			return HANGCHECK_WAIT;
2947
		}
2948
	}
2949

2950
	return HANGCHECK_HUNG;
2951 2952
}

B
Ben Gamari 已提交
2953 2954
/**
 * This is called when the chip hasn't reported back with completed
2955 2956 2957 2958 2959
 * batchbuffers in a long time. We keep track per ring seqno progress and
 * if there are no progress, hangcheck score for that ring is increased.
 * Further, acthd is inspected to see if the ring is stuck. On stuck case
 * we kick the ring. If we see no progress on three subsequent calls
 * we assume chip is wedged and try to fix it by resetting the chip.
B
Ben Gamari 已提交
2960
 */
2961
static void i915_hangcheck_elapsed(unsigned long data)
B
Ben Gamari 已提交
2962 2963
{
	struct drm_device *dev = (struct drm_device *)data;
2964
	struct drm_i915_private *dev_priv = dev->dev_private;
2965
	struct intel_engine_cs *ring;
2966
	int i;
2967
	int busy_count = 0, rings_hung = 0;
2968 2969 2970 2971
	bool stuck[I915_NUM_RINGS] = { 0 };
#define BUSY 1
#define KICK 5
#define HUNG 20
2972

2973
	if (!i915.enable_hangcheck)
2974 2975
		return;

2976
	for_each_ring(ring, dev_priv, i) {
2977 2978
		u64 acthd;
		u32 seqno;
2979
		bool busy = true;
2980

2981 2982
		semaphore_clear_deadlocks(dev_priv);

2983 2984
		seqno = ring->get_seqno(ring, false);
		acthd = intel_ring_get_active_head(ring);
2985

2986 2987
		if (ring->hangcheck.seqno == seqno) {
			if (ring_idle(ring, seqno)) {
2988 2989
				ring->hangcheck.action = HANGCHECK_IDLE;

2990 2991
				if (waitqueue_active(&ring->irq_queue)) {
					/* Issue a wake-up to catch stuck h/w. */
2992
					if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2993 2994 2995 2996 2997 2998
						if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
							DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
								  ring->name);
						else
							DRM_INFO("Fake missed irq on %s\n",
								 ring->name);
2999 3000 3001 3002
						wake_up_all(&ring->irq_queue);
					}
					/* Safeguard against driver failure */
					ring->hangcheck.score += BUSY;
3003 3004
				} else
					busy = false;
3005
			} else {
3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020
				/* We always increment the hangcheck score
				 * if the ring is busy and still processing
				 * the same request, so that no single request
				 * can run indefinitely (such as a chain of
				 * batches). The only time we do not increment
				 * the hangcheck score on this ring, if this
				 * ring is in a legitimate wait for another
				 * ring. In that case the waiting ring is a
				 * victim and we want to be sure we catch the
				 * right culprit. Then every time we do kick
				 * the ring, add a small increment to the
				 * score so that we can catch a batch that is
				 * being repeatedly kicked and so responsible
				 * for stalling the machine.
				 */
3021 3022 3023 3024
				ring->hangcheck.action = ring_stuck(ring,
								    acthd);

				switch (ring->hangcheck.action) {
3025
				case HANGCHECK_IDLE:
3026 3027
				case HANGCHECK_WAIT:
				case HANGCHECK_ACTIVE:
3028 3029
					break;
				case HANGCHECK_ACTIVE_LOOP:
3030
					ring->hangcheck.score += BUSY;
3031
					break;
3032
				case HANGCHECK_KICK:
3033
					ring->hangcheck.score += KICK;
3034
					break;
3035
				case HANGCHECK_HUNG:
3036
					ring->hangcheck.score += HUNG;
3037 3038 3039
					stuck[i] = true;
					break;
				}
3040
			}
3041
		} else {
3042 3043
			ring->hangcheck.action = HANGCHECK_ACTIVE;

3044 3045 3046 3047 3048
			/* Gradually reduce the count so that we catch DoS
			 * attempts across multiple batches.
			 */
			if (ring->hangcheck.score > 0)
				ring->hangcheck.score--;
3049 3050

			ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3051 3052
		}

3053 3054
		ring->hangcheck.seqno = seqno;
		ring->hangcheck.acthd = acthd;
3055
		busy_count += busy;
3056
	}
3057

3058
	for_each_ring(ring, dev_priv, i) {
3059
		if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3060 3061 3062
			DRM_INFO("%s on %s\n",
				 stuck[i] ? "stuck" : "no progress",
				 ring->name);
3063
			rings_hung++;
3064 3065 3066
		}
	}

3067
	if (rings_hung)
3068
		return i915_handle_error(dev, true, "Ring hung");
B
Ben Gamari 已提交
3069

3070 3071 3072
	if (busy_count)
		/* Reset timer case chip hangs without another request
		 * being added */
3073 3074 3075 3076 3077 3078
		i915_queue_hangcheck(dev);
}

void i915_queue_hangcheck(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3079 3080
	struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer;

3081
	if (!i915.enable_hangcheck)
3082 3083
		return;

3084
	/* Don't continually defer the hangcheck, but make sure it is active */
3085 3086 3087 3088
	if (timer_pending(timer))
		return;
	mod_timer(timer,
		  round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
B
Ben Gamari 已提交
3089 3090
}

3091
static void ibx_irq_reset(struct drm_device *dev)
P
Paulo Zanoni 已提交
3092 3093 3094 3095 3096 3097
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

3098
	GEN5_IRQ_RESET(SDE);
3099 3100 3101

	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
		I915_WRITE(SERR_INT, 0xffffffff);
P
Paulo Zanoni 已提交
3102
}
3103

P
Paulo Zanoni 已提交
3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119
/*
 * SDEIER is also touched by the interrupt handler to work around missed PCH
 * interrupts. Hence we can't update it after the interrupt handler is enabled -
 * instead we unconditionally enable all PCH interrupt sources here, but then
 * only unmask them as needed with SDEIMR.
 *
 * This function needs to be called before interrupts are enabled.
 */
static void ibx_irq_pre_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

	WARN_ON(I915_READ(SDEIER) != 0);
P
Paulo Zanoni 已提交
3120 3121 3122 3123
	I915_WRITE(SDEIER, 0xffffffff);
	POSTING_READ(SDEIER);
}

3124
static void gen5_gt_irq_reset(struct drm_device *dev)
3125 3126 3127
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3128
	GEN5_IRQ_RESET(GT);
P
Paulo Zanoni 已提交
3129
	if (INTEL_INFO(dev)->gen >= 6)
3130
		GEN5_IRQ_RESET(GEN6_PM);
3131 3132
}

L
Linus Torvalds 已提交
3133 3134
/* drm_dma.h hooks
*/
P
Paulo Zanoni 已提交
3135
static void ironlake_irq_reset(struct drm_device *dev)
3136
{
3137
	struct drm_i915_private *dev_priv = dev->dev_private;
3138

3139
	I915_WRITE(HWSTAM, 0xffffffff);
3140

3141
	GEN5_IRQ_RESET(DE);
3142 3143
	if (IS_GEN7(dev))
		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3144

3145
	gen5_gt_irq_reset(dev);
3146

3147
	ibx_irq_reset(dev);
3148
}
3149

3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
	enum pipe pipe;

	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));

	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);

	GEN5_IRQ_RESET(VLV_);
}

J
Jesse Barnes 已提交
3163 3164
static void valleyview_irq_preinstall(struct drm_device *dev)
{
3165
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
3166 3167 3168 3169 3170 3171 3172

	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);

3173
	gen5_gt_irq_reset(dev);
J
Jesse Barnes 已提交
3174

3175
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
J
Jesse Barnes 已提交
3176

3177
	vlv_display_irq_reset(dev_priv);
J
Jesse Barnes 已提交
3178 3179
}

3180 3181 3182 3183 3184 3185 3186 3187
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
{
	GEN8_IRQ_RESET_NDX(GT, 0);
	GEN8_IRQ_RESET_NDX(GT, 1);
	GEN8_IRQ_RESET_NDX(GT, 2);
	GEN8_IRQ_RESET_NDX(GT, 3);
}

P
Paulo Zanoni 已提交
3188
static void gen8_irq_reset(struct drm_device *dev)
3189 3190 3191 3192 3193 3194 3195
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3196
	gen8_gt_irq_reset(dev_priv);
3197

3198
	for_each_pipe(dev_priv, pipe)
3199 3200
		if (intel_display_power_is_enabled(dev_priv,
						   POWER_DOMAIN_PIPE(pipe)))
3201
			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3202

3203 3204 3205
	GEN5_IRQ_RESET(GEN8_DE_PORT_);
	GEN5_IRQ_RESET(GEN8_DE_MISC_);
	GEN5_IRQ_RESET(GEN8_PCU_);
3206

3207
	ibx_irq_reset(dev);
3208
}
3209

3210 3211
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
{
3212
	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3213

3214
	spin_lock_irq(&dev_priv->irq_lock);
3215
	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3216
			  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3217
	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3218
			  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3219
	spin_unlock_irq(&dev_priv->irq_lock);
3220 3221
}

3222 3223 3224 3225 3226 3227 3228
static void cherryview_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3229
	gen8_gt_irq_reset(dev_priv);
3230 3231 3232 3233 3234

	GEN5_IRQ_RESET(GEN8_PCU_);

	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);

3235
	vlv_display_irq_reset(dev_priv);
3236 3237
}

3238
static void ibx_hpd_irq_setup(struct drm_device *dev)
3239
{
3240
	struct drm_i915_private *dev_priv = dev->dev_private;
3241
	struct intel_encoder *intel_encoder;
3242
	u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3243 3244

	if (HAS_PCH_IBX(dev)) {
3245
		hotplug_irqs = SDE_HOTPLUG_MASK;
3246
		for_each_intel_encoder(dev, intel_encoder)
3247
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3248
				enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3249
	} else {
3250
		hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3251
		for_each_intel_encoder(dev, intel_encoder)
3252
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3253
				enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3254
	}
3255

3256
	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3257 3258 3259 3260 3261 3262 3263

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
	 *
	 * This register is the same on all known PCH chips.
	 */
3264 3265 3266 3267 3268 3269 3270 3271
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}

P
Paulo Zanoni 已提交
3272 3273
static void ibx_irq_postinstall(struct drm_device *dev)
{
3274
	struct drm_i915_private *dev_priv = dev->dev_private;
3275
	u32 mask;
3276

D
Daniel Vetter 已提交
3277 3278 3279
	if (HAS_PCH_NOP(dev))
		return;

3280
	if (HAS_PCH_IBX(dev))
3281
		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3282
	else
3283
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3284

3285
	GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
P
Paulo Zanoni 已提交
3286 3287 3288
	I915_WRITE(SDEIMR, ~mask);
}

3289 3290 3291 3292 3293 3294 3295 3296
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pm_irqs, gt_irqs;

	pm_irqs = gt_irqs = 0;

	dev_priv->gt_irq_mask = ~0;
3297
	if (HAS_L3_DPF(dev)) {
3298
		/* L3 parity interrupt is always unmasked. */
3299 3300
		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
		gt_irqs |= GT_PARITY_ERROR(dev);
3301 3302 3303 3304 3305 3306 3307 3308 3309 3310
	}

	gt_irqs |= GT_RENDER_USER_INTERRUPT;
	if (IS_GEN5(dev)) {
		gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
			   ILK_BSD_USER_INTERRUPT;
	} else {
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
	}

P
Paulo Zanoni 已提交
3311
	GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3312 3313

	if (INTEL_INFO(dev)->gen >= 6) {
3314 3315 3316 3317
		/*
		 * RPS interrupts will get enabled/disabled on demand when RPS
		 * itself is enabled/disabled.
		 */
3318 3319 3320
		if (HAS_VEBOX(dev))
			pm_irqs |= PM_VEBOX_USER_INTERRUPT;

3321
		dev_priv->pm_irq_mask = 0xffffffff;
P
Paulo Zanoni 已提交
3322
		GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3323 3324 3325
	}
}

3326
static int ironlake_irq_postinstall(struct drm_device *dev)
3327
{
3328
	struct drm_i915_private *dev_priv = dev->dev_private;
3329 3330 3331 3332 3333 3334
	u32 display_mask, extra_mask;

	if (INTEL_INFO(dev)->gen >= 7) {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
				DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
				DE_PLANEB_FLIP_DONE_IVB |
3335
				DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3336
		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3337
			      DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3338 3339 3340
	} else {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3341 3342 3343
				DE_AUX_CHANNEL_A |
				DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
				DE_POISON);
3344 3345
		extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
				DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3346
	}
3347

3348
	dev_priv->irq_mask = ~display_mask;
3349

3350 3351
	I915_WRITE(HWSTAM, 0xeffe);

P
Paulo Zanoni 已提交
3352 3353
	ibx_irq_pre_postinstall(dev);

P
Paulo Zanoni 已提交
3354
	GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3355

3356
	gen5_gt_irq_postinstall(dev);
3357

P
Paulo Zanoni 已提交
3358
	ibx_irq_postinstall(dev);
3359

3360
	if (IS_IRONLAKE_M(dev)) {
3361 3362 3363
		/* Enable PCU event interrupts
		 *
		 * spinlocking not required here for correctness since interrupt
3364 3365
		 * setup is guaranteed to run in single-threaded context. But we
		 * need it to make the assert_spin_locked happy. */
3366
		spin_lock_irq(&dev_priv->irq_lock);
3367
		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3368
		spin_unlock_irq(&dev_priv->irq_lock);
3369 3370
	}

3371 3372 3373
	return 0;
}

3374 3375 3376 3377
static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;
3378
	enum pipe pipe;
3379 3380 3381 3382

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;

3383 3384
	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3385 3386 3387 3388 3389
	POSTING_READ(PIPESTAT(PIPE_A));

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

3390 3391 3392
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		      i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3393 3394 3395 3396

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3397 3398
	if (IS_CHERRYVIEW(dev_priv))
		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3399 3400 3401 3402 3403
	dev_priv->irq_mask &= ~iir_mask;

	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3404 3405
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	POSTING_READ(VLV_IMR);
3406 3407 3408 3409 3410 3411
}

static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;
3412
	enum pipe pipe;
3413 3414 3415

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3416
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3417 3418
	if (IS_CHERRYVIEW(dev_priv))
		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3419 3420 3421

	dev_priv->irq_mask |= iir_mask;
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3422
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3423 3424 3425 3426 3427 3428 3429
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	POSTING_READ(VLV_IIR);

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

3430 3431 3432
	i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3433 3434 3435

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;
3436 3437 3438

	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450
	POSTING_READ(PIPESTAT(PIPE_A));
}

void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = true;

3451
	if (intel_irqs_enabled(dev_priv))
3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463
		valleyview_display_irqs_install(dev_priv);
}

void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (!dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = false;

3464
	if (intel_irqs_enabled(dev_priv))
3465 3466 3467
		valleyview_display_irqs_uninstall(dev_priv);
}

3468
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
J
Jesse Barnes 已提交
3469
{
3470
	dev_priv->irq_mask = ~0;
J
Jesse Barnes 已提交
3471

3472 3473 3474
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

J
Jesse Barnes 已提交
3475
	I915_WRITE(VLV_IIR, 0xffffffff);
3476 3477 3478 3479
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	POSTING_READ(VLV_IMR);
J
Jesse Barnes 已提交
3480

3481 3482
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3483
	spin_lock_irq(&dev_priv->irq_lock);
3484 3485
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_install(dev_priv);
3486
	spin_unlock_irq(&dev_priv->irq_lock);
3487 3488 3489 3490 3491 3492 3493
}

static int valleyview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	vlv_display_irq_postinstall(dev_priv);
J
Jesse Barnes 已提交
3494

3495
	gen5_gt_irq_postinstall(dev);
J
Jesse Barnes 已提交
3496 3497 3498 3499 3500 3501 3502 3503

	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif

	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3504 3505 3506 3507

	return 0;
}

3508 3509 3510 3511 3512
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
	/* These are interrupts we'll toggle with the ring mask register */
	uint32_t gt_interrupts[] = {
		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3513
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3514
			GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3515 3516
			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3517
		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3518 3519 3520
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3521
		0,
3522 3523
		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3524 3525
		};

3526
	dev_priv->pm_irq_mask = 0xffffffff;
3527 3528
	GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
	GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3529 3530 3531 3532 3533
	/*
	 * RPS interrupts will get enabled/disabled on demand when RPS itself
	 * is enabled/disabled.
	 */
	GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3534
	GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3535 3536 3537 3538
}

static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
3539 3540
	uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
	uint32_t de_pipe_enables;
3541
	int pipe;
J
Jesse Barnes 已提交
3542
	u32 aux_en = GEN8_AUX_CHANNEL_A;
3543

J
Jesse Barnes 已提交
3544
	if (IS_GEN9(dev_priv)) {
3545 3546
		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
J
Jesse Barnes 已提交
3547 3548 3549
		aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
			GEN9_AUX_CHANNEL_D;
	} else
3550 3551 3552 3553 3554 3555
		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;

	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
					   GEN8_PIPE_FIFO_UNDERRUN;

3556 3557 3558
	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3559

3560
	for_each_pipe(dev_priv, pipe)
3561
		if (intel_display_power_is_enabled(dev_priv,
3562 3563 3564 3565
				POWER_DOMAIN_PIPE(pipe)))
			GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
					  dev_priv->de_irq_mask[pipe],
					  de_pipe_enables);
3566

J
Jesse Barnes 已提交
3567
	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
3568 3569 3570 3571 3572 3573
}

static int gen8_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

P
Paulo Zanoni 已提交
3574 3575
	ibx_irq_pre_postinstall(dev);

3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586
	gen8_gt_irq_postinstall(dev_priv);
	gen8_de_irq_postinstall(dev_priv);

	ibx_irq_postinstall(dev);

	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3587 3588 3589 3590
static int cherryview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3591
	vlv_display_irq_postinstall(dev_priv);
3592 3593 3594 3595 3596 3597 3598 3599 3600

	gen8_gt_irq_postinstall(dev_priv);

	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3601 3602 3603 3604 3605 3606 3607
static void gen8_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3608
	gen8_irq_reset(dev);
3609 3610
}

3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621
static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
{
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irq(&dev_priv->irq_lock);
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_uninstall(dev_priv);
	spin_unlock_irq(&dev_priv->irq_lock);

	vlv_display_irq_reset(dev_priv);

3622
	dev_priv->irq_mask = ~0;
3623 3624
}

J
Jesse Barnes 已提交
3625 3626
static void valleyview_irq_uninstall(struct drm_device *dev)
{
3627
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
3628 3629 3630 3631

	if (!dev_priv)
		return;

3632 3633
	I915_WRITE(VLV_MASTER_IER, 0);

3634 3635
	gen5_gt_irq_reset(dev);

J
Jesse Barnes 已提交
3636
	I915_WRITE(HWSTAM, 0xffffffff);
3637

3638
	vlv_display_irq_uninstall(dev_priv);
J
Jesse Barnes 已提交
3639 3640
}

3641 3642 3643 3644 3645 3646 3647 3648 3649 3650
static void cherryview_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3651
	gen8_gt_irq_reset(dev_priv);
3652

3653
	GEN5_IRQ_RESET(GEN8_PCU_);
3654

3655
	vlv_display_irq_uninstall(dev_priv);
3656 3657
}

3658
static void ironlake_irq_uninstall(struct drm_device *dev)
3659
{
3660
	struct drm_i915_private *dev_priv = dev->dev_private;
3661 3662 3663 3664

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3665
	ironlake_irq_reset(dev);
3666 3667
}

3668
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
3669
{
3670
	struct drm_i915_private *dev_priv = dev->dev_private;
3671
	int pipe;
3672

3673
	for_each_pipe(dev_priv, pipe)
3674
		I915_WRITE(PIPESTAT(pipe), 0);
3675 3676 3677
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
3678 3679 3680 3681
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
3682
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

3703 3704
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3705
	spin_lock_irq(&dev_priv->irq_lock);
3706 3707
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3708
	spin_unlock_irq(&dev_priv->irq_lock);
3709

C
Chris Wilson 已提交
3710 3711 3712
	return 0;
}

3713 3714 3715 3716
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_device *dev,
3717
			       int plane, int pipe, u32 iir)
3718
{
3719
	struct drm_i915_private *dev_priv = dev->dev_private;
3720
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3721

3722
	if (!intel_pipe_handle_vblank(dev, pipe))
3723 3724 3725
		return false;

	if ((iir & flip_pending) == 0)
3726
		goto check_page_flip;
3727 3728 3729 3730 3731 3732 3733 3734

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
3735
		goto check_page_flip;
3736

3737
	intel_prepare_page_flip(dev, plane);
3738 3739
	intel_finish_page_flip(dev, pipe);
	return true;
3740 3741 3742 3743

check_page_flip:
	intel_check_page_flip(dev, pipe);
	return false;
3744 3745
}

3746
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
3747
{
3748
	struct drm_device *dev = arg;
3749
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766
	u16 iir, new_iir;
	u32 pipe_stats[2];
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;

	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
3767
		spin_lock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3768
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3769
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
C
Chris Wilson 已提交
3770

3771
		for_each_pipe(dev_priv, pipe) {
C
Chris Wilson 已提交
3772 3773 3774 3775 3776 3777
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
3778
			if (pipe_stats[pipe] & 0x8000ffff)
C
Chris Wilson 已提交
3779 3780
				I915_WRITE(reg, pipe_stats[pipe]);
		}
3781
		spin_unlock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3782 3783 3784 3785 3786 3787 3788

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

3789
		for_each_pipe(dev_priv, pipe) {
3790
			int plane = pipe;
3791
			if (HAS_FBC(dev))
3792 3793
				plane = !plane;

3794
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3795 3796
			    i8xx_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
C
Chris Wilson 已提交
3797

3798
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3799
				i9xx_pipe_crc_irq_handler(dev, pipe);
3800

3801 3802 3803
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
3804
		}
C
Chris Wilson 已提交
3805 3806 3807 3808 3809 3810 3811 3812 3813

		iir = new_iir;
	}

	return IRQ_HANDLED;
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
3814
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3815 3816
	int pipe;

3817
	for_each_pipe(dev_priv, pipe) {
C
Chris Wilson 已提交
3818 3819 3820 3821 3822 3823 3824 3825 3826
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

3827 3828
static void i915_irq_preinstall(struct drm_device * dev)
{
3829
	struct drm_i915_private *dev_priv = dev->dev_private;
3830 3831 3832 3833 3834 3835 3836
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3837
	I915_WRITE16(HWSTAM, 0xeffe);
3838
	for_each_pipe(dev_priv, pipe)
3839 3840 3841 3842 3843 3844 3845 3846
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
3847
	struct drm_i915_private *dev_priv = dev->dev_private;
3848
	u32 enable_mask;
3849

3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		I915_USER_INTERRUPT;

3868
	if (I915_HAS_HOTPLUG(dev)) {
3869 3870 3871
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		POSTING_READ(PORT_HOTPLUG_EN);

3872 3873 3874 3875 3876 3877 3878 3879 3880 3881
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3882
	i915_enable_asle_pipestat(dev);
3883

3884 3885
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3886
	spin_lock_irq(&dev_priv->irq_lock);
3887 3888
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3889
	spin_unlock_irq(&dev_priv->irq_lock);
3890

3891 3892 3893
	return 0;
}

3894 3895 3896 3897 3898 3899
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_device *dev,
			       int plane, int pipe, u32 iir)
{
3900
	struct drm_i915_private *dev_priv = dev->dev_private;
3901 3902
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

3903
	if (!intel_pipe_handle_vblank(dev, pipe))
3904 3905 3906
		return false;

	if ((iir & flip_pending) == 0)
3907
		goto check_page_flip;
3908 3909 3910 3911 3912 3913 3914 3915

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
3916
		goto check_page_flip;
3917

3918
	intel_prepare_page_flip(dev, plane);
3919 3920
	intel_finish_page_flip(dev, pipe);
	return true;
3921 3922 3923 3924

check_page_flip:
	intel_check_page_flip(dev, pipe);
	return false;
3925 3926
}

3927
static irqreturn_t i915_irq_handler(int irq, void *arg)
3928
{
3929
	struct drm_device *dev = arg;
3930
	struct drm_i915_private *dev_priv = dev->dev_private;
3931
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3932 3933 3934 3935
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
3936 3937

	iir = I915_READ(IIR);
3938 3939
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
3940
		bool blc_event = false;
3941 3942 3943 3944 3945 3946

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
3947
		spin_lock(&dev_priv->irq_lock);
3948
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3949
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3950

3951
		for_each_pipe(dev_priv, pipe) {
3952 3953 3954
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

3955
			/* Clear the PIPE*STAT regs before the IIR */
3956 3957
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
3958
				irq_received = true;
3959 3960
			}
		}
3961
		spin_unlock(&dev_priv->irq_lock);
3962 3963 3964 3965 3966

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
3967 3968 3969
		if (I915_HAS_HOTPLUG(dev) &&
		    iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
3970

3971
		I915_WRITE(IIR, iir & ~flip_mask);
3972 3973 3974 3975 3976
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

3977
		for_each_pipe(dev_priv, pipe) {
3978
			int plane = pipe;
3979
			if (HAS_FBC(dev))
3980
				plane = !plane;
3981

3982
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3983 3984
			    i915_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3985 3986 3987

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
3988 3989

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3990
				i9xx_pipe_crc_irq_handler(dev, pipe);
3991

3992 3993 3994
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
4015
		ret = IRQ_HANDLED;
4016
		iir = new_iir;
4017
	} while (iir & ~flip_mask);
4018 4019 4020 4021 4022 4023

	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
4024
	struct drm_i915_private *dev_priv = dev->dev_private;
4025 4026 4027 4028 4029 4030 4031
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

4032
	I915_WRITE16(HWSTAM, 0xffff);
4033
	for_each_pipe(dev_priv, pipe) {
4034
		/* Clear enable bits; then clear status bits */
4035
		I915_WRITE(PIPESTAT(pipe), 0);
4036 4037
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
4038 4039 4040 4041 4042 4043 4044 4045
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
4046
	struct drm_i915_private *dev_priv = dev->dev_private;
4047 4048
	int pipe;

4049 4050
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4051 4052

	I915_WRITE(HWSTAM, 0xeffe);
4053
	for_each_pipe(dev_priv, pipe)
4054 4055 4056 4057 4058 4059 4060 4061
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
4062
	struct drm_i915_private *dev_priv = dev->dev_private;
4063
	u32 enable_mask;
4064 4065 4066
	u32 error_mask;

	/* Unmask the interrupts that we always want on. */
4067
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4068
			       I915_DISPLAY_PORT_INTERRUPT |
4069 4070 4071 4072 4073 4074 4075
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
4076 4077
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4078 4079 4080 4081
	enable_mask |= I915_USER_INTERRUPT;

	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
4082

4083 4084
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
4085
	spin_lock_irq(&dev_priv->irq_lock);
4086 4087 4088
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4089
	spin_unlock_irq(&dev_priv->irq_lock);
4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

4110 4111 4112
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

4113
	i915_enable_asle_pipestat(dev);
4114 4115 4116 4117

	return 0;
}

4118
static void i915_hpd_irq_setup(struct drm_device *dev)
4119
{
4120
	struct drm_i915_private *dev_priv = dev->dev_private;
4121
	struct intel_encoder *intel_encoder;
4122 4123
	u32 hotplug_en;

4124 4125
	assert_spin_locked(&dev_priv->irq_lock);

4126 4127 4128 4129
	if (I915_HAS_HOTPLUG(dev)) {
		hotplug_en = I915_READ(PORT_HOTPLUG_EN);
		hotplug_en &= ~HOTPLUG_INT_EN_MASK;
		/* Note HDMI and DP share hotplug bits */
4130
		/* enable bits are the same for all generations */
4131
		for_each_intel_encoder(dev, intel_encoder)
4132 4133
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
				hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4134 4135 4136 4137 4138 4139
		/* Programming the CRT detection parameters tends
		   to generate a spurious hotplug event about three
		   seconds later.  So just do it once.
		*/
		if (IS_G4X(dev))
			hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4140
		hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4141
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4142

4143 4144 4145
		/* Ignore TV since it's buggy */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
	}
4146 4147
}

4148
static irqreturn_t i965_irq_handler(int irq, void *arg)
4149
{
4150
	struct drm_device *dev = arg;
4151
	struct drm_i915_private *dev_priv = dev->dev_private;
4152 4153 4154
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	int ret = IRQ_NONE, pipe;
4155 4156 4157
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4158 4159 4160 4161

	iir = I915_READ(IIR);

	for (;;) {
4162
		bool irq_received = (iir & ~flip_mask) != 0;
4163 4164
		bool blc_event = false;

4165 4166 4167 4168 4169
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
4170
		spin_lock(&dev_priv->irq_lock);
4171
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4172
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4173

4174
		for_each_pipe(dev_priv, pipe) {
4175 4176 4177 4178 4179 4180 4181 4182
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
4183
				irq_received = true;
4184 4185
			}
		}
4186
		spin_unlock(&dev_priv->irq_lock);
4187 4188 4189 4190 4191 4192 4193

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
4194 4195
		if (iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
4196

4197
		I915_WRITE(IIR, iir & ~flip_mask);
4198 4199 4200 4201 4202 4203 4204
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);
		if (iir & I915_BSD_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[VCS]);

4205
		for_each_pipe(dev_priv, pipe) {
4206
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4207 4208
			    i915_handle_vblank(dev, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4209 4210 4211

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
4212 4213

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4214
				i9xx_pipe_crc_irq_handler(dev, pipe);
4215

4216 4217
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4218
		}
4219 4220 4221 4222

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

4223 4224 4225
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);

4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
4249
	struct drm_i915_private *dev_priv = dev->dev_private;
4250 4251 4252 4253 4254
	int pipe;

	if (!dev_priv)
		return;

4255 4256
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4257 4258

	I915_WRITE(HWSTAM, 0xffffffff);
4259
	for_each_pipe(dev_priv, pipe)
4260 4261 4262 4263
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

4264
	for_each_pipe(dev_priv, pipe)
4265 4266 4267 4268 4269
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

4270
static void intel_hpd_irq_reenable_work(struct work_struct *work)
4271
{
4272 4273 4274
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv),
			     hotplug_reenable_work.work);
4275 4276 4277 4278
	struct drm_device *dev = dev_priv->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	int i;

4279 4280
	intel_runtime_pm_get(dev_priv);

4281
	spin_lock_irq(&dev_priv->irq_lock);
4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295
	for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
		struct drm_connector *connector;

		if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
			continue;

		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;

		list_for_each_entry(connector, &mode_config->connector_list, head) {
			struct intel_connector *intel_connector = to_intel_connector(connector);

			if (intel_connector->encoder->hpd_pin == i) {
				if (connector->polled != intel_connector->polled)
					DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4296
							 connector->name);
4297 4298 4299 4300 4301 4302 4303 4304
				connector->polled = intel_connector->polled;
				if (!connector->polled)
					connector->polled = DRM_CONNECTOR_POLL_HPD;
			}
		}
	}
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
4305
	spin_unlock_irq(&dev_priv->irq_lock);
4306 4307

	intel_runtime_pm_put(dev_priv);
4308 4309
}

4310 4311 4312 4313 4314 4315 4316
/**
 * intel_irq_init - initializes irq support
 * @dev_priv: i915 device instance
 *
 * This function initializes all the irq support including work items, timers
 * and all the vtables. It does not setup the interrupt itself though.
 */
4317
void intel_irq_init(struct drm_i915_private *dev_priv)
4318
{
4319
	struct drm_device *dev = dev_priv->dev;
4320 4321

	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4322
	INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4323
	INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4324
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4325
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4326

4327
	/* Let's track the enabled rps events */
4328
	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4329
		/* WaGsvRC0ResidencyMethod:vlv */
4330 4331 4332
		dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
	else
		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4333

4334 4335
	setup_timer(&dev_priv->gpu_error.hangcheck_timer,
		    i915_hangcheck_elapsed,
4336
		    (unsigned long) dev);
4337
	INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4338
			  intel_hpd_irq_reenable_work);
4339

4340
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4341

4342
	if (IS_GEN2(dev_priv)) {
4343 4344
		dev->max_vblank_count = 0;
		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4345
	} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4346 4347
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4348 4349 4350
	} else {
		dev->driver->get_vblank_counter = i915_get_vblank_counter;
		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4351 4352
	}

4353 4354 4355 4356 4357
	/*
	 * Opt out of the vblank disable timer on everything except gen2.
	 * Gen2 doesn't have a hardware frame counter and so depends on
	 * vblank interrupts to produce sane vblank seuquence numbers.
	 */
4358
	if (!IS_GEN2(dev_priv))
4359 4360
		dev->vblank_disable_immediate = true;

4361
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4362
		dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4363 4364
		dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
	}
4365

4366
	if (IS_CHERRYVIEW(dev_priv)) {
4367 4368 4369 4370 4371 4372 4373
		dev->driver->irq_handler = cherryview_irq_handler;
		dev->driver->irq_preinstall = cherryview_irq_preinstall;
		dev->driver->irq_postinstall = cherryview_irq_postinstall;
		dev->driver->irq_uninstall = cherryview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4374
	} else if (IS_VALLEYVIEW(dev_priv)) {
J
Jesse Barnes 已提交
4375 4376 4377 4378 4379 4380
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
4381
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4382
	} else if (INTEL_INFO(dev_priv)->gen >= 8) {
4383
		dev->driver->irq_handler = gen8_irq_handler;
4384
		dev->driver->irq_preinstall = gen8_irq_reset;
4385 4386 4387 4388 4389
		dev->driver->irq_postinstall = gen8_irq_postinstall;
		dev->driver->irq_uninstall = gen8_irq_uninstall;
		dev->driver->enable_vblank = gen8_enable_vblank;
		dev->driver->disable_vblank = gen8_disable_vblank;
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4390 4391
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
4392
		dev->driver->irq_preinstall = ironlake_irq_reset;
4393 4394 4395 4396
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
4397
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4398
	} else {
4399
		if (INTEL_INFO(dev_priv)->gen == 2) {
C
Chris Wilson 已提交
4400 4401 4402 4403
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
4404
		} else if (INTEL_INFO(dev_priv)->gen == 3) {
4405 4406 4407 4408
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
4409
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
4410
		} else {
4411 4412 4413 4414
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
4415
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
4416
		}
4417 4418 4419 4420
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
4421

4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433
/**
 * intel_hpd_init - initializes and enables hpd support
 * @dev_priv: i915 device instance
 *
 * This function enables the hotplug support. It requires that interrupts have
 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
 * poll request can run concurrently to other code, so locking rules must be
 * obeyed.
 *
 * This is a separate step from interrupt enabling to simplify the locking rules
 * in the driver load and resume code.
 */
4434
void intel_hpd_init(struct drm_i915_private *dev_priv)
4435
{
4436
	struct drm_device *dev = dev_priv->dev;
4437 4438 4439
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct drm_connector *connector;
	int i;
4440

4441 4442 4443 4444 4445 4446 4447
	for (i = 1; i < HPD_NUM_PINS; i++) {
		dev_priv->hpd_stats[i].hpd_cnt = 0;
		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
	}
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		struct intel_connector *intel_connector = to_intel_connector(connector);
		connector->polled = intel_connector->polled;
4448 4449 4450
		if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
			connector->polled = DRM_CONNECTOR_POLL_HPD;
		if (intel_connector->mst_port)
4451 4452
			connector->polled = DRM_CONNECTOR_POLL_HPD;
	}
4453 4454 4455

	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked checks happy. */
4456
	spin_lock_irq(&dev_priv->irq_lock);
4457 4458
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
4459
	spin_unlock_irq(&dev_priv->irq_lock);
4460
}
4461

4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472
/**
 * intel_irq_install - enables the hardware interrupt
 * @dev_priv: i915 device instance
 *
 * This function enables the hardware interrupt handling, but leaves the hotplug
 * handling still disabled. It is called after intel_irq_init().
 *
 * In the driver load and resume code we need working interrupts in a few places
 * but don't want to deal with the hassle of concurrent probe and hotplug
 * workers. Hence the split into this two-stage approach.
 */
4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484
int intel_irq_install(struct drm_i915_private *dev_priv)
{
	/*
	 * We enable some interrupt sources in our postinstall hooks, so mark
	 * interrupts as enabled _before_ actually enabling them to avoid
	 * special cases in our ordering checks.
	 */
	dev_priv->pm.irqs_enabled = true;

	return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
}

4485 4486 4487 4488 4489 4490 4491
/**
 * intel_irq_uninstall - finilizes all irq handling
 * @dev_priv: i915 device instance
 *
 * This stops interrupt and hotplug handling and unregisters and frees all
 * resources acquired in the init functions.
 */
4492 4493 4494 4495 4496 4497 4498
void intel_irq_uninstall(struct drm_i915_private *dev_priv)
{
	drm_irq_uninstall(dev_priv->dev);
	intel_hpd_cancel_work(dev_priv);
	dev_priv->pm.irqs_enabled = false;
}

4499 4500 4501 4502 4503 4504 4505
/**
 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
 * @dev_priv: i915 device instance
 *
 * This function is used to disable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4506
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4507
{
4508
	dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4509
	dev_priv->pm.irqs_enabled = false;
4510 4511
}

4512 4513 4514 4515 4516 4517 4518
/**
 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
 * @dev_priv: i915 device instance
 *
 * This function is used to enable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4519
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4520
{
4521
	dev_priv->pm.irqs_enabled = true;
4522 4523
	dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
	dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4524
}