i915_drv.h 85.2 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>

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#include "i915_reg.h"
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#include "intel_bios.h"
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#include "intel_ringbuffer.h"
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#include "i915_gem_gtt.h"
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <drm/intel-gtt.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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/* General customization:
 */

#define DRIVER_AUTHOR		"Tungsten Graphics, Inc."

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20140620"
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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
	I915_MAX_TRANSCODERS
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};
#define transcoder_name(t) ((t) + 'A')

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enum plane {
	PLANE_A = 0,
	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
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enum port {
	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1
};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_PORT_DDI_A_2_LANES,
	POWER_DOMAIN_PORT_DDI_A_4_LANES,
	POWER_DOMAIN_PORT_DDI_B_2_LANES,
	POWER_DOMAIN_PORT_DDI_B_4_LANES,
	POWER_DOMAIN_PORT_DDI_C_2_LANES,
	POWER_DOMAIN_PORT_DDI_C_4_LANES,
	POWER_DOMAIN_PORT_DDI_D_2_LANES,
	POWER_DOMAIN_PORT_DDI_D_4_LANES,
	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
	HPD_NUM_PINS
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
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#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
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#define for_each_crtc(dev, crtc) \
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)

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#define for_each_intel_crtc(dev, intel_crtc) \
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
		if ((intel_encoder)->base.crtc == (__crtc))

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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
		if ((intel_connector)->base.encoder == (__encoder))

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struct drm_i915_private;
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struct i915_mmu_object;
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enum intel_dpll_id {
	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
	/* real shared dpll ids must be >= 0 */
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	DPLL_ID_PCH_PLL_A = 0,
	DPLL_ID_PCH_PLL_B = 1,
	DPLL_ID_WRPLL1 = 0,
	DPLL_ID_WRPLL2 = 1,
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};
#define I915_NUM_PLLS 2

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struct intel_dpll_hw_state {
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	uint32_t dpll;
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	uint32_t dpll_md;
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	uint32_t fp0;
	uint32_t fp1;
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	uint32_t wrpll;
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};

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struct intel_shared_dpll {
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	int refcount; /* count of number of CRTCs sharing this PLL */
	int active; /* count of number of active CRTCs (i.e. DPMS on) */
	bool on; /* is the PLL actually active? Disabled during modeset */
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	const char *name;
	/* should match the index in the dev_priv->shared_dplls array */
	enum intel_dpll_id id;
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	struct intel_dpll_hw_state hw_state;
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	/* The mode_set hook is optional and should be used together with the
	 * intel_prepare_shared_dpll function. */
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	void (*mode_set)(struct drm_i915_private *dev_priv,
			 struct intel_shared_dpll *pll);
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	void (*enable)(struct drm_i915_private *dev_priv,
		       struct intel_shared_dpll *pll);
	void (*disable)(struct drm_i915_private *dev_priv,
			struct intel_shared_dpll *pll);
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	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
			     struct intel_shared_dpll *pll,
			     struct intel_dpll_hw_state *hw_state);
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};

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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#define WATCH_LISTS	0
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#define WATCH_GTT	0
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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header __iomem *header;
	struct opregion_acpi __iomem *acpi;
	struct opregion_swsci __iomem *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
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	struct opregion_asle __iomem *asle;
	void __iomem *vbt;
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	u32 __iomem *lid_state;
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	struct work_struct asle_work;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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struct drm_i915_master_private {
	drm_local_map_t *sarea;
	struct _drm_i915_sarea *sarea_priv;
};
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#define I915_FENCE_REG_NONE -1
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#define I915_MAX_NUM_FENCES 32
/* 32 fences + sign bit for FENCE_REG_NONE */
#define I915_MAX_NUM_FENCE_BITS 6
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struct drm_i915_fence_reg {
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	struct list_head lru_list;
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	struct drm_i915_gem_object *obj;
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	int pin_count;
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};
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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_display_error_state;

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struct drm_i915_error_state {
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	struct kref ref;
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	struct timeval time;

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	char error_msg[128];
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	u32 reset_count;
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	u32 suspend_count;
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	/* Generic register state */
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	u32 eir;
	u32 pgtbl_er;
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	u32 ier;
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	u32 ccid;
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	u32 derrmr;
	u32 forcewake;
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	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 done_reg;
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	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
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	u32 extra_instdone[I915_NUM_INSTDONE_REG];
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
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	struct drm_i915_error_object *semaphore_obj;
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	struct drm_i915_error_ring {
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		bool valid;
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		/* Software tracked state */
		bool waiting;
		int hangcheck_score;
		enum intel_ring_hangcheck_action hangcheck_action;
		int num_requests;

		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 semaphore_seqno[I915_NUM_RINGS - 1];

		/* Register state */
		u32 tail;
		u32 head;
		u32 ctl;
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 instdone;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
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		u64 acthd;
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		u32 fault_reg;
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		u64 faddr;
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		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_RINGS - 1];

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		struct drm_i915_error_object {
			int page_count;
			u32 gtt_offset;
			u32 *pages[0];
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		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
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		struct drm_i915_error_request {
			long jiffies;
			u32 seqno;
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			u32 tail;
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		} *requests;
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		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
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		pid_t pid;
		char comm[TASK_COMM_LEN];
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	} ring[I915_NUM_RINGS];
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	struct drm_i915_error_buffer {
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		u32 size;
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		u32 name;
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		u32 rseqno, wseqno;
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		u32 gtt_offset;
		u32 read_domains;
		u32 write_domain;
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		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
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		s32 pinned:2;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
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		u32 userptr:1;
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		s32 ring:4;
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		u32 cache_level:3;
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	} **active_bo, **pinned_bo;
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	u32 *active_bo_count, *pinned_bo_count;
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};

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struct intel_connector;
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struct intel_crtc_config;
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struct intel_plane_config;
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struct intel_crtc;
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struct intel_limit;
struct dpll;
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struct drm_i915_display_funcs {
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	bool (*fbc_enabled)(struct drm_device *dev);
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	void (*enable_fbc)(struct drm_crtc *crtc);
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	void (*disable_fbc)(struct drm_device *dev);
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
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	/**
	 * find_dpll() - Find the best values for the PLL
	 * @limit: limits for the PLL
	 * @crtc: current CRTC
	 * @target: target frequency in kHz
	 * @refclk: reference clock frequency in kHz
	 * @match_clock: if provided, @best_clock P divider must
	 *               match the P divider from @match_clock
	 *               used for LVDS downclocking
	 * @best_clock: best PLL values found
	 *
	 * Returns true on success, false on failure.
	 */
	bool (*find_dpll)(const struct intel_limit *limit,
			  struct drm_crtc *crtc,
			  int target, int refclk,
			  struct dpll *match_clock,
			  struct dpll *best_clock);
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	void (*update_wm)(struct drm_crtc *crtc);
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	void (*update_sprite_wm)(struct drm_plane *plane,
				 struct drm_crtc *crtc,
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				 uint32_t sprite_width, int pixel_size,
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				 bool enable, bool scaled);
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	void (*modeset_global_resources)(struct drm_device *dev);
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	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
				struct intel_crtc_config *);
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	void (*get_plane_config)(struct intel_crtc *,
				 struct intel_plane_config *);
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	int (*crtc_mode_set)(struct drm_crtc *crtc,
			     int x, int y,
			     struct drm_framebuffer *old_fb);
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	void (*crtc_enable)(struct drm_crtc *crtc);
	void (*crtc_disable)(struct drm_crtc *crtc);
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	void (*off)(struct drm_crtc *crtc);
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	void (*write_eld)(struct drm_connector *connector,
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			  struct drm_crtc *crtc,
			  struct drm_display_mode *mode);
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	void (*fdi_link_train)(struct drm_crtc *crtc);
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	void (*init_clock_gating)(struct drm_device *dev);
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	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
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			  struct drm_i915_gem_object *obj,
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			  struct intel_engine_cs *ring,
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			  uint32_t flags);
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	void (*update_primary_plane)(struct drm_crtc *crtc,
				     struct drm_framebuffer *fb,
				     int x, int y);
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	void (*hpd_irq_setup)(struct drm_device *dev);
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	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
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	int (*setup_backlight)(struct intel_connector *connector);
	uint32_t (*get_backlight)(struct intel_connector *connector);
	void (*set_backlight)(struct intel_connector *connector,
			      uint32_t level);
	void (*disable_backlight)(struct intel_connector *connector);
	void (*enable_backlight)(struct intel_connector *connector);
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};

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struct intel_uncore_funcs {
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	void (*force_wake_get)(struct drm_i915_private *dev_priv,
							int fw_engine);
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
							int fw_engine);
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	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);

	void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
				uint8_t val, bool trace);
	void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
				uint16_t val, bool trace);
	void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
				uint32_t val, bool trace);
	void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
				uint64_t val, bool trace);
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};

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struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
	unsigned forcewake_count;
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	unsigned fw_rendercount;
	unsigned fw_mediacount;

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	struct timer_list force_wake_timer;
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};

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#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
	func(is_mobile) sep \
	func(is_i85x) sep \
	func(is_i915g) sep \
	func(is_i945gm) sep \
	func(is_g33) sep \
	func(need_gfx_hws) sep \
	func(is_g4x) sep \
	func(is_pineview) sep \
	func(is_broadwater) sep \
	func(is_crestline) sep \
	func(is_ivybridge) sep \
	func(is_valleyview) sep \
	func(is_haswell) sep \
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	func(is_preliminary) sep \
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	func(has_fbc) sep \
	func(has_pipe_cxsr) sep \
	func(has_hotplug) sep \
	func(cursor_needs_physical) sep \
	func(has_overlay) sep \
	func(overlay_needs_physical) sep \
	func(supports_tv) sep \
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	func(has_llc) sep \
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	func(has_ddi) sep \
	func(has_fpga_dbg)
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#define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ;
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struct intel_device_info {
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	u32 display_mmio_offset;
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	u8 num_pipes:3;
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	u8 num_sprites[I915_MAX_PIPES];
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	u8 gen;
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	u8 ring_mask; /* Rings supported by the HW */
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	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
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	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
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	int cursor_offsets[I915_MAX_PIPES];
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};

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#undef DEFINE_FLAG
#undef SEP_SEMICOLON

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enum i915_cache_level {
	I915_CACHE_NONE = 0,
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	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
570
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
571 572
};

573 574 575 576 577 578
struct i915_ctx_hang_stats {
	/* This context had batch pending when hang was declared */
	unsigned batch_pending;

	/* This context had batch active when hang was declared */
	unsigned batch_active;
579 580 581 582 583 584

	/* Time when this context was last blamed for a GPU reset */
	unsigned long guilty_ts;

	/* This context is banned to submit more work */
	bool banned;
585
};
586 587

/* This must match up with the value previously used for execbuf2.rsvd1. */
588
#define DEFAULT_CONTEXT_HANDLE 0
589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605
/**
 * struct intel_context - as the name implies, represents a context.
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
 * @vm: virtual memory space used by this context.
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
606
struct intel_context {
607
	struct kref ref;
608
	int user_handle;
609
	uint8_t remap_slice;
610
	struct drm_i915_file_private *file_priv;
611
	struct i915_ctx_hang_stats hang_stats;
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Ben Widawsky 已提交
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	struct i915_address_space *vm;
613

614 615 616 617 618
	struct {
		struct drm_i915_gem_object *rcs_state;
		bool initialized;
	} legacy_hw_ctx;

619
	struct list_head link;
620 621
};

622 623
struct i915_fbc {
	unsigned long size;
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Ben Widawsky 已提交
624
	unsigned threshold;
625 626 627 628
	unsigned int fb_id;
	enum plane plane;
	int y;

629
	struct drm_mm_node compressed_fb;
630 631 632 633 634 635 636 637
	struct drm_mm_node *compressed_llb;

	struct intel_fbc_work {
		struct delayed_work work;
		struct drm_crtc *crtc;
		struct drm_framebuffer *fb;
	} *fbc_work;

638 639 640
	enum no_fbc_reason {
		FBC_OK, /* FBC is enabled */
		FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
641 642 643 644 645 646 647 648 649 650
		FBC_NO_OUTPUT, /* no outputs enabled to compress */
		FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
		FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
		FBC_MODE_TOO_LARGE, /* mode too large for compression */
		FBC_BAD_PLANE, /* fbc not supported on plane */
		FBC_NOT_TILED, /* buffer not tiled */
		FBC_MULTIPLE_PIPES, /* more than one pipe active */
		FBC_MODULE_PARAM,
		FBC_CHIP_DEFAULT, /* disabled by default on this chip */
	} no_fbc_reason;
651 652
};

653 654 655 656
struct i915_drrs {
	struct intel_connector *connector;
};

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struct i915_psr {
	bool sink_support;
	bool source_ok;
660
	bool setup_done;
661 662 663
	bool enabled;
	bool active;
	struct delayed_work work;
664
};
665

666
enum intel_pch {
667
	PCH_NONE = 0,	/* No PCH present */
668 669
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
670
	PCH_LPT,	/* Lynxpoint PCH */
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	PCH_NOP,
672 673
};

674 675 676 677 678
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

679
#define QUIRK_PIPEA_FORCE (1<<0)
680
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
681
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
682

683
struct intel_fbdev;
684
struct intel_fbc_work;
685

686 687
struct intel_gmbus {
	struct i2c_adapter adapter;
688
	u32 force_bit;
689
	u32 reg0;
690
	u32 gpio_reg;
691
	struct i2c_algo_bit_data bit_algo;
692 693 694
	struct drm_i915_private *dev_priv;
};

695
struct i915_suspend_saved_registers {
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	u8 saveLBB;
	u32 saveDSPACNTR;
	u32 saveDSPBCNTR;
699
	u32 saveDSPARB;
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	u32 savePIPEACONF;
	u32 savePIPEBCONF;
	u32 savePIPEASRC;
	u32 savePIPEBSRC;
	u32 saveFPA0;
	u32 saveFPA1;
	u32 saveDPLL_A;
	u32 saveDPLL_A_MD;
	u32 saveHTOTAL_A;
	u32 saveHBLANK_A;
	u32 saveHSYNC_A;
	u32 saveVTOTAL_A;
	u32 saveVBLANK_A;
	u32 saveVSYNC_A;
	u32 saveBCLRPAT_A;
715
	u32 saveTRANSACONF;
716 717 718 719 720 721
	u32 saveTRANS_HTOTAL_A;
	u32 saveTRANS_HBLANK_A;
	u32 saveTRANS_HSYNC_A;
	u32 saveTRANS_VTOTAL_A;
	u32 saveTRANS_VBLANK_A;
	u32 saveTRANS_VSYNC_A;
722
	u32 savePIPEASTAT;
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	u32 saveDSPASTRIDE;
	u32 saveDSPASIZE;
	u32 saveDSPAPOS;
726
	u32 saveDSPAADDR;
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	u32 saveDSPASURF;
	u32 saveDSPATILEOFF;
	u32 savePFIT_PGM_RATIOS;
730
	u32 saveBLC_HIST_CTL;
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	u32 saveBLC_PWM_CTL;
	u32 saveBLC_PWM_CTL2;
733
	u32 saveBLC_HIST_CTL_B;
734 735
	u32 saveBLC_CPU_PWM_CTL;
	u32 saveBLC_CPU_PWM_CTL2;
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	u32 saveFPB0;
	u32 saveFPB1;
	u32 saveDPLL_B;
	u32 saveDPLL_B_MD;
	u32 saveHTOTAL_B;
	u32 saveHBLANK_B;
	u32 saveHSYNC_B;
	u32 saveVTOTAL_B;
	u32 saveVBLANK_B;
	u32 saveVSYNC_B;
	u32 saveBCLRPAT_B;
747
	u32 saveTRANSBCONF;
748 749 750 751 752 753
	u32 saveTRANS_HTOTAL_B;
	u32 saveTRANS_HBLANK_B;
	u32 saveTRANS_HSYNC_B;
	u32 saveTRANS_VTOTAL_B;
	u32 saveTRANS_VBLANK_B;
	u32 saveTRANS_VSYNC_B;
754
	u32 savePIPEBSTAT;
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	u32 saveDSPBSTRIDE;
	u32 saveDSPBSIZE;
	u32 saveDSPBPOS;
758
	u32 saveDSPBADDR;
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	u32 saveDSPBSURF;
	u32 saveDSPBTILEOFF;
761 762 763
	u32 saveVGA0;
	u32 saveVGA1;
	u32 saveVGA_PD;
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	u32 saveVGACNTRL;
	u32 saveADPA;
	u32 saveLVDS;
767 768
	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
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	u32 saveDVOA;
	u32 saveDVOB;
	u32 saveDVOC;
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
775
	u32 savePP_DIVISOR;
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	u32 savePFIT_CONTROL;
	u32 save_palette_a[256];
	u32 save_palette_b[256];
	u32 saveFBC_CONTROL;
780 781 782
	u32 saveIER;
	u32 saveIIR;
	u32 saveIMR;
783 784 785 786 787 788
	u32 saveDEIER;
	u32 saveDEIMR;
	u32 saveGTIER;
	u32 saveGTIMR;
	u32 saveFDI_RXA_IMR;
	u32 saveFDI_RXB_IMR;
789 790
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
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	u32 saveSWF0[16];
	u32 saveSWF1[16];
	u32 saveSWF2[3];
	u8 saveMSR;
	u8 saveSR[8];
796
	u8 saveGR[25];
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	u8 saveAR_INDEX;
798
	u8 saveAR[21];
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799
	u8 saveDACMASK;
800
	u8 saveCR[37];
801
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
802 803 804 805 806 807 808
	u32 saveCURACNTR;
	u32 saveCURAPOS;
	u32 saveCURABASE;
	u32 saveCURBCNTR;
	u32 saveCURBPOS;
	u32 saveCURBBASE;
	u32 saveCURSIZE;
809 810 811 812 813 814 815 816 817 818 819
	u32 saveDP_B;
	u32 saveDP_C;
	u32 saveDP_D;
	u32 savePIPEA_GMCH_DATA_M;
	u32 savePIPEB_GMCH_DATA_M;
	u32 savePIPEA_GMCH_DATA_N;
	u32 savePIPEB_GMCH_DATA_N;
	u32 savePIPEA_DP_LINK_M;
	u32 savePIPEB_DP_LINK_M;
	u32 savePIPEA_DP_LINK_N;
	u32 savePIPEB_DP_LINK_N;
820 821 822 823 824 825 826 827 828 829
	u32 saveFDI_RXA_CTL;
	u32 saveFDI_TXA_CTL;
	u32 saveFDI_RXB_CTL;
	u32 saveFDI_TXB_CTL;
	u32 savePFA_CTL_1;
	u32 savePFB_CTL_1;
	u32 savePFA_WIN_SZ;
	u32 savePFB_WIN_SZ;
	u32 savePFA_WIN_POS;
	u32 savePFB_WIN_POS;
830 831 832 833 834 835 836 837 838 839
	u32 savePCH_DREF_CONTROL;
	u32 saveDISP_ARB_CTL;
	u32 savePIPEA_DATA_M1;
	u32 savePIPEA_DATA_N1;
	u32 savePIPEA_LINK_M1;
	u32 savePIPEA_LINK_N1;
	u32 savePIPEB_DATA_M1;
	u32 savePIPEB_DATA_N1;
	u32 savePIPEB_LINK_M1;
	u32 savePIPEB_LINK_N1;
840
	u32 saveMCHBAR_RENDER_STANDBY;
841
	u32 savePCH_PORT_HOTPLUG;
842
};
843

844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
	u32 clock_gate_dis2;
};

905 906 907 908
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
909 910
};

911
struct intel_gen6_power_mgmt {
912
	/* work and pm_iir are protected by dev_priv->irq_lock */
913 914
	struct work_struct work;
	u32 pm_iir;
915

916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
934

935 936
	u32 ei_interrupt_count;

937 938 939
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

940
	bool enabled;
941
	struct delayed_work delayed_resume_work;
942

943 944 945
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

946 947 948 949 950
	/*
	 * Protects RPS/RC6 register access and PCU communication.
	 * Must be taken after struct_mutex if nested.
	 */
	struct mutex hw_lock;
951 952
};

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Daniel Vetter 已提交
953 954 955
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
	struct timespec last_time2;
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
973 974 975

	struct drm_i915_gem_object *pwrctx;
	struct drm_i915_gem_object *renderctx;
976 977
};

978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1008 1009
/* Power well structure for haswell */
struct i915_power_well {
1010
	const char *name;
1011
	bool always_on;
1012 1013
	/* power well enable/disable usage count */
	int count;
1014 1015
	/* cached hw enabled state */
	bool hw_enabled;
1016
	unsigned long domains;
1017
	unsigned long data;
1018
	const struct i915_power_well_ops *ops;
1019 1020
};

1021
struct i915_power_domains {
1022 1023 1024 1025 1026
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1027
	bool initializing;
1028
	int power_well_count;
1029

1030
	struct mutex lock;
1031
	int domain_use_count[POWER_DOMAIN_NUM];
1032
	struct i915_power_well *power_wells;
1033 1034
};

1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047
struct i915_dri1_state {
	unsigned allow_batchbuffer : 1;
	u32 __iomem *gfx_hws_cpu_addr;

	unsigned int cpp;
	int back_offset;
	int front_offset;
	int current_page;
	int page_flipping;

	uint32_t counter;
};

1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059
struct i915_ums_state {
	/**
	 * Flag if the X Server, and thus DRM, is not currently in
	 * control of the device.
	 *
	 * This is set between LeaveVT and EnterVT.  It needs to be
	 * replaced with a semaphore.  It also needs to be
	 * transitioned away from for kernel modesetting.
	 */
	int mm_suspended;
};

1060
#define MAX_L3_SLICES 2
1061
struct intel_l3_parity {
1062
	u32 *remap_info[MAX_L3_SLICES];
1063
	struct work_struct error_work;
1064
	int which_slice;
1065 1066
};

1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
	 * are idle and not used by the GPU) but still have
	 * (presumably uncached) pages still attached.
	 */
	struct list_head unbound_list;

	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1086
	struct notifier_block oom_notifier;
1087
	struct shrinker shrinker;
1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101
	bool shrinker_no_lock_stealing;

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * We leave the user IRQ off as much as possible,
	 * but this means that requests will finish and never
	 * be retired once the system goes idle. Set a timer to
	 * fire periodically while the ring is running. When it
	 * fires, go retire requests.
	 */
	struct delayed_work retire_work;

1102 1103 1104 1105 1106 1107 1108 1109 1110
	/**
	 * When we detect an idle GPU, we want to turn on
	 * powersaving features. So once we see that there
	 * are no more requests outstanding and no more
	 * arrive within a small period of time, we fire
	 * off the idle_work.
	 */
	struct delayed_work idle_work;

1111 1112 1113 1114 1115 1116
	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1117 1118 1119 1120 1121 1122 1123 1124
	/**
	 * Is the GPU currently considered idle, or busy executing userspace
	 * requests?  Whilst idle, we attempt to power down the hardware and
	 * display clocks. In order to reduce the effect on performance, there
	 * is a slight delay before we do so.
	 */
	bool busy;

1125 1126 1127
	/* the indicator for dispatch video commands on two BSD rings */
	int bsd_ring_dispatch_index;

1128 1129 1130 1131 1132 1133
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1134
	spinlock_t object_stat_lock;
1135 1136 1137 1138
	size_t object_memory;
	u32 object_count;
};

1139 1140 1141 1142 1143 1144 1145 1146 1147
struct drm_i915_error_state_buf {
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1148 1149 1150 1151 1152
struct i915_error_state_file_priv {
	struct drm_device *dev;
	struct drm_i915_error_state *error;
};

1153 1154 1155 1156
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1157 1158 1159
	/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)

1160 1161 1162 1163 1164 1165 1166 1167
	struct timer_list hangcheck_timer;

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
	struct work_struct work;

1168 1169 1170

	unsigned long missed_irq_rings;

1171
	/**
M
Mika Kuoppala 已提交
1172
	 * State variable controlling the reset flow and count
1173
	 *
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Mika Kuoppala 已提交
1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186
	 * This is a counter which gets incremented when reset is triggered,
	 * and again when reset has been handled. So odd values (lowest bit set)
	 * means that reset is in progress and even values that
	 * (reset_counter >> 1):th reset was successfully completed.
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1187 1188 1189 1190
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1191 1192 1193 1194
	 */
	atomic_t reset_counter;

#define I915_RESET_IN_PROGRESS_FLAG	1
M
Mika Kuoppala 已提交
1195
#define I915_WEDGED			(1 << 31)
1196 1197 1198 1199 1200 1201

	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1202

1203 1204 1205 1206 1207 1208
	/* Userspace knobs for gpu hang simulation;
	 * combines both a ring mask, and extra flags
	 */
	u32 stop_rings;
#define I915_STOP_RING_ALLOW_BAN       (1 << 31)
#define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1209 1210 1211

	/* For missed irq/seqno simulation. */
	unsigned int test_irq_rings;
1212 1213
};

1214 1215 1216 1217 1218 1219
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1220 1221
struct ddi_vbt_port_info {
	uint8_t hdmi_level_shift;
1222 1223 1224 1225

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1226 1227
};

1228 1229 1230 1231 1232 1233
enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
};

1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1246
	unsigned int has_mipi:1;
1247 1248 1249
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1250 1251
	enum drrs_support_type drrs_type;

1252 1253 1254 1255 1256 1257 1258 1259 1260 1261
	/* eDP */
	int edp_rate;
	int edp_lanes;
	int edp_preemphasis;
	int edp_vswing;
	bool edp_initialized;
	bool edp_support;
	int edp_bpp;
	struct edp_power_seq edp_pps;

1262 1263
	struct {
		u16 pwm_freq_hz;
1264
		bool present;
1265 1266 1267
		bool active_low_pwm;
	} backlight;

1268 1269
	/* MIPI DSI */
	struct {
1270
		u16 port;
1271
		u16 panel_id;
1272 1273 1274 1275 1276 1277
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
		u8 *sequence[MIPI_SEQ_MAX];
1278 1279
	} dsi;

1280 1281 1282
	int crt_ddc_pin;

	int child_dev_num;
1283
	union child_device_config *child_dev;
1284 1285

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1286 1287
};

1288 1289 1290 1291 1292
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1293 1294 1295 1296 1297 1298 1299 1300
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1301
struct ilk_wm_values {
1302 1303 1304 1305 1306 1307 1308 1309
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1310
/*
1311 1312 1313 1314
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1315
 *
1316 1317 1318
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1319
 *
1320 1321 1322 1323
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
 * default value is currently very conservative (see intel_init_runtime_pm), but
 * it can be changed with the standard runtime PM files from sysfs.
1324 1325 1326 1327 1328
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1329
 * case it happens.
1330
 *
1331
 * For more, read the Documentation/power/runtime_pm.txt.
1332
 */
1333 1334 1335
struct i915_runtime_pm {
	bool suspended;
	bool irqs_disabled;
1336 1337
};

1338 1339 1340 1341 1342
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1343
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1344 1345 1346 1347 1348
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1349
	INTEL_PIPE_CRC_SOURCE_AUTO,
1350 1351 1352
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1353
struct intel_pipe_crc_entry {
1354
	uint32_t frame;
1355 1356 1357
	uint32_t crc[5];
};

1358
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1359
struct intel_pipe_crc {
1360 1361
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1362
	struct intel_pipe_crc_entry *entries;
1363
	enum intel_pipe_crc_source source;
1364
	int head, tail;
1365
	wait_queue_head_t wq;
1366 1367
};

1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378
struct i915_frontbuffer_tracking {
	struct mutex lock;

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1379
struct drm_i915_private {
1380
	struct drm_device *dev;
1381
	struct kmem_cache *slab;
1382

1383
	const struct intel_device_info info;
1384 1385 1386 1387 1388

	int relative_constants_mode;

	void __iomem *regs;

1389
	struct intel_uncore uncore;
1390 1391 1392

	struct intel_gmbus gmbus[GMBUS_NUM_PORTS];

1393

1394 1395 1396 1397 1398 1399 1400 1401 1402
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1403 1404 1405
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1406 1407
	wait_queue_head_t gmbus_wait_queue;

1408
	struct pci_dev *bridge_dev;
1409
	struct intel_engine_cs ring[I915_NUM_RINGS];
1410
	struct drm_i915_gem_object *semaphore_obj;
1411
	uint32_t last_seqno, next_seqno;
1412 1413 1414 1415 1416 1417 1418

	drm_dma_handle_t *status_page_dmah;
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1419 1420 1421
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1422 1423
	bool display_irqs_enabled;

1424 1425 1426
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

1427
	/* DPIO indirect register protection */
1428
	struct mutex dpio_lock;
1429 1430

	/** Cached value of IMR to avoid reads in updating the bitfield */
1431 1432 1433 1434
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1435
	u32 gt_irq_mask;
1436
	u32 pm_irq_mask;
1437
	u32 pm_rps_events;
1438
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1439 1440

	struct work_struct hotplug_work;
1441
	bool enable_hotplug_processing;
1442 1443 1444 1445 1446 1447 1448 1449 1450
	struct {
		unsigned long hpd_last_jiffies;
		int hpd_cnt;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} hpd_mark;
	} hpd_stats[HPD_NUM_PINS];
1451
	u32 hpd_event_bits;
1452
	struct timer_list hotplug_reenable_timer;
1453

1454
	struct i915_fbc fbc;
1455
	struct i915_drrs drrs;
1456
	struct intel_opregion opregion;
1457
	struct intel_vbt_data vbt;
1458 1459 1460 1461

	/* overlay */
	struct intel_overlay *overlay;

1462 1463
	/* backlight registers and fields in struct intel_panel */
	spinlock_t backlight_lock;
1464

1465 1466 1467 1468 1469 1470 1471 1472
	/* LVDS info */
	bool no_aux_handshake;

	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1473
	unsigned int vlv_cdclk_freq;
1474

1475 1476 1477 1478 1479 1480 1481
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1482 1483 1484 1485 1486 1487 1488
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1489
	unsigned short pch_id;
1490 1491 1492

	unsigned long quirks;

1493 1494
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1495

1496
	struct list_head vm_list; /* Global list of all address spaces */
1497
	struct i915_gtt gtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1498

1499
	struct i915_gem_mm mm;
1500 1501 1502
#if defined(CONFIG_MMU_NOTIFIER)
	DECLARE_HASHTABLE(mmu_notifiers, 7);
#endif
1503 1504 1505

	/* Kernel Modesetting */

1506
	struct sdvo_device_mapping sdvo_mappings[2];
1507

1508 1509
	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1510 1511
	wait_queue_head_t pending_flip_queue;

1512 1513 1514 1515
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

D
Daniel Vetter 已提交
1516 1517
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1518
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1519

1520 1521 1522
	/* Reclocking support */
	bool render_reclock_avail;
	bool lvds_downclock_avail;
1523 1524
	/* indicates the reduced downclock for LVDS*/
	int lvds_downclock;
1525 1526 1527

	struct i915_frontbuffer_tracking fb_tracking;

1528
	u16 orig_clock;
1529

1530
	bool mchbar_need_disable;
1531

1532 1533
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1534 1535 1536
	/* Cannot be determined by PCIID. You must always read a register. */
	size_t ellc_size;

1537
	/* gen6+ rps state */
1538
	struct intel_gen6_power_mgmt rps;
1539

1540 1541
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1542
	struct intel_ilk_power_mgmt ips;
1543

1544
	struct i915_power_domains power_domains;
1545

R
Rodrigo Vivi 已提交
1546
	struct i915_psr psr;
1547

1548
	struct i915_gpu_error gpu_error;
1549

1550 1551
	struct drm_i915_gem_object *vlv_pctx;

1552
#ifdef CONFIG_DRM_I915_FBDEV
1553 1554
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1555
#endif
1556

1557 1558 1559 1560 1561 1562
	/*
	 * The console may be contended at resume, but we don't
	 * want it to block on it.
	 */
	struct work_struct console_resume_work;

1563
	struct drm_property *broadcast_rgb_property;
1564
	struct drm_property *force_audio_property;
1565

1566
	uint32_t hw_context_size;
1567
	struct list_head context_list;
1568

1569
	u32 fdi_rx_config;
1570

1571
	u32 suspend_count;
1572
	struct i915_suspend_saved_registers regfile;
1573
	struct vlv_s0ix_state vlv_s0ix_state;
1574

1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
1587 1588

		/* current hardware state */
1589
		struct ilk_wm_values hw;
1590 1591
	} wm;

1592 1593
	struct i915_runtime_pm pm;

1594 1595 1596 1597 1598
	struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
	u32 long_hpd_port_mask;
	u32 short_hpd_port_mask;
	struct work_struct dig_port_work;

1599 1600 1601
	/* Old dri1 support infrastructure, beware the dragons ya fools entering
	 * here! */
	struct i915_dri1_state dri1;
1602 1603
	/* Old ums support infrastructure, same warning applies. */
	struct i915_ums_state ums;
1604 1605 1606 1607 1608

	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
1609
};
L
Linus Torvalds 已提交
1610

1611 1612 1613 1614 1615
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
	return dev->dev_private;
}

1616 1617 1618 1619 1620
/* Iterate over initialised rings */
#define for_each_ring(ring__, dev_priv__, i__) \
	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
		if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))

1621 1622 1623 1624 1625 1626 1627
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

1628
#define I915_GTT_OFFSET_NONE ((u32)-1)
1629

1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645
struct drm_i915_gem_object_ops {
	/* Interface between the GEM object and its backing storage.
	 * get_pages() is called once prior to the use of the associated set
	 * of pages before to binding them into the GTT, and put_pages() is
	 * called after we no longer need them. As we expect there to be
	 * associated cost with migrating pages between the backing storage
	 * and making them available for the GPU (e.g. clflush), we may hold
	 * onto the pages after they are no longer referenced by the GPU
	 * in case they may be used again shortly (for example migrating the
	 * pages to a different memory domain within the GTT). put_pages()
	 * will therefore most likely be called when the object itself is
	 * being released or under memory pressure (where we attempt to
	 * reap pages for the shrinker).
	 */
	int (*get_pages)(struct drm_i915_gem_object *);
	void (*put_pages)(struct drm_i915_gem_object *);
1646 1647
	int (*dmabuf_export)(struct drm_i915_gem_object *);
	void (*release)(struct drm_i915_gem_object *);
1648 1649
};

1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
 * considered to be the frontbuffer for the given plane interface-vise. This
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
#define INTEL_FRONTBUFFER_BITS \
	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
	(1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe) \
	(1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
	(1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1669 1670
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
	(0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1671

1672
struct drm_i915_gem_object {
1673
	struct drm_gem_object base;
1674

1675 1676
	const struct drm_i915_gem_object_ops *ops;

B
Ben Widawsky 已提交
1677 1678 1679
	/** List of VMAs backed by this object */
	struct list_head vma_list;

1680 1681
	/** Stolen memory for this object, instead of being backed by shmem. */
	struct drm_mm_node *stolen;
1682
	struct list_head global_list;
1683

1684
	struct list_head ring_list;
1685 1686
	/** Used in execbuf to temporarily hold a ref */
	struct list_head obj_exec_link;
1687 1688

	/**
1689 1690 1691
	 * This is set if the object is on the active lists (has pending
	 * rendering and so a non-zero seqno), and is not set if it i s on
	 * inactive (ready to be unbound) list.
1692
	 */
1693
	unsigned int active:1;
1694 1695 1696 1697 1698

	/**
	 * This is set if the object has been written to since last bound
	 * to the GTT
	 */
1699
	unsigned int dirty:1;
1700 1701 1702 1703 1704 1705

	/**
	 * Fence register bits (if any) for this object.  Will be set
	 * as needed when mapped into the GTT.
	 * Protected by dev->struct_mutex.
	 */
1706
	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1707 1708 1709 1710

	/**
	 * Advice: are the backing pages purgeable?
	 */
1711
	unsigned int madv:2;
1712 1713 1714 1715

	/**
	 * Current tiling mode for the object.
	 */
1716
	unsigned int tiling_mode:2;
1717 1718 1719 1720 1721 1722 1723 1724
	/**
	 * Whether the tiling parameters for the currently associated fence
	 * register have changed. Note that for the purposes of tracking
	 * tiling changes we also treat the unfenced register, the register
	 * slot that the object occupies whilst it executes a fenced
	 * command (such as BLT on gen2/3), as a "fence".
	 */
	unsigned int fence_dirty:1;
1725

1726 1727 1728 1729
	/**
	 * Is the object at the current location in the gtt mappable and
	 * fenceable? Used to avoid costly recalculations.
	 */
1730
	unsigned int map_and_fenceable:1;
1731

1732 1733 1734 1735 1736
	/**
	 * Whether the current gtt mapping needs to be mappable (and isn't just
	 * mappable by accident). Track pin and fault separate for a more
	 * accurate mappable working set.
	 */
1737 1738
	unsigned int fault_mappable:1;
	unsigned int pin_mappable:1;
1739
	unsigned int pin_display:1;
1740

1741 1742 1743 1744 1745 1746
	/*
	 * Is the object to be mapped as read-only to the GPU
	 * Only honoured if hardware has relevant pte bit
	 */
	unsigned long gt_ro:1;

1747 1748 1749 1750 1751 1752
	/*
	 * Is the GPU currently using a fence to access this buffer,
	 */
	unsigned int pending_fenced_gpu_access:1;
	unsigned int fenced_gpu_access:1;

1753
	unsigned int cache_level:3;
1754

1755
	unsigned int has_aliasing_ppgtt_mapping:1;
1756
	unsigned int has_global_gtt_mapping:1;
1757
	unsigned int has_dma_mapping:1;
1758

1759 1760
	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;

1761
	struct sg_table *pages;
1762
	int pages_pin_count;
1763

1764
	/* prime dma-buf support */
1765 1766 1767
	void *dma_buf_vmapping;
	int vmapping_count;

1768
	struct intel_engine_cs *ring;
1769

1770
	/** Breadcrumb of last rendering to the buffer. */
1771 1772
	uint32_t last_read_seqno;
	uint32_t last_write_seqno;
1773 1774
	/** Breadcrumb of last fenced GPU access to the buffer. */
	uint32_t last_fenced_seqno;
1775

1776
	/** Current tiling stride for the object, if it's tiled. */
1777
	uint32_t stride;
1778

1779 1780 1781
	/** References from framebuffers, locks out tiling changes. */
	unsigned long framebuffer_references;

1782
	/** Record of address bit 17 of each page at last unbind. */
1783
	unsigned long *bit_17;
1784

J
Jesse Barnes 已提交
1785
	/** User space pin count and filp owning the pin */
1786
	unsigned long user_pin_count;
J
Jesse Barnes 已提交
1787
	struct drm_file *pin_filp;
1788 1789

	/** for phy allocated objects */
1790
	drm_dma_handle_t *phys_handle;
1791

1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804
	union {
		struct i915_gem_userptr {
			uintptr_t ptr;
			unsigned read_only :1;
			unsigned workers :4;
#define I915_GEM_USERPTR_MAX_WORKERS 15

			struct mm_struct *mm;
			struct i915_mmu_object *mn;
			struct work_struct *work;
		} userptr;
	};
};
1805
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1806

1807 1808 1809 1810
void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821
/**
 * Request queue structure.
 *
 * The request queue allows us to note sequence numbers that have been emitted
 * and may be associated with active buffers to be retired.
 *
 * By keeping this list, we can avoid having to do questionable
 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 * an emission time with seqnos for tracking how far ahead of the GPU we are.
 */
struct drm_i915_gem_request {
1822
	/** On Which ring this request was generated */
1823
	struct intel_engine_cs *ring;
1824

1825 1826 1827
	/** GEM sequence number associated with this request. */
	uint32_t seqno;

1828 1829 1830 1831
	/** Position in the ringbuffer of the start of the request */
	u32 head;

	/** Position in the ringbuffer of the end of the request */
1832 1833
	u32 tail;

1834
	/** Context related to this request */
1835
	struct intel_context *ctx;
1836

1837 1838 1839
	/** Batch buffer related to this request if any */
	struct drm_i915_gem_object *batch_obj;

1840 1841 1842
	/** Time at which this request was emitted, in jiffies. */
	unsigned long emitted_jiffies;

1843
	/** global list entry for this request */
1844
	struct list_head list;
1845

1846
	struct drm_i915_file_private *file_priv;
1847 1848
	/** file_priv list entry for this request */
	struct list_head client_list;
1849 1850 1851
};

struct drm_i915_file_private {
1852
	struct drm_i915_private *dev_priv;
1853
	struct drm_file *file;
1854

1855
	struct {
1856
		spinlock_t lock;
1857
		struct list_head request_list;
1858
		struct delayed_work idle_work;
1859
	} mm;
1860
	struct idr context_idr;
1861

1862
	atomic_t rps_wait_boost;
1863
	struct  intel_engine_cs *bsd_ring;
1864 1865
};

1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930
/*
 * A command that requires special handling by the command parser.
 */
struct drm_i915_cmd_descriptor {
	/*
	 * Flags describing how the command parser processes the command.
	 *
	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
	 *                 a length mask if not set
	 * CMD_DESC_SKIP: The command is allowed but does not follow the
	 *                standard length encoding for the opcode range in
	 *                which it falls
	 * CMD_DESC_REJECT: The command is never allowed
	 * CMD_DESC_REGISTER: The command should be checked against the
	 *                    register whitelist for the appropriate ring
	 * CMD_DESC_MASTER: The command is allowed if the submitting process
	 *                  is the DRM master
	 */
	u32 flags;
#define CMD_DESC_FIXED    (1<<0)
#define CMD_DESC_SKIP     (1<<1)
#define CMD_DESC_REJECT   (1<<2)
#define CMD_DESC_REGISTER (1<<3)
#define CMD_DESC_BITMASK  (1<<4)
#define CMD_DESC_MASTER   (1<<5)

	/*
	 * The command's unique identification bits and the bitmask to get them.
	 * This isn't strictly the opcode field as defined in the spec and may
	 * also include type, subtype, and/or subop fields.
	 */
	struct {
		u32 value;
		u32 mask;
	} cmd;

	/*
	 * The command's length. The command is either fixed length (i.e. does
	 * not include a length field) or has a length field mask. The flag
	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
	 * a length mask. All command entries in a command table must include
	 * length information.
	 */
	union {
		u32 fixed;
		u32 mask;
	} length;

	/*
	 * Describes where to find a register address in the command to check
	 * against the ring's register whitelist. Only valid if flags has the
	 * CMD_DESC_REGISTER bit set.
	 */
	struct {
		u32 offset;
		u32 mask;
	} reg;

#define MAX_CMD_DESC_BITMASKS 3
	/*
	 * Describes command checks where a particular dword is masked and
	 * compared against an expected value. If the command does not match
	 * the expected value, the parser rejects it. Only valid if flags has
	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
	 * are valid.
1931 1932 1933 1934
	 *
	 * If the check specifies a non-zero condition_mask then the parser
	 * only performs the check when the bits specified by condition_mask
	 * are non-zero.
1935 1936 1937 1938 1939
	 */
	struct {
		u32 offset;
		u32 mask;
		u32 expected;
1940 1941
		u32 condition_offset;
		u32 condition_mask;
1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955
	} bits[MAX_CMD_DESC_BITMASKS];
};

/*
 * A table of commands requiring special handling by the command parser.
 *
 * Each ring has an array of tables. Each table consists of an array of command
 * descriptors, which must be sorted with command opcodes in ascending order.
 */
struct drm_i915_cmd_table {
	const struct drm_i915_cmd_descriptor *table;
	int count;
};

1956
#define INTEL_INFO(dev)	(&to_i915(dev)->info)
1957

1958 1959
#define IS_I830(dev)		((dev)->pdev->device == 0x3577)
#define IS_845G(dev)		((dev)->pdev->device == 0x2562)
1960
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
1961
#define IS_I865G(dev)		((dev)->pdev->device == 0x2572)
1962
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
1963 1964
#define IS_I915GM(dev)		((dev)->pdev->device == 0x2592)
#define IS_I945G(dev)		((dev)->pdev->device == 0x2772)
1965 1966 1967
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
1968
#define IS_GM45(dev)		((dev)->pdev->device == 0x2A42)
1969
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
1970 1971
#define IS_PINEVIEW_G(dev)	((dev)->pdev->device == 0xa001)
#define IS_PINEVIEW_M(dev)	((dev)->pdev->device == 0xa011)
1972 1973
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
1974
#define IS_IRONLAKE_M(dev)	((dev)->pdev->device == 0x0046)
1975
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
1976 1977 1978 1979 1980 1981
#define IS_IVB_GT1(dev)		((dev)->pdev->device == 0x0156 || \
				 (dev)->pdev->device == 0x0152 || \
				 (dev)->pdev->device == 0x015a)
#define IS_SNB_GT1(dev)		((dev)->pdev->device == 0x0102 || \
				 (dev)->pdev->device == 0x0106 || \
				 (dev)->pdev->device == 0x010A)
1982
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
1983
#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1984
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
1985
#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1986
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
1987
#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
1988
				 ((dev)->pdev->device & 0xFF00) == 0x0C00)
B
Ben Widawsky 已提交
1989 1990 1991 1992 1993
#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
				 (((dev)->pdev->device & 0xf) == 0x2  || \
				 ((dev)->pdev->device & 0xf) == 0x6 || \
				 ((dev)->pdev->device & 0xf) == 0xe))
#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
1994
				 ((dev)->pdev->device & 0xFF00) == 0x0A00)
B
Ben Widawsky 已提交
1995
#define IS_ULT(dev)		(IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1996
#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
1997
				 ((dev)->pdev->device & 0x00F0) == 0x0020)
1998 1999 2000
/* ULX machines are also considered ULT. */
#define IS_HSW_ULX(dev)		((dev)->pdev->device == 0x0A0E || \
				 (dev)->pdev->device == 0x0A1E)
2001
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2002

2003 2004 2005 2006 2007 2008
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2009 2010 2011 2012 2013
#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
2014
#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
B
Ben Widawsky 已提交
2015
#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen == 8)
2016

2017 2018 2019 2020
#define RENDER_RING		(1<<RCS)
#define BSD_RING		(1<<VCS)
#define BLT_RING		(1<<BCS)
#define VEBOX_RING		(1<<VECS)
2021
#define BSD2_RING		(1<<VCS2)
2022
#define HAS_BSD(dev)		(INTEL_INFO(dev)->ring_mask & BSD_RING)
2023
#define HAS_BSD2(dev)		(INTEL_INFO(dev)->ring_mask & BSD2_RING)
2024 2025 2026 2027 2028
#define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
#define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
				 to_i915(dev)->ellc_size)
2029 2030
#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)

2031
#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
J
Jesse Barnes 已提交
2032 2033
#define HAS_ALIASING_PPGTT(dev)	(INTEL_INFO(dev)->gen >= 6)
#define HAS_PPGTT(dev)		(INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
2034
#define USES_PPGTT(dev)		intel_enable_ppgtt(dev, false)
2035
#define USES_FULL_PPGTT(dev)	intel_enable_ppgtt(dev, true)
2036

2037
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2038 2039
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

2040 2041
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2042 2043 2044 2045 2046 2047 2048 2049
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2050

2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_DIGITAL_OUTPUTS(dev)	(!IS_GEN2(dev) && !IS_PINEVIEW(dev))
#define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2064
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2065

2066
#define HAS_IPS(dev)		(IS_ULT(dev) || IS_BROADWELL(dev))
2067

2068
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2069
#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
B
Ben Widawsky 已提交
2070
#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))
2071
#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
I
Imre Deak 已提交
2072
				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
P
Paulo Zanoni 已提交
2073

2074 2075 2076 2077 2078 2079 2080
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00

2081
#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2082
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2083 2084
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
B
Ben Widawsky 已提交
2085
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2086
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2087

2088 2089 2090
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2091

2092 2093
#define GT_FREQUENCY_MULTIPLIER 50

2094 2095
#include "i915_trace.h"

R
Rob Clark 已提交
2096
extern const struct drm_ioctl_desc i915_ioctls[];
2097 2098
extern int i915_max_ioctl;

2099 2100
extern int i915_suspend(struct drm_device *dev, pm_message_t state);
extern int i915_resume(struct drm_device *dev);
2101 2102 2103
extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);

2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120
/* i915_params.c */
struct i915_params {
	int modeset;
	int panel_ignore_lid;
	unsigned int powersave;
	int semaphores;
	unsigned int lvds_downclock;
	int lvds_channel_mode;
	int panel_use_ssc;
	int vbt_sdvo_panel_type;
	int enable_rc6;
	int enable_fbc;
	int enable_ppgtt;
	int enable_psr;
	unsigned int preliminary_hw_support;
	int disable_power_well;
	int enable_ips;
2121
	int invert_brightness;
2122
	int enable_cmd_parser;
2123 2124 2125
	/* leave bools at the end to not create holes */
	bool enable_hangcheck;
	bool fastboot;
2126 2127
	bool prefault_disable;
	bool reset;
2128
	bool disable_display;
2129
	bool disable_vtd_wa;
2130
	int use_mmio_flip;
2131 2132 2133
};
extern struct i915_params i915 __read_mostly;

L
Linus Torvalds 已提交
2134
				/* i915_dma.c */
2135
void i915_update_dri1_breadcrumb(struct drm_device *dev);
2136
extern void i915_kernel_lost_context(struct drm_device * dev);
2137
extern int i915_driver_load(struct drm_device *, unsigned long flags);
J
Jesse Barnes 已提交
2138
extern int i915_driver_unload(struct drm_device *);
2139
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2140
extern void i915_driver_lastclose(struct drm_device * dev);
2141
extern void i915_driver_preclose(struct drm_device *dev,
2142
				 struct drm_file *file);
2143
extern void i915_driver_postclose(struct drm_device *dev,
2144
				  struct drm_file *file);
2145
extern int i915_driver_device_is_agp(struct drm_device * dev);
2146
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2147 2148
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2149
#endif
2150
extern int i915_emit_box(struct drm_device *dev,
2151 2152
			 struct drm_clip_rect *box,
			 int DR1, int DR4);
2153
extern int intel_gpu_reset(struct drm_device *dev);
2154
extern int i915_reset(struct drm_device *dev);
2155 2156 2157 2158
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2159
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2160

2161
extern void intel_console_resume(struct work_struct *work);
2162

L
Linus Torvalds 已提交
2163
/* i915_irq.c */
2164
void i915_queue_hangcheck(struct drm_device *dev);
2165 2166 2167
__printf(3, 4)
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2168

2169 2170
void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
							int new_delay);
2171
extern void intel_irq_init(struct drm_device *dev);
2172
extern void intel_hpd_init(struct drm_device *dev);
2173 2174

extern void intel_uncore_sanitize(struct drm_device *dev);
2175 2176
extern void intel_uncore_early_sanitize(struct drm_device *dev,
					bool restore_forcewake);
2177 2178
extern void intel_uncore_init(struct drm_device *dev);
extern void intel_uncore_check_errors(struct drm_device *dev);
2179
extern void intel_uncore_fini(struct drm_device *dev);
2180
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2181

2182
void
2183
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2184
		     u32 status_mask);
2185 2186

void
2187
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2188
		      u32 status_mask);
2189

2190 2191 2192
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);

2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203
/* i915_gem.c */
int i915_gem_init_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2204 2205
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2206 2207 2208 2209 2210 2211
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
2212 2213
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
2214 2215 2216 2217 2218 2219
int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv);
int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
2220 2221 2222 2223
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2224 2225
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
2226 2227
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
2228 2229 2230 2231 2232 2233 2234 2235
int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2236 2237 2238
int i915_gem_init_userptr(struct drm_device *dev);
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
2239 2240
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
2241 2242
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2243
void i915_gem_load(struct drm_device *dev);
2244 2245
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
2246 2247
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
2248 2249
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size);
2250 2251
void i915_init_vm(struct drm_i915_private *dev_priv,
		  struct i915_address_space *vm);
2252
void i915_gem_free_object(struct drm_gem_object *obj);
B
Ben Widawsky 已提交
2253
void i915_gem_vma_destroy(struct i915_vma *vma);
2254

2255 2256
#define PIN_MAPPABLE 0x1
#define PIN_NONBLOCK 0x2
2257
#define PIN_GLOBAL 0x4
2258 2259
#define PIN_OFFSET_BIAS 0x8
#define PIN_OFFSET_MASK (~4095)
2260
int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
B
Ben Widawsky 已提交
2261
				     struct i915_address_space *vm,
2262
				     uint32_t alignment,
2263
				     uint64_t flags);
2264
int __must_check i915_vma_unbind(struct i915_vma *vma);
2265
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2266
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2267
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2268
void i915_gem_lastclose(struct drm_device *dev);
2269

2270 2271 2272
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    int *needs_clflush);

2273
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2274 2275
static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
{
2276 2277 2278
	struct sg_page_iter sg_iter;

	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2279
		return sg_page_iter_page(&sg_iter);
2280 2281

	return NULL;
2282
}
2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293
static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages == NULL);
	obj->pages_pin_count++;
}
static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages_pin_count == 0);
	obj->pages_pin_count--;
}

2294
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2295
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2296
			 struct intel_engine_cs *to);
B
Ben Widawsky 已提交
2297
void i915_vma_move_to_active(struct i915_vma *vma,
2298
			     struct intel_engine_cs *ring);
2299 2300 2301 2302 2303
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
2304 2305 2306 2307 2308 2309 2310 2311 2312
/**
 * Returns true if seq1 is later than seq2.
 */
static inline bool
i915_seqno_passed(uint32_t seq1, uint32_t seq2)
{
	return (int32_t)(seq1 - seq2) >= 0;
}

2313 2314
int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2315
int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2316
int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2317

2318 2319
bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2320

2321
struct drm_i915_gem_request *
2322
i915_gem_find_active_request(struct intel_engine_cs *ring);
2323

2324
bool i915_gem_retire_requests(struct drm_device *dev);
2325
void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2326
int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2327
				      bool interruptible);
2328 2329
int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);

2330 2331 2332
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
	return unlikely(atomic_read(&error->reset_counter)
M
Mika Kuoppala 已提交
2333
			& (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2334 2335 2336 2337
}

static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
M
Mika Kuoppala 已提交
2338 2339 2340 2341 2342 2343
	return atomic_read(&error->reset_counter) & I915_WEDGED;
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
	return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2344
}
2345

2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357
static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
}

static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
}

2358
void i915_gem_reset(struct drm_device *dev);
2359
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2360
int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2361
int __must_check i915_gem_init(struct drm_device *dev);
2362
int __must_check i915_gem_init_hw(struct drm_device *dev);
2363
int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2364
void i915_gem_init_swizzling(struct drm_device *dev);
J
Jesse Barnes 已提交
2365
void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2366
int __must_check i915_gpu_idle(struct drm_device *dev);
2367
int __must_check i915_gem_suspend(struct drm_device *dev);
2368
int __i915_add_request(struct intel_engine_cs *ring,
2369
		       struct drm_file *file,
2370
		       struct drm_i915_gem_object *batch_obj,
2371 2372
		       u32 *seqno);
#define i915_add_request(ring, seqno) \
2373
	__i915_add_request(ring, NULL, NULL, seqno)
2374
int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
2375
				 uint32_t seqno);
2376
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2377 2378 2379 2380
int __must_check
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
2381 2382
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
2383 2384
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
2385
				     struct intel_engine_cs *pipelined);
2386
void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2387
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2388
				int align);
2389
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2390
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2391

2392 2393
uint32_t
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2394
uint32_t
2395 2396
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
			    int tiling_mode, bool fenced);
2397

2398 2399 2400
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

2401 2402 2403 2404 2405 2406
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

2407 2408
void i915_gem_restore_fences(struct drm_device *dev);

2409 2410 2411 2412 2413 2414 2415 2416 2417
unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
				  struct i915_address_space *vm);
bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
			struct i915_address_space *vm);
unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
				struct i915_address_space *vm);
struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
				     struct i915_address_space *vm);
2418 2419 2420
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
				  struct i915_address_space *vm);
2421 2422

struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
B
Ben Widawsky 已提交
2423 2424 2425 2426 2427 2428 2429
static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
	struct i915_vma *vma;
	list_for_each_entry(vma, &obj->vma_list, vma_link)
		if (vma->pin_count > 0)
			return true;
	return false;
}
2430

2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456
/* Some GGTT VM helpers */
#define obj_to_ggtt(obj) \
	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
static inline bool i915_is_ggtt(struct i915_address_space *vm)
{
	struct i915_address_space *ggtt =
		&((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
	return vm == ggtt;
}

static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
{
	return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
}

static inline unsigned long
i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
{
	return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
}

static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
{
	return i915_gem_obj_size(obj, obj_to_ggtt(obj));
}
B
Ben Widawsky 已提交
2457 2458 2459 2460

static inline int __must_check
i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
		      uint32_t alignment,
2461
		      unsigned flags)
B
Ben Widawsky 已提交
2462
{
2463
	return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
B
Ben Widawsky 已提交
2464
}
2465

2466 2467 2468 2469 2470 2471 2472 2473
static inline int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
{
	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
}

void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);

2474
/* i915_gem_context.c */
2475
#define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2476
int __must_check i915_gem_context_init(struct drm_device *dev);
2477
void i915_gem_context_fini(struct drm_device *dev);
2478
void i915_gem_context_reset(struct drm_device *dev);
2479
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2480
int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2481
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2482
int i915_switch_context(struct intel_engine_cs *ring,
2483 2484
			struct intel_context *to);
struct intel_context *
2485
i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2486
void i915_gem_context_free(struct kref *ctx_ref);
2487
static inline void i915_gem_context_reference(struct intel_context *ctx)
2488
{
2489
	kref_get(&ctx->ref);
2490 2491
}

2492
static inline void i915_gem_context_unreference(struct intel_context *ctx)
2493
{
2494
	kref_put(&ctx->ref, i915_gem_context_free);
2495 2496
}

2497
static inline bool i915_gem_context_is_default(const struct intel_context *c)
2498
{
2499
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2500 2501
}

2502 2503 2504 2505
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
2506

2507
/* i915_gem_render_state.c */
2508
int i915_gem_render_state_init(struct intel_engine_cs *ring);
2509 2510 2511 2512 2513 2514
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct drm_device *dev,
					  struct i915_address_space *vm,
					  int min_size,
					  unsigned alignment,
					  unsigned cache_level,
2515 2516
					  unsigned long start,
					  unsigned long end,
2517
					  unsigned flags);
2518 2519
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
int i915_gem_evict_everything(struct drm_device *dev);
2520

2521
/* belongs in i915_gem_gtt.h */
2522
static inline void i915_gem_chipset_flush(struct drm_device *dev)
2523 2524 2525 2526
{
	if (INTEL_INFO(dev)->gen < 6)
		intel_gtt_chipset_flush();
}
2527

2528 2529
/* i915_gem_stolen.c */
int i915_gem_init_stolen(struct drm_device *dev);
B
Ben Widawsky 已提交
2530
int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2531
void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2532
void i915_gem_cleanup_stolen(struct drm_device *dev);
2533 2534
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2535 2536 2537 2538 2539
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
2540

2541
/* i915_gem_tiling.c */
2542
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2543
{
2544
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2545 2546 2547 2548 2549

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		obj->tiling_mode != I915_TILING_NONE;
}

2550
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2551 2552
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2553 2554

/* i915_gem_debug.c */
2555 2556
#if WATCH_LISTS
int i915_verify_lists(struct drm_device *dev);
2557
#else
2558
#define i915_verify_lists(dev) 0
2559
#endif
L
Linus Torvalds 已提交
2560

2561
/* i915_debugfs.c */
2562 2563
int i915_debugfs_init(struct drm_minor *minor);
void i915_debugfs_cleanup(struct drm_minor *minor);
2564
#ifdef CONFIG_DEBUG_FS
2565 2566
void intel_display_crc_init(struct drm_device *dev);
#else
2567
static inline void intel_display_crc_init(struct drm_device *dev) {}
2568
#endif
2569 2570

/* i915_gpu_error.c */
2571 2572
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2573 2574
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
2575 2576 2577 2578 2579 2580 2581
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
2582 2583
void i915_capture_error_state(struct drm_device *dev, bool wedge,
			      const char *error_msg);
2584 2585 2586 2587 2588 2589 2590
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);

void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
const char *i915_cache_level_str(int type);
2591

2592
/* i915_cmd_parser.c */
2593
int i915_cmd_parser_get_version(void);
2594 2595 2596 2597
int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
int i915_parse_cmds(struct intel_engine_cs *ring,
2598 2599 2600 2601
		    struct drm_i915_gem_object *batch_obj,
		    u32 batch_start_offset,
		    bool is_master);

2602 2603 2604
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
2605

2606 2607 2608
/* i915_ums.c */
void i915_save_display_reg(struct drm_device *dev);
void i915_restore_display_reg(struct drm_device *dev);
2609

B
Ben Widawsky 已提交
2610 2611 2612 2613
/* i915_sysfs.c */
void i915_setup_sysfs(struct drm_device *dev_priv);
void i915_teardown_sysfs(struct drm_device *dev_priv);

2614 2615 2616
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
2617
static inline bool intel_gmbus_is_port_valid(unsigned port)
2618
{
2619
	return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2620 2621 2622 2623
}

extern struct i2c_adapter *intel_gmbus_get_adapter(
		struct drm_i915_private *dev_priv, unsigned port);
C
Chris Wilson 已提交
2624 2625
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2626
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2627 2628 2629
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
2630 2631
extern void intel_i2c_reset(struct drm_device *dev);

2632
/* intel_opregion.c */
2633
struct intel_encoder;
2634
#ifdef CONFIG_ACPI
2635
extern int intel_opregion_setup(struct drm_device *dev);
2636 2637
extern void intel_opregion_init(struct drm_device *dev);
extern void intel_opregion_fini(struct drm_device *dev);
2638
extern void intel_opregion_asle_intr(struct drm_device *dev);
2639 2640
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
2641 2642
extern int intel_opregion_notify_adapter(struct drm_device *dev,
					 pci_power_t state);
2643
#else
2644
static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2645 2646
static inline void intel_opregion_init(struct drm_device *dev) { return; }
static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2647
static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2648 2649 2650 2651 2652
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
2653 2654 2655 2656 2657
static inline int
intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
{
	return 0;
}
2658
#endif
2659

J
Jesse Barnes 已提交
2660 2661 2662 2663 2664 2665 2666 2667 2668
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

J
Jesse Barnes 已提交
2669
/* modesetting */
2670
extern void intel_modeset_init_hw(struct drm_device *dev);
2671
extern void intel_modeset_suspend_hw(struct drm_device *dev);
J
Jesse Barnes 已提交
2672
extern void intel_modeset_init(struct drm_device *dev);
2673
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
2674
extern void intel_modeset_cleanup(struct drm_device *dev);
2675
extern void intel_connector_unregister(struct intel_connector *);
2676
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2677 2678
extern void intel_modeset_setup_hw_state(struct drm_device *dev,
					 bool force_restore);
2679
extern void i915_redisable_vga(struct drm_device *dev);
2680
extern void i915_redisable_vga_power_on(struct drm_device *dev);
2681
extern bool intel_fbc_enabled(struct drm_device *dev);
2682
extern void intel_disable_fbc(struct drm_device *dev);
2683
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
P
Paulo Zanoni 已提交
2684
extern void intel_init_pch_refclk(struct drm_device *dev);
2685
extern void gen6_set_rps(struct drm_device *dev, u8 val);
2686
extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2687 2688
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
				  bool enable);
2689 2690
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
B
Ben Widawsky 已提交
2691
extern int intel_enable_rc6(const struct drm_device *dev);
2692

2693
extern bool i915_semaphore_is_enabled(struct drm_device *dev);
B
Ben Widawsky 已提交
2694 2695
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
2696 2697
int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2698

2699 2700
void intel_notify_mmio_flip(struct intel_engine_cs *ring);

2701 2702
/* overlay */
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2703 2704
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
2705 2706

extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2707
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2708 2709
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
2710

B
Ben Widawsky 已提交
2711 2712 2713 2714
/* On SNB platform, before reading ring registers forcewake bit
 * must be set to prevent GT core from power down and stale values being
 * returned.
 */
2715 2716
void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2717
void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
2718

B
Ben Widawsky 已提交
2719 2720
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2721 2722

/* intel_sideband.c */
2723 2724 2725
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2726 2727 2728 2729 2730 2731
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2732 2733
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2734 2735
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2736 2737
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2738 2739 2740 2741
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
2742 2743
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2744

2745 2746
int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
B
Ben Widawsky 已提交
2747

2748 2749 2750 2751 2752
#define FORCEWAKE_RENDER	(1 << 0)
#define FORCEWAKE_MEDIA		(1 << 1)
#define FORCEWAKE_ALL		(FORCEWAKE_RENDER | FORCEWAKE_MEDIA)


2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

2766 2767 2768 2769 2770 2771
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
 * machine death. You have been warned.
 */
2772 2773
#define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2774

2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
		u32 upper = I915_READ(upper_reg);			\
		u32 lower = I915_READ(lower_reg);			\
		u32 tmp = I915_READ(upper_reg);				\
		if (upper != tmp) {					\
			upper = tmp;					\
			lower = I915_READ(lower_reg);			\
			WARN_ON(I915_READ(upper_reg) != upper);		\
		}							\
		(u64)upper << 32 | lower; })

2786 2787 2788
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

2789 2790 2791 2792
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
2793

2794 2795 2796 2797 2798 2799 2800 2801 2802 2803
static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
{
	if (HAS_PCH_SPLIT(dev))
		return CPU_VGACNTRL;
	else if (IS_VALLEYVIEW(dev))
		return VLV_VGACNTRL;
	else
		return VGACNTRL;
}

V
Ville Syrjälä 已提交
2804 2805 2806 2807 2808
static inline void __user *to_user_ptr(u64 address)
{
	return (void __user *)(uintptr_t)address;
}

2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

2824 2825 2826 2827 2828 2829 2830 2831 2832
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
2833
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2834 2835 2836 2837 2838 2839 2840 2841 2842 2843

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
2844 2845 2846 2847
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
2848 2849 2850
	}
}

L
Linus Torvalds 已提交
2851
#endif