i915_drv.h 99.6 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>

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#include "i915_reg.h"
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#include "intel_bios.h"
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#include "intel_ringbuffer.h"
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#include "intel_lrc.h"
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#include "i915_gem_gtt.h"
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#include "i915_gem_render_state.h"
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <drm/intel-gtt.h>
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#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
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#include <drm/drm_gem.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20150117"
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
#define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
#endif

#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
	if (unlikely(__ret_warn_on)) {					\
		if (i915.verbose_state_checks)				\
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			WARN(1, format);				\
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		else 							\
			DRM_ERROR(format);				\
	}								\
	unlikely(__ret_warn_on);					\
})

#define I915_STATE_WARN_ON(condition) ({				\
	int __ret_warn_on = !!(condition);				\
	if (unlikely(__ret_warn_on)) {					\
		if (i915.verbose_state_checks)				\
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			WARN(1, "WARN_ON(" #condition ")\n");		\
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		else 							\
			DRM_ERROR("WARN_ON(" #condition ")\n");		\
	}								\
	unlikely(__ret_warn_on);					\
})

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
	I915_MAX_TRANSCODERS
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};
#define transcoder_name(t) ((t) + 'A')

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/*
 * This is the maximum (across all platforms) number of planes (primary +
 * sprites) that can be active at the same time on one pipe.
 *
 * This value doesn't count the cursor plane.
 */
#define I915_MAX_PLANES	3

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enum plane {
	PLANE_A = 0,
	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
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enum port {
	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1
};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_PORT_DDI_A_2_LANES,
	POWER_DOMAIN_PORT_DDI_A_4_LANES,
	POWER_DOMAIN_PORT_DDI_B_2_LANES,
	POWER_DOMAIN_PORT_DDI_B_4_LANES,
	POWER_DOMAIN_PORT_DDI_C_2_LANES,
	POWER_DOMAIN_PORT_DDI_C_4_LANES,
	POWER_DOMAIN_PORT_DDI_D_2_LANES,
	POWER_DOMAIN_PORT_DDI_D_4_LANES,
	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
	HPD_NUM_PINS
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_plane(pipe, p) \
	for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
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#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
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#define for_each_crtc(dev, crtc) \
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)

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#define for_each_intel_crtc(dev, intel_crtc) \
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
		if ((intel_encoder)->base.crtc == (__crtc))

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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
		if ((intel_connector)->base.encoder == (__encoder))

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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
		if ((1 << (domain)) & (mask))

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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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enum intel_dpll_id {
	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
	/* real shared dpll ids must be >= 0 */
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	DPLL_ID_PCH_PLL_A = 0,
	DPLL_ID_PCH_PLL_B = 1,
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	/* hsw/bdw */
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	DPLL_ID_WRPLL1 = 0,
	DPLL_ID_WRPLL2 = 1,
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	/* skl */
	DPLL_ID_SKL_DPLL1 = 0,
	DPLL_ID_SKL_DPLL2 = 1,
	DPLL_ID_SKL_DPLL3 = 2,
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};
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#define I915_NUM_PLLS 3
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struct intel_dpll_hw_state {
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	/* i9xx, pch plls */
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	uint32_t dpll;
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	uint32_t dpll_md;
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	uint32_t fp0;
	uint32_t fp1;
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	/* hsw, bdw */
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	uint32_t wrpll;
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	/* skl */
	/*
	 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
	 * lower part of crtl1 and they get shifted into position when writing
	 * the register.  This allows us to easily compare the state to share
	 * the DPLL.
	 */
	uint32_t ctrl1;
	/* HDMI only, 0 when used for DP */
	uint32_t cfgcr1, cfgcr2;
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};

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struct intel_shared_dpll_config {
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	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
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	struct intel_dpll_hw_state hw_state;
};

struct intel_shared_dpll {
	struct intel_shared_dpll_config config;
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	struct intel_shared_dpll_config *new_config;

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	int active; /* count of number of active CRTCs (i.e. DPMS on) */
	bool on; /* is the PLL actually active? Disabled during modeset */
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	const char *name;
	/* should match the index in the dev_priv->shared_dplls array */
	enum intel_dpll_id id;
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	/* The mode_set hook is optional and should be used together with the
	 * intel_prepare_shared_dpll function. */
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	void (*mode_set)(struct drm_i915_private *dev_priv,
			 struct intel_shared_dpll *pll);
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	void (*enable)(struct drm_i915_private *dev_priv,
		       struct intel_shared_dpll *pll);
	void (*disable)(struct drm_i915_private *dev_priv,
			struct intel_shared_dpll *pll);
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	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
			     struct intel_shared_dpll *pll,
			     struct intel_dpll_hw_state *hw_state);
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};

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#define SKL_DPLL0 0
#define SKL_DPLL1 1
#define SKL_DPLL2 2
#define SKL_DPLL3 3

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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#define WATCH_LISTS	0
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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header __iomem *header;
	struct opregion_acpi __iomem *acpi;
	struct opregion_swsci __iomem *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
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	struct opregion_asle __iomem *asle;
	void __iomem *vbt;
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	u32 __iomem *lid_state;
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	struct work_struct asle_work;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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#define I915_FENCE_REG_NONE -1
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#define I915_MAX_NUM_FENCES 32
/* 32 fences + sign bit for FENCE_REG_NONE */
#define I915_MAX_NUM_FENCE_BITS 6
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struct drm_i915_fence_reg {
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	struct list_head lru_list;
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	struct drm_i915_gem_object *obj;
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	int pin_count;
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};
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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_display_error_state;

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struct drm_i915_error_state {
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	struct kref ref;
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	struct timeval time;

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	char error_msg[128];
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	u32 reset_count;
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	u32 suspend_count;
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	/* Generic register state */
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	u32 eir;
	u32 pgtbl_er;
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	u32 ier;
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	u32 gtier[4];
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	u32 ccid;
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	u32 derrmr;
	u32 forcewake;
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	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 done_reg;
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	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
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	u32 extra_instdone[I915_NUM_INSTDONE_REG];
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
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	struct drm_i915_error_object *semaphore_obj;
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	struct drm_i915_error_ring {
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		bool valid;
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		/* Software tracked state */
		bool waiting;
		int hangcheck_score;
		enum intel_ring_hangcheck_action hangcheck_action;
		int num_requests;

		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 semaphore_seqno[I915_NUM_RINGS - 1];

		/* Register state */
		u32 tail;
		u32 head;
		u32 ctl;
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 instdone;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
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		u64 acthd;
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		u32 fault_reg;
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		u64 faddr;
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		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_RINGS - 1];

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		struct drm_i915_error_object {
			int page_count;
			u32 gtt_offset;
			u32 *pages[0];
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		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
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		struct drm_i915_error_request {
			long jiffies;
			u32 seqno;
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			u32 tail;
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		} *requests;
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		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
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		pid_t pid;
		char comm[TASK_COMM_LEN];
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	} ring[I915_NUM_RINGS];
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	struct drm_i915_error_buffer {
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		u32 size;
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		u32 name;
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		u32 rseqno, wseqno;
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		u32 gtt_offset;
		u32 read_domains;
		u32 write_domain;
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		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
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		s32 pinned:2;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
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		u32 userptr:1;
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		s32 ring:4;
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		u32 cache_level:3;
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	} **active_bo, **pinned_bo;
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	u32 *active_bo_count, *pinned_bo_count;
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	u32 vm_count;
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};

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struct intel_connector;
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struct intel_encoder;
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struct intel_crtc_state;
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struct intel_initial_plane_config;
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struct intel_crtc;
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struct intel_limit;
struct dpll;
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struct drm_i915_display_funcs {
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	bool (*fbc_enabled)(struct drm_device *dev);
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	void (*enable_fbc)(struct drm_crtc *crtc);
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	void (*disable_fbc)(struct drm_device *dev);
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
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	/**
	 * find_dpll() - Find the best values for the PLL
	 * @limit: limits for the PLL
	 * @crtc: current CRTC
	 * @target: target frequency in kHz
	 * @refclk: reference clock frequency in kHz
	 * @match_clock: if provided, @best_clock P divider must
	 *               match the P divider from @match_clock
	 *               used for LVDS downclocking
	 * @best_clock: best PLL values found
	 *
	 * Returns true on success, false on failure.
	 */
	bool (*find_dpll)(const struct intel_limit *limit,
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			  struct intel_crtc *crtc,
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			  int target, int refclk,
			  struct dpll *match_clock,
			  struct dpll *best_clock);
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	void (*update_wm)(struct drm_crtc *crtc);
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	void (*update_sprite_wm)(struct drm_plane *plane,
				 struct drm_crtc *crtc,
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				 uint32_t sprite_width, uint32_t sprite_height,
				 int pixel_size, bool enable, bool scaled);
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	void (*modeset_global_resources)(struct drm_device *dev);
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	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
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				struct intel_crtc_state *);
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	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
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	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
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	void (*crtc_enable)(struct drm_crtc *crtc);
	void (*crtc_disable)(struct drm_crtc *crtc);
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	void (*off)(struct drm_crtc *crtc);
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	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
				   struct drm_display_mode *mode);
	void (*audio_codec_disable)(struct intel_encoder *encoder);
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	void (*fdi_link_train)(struct drm_crtc *crtc);
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	void (*init_clock_gating)(struct drm_device *dev);
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	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
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			  struct drm_i915_gem_object *obj,
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			  struct intel_engine_cs *ring,
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			  uint32_t flags);
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	void (*update_primary_plane)(struct drm_crtc *crtc,
				     struct drm_framebuffer *fb,
				     int x, int y);
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	void (*hpd_irq_setup)(struct drm_device *dev);
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	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
573

574
	int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
575 576 577 578 579
	uint32_t (*get_backlight)(struct intel_connector *connector);
	void (*set_backlight)(struct intel_connector *connector,
			      uint32_t level);
	void (*disable_backlight)(struct intel_connector *connector);
	void (*enable_backlight)(struct intel_connector *connector);
580 581
};

582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

599
struct intel_uncore_funcs {
600
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
601
							enum forcewake_domains domains);
602
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
603
							enum forcewake_domains domains);
604 605 606 607 608 609 610 611 612 613 614 615 616 617

	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);

	void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
				uint8_t val, bool trace);
	void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
				uint16_t val, bool trace);
	void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
				uint32_t val, bool trace);
	void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
				uint64_t val, bool trace);
618 619
};

620 621 622 623 624 625
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
626
	enum forcewake_domains fw_domains;
627 628 629

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
630
		enum forcewake_domain_id id;
631 632
		unsigned wake_count;
		struct timer_list timer;
633 634 635 636 637 638
		u32 reg_set;
		u32 val_set;
		u32 val_clear;
		u32 reg_ack;
		u32 reg_post;
		u32 val_reset;
639 640 641 642 643 644 645 646 647 648 649 650
	} fw_domain[FW_DOMAIN_ID_COUNT];
};

/* Iterate over initialised fw domains */
#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
	for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (i__) < FW_DOMAIN_ID_COUNT; \
	     (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
		if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))

#define for_each_fw_domain(domain__, dev_priv__, i__) \
	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
651

652 653 654 655 656 657 658 659 660 661 662 663 664 665
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
	func(is_mobile) sep \
	func(is_i85x) sep \
	func(is_i915g) sep \
	func(is_i945gm) sep \
	func(is_g33) sep \
	func(need_gfx_hws) sep \
	func(is_g4x) sep \
	func(is_pineview) sep \
	func(is_broadwater) sep \
	func(is_crestline) sep \
	func(is_ivybridge) sep \
	func(is_valleyview) sep \
	func(is_haswell) sep \
666
	func(is_skylake) sep \
667
	func(is_preliminary) sep \
668 669 670 671 672 673 674
	func(has_fbc) sep \
	func(has_pipe_cxsr) sep \
	func(has_hotplug) sep \
	func(cursor_needs_physical) sep \
	func(has_overlay) sep \
	func(overlay_needs_physical) sep \
	func(supports_tv) sep \
675
	func(has_llc) sep \
676 677
	func(has_ddi) sep \
	func(has_fpga_dbg)
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679 680
#define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ;
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682
struct intel_device_info {
683
	u32 display_mmio_offset;
684
	u16 device_id;
685
	u8 num_pipes:3;
686
	u8 num_sprites[I915_MAX_PIPES];
687
	u8 gen;
688
	u8 ring_mask; /* Rings supported by the HW */
689
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
690 691 692 693
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
694
	int cursor_offsets[I915_MAX_PIPES];
695
	unsigned int eu_total;
696 697
};

698 699 700
#undef DEFINE_FLAG
#undef SEP_SEMICOLON

701 702
enum i915_cache_level {
	I915_CACHE_NONE = 0,
703 704 705 706 707
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
708
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
709 710
};

711 712 713 714 715 716
struct i915_ctx_hang_stats {
	/* This context had batch pending when hang was declared */
	unsigned batch_pending;

	/* This context had batch active when hang was declared */
	unsigned batch_active;
717 718 719 720

	/* Time when this context was last blamed for a GPU reset */
	unsigned long guilty_ts;

721 722 723 724 725
	/* If the contexts causes a second GPU hang within this time,
	 * it is permanently banned from submitting any more work.
	 */
	unsigned long ban_period_seconds;

726 727
	/* This context is banned to submit more work */
	bool banned;
728
};
729 730

/* This must match up with the value previously used for execbuf2.rsvd1. */
731
#define DEFAULT_CONTEXT_HANDLE 0
732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748
/**
 * struct intel_context - as the name implies, represents a context.
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
 * @vm: virtual memory space used by this context.
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
749
struct intel_context {
750
	struct kref ref;
751
	int user_handle;
752
	uint8_t remap_slice;
753
	struct drm_i915_file_private *file_priv;
754
	struct i915_ctx_hang_stats hang_stats;
755
	struct i915_hw_ppgtt *ppgtt;
756

757
	/* Legacy ring buffer submission */
758 759 760 761 762
	struct {
		struct drm_i915_gem_object *rcs_state;
		bool initialized;
	} legacy_hw_ctx;

763
	/* Execlists */
764
	bool rcs_initialized;
765 766
	struct {
		struct drm_i915_gem_object *state;
767
		struct intel_ringbuffer *ringbuf;
768
		int unpin_count;
769 770
	} engine[I915_NUM_RINGS];

771
	struct list_head link;
772 773
};

774 775
struct i915_fbc {
	unsigned long size;
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	unsigned threshold;
777 778 779 780
	unsigned int fb_id;
	enum plane plane;
	int y;

781
	struct drm_mm_node compressed_fb;
782 783
	struct drm_mm_node *compressed_llb;

784 785
	bool false_color;

786 787 788 789
	/* Tracks whether the HW is actually enabled, not whether the feature is
	 * possible. */
	bool enabled;

790 791 792 793 794 795 796 797
	/* On gen8 some rings cannont perform fbc clean operation so for now
	 * we are doing this on SW with mmio.
	 * This variable works in the opposite information direction
	 * of ring->fbc_dirty telling software on frontbuffer tracking
	 * to perform the cache clean on sw side.
	 */
	bool need_sw_cache_clean;

798 799 800 801 802 803
	struct intel_fbc_work {
		struct delayed_work work;
		struct drm_crtc *crtc;
		struct drm_framebuffer *fb;
	} *fbc_work;

804 805 806
	enum no_fbc_reason {
		FBC_OK, /* FBC is enabled */
		FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
807 808 809 810 811 812 813 814 815 816
		FBC_NO_OUTPUT, /* no outputs enabled to compress */
		FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
		FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
		FBC_MODE_TOO_LARGE, /* mode too large for compression */
		FBC_BAD_PLANE, /* fbc not supported on plane */
		FBC_NOT_TILED, /* buffer not tiled */
		FBC_MULTIPLE_PIPES, /* more than one pipe active */
		FBC_MODULE_PARAM,
		FBC_CHIP_DEFAULT, /* disabled by default on this chip */
	} no_fbc_reason;
817 818
};

819 820 821 822 823 824 825 826 827 828 829 830 831 832 833
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
834 835
};

836
struct intel_dp;
837 838 839 840 841 842 843 844 845
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

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struct i915_psr {
847
	struct mutex lock;
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848 849
	bool sink_support;
	bool source_ok;
850
	struct intel_dp *enabled;
851 852
	bool active;
	struct delayed_work work;
853
	unsigned busy_frontbuffer_bits;
854
	bool link_standby;
855
};
856

857
enum intel_pch {
858
	PCH_NONE = 0,	/* No PCH present */
859 860
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
861
	PCH_LPT,	/* Lynxpoint PCH */
862
	PCH_SPT,        /* Sunrisepoint PCH */
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	PCH_NOP,
864 865
};

866 867 868 869 870
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

871
#define QUIRK_PIPEA_FORCE (1<<0)
872
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
873
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
874
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
875
#define QUIRK_PIPEB_FORCE (1<<4)
876
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
877

878
struct intel_fbdev;
879
struct intel_fbc_work;
880

881 882
struct intel_gmbus {
	struct i2c_adapter adapter;
883
	u32 force_bit;
884
	u32 reg0;
885
	u32 gpio_reg;
886
	struct i2c_algo_bit_data bit_algo;
887 888 889
	struct drm_i915_private *dev_priv;
};

890
struct i915_suspend_saved_registers {
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	u8 saveLBB;
	u32 saveDSPACNTR;
	u32 saveDSPBCNTR;
894
	u32 saveDSPARB;
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	u32 savePIPEACONF;
	u32 savePIPEBCONF;
	u32 savePIPEASRC;
	u32 savePIPEBSRC;
	u32 saveFPA0;
	u32 saveFPA1;
	u32 saveDPLL_A;
	u32 saveDPLL_A_MD;
	u32 saveHTOTAL_A;
	u32 saveHBLANK_A;
	u32 saveHSYNC_A;
	u32 saveVTOTAL_A;
	u32 saveVBLANK_A;
	u32 saveVSYNC_A;
	u32 saveBCLRPAT_A;
910
	u32 saveTRANSACONF;
911 912 913 914 915 916
	u32 saveTRANS_HTOTAL_A;
	u32 saveTRANS_HBLANK_A;
	u32 saveTRANS_HSYNC_A;
	u32 saveTRANS_VTOTAL_A;
	u32 saveTRANS_VBLANK_A;
	u32 saveTRANS_VSYNC_A;
917
	u32 savePIPEASTAT;
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	u32 saveDSPASTRIDE;
	u32 saveDSPASIZE;
	u32 saveDSPAPOS;
921
	u32 saveDSPAADDR;
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	u32 saveDSPASURF;
	u32 saveDSPATILEOFF;
	u32 savePFIT_PGM_RATIOS;
925
	u32 saveBLC_HIST_CTL;
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	u32 saveBLC_PWM_CTL;
	u32 saveBLC_PWM_CTL2;
928 929
	u32 saveBLC_CPU_PWM_CTL;
	u32 saveBLC_CPU_PWM_CTL2;
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	u32 saveFPB0;
	u32 saveFPB1;
	u32 saveDPLL_B;
	u32 saveDPLL_B_MD;
	u32 saveHTOTAL_B;
	u32 saveHBLANK_B;
	u32 saveHSYNC_B;
	u32 saveVTOTAL_B;
	u32 saveVBLANK_B;
	u32 saveVSYNC_B;
	u32 saveBCLRPAT_B;
941
	u32 saveTRANSBCONF;
942 943 944 945 946 947
	u32 saveTRANS_HTOTAL_B;
	u32 saveTRANS_HBLANK_B;
	u32 saveTRANS_HSYNC_B;
	u32 saveTRANS_VTOTAL_B;
	u32 saveTRANS_VBLANK_B;
	u32 saveTRANS_VSYNC_B;
948
	u32 savePIPEBSTAT;
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	u32 saveDSPBSTRIDE;
	u32 saveDSPBSIZE;
	u32 saveDSPBPOS;
952
	u32 saveDSPBADDR;
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	u32 saveDSPBSURF;
	u32 saveDSPBTILEOFF;
955 956 957
	u32 saveVGA0;
	u32 saveVGA1;
	u32 saveVGA_PD;
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	u32 saveVGACNTRL;
	u32 saveADPA;
	u32 saveLVDS;
961 962
	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
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	u32 saveDVOA;
	u32 saveDVOB;
	u32 saveDVOC;
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
969
	u32 savePP_DIVISOR;
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970 971 972 973
	u32 savePFIT_CONTROL;
	u32 save_palette_a[256];
	u32 save_palette_b[256];
	u32 saveFBC_CONTROL;
974 975 976
	u32 saveIER;
	u32 saveIIR;
	u32 saveIMR;
977 978 979 980 981 982
	u32 saveDEIER;
	u32 saveDEIMR;
	u32 saveGTIER;
	u32 saveGTIMR;
	u32 saveFDI_RXA_IMR;
	u32 saveFDI_RXB_IMR;
983 984
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
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	u32 saveSWF0[16];
	u32 saveSWF1[16];
	u32 saveSWF2[3];
	u8 saveMSR;
	u8 saveSR[8];
990
	u8 saveGR[25];
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991
	u8 saveAR_INDEX;
992
	u8 saveAR[21];
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993
	u8 saveDACMASK;
994
	u8 saveCR[37];
995
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
996 997 998 999 1000 1001 1002
	u32 saveCURACNTR;
	u32 saveCURAPOS;
	u32 saveCURABASE;
	u32 saveCURBCNTR;
	u32 saveCURBPOS;
	u32 saveCURBBASE;
	u32 saveCURSIZE;
1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013
	u32 saveDP_B;
	u32 saveDP_C;
	u32 saveDP_D;
	u32 savePIPEA_GMCH_DATA_M;
	u32 savePIPEB_GMCH_DATA_M;
	u32 savePIPEA_GMCH_DATA_N;
	u32 savePIPEB_GMCH_DATA_N;
	u32 savePIPEA_DP_LINK_M;
	u32 savePIPEB_DP_LINK_M;
	u32 savePIPEA_DP_LINK_N;
	u32 savePIPEB_DP_LINK_N;
1014 1015 1016 1017 1018 1019 1020 1021 1022 1023
	u32 saveFDI_RXA_CTL;
	u32 saveFDI_TXA_CTL;
	u32 saveFDI_RXB_CTL;
	u32 saveFDI_TXB_CTL;
	u32 savePFA_CTL_1;
	u32 savePFB_CTL_1;
	u32 savePFA_WIN_SZ;
	u32 savePFB_WIN_SZ;
	u32 savePFA_WIN_POS;
	u32 savePFB_WIN_POS;
1024 1025 1026 1027 1028 1029 1030 1031 1032 1033
	u32 savePCH_DREF_CONTROL;
	u32 saveDISP_ARB_CTL;
	u32 savePIPEA_DATA_M1;
	u32 savePIPEA_DATA_N1;
	u32 savePIPEA_LINK_M1;
	u32 savePIPEA_LINK_N1;
	u32 savePIPEB_DATA_M1;
	u32 savePIPEB_DATA_N1;
	u32 savePIPEB_LINK_M1;
	u32 savePIPEB_LINK_N1;
1034
	u32 saveMCHBAR_RENDER_STANDBY;
1035
	u32 savePCH_PORT_HOTPLUG;
1036
	u16 saveGCDGMBUS;
1037
};
1038

1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
	u32 clock_gate_dis2;
};

1100 1101 1102 1103
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1104 1105
};

1106
struct intel_gen6_power_mgmt {
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Imre Deak 已提交
1107 1108 1109 1110
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1111
	struct work_struct work;
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1112
	bool interrupts_enabled;
1113
	u32 pm_iir;
1114

1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1133
	u32 cz_freq;
1134

1135
	u32 ei_interrupt_count;
1136

1137 1138 1139
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1140
	bool enabled;
1141
	struct delayed_work delayed_resume_work;
1142

1143 1144 1145
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1146 1147 1148 1149 1150
	/*
	 * Protects RPS/RC6 register access and PCU communication.
	 * Must be taken after struct_mutex if nested.
	 */
	struct mutex hw_lock;
1151 1152
};

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Daniel Vetter 已提交
1153 1154 1155
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1167
	u64 last_time2;
1168 1169 1170 1171 1172
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
1173 1174 1175

	struct drm_i915_gem_object *pwrctx;
	struct drm_i915_gem_object *renderctx;
1176 1177
};

1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1208 1209
/* Power well structure for haswell */
struct i915_power_well {
1210
	const char *name;
1211
	bool always_on;
1212 1213
	/* power well enable/disable usage count */
	int count;
1214 1215
	/* cached hw enabled state */
	bool hw_enabled;
1216
	unsigned long domains;
1217
	unsigned long data;
1218
	const struct i915_power_well_ops *ops;
1219 1220
};

1221
struct i915_power_domains {
1222 1223 1224 1225 1226
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1227
	bool initializing;
1228
	int power_well_count;
1229

1230
	struct mutex lock;
1231
	int domain_use_count[POWER_DOMAIN_NUM];
1232
	struct i915_power_well *power_wells;
1233 1234
};

1235
#define MAX_L3_SLICES 2
1236
struct intel_l3_parity {
1237
	u32 *remap_info[MAX_L3_SLICES];
1238
	struct work_struct error_work;
1239
	int which_slice;
1240 1241
};

1242 1243 1244 1245 1246
struct i915_gem_batch_pool {
	struct drm_device *dev;
	struct list_head cache_list;
};

1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
	 * are idle and not used by the GPU) but still have
	 * (presumably uncached) pages still attached.
	 */
	struct list_head unbound_list;

1260 1261 1262 1263 1264 1265 1266
	/*
	 * A pool of objects to use as shadow copies of client batch buffers
	 * when the command parser is enabled. Prevents the client from
	 * modifying the batch contents after software parsing.
	 */
	struct i915_gem_batch_pool batch_pool;

1267 1268 1269 1270 1271 1272
	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1273
	struct notifier_block oom_notifier;
1274
	struct shrinker shrinker;
1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288
	bool shrinker_no_lock_stealing;

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * We leave the user IRQ off as much as possible,
	 * but this means that requests will finish and never
	 * be retired once the system goes idle. Set a timer to
	 * fire periodically while the ring is running. When it
	 * fires, go retire requests.
	 */
	struct delayed_work retire_work;

1289 1290 1291 1292 1293 1294 1295 1296 1297
	/**
	 * When we detect an idle GPU, we want to turn on
	 * powersaving features. So once we see that there
	 * are no more requests outstanding and no more
	 * arrive within a small period of time, we fire
	 * off the idle_work.
	 */
	struct delayed_work idle_work;

1298 1299 1300 1301 1302 1303
	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1304 1305 1306 1307 1308 1309 1310 1311
	/**
	 * Is the GPU currently considered idle, or busy executing userspace
	 * requests?  Whilst idle, we attempt to power down the hardware and
	 * display clocks. In order to reduce the effect on performance, there
	 * is a slight delay before we do so.
	 */
	bool busy;

1312 1313 1314
	/* the indicator for dispatch video commands on two BSD rings */
	int bsd_ring_dispatch_index;

1315 1316 1317 1318 1319 1320
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1321
	spinlock_t object_stat_lock;
1322 1323 1324 1325
	size_t object_memory;
	u32 object_count;
};

1326
struct drm_i915_error_state_buf {
1327
	struct drm_i915_private *i915;
1328 1329 1330 1331 1332 1333 1334 1335
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1336 1337 1338 1339 1340
struct i915_error_state_file_priv {
	struct drm_device *dev;
	struct drm_i915_error_state *error;
};

1341 1342 1343 1344
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1345 1346 1347
	/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)

1348 1349 1350 1351 1352 1353 1354 1355
	struct timer_list hangcheck_timer;

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
	struct work_struct work;

1356 1357 1358

	unsigned long missed_irq_rings;

1359
	/**
M
Mika Kuoppala 已提交
1360
	 * State variable controlling the reset flow and count
1361
	 *
M
Mika Kuoppala 已提交
1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374
	 * This is a counter which gets incremented when reset is triggered,
	 * and again when reset has been handled. So odd values (lowest bit set)
	 * means that reset is in progress and even values that
	 * (reset_counter >> 1):th reset was successfully completed.
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1375 1376 1377 1378
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1379 1380 1381 1382
	 */
	atomic_t reset_counter;

#define I915_RESET_IN_PROGRESS_FLAG	1
M
Mika Kuoppala 已提交
1383
#define I915_WEDGED			(1 << 31)
1384 1385 1386 1387 1388 1389

	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1390

1391 1392 1393 1394 1395 1396
	/* Userspace knobs for gpu hang simulation;
	 * combines both a ring mask, and extra flags
	 */
	u32 stop_rings;
#define I915_STOP_RING_ALLOW_BAN       (1 << 31)
#define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1397 1398 1399

	/* For missed irq/seqno simulation. */
	unsigned int test_irq_rings;
1400 1401 1402

	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset   */
	bool reload_in_reset;
1403 1404
};

1405 1406 1407 1408 1409 1410
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1411
struct ddi_vbt_port_info {
1412 1413 1414 1415 1416 1417
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1418
	uint8_t hdmi_level_shift;
1419 1420 1421 1422

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1423 1424
};

R
Rodrigo Vivi 已提交
1425 1426 1427 1428 1429 1430 1431
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
};

1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1444
	unsigned int has_mipi:1;
1445 1446 1447
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1448 1449
	enum drrs_support_type drrs_type;

1450 1451 1452 1453 1454 1455 1456 1457 1458 1459
	/* eDP */
	int edp_rate;
	int edp_lanes;
	int edp_preemphasis;
	int edp_vswing;
	bool edp_initialized;
	bool edp_support;
	int edp_bpp;
	struct edp_power_seq edp_pps;

R
Rodrigo Vivi 已提交
1460 1461 1462 1463 1464 1465 1466 1467 1468
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1469 1470
	struct {
		u16 pwm_freq_hz;
1471
		bool present;
1472
		bool active_low_pwm;
1473
		u8 min_brightness;	/* min_brightness/255 of max */
1474 1475
	} backlight;

1476 1477
	/* MIPI DSI */
	struct {
1478
		u16 port;
1479
		u16 panel_id;
1480 1481 1482 1483 1484 1485
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
		u8 *sequence[MIPI_SEQ_MAX];
1486 1487
	} dsi;

1488 1489 1490
	int crt_ddc_pin;

	int child_dev_num;
1491
	union child_device_config *child_dev;
1492 1493

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1494 1495
};

1496 1497 1498 1499 1500
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1501 1502 1503 1504 1505 1506 1507 1508
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1509
struct ilk_wm_values {
1510 1511 1512 1513 1514 1515 1516 1517
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1518
struct skl_ddb_entry {
1519
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1520 1521 1522 1523
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1524
	return entry->end - entry->start;
1525 1526
}

1527 1528 1529 1530 1531 1532 1533 1534 1535
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1536
struct skl_ddb_allocation {
1537
	struct skl_ddb_entry pipe[I915_MAX_PIPES];
1538 1539 1540 1541
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
	struct skl_ddb_entry cursor[I915_MAX_PIPES];
};

1542 1543
struct skl_wm_values {
	bool dirty[I915_MAX_PIPES];
1544
	struct skl_ddb_allocation ddb;
1545 1546 1547 1548 1549 1550 1551 1552 1553
	uint32_t wm_linetime[I915_MAX_PIPES];
	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
	uint32_t cursor[I915_MAX_PIPES][8];
	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
	uint32_t cursor_trans[I915_MAX_PIPES];
};

struct skl_wm_level {
	bool plane_en[I915_MAX_PLANES];
1554
	bool cursor_en;
1555 1556 1557 1558 1559 1560
	uint16_t plane_res_b[I915_MAX_PLANES];
	uint8_t plane_res_l[I915_MAX_PLANES];
	uint16_t cursor_res_b;
	uint8_t cursor_res_l;
};

1561
/*
1562 1563 1564 1565
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1566
 *
1567 1568 1569
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1570
 *
1571 1572
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1573
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1574
 * it can be changed with the standard runtime PM files from sysfs.
1575 1576 1577 1578 1579
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1580
 * case it happens.
1581
 *
1582
 * For more, read the Documentation/power/runtime_pm.txt.
1583
 */
1584 1585
struct i915_runtime_pm {
	bool suspended;
1586
	bool irqs_enabled;
1587 1588
};

1589 1590 1591 1592 1593
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1594
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1595 1596 1597 1598 1599
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1600
	INTEL_PIPE_CRC_SOURCE_AUTO,
1601 1602 1603
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1604
struct intel_pipe_crc_entry {
1605
	uint32_t frame;
1606 1607 1608
	uint32_t crc[5];
};

1609
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1610
struct intel_pipe_crc {
1611 1612
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1613
	struct intel_pipe_crc_entry *entries;
1614
	enum intel_pipe_crc_source source;
1615
	int head, tail;
1616
	wait_queue_head_t wq;
1617 1618
};

1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629
struct i915_frontbuffer_tracking {
	struct mutex lock;

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643
struct i915_wa_reg {
	u32 addr;
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

#define I915_MAX_WA_REGS 16

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
};

1644
struct drm_i915_private {
1645
	struct drm_device *dev;
1646
	struct kmem_cache *slab;
1647

1648
	const struct intel_device_info info;
1649 1650 1651 1652 1653

	int relative_constants_mode;

	void __iomem *regs;

1654
	struct intel_uncore uncore;
1655 1656 1657

	struct intel_gmbus gmbus[GMBUS_NUM_PORTS];

1658

1659 1660 1661 1662 1663 1664 1665 1666 1667
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1668 1669 1670
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1671 1672
	wait_queue_head_t gmbus_wait_queue;

1673
	struct pci_dev *bridge_dev;
1674
	struct intel_engine_cs ring[I915_NUM_RINGS];
1675
	struct drm_i915_gem_object *semaphore_obj;
1676
	uint32_t last_seqno, next_seqno;
1677

1678
	struct drm_dma_handle *status_page_dmah;
1679 1680 1681 1682 1683
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1684 1685 1686
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1687 1688
	bool display_irqs_enabled;

1689 1690 1691
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

1692
	/* DPIO indirect register protection */
1693
	struct mutex dpio_lock;
1694 1695

	/** Cached value of IMR to avoid reads in updating the bitfield */
1696 1697 1698 1699
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1700
	u32 gt_irq_mask;
1701
	u32 pm_irq_mask;
1702
	u32 pm_rps_events;
1703
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1704 1705

	struct work_struct hotplug_work;
1706 1707 1708 1709 1710 1711 1712 1713 1714
	struct {
		unsigned long hpd_last_jiffies;
		int hpd_cnt;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} hpd_mark;
	} hpd_stats[HPD_NUM_PINS];
1715
	u32 hpd_event_bits;
1716
	struct delayed_work hotplug_reenable_work;
1717

1718
	struct i915_fbc fbc;
1719
	struct i915_drrs drrs;
1720
	struct intel_opregion opregion;
1721
	struct intel_vbt_data vbt;
1722

1723 1724
	bool preserve_bios_swizzle;

1725 1726 1727
	/* overlay */
	struct intel_overlay *overlay;

1728
	/* backlight registers and fields in struct intel_panel */
1729
	struct mutex backlight_lock;
1730

1731 1732 1733
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1734 1735 1736
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1737 1738 1739 1740 1741
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1742
	unsigned int vlv_cdclk_freq;
1743
	unsigned int hpll_freq;
1744

1745 1746 1747 1748 1749 1750 1751
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1752 1753 1754 1755 1756 1757 1758
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1759
	unsigned short pch_id;
1760 1761 1762

	unsigned long quirks;

1763 1764
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1765

1766
	struct list_head vm_list; /* Global list of all address spaces */
1767
	struct i915_gtt gtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1768

1769
	struct i915_gem_mm mm;
1770 1771
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1772 1773 1774

	/* Kernel Modesetting */

1775
	struct sdvo_device_mapping sdvo_mappings[2];
1776

1777 1778
	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1779 1780
	wait_queue_head_t pending_flip_queue;

1781 1782 1783 1784
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

D
Daniel Vetter 已提交
1785 1786
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1787
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1788

1789
	struct i915_workarounds workarounds;
1790

1791 1792 1793
	/* Reclocking support */
	bool render_reclock_avail;
	bool lvds_downclock_avail;
1794 1795
	/* indicates the reduced downclock for LVDS*/
	int lvds_downclock;
1796 1797 1798

	struct i915_frontbuffer_tracking fb_tracking;

1799
	u16 orig_clock;
1800

1801
	bool mchbar_need_disable;
1802

1803 1804
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1805 1806 1807
	/* Cannot be determined by PCIID. You must always read a register. */
	size_t ellc_size;

1808
	/* gen6+ rps state */
1809
	struct intel_gen6_power_mgmt rps;
1810

1811 1812
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1813
	struct intel_ilk_power_mgmt ips;
1814

1815
	struct i915_power_domains power_domains;
1816

R
Rodrigo Vivi 已提交
1817
	struct i915_psr psr;
1818

1819
	struct i915_gpu_error gpu_error;
1820

1821 1822
	struct drm_i915_gem_object *vlv_pctx;

1823
#ifdef CONFIG_DRM_I915_FBDEV
1824 1825
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1826
	struct work_struct fbdev_suspend_work;
1827
#endif
1828 1829

	struct drm_property *broadcast_rgb_property;
1830
	struct drm_property *force_audio_property;
1831

I
Imre Deak 已提交
1832 1833 1834
	/* hda/i915 audio component */
	bool audio_component_registered;

1835
	uint32_t hw_context_size;
1836
	struct list_head context_list;
1837

1838
	u32 fdi_rx_config;
1839

1840
	u32 suspend_count;
1841
	struct i915_suspend_saved_registers regfile;
1842
	struct vlv_s0ix_state vlv_s0ix_state;
1843

1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
1856 1857 1858 1859 1860 1861
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
1862

1863 1864 1865 1866 1867 1868 1869
		/*
		 * The skl_wm_values structure is a bit too big for stack
		 * allocation, so we keep the staging struct where we store
		 * intermediate results here instead.
		 */
		struct skl_wm_values skl_results;

1870
		/* current hardware state */
1871 1872 1873 1874
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
		};
1875 1876
	} wm;

1877 1878
	struct i915_runtime_pm pm;

1879 1880 1881 1882 1883
	struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
	u32 long_hpd_port_mask;
	u32 short_hpd_port_mask;
	struct work_struct dig_port_work;

1884 1885 1886 1887 1888 1889 1890 1891 1892
	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;

1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
		int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
				  struct intel_engine_cs *ring,
				  struct intel_context *ctx,
				  struct drm_i915_gem_execbuffer2 *args,
				  struct list_head *vmas,
				  struct drm_i915_gem_object *batch_obj,
				  u64 exec_start, u32 flags);
		int (*init_rings)(struct drm_device *dev);
		void (*cleanup_ring)(struct intel_engine_cs *ring);
		void (*stop_ring)(struct intel_engine_cs *ring);
	} gt;

1907 1908
	uint32_t request_uniq;

1909 1910 1911 1912
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
1913
};
L
Linus Torvalds 已提交
1914

1915 1916 1917 1918 1919
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
	return dev->dev_private;
}

I
Imre Deak 已提交
1920 1921 1922 1923 1924
static inline struct drm_i915_private *dev_to_i915(struct device *dev)
{
	return to_i915(dev_get_drvdata(dev));
}

1925 1926 1927 1928 1929
/* Iterate over initialised rings */
#define for_each_ring(ring__, dev_priv__, i__) \
	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
		if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))

1930 1931 1932 1933 1934 1935 1936
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

1937
#define I915_GTT_OFFSET_NONE ((u32)-1)
1938

1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954
struct drm_i915_gem_object_ops {
	/* Interface between the GEM object and its backing storage.
	 * get_pages() is called once prior to the use of the associated set
	 * of pages before to binding them into the GTT, and put_pages() is
	 * called after we no longer need them. As we expect there to be
	 * associated cost with migrating pages between the backing storage
	 * and making them available for the GPU (e.g. clflush), we may hold
	 * onto the pages after they are no longer referenced by the GPU
	 * in case they may be used again shortly (for example migrating the
	 * pages to a different memory domain within the GTT). put_pages()
	 * will therefore most likely be called when the object itself is
	 * being released or under memory pressure (where we attempt to
	 * reap pages for the shrinker).
	 */
	int (*get_pages)(struct drm_i915_gem_object *);
	void (*put_pages)(struct drm_i915_gem_object *);
1955 1956
	int (*dmabuf_export)(struct drm_i915_gem_object *);
	void (*release)(struct drm_i915_gem_object *);
1957 1958
};

1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
 * considered to be the frontbuffer for the given plane interface-vise. This
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
#define INTEL_FRONTBUFFER_BITS \
	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
	(1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe) \
	(1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
	(1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1978 1979
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
	(0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1980

1981
struct drm_i915_gem_object {
1982
	struct drm_gem_object base;
1983

1984 1985
	const struct drm_i915_gem_object_ops *ops;

B
Ben Widawsky 已提交
1986 1987 1988
	/** List of VMAs backed by this object */
	struct list_head vma_list;

1989 1990
	/** Stolen memory for this object, instead of being backed by shmem. */
	struct drm_mm_node *stolen;
1991
	struct list_head global_list;
1992

1993
	struct list_head ring_list;
1994 1995
	/** Used in execbuf to temporarily hold a ref */
	struct list_head obj_exec_link;
1996

1997 1998
	struct list_head batch_pool_list;

1999
	/**
2000 2001 2002
	 * This is set if the object is on the active lists (has pending
	 * rendering and so a non-zero seqno), and is not set if it i s on
	 * inactive (ready to be unbound) list.
2003
	 */
2004
	unsigned int active:1;
2005 2006 2007 2008 2009

	/**
	 * This is set if the object has been written to since last bound
	 * to the GTT
	 */
2010
	unsigned int dirty:1;
2011 2012 2013 2014 2015 2016

	/**
	 * Fence register bits (if any) for this object.  Will be set
	 * as needed when mapped into the GTT.
	 * Protected by dev->struct_mutex.
	 */
2017
	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2018 2019 2020 2021

	/**
	 * Advice: are the backing pages purgeable?
	 */
2022
	unsigned int madv:2;
2023 2024 2025 2026

	/**
	 * Current tiling mode for the object.
	 */
2027
	unsigned int tiling_mode:2;
2028 2029 2030 2031 2032 2033 2034 2035
	/**
	 * Whether the tiling parameters for the currently associated fence
	 * register have changed. Note that for the purposes of tracking
	 * tiling changes we also treat the unfenced register, the register
	 * slot that the object occupies whilst it executes a fenced
	 * command (such as BLT on gen2/3), as a "fence".
	 */
	unsigned int fence_dirty:1;
2036

2037 2038 2039 2040
	/**
	 * Is the object at the current location in the gtt mappable and
	 * fenceable? Used to avoid costly recalculations.
	 */
2041
	unsigned int map_and_fenceable:1;
2042

2043 2044 2045 2046 2047
	/**
	 * Whether the current gtt mapping needs to be mappable (and isn't just
	 * mappable by accident). Track pin and fault separate for a more
	 * accurate mappable working set.
	 */
2048 2049
	unsigned int fault_mappable:1;
	unsigned int pin_mappable:1;
2050
	unsigned int pin_display:1;
2051

2052 2053 2054 2055 2056
	/*
	 * Is the object to be mapped as read-only to the GPU
	 * Only honoured if hardware has relevant pte bit
	 */
	unsigned long gt_ro:1;
2057
	unsigned int cache_level:3;
2058

2059
	unsigned int has_dma_mapping:1;
2060

2061 2062
	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;

2063
	struct sg_table *pages;
2064
	int pages_pin_count;
2065

2066
	/* prime dma-buf support */
2067 2068 2069
	void *dma_buf_vmapping;
	int vmapping_count;

2070
	/** Breadcrumb of last rendering to the buffer. */
2071 2072
	struct drm_i915_gem_request *last_read_req;
	struct drm_i915_gem_request *last_write_req;
2073
	/** Breadcrumb of last fenced GPU access to the buffer. */
2074
	struct drm_i915_gem_request *last_fenced_req;
2075

2076
	/** Current tiling stride for the object, if it's tiled. */
2077
	uint32_t stride;
2078

2079 2080 2081
	/** References from framebuffers, locks out tiling changes. */
	unsigned long framebuffer_references;

2082
	/** Record of address bit 17 of each page at last unbind. */
2083
	unsigned long *bit_17;
2084

2085
	union {
2086 2087 2088
		/** for phy allocated objects */
		struct drm_dma_handle *phys_handle;

2089 2090 2091 2092 2093 2094
		struct i915_gem_userptr {
			uintptr_t ptr;
			unsigned read_only :1;
			unsigned workers :4;
#define I915_GEM_USERPTR_MAX_WORKERS 15

2095 2096
			struct i915_mm_struct *mm;
			struct i915_mmu_object *mmu_object;
2097 2098 2099 2100
			struct work_struct *work;
		} userptr;
	};
};
2101
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2102

2103 2104 2105 2106
void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

2107 2108 2109 2110 2111 2112
/**
 * Request queue structure.
 *
 * The request queue allows us to note sequence numbers that have been emitted
 * and may be associated with active buffers to be retired.
 *
2113 2114 2115 2116
 * By keeping this list, we can avoid having to do questionable sequence
 * number comparisons on buffer last_read|write_seqno. It also allows an
 * emission time to be associated with the request for tracking how far ahead
 * of the GPU the submission is.
2117 2118
 */
struct drm_i915_gem_request {
2119 2120
	struct kref ref;

2121
	/** On Which ring this request was generated */
2122
	struct intel_engine_cs *ring;
2123

2124 2125 2126
	/** GEM sequence number associated with this request. */
	uint32_t seqno;

2127 2128 2129
	/** Position in the ringbuffer of the start of the request */
	u32 head;

2130 2131 2132 2133 2134 2135 2136 2137
	/**
	 * Position in the ringbuffer of the start of the postfix.
	 * This is required to calculate the maximum available ringbuffer
	 * space without overwriting the postfix.
	 */
	 u32 postfix;

	/** Position in the ringbuffer of the end of the whole request */
2138 2139
	u32 tail;

2140
	/** Context related to this request */
2141
	struct intel_context *ctx;
2142

2143 2144 2145
	/** Batch buffer related to this request if any */
	struct drm_i915_gem_object *batch_obj;

2146 2147 2148
	/** Time at which this request was emitted, in jiffies. */
	unsigned long emitted_jiffies;

2149
	/** global list entry for this request */
2150
	struct list_head list;
2151

2152
	struct drm_i915_file_private *file_priv;
2153 2154
	/** file_priv list entry for this request */
	struct list_head client_list;
2155 2156

	uint32_t uniq;
2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176

	/**
	 * The ELSP only accepts two elements at a time, so we queue
	 * context/tail pairs on a given queue (ring->execlist_queue) until the
	 * hardware is available. The queue serves a double purpose: we also use
	 * it to keep track of the up to 2 contexts currently in the hardware
	 * (usually one in execution and the other queued up by the GPU): We
	 * only remove elements from the head of the queue when the hardware
	 * informs us that an element has been completed.
	 *
	 * All accesses to the queue are mediated by a spinlock
	 * (ring->execlist_lock).
	 */

	/** Execlist link in the submission queue.*/
	struct list_head execlist_link;

	/** Execlists no. of times this request has been sent to the ELSP */
	int elsp_submitted;

2177 2178
};

2179 2180
void i915_gem_request_free(struct kref *req_ref);

2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192
static inline uint32_t
i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
{
	return req ? req->seqno : 0;
}

static inline struct intel_engine_cs *
i915_gem_request_get_ring(struct drm_i915_gem_request *req)
{
	return req ? req->ring : NULL;
}

2193 2194 2195 2196 2197 2198 2199 2200 2201
static inline void
i915_gem_request_reference(struct drm_i915_gem_request *req)
{
	kref_get(&req->ref);
}

static inline void
i915_gem_request_unreference(struct drm_i915_gem_request *req)
{
2202
	WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217
	kref_put(&req->ref, i915_gem_request_free);
}

static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
					   struct drm_i915_gem_request *src)
{
	if (src)
		i915_gem_request_reference(src);

	if (*pdst)
		i915_gem_request_unreference(*pdst);

	*pdst = src;
}

2218 2219 2220 2221 2222 2223
/*
 * XXX: i915_gem_request_completed should be here but currently needs the
 * definition of i915_seqno_passed() which is below. It will be moved in
 * a later patch when the call to i915_seqno_passed() is obsoleted...
 */

2224
struct drm_i915_file_private {
2225
	struct drm_i915_private *dev_priv;
2226
	struct drm_file *file;
2227

2228
	struct {
2229
		spinlock_t lock;
2230
		struct list_head request_list;
2231
		struct delayed_work idle_work;
2232
	} mm;
2233
	struct idr context_idr;
2234

2235
	atomic_t rps_wait_boost;
2236
	struct  intel_engine_cs *bsd_ring;
2237 2238
};

2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303
/*
 * A command that requires special handling by the command parser.
 */
struct drm_i915_cmd_descriptor {
	/*
	 * Flags describing how the command parser processes the command.
	 *
	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
	 *                 a length mask if not set
	 * CMD_DESC_SKIP: The command is allowed but does not follow the
	 *                standard length encoding for the opcode range in
	 *                which it falls
	 * CMD_DESC_REJECT: The command is never allowed
	 * CMD_DESC_REGISTER: The command should be checked against the
	 *                    register whitelist for the appropriate ring
	 * CMD_DESC_MASTER: The command is allowed if the submitting process
	 *                  is the DRM master
	 */
	u32 flags;
#define CMD_DESC_FIXED    (1<<0)
#define CMD_DESC_SKIP     (1<<1)
#define CMD_DESC_REJECT   (1<<2)
#define CMD_DESC_REGISTER (1<<3)
#define CMD_DESC_BITMASK  (1<<4)
#define CMD_DESC_MASTER   (1<<5)

	/*
	 * The command's unique identification bits and the bitmask to get them.
	 * This isn't strictly the opcode field as defined in the spec and may
	 * also include type, subtype, and/or subop fields.
	 */
	struct {
		u32 value;
		u32 mask;
	} cmd;

	/*
	 * The command's length. The command is either fixed length (i.e. does
	 * not include a length field) or has a length field mask. The flag
	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
	 * a length mask. All command entries in a command table must include
	 * length information.
	 */
	union {
		u32 fixed;
		u32 mask;
	} length;

	/*
	 * Describes where to find a register address in the command to check
	 * against the ring's register whitelist. Only valid if flags has the
	 * CMD_DESC_REGISTER bit set.
	 */
	struct {
		u32 offset;
		u32 mask;
	} reg;

#define MAX_CMD_DESC_BITMASKS 3
	/*
	 * Describes command checks where a particular dword is masked and
	 * compared against an expected value. If the command does not match
	 * the expected value, the parser rejects it. Only valid if flags has
	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
	 * are valid.
2304 2305 2306 2307
	 *
	 * If the check specifies a non-zero condition_mask then the parser
	 * only performs the check when the bits specified by condition_mask
	 * are non-zero.
2308 2309 2310 2311 2312
	 */
	struct {
		u32 offset;
		u32 mask;
		u32 expected;
2313 2314
		u32 condition_offset;
		u32 condition_mask;
2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328
	} bits[MAX_CMD_DESC_BITMASKS];
};

/*
 * A table of commands requiring special handling by the command parser.
 *
 * Each ring has an array of tables. Each table consists of an array of command
 * descriptors, which must be sorted with command opcodes in ascending order.
 */
struct drm_i915_cmd_table {
	const struct drm_i915_cmd_descriptor *table;
	int count;
};

C
Chris Wilson 已提交
2329
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2330 2331 2332 2333 2334 2335 2336 2337 2338 2339
#define __I915__(p) ({ \
	struct drm_i915_private *__p; \
	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		__p = (struct drm_i915_private *)p; \
	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		__p = to_i915((struct drm_device *)p); \
	else \
		BUILD_BUG(); \
	__p; \
})
C
Chris Wilson 已提交
2340
#define INTEL_INFO(p) 	(&__I915__(p)->info)
2341
#define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
2342

2343 2344
#define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
#define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
2345
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
2346
#define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)
2347
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
2348 2349
#define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)
#define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)
2350 2351 2352
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
2353
#define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)
2354
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
2355 2356
#define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)
#define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)
2357 2358
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
2359
#define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)
2360
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
2361 2362 2363 2364 2365 2366
#define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \
				 INTEL_DEVID(dev) == 0x0152 || \
				 INTEL_DEVID(dev) == 0x015a)
#define IS_SNB_GT1(dev)		(INTEL_DEVID(dev) == 0x0102 || \
				 INTEL_DEVID(dev) == 0x0106 || \
				 INTEL_DEVID(dev) == 0x010A)
2367
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
2368
#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2369
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
2370
#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2371
#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
2372
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
2373
#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
2374
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
B
Ben Widawsky 已提交
2375
#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
2376 2377 2378
				 ((INTEL_DEVID(dev) & 0xf) == 0x2  || \
				 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
				 (INTEL_DEVID(dev) & 0xf) == 0xe))
R
Rodrigo Vivi 已提交
2379 2380
#define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
B
Ben Widawsky 已提交
2381
#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
2382
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2383
#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
2384
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2385
/* ULX machines are also considered ULT. */
2386 2387
#define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \
				 INTEL_DEVID(dev) == 0x0A1E)
2388
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2389

2390 2391 2392 2393 2394 2395
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2396 2397 2398 2399 2400
#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
2401
#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
B
Ben Widawsky 已提交
2402
#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen == 8)
2403
#define IS_GEN9(dev)	(INTEL_INFO(dev)->gen == 9)
2404

2405 2406 2407 2408
#define RENDER_RING		(1<<RCS)
#define BSD_RING		(1<<VCS)
#define BLT_RING		(1<<BCS)
#define VEBOX_RING		(1<<VECS)
2409
#define BSD2_RING		(1<<VCS2)
2410
#define HAS_BSD(dev)		(INTEL_INFO(dev)->ring_mask & BSD_RING)
2411
#define HAS_BSD2(dev)		(INTEL_INFO(dev)->ring_mask & BSD2_RING)
2412 2413 2414 2415
#define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
#define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2416
				 __I915__(dev)->ellc_size)
2417 2418
#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)

2419
#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
2420
#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
2421 2422
#define USES_PPGTT(dev)		(i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt == 2)
2423

2424
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2425 2426
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

2427 2428
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2429 2430 2431 2432 2433 2434 2435 2436
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2437

2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_DIGITAL_OUTPUTS(dev)	(!IS_GEN2(dev) && !IS_PINEVIEW(dev))
#define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2451
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2452

2453
#define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2454

2455
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2456
#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
2457 2458
#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2459
#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
I
Imre Deak 已提交
2460
				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2461 2462
#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
#define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
P
Paulo Zanoni 已提交
2463

2464 2465 2466 2467 2468 2469
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2470 2471
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2472

2473
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2474
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2475
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2476 2477
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
B
Ben Widawsky 已提交
2478
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2479
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2480

2481 2482
#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))

2483 2484 2485
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2486

2487 2488
#define GT_FREQUENCY_MULTIPLIER 50

2489 2490
#include "i915_trace.h"

R
Rob Clark 已提交
2491
extern const struct drm_ioctl_desc i915_ioctls[];
2492 2493
extern int i915_max_ioctl;

2494 2495
extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
extern int i915_resume_legacy(struct drm_device *dev);
2496 2497 2498
extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);

2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511
/* i915_params.c */
struct i915_params {
	int modeset;
	int panel_ignore_lid;
	unsigned int powersave;
	int semaphores;
	unsigned int lvds_downclock;
	int lvds_channel_mode;
	int panel_use_ssc;
	int vbt_sdvo_panel_type;
	int enable_rc6;
	int enable_fbc;
	int enable_ppgtt;
2512
	int enable_execlists;
2513 2514 2515 2516
	int enable_psr;
	unsigned int preliminary_hw_support;
	int disable_power_well;
	int enable_ips;
2517
	int invert_brightness;
2518
	int enable_cmd_parser;
2519 2520 2521
	/* leave bools at the end to not create holes */
	bool enable_hangcheck;
	bool fastboot;
2522 2523
	bool prefault_disable;
	bool reset;
2524
	bool disable_display;
2525
	bool disable_vtd_wa;
2526
	int use_mmio_flip;
2527
	bool mmio_debug;
R
Rob Clark 已提交
2528
	bool verbose_state_checks;
2529 2530 2531
};
extern struct i915_params i915 __read_mostly;

L
Linus Torvalds 已提交
2532
				/* i915_dma.c */
2533
extern int i915_driver_load(struct drm_device *, unsigned long flags);
J
Jesse Barnes 已提交
2534
extern int i915_driver_unload(struct drm_device *);
2535
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2536
extern void i915_driver_lastclose(struct drm_device * dev);
2537
extern void i915_driver_preclose(struct drm_device *dev,
2538
				 struct drm_file *file);
2539
extern void i915_driver_postclose(struct drm_device *dev,
2540
				  struct drm_file *file);
2541
extern int i915_driver_device_is_agp(struct drm_device * dev);
2542
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2543 2544
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2545
#endif
2546
extern int intel_gpu_reset(struct drm_device *dev);
2547
extern int i915_reset(struct drm_device *dev);
2548 2549 2550 2551
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2552
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2553
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2554

L
Linus Torvalds 已提交
2555
/* i915_irq.c */
2556
void i915_queue_hangcheck(struct drm_device *dev);
2557 2558 2559
__printf(3, 4)
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2560

2561 2562
extern void intel_irq_init(struct drm_i915_private *dev_priv);
extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2563 2564
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2565 2566

extern void intel_uncore_sanitize(struct drm_device *dev);
2567 2568
extern void intel_uncore_early_sanitize(struct drm_device *dev,
					bool restore_forcewake);
2569 2570
extern void intel_uncore_init(struct drm_device *dev);
extern void intel_uncore_check_errors(struct drm_device *dev);
2571
extern void intel_uncore_fini(struct drm_device *dev);
2572
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2573
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2574
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2575
				enum forcewake_domains domains);
2576
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2577
				enum forcewake_domains domains);
2578
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2579

2580
void
2581
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2582
		     u32 status_mask);
2583 2584

void
2585
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2586
		      u32 status_mask);
2587

2588 2589
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600
void
ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
void
ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
#define ibx_enable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), (bits))
#define ibx_disable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), 0)
2601

2602 2603 2604 2605 2606 2607 2608 2609 2610
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2611 2612
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2613 2614 2615 2616
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
2617 2618 2619 2620 2621 2622
void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
					struct intel_engine_cs *ring);
void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
					 struct drm_file *file,
					 struct intel_engine_cs *ring,
					 struct drm_i915_gem_object *obj);
2623 2624 2625 2626 2627 2628 2629 2630
int i915_gem_ringbuffer_submission(struct drm_device *dev,
				   struct drm_file *file,
				   struct intel_engine_cs *ring,
				   struct intel_context *ctx,
				   struct drm_i915_gem_execbuffer2 *args,
				   struct list_head *vmas,
				   struct drm_i915_gem_object *batch_obj,
				   u64 exec_start, u32 flags);
2631 2632
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
2633 2634
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
2635 2636
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
2637 2638 2639 2640
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2641 2642
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
2643 2644
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
2645 2646 2647 2648
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2649 2650 2651
int i915_gem_init_userptr(struct drm_device *dev);
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
2652 2653
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
2654 2655
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2656
void i915_gem_load(struct drm_device *dev);
2657 2658 2659 2660 2661 2662
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
			      long target,
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
2663 2664
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
2665 2666
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
2667 2668
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size);
2669 2670
void i915_init_vm(struct drm_i915_private *dev_priv,
		  struct i915_address_space *vm);
2671
void i915_gem_free_object(struct drm_gem_object *obj);
B
Ben Widawsky 已提交
2672
void i915_gem_vma_destroy(struct i915_vma *vma);
2673

2674 2675
#define PIN_MAPPABLE 0x1
#define PIN_NONBLOCK 0x2
2676
#define PIN_GLOBAL 0x4
2677 2678
#define PIN_OFFSET_BIAS 0x8
#define PIN_OFFSET_MASK (~4095)
2679 2680 2681 2682 2683 2684
int __must_check i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
					  struct i915_address_space *vm,
					  uint32_t alignment,
					  uint64_t flags,
					  const struct i915_ggtt_view *view);
static inline
2685
int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
B
Ben Widawsky 已提交
2686
				     struct i915_address_space *vm,
2687
				     uint32_t alignment,
2688 2689 2690 2691 2692 2693 2694 2695
				     uint64_t flags)
{
	return i915_gem_object_pin_view(obj, vm, alignment, flags,
						&i915_ggtt_view_normal);
}

int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		  u32 flags);
2696
int __must_check i915_vma_unbind(struct i915_vma *vma);
2697
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2698
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2699
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2700

2701 2702 2703
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    int *needs_clflush);

2704
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2705 2706
static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
{
2707 2708 2709
	struct sg_page_iter sg_iter;

	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2710
		return sg_page_iter_page(&sg_iter);
2711 2712

	return NULL;
2713
}
2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724
static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages == NULL);
	obj->pages_pin_count++;
}
static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages_pin_count == 0);
	obj->pages_pin_count--;
}

2725
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2726
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2727
			 struct intel_engine_cs *to);
B
Ben Widawsky 已提交
2728
void i915_vma_move_to_active(struct i915_vma *vma,
2729
			     struct intel_engine_cs *ring);
2730 2731 2732
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
2733 2734
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
2735 2736 2737 2738 2739 2740 2741 2742 2743
/**
 * Returns true if seq1 is later than seq2.
 */
static inline bool
i915_seqno_passed(uint32_t seq1, uint32_t seq2)
{
	return (int32_t)(seq1 - seq2) >= 0;
}

2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755
static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
					      bool lazy_coherency)
{
	u32 seqno;

	BUG_ON(req == NULL);

	seqno = req->ring->get_seqno(req->ring, lazy_coherency);

	return i915_seqno_passed(seqno, req->seqno);
}

2756 2757
int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2758
int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2759
int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2760

2761 2762
bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2763

2764
struct drm_i915_gem_request *
2765
i915_gem_find_active_request(struct intel_engine_cs *ring);
2766

2767
bool i915_gem_retire_requests(struct drm_device *dev);
2768
void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2769
int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2770
				      bool interruptible);
2771
int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
2772

2773 2774 2775
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
	return unlikely(atomic_read(&error->reset_counter)
M
Mika Kuoppala 已提交
2776
			& (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2777 2778 2779 2780
}

static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
M
Mika Kuoppala 已提交
2781 2782 2783 2784 2785 2786
	return atomic_read(&error->reset_counter) & I915_WEDGED;
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
	return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2787
}
2788

2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800
static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
}

static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
}

2801
void i915_gem_reset(struct drm_device *dev);
2802
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2803
int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2804
int __must_check i915_gem_init(struct drm_device *dev);
2805
int i915_gem_init_rings(struct drm_device *dev);
2806
int __must_check i915_gem_init_hw(struct drm_device *dev);
2807
int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2808
void i915_gem_init_swizzling(struct drm_device *dev);
J
Jesse Barnes 已提交
2809
void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2810
int __must_check i915_gpu_idle(struct drm_device *dev);
2811
int __must_check i915_gem_suspend(struct drm_device *dev);
2812
int __i915_add_request(struct intel_engine_cs *ring,
2813
		       struct drm_file *file,
2814 2815 2816
		       struct drm_i915_gem_object *batch_obj);
#define i915_add_request(ring) \
	__i915_add_request(ring, NULL, NULL)
2817
int __i915_wait_request(struct drm_i915_gem_request *req,
2818 2819 2820 2821
			unsigned reset_counter,
			bool interruptible,
			s64 *timeout,
			struct drm_i915_file_private *file_priv);
2822
int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2823
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2824 2825 2826 2827
int __must_check
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
2828 2829
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
2830 2831
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
2832
				     struct intel_engine_cs *pipelined);
2833
void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2834
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2835
				int align);
2836
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2837
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2838

2839 2840
uint32_t
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2841
uint32_t
2842 2843
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
			    int tiling_mode, bool fenced);
2844

2845 2846 2847
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

2848 2849 2850 2851 2852 2853
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

2854 2855
void i915_gem_restore_fences(struct drm_device *dev);

2856 2857 2858 2859
unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o,
				       struct i915_address_space *vm,
				       enum i915_ggtt_view_type view);
static inline
2860
unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2861 2862 2863 2864
				  struct i915_address_space *vm)
{
	return i915_gem_obj_offset_view(o, vm, I915_GGTT_VIEW_NORMAL);
}
2865
bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2866 2867 2868 2869
bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o,
			     struct i915_address_space *vm,
			     enum i915_ggtt_view_type view);
static inline
2870
bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2871 2872 2873 2874 2875
			struct i915_address_space *vm)
{
	return i915_gem_obj_bound_view(o, vm, I915_GGTT_VIEW_NORMAL);
}

2876 2877
unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
				struct i915_address_space *vm);
2878 2879 2880 2881
struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj,
					  struct i915_address_space *vm,
					  const struct i915_ggtt_view *view);
static inline
2882
struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893
				     struct i915_address_space *vm)
{
	return i915_gem_obj_to_vma_view(obj, vm, &i915_ggtt_view_normal);
}

struct i915_vma *
i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj,
				       struct i915_address_space *vm,
				       const struct i915_ggtt_view *view);

static inline
2894 2895
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2896 2897 2898 2899 2900
				  struct i915_address_space *vm)
{
	return i915_gem_obj_lookup_or_create_vma_view(obj, vm,
						&i915_ggtt_view_normal);
}
2901 2902

struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
B
Ben Widawsky 已提交
2903 2904 2905 2906 2907 2908 2909
static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
	struct i915_vma *vma;
	list_for_each_entry(vma, &obj->vma_list, vma_link)
		if (vma->pin_count > 0)
			return true;
	return false;
}
2910

2911
/* Some GGTT VM helpers */
2912
#define i915_obj_to_ggtt(obj) \
2913 2914 2915 2916 2917 2918 2919 2920
	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
static inline bool i915_is_ggtt(struct i915_address_space *vm)
{
	struct i915_address_space *ggtt =
		&((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
	return vm == ggtt;
}

2921 2922 2923 2924 2925 2926 2927 2928 2929
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	WARN_ON(i915_is_ggtt(vm));

	return container_of(vm, struct i915_hw_ppgtt, base);
}


2930 2931
static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
{
2932
	return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
2933 2934 2935 2936 2937
}

static inline unsigned long
i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
{
2938
	return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
2939 2940 2941 2942 2943
}

static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
{
2944
	return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2945
}
B
Ben Widawsky 已提交
2946 2947 2948 2949

static inline int __must_check
i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
		      uint32_t alignment,
2950
		      unsigned flags)
B
Ben Widawsky 已提交
2951
{
2952 2953
	return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
				   alignment, flags | PIN_GLOBAL);
B
Ben Widawsky 已提交
2954
}
2955

2956 2957 2958 2959 2960 2961 2962 2963
static inline int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
{
	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
}

void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);

2964
/* i915_gem_context.c */
2965
int __must_check i915_gem_context_init(struct drm_device *dev);
2966
void i915_gem_context_fini(struct drm_device *dev);
2967
void i915_gem_context_reset(struct drm_device *dev);
2968
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2969
int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2970
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2971
int i915_switch_context(struct intel_engine_cs *ring,
2972 2973
			struct intel_context *to);
struct intel_context *
2974
i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2975
void i915_gem_context_free(struct kref *ctx_ref);
2976 2977
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
2978
static inline void i915_gem_context_reference(struct intel_context *ctx)
2979
{
2980
	kref_get(&ctx->ref);
2981 2982
}

2983
static inline void i915_gem_context_unreference(struct intel_context *ctx)
2984
{
2985
	kref_put(&ctx->ref, i915_gem_context_free);
2986 2987
}

2988
static inline bool i915_gem_context_is_default(const struct intel_context *c)
2989
{
2990
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2991 2992
}

2993 2994 2995 2996
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
2997 2998 2999 3000
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3001

3002 3003 3004 3005 3006 3007
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct drm_device *dev,
					  struct i915_address_space *vm,
					  int min_size,
					  unsigned alignment,
					  unsigned cache_level,
3008 3009
					  unsigned long start,
					  unsigned long end,
3010
					  unsigned flags);
3011 3012
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
int i915_gem_evict_everything(struct drm_device *dev);
3013

3014
/* belongs in i915_gem_gtt.h */
3015
static inline void i915_gem_chipset_flush(struct drm_device *dev)
3016 3017 3018 3019
{
	if (INTEL_INFO(dev)->gen < 6)
		intel_gtt_chipset_flush();
}
3020

3021 3022
/* i915_gem_stolen.c */
int i915_gem_init_stolen(struct drm_device *dev);
B
Ben Widawsky 已提交
3023
int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
3024
void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
3025
void i915_gem_cleanup_stolen(struct drm_device *dev);
3026 3027
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3028 3029 3030 3031 3032
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3033

3034
/* i915_gem_tiling.c */
3035
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3036
{
3037
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3038 3039 3040 3041 3042

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		obj->tiling_mode != I915_TILING_NONE;
}

3043
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3044 3045
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3046 3047

/* i915_gem_debug.c */
3048 3049
#if WATCH_LISTS
int i915_verify_lists(struct drm_device *dev);
3050
#else
3051
#define i915_verify_lists(dev) 0
3052
#endif
L
Linus Torvalds 已提交
3053

3054
/* i915_debugfs.c */
3055 3056
int i915_debugfs_init(struct drm_minor *minor);
void i915_debugfs_cleanup(struct drm_minor *minor);
3057
#ifdef CONFIG_DEBUG_FS
3058 3059
void intel_display_crc_init(struct drm_device *dev);
#else
3060
static inline void intel_display_crc_init(struct drm_device *dev) {}
3061
#endif
3062 3063

/* i915_gpu_error.c */
3064 3065
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3066 3067
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3068
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3069
			      struct drm_i915_private *i915,
3070 3071 3072 3073 3074 3075
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3076 3077
void i915_capture_error_state(struct drm_device *dev, bool wedge,
			      const char *error_msg);
3078 3079 3080 3081 3082 3083
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);

void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3084
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3085

3086 3087 3088 3089 3090 3091 3092
/* i915_gem_batch_pool.c */
void i915_gem_batch_pool_init(struct drm_device *dev,
			      struct i915_gem_batch_pool *pool);
void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool);
struct drm_i915_gem_object*
i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size);

3093
/* i915_cmd_parser.c */
3094
int i915_cmd_parser_get_version(void);
3095 3096 3097 3098
int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
int i915_parse_cmds(struct intel_engine_cs *ring,
3099
		    struct drm_i915_gem_object *batch_obj,
3100
		    struct drm_i915_gem_object *shadow_batch_obj,
3101
		    u32 batch_start_offset,
3102
		    u32 batch_len,
3103 3104
		    bool is_master);

3105 3106 3107
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
3108

3109 3110 3111
/* i915_ums.c */
void i915_save_display_reg(struct drm_device *dev);
void i915_restore_display_reg(struct drm_device *dev);
3112

B
Ben Widawsky 已提交
3113 3114 3115 3116
/* i915_sysfs.c */
void i915_setup_sysfs(struct drm_device *dev_priv);
void i915_teardown_sysfs(struct drm_device *dev_priv);

3117 3118 3119
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
3120
static inline bool intel_gmbus_is_port_valid(unsigned port)
3121
{
3122
	return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
3123 3124 3125 3126
}

extern struct i2c_adapter *intel_gmbus_get_adapter(
		struct drm_i915_private *dev_priv, unsigned port);
C
Chris Wilson 已提交
3127 3128
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3129
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3130 3131 3132
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3133 3134
extern void intel_i2c_reset(struct drm_device *dev);

3135
/* intel_opregion.c */
3136
#ifdef CONFIG_ACPI
3137
extern int intel_opregion_setup(struct drm_device *dev);
3138 3139
extern void intel_opregion_init(struct drm_device *dev);
extern void intel_opregion_fini(struct drm_device *dev);
3140
extern void intel_opregion_asle_intr(struct drm_device *dev);
3141 3142
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3143 3144
extern int intel_opregion_notify_adapter(struct drm_device *dev,
					 pci_power_t state);
3145
#else
3146
static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3147 3148
static inline void intel_opregion_init(struct drm_device *dev) { return; }
static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3149
static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3150 3151 3152 3153 3154
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3155 3156 3157 3158 3159
static inline int
intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
{
	return 0;
}
3160
#endif
3161

J
Jesse Barnes 已提交
3162 3163 3164 3165 3166 3167 3168 3169 3170
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

J
Jesse Barnes 已提交
3171
/* modesetting */
3172
extern void intel_modeset_init_hw(struct drm_device *dev);
J
Jesse Barnes 已提交
3173
extern void intel_modeset_init(struct drm_device *dev);
3174
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3175
extern void intel_modeset_cleanup(struct drm_device *dev);
3176
extern void intel_connector_unregister(struct intel_connector *);
3177
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3178 3179
extern void intel_modeset_setup_hw_state(struct drm_device *dev,
					 bool force_restore);
3180
extern void i915_redisable_vga(struct drm_device *dev);
3181
extern void i915_redisable_vga_power_on(struct drm_device *dev);
3182
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
P
Paulo Zanoni 已提交
3183
extern void intel_init_pch_refclk(struct drm_device *dev);
3184
extern void gen6_set_rps(struct drm_device *dev, u8 val);
3185
extern void valleyview_set_rps(struct drm_device *dev, u8 val);
3186 3187
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
				  bool enable);
3188 3189
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
B
Ben Widawsky 已提交
3190
extern int intel_enable_rc6(const struct drm_device *dev);
3191

3192
extern bool i915_semaphore_is_enabled(struct drm_device *dev);
B
Ben Widawsky 已提交
3193 3194
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3195 3196
int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3197

3198 3199
void intel_notify_mmio_flip(struct intel_engine_cs *ring);

3200 3201
/* overlay */
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3202 3203
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3204 3205

extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3206
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3207 3208
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
3209

3210 3211
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3212 3213

/* intel_sideband.c */
3214 3215
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3216
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3217 3218 3219 3220 3221 3222
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3223 3224
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3225 3226
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3227 3228
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3229 3230 3231 3232
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3233 3234
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3235

3236 3237
int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
B
Ben Widawsky 已提交
3238

3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3252 3253 3254 3255 3256 3257
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
 * machine death. You have been warned.
 */
3258 3259
#define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3260

3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
		u32 upper = I915_READ(upper_reg);			\
		u32 lower = I915_READ(lower_reg);			\
		u32 tmp = I915_READ(upper_reg);				\
		if (upper != tmp) {					\
			upper = tmp;					\
			lower = I915_READ(lower_reg);			\
			WARN_ON(I915_READ(upper_reg) != upper);		\
		}							\
		(u64)upper << 32 | lower; })

3272 3273 3274
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3275 3276 3277 3278
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3279

3280 3281
static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
{
3282
	if (IS_VALLEYVIEW(dev))
3283
		return VLV_VGACNTRL;
3284 3285
	else if (INTEL_INFO(dev)->gen >= 5)
		return CPU_VGACNTRL;
3286 3287 3288 3289
	else
		return VGACNTRL;
}

V
Ville Syrjälä 已提交
3290 3291 3292 3293 3294
static inline void __user *to_user_ptr(u64 address)
{
	return (void __user *)(uintptr_t)address;
}

3295 3296 3297 3298 3299 3300 3301
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3302 3303 3304 3305 3306
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3307 3308 3309 3310 3311 3312 3313 3314
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3315 3316 3317 3318 3319 3320 3321 3322 3323
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3324
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3325 3326 3327 3328 3329 3330 3331 3332 3333 3334

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3335 3336 3337 3338
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3339 3340 3341
	}
}

3342 3343 3344 3345 3346 3347 3348
static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
				      struct drm_i915_gem_request *req)
{
	if (ring->trace_irq_req == NULL && ring->irq_get(ring))
		i915_gem_request_assign(&ring->trace_irq_req, req);
}

L
Linus Torvalds 已提交
3349
#endif