Backend, Fusion: another implementation for instruction fusion case 'lui + addi(w)' without widening imm bits

*pass: vmand.mm, vmnand.mm, vmandn.mm, vmxor.mm, vmor.mm, vmnor.mm, vmorn.mm, vmxnor.mm

For consecutive instructions that do not raise exceptions,
they can share a same rob entry and reduce rob consumption.

Only scalar instructions are supported now.

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Co-authored-by: Nfdy <841513191@qq.com>

DefaultConfig：
[ALU]*2 + [ALU + MUL]*2 + [ALU+BJU]*2 + IMISC(to Vf) + IMISC(to Int)
IssueQueueSize is 32
RegfileReadPort: ALU * 6 + Load * 2 are the base, other exeUnit reuse the src2 port

MinimalConfig:
Same with Default Config except that issueQueueSize is 4.

TODO: minimize exu/issuequeue num of MinimalConfig
TODO: larger ALU exe window needs larger ifetch, decode, rename, dispatch window.

* Prepare for merge master

* Prepare for merge master

* Data in dontTouch should be hardware type not literal type.
* Mux1H will return input data directly, when there is only one sel input. When input data is not hardware type, a firrtl.annotations.AnnotationException will be raised.

* Since all exu used as source of wake-up must be ready at OG1 stage, there is no need to take the cancel signal of indirect source of wake-up into consideration.

* PerfCnt related inst run in csr should assign isPerfCnt as true