params,backend: refactor RegFile parameters

src/main/scala/top/Configs.scala

@@ -62,9 +62,6 @@ class MinimalConfig(n: Int = 1) extends Config(
         RenameWidth = 2,
         CommitWidth = 2,
         FetchWidth = 4,
-        NRPhyRegs = 96,
-        IntPhyRegs = 96,
-        VfPhyRegs = 96,
         VirtualLoadQueueSize = 16,
         LoadQueueRARSize = 16,
         LoadQueueRAWSize = 12,
@@ -89,14 +86,14 @@ class MinimalConfig(n: Int = 1) extends Config(
           LsDqDeqWidth = 4
         ),
         intPreg = IntPregParams(
-          numEntries = 128,
-          numRead = 14,
-          numWrite = 8,
+          numEntries = 64,
+          numRead = Some(14),
+          numWrite = Some(8),
         ),
         vfPreg = VfPregParams(
-          numEntries = 128,
-          numRead = 14,
-          numWrite = 8,
+          numEntries = 96,
+          numRead = Some(14),
+          numWrite = Some(8),
         ),
         icacheParameters = ICacheParameters(
           nSets = 64, // 16KB ICache

src/main/scala/utils/BundleUtils.scala

+package utils
+
+import chisel3._
+import chisel3.util._
+
+object BundleUtils {
+  def makeValid[T <: Data](valid: Bool, bits: T): ValidIO[T] = {
+    val x = Wire(ValidIO(bits.cloneType))
+    x.valid := valid
+    x.bits := bits
+    x
+  }
+}

src/main/scala/utils/SeqUtils.scala

 package utils
 
+import chisel3._
+import chisel3.util._
+
 import scala.collection.mutable
 
 object SeqUtils {
@@ -18,4 +21,21 @@ object SeqUtils {
     }
     res
   }
+
+  type Seq2[+T] = Seq[Seq[T]]
+  type Seq3[+T] = Seq2[Seq[T]]
+  type MixedVec2[T <: Data] = MixedVec[MixedVec[T]]
+  type MixedVec3[T <: Data] = MixedVec2[MixedVec[T]]
+
+  def mapToMixedVec[T, A <: Data](in: Seq[T], f: T => A): MixedVec[A] = {
+    MixedVec(in.map(f))
+  }
+
+  def mapToMixedVec2[T, A <: Data](in: Seq2[T], f: T => A): MixedVec2[A] = {
+    MixedVec(in.map(x => mapToMixedVec(x, f)))
+  }
+
+  def mapToMixedVec3[T, A <: Data](in: Seq3[T], f: T => A): MixedVec3[A] = {
+    MixedVec(in.map(x => mapToMixedVec2(x, f)))
+  }
 }

src/main/scala/xiangshan/Parameters.scala

@@ -150,8 +150,6 @@ case class XSCoreParameters
   VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig
   VCONFIG_IDX: Int = 32,
   NRPhyRegs: Int = 192,
-  IntPhyRegs: Int = 192,
-  VfPhyRegs: Int = 192,
   VirtualLoadQueueSize: Int = 80,
   LoadQueueRARSize: Int = 80,
   LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2.
@@ -174,14 +172,14 @@ case class XSCoreParameters
     LsDqDeqWidth = 6,
   ),
   intPreg: PregParams = IntPregParams(
-    numEntries = 256,
-    numRead = 14,
-    numWrite = 8,
+    numEntries = 192,
+    numRead = None,
+    numWrite = None,
   ),
   vfPreg: VfPregParams = VfPregParams(
-    numEntries = 256,
-    numRead = 14,
-    numWrite = 8,
+    numEntries = 192,
+    numRead = None,
+    numWrite = None,
   ),
   prefetcher: Option[PrefetcherParams] = Some(SMSParams()),
   LoadPipelineWidth: Int = 2,
@@ -297,102 +295,93 @@ case class XSCoreParameters
   val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength
   val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now
 
-  def intSchdParams = {
+  val intSchdParams = {
     implicit val schdType: SchedulerType = IntScheduler()
-    val pregBits = intPreg.addrWidth
-    val numRfRead = intPreg.numRead
-    val numRfWrite = intPreg.numWrite
     SchdBlockParams(Seq(
       IssueBlockParams(Seq(
         ExeUnitParams("IEX0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))),
         ExeUnitParams("IEX1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams("IEX2", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))),
         ExeUnitParams("IEX3", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))),
         ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, VSetRiWvfCfg), Seq(IntWB(port = 4, 1), VfWB(4, 0)), Seq(Seq(IntRD(8, 1)), Seq(IntRD(9, 1)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 5, 1)), Seq(Seq(IntRD(6, Int.MaxValue)), Seq(IntRD(7, Int.MaxValue)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
     ),
       numPregs = intPreg.numEntries,
-      numRfReadWrite = Some((numRfRead, numRfWrite)),
       numDeqOutside = 0,
       schdType = schdType,
       rfDataWidth = intPreg.dataCfg.dataWidth,
       numUopIn = dpParams.IntDqDeqWidth,
     )
   }
-  def vfSchdParams = {
+  val vfSchdParams = {
     implicit val schdType: SchedulerType = VfScheduler()
-    val pregBits = vfPreg.addrWidth
-    val numRfRead = vfPreg.numRead
-    val numRfWrite = vfPreg.numWrite
     SchdBlockParams(Seq(
       IssueBlockParams(Seq(
         ExeUnitParams("VEX0", Seq(VialuCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
         ExeUnitParams("VEX1", Seq(VimacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
-        ExeUnitParams("FEX0", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)))),
+        ExeUnitParams("FEX0", Seq(FmacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)))),
         ExeUnitParams("FEX1", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(VfRD(6, 0)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams("FEX2", Seq(FDivSqrtCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(11, 0)), Seq(VfRD(12, 0)))),
         ExeUnitParams("FEX3", Seq(F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 2, 0), IntWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams("VEX2", Seq(VppuCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
         ExeUnitParams("VEX3", Seq(VipuCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams("VEX2", Seq(VfaluCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
         ExeUnitParams("VEX3", Seq(VfmaCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams("VEX4", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
     ),
       numPregs = vfPreg.numEntries,
-      numRfReadWrite = Some((numRfRead, numRfWrite)),
       numDeqOutside = 0,
       schdType = schdType,
       rfDataWidth = vfPreg.dataCfg.dataWidth,
       numUopIn = dpParams.FpDqDeqWidth,
     )
   }
-  def memSchdParams = {
+
+  val memSchdParams = {
     implicit val schdType: SchedulerType = MemScheduler()
-    val pregBits = vfPreg.addrWidth max intPreg.addrWidth
     val rfDataWidth = 64
 
     SchdBlockParams(Seq(
       IssueBlockParams(Seq(
         ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(10, 0)))),
         ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(11, 0)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(12, 0)))),
         ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(7, 1)), Seq(Seq(IntRD(13, 0)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(8, Int.MaxValue), VfRD(12, Int.MaxValue)))),
-        ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(13, Int.MaxValue)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2),
+        ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(10, Int.MaxValue)))),
+      ), numEntries = 8, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))),
         ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))),
-      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2),
+      ), numEntries = 8, numEnq = 2),
     ),
       numPregs = intPreg.numEntries max vfPreg.numEntries,
-      numRfReadWrite = None,
       numDeqOutside = 0,
       schdType = schdType,
       rfDataWidth = rfDataWidth,
@@ -564,12 +553,9 @@ trait HasXSParameter {
   val FpLogicRegs = coreParams.FpLogicRegs
   val VecLogicRegs = coreParams.VecLogicRegs
   val VCONFIG_IDX = coreParams.VCONFIG_IDX
-  val NRPhyRegs = coreParams.NRPhyRegs
-  val PhyRegIdxWidth = log2Up(NRPhyRegs)
-  val IntPhyRegs = coreParams.IntPhyRegs
-  val VfPhyRegs = coreParams.VfPhyRegs
-  val IntPregIdxWidth = log2Up(IntPhyRegs)
-  val VfPregIdxWidth = log2Up(VfPhyRegs)
+  val IntPhyRegs = coreParams.intPreg.numEntries
+  val VfPhyRegs = coreParams.vfPreg.numEntries
+  val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs)
   val RobSize = coreParams.RobSize
   val RabSize = coreParams.RabSize
   val IntRefCounterWidth = log2Ceil(RobSize)

src/main/scala/xiangshan/backend/Backend.scala

@@ -8,6 +8,7 @@ import utility.ZeroExt
 import xiangshan._
 import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, MemExuInput, MemExuOutput}
 import xiangshan.backend.ctrlblock.CtrlBlock
+import xiangshan.backend.datapath.DataConfig.{IntData, VecData}
 import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD}
 import xiangshan.backend.datapath.WbConfig._
 import xiangshan.backend.datapath._
@@ -78,22 +79,22 @@ class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyMod
   }
 
   println(s"[Backend] Int RdConfigs: ExuName(Priority)")
-  for ((port, seq) <- params.getRdPortParams[IntRD]) {
+  for ((port, seq) <- params.getRdPortParams(IntData())) {
     println(s"[Backend]   port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
   }
 
   println(s"[Backend] Int WbConfigs: ExuName(Priority)")
-  for ((port, seq) <- params.getWbPortParams[IntWB]) {
+  for ((port, seq) <- params.getWbPortParams(IntData())) {
     println(s"[Backend]   port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
   }
 
   println(s"[Backend] Vf RdConfigs: ExuName(Priority)")
-  for ((port, seq) <- params.getRdPortParams[VfRD]) {
+  for ((port, seq) <- params.getRdPortParams(VecData())) {
     println(s"[Backend]   port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
   }
 
   println(s"[Backend] Vf WbConfigs: ExuName(Priority)")
-  for ((port, seq) <- params.getWbPortParams[VfWB]) {
+  for ((port, seq) <- params.getWbPortParams(VecData())) {
     println(s"[Backend]   port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
   }
 

src/main/scala/xiangshan/backend/BackendParams.scala

@@ -28,7 +28,7 @@ import xiangshan.backend.exu.ExeUnitParams
 import xiangshan.backend.issue._
 import xiangshan.backend.regfile._
 
-import scala.reflect.ClassTag
+import scala.reflect.{ClassTag, classTag}
 
 case class BackendParams(
   schdParams : Map[SchedulerType, SchdBlockParams],
@@ -52,6 +52,10 @@ case class BackendParams(
 
   def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get
   def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get
+  def getPregParams: Map[DataConfig, PregParams] = {
+    pregParams.map(x => (x.dataCfg, x)).toMap
+  }
+
   def pregIdxWidth = pregParams.map(_.addrWidth).max
 
   def numSrc      : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max
@@ -71,12 +75,11 @@ case class BackendParams(
 
   def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum
 
-  def numIntWb = intPregParams.numWrite
-  def numVfWb = vfPregParams.numWrite
+  def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg)
+  def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg)
+
   def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum
   def numExu = allSchdParams.map(_.numExu).sum
-  def numRfRead  = 14
-  def numRfWrite = 8
   def vconfigPort = 0 // Todo: remove it
 
   def numException = allExuParams.count(_.exceptionOut.nonEmpty)
@@ -84,13 +87,11 @@ case class BackendParams(
   def numRedirect = allSchdParams.map(_.numRedirect).sum
 
   def genIntWriteBackBundle(implicit p: Parameters) = {
-    // Todo: limit write port
-    Seq.tabulate(numIntWb)(x => new RfWritePortWithConfig(IntData(), intPregParams.addrWidth))
+    Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth))
   }
 
   def genVfWriteBackBundle(implicit p: Parameters) = {
-    // Todo: limit write port
-    Seq.tabulate(numVfWb)(x => new RfWritePortWithConfig(VecData(), intPregParams.addrWidth))
+    Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth))
   }
 
   def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = {
@@ -102,26 +103,26 @@ case class BackendParams(
   }
 
   def getIntWbArbiterParams: WbArbiterParams = {
-    val intWbCfgs: Seq[WbConfig] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt))
-    datapath.WbArbiterParams(intWbCfgs, intPregParams)
+    val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB])
+    datapath.WbArbiterParams(intWbCfgs, intPregParams, this)
   }
 
   def getVfWbArbiterParams: WbArbiterParams = {
-    val vfWbCfgs = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp))
-    datapath.WbArbiterParams(vfWbCfgs, vfPregParams)
+    val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)).map(_.asInstanceOf[VfWB])
+    datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this)
   }
 
   /**
     * Get regfile read port params
-    * @param tag ClassTag of T
-    * @tparam T [[IntRD]] or [[VfRD]]
+    *
+    * @param dataCfg [[IntData]] or [[VecData]]
     * @return Seq[port->Seq[(exuIdx, priority)]
     */
-  def getRdPortParams[T <: RdConfig](implicit tag: ClassTag[T]): Seq[(Int, Seq[(Int, Int)])] = {
+  def getRdPortParams(dataCfg: DataConfig) = {
     // port -> Seq[exuIdx, priority]
     val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams
       .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx)))
-      .filter { x => ClassTag(x._1.getClass) == tag }
+      .filter { x => x._1.getDataConfig == dataCfg }
       .map(x => (x._1.port, (x._2, x._1.priority)))
       .groupBy(_._1)
       .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority })))
@@ -133,14 +134,13 @@ case class BackendParams(
   /**
     * Get regfile write back port params
     *
-    * @param tag ClassTag of T
-    * @tparam T [[IntWB]] or [[VfWB]]
+    * @param dataCfg [[IntData]] or [[VecData]]
     * @return Seq[port->Seq[(exuIdx, priority)]
     */
-  def getWbPortParams[T <: PregWB](implicit tag: ClassTag[T]) = {
+  def getWbPortParams(dataCfg: DataConfig) = {
     val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams
-      .flatMap(x => x.wbPortConfigs.map(xx => (xx.asInstanceOf[PregWB], x.exuIdx)))
-      .filter { x => ClassTag(x._1.getClass) == tag }
+      .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx)))
+      .filter { x => x._1.dataCfg == dataCfg }
       .map(x => (x._1.port, (x._2, x._1.priority)))
       .groupBy(_._1)
       .map(x => (x._1, x._2.map(_._2)))
@@ -149,6 +149,79 @@ case class BackendParams(
     cfgs
   }
 
+  def getRdPortIndices(dataCfg: DataConfig) = {
+    this.getRdPortParams(dataCfg).map(_._1)
+  }
+
+  def getWbPortIndices(dataCfg: DataConfig) = {
+    this.getWbPortParams(dataCfg).map(_._1)
+  }
+
+  def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = {
+    val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map(
+      _.exuBlockParams.map(
+        _.rfrPortConfigs.map(
+          _.collectFirst{ case x: T => x }
+            .getOrElse(NoRD())
+        )
+      )
+    )
+    rdCfgs
+  }
+
+  def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = {
+    allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet))
+  }
+
+  def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = {
+    val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB())))
+    wbCfgs
+  }
+
+  /**
+    * Get size of read ports of int regfile
+    *
+    * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]]
+    */
+  def getIntRfReadSize = {
+    this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size)
+  }
+
+  /**
+    * Get size of write ports of vf regfile
+    *
+    * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]]
+    */
+  def getIntRfWriteSize = {
+    this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size)
+  }
+
+  /**
+    * Get size of read ports of int regfile
+    *
+    * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]]
+    */
+  def getVfRfReadSize = {
+    this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size)
+  }
+
+  /**
+    * Get size of write ports of vf regfile
+    *
+    * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]]
+    */
+  def getVfRfWriteSize = {
+    this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size)
+  }
+
+  def getRfReadSize(dataCfg: DataConfig) = {
+    this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size)
+  }
+
+  def getRfWriteSize(dataCfg: DataConfig) = {
+    this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size)
+  }
+
   def getExuIdx(name: String): Int = {
     val exuParams = allExuParams
     if (name != "WB") {
@@ -167,7 +240,42 @@ case class BackendParams(
   def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1)
   def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1)
 
+  private def isContinuous(portIndices: Seq[Int]): Boolean = {
+    val portIndicesSet = portIndices.toSet
+    portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1
+  }
+
   def configChecks = {
+    checkReadPortContinuous
+    checkWritePortContinuous
+    configCheck
+  }
+
+  def checkReadPortContinuous = {
+    pregParams.foreach { x =>
+      if (x.numRead.isEmpty) {
+        val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg)
+        require(isContinuous(portIndices),
+          s"The read ports of ${x.getClass.getSimpleName} should be continuous, " +
+            s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices")
+      }
+    }
+  }
+
+  def checkWritePortContinuous = {
+    pregParams.foreach { x =>
+      if (x.numWrite.isEmpty) {
+        val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg)
+        require(
+          isContinuous(portIndices),
+          s"The write ports of ${x.getClass.getSimpleName} should be continuous, " +
+            s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices"
+        )
+      }
+    }
+  }
+
+  def configCheck = {
     // check 0
     val maxPortSource = 2
 

src/main/scala/xiangshan/backend/Bundles.scala

@@ -4,17 +4,18 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util.BitPat.bitPatToUInt
 import chisel3.util._
+import utils.BundleUtils.makeValid
 import utils.OptionWrapper
 import xiangshan._
 import xiangshan.backend.datapath.DataConfig._
 import xiangshan.backend.datapath.DataSource
-import xiangshan.backend.datapath.WbConfig.WbConfig
+import xiangshan.backend.datapath.WbConfig.PregWB
 import xiangshan.backend.decode.{ImmUnion, XDecode}
 import xiangshan.backend.exu.ExeUnitParams
 import xiangshan.backend.fu.FuType
 import xiangshan.backend.fu.fpu.Bundles.Frm
-import xiangshan.backend.fu.vector.Bundles.{Category, Nf, VConfig, VLmul, VSew, VType, Vl, Vxrm}
-import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType, StatusArrayDeqRespBundle}
+import xiangshan.backend.fu.vector.Bundles._
+import xiangshan.backend.issue.{IssueBlockParams, IssueQueueJumpBundle, SchedulerType, StatusArrayDeqRespBundle}
 import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig}
 import xiangshan.backend.rob.RobPtr
 import xiangshan.frontend._
@@ -324,9 +325,7 @@ object Bundles {
   // DynInst --[IssueQueue]--> DataPath
   class IssueQueueIssueBundle(
     iqParams: IssueBlockParams,
-    exuParams: ExeUnitParams,
-    addrWidth: Int,
-    vaddrBits: Int
+    val exuParams: ExeUnitParams,
   )(implicit
     p: Parameters
   ) extends Bundle {
@@ -334,7 +333,7 @@ object Bundles {
 
     val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec(
       rfReadDataCfgSet.map((set: Set[DataConfig]) =>
-        MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, addrWidth)).toSeq)
+        MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq)
       )
     ))
 
@@ -350,6 +349,24 @@ object Bundles {
     def getVfWbBusyBundle = common.getVfWen.toSeq
     def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt)
     def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf)
+
+    def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = {
+      getIntRfReadBundle.zip(srcType).map {
+        case (rfRd: RfReadPortWithConfig, t: UInt) =>
+          makeValid(issueValid && SrcType.isXp(t), rfRd)
+      }
+    }
+
+    def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = {
+      getVfRfReadBundle.zip(srcType).map {
+        case (rfRd: RfReadPortWithConfig, t: UInt) =>
+          makeValid(issueValid && SrcType.isVfp(t), rfRd)
+      }
+    }
+
+    def getIntRfWriteValidBundle(issueValid: Bool) = {
+
+    }
   }
 
   class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle {
@@ -512,11 +529,11 @@ object Bundles {
   }
 
   // ExuOutput + DynInst --> WriteBackBundle
-  class WriteBackBundle(val params: WbConfig)(implicit p: Parameters) extends Bundle with BundleSource {
+  class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource {
     val rfWen = Bool()
     val fpWen = Bool()
     val vecWen = Bool()
-    val pdest = UInt(params.pregIdxWidth.W)
+    val pdest = UInt(params.pregIdxWidth(backendParams).W)
     val data = UInt(params.dataWidth.W)
     val robIdx = new RobPtr()(p)
     val flushPipe = Bool()
@@ -548,7 +565,7 @@ object Bundles {
     }
 
     def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = {
-      val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth)))
+      val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth)))
       rfWrite.wen := this.rfWen && fire
       rfWrite.addr := this.pdest
       rfWrite.data := this.data
@@ -559,7 +576,7 @@ object Bundles {
     }
 
     def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = {
-      val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth)))
+      val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth)))
       rfWrite.wen := (this.fpWen || this.vecWen) && fire
       rfWrite.addr := this.pdest
       rfWrite.data := this.data

src/main/scala/xiangshan/backend/datapath/DataPath.scala

 package xiangshan.backend.datapath
 
 import chipsalliance.rocketchip.config.Parameters
-import chisel3.{Data, _}
+import chisel3._
 import chisel3.util._
 import difftest.{DifftestArchFpRegState, DifftestArchIntRegState, DifftestArchVecRegState}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import utility._
+import utils.SeqUtils._
 import xiangshan._
 import xiangshan.backend.BackendParams
+import xiangshan.backend.Bundles._
 import xiangshan.backend.datapath.DataConfig._
 import xiangshan.backend.datapath.RdConfig._
 import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler}
-import xiangshan.backend.Bundles._
 import xiangshan.backend.regfile._
-import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB}
-
-class WbBusyArbiterIO(inPortSize: Int, outPortSize: Int)(implicit p: Parameters) extends XSBundle {
-  val in = Vec(inPortSize, Flipped(DecoupledIO(new Bundle{}))) // TODO: remote the bool
-  val flush = Flipped(ValidIO(new Redirect))
-}
-
-class WbBusyArbiter(isInt: Boolean)(implicit p: Parameters) extends XSModule {
-  val allExuParams = backendParams.allExuParams
-
-  val portConfigs = allExuParams.flatMap(_.wbPortConfigs).filter{
-    wbPortConfig =>
-      if(isInt){
-        wbPortConfig.isInstanceOf[IntWB]
-      }
-      else{
-        wbPortConfig.isInstanceOf[VfWB]
-      }
-  }
-
-  val numRfWrite = if (isInt) backendParams.numIntWb else backendParams.numVfWb
-
-  val io = IO(new WbBusyArbiterIO(portConfigs.size, numRfWrite))
-  // inGroup[port -> Bundle]
-  val inGroup = io.in.zip(portConfigs).groupBy{ case(port, config) => config.port}
-  // sort by priority
-  val inGroupSorted = inGroup.map{
-    case(key, value) => (key -> value.sortBy{ case(port, config) => config.asInstanceOf[PregWB].priority})
-  }
-
-  private val arbiters = Seq.tabulate(numRfWrite) { x => {
-    if (inGroupSorted.contains(x)) {
-      Some(Module(new Arbiter( new Bundle{} ,n = inGroupSorted(x).length)))
-    } else {
-      None
-    }
-  }}
-
-  arbiters.zipWithIndex.foreach { case (arb, i) =>
-    if (arb.nonEmpty) {
-      arb.get.io.in.zip(inGroupSorted(i).map(_._1)).foreach { case (arbIn, addrIn) =>
-        arbIn <> addrIn
-      }
-    }
-  }
-
-  arbiters.foreach(_.foreach(_.io.out.ready := true.B))
-}
-
-class RFArbiterBundle(addrWidth: Int)(implicit p: Parameters) extends XSBundle {
-  val addr = UInt(addrWidth.W)
-}
-
-class RFReadArbiterIO(inPortSize: Int, outPortSize: Int, pregWidth: Int)(implicit p: Parameters) extends XSBundle {
-  val in = Vec(inPortSize, Flipped(DecoupledIO(new RFArbiterBundle(pregWidth))))
-  val out = Vec(outPortSize, Valid(new RFArbiterBundle(pregWidth)))
-  val flush = Flipped(ValidIO(new Redirect))
-}
-
-class RFReadArbiter(isInt: Boolean)(implicit p: Parameters) extends XSModule {
-  val allExuParams = backendParams.allExuParams
-
-  val portConfigs: Seq[RdConfig] = allExuParams.map(_.rfrPortConfigs.flatten).flatten.filter{
-    rfrPortConfigs =>
-      if(isInt){
-        rfrPortConfigs.isInstanceOf[IntRD]
-      }
-      else{
-        rfrPortConfigs.isInstanceOf[VfRD]
-      }
-  }
-
-  private val moduleName = this.getClass.getName + (if (isInt) "Int" else "Vf")
-
-  println(s"[$moduleName] ports(${portConfigs.size})")
-  for (portCfg <- portConfigs) {
-    println(s"[$moduleName] port: ${portCfg.port}, priority: ${portCfg.priority}")
-  }
-
-  val pregParams = if(isInt) backendParams.intPregParams else backendParams.vfPregParams
-
-  val io = IO(new RFReadArbiterIO(portConfigs.size, backendParams.numRfRead, pregParams.addrWidth))
-  // inGroup[port -> Bundle]
-  val inGroup: Map[Int, IndexedSeq[(DecoupledIO[RFArbiterBundle], RdConfig)]] = io.in.zip(portConfigs).groupBy{ case(port, config) => config.port}
-  // sort by priority
-  val inGroupSorted: Map[Int, IndexedSeq[(DecoupledIO[RFArbiterBundle], RdConfig)]] = inGroup.map{
-    case(key, value) => (key -> value.sortBy{ case(port, config) => config.priority})
-  }
-
-  private val arbiters: Seq[Option[Arbiter[RFArbiterBundle]]] = Seq.tabulate(backendParams.numRfRead) { x => {
-    if (inGroupSorted.contains(x)) {
-      Some(Module(new Arbiter(new RFArbiterBundle(pregParams.addrWidth), inGroupSorted(x).length)))
-    } else {
-      None
-    }
-  }}
-
-  arbiters.zipWithIndex.foreach { case (arb, i) =>
-    if (arb.nonEmpty) {
-      arb.get.io.in.zip(inGroupSorted(i).map(_._1)).foreach { case (arbIn, addrIn) =>
-        arbIn <> addrIn
-      }
-    }
-  }
-
-  io.out.zip(arbiters).foreach { case (addrOut, arb) =>
-    if (arb.nonEmpty) {
-      val arbOut = arb.get.io.out
-      arbOut.ready := true.B
-      addrOut.valid := arbOut.valid
-      addrOut.bits := arbOut.bits
-    } else {
-      addrOut := 0.U.asTypeOf(addrOut)
-    }
-  }
-}
 
 class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule {
   private implicit val dpParams: BackendParams = params
   lazy val module = new DataPathImp(this)
+
+  println(s"[DataPath] Preg Params: ")
+  println(s"[DataPath]   Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ")
+  println(s"[DataPath]   Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ")
 }
 
 class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams)
@@ -163,114 +52,71 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
 
   private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten
 
-  private val intWbBusyArbiter = Module(new WbBusyArbiter(true))
-  private val vfWbBusyArbiter = Module(new WbBusyArbiter(false))
-  private val intRFReadArbiter = Module(new RFReadArbiter(true))
-  private val vfRFReadArbiter = Module(new RFReadArbiter(false))
+  private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams))
+  private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams))
+  private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams))
+  private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams))
 
   private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool()))))
   private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool()))))
 
-  private val issuePortsIn = fromIQ.flatten
-  private val intNotBlocksW = fromIQ.map { case iq => Wire(Vec(iq.size, Bool())) }
-  private val intNotBlocksSeqW = intNotBlocksW.flatten
-  private val vfNotBlocksW = fromIQ.map { case iq => Wire(Vec(iq.size, Bool())) }
-  private val vfNotBlocksSeqW = vfNotBlocksW.flatten
-  private val intBlocks = fromIQ.map{ case iq => Wire(Vec(iq.size, Bool())) }
-  private val intBlocksSeq = intBlocks.flatten
-  private val vfBlocks = fromIQ.map { case iq => Wire(Vec(iq.size, Bool())) }
-  private val vfBlocksSeq = vfBlocks.flatten
-  private val intWbConflictReads = io.wbConfictRead.flatten.flatten.map(_.intConflict)
-  private val vfWbConflictReads = io.wbConfictRead.flatten.flatten.map(_.vfConflict)
-
-  val intWbBusyInSize = issuePortsIn.map(issuePortIn => issuePortIn.bits.getIntWbBusyBundle.size).scan(0)(_ + _)
-  val intReadPortInSize: IndexedSeq[Int] = issuePortsIn.map(issuePortIn => issuePortIn.bits.getIntRfReadBundle.size).scan(0)(_ + _)
-  issuePortsIn.zipWithIndex.foreach{
-    case (issuePortIn, idx) =>
-      val wbBusyIn: Seq[Bool] = issuePortIn.bits.getIntWbBusyBundle
-      val lw = intWbBusyInSize(idx)
-      val rw = intWbBusyInSize(idx + 1)
-      val arbiterInW = intWbBusyArbiter.io.in.slice(lw, rw)
-      arbiterInW.zip(wbBusyIn).foreach {
-        case (sink, source) =>
-          sink.bits := DontCare
-          sink.valid := issuePortIn.valid && source
-      }
-       val notBlockFlag = if (rw > lw) {
-        val arbiterRes = arbiterInW.zip(wbBusyIn).map {
-          case (sink, source) => sink.ready
-        }.reduce(_ & _)
-        if (intWbConflictReads(idx).isDefined) {
-          Mux(intWbConflictReads(idx).get, arbiterRes, true.B)
-        } else arbiterRes
-      } else true.B
-      intNotBlocksSeqW(idx) := notBlockFlag
-      val readPortIn = issuePortIn.bits.getIntRfReadBundle
-      val l = intReadPortInSize(idx)
-      val r = intReadPortInSize(idx + 1)
-      val arbiterIn = intRFReadArbiter.io.in.slice(l, r)
-      arbiterIn.zip(readPortIn).foreach{
-        case(sink, source) =>
-          sink.bits.addr := source.addr
-          sink.valid := issuePortIn.valid && SrcType.isXp(source.srcType)
-      }
-      if(r > l){
-        intBlocksSeq(idx) := !arbiterIn.zip(readPortIn).map {
-          case (sink, source) => Mux(SrcType.isXp(source.srcType), sink.ready, true.B)
-        }.reduce(_ & _)
-      }
-      else{
-        intBlocksSeq(idx) := false.B
+  // port -> win
+  private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready))))
+  private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready))))
+  private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready)))
+  private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready)))
+
+  private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR))
+  private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR))
+
+  private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getIntRfReadValidBundle(xx.valid)))
+
+  intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) =>
+    arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) =>
+      val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData())
+      for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) {
+        if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) {
+          arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid
+          arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr
+        } else {
+          arbInSeq(srcIdx).valid := false.B
+          arbInSeq(srcIdx).bits.addr := 0.U
+        }
       }
+    }
   }
-  intWbBusyArbiter.io.flush := io.flush
-  intRFReadArbiter.io.flush := io.flush
-
-  val vfWbBusyInSize = issuePortsIn.map(issuePortIn => issuePortIn.bits.getVfWbBusyBundle.size).scan(0)(_ + _)
-  val vfReadPortInSize: IndexedSeq[Int] = issuePortsIn.map(issuePortIn => issuePortIn.bits.getVfRfReadBundle.size).scan(0)(_ + _)
-  println(s"vfReadPortInSize: $vfReadPortInSize")
-
-  issuePortsIn.zipWithIndex.foreach {
-    case (issuePortIn, idx) =>
-      val wbBusyIn = issuePortIn.bits.getVfWbBusyBundle
-      val lw = vfWbBusyInSize(idx)
-      val rw = vfWbBusyInSize(idx + 1)
-      val arbiterInW = vfWbBusyArbiter.io.in.slice(lw, rw)
-      arbiterInW.zip(wbBusyIn).foreach {
-        case (sink, source) =>
-          sink.bits := DontCare
-          sink.valid := issuePortIn.valid && source
-      }
-      val notBlockFlag = if (rw > lw){
-        val arbiterRes = arbiterInW.zip(wbBusyIn).map {
-          case (sink, source) => sink.ready
-        }.reduce(_ & _)
-        if(vfWbConflictReads(idx).isDefined) {
-          Mux(vfWbConflictReads(idx).get, arbiterRes, true.B)
-        }else arbiterRes
-      }else true.B
-      vfNotBlocksSeqW(idx) := notBlockFlag
-
-      val readPortIn = issuePortIn.bits.getVfRfReadBundle
-      val l = vfReadPortInSize(idx)
-      val r = vfReadPortInSize(idx + 1)
-      val arbiterIn = vfRFReadArbiter.io.in.slice(l, r)
-      arbiterIn.zip(readPortIn).foreach {
-        case (sink, source) =>
-          sink.bits.addr := source.addr
-          sink.valid := issuePortIn.valid && SrcType.isVfp(source.srcType)
-      }
-      if (r > l) {
-        vfBlocksSeq(idx) := !arbiterIn.zip(readPortIn).map {
-          case (sink, source) => Mux(SrcType.isVfp(source.srcType), sink.ready, true.B)
-        }.reduce(_ & _)
-      }
-      else {
-        vfBlocksSeq(idx) := false.B
+
+  private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getVfRfReadValidBundle(xx.valid)))
+
+  vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) =>
+    arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) =>
+      val srcIndices: Seq[Int] = VfRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted
+      for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) {
+        if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) {
+          arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid
+          arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr
+        } else {
+          arbInSeq(srcIdx).valid := false.B
+          arbInSeq(srcIdx).bits.addr := 0.U
+        }
       }
+    }
+  }
+
+  private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)))
+  private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.getVfWen.getOrElse(false.B)))
+
+  intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) =>
+    arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) =>
+      arbIn.valid := inRFWriteReq
+    }
+  }
+
+  vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) =>
+    arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) =>
+      arbIn.valid := inRFWriteReq
+    }
   }
-  vfWbBusyArbiter.io.flush := io.flush
-  vfRFReadArbiter.io.flush := io.flush
 
   private val intSchdParams = params.schdParams(IntScheduler())
   private val vfSchdParams = params.schdParams(VfScheduler())
@@ -286,15 +132,15 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
 
   private val schdParams = params.allSchdParams
 
-  private val intRfRaddr = Wire(Vec(params.numRfRead, UInt(intSchdParams.pregIdxWidth.W)))
-  private val intRfRdata = Wire(Vec(params.numRfRead, UInt(intSchdParams.rfDataWidth.W)))
+  private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W)))
+  private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W)))
   private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool()))
   private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W)))
   private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W)))
 
   private val vfRfSplitNum = VLEN / XLEN
-  private val vfRfRaddr = Wire(Vec(params.numRfRead, UInt(vfSchdParams.pregIdxWidth.W)))
-  private val vfRfRdata = Wire(Vec(params.numRfRead, UInt(vfSchdParams.rfDataWidth.W)))
+  private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W)))
+  private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W)))
   private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool())))
   private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W)))
   private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W)))
@@ -349,13 +195,24 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
   intRfWdata := io.fromIntWb.map(_.data)
   intRfWen := io.fromIntWb.map(_.wen)
 
-  intRFReadArbiter.io.out.map(_.bits.addr).zip(intRfRaddr).foreach{ case(source, sink) => sink := source }
+  for (portIdx <- intRfRaddr.indices) {
+    if (intRFReadArbiter.io.out.isDefinedAt(portIdx))
+      intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr
+    else
+      intRfRaddr(portIdx) := 0.U
+  }
 
   vfRfWaddr := io.fromVfWb.map(_.addr)
   vfRfWdata := io.fromVfWb.map(_.data)
   vfRfWen.foreach(_.zip(io.fromVfWb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write
 
-  vfRFReadArbiter.io.out.map(_.bits.addr).zip(vfRfRaddr).foreach{ case(source, sink) => sink := source }
+  for (portIdx <- vfRfRaddr.indices) {
+    if (vfRFReadArbiter.io.out.isDefinedAt(portIdx))
+      vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr
+    else
+      vfRfRaddr(portIdx) := 0.U
+  }
+
   vfRfRaddr(VCONFIG_PORT) := io.vconfigReadPort.addr
   io.vconfigReadPort.data := vfRfRdata(VCONFIG_PORT)
 
@@ -418,23 +275,22 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
       val s1_data = s1_toExuData(i)(j)
       val s1_addrOH = s1_addrOHs(i)(j)
       val s0 = fromIQ(i)(j) // s0
-      val block = (intBlocks(i)(j) || !intNotBlocksW(i)(j)) || (vfBlocks(i)(j) || !vfNotBlocksW(i)(j))
+      val notBlock = intRdNotBlock(i)(j) && intWbNotBlock(i)(j) && vfRdNotBlock(i)(j) && vfWbNotBlock(i)(j)
       val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush)))
       val s1_cancel = og1FailedVec2(i)(j)
-      when (s0.fire && !s1_flush && !block && !s1_cancel) {
+      when (s0.fire && !s1_flush && notBlock && !s1_cancel) {
         s1_valid := s0.valid
         s1_data.fromIssueBundle(s0.bits) // no src data here
         s1_addrOH := s0.bits.addrOH
       }.otherwise {
         s1_valid := false.B
       }
-//      dontTouch(block)
-      s0.ready := (s1_ready || !s1_valid) && !block
+      s0.ready := (s1_ready || !s1_valid) && notBlock
       // IQ(s0) --[Ctrl]--> s1Reg ---------- end
 
       // IQ(s0) --[Data]--> s1Reg ---------- begin
       // imm extract
-      when (s0.fire && !s1_flush && !block) {
+      when (s0.fire && !s1_flush && notBlock) {
         if (s1_data.params.immType.nonEmpty && s1_data.src.size > 1) {
           // rs1 is always int reg, rs2 may be imm
           when(SrcType.isImm(s0.bits.srcType(1))) {

src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala

+package xiangshan.backend.datapath
+
+import chipsalliance.rocketchip.config.Parameters
+import chisel3._
+import chisel3.util.{Arbiter, DecoupledIO, Valid}
+import utils.SeqUtils.{MixedVec3, Seq3}
+import utils.{OptionWrapper, SeqUtils}
+import xiangshan.backend.BackendParams
+import xiangshan.backend.datapath.DataConfig.{IntData, VecData}
+import xiangshan.backend.datapath.RdConfig.{IntRD, NoRD, RdConfig, VfRD}
+import xiangshan.backend.regfile.PregParams
+
+case class RFRdArbParams(
+  inRdCfgs: Seq3[RdConfig],
+  pregParams: PregParams,
+) {
+  require(inRdCfgs.nonEmpty)
+
+  def genInputBundle: MixedVec3[DecoupledIO[RFArbiterBundle]] = {
+    val pregWidth = pregParams.addrWidth
+    SeqUtils.mapToMixedVec3(this.inRdCfgs, (rd: RdConfig) => DecoupledIO(new RFArbiterBundle(rd, pregWidth)))
+  }
+
+  def portMax: Int = inRdCfgs.flatten.flatten.map(_.port).max
+}
+
+class RFArbiterBundle(var rdCfg: Option[RdConfig], pregWidth: Int) extends Bundle {
+  val addr = UInt(pregWidth.W)
+
+  def this(rdCfg_ : RdConfig, pregWidth_ : Int) = this(Some(rdCfg_), pregWidth_)
+
+  def this(pregWidth_ :Int) = this(None, pregWidth_)
+}
+
+class RFReadArbiterIO(params: RFRdArbParams)(implicit p: Parameters) extends Bundle {
+  private val pregWidth = params.pregParams.addrWidth
+  val in = Flipped(params.genInputBundle)
+  val out = Vec(params.portMax + 1, Valid(new RFArbiterBundle(pregWidth)))
+}
+
+abstract class RFReadArbiterBase(val params: RFRdArbParams)(implicit p: Parameters) extends Module {
+  protected def portRange: Range
+
+  val io = IO(new RFReadArbiterIO(params))
+  dontTouch(io)
+
+  protected val pregParams = params.pregParams
+  protected val pregWidth = pregParams.addrWidth
+
+  protected val inGroup: Map[Int, Seq[DecoupledIO[RFArbiterBundle]]] = io.in
+    .flatten.flatten
+    .groupBy(_.bits.rdCfg.get.port)
+    .map(x => (x._1, x._2.sortBy(_.bits.rdCfg.get.priority)))
+
+  protected val arbiters: Seq[Option[Arbiter[RFArbiterBundle]]] = portRange.map { portIdx =>
+    OptionWrapper(
+      inGroup.isDefinedAt(portIdx),
+      Module(new Arbiter(
+        new RFArbiterBundle(pregWidth),
+        inGroup(portIdx).size
+      ))
+    )
+  }
+
+  arbiters.zipWithIndex.foreach { case (arbiter, portIdx) =>
+    if (arbiter.nonEmpty) {
+      arbiter.get.io.in.zip(inGroup(portIdx)).foreach { case (arbiterIn, ioIn) =>
+        arbiterIn <> ioIn
+      }
+    }
+  }
+
+  // connection of NoRD
+  io.in.map(_.map(_.map(x =>
+    if (x.bits.rdCfg.get.isInstanceOf[NoRD]) {
+      x.ready := true.B
+    }
+  )))
+
+  for (portIdx <- io.out.indices) {
+    val arb = arbiters(portIdx)
+    val out = io.out(portIdx)
+    if (arb.nonEmpty) {
+      val arbOut = arb.get.io.out
+      arbOut.ready := true.B
+      out.valid := arbOut.valid
+      out.bits := arbOut.bits
+    } else {
+      out := 0.U.asTypeOf(out)
+    }
+  }
+}
+
+class IntRFReadArbiter(
+  backendParams: BackendParams
+)(implicit
+  p: Parameters
+) extends RFReadArbiterBase(RFRdArbParams(backendParams.getRdCfgs[IntRD], backendParams.intPregParams)) {
+  override protected def portRange: Range = 0 to backendParams.getRdPortIndices(IntData()).max
+}
+
+class VfRFReadArbiter(
+  backendParams: BackendParams
+)(implicit
+  p: Parameters
+) extends RFReadArbiterBase(RFRdArbParams(backendParams.getRdCfgs[VfRD], backendParams.vfPregParams)) {
+  override protected def portRange: Range = 0 to backendParams.getRdPortIndices(VecData()).max
+}
+

src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala

+package xiangshan.backend.datapath
+
+import chipsalliance.rocketchip.config.Parameters
+import chisel3._
+import chisel3.util._
+import utils.OptionWrapper
+import utils.SeqUtils.MixedVec2
+import xiangshan.backend.BackendParams
+import xiangshan.backend.datapath.DataConfig.{IntData, VecData}
+import xiangshan.backend.datapath.WbConfig.{NoWB, PregWB}
+import xiangshan.backend.regfile.PregParams
+
+case class RFWBCollideCheckerParams (
+  inWbCfgs: Seq[Seq[Set[PregWB]]],
+  pregParams: PregParams,
+) {
+  def genInputBundle: MixedVec2[DecoupledIO[RFWBCollideCheckerBundle]] = {
+    val pregWidth = pregParams.addrWidth
+    utils.SeqUtils.mapToMixedVec2(this.filteredCfgs, (wb: PregWB) => DecoupledIO(new RFWBCollideCheckerBundle(wb, pregWidth)))
+  }
+
+  def filteredCfgs: Seq[Seq[PregWB]] = inWbCfgs.map(_.map(x =>
+    if (x.map(_.dataCfg).contains(pregParams.dataCfg))
+      x.find(x => x.dataCfg == pregParams.dataCfg).get
+    else
+      NoWB()
+  ))
+
+  def portMax = filteredCfgs.flatten.map(_.port).max
+}
+
+class RFWBCollideCheckerBundle(var wbCfg: Option[PregWB], pregWidth: Int) extends Bundle {
+
+  def this(wbCfg_ : PregWB, pregWidth_ : Int) = this(Some(wbCfg_), pregWidth_)
+
+  def this(pregWidth_ : Int) = this(None, pregWidth_)
+}
+
+class RFWBCollideCheckerIO(val params: RFWBCollideCheckerParams)(implicit p: Parameters) extends Bundle {
+  private val pregWidth = params.pregParams.addrWidth
+  val in: MixedVec2[DecoupledIO[RFWBCollideCheckerBundle]] = Flipped(params.genInputBundle)
+  val out = Vec(params.portMax + 1, Valid(new RFWBCollideCheckerBundle(pregWidth)))
+}
+
+abstract class RFWBCollideCheckerBase(params: RFWBCollideCheckerParams)(implicit p: Parameters) extends Module {
+  protected def portRange: Range
+
+  val io = IO(new RFWBCollideCheckerIO(params))
+  dontTouch(io)
+
+  protected val pregParams = params.pregParams
+  protected val pregWidth = pregParams.addrWidth
+
+  protected val inGroup = io.in
+    .flatten
+    .groupBy(_.bits.wbCfg.get.port)
+    .map(x => (x._1, x._2.sortBy(_.bits.wbCfg.get.priority)))
+
+  protected val arbiters: Seq[Option[Arbiter[RFWBCollideCheckerBundle]]] = portRange.map { portIdx =>
+    OptionWrapper(
+      inGroup.isDefinedAt(portIdx),
+      Module(new Arbiter(
+        new RFWBCollideCheckerBundle(pregWidth),
+        inGroup(portIdx).size
+      ))
+    )
+  }
+
+  // connection of IntWB or VfWB
+  arbiters.zipWithIndex.foreach { case (arb, portIdx) =>
+    if (arb.nonEmpty) {
+      arb.get.io.in.zip(inGroup(portIdx)).foreach { case (arbiterIn, ioIn) =>
+        arbiterIn <> ioIn
+      }
+    }
+  }
+
+  // connection of NoWB
+  io.in.map(_.map(x =>
+    if (x.bits.wbCfg.get.isInstanceOf[NoWB]) {
+      x.ready := true.B
+    }
+  ))
+
+  io.out.zip(arbiters).foreach { case (out, arb) =>
+    if (arb.nonEmpty) {
+      val arbOut = arb.get.io.out
+      arbOut.ready := true.B
+      out.valid := arbOut.valid
+      out.bits := arbOut.bits
+    } else {
+      out := 0.U.asTypeOf(out)
+    }
+  }
+}
+
+class IntRFWBCollideChecker(
+  backendParams: BackendParams
+)(implicit
+  p:Parameters
+) extends RFWBCollideCheckerBase(RFWBCollideCheckerParams(backendParams.getAllWbCfgs, backendParams.intPregParams)) {
+  override protected def portRange: Range = 0 to backendParams.getWbPortIndices(IntData()).max
+}
+
+class VfRFWBCollideChecker(
+  backendParams: BackendParams
+)(implicit
+  p:Parameters
+) extends RFWBCollideCheckerBase(RFWBCollideCheckerParams(backendParams.getAllWbCfgs, backendParams.vfPregParams)) {
+  override protected def portRange: Range = 0 to backendParams.getWbPortIndices(VecData()).max
+}

src/main/scala/xiangshan/backend/datapath/RdConfig.scala

 package xiangshan.backend.datapath
 
+import xiangshan.backend.datapath.DataConfig.{DataConfig, IntData, NoData, VecData}
+
 object RdConfig {
   sealed abstract class RdConfig() {
     val port: Int
     val priority: Int
+
+    def getDataConfig: DataConfig
+  }
+
+  case class IntRD(port: Int = -1, priority: Int = Int.MaxValue) extends RdConfig() {
+    override def getDataConfig = IntData()
   }
 
-  case class IntRD(port: Int = -1, priority: Int = Int.MaxValue) extends RdConfig()
+  case class VfRD(port: Int = -1, priority: Int = Int.MaxValue) extends RdConfig() {
+    override def getDataConfig = VecData()
+  }
+
+  case class NoRD() extends RdConfig() {
+    override val port: Int = -1
 
-  case class VfRD(port: Int = -1, priority: Int = Int.MaxValue) extends RdConfig()
+    override val priority: Int = Int.MaxValue
+
+    override def getDataConfig: DataConfig = NoData()
+  }
 }
 

src/main/scala/xiangshan/backend/datapath/WbArbiter.scala

@@ -7,6 +7,7 @@ import difftest.{DifftestFpWriteback, DifftestIntWriteback}
 import utils.XSError
 import xiangshan.backend.BackendParams
 import xiangshan.backend.Bundles.{ExuOutput, WriteBackBundle}
+import xiangshan.backend.datapath.DataConfig.{IntData, VecData}
 import xiangshan.backend.regfile.RfWritePortWithConfig
 import xiangshan.{Redirect, XSBundle, XSModule}
 
@@ -24,7 +25,7 @@ class WbArbiterDispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T =
 
   private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits))
 
-  XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ")
+  XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ")
 
   io.out.zipWithIndex.foreach { case (out, i) =>
     out.valid := acceptVec(i) && io.in.valid
@@ -49,7 +50,7 @@ class WbArbiter(params: WbArbiterParams)(implicit p: Parameters) extends XSModul
 
   private val arbiters: Seq[Option[Arbiter[WriteBackBundle]]] = Seq.tabulate(params.numOut) { x => {
     if (inGroup.contains(x)) {
-      Some(Module(new Arbiter(new WriteBackBundle(inGroup.values.head.head.bits.params), inGroup(x).length)))
+      Some(Module(new Arbiter(new WriteBackBundle(inGroup.values.head.head.bits.params, backendParams), inGroup(x).length)))
     } else {
       None
     }
@@ -92,10 +93,10 @@ class WbDataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBu
 
   val fromMemExu: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = Flipped(params.memSchdParams.get.genExuOutputDecoupledBundle)
 
-  val toIntPreg = Flipped(MixedVec(Vec(params.intPregParams.numWrite,
+  val toIntPreg = Flipped(MixedVec(Vec(params.numPregWb(IntData()),
     new RfWritePortWithConfig(params.intPregParams.dataCfg, params.intPregParams.addrWidth))))
 
-  val toVfPreg = Flipped(MixedVec(Vec(params.vfPregParams.numWrite,
+  val toVfPreg = Flipped(MixedVec(Vec(params.numPregWb(VecData()),
     new RfWritePortWithConfig(params.vfPregParams.dataCfg, params.vfPregParams.addrWidth))))
 
   val toCtrlBlock = new Bundle {

src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala

@@ -3,26 +3,34 @@ package xiangshan.backend.datapath
 import chipsalliance.rocketchip.config.Parameters
 import chisel3.Output
 import chisel3.util.{DecoupledIO, MixedVec, ValidIO, log2Up}
+import xiangshan.backend.BackendParams
 import xiangshan.backend.Bundles.WriteBackBundle
 import xiangshan.backend.datapath.DataConfig.{FpData, IntData, VecData}
-import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB, WbConfig}
+import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB}
 import xiangshan.backend.regfile.PregParams
 
 case class WbArbiterParams(
-  wbCfgs    : Seq[WbConfig],
+  wbCfgs    : Seq[PregWB],
   pregParams: PregParams,
+  backendParams: BackendParams,
 ) {
 
   def numIn = wbCfgs.length
 
-  def numOut = pregParams.numWrite
+  def numOut = wbCfgs.head match {
+    case _: WbConfig.IntWB => pregParams.numWrite.getOrElse(backendParams.getWbPortIndices(IntData()).size)
+    case _: WbConfig.VfWB => pregParams.numWrite.getOrElse(backendParams.getWbPortIndices(VecData()).size)
+    case x =>
+      assert(assertion = false, s"the WbConfig in WbArbiterParams should be either IntWB or VfWB, found ${x.getClass}")
+      0
+  }
 
   def dataWidth = pregParams.dataCfg.dataWidth
 
   def addrWidth = log2Up(pregParams.numEntries)
 
   def genInput(implicit p: Parameters) = {
-    MixedVec(wbCfgs.map(x => DecoupledIO(new WriteBackBundle(x))))
+    MixedVec(wbCfgs.map(x => DecoupledIO(new WriteBackBundle(x, backendParams))))
   }
 
   def genOutput(implicit p: Parameters): MixedVec[ValidIO[WriteBackBundle]] = {
@@ -34,7 +42,8 @@ case class WbArbiterParams(
             case FpData() => VfWB(port = x)
             case VecData() => VfWB(port = x)
             case _ => ???
-          }
+          },
+          backendParams
         )
         )
     }

src/main/scala/xiangshan/backend/datapath/WbConfig.scala

 package xiangshan.backend.datapath
 
 import chisel3.util.log2Up
+import xiangshan.backend.BackendParams
 import xiangshan.backend.datapath.DataConfig._
 
 object WbConfig {
   sealed abstract class WbConfig() {
     val port: Int
     def dataCfg: DataConfig
-    def numPreg: Int = 0
     def dataWidth: Int = dataCfg.dataWidth
 
-    def pregIdxWidth = log2Up(numPreg)
-
     def writeInt = dataCfg == IntData()
     def writeFp = dataCfg == FpData()
     def writeVec = dataCfg == VecData()
 
     override def toString: String = {
-      var res = dataCfg match {
-        case IntData() => "I"
-        case FpData() => "F"
-        case VecData() => "V"
-        case _ => "?"
+      var res = this match {
+        case _: IntWB => "INT"
+        case _: VfWB => "VF"
+        case _: NoWB => "NO"
+        case _ => "??"
       }
       res += s"($port)"
       res
@@ -32,31 +30,40 @@ object WbConfig {
 
   sealed abstract class PregWB extends ExuWB {
     val priority: Int
+
+    def numPreg(backendParams: BackendParams): Int
+
+    def pregIdxWidth(backendParams: BackendParams) = log2Up(numPreg(backendParams))
   }
 
   case class IntWB(
     port    : Int = -1,
     priority: Int = Int.MaxValue,
   ) extends PregWB {
+
     def dataCfg: DataConfig = IntData()
-    override def numPreg: Int = 160
+
+    def numPreg(backendParams: BackendParams): Int = backendParams.getPregParams(IntData()).numEntries
   }
 
   case class VfWB(
     port    : Int = -1,
     priority: Int = Int.MaxValue,
   ) extends PregWB {
+
     def dataCfg: DataConfig = VecData()
-    override def numPreg: Int = 160
+
+    def numPreg(backendParams: BackendParams): Int = backendParams.getPregParams(VecData()).numEntries
   }
 
-  case class VecWB(
-    port: Int = -1,
+  case class NoWB(
+    port    : Int = -1,
     priority: Int = Int.MaxValue,
   ) extends PregWB {
-    def dataCfg: DataConfig = VecData()
 
-    override def numPreg: Int = 160
+    override def dataCfg: DataConfig = NoData()
+
+    override def numPreg(backendParams: BackendParams): Int = 0
   }
 
   case class CtrlWB(
@@ -65,12 +72,5 @@ object WbConfig {
     val priority: Int = Int.MaxValue
     override def dataCfg: DataConfig = NoData()
   }
-
-  // Todo: use it
-  sealed trait WBSource
-  case class WBFromInt() extends WBSource
-  case class WBFromMem() extends WBSource
-  case class WBFromVec() extends WBSource
-  case class WBFromFp()  extends WBSource
 }
 

src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala

@@ -3,20 +3,19 @@ package xiangshan.backend.exu
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
-import xiangshan.HasXSParameter
 import xiangshan.backend.BackendParams
-import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput, WriteBackBundle}
+import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput}
 import xiangshan.backend.datapath.DataConfig.DataConfig
 import xiangshan.backend.datapath.RdConfig._
-import xiangshan.backend.datapath.WakeUpConfig
-import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB, WbConfig}
+import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB}
+import xiangshan.backend.datapath.{DataConfig, WakeUpConfig}
 import xiangshan.backend.fu.{FuConfig, FuType}
 import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler}
 
 case class ExeUnitParams(
   name          : String,
   fuConfigs     : Seq[FuConfig],
-  wbPortConfigs : Seq[WbConfig],
+  wbPortConfigs : Seq[PregWB],
   rfrPortConfigs: Seq[Seq[RdConfig]],
 )(
   implicit
@@ -58,7 +57,14 @@ case class ExeUnitParams(
   val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _)
   val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _)
   val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _)
-  val wbPregIdxWidth = if (wbPortConfigs.nonEmpty) wbPortConfigs.map(_.pregIdxWidth).max else 0
+
+  def rdPregIdxWidth: Int = {
+    this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _)
+  }
+
+  def wbPregIdxWidth: Int = {
+    this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _)
+  }
 
   val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf)
   val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf)
@@ -195,6 +201,20 @@ case class ExeUnitParams(
     }
   }
 
+  /**
+    * Get the [[DataConfig]] that this exu need to read
+    */
+  def pregRdDataCfgSet: Set[DataConfig] = {
+    this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet
+  }
+
+  /**
+    * Get the [[DataConfig]] that this exu need to write
+    */
+  def pregWbDataCfgSet: Set[DataConfig] = {
+    this.wbPortConfigs.map(_.dataCfg).toSet
+  }
+
   def getRfReadDataCfgSet: Seq[Set[DataConfig]] = {
     val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet)
     val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]()))
@@ -204,6 +224,34 @@ case class ExeUnitParams(
     exuSrcsCfgSet
   }
 
+  /**
+    * Get the [[DataConfig]] mapped indices of source data of exu
+    *
+    * @example
+    * {{{
+    *   fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData())
+    *   getRfReadSrcIdx(VecData()) = Seq(0, 1, 2)
+    *   getRfReadSrcIdx(MaskSrcData()) = Seq(3)
+    *   getRfReadSrcIdx(VConfigData()) = Seq(4)
+    * }}}
+    * @return Map[DataConfig -> Seq[indices]]
+    */
+  def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = {
+    val dataCfgs = DataConfig.RegSrcDataSet
+    val rfRdDataCfgSet = this.getRfReadDataCfgSet
+    dataCfgs.toSeq.map { cfg =>
+      (
+        cfg,
+        rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) =>
+          if (set.contains(cfg))
+            Option(srcIdx)
+          else
+            None
+        }.filter(_.nonEmpty).map(_.get)
+      )
+    }.toMap
+  }
+
   def genExuModule(implicit p: Parameters): ExeUnit = {
     new ExeUnit(this)
   }

src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala

@@ -6,17 +6,16 @@ import chisel3.util._
 import utils.SeqUtils
 import xiangshan.backend.BackendParams
 import xiangshan.backend.Bundles._
-import xiangshan.backend.datapath.WbConfig.WbConfig
+import xiangshan.backend.datapath.DataConfig.DataConfig
+import xiangshan.backend.datapath.WbConfig.PregWB
 import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource}
-import xiangshan.backend.exu.ExeUnitParams
+import xiangshan.backend.exu.{ExeUnit, ExeUnitParams}
 import xiangshan.backend.fu.{FuConfig, FuType}
 
 case class IssueBlockParams(
   // top down
   exuBlockParams     : Seq[ExeUnitParams],
   numEntries         : Int,
-  pregBits           : Int,
-  numWakeupFromWB    : Int,
   numEnq             : Int,
   numDeqOutside      : Int = 0,
   numWakeupFromOthers: Int = 0,
@@ -151,6 +150,30 @@ case class IssueBlockParams(
 
   def numRedirect: Int = exuBlockParams.count(_.hasRedirect)
 
+  /**
+    * Get the regfile type that this issue queue need to read
+    */
+  def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _)
+
+  /**
+    * Get the regfile type that this issue queue need to read
+    */
+  def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _)
+
+  /**
+    * Get the max width of psrc
+    */
+  def rdPregIdxWidth = {
+    this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _)
+  }
+
+  /**
+    * Get the max width of pdest
+    */
+  def wbPregIdxWidth = {
+    this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _)
+  }
+
   def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs)
 
   /** Get exu source wake up
@@ -185,12 +208,22 @@ case class IssueBlockParams(
 
   def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers
 
+  def numWakeupFromWB = {
+    val pregSet = this.pregReadSet
+    pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum
+  }
+
   def hasIQWakeUp: Boolean = numWakeupFromIQ > 0
 
   def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct
 
   // cfgs(exuIdx)(set of exu's wb)
-  def getWbCfgs: Seq[Set[WbConfig]] = {
+
+  /**
+    * Get [[PregWB]] of this IssueBlock
+    * @return set of [[PregWB]] of [[ExeUnit]]
+    */
+  def getWbCfgs: Seq[Set[PregWB]] = {
     exuBlockParams.map(exu => exu.wbPortConfigs.toSet)
   }
 
@@ -219,7 +252,7 @@ case class IssueBlockParams(
   }
 
   def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = {
-    MixedVec(exuBlockParams.map(x => DecoupledIO(new IssueQueueIssueBundle(this, x, pregBits, vaddrBits))))
+    MixedVec(exuBlockParams.map(x => DecoupledIO(new IssueQueueIssueBundle(this, x))))
   }
 
   def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = {

src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala

@@ -6,12 +6,11 @@ import utils.SeqUtils
 import xiangshan.backend.BackendParams
 import xiangshan.backend.Bundles._
 import xiangshan.backend.datapath.WakeUpSource
-import xiangshan.backend.datapath.WbConfig.WbConfig
+import xiangshan.backend.datapath.WbConfig.PregWB
 
 case class SchdBlockParams(
   issueBlockParams: Seq[IssueBlockParams],
   numPregs        : Int,
-  numRfReadWrite  : Option[(Int, Int)],
   numDeqOutside   : Int,
   schdType        : SchedulerType,
   rfDataWidth     : Int,
@@ -104,9 +103,6 @@ case class SchdBlockParams(
 
   def numVfRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(x => x.numFpSrc + x.numVecSrc).sum).sum
 
-  // Todo: 14R8W
-  def numIntRfRead: Int = numIntRfReadByExu
-
   def bindBackendParam(param: BackendParams): Unit = {
     backendParam = param
   }
@@ -162,7 +158,7 @@ case class SchdBlockParams(
   }
 
   // cfgs(issueIdx)(exuIdx)(set of exu's wb)
-  def getWbCfgs: Seq[Seq[Set[WbConfig]]] = {
+  def getWbCfgs: Seq[Seq[Set[PregWB]]] = {
     this.issueBlockParams.map(_.getWbCfgs)
   }
 }

src/main/scala/xiangshan/backend/issue/Scheduler.scala

@@ -6,7 +6,8 @@ import chisel3.util._
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import xiangshan._
 import xiangshan.backend.Bundles._
-import xiangshan.backend.datapath.DataConfig.VAddrData
+import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData}
+import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB}
 import xiangshan.backend.regfile.RfWritePortWithConfig
 import xiangshan.backend.rename.BusyTable
 import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr}
@@ -19,8 +20,8 @@ case class VfScheduler() extends SchedulerType
 case class NoScheduler() extends SchedulerType
 
 class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
-  val numIntStateWrite = backendParams.numIntWb
-  val numVfStateWrite = backendParams.numVfWb
+  val numIntStateWrite = backendParams.numPregWb(IntData())
+  val numVfStateWrite = backendParams.numPregWb(VecData())
 
   val dispatch2Iq = LazyModule(new Dispatch2Iq(params))
   val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName)))
@@ -59,9 +60,9 @@ class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends Bun
     val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq))
     val uops =  Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst)))
   }
-  val intWriteBack = MixedVec(Vec(backendParams.intPregParams.numWrite,
+  val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()),
     new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth)))
-  val vfWriteBack = MixedVec(Vec(backendParams.vfPregParams.numWrite,
+  val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()),
     new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth)))
   val toDataPath: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))
   val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle))
@@ -114,8 +115,6 @@ abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockPa
   private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] =
     io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap
   private val schdType = params.schdType
-  private val (numRfRead, numRfWrite) = params.numRfReadWrite.getOrElse((0, 0))
-  private val numPregs = params.numPregs
 
   // Modules
   val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module
@@ -123,12 +122,12 @@ abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockPa
 
   // BusyTable Modules
   val intBusyTable = schdType match {
-    case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite)))
+    case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs)))
     case _ => None
   }
 
   val vfBusyTable = schdType match {
-    case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite)))
+    case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs)))
     case _ => None
   }
 

src/main/scala/xiangshan/backend/issue/StatusArray.scala

@@ -24,7 +24,7 @@ class StatusEntryMemPart(implicit p:Parameters, params: IssueBlockParams) extend
 class StatusEntry(implicit p:Parameters, params: IssueBlockParams) extends Bundle {
   val srcState = Vec(params.numRegSrc, SrcState())
 
-  val psrc = Vec(params.numRegSrc, UInt(params.pregBits.W))
+  val psrc = Vec(params.numRegSrc, UInt(params.rdPregIdxWidth.W))
   val srcType = Vec(params.numRegSrc, SrcType())
   val robIdx = new RobPtr
   val issued = Bool()           // for predict issue

src/main/scala/xiangshan/backend/regfile/PregParams.scala

@@ -5,8 +5,8 @@ import xiangshan.backend.datapath.DataConfig._
 
 abstract class PregParams {
   val numEntries: Int
-  val numRead: Int
-  val numWrite: Int
+  val numRead: Option[Int]
+  val numWrite: Option[Int]
   val dataCfg: DataConfig
 
   def addrWidth = log2Up(numEntries)
@@ -14,17 +14,26 @@ abstract class PregParams {
 
 case class IntPregParams(
   numEntries: Int,
-  numRead   : Int,
-  numWrite  : Int,
+  numRead   : Option[Int],
+  numWrite  : Option[Int],
 ) extends PregParams {
+
   override val dataCfg: DataConfig = IntData()
 }
 
 case class VfPregParams(
   numEntries: Int,
-  numRead   : Int,
-  numWrite  : Int,
+  numRead   : Option[Int],
+  numWrite  : Option[Int],
 ) extends PregParams {
+
   override val dataCfg: DataConfig = VecData()
 }
 
+case class NoPregParams() extends PregParams {
+  val numEntries: Int = 0
+  val numRead   : Option[Int] = None
+  val numWrite  : Option[Int] = None
+
+  override val dataCfg: DataConfig = NoData()
+}

src/main/scala/xiangshan/backend/regfile/Regfile.scala

@@ -21,6 +21,7 @@ import chisel3._
 import chisel3.util._
 import xiangshan._
 import xiangshan.backend.datapath.DataConfig.{DataConfig, FpData, FpRegSrcDataSet, IntData, IntRegSrcDataSet, VecData, VecRegSrcDataSet, VfRegSrcDataSet}
+import xiangshan.backend.exu.ExeUnitParams
 
 class RfReadPort(dataWidth: Int, addrWidth: Int) extends Bundle {
   val addr = Input(UInt(addrWidth.W))

src/main/scala/xiangshan/backend/rename/BusyTable.scala

@@ -28,7 +28,7 @@ class BusyTableReadIO(implicit p: Parameters) extends XSBundle {
   val resp = Output(Bool())
 }
 
-class BusyTable(numReadPorts: Int, numWritePorts: Int)(implicit p: Parameters) extends XSModule with HasPerfEvents {
+class BusyTable(numReadPorts: Int, numWritePorts: Int, numPhyPregs: Int)(implicit p: Parameters) extends XSModule with HasPerfEvents {
   val io = IO(new Bundle() {
     // set preg state to busy
     val allocPregs = Vec(RenameWidth, Flipped(ValidIO(UInt(PhyRegIdxWidth.W))))
@@ -38,7 +38,7 @@ class BusyTable(numReadPorts: Int, numWritePorts: Int)(implicit p: Parameters) e
     val read = Vec(numReadPorts, new BusyTableReadIO)
   })
 
-  val table = RegInit(0.U(NRPhyRegs.W))
+  val table = RegInit(0.U(numPhyPregs.W))
 
   def reqVecToMask(rVec: Vec[Valid[UInt]]): UInt = {
     ParallelOR(rVec.map(v => Mux(v.valid, UIntToOH(v.bits), 0.U)))
@@ -62,17 +62,17 @@ class BusyTable(numReadPorts: Int, numWritePorts: Int)(implicit p: Parameters) e
   XSDebug(p"tableNext: ${Binary(tableAfterAlloc)}\n")
   XSDebug(p"allocMask: ${Binary(allocMask)}\n")
   XSDebug(p"wbMask   : ${Binary(wbMask)}\n")
-  for (i <- 0 until NRPhyRegs) {
+  for (i <- 0 until numPhyPregs) {
     XSDebug(table(i), "%d is busy\n", i.U)
   }
 
   XSPerfAccumulate("busy_count", PopCount(table))
 
   val perfEvents = Seq(
-    ("std_freelist_1_4_valid", busyCount < (NRPhyRegs / 4).U                                      ),
-    ("std_freelist_2_4_valid", busyCount > (NRPhyRegs / 4).U && busyCount <= (NRPhyRegs / 2).U    ),
-    ("std_freelist_3_4_valid", busyCount > (NRPhyRegs / 2).U && busyCount <= (NRPhyRegs * 3 / 4).U),
-    ("std_freelist_4_4_valid", busyCount > (NRPhyRegs * 3 / 4).U                                  )
+    ("std_freelist_1_4_valid", busyCount < (numPhyPregs / 4).U                                      ),
+    ("std_freelist_2_4_valid", busyCount > (numPhyPregs / 4).U && busyCount <= (numPhyPregs / 2).U    ),
+    ("std_freelist_3_4_valid", busyCount > (numPhyPregs / 2).U && busyCount <= (numPhyPregs * 3 / 4).U),
+    ("std_freelist_4_4_valid", busyCount > (numPhyPregs * 3 / 4).U                                  )
   )
   generatePerfEvent()
 }

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -66,9 +66,9 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
   })
 
   // create free list and rat
-  val intFreeList = Module(new MEFreeList(NRPhyRegs))
-  val intRefCounter = Module(new RefCounter(NRPhyRegs))
-  val fpFreeList = Module(new StdFreeList(NRPhyRegs - FpLogicRegs - VecLogicRegs))
+  val intFreeList = Module(new MEFreeList(IntPhyRegs))
+  val intRefCounter = Module(new RefCounter(IntPhyRegs))
+  val fpFreeList = Module(new StdFreeList(VfPhyRegs - FpLogicRegs - VecLogicRegs))
 
   intRefCounter.io.commit        <> io.robCommits
   intRefCounter.io.redirect      := io.redirect.valid

src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala

@@ -102,7 +102,7 @@ class MEFreeList(size: Int)(implicit p: Parameters) extends BaseFreeList(size) w
     case 0 => true.B
     case _ => !debugArchRAT.take(i).map(_ === debugArchRAT(i)).reduce(_ || _)
   })
-  XSError(distanceBetween(tailPtr, debugArchHeadPtr) +& PopCount(debugUniqPR) =/= NRPhyRegs.U, "Integer physical register should be in either arch RAT or arch free list\n")
+  XSError(distanceBetween(tailPtr, debugArchHeadPtr) +& PopCount(debugUniqPR) =/= size.U, "Integer physical register should be in either arch RAT or arch free list\n")
 
   val perfEvents = Seq(
     ("me_freelist_1_4_valid", freeRegCntReg <  (size / 4).U                                     ),

src/test/scala/xiangshan/DecodeTest.scala

@@ -29,8 +29,8 @@ object DecodeMain extends App with HasRocketChipStageUtils {
         // Example of how to change params
         intPreg = IntPregParams(
           numEntries = 64,
-          numRead = 14,
-          numWrite = 8,
+          numRead = Some(14),
+          numWrite = Some(8),
         ),
       )
     })

src/test/scala/xiangshan/XSTester.scala

@@ -21,8 +21,8 @@ abstract class XSTester extends AnyFlatSpec with ChiselScalatestTester with Matc
       // Example of how to change params
       intPreg = IntPregParams(
         numEntries = 64,
-        numRead = 14,
-        numWrite = 8,
+        numRead = Some(14),
+        numWrite = Some(8),
       ),
     )
   })