vector: fix mask for vipu and vppu

src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala

@@ -105,17 +105,17 @@ class VIPU(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg)
   // modules
   private val decoder = Module(new VIAluDecoder)
   private val vialu   = Module(new VIAlu)
-  private val mgu     = Module(new Mgu(dataWidth))
   
   /**
-  * [[decoder]]'s in connection
-  */
+    * [[decoder]]'s in connection
+    */
   decoder.io.in.fuOpType := fuOpType
   decoder.io.in.sew      := vsew(1,0)
 
+
   /**
-  * [[vialu]]'s in connection
-  */
+    * [[vialu]]'s in connection
+    */
   vialu.io match {
     case subIO =>
       subIO.in.valid            := io.in.valid
@@ -136,27 +136,8 @@ class VIPU(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg)
                                            ((!needClearVs1) && (!needShiftVs1)) -> vs1))
       subIO.in.bits.vs2         := vs2
       subIO.in.bits.old_vd      := oldVd
-      subIO.in.bits.mask        := outSrcMask
+      subIO.in.bits.mask        := srcMask
   }
 
-  /**
-  * [[mgu]]'s in connection
-  */
-  private val outVd = vialu.io.out.bits.vd
-  private val outWiden = fuOpType === VipuType.vwredsumu_vs || fuOpType === VipuType.vwredsum_vs
-  private val outEew = Mux(outWiden, outVecCtrl.vsew + 1.U, outVecCtrl.vsew)
-
-  mgu.io.in.vd           := outVd
-  mgu.io.in.oldVd        := outOldVd
-  mgu.io.in.mask         := outSrcMask
-  mgu.io.in.info.ta      := outVecCtrl.vta
-  mgu.io.in.info.ma      := outVecCtrl.vma
-  mgu.io.in.info.vl      := outVl
-  mgu.io.in.info.vstart  := outVecCtrl.vstart
-  mgu.io.in.info.eew     := outEew
-  mgu.io.in.info.vdIdx   := outVecCtrl.vuopIdx
-  mgu.io.in.info.narrow  := 0.B
-  mgu.io.in.info.dstMask := 0.B
-
-  io.out.bits.res.data := mgu.io.out.vd
+  io.out.bits.res.data := vialu.io.out.bits.vd
 }

src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala

@@ -35,7 +35,7 @@ class VPPU(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg)
   private val dataWidthOfDataModule = 64
   private val numVecModule = dataWidth / dataWidthOfDataModule
   private val vppuNeedClearMask = (VpermType.vcompress === io.in.bits.ctrl.fuOpType) && (vuopIdx(log2Up(MaxUopSize)-1,1) === 0.U)
-  private val mask = Mux(vppuNeedClearMask, 0.U, outSrcMask)
+  private val mask = Mux(vppuNeedClearMask, 0.U, srcMask)
 
   // io alias
   private val opcode  = VpermType.getOpcode(fuOpType)