Backend, Fusion: support instruction fusion case 'lui + addiw'

src/main/scala/xiangshan/backend/decode/FusionDecoder.scala

@@ -486,6 +486,25 @@ class FusedLui32(pair: Seq[Valid[UInt]])(implicit p: Parameters)
   XSDebug(isValid, p"[fusedLui32] ${Hexadecimal(imm.get)} instr0=${Hexadecimal(instr(0))} instr1=${Hexadecimal(instr(1))}\n")
 }
 
+// Case: get 32 bits imm (in word format)
+// Source: `lui r1, 0xffffa`` + `addiw r1, r1, 1`
+// Target: `lui32 r1, 0xffffa001` (customized internal opcode)
+class FusedLui32w(pair: Seq[Valid[UInt]])(implicit p: Parameters)
+  extends BaseFusionCase(pair) {
+  def inst1Cond = instr(0) === Instructions.LUI
+  def inst2Cond = instr(1) === Instructions.ADDIW
+
+  def isValid: Bool = inst1Cond && inst2Cond && withSameDest && destToRs1
+
+  override def fuOpType: Option[UInt => UInt] = Some((_: UInt) => ALUOpType.lui32addw)
+  override def selImm: Option[UInt] = Some(SelImm.IMM_LUI32)
+  override def imm: Option[UInt] = Some(Cat(instr(0)(31, 12), instr(1)(31, 20)))
+
+  def fusionName: String = "lui_addiw"
+
+  XSDebug(isValid, p"[fusedLui32w] ${Hexadecimal(imm.get)} instr0=${Hexadecimal(instr(0))} instr1=${Hexadecimal(instr(1))}\n")
+}
+
 class FusionDecodeInfo extends Bundle {
   val rs2FromRs1 = Output(Bool())
   val rs2FromRs2 = Output(Bool())
@@ -567,7 +586,8 @@ class FusionDecoder(implicit p: Parameters) extends XSModule {
       new FusedAddwsexth(pair),
       new FusedLogiclsb(pair),
       new FusedLogicZexth(pair),
-      new FusedLui32(pair)
+      new FusedLui32(pair),
+      new FusedLui32w(pair)
     )
     val fire = io.in(i).valid && io.inReady(i)
     val instrPairValid = RegEnable(VecInit(pair.map(_.valid)).asUInt.andR, false.B, io.inReady(i))

src/main/scala/xiangshan/backend/fu/Alu.scala

@@ -158,7 +158,7 @@ class WordResultSelect(implicit p: Parameters) extends XSModule {
     val wordRes = Output(UInt(XLEN.W))
   })
 
-  val addsubRes = Mux(!io.func(2) && io.func(1), io.subw, io.addw)
+  val addsubRes = Mux(!io.func(2) && io.func(1) && !io.func(0), io.subw, io.addw)
   val shiftRes = Mux(io.func(2), Mux(io.func(0), io.rorw, io.rolw),
                   Mux(io.func(1), io.sraw, Mux(io.func(0), io.srlw, io.sllw)))
   val wordRes = Mux(io.func(3), shiftRes, addsubRes)
@@ -219,7 +219,7 @@ class AluDataModule(implicit p: Parameters) extends XSModule {
 
   // addw
   val addModule = Module(new AddModule)
-  addModule.io.srcw := Mux(!func(2) && func(0), ZeroExt(src1(0), XLEN), src1(31, 0))
+  addModule.io.srcw := Mux(!func(2) && func(0), Mux(func(1), SignExt(src2(11, 0), XLEN), ZeroExt(src1(0), XLEN)), src1(31, 0))
   val addwResultAll = VecInit(Seq(
     ZeroExt(addModule.io.addw(0), XLEN),
     ZeroExt(addModule.io.addw(7, 0), XLEN),
@@ -358,4 +358,7 @@ class AluDataModule(implicit p: Parameters) extends XSModule {
 
   XSDebug(func === ALUOpType.lui32add, p"[alu] func lui32: src1=${Hexadecimal(src1)} src2=${Hexadecimal(src2)} alures=${Hexadecimal(aluRes)}\n")
   XSDebug(func === ALUOpType.lui32add, p"[alu] func lui32: add_src1=${Hexadecimal(addModule.io.src(0))} add_src2=${Hexadecimal(addModule.io.src(1))} addres=${Hexadecimal(add)}\n")
+
+  XSDebug(func === ALUOpType.lui32addw, p"[alu] func lui32w: src1=${Hexadecimal(src1)} src2=${Hexadecimal(src2)} alures=${Hexadecimal(aluRes)}\n")
+  XSDebug(func === ALUOpType.lui32addw, p"[alu] func lui32w: add_src1=${Hexadecimal(addModule.io.srcw)} add_src2=${Hexadecimal(addModule.io.src(1)(31,0))} addres=${Hexadecimal(addw)}\n")
 }

src/main/scala/xiangshan/package.scala

@@ -188,6 +188,7 @@ package object xiangshan {
     def addw       = "b001_0000".U // addw:      SEXT((src1 + src2)[31:0])
     def oddaddw    = "b001_0001".U // oddaddw:   SEXT((src1[0] + src2)[31:0])
     def subw       = "b001_0010".U // subw:      SEXT((src1 - src2)[31:0])
+    def lui32addw  = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64)
 
     def addwbit    = "b001_0100".U // addwbit:   (src1 + src2)[0]
     def addwbyte   = "b001_0101".U // addwbyte:  (src1 + src2)[7:0]