Backend, Fusion: enable fused_lui_load

src/main/scala/xiangshan/backend/datapath/DataPath.scala

@@ -10,6 +10,7 @@ import utils.SeqUtils._
 import xiangshan._
 import xiangshan.backend.BackendParams
 import xiangshan.backend.Bundles._
+import xiangshan.backend.decode.ImmUnion
 import xiangshan.backend.datapath.DataConfig._
 import xiangshan.backend.datapath.RdConfig._
 import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler}
@@ -316,6 +317,11 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
               s1_data.params.immType.map(_.litValue)
             )
           }
+        } else if (s1_data.params.hasLoadFu) {
+          // dirty code for fused_lui_load
+          when(SrcType.isImm(s0.bits.srcType(0))) {
+            s1_data.src(0) := ImmUnion.U.toImm32(s0.bits.common.imm(s0.bits.common.imm.getWidth - 1, ImmUnion.I.len))
+          }
         }
       }
       // IQ(s0) --[Data]--> s1Reg ---------- end
@@ -396,6 +402,10 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
         when(SrcType.isImm(s1_srcType(i)(j)(0))) {
           sinkData.src(0) := s1_toExuData(i)(j).src(0)
         }
+      } else if (sinkData.params.hasLoadFu) {
+        when(SrcType.isImm(s1_srcType(i)(j)(0))) {
+          sinkData.src(0) := s1_toExuData(i)(j).src(0)
+        }
       }
       // s1Reg --[Data]--> exu(s1) ---------- end
     }

src/main/scala/xiangshan/backend/decode/DecodeUnit.scala

@@ -613,7 +613,7 @@ case class Imm_LUI_LOAD() {
   def getLuiImm(uop: DynInst): UInt = {
     val loadImmLen = Imm_I().len
     val imm_u = Cat(uop.psrc(1), uop.psrc(0), uop.imm(ImmUnion.maxLen - 1, loadImmLen))
-    Imm_U().do_toImm32(imm_u)
+    Cat(Imm_U().toImm32(imm_u)(31, loadImmLen), uop.imm(loadImmLen - 1, 0))
   }
 }
 

src/main/scala/xiangshan/backend/issue/IssueQueue.scala

@@ -8,7 +8,7 @@ import utility.HasCircularQueuePtrHelper
 import utils._
 import xiangshan._
 import xiangshan.backend.Bundles._
-import xiangshan.backend.decode.ImmUnion
+import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
 import xiangshan.backend.datapath.DataConfig._
 import xiangshan.backend.datapath.DataSource
 import xiangshan.backend.fu.{FuConfig, FuType}
@@ -467,6 +467,11 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
       val lui_imm = Cat(deqEntryVec(i).bits.payload.lsrc(1), deqEntryVec(i).bits.payload.lsrc(0), deqEntryVec(i).bits.imm(ImmUnion.maxLen - 1, 0))
       deq.bits.common.imm := ImmUnion.LUI32.toImm32(lui_imm)
     }
+
+    // dirty code for fused_lui_load
+    when (SrcType.isImm(deqEntryVec(i).bits.payload.srcType(0)) && deqEntryVec(i).bits.payload.fuType === FuType.ldu.U) {
+      deq.bits.common.imm := Imm_LUI_LOAD().getLuiImm(deqEntryVec(i).bits.payload)
+    }
   }
   io.deqDelay.zip(io.fromCancelNetwork).foreach{ case(deqDly, deq) =>
     NewPipelineConnect(

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -361,7 +361,7 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
     val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc
     val this_is_load = io.in(i).bits.fuType === FuType.ldu.U
     val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0)
-    val fused_lui_load = last_is_lui && this_is_load && lui_to_load && false.B // Todo: enable it
+    val fused_lui_load = last_is_lui && this_is_load && lui_to_load
     when (fused_lui_load) {
       // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm}
       val lui_imm = io.in(i - 1).bits.imm(19, 0)