backend: refactor

* Prepare for merge master

src/main/scala/xiangshan/DbEntry.scala

@@ -3,7 +3,7 @@ package xiangshan
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util.log2Ceil
-import xiangshan.backend.rob.{DebugLsInfo, DebugMdpInfo}
+import xiangshan.backend.ctrlblock.{DebugLsInfo, DebugMdpInfo}
 import xiangshan.cache.DCacheBundle
 import xiangshan.backend.fu.FuType
 

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -19,22 +19,21 @@ package xiangshan.backend
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
+import coupledL2.PrefetchRecv
 import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp}
 import freechips.rocketchip.tile.HasFPUParameters
-import coupledL2.PrefetchRecv
-import utils._
 import utility._
 import utils._
 import xiangshan._
+import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput}
+import xiangshan.backend.ctrlblock.DebugLSIO
 import xiangshan.backend.exu.MemExeUnit
 import xiangshan.backend.fu._
-import xiangshan.backend.rob.{DebugLSIO, RobLsqIO}
+import xiangshan.backend.rob.RobLsqIO
 import xiangshan.cache._
 import xiangshan.cache.mmu.{TLBNonBlock, TlbReplace, VectorTlbPtwIO}
 import xiangshan.mem._
-import xiangshan.mem.mdp._
 import xiangshan.mem.prefetch.{BasePrefecher, SMSParams, SMSPrefetcher}
-import Bundles.{DynInst, MemExuInput, MemExuOutput}
 
 class Std(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) {
   io.in.ready := io.out.ready

src/main/scala/xiangshan/backend/ctrlblock/LsInfo.scala

+package xiangshan.backend.ctrlblock
+
+import chipsalliance.rocketchip.config.Parameters
+import chisel3._
+import chisel3.util._
+import xiangshan.XSBundle
+
+class DebugMdpInfo(implicit p: Parameters) extends XSBundle{
+  val ssid = UInt(SSIDWidth.W)
+  val waitAllStore = Bool()
+}
+
+class DebugLsInfo(implicit p: Parameters) extends XSBundle{
+  val s1 = new Bundle{
+    val isTlbFirstMiss = Bool() // in s1
+    val isBankConflict = Bool() // in s1
+    val isLoadToLoadForward = Bool()
+    val isReplayFast = Bool()
+  }
+  val s2 = new Bundle{
+    val isDcacheFirstMiss = Bool() // in s2 (predicted result is in s1 when using WPU, real result is in s2)
+    val isForwardFail = Bool() // in s2
+    val isReplaySlow = Bool()
+    val isLoadReplayTLBMiss = Bool()
+    val isLoadReplayCacheMiss = Bool()
+  }
+  val replayCnt = UInt(XLEN.W)
+
+  def s1SignalEnable(ena: DebugLsInfo) = {
+    when(ena.s1.isTlbFirstMiss) { s1.isTlbFirstMiss := true.B }
+    when(ena.s1.isBankConflict) { s1.isBankConflict := true.B }
+    when(ena.s1.isLoadToLoadForward) { s1.isLoadToLoadForward := true.B }
+    when(ena.s1.isReplayFast) {
+      s1.isReplayFast := true.B
+      replayCnt := replayCnt + 1.U
+    }
+  }
+
+  def s2SignalEnable(ena: DebugLsInfo) = {
+    when(ena.s2.isDcacheFirstMiss) { s2.isDcacheFirstMiss := true.B }
+    when(ena.s2.isForwardFail) { s2.isForwardFail := true.B }
+    when(ena.s2.isLoadReplayTLBMiss) { s2.isLoadReplayTLBMiss := true.B }
+    when(ena.s2.isLoadReplayCacheMiss) { s2.isLoadReplayCacheMiss := true.B }
+    when(ena.s2.isReplaySlow) {
+      s2.isReplaySlow := true.B
+      replayCnt := replayCnt + 1.U
+    }
+  }
+}
+
+object DebugLsInfo{
+  def init(implicit p: Parameters): DebugLsInfo = {
+    val lsInfo = Wire(new DebugLsInfo)
+    lsInfo.s1.isTlbFirstMiss := false.B
+    lsInfo.s1.isBankConflict := false.B
+    lsInfo.s1.isLoadToLoadForward := false.B
+    lsInfo.s1.isReplayFast := false.B
+    lsInfo.s2.isDcacheFirstMiss := false.B
+    lsInfo.s2.isForwardFail := false.B
+    lsInfo.s2.isReplaySlow := false.B
+    lsInfo.s2.isLoadReplayTLBMiss := false.B
+    lsInfo.s2.isLoadReplayCacheMiss := false.B
+    lsInfo.replayCnt := 0.U
+    lsInfo
+  }
+}
+
+class DebugLsInfoBundle(implicit p: Parameters) extends DebugLsInfo {
+  // unified processing at the end stage of load/store  ==> s2  ==> bug that will write error robIdx data
+  val s1_robIdx = UInt(log2Ceil(RobSize).W)
+  val s2_robIdx = UInt(log2Ceil(RobSize).W)
+}
+
+class DebugLSIO(implicit p: Parameters) extends XSBundle {
+  val debugLsInfo = Vec(backendParams.LduCnt + backendParams.StaCnt, Output(new DebugLsInfoBundle))
+}

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -31,76 +31,6 @@ import xiangshan.frontend.FtqPtr
 import xiangshan.mem.{LqPtr, SqPtr}
 import xiangshan.backend.Bundles.{DynInst, ExceptionInfo, ExuOutput}
 
-class DebugMdpInfo(implicit p: Parameters) extends XSBundle{
-  val ssid = UInt(SSIDWidth.W)
-  val waitAllStore = Bool()
-}
-
-class DebugLsInfo(implicit p: Parameters) extends XSBundle{
-  val s1 = new Bundle{
-    val isTlbFirstMiss = Bool() // in s1
-    val isBankConflict = Bool() // in s1
-    val isLoadToLoadForward = Bool()
-    val isReplayFast = Bool()
-  }
-  val s2 = new Bundle{
-    val isDcacheFirstMiss = Bool() // in s2 (predicted result is in s1 when using WPU, real result is in s2)
-    val isForwardFail = Bool() // in s2
-    val isReplaySlow = Bool()
-    val isLoadReplayTLBMiss = Bool()
-    val isLoadReplayCacheMiss = Bool()
-  }
-  val replayCnt = UInt(XLEN.W)
-
-  def s1SignalEnable(ena: DebugLsInfo) = {
-    when(ena.s1.isTlbFirstMiss) { s1.isTlbFirstMiss := true.B }
-    when(ena.s1.isBankConflict) { s1.isBankConflict := true.B }
-    when(ena.s1.isLoadToLoadForward) { s1.isLoadToLoadForward := true.B }
-    when(ena.s1.isReplayFast) {
-      s1.isReplayFast := true.B
-      replayCnt := replayCnt + 1.U
-    }
-  }
-
-  def s2SignalEnable(ena: DebugLsInfo) = {
-    when(ena.s2.isDcacheFirstMiss) { s2.isDcacheFirstMiss := true.B }
-    when(ena.s2.isForwardFail) { s2.isForwardFail := true.B }
-    when(ena.s2.isLoadReplayTLBMiss) { s2.isLoadReplayTLBMiss := true.B }
-    when(ena.s2.isLoadReplayCacheMiss) { s2.isLoadReplayCacheMiss := true.B }
-    when(ena.s2.isReplaySlow) {
-      s2.isReplaySlow := true.B
-      replayCnt := replayCnt + 1.U
-    }
-  }
-}
-
-object DebugLsInfo{
-  def init(implicit p: Parameters): DebugLsInfo = {
-    val lsInfo = Wire(new DebugLsInfo)
-    lsInfo.s1.isTlbFirstMiss := false.B
-    lsInfo.s1.isBankConflict := false.B
-    lsInfo.s1.isLoadToLoadForward := false.B
-    lsInfo.s1.isReplayFast := false.B
-    lsInfo.s2.isDcacheFirstMiss := false.B
-    lsInfo.s2.isForwardFail := false.B
-    lsInfo.s2.isReplaySlow := false.B
-    lsInfo.s2.isLoadReplayTLBMiss := false.B
-    lsInfo.s2.isLoadReplayCacheMiss := false.B
-    lsInfo.replayCnt := 0.U
-    lsInfo
-  }
-}
-
-class DebugLsInfoBundle(implicit p: Parameters) extends DebugLsInfo {
-  // unified processing at the end stage of load/store  ==> s2  ==> bug that will write error robIdx data
-  val s1_robIdx = UInt(log2Ceil(RobSize).W)
-  val s2_robIdx = UInt(log2Ceil(RobSize).W)
-}
-
-class DebugLSIO(implicit p: Parameters) extends XSBundle {
-  val debugLsInfo = Vec(backendParams.LduCnt + backendParams.StaCnt, Output(new DebugLsInfoBundle))
-}
-
 class RobPtr(entries: Int) extends CircularQueuePtr[RobPtr](
   entries
 ) with HasCircularQueuePtrHelper {

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -25,8 +25,9 @@ import xiangshan.ExceptionNO._
 import xiangshan._
 import xiangshan.backend.fu.PMPRespBundle
 import xiangshan.backend.fu.FuConfig.LduCfg
-import xiangshan.backend.rob.{DebugLsInfoBundle, RobPtr}
+import xiangshan.backend.rob.RobPtr
 import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput}
+import xiangshan.backend.ctrlblock.DebugLsInfoBundle
 import xiangshan.cache._
 import xiangshan.cache.dcache.ReplayCarry
 import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp}

src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

@@ -25,9 +25,9 @@ import xiangshan.ExceptionNO._
 import xiangshan._
 import xiangshan.backend.fu.PMPRespBundle
 import xiangshan.backend.fu.FuConfig.StaCfg
-import xiangshan.backend.rob.DebugLsInfoBundle
 import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp}
 import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput}
+import xiangshan.backend.ctrlblock.DebugLsInfoBundle
 
 // Store Pipeline Stage 0
 // Generate addr, use addr to query DCache and DTLB