Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OpenXiangShan
XiangShan
提交
ddef3fab
X
XiangShan
项目概览
OpenXiangShan
/
XiangShan
9 个月 前同步成功
通知
1183
Star
3914
Fork
526
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
X
XiangShan
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
未验证
提交
ddef3fab
编写于
9月 05, 2023
作者:
H
Haojin Tang
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
wakeupQueue: flush pending wakeup requests when canceling
上级
b4361ce3
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
52 addition
and
35 deletion
+52
-35
src/main/scala/utils/PipeWithFlush.scala
src/main/scala/utils/PipeWithFlush.scala
+13
-19
src/main/scala/xiangshan/backend/issue/IssueQueue.scala
src/main/scala/xiangshan/backend/issue/IssueQueue.scala
+25
-8
src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala
...main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala
+12
-6
src/test/scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala
.../scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala
+1
-1
src/test/scala/xiangshan/utils/GenPipeWithFlush.scala
src/test/scala/xiangshan/utils/GenPipeWithFlush.scala
+1
-1
未找到文件。
src/main/scala/utils/PipeWithFlush.scala
浏览文件 @
ddef3fab
...
...
@@ -2,9 +2,7 @@ package utils
import
chisel3._
import
chisel3.util._
import
top.
{
ArgParser
,
BaseConfig
,
DefaultConfig
}
import
xiangshan._
import
xiangshan.backend.Bundles.DynInst
/** Pipeline module generator parameterized by data type and latency.
*
...
...
@@ -16,34 +14,30 @@ import xiangshan.backend.Bundles.DynInst
* @tparam TFlush Type of [[io.flush]]
*/
class
PipeWithFlush
[
T
<:
Data
,
TFlush
<:
Data
]
(
val
gen
:
T
,
val
flushGen
:
TFlush
,
val
latency
:
Int
,
flushFunc
:
(
T
,
TFlush
)
=>
Bool
gen
:
T
,
flushGen
:
TFlush
,
latency
:
Int
,
flushFunc
:
(
T
,
TFlush
,
Int
)
=>
Bool
)
extends
Module
{
require
(
latency
>=
0
,
"Pipe latency must be greater than or equal to zero!"
)
class
PipeIO
extends
Bundle
{
val
flush
=
Flipped
(
flushGen
)
val
flush
=
Input
(
flushGen
)
val
enq
=
Input
(
Valid
(
gen
))
val
deq
=
Output
(
Valid
(
gen
))
}
val
io
=
IO
(
new
PipeIO
)
if
(
latency
==
0
)
{
io
.
deq
:=
io
.
enq
}
else
{
val
valids
:
Seq
[
Bool
]
=
io
.
enq
.
valid
+:
Seq
.
fill
(
latency
)(
RegInit
(
false
.
B
))
val
bits
:
Seq
[
T
]
=
io
.
enq
.
bits
+:
Seq
.
fill
(
latency
)(
Reg
(
gen
))
val
valids
:
Seq
[
Bool
]
=
io
.
enq
.
valid
+:
Seq
.
fill
(
latency
)(
RegInit
(
false
.
B
))
val
bits
:
Seq
[
T
]
=
io
.
enq
.
bits
+:
Seq
.
fill
(
latency
)(
Reg
(
gen
))
for
(
i
<-
0
until
latency
)
{
valids
(
i
+
1
)
:=
valids
(
i
)
&&
!
flushFunc
(
bits
(
i
),
io
.
flush
)
when
(
valids
(
i
))
{
bits
(
i
+
1
)
:=
bits
(
i
)
}
for
(
i
<-
0
until
latency
)
{
valids
(
i
+
1
)
:=
valids
(
i
)
&&
!
flushFunc
(
bits
(
i
),
io
.
flush
,
i
)
when
(
valids
(
i
))
{
bits
(
i
+
1
)
:=
bits
(
i
)
}
io
.
deq
.
valid
:=
valids
.
last
io
.
deq
.
bits
:=
bits
.
last
}
io
.
deq
.
valid
:=
valids
.
last
io
.
deq
.
bits
:=
bits
.
last
}
src/main/scala/xiangshan/backend/issue/IssueQueue.scala
浏览文件 @
ddef3fab
...
...
@@ -92,13 +92,24 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
val
vfWbBusyTableWrite
=
params
.
exuBlockParams
.
map
{
case
x
=>
OptionWrapper
(
x
.
vfLatencyCertain
,
Module
(
new
FuBusyTableWrite
(
x
.
vfFuLatencyMap
)))
}
val
vfWbBusyTableRead
=
params
.
exuBlockParams
.
map
{
case
x
=>
OptionWrapper
(
x
.
vfLatencyCertain
,
Module
(
new
FuBusyTableRead
(
x
.
vfFuLatencyMap
)))
}
val
wakeUpQueues
:
Seq
[
Option
[
MultiWakeupQueue
[
ExuInput
,
ValidIO
[
Redirect
]]]]
=
params
.
exuBlockParams
.
map
{
x
=>
OptionWrapper
(
x
.
isIQWakeUpSource
,
Module
(
new
MultiWakeupQueue
(
new
ExuInput
(
x
),
ValidIO
(
new
Redirect
)
,
x
.
fuLatancySet
,
(
exuInput
:
ExuInput
,
flush
:
ValidIO
[
Redirect
])
=>
exuInput
.
robIdx
.
needFlush
(
flush
)
)
class
WakeupQueueFlush
extends
Bundle
{
val
redirect
=
ValidIO
(
new
Redirect
)
val
og0Fail
=
Output
(
Bool
())
val
og1Fail
=
Output
(
Bool
())
}
private
def
flushFunc
(
exuInput
:
ExuInput
,
flush
:
WakeupQueueFlush
,
stage
:
Int
)
:
Bool
=
{
val
redirectFlush
=
exuInput
.
robIdx
.
needFlush
(
flush
.
redirect
)
val
ogFailFlush
=
stage
match
{
case
1
=>
flush
.
og0Fail
case
2
=>
flush
.
og1Fail
case
_
=>
false
.
B
}
redirectFlush
||
ogFailFlush
}
val
wakeUpQueues
:
Seq
[
Option
[
MultiWakeupQueue
[
ExuInput
,
WakeupQueueFlush
]]]
=
params
.
exuBlockParams
.
map
{
x
=>
OptionWrapper
(
x
.
isIQWakeUpSource
,
Module
(
new
MultiWakeupQueue
(
new
ExuInput
(
x
),
new
WakeupQueueFlush
,
x
.
fuLatancySet
,
flushFunc
)
))}
val
intWbBusyTableIn
=
io
.
wbBusyTableRead
.
map
(
_
.
intWbBusyTable
)
...
...
@@ -414,7 +425,11 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
wakeUpQueues
.
zipWithIndex
.
foreach
{
case
(
wakeUpQueueOption
,
i
)
=>
wakeUpQueueOption
.
foreach
{
wakeUpQueue
=>
wakeUpQueue
.
io
.
flush
:=
io
.
flush
val
flush
=
Wire
(
new
WakeupQueueFlush
)
flush
.
redirect
:=
io
.
flush
flush
.
og0Fail
:=
io
.
og0Resp
(
i
).
valid
&&
RSFeedbackType
.
isBlocked
(
io
.
og0Resp
(
i
).
bits
.
respType
)
flush
.
og1Fail
:=
io
.
og1Resp
(
i
).
valid
&&
RSFeedbackType
.
isBlocked
(
io
.
og1Resp
(
i
).
bits
.
respType
)
wakeUpQueue
.
io
.
flush
:=
flush
wakeUpQueue
.
io
.
enq
.
valid
:=
io
.
deq
(
i
).
fire
&&
!
io
.
deq
(
i
).
bits
.
common
.
needCancel
(
io
.
og0Cancel
,
io
.
og1Cancel
)
&&
{
if
(
io
.
deq
(
i
).
bits
.
common
.
rfWen
.
isDefined
)
io
.
deq
(
i
).
bits
.
common
.
rfWen
.
get
&&
io
.
deq
(
i
).
bits
.
common
.
pdest
=/=
0.
U
...
...
@@ -423,6 +438,8 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
}
wakeUpQueue
.
io
.
enq
.
bits
.
uop
:=
io
.
deq
(
i
).
bits
.
common
wakeUpQueue
.
io
.
enq
.
bits
.
lat
:=
getDeqLat
(
i
,
io
.
deq
(
i
).
bits
.
common
.
fuType
)
wakeUpQueue
.
io
.
og0IssueFail
:=
flush
.
og0Fail
wakeUpQueue
.
io
.
og1IssueFail
:=
flush
.
og1Fail
}
}
...
...
src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala
浏览文件 @
ddef3fab
...
...
@@ -14,8 +14,10 @@ class MultiWakeupQueueIO[T <: Data, TFlush <: Data](
val
lat
=
Output
(
UInt
(
latWidth
.
W
))
}
val
flush
=
Flipped
(
flushGen
)
val
flush
=
Input
(
flushGen
)
val
enq
=
Flipped
(
Valid
(
new
EnqBundle
))
val
og0IssueFail
=
Input
(
Bool
())
val
og1IssueFail
=
Input
(
Bool
())
val
deq
=
Output
(
Valid
(
gen
))
}
...
...
@@ -23,7 +25,7 @@ class MultiWakeupQueue[T <: Data, TFlush <: Data](
val
gen
:
T
,
val
flushGen
:
TFlush
,
val
latencySet
:
Set
[
Int
],
flushFunc
:
(
T
,
TFlush
)
=>
Bool
,
flushFunc
:
(
T
,
TFlush
,
Int
)
=>
Bool
)
extends
Module
{
require
(
latencySet
.
min
>=
0
)
...
...
@@ -31,14 +33,18 @@ class MultiWakeupQueue[T <: Data, TFlush <: Data](
val
pipes
=
latencySet
.
map
(
x
=>
Module
(
new
PipeWithFlush
[
T
,
TFlush
](
gen
,
flushGen
,
x
,
flushFunc
))).
toSeq
pipes
.
zip
WithIndex
.
foreach
{
case
(
pipe
,
i
)
=>
pipes
.
zip
(
latencySet
)
.
foreach
{
case
(
pipe
,
lat
)
=>
pipe
.
io
.
flush
:=
io
.
flush
pipe
.
io
.
enq
.
valid
:=
io
.
enq
.
valid
&&
io
.
enq
.
bits
.
lat
===
i
.
U
pipe
.
io
.
enq
.
valid
:=
io
.
enq
.
valid
&&
io
.
enq
.
bits
.
lat
===
lat
.
U
pipe
.
io
.
enq
.
bits
:=
io
.
enq
.
bits
.
uop
}
private
val
pipesValidVec
=
VecInit
(
pipes
.
map
(
_
.
io
.
deq
.
valid
))
private
val
pipesValidVec
=
VecInit
(
pipes
.
map
(
_
.
io
.
deq
.
valid
).
zip
(
latencySet
).
map
(
_
match
{
case
(
valid
,
1
)
=>
valid
&&
!
io
.
og0IssueFail
case
(
valid
,
2
)
=>
valid
&&
!
io
.
og1IssueFail
case
(
valid
,
_
)
=>
valid
}))
private
val
pipesBitsVec
=
VecInit
(
pipes
.
map
(
_
.
io
.
deq
.
bits
))
io
.
deq
.
valid
:=
pipesValidVec
.
asUInt
.
orR
...
...
src/test/scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala
浏览文件 @
ddef3fab
...
...
@@ -16,7 +16,7 @@ object MultiWakeupQueueMain extends App {
new
DynInst
()(
p
),
ValidIO
(
new
Redirect
()(
p
)),
Set
(
2
,
4
),
(
dynInst
:
DynInst
,
flush
:
ValidIO
[
Redirect
])
=>
dynInst
.
robIdx
.
needFlush
(
flush
)
(
dynInst
:
DynInst
,
flush
:
ValidIO
[
Redirect
]
,
stage
:
Int
)
=>
dynInst
.
robIdx
.
needFlush
(
flush
)
),
Array
(
"--full-stacktrace"
,
"--target-dir"
,
"build/issue"
)
)
...
...
src/test/scala/xiangshan/utils/GenPipeWithFlush.scala
浏览文件 @
ddef3fab
...
...
@@ -17,7 +17,7 @@ object GenPipeWithFlush extends App {
new
DynInst
()(
p
),
ValidIO
(
new
Redirect
()(
p
)),
2
,
(
dynInst
:
DynInst
,
flush
:
ValidIO
[
Redirect
])
=>
dynInst
.
robIdx
.
needFlush
(
flush
)
(
dynInst
:
DynInst
,
flush
:
ValidIO
[
Redirect
]
,
stage
:
Int
)
=>
dynInst
.
robIdx
.
needFlush
(
flush
)
),
Array
(
"--target-dir"
,
"build/vifu"
))
}
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录