* dp2: add a pipeline for load/store

Load/store Dispatch2 has a bad timing because it requires the fuType
to disguish the out ports. This brings timing issues because the
instruction has to read busyTable after the port arbitration.

This commit adds a pipeline in dp2Ls, which may cause performance
degradation. Instructions are dispatched according to out, and at
the next cycle it will leave dp2.

* bump difftest trying to fix vcs

* dcache: do not access plru when refill

Now we have accessed plru when load miss, we should not access plru
when refill

* dcache: not not access plru when miss queue full

It will help avoid invalid plru access when miss queue full

fix some bugs.

1. fix l2tlb dead-lock bug
l2tlb won't merge requests at same addr. It will be blocked when having too many requests.
PtwFilter has a bug that will send too many requests. Add a counter to avoid that.

2. fix sfence sync at mmu
different modules in mmu may get sfence at different latency, which will lost requests or some requests have no receiver.
Sync the sfence latency manually to avoid the bug.

* mmu.filter: add counter not to send to many req to l2tlb

* mmu.filter: fix bug that forget counter signal when block issue and deq

* mmu: set sfence/csr delay to 2 cycle, must sync in mmu

now the l2tlb page cache are divided into:
1. stageReq: input && read sram valid && will block when sram write
2. stageDelay: get sram data and delay one cycle
3. stageCheck: check hit and ecc result
4. stageResp: output

Background:
dtlb has 128 entries stored in sram. 128 sets, 1 ways.
advantage: large volume & 1 ways means no tag match logic at data select path
disadvantage: 128 sets means long latency at valid select, which is a Vec-Register.

Optimization: divide valid select into two-cycles

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representation of headPtr and further uses it to
read the free registers from the list, which should be better than the
previous implementation where headPtr is used to indexed into the queue.

The update of tailPtr and the freelist is delayed by one cycle to
optimize the timing. Because freelist allocates new registers in the
next cycle iff there are more than RenameWidth free registers in this
cycle. The freed registers in this cycle will never be used in the next
cycle. Thus, we can delay the updating of queue data to the next cycle.
We also move the update of tailPtr to the next cycle, since PopCount
takes a long timing and we move the last adder to the next cycle. Now
the adder works parallely with PopCount. That is, the updating of
tailPtr is pipelined.

This commit adds a buffer after the function unit that operate across
the integer block and the floating-point block, such as f2i and i2f.

For example, previously the out.ready of f2i depends on whether
mul/div/csr/jump has a valid instruction out, since f2i has lower
priority than them. This ready back-propagates from the integer function
units to the floating-point function units, and finally to the
floating-point reservation stations (since f2i is fully pipelined).

We add a buffer after the function unit to break this ready
back-propagation. It incurs one more cycle of execution latency, but we
leave it not-fully-optimized for now.

Timing can be further optimized if we separates the int writeback and fp
writeback in function units. In the current version, the ready of f2i
affects the ready of f2f pipelines, which is unnecessary. This is the
future work.

This commit adds some registers for performance counters to optimize
the timing. Pipelines are added.

This commit changes the lsrc/psrc of LUI in dispatch instead of
decode to optimize the timing of lsrc in DecodeStage, which is
critical for rename table.

lsrc/ldest should be directly get from instr for the timing. Fused
instructions change lsrc/ldest now, which will be optimized later.

* buspmu: avoid inner space in perf-cnt name

* perfcnt: judge regularity of perfname

* perfcnt: fix some irregular perfname

* bump huancun

last_may_be_rvi_call in case that a call comes after a taken branch

* add SRAM ready (resetfinish) condition for *Array (metaArray/dataArray)
req.ready

* fix mmio_resend_af wrong assignment
* fix wb_half_flush missOffset(using wb_lastIdx instead of PredictWidth
-1)
* change pipeline ready condition (this_ready =  this_stage_fire || this_stage_empty)
* delete 500-cycle ready condition (toICache(*).ready means the SRAM has
been reset and ready for read)

Previous logic checked the value of old_ctr to select between old target and
new target when updating ittage table. However, when we need to alloc a new
entry, the value of old_ctr is X because we do not reset ittage table. So we
would definitely write an X to the target field, which is the output of the
mux, as the selector is X.

* fix for chipsalliance/rocket-chip#2967

* decode: fix width of BitPat(?) in decode logic
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>

* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-to-run

* difftest support ramsize and paddr base config
* 8GB/16GB nemu so are provided by ready-to-run

* ci: update nightly ci, manually set ram_size

* difftest: bump huancun to make vcs happy

* difftest,nemu: support run-time assign mem size

* ci: polish nightly ci script

An instruction with exceptions may have arbitrary instr values and
may be decoded into WFI instructions, which cause errors.

* sc: fix a performance bug

* tage: fix number of use-alt-on-na counters

* tage: update provider u-bit according to provider results

* feat: parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* SBuffer: fix idx update logic

* atomic: parameterize atomic logic in `MemBlock`

* StoreQueue: update allow enque requirement

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

* chore: remove sc too many fail assertion

* chore: use XSWarn()

s1_tag_match_way is vaild iff tag_read.valid and meta_read.valid in s0
for the same req

XiangShan does not support fs=0 because when fs=0, all floating-point
states are not accessible. Spike supports fs=0. To diff with Spike,
we temporarily set fs to 1 when initialized.

This commit fixes the implementation of WFI. The WFI instruction
waits in the ROB until an interrupt might need servicing.

According to the RISC-V manual, the WFI must be unaffected by the
global interrupt bits in `mstatus` and the delegation register
`mideleg`.

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next
instruction will wait in the ROB until an interrupt.

* difftest: fix false-positive difftest intRF writeback, adapt to new difftest API

* csr: skip mip difftest

* bump difftest

* bump difftest

* fix some typos
Signed-off-by: Ncuishuang <imcusg@gmail.com>