dcache: do not access plru when refill (#1591)

* dcache: do not access plru when refill

Now we have accessed plru when load miss, we should not access plru
when refill

* dcache: not not access plru when miss queue full

It will help avoid invalid plru access when miss queue full

src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala

@@ -638,8 +638,7 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   }
 
   val replAccessReqs = ldu.map(_.io.replace_access) ++ Seq(
-    mainPipe.io.replace_access,
-    refillPipe.io.replace_access
+    mainPipe.io.replace_access
   )
   val touchWays = Seq.fill(replAccessReqs.size)(Wire(ValidIO(UInt(log2Up(nWays).W))))
   touchWays.zip(replAccessReqs).foreach {

src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala

@@ -150,10 +150,6 @@ class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPer
   io.banked_data_read.bits.addr := s1_vaddr
   io.banked_data_read.bits.way_en := s1_tag_match_way
 
-  io.replace_access.valid := RegNext(RegNext(io.meta_read.fire()) && s1_valid)
-  io.replace_access.bits.set := RegNext(get_idx(s1_req.addr))
-  io.replace_access.bits.way := RegNext(Mux(s1_tag_match, OHToUInt(s1_tag_match_way), io.replace_way.way))
-
   // get s1_will_send_miss_req in lpad_s1
   val s1_has_permission = s1_hit_coh.onAccess(s1_req.cmd)._1
   val s1_new_hit_coh = s1_hit_coh.onAccess(s1_req.cmd)._3
@@ -272,6 +268,12 @@ class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPer
   io.lsu.s1_bank_conflict := io.bank_conflict_fast
   assert(RegNext(s1_ready && s2_ready), "load pipeline should never be blocked")
 
+  // update plru, report error in s3
+
+  io.replace_access.valid := RegNext(RegNext(RegNext(io.meta_read.fire()) && s1_valid) && !s2_nack_no_mshr)
+  io.replace_access.bits.set := RegNext(RegNext(get_idx(s1_req.addr)))
+  io.replace_access.bits.way := RegNext(RegNext(Mux(s1_tag_match, OHToUInt(s1_tag_match_way), io.replace_way.way)))
+
   io.error := 0.U.asTypeOf(new L1CacheErrorInfo())
   // report tag / data / l2 error (with paddr) to bus error unit
   io.error.report_to_beu := RegNext((s2_tag_error || s2_data_error) && s2_valid)

src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala

@@ -51,7 +51,6 @@ class RefillPipe(implicit p: Parameters) extends DCacheModule {
     val tag_write = DecoupledIO(new TagWriteReq)
     val store_resp = ValidIO(new DCacheLineResp)
     val release_wakeup = ValidIO(UInt(log2Up(cfg.nMissEntries).W))
-    val replace_access = ValidIO(new ReplacementAccessBundle)
   })
 
   // Assume that write in refill pipe is always ready
@@ -98,8 +97,4 @@ class RefillPipe(implicit p: Parameters) extends DCacheModule {
 
   io.release_wakeup.valid := refill_w_valid
   io.release_wakeup.bits := refill_w_req.miss_id
-
-  io.replace_access.valid := refill_w_valid
-  io.replace_access.bits.set := idx
-  io.replace_access.bits.way := OHToUInt(refill_w_req.way_en)
 }