This reverts commit 58fca539.

Previously, CSR determines interrupt by redirect.valid && interruptBitEnable.
However, interruptBitEnable does not mean the redirect is an interrupt.
We reuse isFlushPipe in Roq to represent an interrupt for CSR.

have not connected the performance counters to CSR

* It will make snapshot more precise
* NEMU that includes commit d4efeb7 is needed to use difftest

* If satp is written with an unsupported MODE,
the entire write has no effect

cputest pass