dtlb/csr: add perf cnt for itlb

cputest pass

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -319,8 +319,8 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
   // val sie = RegInit(0.U(XLEN.W))
   val sieMask = "h222".U & mideleg
   val sipMask  = "h222".U & mideleg
-  val satp = RegInit(0.U(XLEN.W))
-  // val satp = RegInit(UInt(XLEN.W), "h8000000000087fbe".U) // only use for tlb naive debug
+  // val satp = RegInit(0.U(XLEN.W))
+  val satp = RegInit(UInt(XLEN.W), "h8000000000087fbe".U) // only use for tlb naive debug
   val satpMask = "hf0000fffffffffff".U // disable asid
   // val satp = RegInit(UInt(XLEN.W), 0.U)
   val sepc = RegInit(UInt(XLEN.W), 0.U)
@@ -790,9 +790,11 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
     "DTlbMissCnt1"-> (0xb20, "perfCntDtlbMissCnt1"    ),
     "DTlbMissCnt2"-> (0xb21, "perfCntDtlbMissCnt2"    ),
     "DTlbMissCnt3"-> (0xb22, "perfCntDtlbMissCnt3"    ),
-    "PtwReqCnt"   -> (0xb23, "perfCntPtwReqCnt"       ),
-    "PtwCycleCnt" -> (0xb24, "perfCntPtwCycleCnt"     ),
-    "PtwL2TlbHit" -> (0xb25, "perfCntPtwL2TlbHit"     )
+    "ITlbReqCnt0" -> (0xb23, "perfCntItlbReqCnt0"     ),
+    "ITlbMissCnt0"-> (0xb24, "perfCntItlbMissCnt0"    ),
+    "PtwReqCnt"   -> (0xb25, "perfCntPtwReqCnt"       ),
+    "PtwCycleCnt" -> (0xb26, "perfCntPtwCycleCnt"     ),
+    "PtwL2TlbHit" -> (0xb27, "perfCntPtwL2TlbHit"     )
 //    "Custom1"     -> (0xb1b, "Custom1"             ),
 //    "Custom2"     -> (0xb1c, "Custom2"             ),
 //    "Custom3"     -> (0xb1d, "Custom3"             ),

src/main/scala/xiangshan/cache/dtlb.scala

@@ -329,7 +329,7 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
     }
   }
 
-  if (!env.FPGAPlatform) {
+  if (!env.FPGAPlatform && isDtlb) {
     ExcitingUtils.addSource(valid(0)/* && vmEnable*/, "perfCntDtlbReqCnt0", Perf)
     ExcitingUtils.addSource(valid(1)/* && vmEnable*/, "perfCntDtlbReqCnt1", Perf)
     ExcitingUtils.addSource(valid(2)/* && vmEnable*/, "perfCntDtlbReqCnt2", Perf)
@@ -340,6 +340,11 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
     ExcitingUtils.addSource(valid(3)/* && vmEnable*/ && miss(3), "perfCntDtlbMissCnt3", Perf)
   }
 
+  if (!env.FPGAPlatform && !isDtlb) {
+    ExcitingUtils.addSource(valid(0)/* && vmEnable*/, "perfCntItlbReqCnt0", Perf)
+    ExcitingUtils.addSource(valid(0)/* && vmEnable*/ && miss(0), "perfCntItlbMissCnt0", Perf)
+  }
+
   // Log
   for(i <- 0 until Width) {
     XSDebug(req(i).valid, p"req(${i.U}): ${req(i).bits}\n")
@@ -397,7 +402,7 @@ object TLB {
     } else { // itlb
       require(width == 1)
       tlb.io.requestor(0).req.valid := in(0).req.valid
-      tlb.io.requestor(0).req.bits := in(0).req.valid
+      tlb.io.requestor(0).req.bits := in(0).req.bits
       in(0).req.ready := !tlb.io.requestor(0).resp.bits.miss && in(0).resp.ready
 
       // val pf = LookupTree(tlb.io.requestor(0).req.bits.cmd, List(

src/main/scala/xiangshan/cache/icache.scala

@@ -339,7 +339,7 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
   bus.a.bits  := edge.Get(
     fromSource      = cacheID.U,
     // toAddress       = groupPC(s3_req_pc),
-    toAddress       = groupPC(s3_tlb_resp.paddr)
+    toAddress       = groupPC(s3_tlb_resp.paddr),
     lgSize          = (log2Up(cacheParams.blockBytes)).U)._2 
 
   bus.d.ready := true.B

src/main/scala/xiangshan/frontend/IFU.scala

@@ -255,10 +255,14 @@ class IFU extends XSModule with HasIFUConst
   pd.io.prev.bits := prevHalfInstr.instr
   // if a fetch packet triggers page fault, set the pf instruction to nop
   when (!if3_hasPrevHalfInstr && io.icacheResp.bits.ipf) {
-    (0 until FetchWidth).foreach(i => pd.io.in.data(i*32+31, i*32) := ZeroExt("b0010011".U, 32)) // nop
+    val instrs = Wire(Vec(FetchWidth, UInt(32.W)))
+    (0 until FetchWidth).foreach(i => instrs(i) := ZeroExt("b0010011".U, 32)) // nop
+    pd.io.in.data := instrs.asUInt
   }.elsewhen (if3_hasPrevHalfInstr && (prevHalfInstr.ipf || io.icacheResp.bits.ipf)) {
     pd.io.prev.bits := ZeroExt("b0010011".U, 16)
-    (0 until FetchWidth).foreach(i => pd.io.in.data(i*32+31, i*32) := Cat(ZeroExt("b0010011".U, 16), Fill(16, 0.U(1.W))))
+    val instrs = Wire(Vec(FetchWidth, UInt(32.W)))
+    (0 until FetchWidth).foreach(i => instrs(i) := Cat(ZeroExt("b0010011".U, 16), Fill(16, 0.U(1.W))))
+    pd.io.in.data := instrs.asUInt
 
     when (io.icacheResp.bits.ipf && !prevHalfInstr.ipf) { crossPageIPF := true.B } // higher 16 bits page fault
   }

src/main/scala/xiangshan/frontend/Ibuffer.scala

@@ -7,7 +7,7 @@ import xiangshan._
 import utils._
 import xiangshan.backend.fu.HasExceptionNO
 
-class Ibuffer extends XSModule with HasExceptionNO {
+class Ibuffer extends XSModule {
   val io = IO(new Bundle() {
     val flush = Input(Bool())
     val in = Flipped(DecoupledIO(new FetchPacket))
@@ -73,7 +73,9 @@ class Ibuffer extends XSModule with HasExceptionNO {
       
       io.out(i).bits.instr := ibuf(deq_idx).inst
       io.out(i).bits.pc := ibuf(deq_idx).pc
-      io.out(i).bits.exceptionVec := Mux(ibuf(deq_idx).ipf, UIntToOH(instrPageFault.U), 0.U)
+      // io.out(i).bits.exceptionVec := Mux(ibuf(deq_idx).ipf, UIntToOH(instrPageFault.U), 0.U)
+      io.out(i).bits.exceptionVec := 0.U.asTypeOf(Vec(16, Bool()))
+      io.out(i).bits.exceptionVec(instrPageFault) := ibuf(deq_idx).ipf
       // io.out(i).bits.brUpdate := ibuf(deq_idx).brInfo
       io.out(i).bits.brUpdate := DontCare
       io.out(i).bits.brUpdate.pc := ibuf(deq_idx).pc