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体验新版 GitCode,发现更多精彩内容 >>
提交
7ccd034b
编写于
9月 07, 2020
作者:
J
jinyue110
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
icache: add performance counter
上级
5c979681
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
13 addition
and
4 deletion
+13
-4
debug/Makefile
debug/Makefile
+1
-1
src/main/scala/xiangshan/backend/fu/CSR.scala
src/main/scala/xiangshan/backend/fu/CSR.scala
+3
-1
src/main/scala/xiangshan/cache/icache.scala
src/main/scala/xiangshan/cache/icache.scala
+9
-2
未找到文件。
debug/Makefile
浏览文件 @
7ccd034b
...
@@ -3,7 +3,7 @@ NANOS_HOME ?= $(AM_HOME)/../nanos-lite
...
@@ -3,7 +3,7 @@ NANOS_HOME ?= $(AM_HOME)/../nanos-lite
SINGLETEST
=
ALL
=
min3
SINGLETEST
=
ALL
=
min3
B
?=
0
B
?=
0
E
?=
-1
E
?=
0
V
?=
ALL
V
?=
ALL
#V ?= OFF
#V ?= OFF
EMU_ARGS
=
B
=
$(B)
E
=
$(E)
V
=
$(V)
EMU_ARGS
=
B
=
$(B)
E
=
$(E)
V
=
$(V)
...
...
src/main/scala/xiangshan/backend/fu/CSR.scala
浏览文件 @
7ccd034b
...
@@ -793,7 +793,9 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
...
@@ -793,7 +793,9 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
"ITlbMissCnt0"
->
(
0xb24
,
"perfCntItlbMissCnt0"
),
"ITlbMissCnt0"
->
(
0xb24
,
"perfCntItlbMissCnt0"
),
"PtwReqCnt"
->
(
0xb25
,
"perfCntPtwReqCnt"
),
"PtwReqCnt"
->
(
0xb25
,
"perfCntPtwReqCnt"
),
"PtwCycleCnt"
->
(
0xb26
,
"perfCntPtwCycleCnt"
),
"PtwCycleCnt"
->
(
0xb26
,
"perfCntPtwCycleCnt"
),
"PtwL2TlbHit"
->
(
0xb27
,
"perfCntPtwL2TlbHit"
)
"PtwL2TlbHit"
->
(
0xb27
,
"perfCntPtwL2TlbHit"
),
"ICacheReq"
->
(
0xb28
,
"perfCntIcacheReqCnt"
),
"ICacheMiss"
->
(
0xb29
,
"perfCntIcacheMissCnt"
)
// "Custom1" -> (0xb1b, "Custom1" ),
// "Custom1" -> (0xb1b, "Custom1" ),
// "Custom2" -> (0xb1c, "Custom2" ),
// "Custom2" -> (0xb1c, "Custom2" ),
// "Custom3" -> (0xb1d, "Custom3" ),
// "Custom3" -> (0xb1d, "Custom3" ),
...
...
src/main/scala/xiangshan/cache/icache.scala
浏览文件 @
7ccd034b
package
xiangshan.cache
package
xiangshan.cache
import
chisel3.util.experimental.BoringUtils
import
chipsalliance.rocketchip.config.Parameters
import
chisel3._
import
chisel3._
import
chisel3.util._
import
chisel3.util._
import
device._
import
device._
import
xiangshan._
import
xiangshan._
import
xiangshan.frontend._
import
xiangshan.frontend._
import
utils._
import
utils._
import
chisel3.ExcitingUtils._
import
chisel3.util.experimental.BoringUtils
import
chipsalliance.rocketchip.config.Parameters
import
freechips.rocketchip.tilelink.
{
TLBundleA
,
TLBundleD
,
TLBundleE
,
TLEdgeOut
}
import
freechips.rocketchip.tilelink.
{
TLBundleA
,
TLBundleD
,
TLBundleE
,
TLEdgeOut
}
import
freechips.rocketchip.diplomacy.
{
AddressSet
,
IdRange
,
LazyModule
,
LazyModuleImp
,
TransferSizes
}
import
freechips.rocketchip.diplomacy.
{
AddressSet
,
IdRange
,
LazyModule
,
LazyModuleImp
,
TransferSizes
}
...
@@ -406,5 +407,11 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
...
@@ -406,5 +407,11 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
bus
.
d
.
ready
:=
true
.
B
bus
.
d
.
ready
:=
true
.
B
XSDebug
(
"[flush] flush_0:%d flush_1:%d\n"
,
io
.
flush
(
0
),
io
.
flush
(
1
))
XSDebug
(
"[flush] flush_0:%d flush_1:%d\n"
,
io
.
flush
(
0
),
io
.
flush
(
1
))
//Performance Counter
if
(!
env
.
FPGAPlatform
)
{
ExcitingUtils
.
addSource
(
s3_valid
&&
(
state
===
s_idle
),
"perfCntIcacheReqCnt"
,
Perf
)
ExcitingUtils
.
addSource
(
s3_valid
&&
(
state
===
s_idle
)
&&
s3_miss
,
"perfCntIcacheMissCnt"
,
Perf
)
}
}
}
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