icache: add performance counter

debug/Makefile

@@ -3,7 +3,7 @@ NANOS_HOME ?= $(AM_HOME)/../nanos-lite
 SINGLETEST = ALL=min3
 
 B ?= 0
-E ?= -1
+E ?= 0
 V ?= ALL
 #V ?= OFF
 EMU_ARGS = B=$(B) E=$(E) V=$(V)

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -793,7 +793,9 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
     "ITlbMissCnt0"-> (0xb24, "perfCntItlbMissCnt0"    ),
     "PtwReqCnt"   -> (0xb25, "perfCntPtwReqCnt"       ),
     "PtwCycleCnt" -> (0xb26, "perfCntPtwCycleCnt"     ),
-    "PtwL2TlbHit" -> (0xb27, "perfCntPtwL2TlbHit"     )
+    "PtwL2TlbHit" -> (0xb27, "perfCntPtwL2TlbHit"     ),
+    "ICacheReq"   -> (0xb28, "perfCntIcacheReqCnt"     ),
+    "ICacheMiss"   -> (0xb29, "perfCntIcacheMissCnt"     )
 //    "Custom1"     -> (0xb1b, "Custom1"             ),
 //    "Custom2"     -> (0xb1c, "Custom2"             ),
 //    "Custom3"     -> (0xb1d, "Custom3"             ),

src/main/scala/xiangshan/cache/icache.scala

 package xiangshan.cache
 
-import chisel3.util.experimental.BoringUtils
-import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import device._
 import xiangshan._
 import xiangshan.frontend._
 import utils._
+import chisel3.ExcitingUtils._
+import chisel3.util.experimental.BoringUtils
+import chipsalliance.rocketchip.config.Parameters
 
 import freechips.rocketchip.tilelink.{TLBundleA,TLBundleD,TLBundleE,TLEdgeOut}
 import freechips.rocketchip.diplomacy.{AddressSet,IdRange,LazyModule, LazyModuleImp, TransferSizes}
@@ -406,5 +407,11 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
   bus.d.ready := true.B
 
   XSDebug("[flush] flush_0:%d  flush_1:%d\n",io.flush(0),io.flush(1))
+
+  //Performance Counter
+  if (!env.FPGAPlatform ) {
+    ExcitingUtils.addSource( s3_valid && (state === s_idle), "perfCntIcacheReqCnt", Perf)
+    ExcitingUtils.addSource( s3_valid && (state === s_idle) && s3_miss, "perfCntIcacheMissCnt", Perf)
+  }
 }