mem,lsq: remove instIsStore and use commitType instead

src/main/scala/xiangshan/Bundle.scala

@@ -155,26 +155,6 @@ trait HasLSIdx { this: HasXSParameter =>
   // Separate LSQ
   val lqIdx = new LqPtr
   val sqIdx = new SqPtr
-  val instIsLoad = Bool()
-  // }
-
-  // def isLoad(): Bool = instIsLoad
-
-  // def isLoadAfter(thatLqIdx: UInt): Bool = {
-  //   Mux(
-  //     lqIdx.head(1) === thatLqIdx.head(1),
-  //     lqIdx.tail(1) > thatLqIdx.tail(1),
-  //     lqIdx.tail(1) < thatLqIdx.tail(1)
-  //   )
-  // }
-
-  // def isStoreAfter(thatSqIdx: UInt): Bool = {
-  //   Mux(
-  //     sqIdx.head(1) === thatSqIdx.head(1),
-  //     sqIdx.tail(1) > thatSqIdx.tail(1),
-  //     sqIdx.tail(1) < thatSqIdx.tail(1)
-  //   )
-  // }
 }
 
 class LSIdx extends XSBundle with HasLSIdx {}

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -69,12 +69,15 @@ class Dispatch1 extends XSModule {
 
   for (i <- 0 until RenameWidth) {
     // input for ROQ and LSROQ
+    val commitType = Cat(isLs(i), isStore(i) | isFp(i))
+
     io.toRoq(i).valid := io.fromRename(i).valid && !roqIndexRegValid(i)
     io.toRoq(i).bits := io.fromRename(i).bits
-    io.toRoq(i).bits.ctrl.commitType := Cat(isLs(i), isStore(i) | isFp(i)) // TODO: add it to decode
+    io.toRoq(i).bits.ctrl.commitType := commitType
 
     io.toLsroq(i).valid := io.fromRename(i).valid && !lsIndexRegValid(i) && isLs(i) && io.fromRename(i).bits.ctrl.fuType =/= FuType.mou && roqIndexAcquired(i) && !cancelled(i)
     io.toLsroq(i).bits := io.fromRename(i).bits
+    io.toLsroq(i).bits.ctrl.commitType := commitType
     io.toLsroq(i).bits.roqIdx := Mux(roqIndexRegValid(i), roqIndexReg(i), io.roqIdxs(i))
 
     // receive indexes from ROQ and LSROQ
@@ -100,8 +103,7 @@ class Dispatch1 extends XSModule {
     } else {
       uopWithIndex(i).lqIdx := Mux(lsIndexRegValid(i), lsIndexReg(i), io.lsIdx(i)).lqIdx
       uopWithIndex(i).sqIdx := Mux(lsIndexRegValid(i), lsIndexReg(i), io.lsIdx(i)).sqIdx
-      uopWithIndex(i).instIsLoad := Mux(lsIndexRegValid(i), lsIndexReg(i), io.lsIdx(i)).instIsLoad
-      XSDebug(io.toLsroq(i).fire(), p"pc 0x${Hexadecimal(io.fromRename(i).bits.cf.pc)} receives lq ${io.lsIdx(i).lqIdx} sq ${io.lsIdx(i).sqIdx} isLoad ${io.lsIdx(i).instIsLoad}\n")
+      XSDebug(io.toLsroq(i).fire(), p"pc 0x${Hexadecimal(io.fromRename(i).bits.cf.pc)} receives lq ${io.lsIdx(i).lqIdx} sq ${io.lsIdx(i).sqIdx}\n")
     }
 
     XSDebug(io.toRoq(i).fire(), p"pc 0x${Hexadecimal(io.fromRename(i).bits.cf.pc)} receives nroq ${io.roqIdxs(i)}\n")
@@ -165,7 +167,7 @@ class Dispatch1 extends XSModule {
     }else{
       XSInfo(io.recv(i) && !cancelled(i),
         p"pc 0x${Hexadecimal(io.fromRename(i).bits.cf.pc)} type(${isInt(i)}, ${isFp(i)}, ${isLs(i)}) " +
-          p"roq ${uopWithIndex(i).roqIdx} lq ${uopWithIndex(i).lqIdx} sq ${uopWithIndex(i).sqIdx} isLoad ${uopWithIndex(i).instIsLoad}" +
+          p"roq ${uopWithIndex(i).roqIdx} lq ${uopWithIndex(i).lqIdx} sq ${uopWithIndex(i).sqIdx}" +
           p"(${intIndex.io.reverseMapping(i).bits}, ${fpIndex.io.reverseMapping(i).bits}, ${lsIndex.io.reverseMapping(i).bits})\n")
     }
 

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -603,13 +603,12 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
     val lsIdx = WireInit(0.U.asTypeOf(new LSIdx()))
     lsIdx.lqIdx := io.exception.bits.lqIdx
     lsIdx.sqIdx := io.exception.bits.sqIdx
-    lsIdx.instIsLoad := io.exception.bits.instIsLoad
     ExcitingUtils.addSource(lsIdx, "EXECPTION_LSROQIDX")
     val lqExceptionAddr = WireInit(0.U(VAddrBits.W))
     val sqExceptionAddr = WireInit(0.U(VAddrBits.W))
     ExcitingUtils.addSink(lqExceptionAddr, "EXECPTION_LOAD_VADDR")
     ExcitingUtils.addSink(sqExceptionAddr, "EXECPTION_STORE_VADDR")
-    lsroqExceptionAddr := Mux(io.exception.bits.instIsLoad, lqExceptionAddr, sqExceptionAddr)
+    lsroqExceptionAddr := Mux(CommitType.lsInstIsStore(io.exception.bits.ctrl.commitType), sqExceptionAddr, lqExceptionAddr)
   }
 
   val atomExceptionAddr = WireInit(0.U(VAddrBits.W))

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -71,7 +71,6 @@ class Rename extends XSModule {
     uop.diffTestDebugLrScValid := DontCare
 
     uop.lsroqIdx := DontCare
-    uop.instIsLoad := DontCare
     uop.lqIdx := DontCare
     uop.sqIdx := DontCare
   })

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -112,7 +112,6 @@ class Roq extends XSModule with HasCircularQueuePtrHelper {
       microOp(wbIdx).lsroqIdx := io.exeWbResults(i).bits.uop.lsroqIdx
       microOp(wbIdx).lqIdx := io.exeWbResults(i).bits.uop.lqIdx
       microOp(wbIdx).sqIdx := io.exeWbResults(i).bits.uop.sqIdx
-      microOp(wbIdx).instIsLoad := io.exeWbResults(i).bits.uop.instIsLoad
       microOp(wbIdx).ctrl.flushPipe := io.exeWbResults(i).bits.uop.ctrl.flushPipe
       microOp(wbIdx).diffTestDebugLrScValid := io.exeWbResults(i).bits.uop.diffTestDebugLrScValid
       exuData(wbIdx) := io.exeWbResults(i).bits.data

src/main/scala/xiangshan/mem/lsqueue/separated/LSQWrapper.scala

@@ -122,14 +122,12 @@ class LsqWrappper extends XSModule with HasDCacheParameters with NeedImpl {
     
     // fix valid, allocate lq / sq index
     (0 until RenameWidth).map(i => {
-      val isStore = LSUOpType.isStore(io.dp1Req(i).bits.ctrl.fuOpType)
+      val isStore = CommitType.lsInstIsStore(io.dp1Req(i).bits.ctrl.commitType)
       val prevCanIn = if (i == 0) true.B else Cat((0 until i).map(i => io.dp1Req(i).ready)).andR
       loadQueue.io.dp1Req(i).valid := !isStore && io.dp1Req(i).valid && prevCanIn
       storeQueue.io.dp1Req(i).valid := isStore && io.dp1Req(i).valid && prevCanIn
-      io.lsIdxs(i) := DontCare
       loadQueue.io.lqIdxs(i) <> io.lsIdxs(i).lqIdx
       storeQueue.io.sqIdxs(i) <> io.lsIdxs(i).sqIdx
-      io.lsIdxs(i).instIsLoad := !isStore
       io.dp1Req(i).ready := storeQueue.io.dp1Req(i).ready && loadQueue.io.dp1Req(i).ready
     })
   }

src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala

@@ -90,7 +90,6 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
     }
     val numTryEnqueue = offset +& io.dp1Req(i).valid
     io.dp1Req(i).ready := numTryEnqueue <= emptyEntries
-
     io.lqIdxs(i) := lqIdx
     XSDebug(false, true.B, "(%d, %d) ", io.dp1Req(i).ready, io.dp1Req(i).valid)
   }

src/main/scala/xiangshan/mem/lsqueue/separated/StoreQueue.scala

@@ -86,11 +86,7 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
       // data(index).bwdMask := 0.U(8.W).asBools
     }
     val numTryEnqueue = offset +& io.dp1Req(i).valid
-    // if (i == 0) {
     io.dp1Req(i).ready := numTryEnqueue <= emptyEntries
-    // } else {
-    //   io.dp1Req(i).ready := ringBufferAllowin && !allocated(index)// && io.dp1Req(i - 1).ready
-    // }
     io.sqIdxs(i) := sqIdx
     XSDebug(false, true.B, "(%d, %d) ", io.dp1Req(i).ready, io.dp1Req(i).valid)
   }

src/main/scala/xiangshan/package.scala

@@ -90,5 +90,6 @@ package object xiangshan {
 
     def apply() = UInt(2.W)
     def isLoadStore(commitType: UInt) = commitType(1)
+    def lsInstIsStore(commitType: UInt) = commitType(0)
   }
 }