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2fdc488a
编写于
11月 05, 2020
作者:
L
LinJiawei
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
Remove BoringUtils in fence unit
上级
2f21c20a
变更
11
隐藏空白更改
内联
并排
Showing
11 changed file
with
57 addition
and
29 deletion
+57
-29
src/main/scala/xiangshan/Bundle.scala
src/main/scala/xiangshan/Bundle.scala
+1
-0
src/main/scala/xiangshan/XSCore.scala
src/main/scala/xiangshan/XSCore.scala
+2
-2
src/main/scala/xiangshan/backend/Backend.scala
src/main/scala/xiangshan/backend/Backend.scala
+7
-0
src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala
src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala
+9
-1
src/main/scala/xiangshan/backend/fu/CSR.scala
src/main/scala/xiangshan/backend/fu/CSR.scala
+0
-3
src/main/scala/xiangshan/backend/fu/Fence.scala
src/main/scala/xiangshan/backend/fu/Fence.scala
+14
-10
src/main/scala/xiangshan/cache/dtlb.scala
src/main/scala/xiangshan/cache/dtlb.scala
+12
-3
src/main/scala/xiangshan/cache/icache.scala
src/main/scala/xiangshan/cache/icache.scala
+2
-2
src/main/scala/xiangshan/cache/ptw.scala
src/main/scala/xiangshan/cache/ptw.scala
+2
-2
src/main/scala/xiangshan/frontend/Frontend.scala
src/main/scala/xiangshan/frontend/Frontend.scala
+1
-0
src/main/scala/xiangshan/mem/Memend.scala
src/main/scala/xiangshan/mem/Memend.scala
+7
-6
未找到文件。
src/main/scala/xiangshan/Bundle.scala
浏览文件 @
2fdc488a
...
...
@@ -250,6 +250,7 @@ class FrontendToBackendIO extends XSBundle {
val
redirect
=
Flipped
(
ValidIO
(
new
Redirect
))
val
outOfOrderBrInfo
=
Flipped
(
ValidIO
(
new
BranchUpdateInfo
))
val
inOrderBrInfo
=
Flipped
(
ValidIO
(
new
BranchUpdateInfo
))
val
sfence
=
Input
(
new
SfenceBundle
)
}
class
TlbCsrBundle
extends
XSBundle
{
...
...
src/main/scala/xiangshan/XSCore.scala
浏览文件 @
2fdc488a
...
...
@@ -281,18 +281,18 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter
val
icache
=
outer
.
icache
.
module
val
ptw
=
outer
.
ptw
.
module
// TODO: connect this
front
.
io
.
backend
<>
backend
.
io
.
frontend
front
.
io
.
icacheResp
<>
icache
.
io
.
resp
front
.
io
.
icacheToTlb
<>
icache
.
io
.
tlb
icache
.
io
.
req
<>
front
.
io
.
icacheReq
icache
.
io
.
flush
<>
front
.
io
.
icacheFlush
icache
.
io
.
fencei
:=
backend
.
io
.
fencei
mem
.
io
.
backend
<>
backend
.
io
.
mem
io
.
externalInterrupt
<>
backend
.
io
.
externalInterrupt
ptw
.
io
.
tlb
(
0
)
<>
mem
.
io
.
ptw
ptw
.
io
.
tlb
(
1
)
<>
front
.
io
.
ptw
ptw
.
io
.
sfence
<>
backend
.
io
.
sfence
dcache
.
io
.
lsu
.
load
<>
mem
.
io
.
loadUnitToDcacheVec
dcache
.
io
.
lsu
.
lsroq
<>
mem
.
io
.
loadMiss
...
...
src/main/scala/xiangshan/backend/Backend.scala
浏览文件 @
2fdc488a
...
...
@@ -25,6 +25,8 @@ class Backend extends XSModule
val
frontend
=
Flipped
(
new
FrontendToBackendIO
)
val
mem
=
Flipped
(
new
MemToBackendIO
)
val
externalInterrupt
=
new
ExternalInterruptIO
val
sfence
=
Output
(
new
SfenceBundle
)
val
fencei
=
Output
(
Bool
())
})
...
...
@@ -176,6 +178,8 @@ class Backend extends XSModule
jmpExeUnit
.
io
.
csrOnly
.
exception
.
bits
:=
roq
.
io
.
exception
jmpExeUnit
.
io
.
csrOnly
.
memExceptionVAddr
:=
io
.
mem
.
exceptionAddr
.
vaddr
jmpExeUnit
.
fenceToSbuffer
<>
io
.
mem
.
fenceToSbuffer
io
.
mem
.
sfence
<>
jmpExeUnit
.
sfence
io
.
mem
.
exceptionAddr
.
lsIdx
.
lsroqIdx
:=
roq
.
io
.
exception
.
lsroqIdx
io
.
mem
.
exceptionAddr
.
lsIdx
.
lqIdx
:=
roq
.
io
.
exception
.
lqIdx
io
.
mem
.
exceptionAddr
.
lsIdx
.
sqIdx
:=
roq
.
io
.
exception
.
sqIdx
...
...
@@ -183,6 +187,9 @@ class Backend extends XSModule
io
.
frontend
.
outOfOrderBrInfo
<>
brq
.
io
.
outOfOrderBrInfo
io
.
frontend
.
inOrderBrInfo
<>
brq
.
io
.
inOrderBrInfo
io
.
frontend
.
sfence
<>
jmpExeUnit
.
sfence
io
.
fencei
:=
jmpExeUnit
.
fencei
decode
.
io
.
in
<>
io
.
frontend
.
cfVec
brq
.
io
.
roqRedirect
<>
roq
.
io
.
redirect
...
...
src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala
浏览文件 @
2fdc488a
...
...
@@ -2,7 +2,7 @@ package xiangshan.backend.exu
import
chisel3._
import
chisel3.util.experimental.BoringUtils
import
xiangshan.
{
ExuOutput
,
FuType
}
import
xiangshan.
{
ExuOutput
,
FuType
,
SfenceBundle
}
import
xiangshan.backend.fu.
{
CSR
,
Jump
}
import
xiangshan.backend.decode.isa._
import
xiangshan.backend.fu.fpu.Fflags
...
...
@@ -10,6 +10,10 @@ import utils._
class
JmpExeUnit
extends
Exu
(
Exu
.
jmpExeUnitCfg
)
{
val
fenceToSbuffer
=
IO
(
new
FenceToSbuffer
)
val
sfence
=
IO
(
Output
(
new
SfenceBundle
))
val
fencei
=
IO
(
Output
(
Bool
()))
val
(
valid
,
src1
,
src2
,
uop
,
fuType
,
func
)
=
(
io
.
in
.
valid
,
io
.
in
.
bits
.
src1
,
io
.
in
.
bits
.
src2
,
io
.
in
.
bits
.
uop
,
io
.
in
.
bits
.
uop
.
ctrl
.
fuType
,
io
.
in
.
bits
.
uop
.
ctrl
.
fuOpType
)
val
jmp
=
Module
(
new
Jump
)
...
...
@@ -17,6 +21,10 @@ class JmpExeUnit extends Exu(Exu.jmpExeUnitCfg) {
val
fence
=
Module
(
new
FenceExeUnit
)
val
i2f
=
Module
(
new
I2fExeUnit
)
fenceToSbuffer
<>
fence
.
toSbuffer
sfence
<>
fence
.
sfence
fencei
:=
fence
.
fencei
fence
.
io
.
csrOnly
<>
DontCare
i2f
.
io
.
csrOnly
<>
DontCare
...
...
src/main/scala/xiangshan/backend/fu/CSR.scala
浏览文件 @
2fdc488a
...
...
@@ -359,11 +359,8 @@ class CSR extends XSModule
val
scounteren
=
RegInit
(
UInt
(
XLEN
.
W
),
0.
U
)
val
tlbBundle
=
Wire
(
new
TlbCsrBundle
)
// val sfence = Wire(new SfenceBundle)
tlbBundle
.
satp
:=
satp
.
asTypeOf
(
new
SatpStruct
)
// sfence := 0.U.asTypeOf(new SfenceBundle)
BoringUtils
.
addSource
(
tlbBundle
,
"TLBCSRIO"
)
// BoringUtils.addSource(sfence, "SfenceBundle") // FIXME: move to MOU
// User-Level CSRs
val
uepc
=
Reg
(
UInt
(
XLEN
.
W
))
...
...
src/main/scala/xiangshan/backend/fu/Fence.scala
浏览文件 @
2fdc488a
...
...
@@ -4,25 +4,29 @@ import chisel3._
import
chisel3.util._
import
xiangshan._
import
utils._
import
chisel3.util.experimental.BoringUtils
import
xiangshan.backend.FenceOpType
class
FenceToSbuffer
extends
XSBundle
{
val
flushSb
=
Output
(
Bool
())
val
sbIsEmpty
=
Input
(
Bool
())
}
class
FenceExeUnit
extends
Exu
(
Exu
.
fenceExeUnitCfg
)
{
val
sfence
=
IO
(
Output
(
new
SfenceBundle
))
val
fencei
=
IO
(
Output
(
Bool
()))
val
toSbuffer
=
IO
(
new
FenceToSbuffer
)
val
(
valid
,
src1
,
src2
,
uop
,
func
,
lsrc1
,
lsrc2
)
=
(
io
.
in
.
valid
,
io
.
in
.
bits
.
src1
,
io
.
in
.
bits
.
src2
,
io
.
in
.
bits
.
uop
,
io
.
in
.
bits
.
uop
.
ctrl
.
fuOpType
,
io
.
in
.
bits
.
uop
.
ctrl
.
lsrc1
,
io
.
in
.
bits
.
uop
.
ctrl
.
lsrc2
)
val
s_sb
::
s_tlb
::
s_icache
::
s_none
::
Nil
=
Enum
(
4
)
val
state
=
RegInit
(
s_sb
)
val
sfence
=
WireInit
(
0.
U
.
asTypeOf
(
new
SfenceBundle
))
val
sbuffer
=
WireInit
(
false
.
B
)
val
fencei
=
WireInit
(
false
.
B
)
val
sbEmpty
=
WireInit
(
false
.
B
)
BoringUtils
.
addSource
(
sbuffer
,
"FenceUnitSbufferFlush"
)
BoringUtils
.
addSource
(
sfence
,
"SfenceBundle"
)
BoringUtils
.
addSource
(
fencei
,
"FenceI"
)
BoringUtils
.
addSink
(
sbEmpty
,
"SBufferEmpty"
)
val
sbuffer
=
toSbuffer
.
flushSb
val
sbEmpty
=
toSbuffer
.
sbIsEmpty
// NOTE: icache & tlb & sbuffer must receive flush signal at any time
sbuffer
:=
valid
&&
state
===
s_sb
&&
!
sbEmpty
fencei
:=
(
state
===
s_icache
&&
sbEmpty
)
||
(
state
===
s_sb
&&
valid
&&
sbEmpty
&&
func
===
FenceOpType
.
fencei
)
...
...
@@ -49,4 +53,4 @@ class FenceExeUnit extends Exu(Exu.fenceExeUnitCfg) {
assert
(!(
valid
||
state
=/=
s_sb
)
||
io
.
out
.
ready
)
// NOTE: fence instr must be the first(only one) instr, so io.out.ready must be true
XSDebug
(
valid
||
state
=/=
s_sb
||
io
.
out
.
valid
,
p
"In(${io.in.valid} ${io.in.ready}) Out(${io.out.valid} ${io.out.ready}) state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InroqIdx:${io.in.bits.uop.roqIdx} Outpc:0x${Hexadecimal(io.out.bits.uop.cf.pc)} OutroqIdx:${io.out.bits.uop.roqIdx}\n"
)
}
\ No newline at end of file
}
src/main/scala/xiangshan/cache/dtlb.scala
浏览文件 @
2fdc488a
...
...
@@ -175,6 +175,7 @@ class TlbPtwIO extends TlbBundle {
class
TlbIO
(
Width
:
Int
)
extends
TlbBundle
{
val
requestor
=
Vec
(
Width
,
Flipped
(
new
TlbRequestIO
))
val
ptw
=
new
TlbPtwIO
val
sfence
=
Input
(
new
SfenceBundle
)
override
def
cloneType
:
this.
type
=
(
new
TlbIO
(
Width
)).
asInstanceOf
[
this.
type
]
}
...
...
@@ -187,7 +188,7 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
val
resp
=
io
.
requestor
.
map
(
_
.
resp
)
val
ptw
=
io
.
ptw
val
sfence
=
WireInit
(
0.
U
.
asTypeOf
(
new
SfenceBundle
))
val
sfence
=
io
.
sfence
val
csr
=
WireInit
(
0.
U
.
asTypeOf
(
new
TlbCsrBundle
))
val
satp
=
csr
.
satp
val
priv
=
csr
.
priv
...
...
@@ -195,7 +196,6 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
val
mode
=
if
(
isDtlb
)
priv
.
dmode
else
priv
.
imode
// val vmEnable = satp.mode === 8.U // && (mode < ModeM) // FIXME: fix me when boot xv6/linux...
val
vmEnable
=
satp
.
mode
===
8.
U
&&
(
mode
<
ModeM
)
BoringUtils
.
addSink
(
sfence
,
"SfenceBundle"
)
BoringUtils
.
addSink
(
csr
,
"TLBCSRIO"
)
val
reqAddr
=
req
.
map
(
_
.
bits
.
vaddr
.
asTypeOf
(
vaBundle
))
...
...
@@ -396,10 +396,19 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
}
object
TLB
{
def
apply
(
in
:
Seq
[
BlockTlbRequestIO
],
width
:
Int
,
isDtlb
:
Boolean
,
shouldBlock
:
Boolean
)
=
{
def
apply
(
in
:
Seq
[
BlockTlbRequestIO
],
sfence
:
SfenceBundle
,
width
:
Int
,
isDtlb
:
Boolean
,
shouldBlock
:
Boolean
)
=
{
require
(
in
.
length
==
width
)
val
tlb
=
Module
(
new
TLB
(
width
,
isDtlb
))
tlb
.
io
.
sfence
<>
sfence
if
(!
shouldBlock
)
{
// dtlb
for
(
i
<-
0
until
width
)
{
...
...
src/main/scala/xiangshan/cache/icache.scala
浏览文件 @
2fdc488a
...
...
@@ -91,6 +91,7 @@ class ICacheIO(edge: TLEdgeOut) extends ICacheBundle
val
resp
=
DecoupledIO
(
new
ICacheResp
)
val
tlb
=
new
BlockTlbRequestIO
val
flush
=
Input
(
UInt
(
2.
W
))
val
fencei
=
Input
(
Bool
())
}
/* ------------------------------------------------------------
...
...
@@ -276,9 +277,8 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
.
elsewhen
((
state
===
s_wait_resp
)
&&
needFlush
){
needFlush
:=
false
.
B
}
//cache flush register
val
icacheFlush
=
WireInit
(
false
.
B
)
val
icacheFlush
=
io
.
fencei
val
cacheflushed
=
RegInit
(
false
.
B
)
BoringUtils
.
addSink
(
icacheFlush
,
"FenceI"
)
XSDebug
(
"[Fence.i] icacheFlush:%d, cacheflushed:%d\n"
,
icacheFlush
,
cacheflushed
)
when
(
icacheFlush
&&
(
state
=/=
s_idle
)
&&
(
state
=/=
s_wait_resp
)){
cacheflushed
:=
true
.
B
}
.
elsewhen
((
state
===
s_wait_resp
)
&&
cacheflushed
)
{
cacheflushed
:=
false
.
B
}
...
...
src/main/scala/xiangshan/cache/ptw.scala
浏览文件 @
2fdc488a
...
...
@@ -108,6 +108,7 @@ class PtwResp extends PtwBundle {
class
PtwIO
extends
PtwBundle
{
val
tlb
=
Vec
(
PtwWidth
,
Flipped
(
new
TlbPtwIO
))
val
sfence
=
Input
(
new
SfenceBundle
)
}
object
ValidHold
{
...
...
@@ -159,11 +160,10 @@ class PTWImp(outer: PTW) extends PtwModule(outer){
val
validOneCycle
=
OneCycleValid
(
arb
.
io
.
out
.
fire
())
arb
.
io
.
out
.
ready
:=
!
valid
// || resp(arbChosen).fire()
val
sfence
=
WireInit
(
0.
U
.
asTypeOf
(
new
SfenceBundle
))
val
sfence
=
io
.
sfence
val
csr
=
WireInit
(
0.
U
.
asTypeOf
(
new
TlbCsrBundle
))
val
satp
=
csr
.
satp
val
priv
=
csr
.
priv
BoringUtils
.
addSink
(
sfence
,
"SfenceBundle"
)
BoringUtils
.
addSink
(
csr
,
"TLBCSRIO"
)
// two level: l2-tlb-cache && pde/pte-cache
...
...
src/main/scala/xiangshan/frontend/Frontend.scala
浏览文件 @
2fdc488a
...
...
@@ -33,6 +33,7 @@ class Frontend extends XSModule {
//itlb to ptw
io
.
ptw
<>
TLB
(
in
=
Seq
(
io
.
icacheToTlb
),
sfence
=
io
.
backend
.
sfence
,
width
=
1
,
isDtlb
=
false
,
shouldBlock
=
true
...
...
src/main/scala/xiangshan/mem/Memend.scala
浏览文件 @
2fdc488a
...
...
@@ -2,14 +2,13 @@ package xiangshan.mem
import
chisel3._
import
chisel3.util._
import
chisel3.util.experimental.BoringUtils
import
xiangshan._
import
utils._
import
chisel3.util.experimental.BoringUtils
import
xiangshan.backend.roq.RoqPtr
import
xiangshan.cache._
import
bus.tilelink.
{
TLArbiter
,
TLCached
,
TLMasterUtilities
,
TLParameters
}
import
xiangshan.backend.exu.FenceToSbuffer
object
genWmask
{
def
apply
(
addr
:
UInt
,
sizeEncode
:
UInt
)
:
UInt
=
{
...
...
@@ -80,6 +79,8 @@ class MemToBackendIO extends XSBundle {
val
oldestStore
=
Output
(
Valid
(
new
RoqPtr
))
val
roqDeqPtr
=
Input
(
new
RoqPtr
)
val
exceptionAddr
=
new
ExceptionAddrIO
val
fenceToSbuffer
=
Flipped
(
new
FenceToSbuffer
)
val
sfence
=
Input
(
new
SfenceBundle
)
}
// Memory pipeline wrapper
...
...
@@ -108,6 +109,7 @@ class Memend extends XSModule {
// dtlb
io
.
ptw
<>
dtlb
.
io
.
ptw
dtlb
.
io
.
sfence
<>
io
.
backend
.
sfence
// LoadUnit
for
(
i
<-
0
until
exuParameters
.
LduCnt
)
{
...
...
@@ -166,10 +168,9 @@ class Memend extends XSModule {
// flush sbuffer
val
fenceFlush
=
WireInit
(
false
.
B
)
val
atomicsFlush
=
atomicsUnit
.
io
.
flush_sbuffer
.
valid
BoringUtils
.
addSink
(
fenceFlush
,
"FenceUnitSbufferFlush"
)
val
sbEmpty
=
WireInit
(
false
.
B
)
sbEmpty
:=
sbuffer
.
io
.
flush
.
empty
BoringUtils
.
addSource
(
sbEmpty
,
"SBufferEmpty"
)
fenceFlush
:=
io
.
backend
.
fenceToSbuffer
.
flushSb
val
sbEmpty
=
sbuffer
.
io
.
flush
.
empty
io
.
backend
.
fenceToSbuffer
.
sbIsEmpty
:=
sbEmpty
// if both of them tries to flush sbuffer at the same time
// something must have gone wrong
assert
(!(
fenceFlush
&&
atomicsFlush
))
...
...
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