Difftest: use exciting utils instead boring utils

src/main/scala/xiangshan/backend/Backend.scala

@@ -260,32 +260,12 @@ class Backend extends XSModule
   roq.io.exeWbResults.last := brq.io.out
 
 
-  // TODO: Remove sink and source
-  val tmp = WireInit(0.U)
-  val sinks = Array[String](
-    "DTLBFINISH",
-    "DTLBPF",
-    "DTLBENABLE",
-    "perfCntCondMdcacheLoss",
-    "perfCntCondMl2cacheLoss",
-    "perfCntCondMdcacheHit",
-    "lsuMMIO",
-    "perfCntCondMl2cacheHit",
-    "perfCntCondMl2cacheReq",
-    "mtip",
-    "perfCntCondMdcacheReq",
-    "meip"
-  )
-  for (s <- sinks) {
-    BoringUtils.addSink(tmp, s)
-  }
-
   val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
   BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG")
   BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG")
   val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
   if (!env.FPGAPlatform) {
-    BoringUtils.addSource(debugArchReg, "difftestRegs")
+    ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug)
   }
 
 }

src/main/scala/xiangshan/backend/fu/CSR.scala

 package xiangshan.backend.fu
 
 import chisel3._
-import chisel3.ExcitingUtils.ConnectionType
+import chisel3.ExcitingUtils.{ConnectionType, Debug}
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
 import fpu.Fflags
@@ -862,24 +862,24 @@ class CSR extends XSModule
 //    BoringUtils.addSource(RegNext(sepc), "difftestSepc")
 //    BoringUtils.addSource(RegNext(mcause), "difftestMcause")
 //    BoringUtils.addSource(RegNext(scause), "difftestScause")
-    BoringUtils.addSource(priviledgeMode, "difftestMode")
-    BoringUtils.addSource(mstatus, "difftestMstatus")
-    BoringUtils.addSource(mstatus & sstatusRmask, "difftestSstatus")
-    BoringUtils.addSource(mepc, "difftestMepc")
-    BoringUtils.addSource(sepc, "difftestSepc")
-    BoringUtils.addSource(mtval, "difftestMtval")
-    BoringUtils.addSource(stval, "difftestStval")
-    BoringUtils.addSource(mtvec, "difftestMtvec")
-    BoringUtils.addSource(stvec, "difftestStvec")
-    BoringUtils.addSource(mcause, "difftestMcause")
-    BoringUtils.addSource(scause, "difftestScause")
-    BoringUtils.addSource(satp, "difftestSatp")
-    BoringUtils.addSource(mipReg, "difftestMip")
-    BoringUtils.addSource(mie, "difftestMie")
-    BoringUtils.addSource(mscratch, "difftestMscratch")
-    BoringUtils.addSource(sscratch, "difftestSscratch")
-    BoringUtils.addSource(mideleg, "difftestMideleg")
-    BoringUtils.addSource(medeleg, "difftestMedeleg")
+    ExcitingUtils.addSource(priviledgeMode, "difftestMode", Debug)
+    ExcitingUtils.addSource(mstatus, "difftestMstatus", Debug)
+    ExcitingUtils.addSource(mstatus & sstatusRmask, "difftestSstatus", Debug)
+    ExcitingUtils.addSource(mepc, "difftestMepc", Debug)
+    ExcitingUtils.addSource(sepc, "difftestSepc", Debug)
+    ExcitingUtils.addSource(mtval, "difftestMtval", Debug)
+    ExcitingUtils.addSource(stval, "difftestStval", Debug)
+    ExcitingUtils.addSource(mtvec, "difftestMtvec", Debug)
+    ExcitingUtils.addSource(stvec, "difftestStvec", Debug)
+    ExcitingUtils.addSource(mcause, "difftestMcause", Debug)
+    ExcitingUtils.addSource(scause, "difftestScause", Debug)
+    ExcitingUtils.addSource(satp, "difftestSatp", Debug)
+    ExcitingUtils.addSource(mipReg, "difftestMip", Debug)
+    ExcitingUtils.addSource(mie, "difftestMie", Debug)
+    ExcitingUtils.addSource(mscratch, "difftestMscratch", Debug)
+    ExcitingUtils.addSource(sscratch, "difftestSscratch", Debug)
+    ExcitingUtils.addSource(mideleg, "difftestMideleg", Debug)
+    ExcitingUtils.addSource(medeleg, "difftestMedeleg", Debug)
   } else {
 //    BoringUtils.addSource(readWithScala(perfCntList("Minstret")._1), "ilaInstrCnt")
   }

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -390,19 +390,19 @@ class Roq extends XSModule with HasCircularQueuePtrHelper {
   val retirePCFix = SignExt(Mux(io.redirect.valid, microOp(deqPtr).cf.pc, microOp(firstValidCommit).cf.pc), XLEN)
   val retireInstFix = Mux(io.redirect.valid, microOp(deqPtr).cf.instr, microOp(firstValidCommit).cf.instr)
   if(!env.FPGAPlatform){
-    BoringUtils.addSource(RegNext(retireCounterFix), "difftestCommit")
-    BoringUtils.addSource(RegNext(retirePCFix), "difftestThisPC")//first valid PC
-    BoringUtils.addSource(RegNext(retireInstFix), "difftestThisINST")//first valid inst
-    BoringUtils.addSource(RegNext(skip.asUInt), "difftestSkip")
+    ExcitingUtils.addSource(RegNext(retireCounterFix), "difftestCommit", ExcitingUtils.Debug)
+    ExcitingUtils.addSource(RegNext(retirePCFix), "difftestThisPC", ExcitingUtils.Debug)//first valid PC
+    ExcitingUtils.addSource(RegNext(retireInstFix), "difftestThisINST", ExcitingUtils.Debug)//first valid inst
+    ExcitingUtils.addSource(RegNext(skip.asUInt), "difftestSkip", ExcitingUtils.Debug)
     // BoringUtils.addSource(RegNext(false.B), "difftestIsRVC")//FIXIT
-    BoringUtils.addSource(RegNext(isRVC.asUInt), "difftestIsRVC")
-    BoringUtils.addSource(RegNext(wen.asUInt), "difftestWen")
-    BoringUtils.addSource(RegNext(wpc), "difftestWpc")
-    BoringUtils.addSource(RegNext(wdata), "difftestWdata")
-    BoringUtils.addSource(RegNext(wdst), "difftestWdst")
-    BoringUtils.addSource(RegNext(scFailed), "difftestScFailed")
-    BoringUtils.addSource(RegNext(difftestIntrNO), "difftestIntrNO")
-    BoringUtils.addSource(RegNext(difftestCause), "difftestCause")
+    ExcitingUtils.addSource(RegNext(isRVC.asUInt), "difftestIsRVC", ExcitingUtils.Debug)
+    ExcitingUtils.addSource(RegNext(wen.asUInt), "difftestWen", ExcitingUtils.Debug)
+    ExcitingUtils.addSource(RegNext(wpc), "difftestWpc", ExcitingUtils.Debug)
+    ExcitingUtils.addSource(RegNext(wdata), "difftestWdata", ExcitingUtils.Debug)
+    ExcitingUtils.addSource(RegNext(wdst), "difftestWdst", ExcitingUtils.Debug)
+    ExcitingUtils.addSource(RegNext(scFailed), "difftestScFailed", ExcitingUtils.Debug)
+    ExcitingUtils.addSource(RegNext(difftestIntrNO), "difftestIntrNO", ExcitingUtils.Debug)
+    ExcitingUtils.addSource(RegNext(difftestCause), "difftestCause", ExcitingUtils.Debug)
 
     val hitTrap = trapVec.reduce(_||_)
     val trapCode = PriorityMux(wdata.zip(trapVec).map(x => x._2 -> x._1))

src/test/scala/top/XSSim.scala

@@ -3,7 +3,6 @@ package top
 import system._
 import chisel3._
 import chisel3.util._
-import chisel3.util.experimental.BoringUtils
 import chipsalliance.rocketchip.config
 import chisel3.stage.ChiselGeneratorAnnotation
 import device._
@@ -12,8 +11,7 @@ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, LazyModule, Laz
 import freechips.rocketchip.tilelink.{TLBuffer, TLCacheCork, TLFragmenter, TLFuzzer, TLToAXI4, TLXbar}
 import xiangshan._
 import utils._
-import firrtl.stage.RunFirrtlTransformAnnotation
-import xstransforms.ShowPrintTransform
+import ExcitingUtils.Debug
 
 class DiffTestIO extends XSBundle {
   val r = Output(Vec(64, UInt(XLEN.W)))
@@ -102,37 +100,37 @@ class XSSimTop()(implicit p: config.Parameters) extends LazyModule {
     soc.module.io.meip := false.B
 
     val difftest = WireInit(0.U.asTypeOf(new DiffTestIO))
-    BoringUtils.addSink(difftest.commit, "difftestCommit")
-    BoringUtils.addSink(difftest.thisPC, "difftestThisPC")
-    BoringUtils.addSink(difftest.thisINST, "difftestThisINST")
-    BoringUtils.addSink(difftest.skip, "difftestSkip")
-    BoringUtils.addSink(difftest.isRVC, "difftestIsRVC")
-    BoringUtils.addSink(difftest.wen, "difftestWen")
-    BoringUtils.addSink(difftest.wdata, "difftestWdata")
-    BoringUtils.addSink(difftest.wdst, "difftestWdst")
-    BoringUtils.addSink(difftest.wpc, "difftestWpc")
-    BoringUtils.addSink(difftest.intrNO, "difftestIntrNO")
-    BoringUtils.addSink(difftest.cause, "difftestCause")
-    BoringUtils.addSink(difftest.r, "difftestRegs")
-    BoringUtils.addSink(difftest.priviledgeMode, "difftestMode")
-    BoringUtils.addSink(difftest.mstatus, "difftestMstatus")
-    BoringUtils.addSink(difftest.sstatus, "difftestSstatus")
-    BoringUtils.addSink(difftest.mepc, "difftestMepc")
-    BoringUtils.addSink(difftest.sepc, "difftestSepc")
-    BoringUtils.addSink(difftest.mtval, "difftestMtval")
-    BoringUtils.addSink(difftest.stval, "difftestStval")
-    BoringUtils.addSink(difftest.mtvec, "difftestMtvec")
-    BoringUtils.addSink(difftest.stvec, "difftestStvec")
-    BoringUtils.addSink(difftest.mcause, "difftestMcause")
-    BoringUtils.addSink(difftest.scause, "difftestScause")
-    BoringUtils.addSink(difftest.satp, "difftestSatp")
-    BoringUtils.addSink(difftest.mip, "difftestMip")
-    BoringUtils.addSink(difftest.mie, "difftestMie")
-    BoringUtils.addSink(difftest.mscratch, "difftestMscratch")
-    BoringUtils.addSink(difftest.sscratch, "difftestSscratch")
-    BoringUtils.addSink(difftest.mideleg, "difftestMideleg")
-    BoringUtils.addSink(difftest.medeleg, "difftestMedeleg")
-    BoringUtils.addSink(difftest.scFailed, "difftestScFailed")
+    ExcitingUtils.addSink(difftest.commit, "difftestCommit", Debug)
+    ExcitingUtils.addSink(difftest.thisPC, "difftestThisPC", Debug)
+    ExcitingUtils.addSink(difftest.thisINST, "difftestThisINST", Debug)
+    ExcitingUtils.addSink(difftest.skip, "difftestSkip", Debug)
+    ExcitingUtils.addSink(difftest.isRVC, "difftestIsRVC", Debug)
+    ExcitingUtils.addSink(difftest.wen, "difftestWen", Debug)
+    ExcitingUtils.addSink(difftest.wdata, "difftestWdata", Debug)
+    ExcitingUtils.addSink(difftest.wdst, "difftestWdst", Debug)
+    ExcitingUtils.addSink(difftest.wpc, "difftestWpc", Debug)
+    ExcitingUtils.addSink(difftest.intrNO, "difftestIntrNO", Debug)
+    ExcitingUtils.addSink(difftest.cause, "difftestCause", Debug)
+    ExcitingUtils.addSink(difftest.r, "difftestRegs", Debug)
+    ExcitingUtils.addSink(difftest.priviledgeMode, "difftestMode", Debug)
+    ExcitingUtils.addSink(difftest.mstatus, "difftestMstatus", Debug)
+    ExcitingUtils.addSink(difftest.sstatus, "difftestSstatus", Debug)
+    ExcitingUtils.addSink(difftest.mepc, "difftestMepc", Debug)
+    ExcitingUtils.addSink(difftest.sepc, "difftestSepc", Debug)
+    ExcitingUtils.addSink(difftest.mtval, "difftestMtval", Debug)
+    ExcitingUtils.addSink(difftest.stval, "difftestStval", Debug)
+    ExcitingUtils.addSink(difftest.mtvec, "difftestMtvec", Debug)
+    ExcitingUtils.addSink(difftest.stvec, "difftestStvec", Debug)
+    ExcitingUtils.addSink(difftest.mcause, "difftestMcause", Debug)
+    ExcitingUtils.addSink(difftest.scause, "difftestScause", Debug)
+    ExcitingUtils.addSink(difftest.satp, "difftestSatp", Debug)
+    ExcitingUtils.addSink(difftest.mip, "difftestMip", Debug)
+    ExcitingUtils.addSink(difftest.mie, "difftestMie", Debug)
+    ExcitingUtils.addSink(difftest.mscratch, "difftestMscratch", Debug)
+    ExcitingUtils.addSink(difftest.sscratch, "difftestSscratch", Debug)
+    ExcitingUtils.addSink(difftest.mideleg, "difftestMideleg", Debug)
+    ExcitingUtils.addSink(difftest.medeleg, "difftestMedeleg", Debug)
+    ExcitingUtils.addSink(difftest.scFailed, "difftestScFailed", Debug)
     // BoringUtils.addSink(difftest.lrscAddr, "difftestLrscAddr")
     io.difftest := difftest