- 09 11月, 2022 1 次提交
-
-
由 Yinan Xu 提交于
* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq * ctrl: add data modules for pc and jalr_target This commit adds two data modules for pc and jalr_target respectively. They are the same as data modules in frontend. Should benefit timing. * jump: reduce pc and jalr_target read latency * ftq: add predecode redirect update target interface, valid only on ifuRedirect * ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>
-
- 08 11月, 2022 1 次提交
-
-
由 Steve Gou 提交于
and remove all bypass for ftq_pc_mem
-
- 18 7月, 2022 1 次提交
-
-
由 Yinan Xu 提交于
* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq * ctrl: add data modules for pc and jalr_target This commit adds two data modules for pc and jalr_target respectively. They are the same as data modules in frontend. Should benefit timing. * jump: reduce pc and jalr_target read latency * ftq: add predecode redirect update target interface, valid only on ifuRedirect * ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>
-
- 30 6月, 2022 1 次提交
-
-
由 Lingrui98 提交于
* add one cycle stall to ftb miss update, and * add one cycle delay to all other predictors
-
- 29 6月, 2022 2 次提交
- 09 6月, 2022 1 次提交
-
-
由 Steve Gou 提交于
last_may_be_rvi_call in case that a call comes after a taken branch
-
- 06 6月, 2022 1 次提交
-
-
由 Jenius 提交于
-
- 26 5月, 2022 1 次提交
-
-
由 Jiuyang Liu 提交于
-
- 31 3月, 2022 1 次提交
-
-
由 LinJiawei 提交于
-
- 14 2月, 2022 1 次提交
-
-
由 Steve Gou 提交于
-
- 03 2月, 2022 1 次提交
-
-
由 Steve Gou 提交于
-
- 23 1月, 2022 2 次提交
-
-
由 Lingrui98 提交于
ftb,ftq: add a bit indicating there is an rvi call at the last 2 byte for ras to push the right address
-
由 Jay 提交于
* IFU <timing>: f2_data select signal optimization * ICacheMainPipe <timing>: latch fetch req when tlb miss * Frontend <timing>: add additional PMP checker * Ftq <timing>: delete flush condition for prefetch.req * ICacheMainPipe <timing>: move hit state change to s2 * ICache <bug-fix> delete PMP check assertion * ICache <bug-fix> fix parity error condition * ICacheMainPipe <bug-fix>: fix tlb resp condition * when TLB req has been latched into tlb_slot, the tlb_all_resp condition, which affects s0_fire should depend on the slot result.
-
- 22 1月, 2022 2 次提交
- 18 1月, 2022 1 次提交
-
-
由 Lingrui98 提交于
-
- 17 1月, 2022 1 次提交
-
-
由 Lingrui98 提交于
-
- 14 1月, 2022 1 次提交
-
-
由 Lingrui98 提交于
-
- 08 1月, 2022 1 次提交
-
-
由 Lingrui98 提交于
-
- 04 1月, 2022 1 次提交
-
-
由 Lingrui98 提交于
-
- 01 1月, 2022 1 次提交
-
-
由 Lingrui98 提交于
* move statisical corrector to stage 3 * add recover path in stage 3 for ras in case stage 2 falsely push or pop * let stage 2 has the highest physical priority in bpu * left ras broken for the next commit to fix
-
- 30 12月, 2021 1 次提交
-
-
由 Lingrui98 提交于
* timing: use single ported SRAMs, invalidating read responses on write * performance: -- shortening history length to accelerate training -- use a predictor to reduce s2_redirects on FTB not hit
-
- 24 12月, 2021 1 次提交
-
-
由 Jay 提交于
* IPrefetch: fix prefetchPtr stop problem * This problem happens because prefetchPtr still exits when close IPrefetch * Fix PMP req port still be occupied even when ICache miss * Shut down IPrefetch * IPrefetch: fix Hint not set PreferCache bit * bump HuanCun
-
- 23 12月, 2021 3 次提交
- 22 12月, 2021 1 次提交
-
-
由 JinYue 提交于
* This problem happens because prefetchPtr still exits when close IPrefetch * Fix PMP req port still be occupied even when ICache miss
-
- 21 12月, 2021 1 次提交
-
-
由 Jay 提交于
* Add Naive Instruction Prefetch * Add instruction prefetch module in ICache * send Hint to L2 (prefetched data stores in L2) * Ftq: add prefetchPtr and prefetch interface * Fix IPrefetch PMP Port preempting problem * Fix merge conflict
-
- 20 12月, 2021 1 次提交
-
-
由 Li Qianruo 提交于
-
- 18 12月, 2021 2 次提交
- 17 12月, 2021 1 次提交
-
-
由 Lingrui98 提交于
-
- 11 12月, 2021 1 次提交
-
-
由 Yinan Xu 提交于
This commit adds DelayN(2) to some CSR-related signals, including control bits to ITLB, DTLB, PTW, etc. To avoid accessing the ITLB before control bits change, we also need to delay the flush for two cycles. We assume branch misprediction or memory violation does not cause csrCtrl to change.
-
- 10 12月, 2021 1 次提交
-
-
由 Yinan Xu 提交于
This commit optimizes the coding style and timing for hardware performance counters. By default, performance counters are RegNext(RegNext(_)).
-
- 08 12月, 2021 1 次提交
-
-
由 Lingrui98 提交于
-
- 03 12月, 2021 1 次提交
-
-
由 Lingrui98 提交于
* let ubtb store full targets and fall through addresses * add some fields in BranchPrediction so that ifu requests can be solely derived from it
-
- 26 11月, 2021 1 次提交
-
-
由 Lingrui98 提交于
* decouple fall through address calculating logic from the pftAddr interface * let ghr update from s1 has the highest priority * fix the physical priority of PhyPriorityMuxGenerator
-
- 25 11月, 2021 1 次提交
-
-
由 Lingrui98 提交于
-
- 18 11月, 2021 1 次提交
-
-
由 Lingrui98 提交于
-