bpu: read oldest bits one stage ahead

src/main/scala/xiangshan/Bundle.scala

@@ -40,6 +40,7 @@ import chisel3.util.BitPat.bitPatToUInt
 import xiangshan.backend.fu.PMPEntry
 import xiangshan.frontend.Ftq_Redirect_SRAMEntry
 import xiangshan.frontend.AllFoldedHistories
+import xiangshan.frontend.AllAheadFoldedHistoryOldestBits
 
 class ValidUndirectioned[T <: Data](gen: T) extends Bundle {
   val valid = Bool()
@@ -79,6 +80,8 @@ class CfiUpdateInfo(implicit p: Parameters) extends XSBundle with HasBPUParamete
   val rasEntry = new RASEntry
   // val hist = new ShiftingGlobalHistory
   val folded_hist = new AllFoldedHistories(foldedGHistInfos)
+  val afhob = new AllAheadFoldedHistoryOldestBits(foldedGHistInfos)
+  val lastBrNumOH = UInt((numBr+1).W)
   val ghr = UInt(UbtbGHRLength.W)
   val histPtr = new CGHPtr
   val specCnt = Vec(numBr, UInt(10.W))
@@ -94,6 +97,8 @@ class CfiUpdateInfo(implicit p: Parameters) extends XSBundle with HasBPUParamete
   def fromFtqRedirectSram(entry: Ftq_Redirect_SRAMEntry) = {
     // this.hist := entry.ghist
     this.folded_hist := entry.folded_hist
+    this.lastBrNumOH := entry.lastBrNumOH
+    this.afhob := entry.afhob
     this.histPtr := entry.histPtr
     this.rasSp := entry.rasSp
     this.rasEntry := entry.rasEntry

src/main/scala/xiangshan/frontend/BPU.scala

@@ -139,35 +139,6 @@ trait BPUUtils extends HasXSParameter {
 //   def taken = cfi_idx.valid
 // }
 
-class AllFoldedHistories(val gen: Seq[Tuple2[Int, Int]])(implicit p: Parameters) extends XSBundle with HasBPUConst {
-  val hist = MixedVec(gen.map{case (l, cl) => new FoldedHistory(l, cl, numBr)})
-  // println(gen.mkString)
-  require(gen.toSet.toList.equals(gen))
-  def getHistWithInfo(info: Tuple2[Int, Int]) = {
-    val selected = hist.filter(_.info.equals(info))
-    require(selected.length == 1)
-    selected(0)
-  }
-  def autoConnectFrom(that: AllFoldedHistories) = {
-    require(this.hist.length <= that.hist.length)
-    for (h <- this.hist) {
-      h := that.getHistWithInfo(h.info)
-    }
-  }
-  def update(ghv: Vec[Bool], ptr: CGHPtr, shift: Int, taken: Bool): AllFoldedHistories = {
-    val res = WireInit(this)
-    for (i <- 0 until this.hist.length) {
-      res.hist(i) := this.hist(i).update(ghv, ptr, shift, taken)
-    }
-    res
-  }
-
-  def display(cond: Bool) = {
-    for (h <- hist) {
-      XSDebug(cond, p"hist len ${h.len}, folded len ${h.compLen}, value ${Binary(h.folded_hist)}\n")
-    }
-  }
-}
 
 class BasePredictorInput (implicit p: Parameters) extends XSBundle with HasBPUConst {
   def nInputs = 1
@@ -293,9 +264,24 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   val s2_folded_gh = RegEnable(s1_folded_gh, 0.U.asTypeOf(s0_folded_gh), s1_fire)
   val s3_folded_gh = RegEnable(s2_folded_gh, 0.U.asTypeOf(s0_folded_gh), s2_fire)
 
+  val s0_last_br_num_oh = Wire(UInt((numBr+1).W))
+  val s0_last_br_num_oh_reg = RegNext(s0_last_br_num_oh, init=0.U)
+  val s1_last_br_num_oh = RegEnable(s0_last_br_num_oh, 0.U, s0_fire)
+  val s2_last_br_num_oh = RegEnable(s1_last_br_num_oh, 0.U, s1_fire)
+  val s3_last_br_num_oh = RegEnable(s2_last_br_num_oh, 0.U, s2_fire)
+
+  val s0_ahead_fh_oldest_bits = Wire(new AllAheadFoldedHistoryOldestBits(foldedGHistInfos))
+  val s0_ahead_fh_oldest_bits_reg = RegNext(s0_ahead_fh_oldest_bits, init=0.U.asTypeOf(s0_ahead_fh_oldest_bits))
+  val s1_ahead_fh_oldest_bits = RegEnable(s0_ahead_fh_oldest_bits, 0.U.asTypeOf(s0_ahead_fh_oldest_bits), s0_fire)
+  val s2_ahead_fh_oldest_bits = RegEnable(s1_ahead_fh_oldest_bits, 0.U.asTypeOf(s0_ahead_fh_oldest_bits), s1_fire)
+  val s3_ahead_fh_oldest_bits = RegEnable(s2_ahead_fh_oldest_bits, 0.U.asTypeOf(s0_ahead_fh_oldest_bits), s2_fire)
+
   val npcGen   = new PhyPriorityMuxGenerator[UInt]
   val foldedGhGen = new PhyPriorityMuxGenerator[AllFoldedHistories]
   val ghistPtrGen = new PhyPriorityMuxGenerator[CGHPtr]
+  val lastBrNumOHGen = new PhyPriorityMuxGenerator[UInt]
+  val aheadFhObGen = new PhyPriorityMuxGenerator[AllAheadFoldedHistoryOldestBits]
+
   val ghvBitWriteGens = Seq.tabulate(HistoryLength)(n => new PhyPriorityMuxGenerator[Bool])
   // val ghistGen = new PhyPriorityMuxGenerator[UInt]
 
@@ -394,10 +380,14 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   io.bpu_to_ftq.resp.bits.meta  := predictors.io.out.last_stage_meta // TODO: change to lastStageMeta
   io.bpu_to_ftq.resp.bits.s3.folded_hist := s3_folded_gh
   io.bpu_to_ftq.resp.bits.s3.histPtr := s3_ghist_ptr
+  io.bpu_to_ftq.resp.bits.s3.lastBrNumOH := s3_last_br_num_oh
+  io.bpu_to_ftq.resp.bits.s3.afhob := s3_ahead_fh_oldest_bits
 
   npcGen.register(true.B, s0_pc_reg, Some("stallPC"), 0)
   foldedGhGen.register(true.B, s0_folded_gh_reg, Some("stallFGH"), 0)
   ghistPtrGen.register(true.B, s0_ghist_ptr_reg, Some("stallGHPtr"), 0)
+  lastBrNumOHGen.register(true.B, s0_last_br_num_oh_reg, Some("stallBrNumOH"), 0)
+  aheadFhObGen.register(true.B, s0_ahead_fh_oldest_bits_reg, Some("stallAFHOB"), 0)
 
   // History manage
   // s1
@@ -405,9 +395,12 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   val s1_predicted_ghist_ptr = Mux1H(resp.s1.lastBrPosOH, s1_possible_predicted_ghist_ptrs)
 
   val s1_possible_predicted_fhs = (0 to numBr).map(i =>
-    s1_folded_gh.update(ghv, s1_ghist_ptr, i, resp.s1.brTaken && resp.s1.lastBrPosOH(i)))
+    s1_folded_gh.update(s1_ahead_fh_oldest_bits, s1_last_br_num_oh, i, resp.s1.brTaken && resp.s1.lastBrPosOH(i)))
   val s1_predicted_fh = Mux1H(resp.s1.lastBrPosOH, s1_possible_predicted_fhs)
 
+  val s1_ahead_fh_ob_src = Wire(new AllAheadFoldedHistoryOldestBits(foldedGHistInfos))
+  s1_ahead_fh_ob_src.read(ghv, s1_ghist_ptr)
+
   if (EnableGHistDiff) {
     val s1_predicted_ghist = WireInit(getHist(s1_predicted_ghist_ptr).asTypeOf(Vec(HistoryLength, Bool())))
     for (i <- 0 until numBr) {
@@ -437,6 +430,8 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   npcGen.register(s1_valid, resp.s1.getTarget, Some("s1_target"), 4)
   foldedGhGen.register(s1_valid, s1_predicted_fh, Some("s1_FGH"), 4)
   ghistPtrGen.register(s1_valid, s1_predicted_ghist_ptr, Some("s1_GHPtr"), 4)
+  lastBrNumOHGen.register(s1_valid, resp.s1.lastBrPosOH.asUInt, Some("s1_BrNumOH"), 4)
+  aheadFhObGen.register(s1_valid, s1_ahead_fh_ob_src, Some("s1_AFHOB"), 4)
   ghvBitWriteGens.zip(s1_ghv_wens).zipWithIndex.map{case ((b, w), i) =>
     b.register(w.reduce(_||_), s1_ghv_wdatas(i), Some(s"s1_new_bit_$i"), 4)
   }
@@ -458,9 +453,12 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   val s2_predicted_ghist_ptr = Mux1H(resp.s2.lastBrPosOH, s2_possible_predicted_ghist_ptrs)
 
   val s2_possible_predicted_fhs = (0 to numBr).map(i =>
-    s2_folded_gh.update(ghv, s2_ghist_ptr, i, if (i > 0) resp.s2.full_pred.br_taken_mask(i-1) else false.B))
+    s2_folded_gh.update(s2_ahead_fh_oldest_bits, s2_last_br_num_oh, i, if (i > 0) resp.s2.full_pred.br_taken_mask(i-1) else false.B))
   val s2_predicted_fh = Mux1H(resp.s2.lastBrPosOH, s2_possible_predicted_fhs)
 
+  val s2_ahead_fh_ob_src = Wire(new AllAheadFoldedHistoryOldestBits(foldedGHistInfos))
+  s2_ahead_fh_ob_src.read(ghv, s2_ghist_ptr)
+
   if (EnableGHistDiff) {
     val s2_predicted_ghist = WireInit(getHist(s2_predicted_ghist_ptr).asTypeOf(Vec(HistoryLength, Bool())))
     for (i <- 0 until numBr) {
@@ -495,6 +493,8 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   npcGen.register(s2_redirect, resp.s2.getTarget, Some("s2_target"), 5)
   foldedGhGen.register(s2_redirect, s2_predicted_fh, Some("s2_FGH"), 5)
   ghistPtrGen.register(s2_redirect, s2_predicted_ghist_ptr, Some("s2_GHPtr"), 5)
+  lastBrNumOHGen.register(s2_redirect, resp.s2.lastBrPosOH.asUInt, Some("s2_BrNumOH"), 5)
+  aheadFhObGen.register(s2_redirect, s2_ahead_fh_ob_src, Some("s2_AFHOB"), 5)
   ghvBitWriteGens.zip(s2_ghv_wens).zipWithIndex.map{case ((b, w), i) =>
     b.register(w.reduce(_||_), s2_ghv_wdatas(i), Some(s"s2_new_bit_$i"), 5)
   }
@@ -517,9 +517,12 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   val s3_predicted_ghist_ptr = Mux1H(resp.s3.lastBrPosOH, s3_possible_predicted_ghist_ptrs)
 
   val s3_possible_predicted_fhs = (0 to numBr).map(i =>
-    s3_folded_gh.update(ghv, s3_ghist_ptr, i, if (i > 0) resp.s3.full_pred.br_taken_mask(i-1) else false.B))
+    s3_folded_gh.update(s3_ahead_fh_oldest_bits, s3_last_br_num_oh, i, if (i > 0) resp.s3.full_pred.br_taken_mask(i-1) else false.B))
   val s3_predicted_fh = Mux1H(resp.s3.lastBrPosOH, s3_possible_predicted_fhs)
 
+  val s3_ahead_fh_ob_src = Wire(new AllAheadFoldedHistoryOldestBits(foldedGHistInfos))
+  s3_ahead_fh_ob_src.read(ghv, s3_ghist_ptr)
+
   if (EnableGHistDiff) {
     val s3_predicted_ghist = WireInit(getHist(s3_predicted_ghist_ptr).asTypeOf(Vec(HistoryLength, Bool())))
     for (i <- 0 until numBr) {
@@ -556,6 +559,8 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   npcGen.register(s3_redirect, resp.s3.getTarget, Some("s3_target"), 3)
   foldedGhGen.register(s3_redirect, s3_predicted_fh, Some("s3_FGH"), 3)
   ghistPtrGen.register(s3_redirect, s3_predicted_ghist_ptr, Some("s3_GHPtr"), 3)
+  lastBrNumOHGen.register(s3_redirect, resp.s3.lastBrPosOH.asUInt, Some("s3_BrNumOH"), 3)
+  aheadFhObGen.register(s3_redirect, s3_ahead_fh_ob_src, Some("s3_AFHOB"), 3)
   ghvBitWriteGens.zip(s3_ghv_wens).zipWithIndex.map{case ((b, w), i) =>
     b.register(w.reduce(_||_), s3_ghv_wdatas(i), Some(s"s3_new_bit_$i"), 3)
   }
@@ -586,7 +591,10 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   // TODO: remove these below
   val shouldShiftVec = Mux(shift === 0.U, VecInit(0.U((1 << (log2Ceil(numBr) + 1)).W).asBools), VecInit((LowerMask(1.U << (shift-1.U))).asBools()))
   // TODO end
-  
+  val afhob = redirect.cfiUpdate.afhob
+  val lastBrNumOH = redirect.cfiUpdate.lastBrNumOH
+
+
   val isBr = redirect.cfiUpdate.pd.isBr
   val taken = redirect.cfiUpdate.taken
   val real_br_taken_mask = (0 until numBr).map(i => shift === (i+1).U && taken && addIntoHist )
@@ -594,7 +602,10 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   val oldPtr = redirect.cfiUpdate.histPtr
   val oldFh = redirect.cfiUpdate.folded_hist
   val updated_ptr = oldPtr - shift
-  val updated_fh = VecInit((0 to numBr).map(i => oldFh.update(ghv, oldPtr, i, taken && addIntoHist)))(shift)
+  val updated_fh = VecInit((0 to numBr).map(i => oldFh.update(afhob, lastBrNumOH, i, taken && addIntoHist)))(shift)
+  val thisBrNumOH = UIntToOH(shift, numBr+1)
+  val thisAheadFhOb = Wire(new AllAheadFoldedHistoryOldestBits(foldedGHistInfos))
+  thisAheadFhOb.read(ghv, oldPtr)
   val redirect_ghv_wens = (0 until HistoryLength).map(n =>
     (0 until numBr).map(b => oldPtr.value === (n.U(log2Ceil(HistoryLength).W) + b.U) && shouldShiftVec(b) && do_redirect.valid))
   val redirect_ghv_wdatas = (0 until HistoryLength).map(n =>
@@ -622,22 +633,26 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   npcGen.register(do_redirect.valid, do_redirect.bits.cfiUpdate.target, Some("redirect_target"), 2)
   foldedGhGen.register(do_redirect.valid, updated_fh, Some("redirect_FGHT"), 2)
   ghistPtrGen.register(do_redirect.valid, updated_ptr, Some("redirect_GHPtr"), 2)
+  lastBrNumOHGen.register(do_redirect.valid, thisBrNumOH, Some("redirect_BrNumOH"), 2)
+  aheadFhObGen.register(do_redirect.valid, thisAheadFhOb, Some("redirect_AFHOB"), 2)
   ghvBitWriteGens.zip(redirect_ghv_wens).zipWithIndex.map{case ((b, w), i) =>
     b.register(w.reduce(_||_), redirect_ghv_wdatas(i), Some(s"redirect_new_bit_$i"), 2)
   }
   // no need to assign s0_last_pred
 
-  val need_reset = RegNext(reset.asBool) && !reset.asBool
+  // val need_reset = RegNext(reset.asBool) && !reset.asBool
 
   // Reset
-  npcGen.register(need_reset, resetVector.U, Some("reset_pc"), 1)
-  foldedGhGen.register(need_reset, 0.U.asTypeOf(s0_folded_gh), Some("reset_FGH"), 1)
-  ghistPtrGen.register(need_reset, 0.U.asTypeOf(new CGHPtr), Some("reset_GHPtr"), 1)
+  // npcGen.register(need_reset, resetVector.U, Some("reset_pc"), 1)
+  // foldedGhGen.register(need_reset, 0.U.asTypeOf(s0_folded_gh), Some("reset_FGH"), 1)
+  // ghistPtrGen.register(need_reset, 0.U.asTypeOf(new CGHPtr), Some("reset_GHPtr"), 1)
 
   s0_pc         := npcGen()
   s0_pc_reg     := s0_pc
   s0_folded_gh  := foldedGhGen()
   s0_ghist_ptr  := ghistPtrGen()
+  s0_ahead_fh_oldest_bits := aheadFhObGen()
+  s0_last_br_num_oh := lastBrNumOHGen()
   (ghv_write_datas zip ghvBitWriteGens).map{case (wd, d) => wd := d()}
   for (i <- 0 until HistoryLength) {
     ghv_wens(i) := Seq(s1_ghv_wens, s2_ghv_wens, s3_ghv_wens, redirect_ghv_wens).map(_(i).reduce(_||_)).reduce(_||_)

src/main/scala/xiangshan/frontend/FrontendBundle.scala

@@ -163,6 +163,7 @@ class FoldedHistory(val len: Int, val compLen: Int, val max_update_num: Int)(imp
   require(compLen >= max_update_num)
   val folded_hist = UInt(compLen.W)
 
+  def need_oldest_bits = len > compLen
   def info = (len, compLen)
   def oldest_bit_to_get_from_ghr = (0 until max_update_num).map(len - _ - 1)
   def oldest_bit_pos_in_folded = oldest_bit_to_get_from_ghr map (_ % compLen)
@@ -181,8 +182,15 @@ class FoldedHistory(val len: Int, val compLen: Int, val max_update_num: Int)(imp
     shifted
   }
 
-
+  // slow path, read bits from ghr
   def update(ghr: Vec[Bool], histPtr: CGHPtr, num: Int, taken: Bool): FoldedHistory = {
+    val oldest_bits = VecInit(get_oldest_bits_from_ghr(ghr, histPtr))
+    update(oldest_bits, num, taken)
+  }
+
+
+  // fast path, use pre-read oldest bits
+  def update(ob: Vec[Bool], num: Int, taken: Bool): FoldedHistory = {
     // do xors for several bitsets at specified bits
     def bitsets_xor(len: Int, bitsets: Seq[Seq[Tuple2[Int, Bool]]]) = {
       val res = Wire(Vec(len, Bool()))
@@ -209,43 +217,125 @@ class FoldedHistory(val len: Int, val compLen: Int, val max_update_num: Int)(imp
       }
       res.asUInt
     }
-    val oldest_bits = get_oldest_bits_from_ghr(ghr, histPtr)
 
-    // mask off bits that do not update
-    val oldest_bits_masked = oldest_bits.zipWithIndex.map{
-      case (ob, i) => ob && (i < num).B
+    val new_folded_hist = if (need_oldest_bits) {
+      val oldest_bits = ob
+      require(oldest_bits.length == max_update_num)
+      // mask off bits that do not update
+      val oldest_bits_masked = oldest_bits.zipWithIndex.map{
+        case (ob, i) => ob && (i < num).B
+      }
+      // if a bit does not wrap around, it should not be xored when it exits
+      val oldest_bits_set = (0 until max_update_num).filter(oldest_bit_wrap_around).map(i => (oldest_bit_pos_in_folded(i), oldest_bits_masked(i)))
+      
+      // println(f"old bits pos ${oldest_bits_set.map(_._1)}")
+  
+      // only the last bit could be 1, as we have at most one taken branch at a time
+      val newest_bits_masked = VecInit((0 until max_update_num).map(i => taken && ((i+1) == num).B)).asUInt
+      // if a bit does not wrap around, newest bits should not be xored onto it either
+      val newest_bits_set = (0 until max_update_num).map(i => (compLen-1-i, newest_bits_masked(i)))
+  
+      // println(f"new bits set ${newest_bits_set.map(_._1)}")
+      //
+      val original_bits_masked = VecInit(folded_hist.asBools.zipWithIndex.map{
+        case (fb, i) => fb && !(num >= (len-i)).B
+      })
+      val original_bits_set = (0 until compLen).map(i => (i, original_bits_masked(i)))
+
+      // do xor then shift
+      val xored = bitsets_xor(compLen, Seq(original_bits_set, oldest_bits_set, newest_bits_set))
+      circular_shift_left(xored, num)
+    } else {
+      // histLen too short to wrap around
+      ((folded_hist << num) | taken)(compLen-1,0)
     }
-    // if a bit does not wrap around, it should not be xored when it exits
-    val oldest_bits_set = (0 until max_update_num).filter(oldest_bit_wrap_around).map(i => (oldest_bit_pos_in_folded(i), oldest_bits_masked(i)))
-    
-    // println(f"old bits pos ${oldest_bits_set.map(_._1)}")
 
-    // only the last bit could be 1, as we have at most one taken branch at a time
-    val newest_bits_masked = VecInit((0 until max_update_num).map(i => taken && ((i+1) == num).B)).asUInt
-    // if a bit does not wrap around, newest bits should not be xored onto it either
-    val newest_bits_set = (0 until max_update_num).map(i => (compLen-1-i, newest_bits_masked(i)))
+    val fh = WireInit(this)
+    fh.folded_hist := new_folded_hist
+    fh
+  }
+}
 
-    // println(f"new bits set ${newest_bits_set.map(_._1)}")
-    //
-    val original_bits_masked = VecInit(folded_hist.asBools.zipWithIndex.map{
-      case (fb, i) => fb && !(num >= (len-i)).B
-    })
-    val original_bits_set = (0 until compLen).map(i => (i, original_bits_masked(i)))
+class AheadFoldedHistoryOldestBits(val len: Int, val max_update_num: Int)(implicit p: Parameters) extends XSBundle {
+  val bits = Vec(max_update_num*2, Bool())
+  // def info = (len, compLen)
+  def getRealOb(brNumOH: UInt): Vec[Bool] = {
+    val ob = Wire(Vec(max_update_num, Bool()))
+    for (i <- 0 until max_update_num) {
+      ob(i) := Mux1H(brNumOH, bits.drop(i).take(numBr+1))
+    }
+    ob
+  }
+}
 
-    
-    // histLen too short to wrap around
-    val new_folded_hist =
-      if (len <= compLen) {
-        ((folded_hist << num) | taken)(compLen-1,0)
-        // circular_shift_left(max_update_num)(Cat(Reverse(newest_bits_masked), folded_hist(compLen-max_update_num-1,0)), num)
+class AllAheadFoldedHistoryOldestBits(val gen: Seq[Tuple2[Int, Int]])(implicit p: Parameters) extends XSBundle with HasBPUConst {
+  val afhob = MixedVec(gen.filter(t => t._1 > t._2).map{_._1}
+    .toSet.toList.map(l => new AheadFoldedHistoryOldestBits(l, numBr))) // remove duplicates
+  require(gen.toSet.toList.equals(gen))
+  def getObWithInfo(info: Tuple2[Int, Int]) = {
+    val selected = afhob.filter(_.len == info._1)
+    require(selected.length == 1)
+    selected(0)
+  }
+  def read(ghv: Vec[Bool], ptr: CGHPtr) = {
+    val hisLens = afhob.map(_.len)
+    val bitsToRead = hisLens.flatMap(l => (0 until numBr*2).map(i => l-i-1)).toSet // remove duplicates
+    val bitsWithInfo = bitsToRead.map(pos => (pos, ghv((ptr+(pos+1).U).value)))
+    for (ob <- afhob) {
+      for (i <- 0 until numBr*2) {
+        val pos = ob.len - i - 1
+        val bit_found = bitsWithInfo.filter(_._1 == pos).toList
+        require(bit_found.length == 1)
+        ob.bits(i) := bit_found(0)._2
+      }
+    }
+  }
+}
+
+class AllFoldedHistories(val gen: Seq[Tuple2[Int, Int]])(implicit p: Parameters) extends XSBundle with HasBPUConst {
+  val hist = MixedVec(gen.map{case (l, cl) => new FoldedHistory(l, cl, numBr)})
+  // println(gen.mkString)
+  require(gen.toSet.toList.equals(gen))
+  def getHistWithInfo(info: Tuple2[Int, Int]) = {
+    val selected = hist.filter(_.info.equals(info))
+    require(selected.length == 1)
+    selected(0)
+  }
+  def autoConnectFrom(that: AllFoldedHistories) = {
+    require(this.hist.length <= that.hist.length)
+    for (h <- this.hist) {
+      h := that.getHistWithInfo(h.info)
+    }
+  }
+  def update(ghv: Vec[Bool], ptr: CGHPtr, shift: Int, taken: Bool): AllFoldedHistories = {
+    val res = WireInit(this)
+    for (i <- 0 until this.hist.length) {
+      res.hist(i) := this.hist(i).update(ghv, ptr, shift, taken)
+    }
+    res
+  }
+  def update(afhob: AllAheadFoldedHistoryOldestBits, lastBrNumOH: UInt, shift: Int, taken: Bool): AllFoldedHistories = {
+    val res = WireInit(this)
+    for (i <- 0 until this.hist.length) {
+      val fh = this.hist(i)
+      if (fh.need_oldest_bits) {
+        val info = fh.info
+        val selectedAfhob = afhob.getObWithInfo(info)
+        val ob = selectedAfhob.getRealOb(lastBrNumOH)
+        res.hist(i) := this.hist(i).update(ob, shift, taken)
       } else {
-        // do xor then shift
-        val xored = bitsets_xor(compLen, Seq(original_bits_set, oldest_bits_set, newest_bits_set))
-        circular_shift_left(xored, num)
+        val dumb = Wire(Vec(numBr, Bool())) // not needed
+        dumb := DontCare
+        res.hist(i) := this.hist(i).update(dumb, shift, taken)
       }
-    val fh = WireInit(this)
-    fh.folded_hist := new_folded_hist
-    fh
+    }
+    res
+  }
+
+  def display(cond: Bool) = {
+    for (h <- hist) {
+      XSDebug(cond, p"hist len ${h.len}, folded len ${h.compLen}, value ${Binary(h.folded_hist)}\n")
+    }
   }
 }
 
@@ -434,6 +524,8 @@ class BranchPredictionBundle(implicit p: Parameters) extends XSBundle
 
 
   val folded_hist = new AllFoldedHistories(foldedGHistInfos)
+  val afhob = new AllAheadFoldedHistoryOldestBits(foldedGHistInfos)
+  val lastBrNumOH = UInt((numBr+1).W)
   val histPtr = new CGHPtr
   val rasSp = UInt(log2Ceil(RasSize).W)
   val rasTop = new RASEntry
@@ -516,6 +608,8 @@ class BranchPredictionUpdate(implicit p: Parameters) extends BranchPredictionBun
 
   def fromFtqRedirectSram(entry: Ftq_Redirect_SRAMEntry) = {
     folded_hist := entry.folded_hist
+    afhob := entry.afhob
+    lastBrNumOH := entry.lastBrNumOH
     histPtr := entry.histPtr
     rasSp := entry.rasSp
     rasTop := entry.rasEntry

src/main/scala/xiangshan/frontend/NewFtq.scala

@@ -139,6 +139,9 @@ class Ftq_Redirect_SRAMEntry(implicit p: Parameters) extends XSBundle with HasBP
   // val specCnt = Vec(numBr, UInt(10.W))
   // val ghist = new ShiftingGlobalHistory
   val folded_hist = new AllFoldedHistories(foldedGHistInfos)
+  val afhob = new AllAheadFoldedHistoryOldestBits(foldedGHistInfos)
+  val lastBrNumOH = UInt((numBr+1).W)
+
   val histPtr = new CGHPtr
 
   def fromBranchPrediction(resp: BranchPredictionBundle) = {
@@ -146,6 +149,8 @@ class Ftq_Redirect_SRAMEntry(implicit p: Parameters) extends XSBundle with HasBP
     this.rasSp := resp.rasSp
     this.rasEntry := resp.rasTop
     this.folded_hist := resp.folded_hist
+    this.afhob := resp.afhob
+    this.lastBrNumOH := resp.lastBrNumOH
     this.histPtr := resp.histPtr
     this
   }