datamodule: add per-read-port bypass enable bit (#1635)

and remove all bypass for ftq_pc_mem

src/main/scala/xiangshan/frontend/NewFtq.scala

@@ -455,7 +455,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   val bpu_in_resp_idx = bpu_in_resp_ptr.value
 
   // read ports:                                                ifuReq1 + ifuReq2 + commitUpdate
-  val ftq_pc_mem = Module(new SyncDataModuleTemplate(new Ftq_RF_Components, FtqSize, 3, 1))
+  val ftq_pc_mem = Module(new SyncDataModuleTemplate(new Ftq_RF_Components, FtqSize, 3, 1, "FtqPC",
+    concatData=false, Some(Seq.tabulate(3)(i => false))))
   // resp from uBTB
   ftq_pc_mem.io.wen(0) := bpu_in_fire
   ftq_pc_mem.io.waddr(0) := bpu_in_resp_idx