IPrefetch: fix prefetchPtr stop problem (#1387)

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

huancun @ b9f402bc

-Subproject commit 8d99898ff754dbdee5bc064f14baff0d29db650f
+Subproject commit b9f402bc6dfddb21bad3a70c828cdd67b5fefb84

src/main/scala/xiangshan/Parameters.scala

@@ -219,7 +219,7 @@ case class XSCoreParameters
     nReleaseEntries = 2,
     nProbeEntries = 2,
     nPrefetchEntries = 4,
-    hasPrefetch = true,
+    hasPrefetch = false,
   ),
   dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters(
     tagECC = Some("secded"),

src/main/scala/xiangshan/frontend/NewFtq.scala

@@ -21,6 +21,7 @@ import chisel3._
 import chisel3.util._
 import utils._
 import xiangshan._
+import xiangshan.frontend.icache._
 import xiangshan.backend.CtrlToFtqIO
 
 class FtqPtr(implicit p: Parameters) extends CircularQueuePtr[FtqPtr](
@@ -416,7 +417,8 @@ class FTBEntryGen(implicit p: Parameters) extends XSModule with HasBackendRedire
 }
 
 class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper
-  with HasBackendRedirectInfo with BPUUtils with HasBPUConst with HasPerfEvents {
+  with HasBackendRedirectInfo with BPUUtils with HasBPUConst with HasPerfEvents 
+  with HasICacheParameters{
   val io = IO(new Bundle {
     val fromBpu = Flipped(new BpuToFtqIO)
     val fromIfu = Flipped(new IfuToFtqIO)
@@ -449,7 +451,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   allowBpuIn := !ifuFlush && !backendRedirect.valid && !backendRedirectReg.valid
   allowToIfu := !ifuFlush && !backendRedirect.valid && !backendRedirectReg.valid
 
-  val bpuPtr, ifuPtr, ifuWbPtr, commPtr, prefetchPtr = RegInit(FtqPtr(false.B, 0.U))
+  val bpuPtr, ifuPtr, ifuWbPtr, commPtr = RegInit(FtqPtr(false.B, 0.U))
   val validEntries = distanceBetween(bpuPtr, commPtr)
 
   // **********************************************************************
@@ -527,7 +529,6 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
 
   bpuPtr := bpuPtr + enq_fire
   ifuPtr := ifuPtr + io.toIfu.req.fire
-  prefetchPtr := prefetchPtr + io.toPrefetch.req.fire()
 
   // only use ftb result to assign hit status
   when (bpu_s2_resp.valid) {
@@ -543,10 +544,6 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     when (!isBefore(ifuPtr, bpu_s2_resp.ftq_idx)) {
       ifuPtr := bpu_s2_resp.ftq_idx
     }
-
-    when (!isBefore(prefetchPtr, bpu_s2_resp.ftq_idx)) {
-      prefetchPtr := bpu_s2_resp.ftq_idx
-    }
   }
 
   // io.toIfu.flushFromBpu.s3.valid := bpu_s3_redirect
@@ -561,7 +558,6 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   // }
 
   XSError(isBefore(bpuPtr, ifuPtr) && !isFull(bpuPtr, ifuPtr), "\nifuPtr is before bpuPtr!\n")
-  XSError(isBefore(bpuPtr, prefetchPtr) && !isFull(bpuPtr, prefetchPtr), "\nprefetchPtr is before bpuPtr!\n")
 
   // ****************************************************************
   // **************************** to ifu ****************************
@@ -612,9 +608,6 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
       entry_fetch_status(ifuPtr.value) := f_sent
     }
     
-  io.toPrefetch.req.valid := allowToIfu && prefetchPtr =/= bpuPtr && entry_fetch_status(prefetchPtr.value) === f_to_send
-  io.toPrefetch.req.bits.target := update_target(prefetchPtr.value)
-
   // *********************************************************************
   // **************************** wb from ifu ****************************
   // *********************************************************************
@@ -811,7 +804,6 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     val next = idx + 1.U
     bpuPtr := next
     ifuPtr := next
-    prefetchPtr := next
     ifuWbPtr := next
     when (notIfu) {
       commitStateQueue(idx.value).zipWithIndex.foreach({ case (s, i) =>
@@ -929,6 +921,33 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     update.full_pred.targets.last := commit_target
   }
 
+  // ****************************************************************
+  // *********************** to prefetch ****************************
+  // ****************************************************************
+
+  if(cacheParams.hasPrefetch){
+    val prefetchPtr = RegInit(FtqPtr(false.B, 0.U))
+    prefetchPtr := prefetchPtr + io.toPrefetch.req.fire()
+
+    when (bpu_s2_resp.valid && bpu_s2_resp.hasRedirect && !isBefore(prefetchPtr, bpu_s2_resp.ftq_idx)) {
+      prefetchPtr := bpu_s2_resp.ftq_idx
+    }
+
+    io.toPrefetch.req.valid := allowToIfu && prefetchPtr =/= bpuPtr && entry_fetch_status(prefetchPtr.value) === f_to_send
+    io.toPrefetch.req.bits.target := update_target(prefetchPtr.value)
+
+    when(redirectVec.map(r => r.valid).reduce(_||_)){
+      val r = PriorityMux(redirectVec.map(r => (r.valid -> r.bits)))
+      val next = r.ftqIdx + 1.U
+      prefetchPtr := next
+    }
+
+    XSError(isBefore(bpuPtr, prefetchPtr) && !isFull(bpuPtr, prefetchPtr), "\nprefetchPtr is before bpuPtr!\n")
+  }
+  else {
+    io.toPrefetch.req <> DontCare
+  }
+
   // ******************************************************************************
   // **************************** commit perf counters ****************************
   // ******************************************************************************

src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala

@@ -338,7 +338,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
 
   //send physical address to PMP
   io.pmp.zipWithIndex.map { case (p, i) =>
-    p.req.valid := s2_valid
+    p.req.valid := s2_valid && !missSwitchBit
     p.req.bits.addr := s2_req_paddr(i)
     p.req.bits.size := 3.U // TODO
     p.req.bits.cmd := TlbCmd.exec

src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala

@@ -317,7 +317,7 @@ class ICacheMissUnit(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheMiss
 
   val alloc = Wire(UInt(log2Ceil(nPrefetchEntries).W))
 
-  val prefEntries = (PortNumber until PortNumber + nPrefetchEntries - 1) map { i =>
+  val prefEntries = (PortNumber until PortNumber + nPrefetchEntries) map { i =>
     val prefetchEntry = Module(new IPrefetchEntry(edge, PortNumber))
 
     prefetchEntry.io.mem_hint_ack.valid := false.B
@@ -327,12 +327,8 @@ class ICacheMissUnit(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheMiss
       prefetchEntry.io.mem_hint_ack <> io.mem_grant
     }
 
-    prefetchEntry.io.req <> DontCare
-
-    when(i.U === alloc){
-      prefetchEntry.io.req.valid := io.prefetch_req.valid
-      prefetchEntry.io.req.bits  := io.prefetch_req.bits
-    }
+    prefetchEntry.io.req.valid := io.prefetch_req.valid && ((i-PortNumber).U === alloc)
+    prefetchEntry.io.req.bits  := io.prefetch_req.bits
 
     prefetchEntry.io.id := i.U
 

src/main/scala/xiangshan/frontend/icache/IPrefetch.scala

@@ -24,7 +24,7 @@ import utils._
 import xiangshan.cache.mmu._
 import xiangshan.frontend._
 import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle}
-
+import huancun.{PreferCacheKey}
 
 
 abstract class IPrefetchBundle(implicit p: Parameters) extends ICacheBundle
@@ -98,11 +98,13 @@ class IPrefetchPipe(implicit p: Parameters) extends  IPrefetchModule
   val p1_vaddr   =  RegEnable(next = p0_vaddr,    enable=p0_fire)
 
   //tlb resp
-  val tlb_resp_valid = RegNext(p0_fire)
+  val tlb_resp_valid = RegInit(false.B)
+  when(p0_fire) {tlb_resp_valid := true.B} 
+  .elsewhen(tlb_resp_valid && (p1_fire || p1_discard)) {tlb_resp_valid := false.B}
 
-  val tlb_resp_paddr = ResultHoldBypass(valid = tlb_resp_valid, data = fromITLB.bits.paddr)
-  val tlb_resp_pf    = ResultHoldBypass(valid = tlb_resp_valid, data = fromITLB.bits.excp.pf.instr && tlb_resp_valid)
-  val tlb_resp_af    = ResultHoldBypass(valid = tlb_resp_valid, data = fromITLB.bits.excp.af.instr && tlb_resp_valid)
+  val tlb_resp_paddr = ResultHoldBypass(valid = RegNext(p0_fire), data = fromITLB.bits.paddr)
+  val tlb_resp_pf    = ResultHoldBypass(valid = RegNext(p0_fire), data = fromITLB.bits.excp.pf.instr && tlb_resp_valid)
+  val tlb_resp_af    = ResultHoldBypass(valid = RegNext(p0_fire), data = fromITLB.bits.excp.af.instr && tlb_resp_valid)
 
   val p1_exception  = VecInit(Seq(tlb_resp_pf, tlb_resp_af))
   val p1_has_except =  p1_exception.reduce(_ || _)
@@ -150,7 +152,7 @@ class IPrefetchPipe(implicit p: Parameters) extends  IPrefetchModule
   /** Prefetch Stage 2: filtered req PIQ enqueue */
   val p3_valid =  generatePipeControl(lastFire = p2_fire, thisFire = p3_fire, thisFlush = false.B, lastFlush = false.B)
 
-  val p3_paddr = RegEnable(next = tlb_resp_paddr,  enable = p1_fire)
+  val p3_paddr = RegEnable(next = tlb_resp_paddr,  enable = p2_fire)
 
   toMissUnit.enqReq.valid             := p3_valid
   toMissUnit.enqReq.bits.paddr        := p3_paddr
@@ -215,6 +217,7 @@ class IPrefetchEntry(edge: TLEdgeOut, id: Int)(implicit p: Parameters) extends I
     param = TLHints.PREFETCH_READ
   )._2
   io.mem_hint.bits := hint
+  io.mem_hint.bits.user.lift(PreferCacheKey).foreach(_ := true.B)
 
 
   XSPerfAccumulate(